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Thu, 12 Nov 2020 07:41:20 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 90FD3A405C for ; Thu, 12 Nov 2020 07:41:20 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5E186A4064 for ; Thu, 12 Nov 2020 07:41:20 +0000 (GMT) Received: from bart.lotus.com (unknown [9.171.63.148]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP for ; Thu, 12 Nov 2020 07:41:20 +0000 (GMT) To: gcc-patches@gcc.gnu.org Subject: [Committed 1/2] IBM Z: Rename mode attr tointvec to TOINTVEC Date: Thu, 12 Nov 2020 08:41:19 +0100 Message-Id: <20201112074120.9546-1-krebbel@linux.ibm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-11-12_02:2020-11-10, 2020-11-12 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 mlxscore=0 suspectscore=1 adultscore=0 mlxlogscore=999 spamscore=0 clxscore=1015 phishscore=0 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2011120045 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andreas Krebbel via Gcc-patches From: Andreas Krebbel Reply-To: Andreas Krebbel Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Just a preparation to add a lower-case tointvec. Bootstrapped and regression tested on s390x. gcc/ChangeLog: * config/s390/vector.md: Rename tointvec to TOINTVEC. * config/s390/vx-builtins.md: Likewise. --- gcc/config/s390/vector.md | 142 ++++++++++++++++----------------- gcc/config/s390/vx-builtins.md | 50 ++++++------ 2 files changed, 96 insertions(+), 96 deletions(-) diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index 31d323930b2..58b8999f2db 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -137,7 +137,7 @@ (define_mode_attr w [(V1QI "") (V2QI "") (V4QI "") (V8QI "") (V16QI "") ; Resulting mode of a vector comparison. For floating point modes an ; integer vector mode with the same element size is picked. -(define_mode_attr tointvec [(V1QI "V1QI") (V2QI "V2QI") (V4QI "V4QI") (V8QI "V8QI") (V16QI "V16QI") +(define_mode_attr TOINTVEC [(V1QI "V1QI") (V2QI "V2QI") (V4QI "V4QI") (V8QI "V8QI") (V16QI "V16QI") (V1HI "V1HI") (V2HI "V2HI") (V4HI "V4HI") (V8HI "V8HI") (V1SI "V1SI") (V2SI "V2SI") (V4SI "V4SI") (V1DI "V1DI") (V2DI "V2DI") @@ -697,12 +697,12 @@ (define_expand "vcondu" (define_expand "vcond_mask_" [(set (match_operand:V 0 "register_operand" "") (if_then_else:V - (eq (match_operand: 3 "register_operand" "") + (eq (match_operand: 3 "register_operand" "") (match_dup 4)) (match_operand:V 2 "register_operand" "") (match_operand:V 1 "register_operand" "")))] "TARGET_VX" - "operands[4] = CONST0_RTX (mode);") + "operands[4] = CONST0_RTX (mode);") ; We only have HW support for byte vectors. The middle-end is @@ -1586,8 +1586,8 @@ (define_insn "*vec_cmp_nocc" ; vfcesb, vfcedb, wfcexb: non-signaling "==" comparison (a == b) (define_insn "*vec_cmpeq_quiet_nocc" - [(set (match_operand: 0 "register_operand" "=v") - (eq: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (eq: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v")))] "TARGET_VX" "fceb\t%v0,%v1,%v2" @@ -1595,45 +1595,45 @@ (define_insn "*vec_cmpeq_quiet_nocc" ; vfchsb, vfchdb, wfchxb: non-signaling > comparison (!(b u>= a)) (define_insn "vec_cmpgt_quiet_nocc" - [(set (match_operand: 0 "register_operand" "=v") - (not: - (unge: (match_operand:VFT 2 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unge: (match_operand:VFT 2 "register_operand" "v") (match_operand:VFT 1 "register_operand" "v"))))] "TARGET_VX" "fchb\t%v0,%v1,%v2" [(set_attr "op_type" "VRR")]) (define_expand "vec_cmplt_quiet_nocc" - [(set (match_operand: 0 "register_operand" "=v") - (not: - (unge: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unge: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v"))))] "TARGET_VX") ; vfchesb, vfchedb, wfchexb: non-signaling >= comparison (!(a u< b)) (define_insn "vec_cmpge_quiet_nocc" - [(set (match_operand: 0 "register_operand" "=v") - (not: - (unlt: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unlt: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v"))))] "TARGET_VX" "fcheb\t%v0,%v1,%v2" [(set_attr "op_type" "VRR")]) (define_expand "vec_cmple_quiet_nocc" - [(set (match_operand: 0 "register_operand" "=v") - (not: - (unlt: (match_operand:VFT 2 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unlt: (match_operand:VFT 2 "register_operand" "v") (match_operand:VFT 1 "register_operand" "v"))))] "TARGET_VX") ; vfkesb, vfkedb, wfkexb: signaling == comparison ((a >= b) & (b >= a)) (define_insn "*vec_cmpeq_signaling_nocc" - [(set (match_operand: 0 "register_operand" "=v") - (and: - (ge: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (and: + (ge: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v")) - (ge: (match_dup 2) + (ge: (match_dup 2) (match_dup 1))))] "TARGET_VXE" "fkeb\t%v0,%v1,%v2" @@ -1641,16 +1641,16 @@ (define_insn "*vec_cmpeq_signaling_nocc" ; vfkhsb, vfkhdb, wfkhxb: signaling > comparison (a > b) (define_insn "*vec_cmpgt_signaling_nocc" - [(set (match_operand: 0 "register_operand" "=v") - (gt: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (gt: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v")))] "TARGET_VXE" "fkhb\t%v0,%v1,%v2" [(set_attr "op_type" "VRR")]) (define_insn "*vec_cmpgt_signaling_finite_nocc" - [(set (match_operand: 0 "register_operand" "=v") - (gt: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (gt: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v")))] "TARGET_NONSIGNALING_VECTOR_COMPARE_OK" "fchb\t%v0,%v1,%v2" @@ -1658,16 +1658,16 @@ (define_insn "*vec_cmpgt_signaling_finite_nocc" ; vfkhesb, vfkhedb, wfkhexb: signaling >= comparison (a >= b) (define_insn "*vec_cmpge_signaling_nocc" - [(set (match_operand: 0 "register_operand" "=v") - (ge: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (ge: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v")))] "TARGET_VXE" "fkheb\t%v0,%v1,%v2" [(set_attr "op_type" "VRR")]) (define_insn "*vec_cmpge_signaling_finite_nocc" - [(set (match_operand: 0 "register_operand" "=v") - (ge: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (ge: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v")))] "TARGET_NONSIGNALING_VECTOR_COMPARE_OK" "fcheb\t%v0,%v1,%v2" @@ -1679,84 +1679,84 @@ (define_insn "*vec_cmpge_signaling_finite_nocc" ; UNGT a u> b -> !!(b u< a) (define_expand "vec_cmpungt" - [(set (match_operand: 0 "register_operand" "=v") - (not: - (unlt: (match_operand:VFT 2 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unlt: (match_operand:VFT 2 "register_operand" "v") (match_operand:VFT 1 "register_operand" "v")))) (set (match_dup 0) - (not: (match_dup 0)))] + (not: (match_dup 0)))] "TARGET_VX") ; UNGE a u>= b -> !!(a u>= b) (define_expand "vec_cmpunge" - [(set (match_operand: 0 "register_operand" "=v") - (not: - (unge: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unge: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v")))) (set (match_dup 0) - (not: (match_dup 0)))] + (not: (match_dup 0)))] "TARGET_VX") ; UNEQ a u== b -> !(!(a u>= b) | !(b u>= a)) (define_expand "vec_cmpuneq" - [(set (match_operand: 0 "register_operand" "=v") - (not: - (unge: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unge: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v")))) (set (match_dup 3) - (not: - (unge: (match_dup 2) + (not: + (unge: (match_dup 2) (match_dup 1)))) (set (match_dup 0) - (ior: (match_dup 0) + (ior: (match_dup 0) (match_dup 3))) (set (match_dup 0) - (not: (match_dup 0)))] + (not: (match_dup 0)))] "TARGET_VX" { - operands[3] = gen_reg_rtx (mode); + operands[3] = gen_reg_rtx (mode); }) ; LTGT a <> b -> a > b | b > a (define_expand "vec_cmpltgt" - [(set (match_operand: 0 "register_operand" "=v") - (gt: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (gt: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v"))) - (set (match_dup 3) (gt: (match_dup 2) (match_dup 1))) - (set (match_dup 0) (ior: (match_dup 0) (match_dup 3)))] + (set (match_dup 3) (gt: (match_dup 2) (match_dup 1))) + (set (match_dup 0) (ior: (match_dup 0) (match_dup 3)))] "TARGET_VXE" { - operands[3] = gen_reg_rtx (mode); + operands[3] = gen_reg_rtx (mode); }) ; ORDERED (a, b): !(a u< b) | !(a u>= b) (define_expand "vec_cmpordered" - [(set (match_operand: 0 "register_operand" "=v") - (not: - (unlt: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unlt: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v")))) (set (match_dup 3) - (not: - (unge: (match_dup 1) + (not: + (unge: (match_dup 1) (match_dup 2)))) (set (match_dup 0) - (ior: (match_dup 0) + (ior: (match_dup 0) (match_dup 3)))] "TARGET_VX" { - operands[3] = gen_reg_rtx (mode); + operands[3] = gen_reg_rtx (mode); }) ; UNORDERED (a, b): !ORDERED (a, b) (define_expand "vec_cmpunordered" - [(match_operand: 0 "register_operand" "=v") + [(match_operand: 0 "register_operand" "=v") (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v")] "TARGET_VX" { emit_insn (gen_vec_cmpordered (operands[0], operands[1], operands[2])); emit_insn (gen_rtx_SET (operands[0], - gen_rtx_NOT (mode, operands[0]))); + gen_rtx_NOT (mode, operands[0]))); DONE; }) @@ -1835,7 +1835,7 @@ (define_insn "vec_vfenes" (define_split [(set (match_operand:V 0 "register_operand" "") (if_then_else:V - (eq (match_operand: 3 "register_operand" "") + (eq (match_operand: 3 "register_operand" "") (match_operand:V 4 "const0_operand" "")) (match_operand:V 1 "const0_operand" "") (match_operand:V 2 "all_ones_operand" "")))] @@ -1849,7 +1849,7 @@ (define_split (define_split [(set (match_operand:V 0 "register_operand" "") (if_then_else:V - (eq (match_operand: 3 "register_operand" "") + (eq (match_operand: 3 "register_operand" "") (match_operand:V 4 "const0_operand" "")) (match_operand:V 1 "all_ones_operand" "") (match_operand:V 2 "const0_operand" "")))] @@ -1863,7 +1863,7 @@ (define_split (define_split [(set (match_operand:V 0 "register_operand" "") (if_then_else:V - (ne (match_operand: 3 "register_operand" "") + (ne (match_operand: 3 "register_operand" "") (match_operand:V 4 "const0_operand" "")) (match_operand:V 1 "all_ones_operand" "") (match_operand:V 2 "const0_operand" "")))] @@ -1877,7 +1877,7 @@ (define_split (define_split [(set (match_operand:V 0 "register_operand" "") (if_then_else:V - (ne (match_operand: 3 "register_operand" "") + (ne (match_operand: 3 "register_operand" "") (match_operand:V 4 "const0_operand" "")) (match_operand:V 1 "const0_operand" "") (match_operand:V 2 "all_ones_operand" "")))] @@ -1891,8 +1891,8 @@ (define_split (define_insn "*vec_sel0" [(set (match_operand:V 0 "register_operand" "=v") (if_then_else:V - (eq (match_operand: 3 "register_operand" "v") - (match_operand: 4 "const0_operand" "")) + (eq (match_operand: 3 "register_operand" "v") + (match_operand: 4 "const0_operand" "")) (match_operand:V 1 "register_operand" "v") (match_operand:V 2 "register_operand" "v")))] "TARGET_VX" @@ -1903,8 +1903,8 @@ (define_insn "*vec_sel0" (define_insn "*vec_sel0" [(set (match_operand:V 0 "register_operand" "=v") (if_then_else:V - (eq (not: (match_operand: 3 "register_operand" "v")) - (match_operand: 4 "const0_operand" "")) + (eq (not: (match_operand: 3 "register_operand" "v")) + (match_operand: 4 "const0_operand" "")) (match_operand:V 1 "register_operand" "v") (match_operand:V 2 "register_operand" "v")))] "TARGET_VX" @@ -1915,8 +1915,8 @@ (define_insn "*vec_sel0" (define_insn "*vec_sel1" [(set (match_operand:V 0 "register_operand" "=v") (if_then_else:V - (eq (match_operand: 3 "register_operand" "v") - (match_operand: 4 "all_ones_operand" "")) + (eq (match_operand: 3 "register_operand" "v") + (match_operand: 4 "all_ones_operand" "")) (match_operand:V 1 "register_operand" "v") (match_operand:V 2 "register_operand" "v")))] "TARGET_VX" @@ -1927,8 +1927,8 @@ (define_insn "*vec_sel1" (define_insn "*vec_sel1" [(set (match_operand:V 0 "register_operand" "=v") (if_then_else:V - (eq (not: (match_operand: 3 "register_operand" "v")) - (match_operand: 4 "all_ones_operand" "")) + (eq (not: (match_operand: 3 "register_operand" "v")) + (match_operand: 4 "all_ones_operand" "")) (match_operand:V 1 "register_operand" "v") (match_operand:V 2 "register_operand" "v")))] "TARGET_VX" diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md index 010db4d1115..2bbed197e73 100644 --- a/gcc/config/s390/vx-builtins.md +++ b/gcc/config/s390/vx-builtins.md @@ -76,7 +76,7 @@ (define_constants (define_insn "vec_gather_element" [(set (match_operand:V_HW_32_64 0 "register_operand" "=v") (unspec:V_HW_32_64 [(match_operand:V_HW_32_64 1 "register_operand" "0") - (match_operand: 2 "register_operand" "v") + (match_operand: 2 "register_operand" "v") (match_operand:BLK 3 "memory_operand" "R") (match_operand:QI 4 "const_mask_operand" "C")] UNSPEC_VEC_GATHER))] @@ -477,7 +477,7 @@ (define_insn "vec_scatter_element_SI" (define_insn "vec_scatter_element_" [(set (mem: (plus: (unspec: - [(match_operand: 1 "register_operand" "v") + [(match_operand: 1 "register_operand" "v") (match_operand:QI 3 "const_mask_operand" "C")] UNSPEC_VEC_EXTRACT) (match_operand:DI 2 "address_operand" "ZQ"))) @@ -492,7 +492,7 @@ (define_insn "vec_scatter_element_" ; multiplexing here in the expander. (define_expand "vec_scatter_element" [(match_operand:V_HW_32_64 0 "register_operand" "") - (match_operand: 1 "register_operand" "") + (match_operand: 1 "register_operand" "") (match_operand 2 "address_operand" "") (match_operand:QI 3 "const_mask_operand" "")] "TARGET_VX" @@ -813,8 +813,8 @@ (define_expand "vec_cmp" }) (define_expand "vec_cmp" - [(set (match_operand: 0 "register_operand" "=v") - (fpcmp: (match_operand:VF_HW 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (fpcmp: (match_operand:VF_HW 1 "register_operand" "v") (match_operand:VF_HW 2 "register_operand" "v")))] "TARGET_VX" { @@ -1050,7 +1050,7 @@ (define_insn "vec_sll" (define_expand "vec_slb" [(set (match_operand:V_HW 0 "register_operand" "") (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "") - (match_operand: 2 "register_operand" "")] + (match_operand: 2 "register_operand" "")] UNSPEC_VEC_SLB))] "TARGET_VX" { @@ -1121,7 +1121,7 @@ (define_insn "vec_sral" (define_insn "vec_srab" [(set (match_operand:V_HW 0 "register_operand" "=v") (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v") - (match_operand: 2 "register_operand" "v")] + (match_operand: 2 "register_operand" "v")] UNSPEC_VEC_SRAB))] "TARGET_VX" "vsrab\t%v0,%v1,%v2" @@ -1146,7 +1146,7 @@ (define_insn "vec_srl" (define_expand "vec_srb" [(set (match_operand:V_HW 0 "register_operand" "") (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "") - (match_operand: 2 "register_operand" "")] + (match_operand: 2 "register_operand" "")] UNSPEC_VEC_SRLB))] "TARGET_VX" { @@ -1229,7 +1229,7 @@ (define_expand "vec_sum4" (define_expand "vec_test_mask_int" [(set (reg:CCRAW CC_REGNUM) (unspec:CCRAW [(match_operand:V_HW 1 "register_operand" "") - (match_operand: 2 "register_operand" "")] + (match_operand: 2 "register_operand" "")] UNSPEC_VEC_TEST_MASK)) (set (match_operand:SI 0 "register_operand" "") (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] @@ -1238,7 +1238,7 @@ (define_expand "vec_test_mask_int" (define_insn "*vec_test_mask" [(set (reg:CCRAW CC_REGNUM) (unspec:CCRAW [(match_operand:V_HW 0 "register_operand" "v") - (match_operand: 1 "register_operand" "v")] + (match_operand: 1 "register_operand" "v")] UNSPEC_VEC_TEST_MASK))] "TARGET_VX" "vtm\t%v0,%v1" @@ -1946,7 +1946,7 @@ (define_insn "*vftci_cconly" (unspec:CCRAW [(match_operand:VF_HW 1 "register_operand" "v") (match_operand:HI 2 "const_int_operand" "J")] UNSPEC_VEC_VFTCICC)) - (clobber (match_scratch: 0 "=v"))] + (clobber (match_scratch: 0 "=v"))] "TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'J', \"J\")" "ftcib\t%v0,%v1,%x2" [(set_attr "op_type" "VRR")]) @@ -1957,7 +1957,7 @@ (define_expand "vftci_intcconly" (unspec:CCRAW [(match_operand:VF_HW 0 "register_operand") (match_operand:HI 1 "const_int_operand")] UNSPEC_VEC_VFTCICC)) - (clobber (scratch:))]) + (clobber (scratch:))]) (set (match_operand:SI 2 "register_operand" "") (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] "TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")") @@ -2083,7 +2083,7 @@ (define_insn "*vec_cmp_cconly" [(set (reg:VFCMP CC_REGNUM) (compare:VFCMP (match_operand:VF_HW 0 "register_operand" "v") (match_operand:VF_HW 1 "register_operand" "v"))) - (clobber (match_scratch: 2 "=v"))] + (clobber (match_scratch: 2 "=v"))] "TARGET_VX" "fcbs\t%v2,%v0,%v1" [(set_attr "op_type" "VRR")]) @@ -2094,8 +2094,8 @@ (define_expand "vec_cmpeq_cc" [(set (reg:CCVEQ CC_REGNUM) (compare:CCVEQ (match_operand:VF_HW 1 "register_operand" "v") (match_operand:VF_HW 2 "register_operand" "v"))) - (set (match_operand: 0 "register_operand" "=v") - (eq: (match_dup 1) (match_dup 2)))]) + (set (match_operand: 0 "register_operand" "=v") + (eq: (match_dup 1) (match_dup 2)))]) (set (match_operand:SI 3 "memory_operand" "") (unspec:SI [(reg:CCVEQ CC_REGNUM)] UNSPEC_CC_TO_INT))] "TARGET_VX") @@ -2105,8 +2105,8 @@ (define_expand "vec_cmph_cc" [(set (reg:CCVFH CC_REGNUM) (compare:CCVFH (match_operand:VF_HW 1 "register_operand" "v") (match_operand:VF_HW 2 "register_operand" "v"))) - (set (match_operand: 0 "register_operand" "=v") - (gt: (match_dup 1) (match_dup 2)))]) + (set (match_operand: 0 "register_operand" "=v") + (gt: (match_dup 1) (match_dup 2)))]) (set (match_operand:SI 3 "memory_operand" "") (unspec:SI [(reg:CCVIH CC_REGNUM)] UNSPEC_CC_TO_INT))] "TARGET_VX") @@ -2116,8 +2116,8 @@ (define_expand "vec_cmphe_cc" [(set (reg:CCVFHE CC_REGNUM) (compare:CCVFHE (match_operand:VF_HW 1 "register_operand" "v") (match_operand:VF_HW 2 "register_operand" "v"))) - (set (match_operand: 0 "register_operand" "=v") - (ge: (match_dup 1) (match_dup 2)))]) + (set (match_operand: 0 "register_operand" "=v") + (ge: (match_dup 1) (match_dup 2)))]) (set (match_operand:SI 3 "memory_operand" "") (unspec:SI [(reg:CCVFHE CC_REGNUM)] UNSPEC_CC_TO_INT))] "TARGET_VX") @@ -2131,8 +2131,8 @@ (define_insn "*vec_cmpeq_cc" [(set (reg:CCVEQ CC_REGNUM) (compare:CCVEQ (match_operand:VF_HW 0 "register_operand" "v") (match_operand:VF_HW 1 "register_operand" "v"))) - (set (match_operand: 2 "register_operand" "=v") - (eq: (match_dup 0) (match_dup 1)))] + (set (match_operand: 2 "register_operand" "=v") + (eq: (match_dup 0) (match_dup 1)))] "TARGET_VX" "fcebs\t%v2,%v0,%v1" [(set_attr "op_type" "VRR")]) @@ -2142,8 +2142,8 @@ (define_insn "*vec_cmph_cc" [(set (reg:CCVFH CC_REGNUM) (compare:CCVFH (match_operand:VF_HW 0 "register_operand" "v") (match_operand:VF_HW 1 "register_operand" "v"))) - (set (match_operand: 2 "register_operand" "=v") - (gt: (match_dup 0) (match_dup 1)))] + (set (match_operand: 2 "register_operand" "=v") + (gt: (match_dup 0) (match_dup 1)))] "TARGET_VX" "fchbs\t%v2,%v0,%v1" [(set_attr "op_type" "VRR")]) @@ -2153,8 +2153,8 @@ (define_insn "*vec_cmphe_cc" [(set (reg:CCVFHE CC_REGNUM) (compare:CCVFHE (match_operand:VF_HW 0 "register_operand" "v") (match_operand:VF_HW 1 "register_operand" "v"))) - (set (match_operand: 2 "register_operand" "=v") - (ge: (match_dup 0) (match_dup 1)))] + (set (match_operand: 2 "register_operand" "=v") + (ge: (match_dup 0) (match_dup 1)))] "TARGET_VX" "fchebs\t%v2,%v0,%v1" [(set_attr "op_type" "VRR")]) From patchwork Thu Nov 12 07:41:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andreas Krebbel X-Patchwork-Id: 1398737 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gcc.gnu.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=oqwEPpvX; dkim-atps=neutral Received: from sourceware.org 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; Thu, 12 Nov 2020 07:41:20 +0000 (GMT) To: gcc-patches@gcc.gnu.org Subject: [Committed 2/2] IBM Z: Fix PR97326: Enable fp compares in vec_cmp Date: Thu, 12 Nov 2020 08:41:20 +0100 Message-Id: <20201112074120.9546-2-krebbel@linux.ibm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201112074120.9546-1-krebbel@linux.ibm.com> References: <20201112074120.9546-1-krebbel@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-11-11_12:2020-11-10, 2020-11-11 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 bulkscore=0 priorityscore=1501 phishscore=0 clxscore=1015 adultscore=0 suspectscore=1 mlxscore=0 lowpriorityscore=0 impostorscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2011120041 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andreas Krebbel via Gcc-patches From: Andreas Krebbel Reply-To: Andreas Krebbel Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Bootstrapped and regression tested on s390x. gcc/ChangeLog: PR target/97326 * config/s390/vector.md: Support vector floating point modes in vec_cmp. --- gcc/config/s390/vector.md | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index 58b8999f2db..fef68644625 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -145,6 +145,16 @@ (define_mode_attr TOINTVEC [(V1QI "V1QI") (V2QI "V2QI") (V4QI "V4QI") (V8QI "V8Q (V1SF "V1SI") (V2SF "V2SI") (V4SF "V4SI") (V1DF "V1DI") (V2DF "V2DI") (V1TF "V1TI") (TF "V1TI")]) + +(define_mode_attr tointvec [(V1QI "v1qi") (V2QI "v2qi") (V4QI "v4qi") (V8QI "v8qi") (V16QI "v16qi") + (V1HI "v1hi") (V2HI "v2hi") (V4HI "v4hi") (V8HI "v8hi") + (V1SI "v1si") (V2SI "v2si") (V4SI "v4si") + (V1DI "v1di") (V2DI "v2di") + (V1TI "v1ti") + (V1SF "v1si") (V2SF "v2si") (V4SF "v4si") + (V1DF "v1di") (V2DF "v2di") + (V1TF "v1ti") (TF "v1ti")]) + (define_mode_attr vw [(SF "w") (V1SF "w") (V2SF "v") (V4SF "v") (DF "w") (V1DF "w") (V2DF "v") (TF "w") (V1TF "w")]) @@ -1546,14 +1556,14 @@ (define_expand "copysign3" }) ;; -;; Integer compares +;; Compares ;; -(define_expand "vec_cmp" - [(set (match_operand:VI_HW 0 "register_operand" "") - (match_operator:VI_HW 1 "" - [(match_operand:VI_HW 2 "register_operand" "") - (match_operand:VI_HW 3 "register_operand" "")]))] +(define_expand "vec_cmp" + [(set (match_operand: 0 "register_operand" "") + (match_operator: 1 "" + [(match_operand:V_HW 2 "register_operand" "") + (match_operand:V_HW 3 "register_operand" "")]))] "TARGET_VX" { s390_expand_vec_compare (operands[0], GET_CODE(operands[1]), operands[2], operands[3]);