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[2.80.104.46]) by smtp.gmail.com with ESMTPSA id s188sm3115178wmf.45.2020.11.11.08.18.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2020 08:18:04 -0800 (PST) From: cupertinomiranda@gmail.com To: qemu-devel@nongnu.org Subject: [PATCH 01/15] arc: Add initial core cpu files Date: Wed, 11 Nov 2020 16:17:44 +0000 Message-Id: <20201111161758.9636-2-cupertinomiranda@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201111161758.9636-1-cupertinomiranda@gmail.com> References: <20201111161758.9636-1-cupertinomiranda@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201111_111807_480004_E30D4D39 X-CRM114-Status: GOOD ( 20.61 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:441 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [cupertinomiranda[at]gmail.com] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Claudiu Zissulescu , Cupertino Miranda , Shahab Vahedi , Shahab Vahedi , Cupertino Miranda , linux-snps-arc@lists.infradead.org, Claudiu Zissulescu Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Cupertino Miranda Signed-off-by: Cupertino Miranda --- target/arc/arc-common.h | 54 ++++ target/arc/cpu-param.h | 32 +++ target/arc/cpu-qom.h | 52 ++++ target/arc/cpu.c | 467 +++++++++++++++++++++++++++++++++++ target/arc/cpu.h | 531 ++++++++++++++++++++++++++++++++++++++++ target/arc/internals.h | 38 +++ target/arc/meson.build | 20 ++ 7 files changed, 1194 insertions(+) create mode 100644 target/arc/arc-common.h create mode 100644 target/arc/cpu-param.h create mode 100644 target/arc/cpu-qom.h create mode 100644 target/arc/cpu.c create mode 100644 target/arc/cpu.h create mode 100644 target/arc/internals.h create mode 100644 target/arc/meson.build diff --git a/target/arc/arc-common.h b/target/arc/arc-common.h new file mode 100644 index 0000000000..d931944149 --- /dev/null +++ b/target/arc/arc-common.h @@ -0,0 +1,54 @@ +/* + * Common header file to be used by cpu and disassembler. + * Copyright (C) 2017 Free Software Foundation, Inc. + * + * You should have received a copy of the GNU General Public License + * along with GAS or GDB; see the file COPYING3. If not, write to + * the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef ARC_COMMON_H +#define ARC_COMMON_H + + +/* CPU combi. */ +#define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \ + | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS) +#define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM) +#define ARC_OPCODE_ARCV1 (ARC_OPCODE_ARC700 | ARC_OPCODE_ARC600) +#define ARC_OPCODE_ARCV2 (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS) +#define ARC_OPCODE_ARCMPY6E (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCV2) + + +enum arc_cpu_family { + ARC_OPCODE_NONE = 0, + ARC_OPCODE_DEFAULT = 1 << 0, + ARC_OPCODE_ARC600 = 1 << 1, + ARC_OPCODE_ARC700 = 1 << 2, + ARC_OPCODE_ARCv2EM = 1 << 3, + ARC_OPCODE_ARCv2HS = 1 << 4 +}; + +typedef struct { + uint32_t value; + uint32_t type; +} operand_t; + +typedef struct { + uint32_t class; + uint32_t limm; + uint8_t len; + bool limm_p; + operand_t operands[3]; + uint8_t n_ops; + uint8_t cc; + uint8_t aa; + uint8_t zz; + bool d; + bool f; + bool di; + bool x; +} insn_t; + +#endif diff --git a/target/arc/cpu-param.h b/target/arc/cpu-param.h new file mode 100644 index 0000000000..512f4c8b75 --- /dev/null +++ b/target/arc/cpu-param.h @@ -0,0 +1,32 @@ +/* + * ARC cpu parameters for qemu. + * + * Copyright (c) 2020 Synopsys Inc. + * Contributed by Shahab Vahedi + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef ARC_CPU_PARAM_H +#define ARC_CPU_PARAM_H 1 + +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 13 +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define NB_MMU_MODES 2 + +#endif + +/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ +/* vim: set ts=4 sw=4 et: */ diff --git a/target/arc/cpu-qom.h b/target/arc/cpu-qom.h new file mode 100644 index 0000000000..ee60db158d --- /dev/null +++ b/target/arc/cpu-qom.h @@ -0,0 +1,52 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synopsys Inc. + * Contributed by Cupertino Miranda + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef QEMU_ARC_CPU_QOM_H +#define QEMU_ARC_CPU_QOM_H + +#include "hw/core/cpu.h" + +#define TYPE_ARC_CPU "arc-cpu" + +#define ARC_CPU_CLASS(klass) \ + OBJECT_CLASS_CHECK(ARCCPUClass, (klass), TYPE_ARC_CPU) +#define ARC_CPU(obj) \ + OBJECT_CHECK(ARCCPU, (obj), TYPE_ARC_CPU) +#define ARC_CPU_GET_CLASS(obj) \ + OBJECT_GET_CLASS(ARCCPUClass, (obj), TYPE_ARC_CPU) + +/* + * ARCCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_reset: The parent class' reset handler. + * + * A ARC CPU model. + */ +typedef struct ARCCPUClass { + /*< private >*/ + CPUClass parent_class; + /*< public >*/ + + DeviceRealize parent_realize; + DeviceReset parent_reset; +} ARCCPUClass; + +typedef struct ARCCPU ARCCPU; + +#endif diff --git a/target/arc/cpu.c b/target/arc/cpu.c new file mode 100644 index 0000000000..2baa19486d --- /dev/null +++ b/target/arc/cpu.c @@ -0,0 +1,467 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synopsys Inc. + * Contributed by Cupertino Miranda + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "migration/vmstate.h" +#include "exec/log.h" +#include "mmu.h" +#include "mpu.h" +#include "hw/qdev-properties.h" +#include "irq.h" +#include "hw/arc/cpudevs.h" +#include "timer.h" +#include "internals.h" + +static const VMStateDescription vms_arc_cpu = { + .name = "cpu", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_END_OF_LIST() + } +}; + +static Property arc_cpu_properties[] = { + DEFINE_PROP_UINT32("address-size", ARCCPU, cfg.addr_size, 32), + DEFINE_PROP_BOOL("aps", ARCCPU, cfg.aps_feature, false), + DEFINE_PROP_BOOL("byte-order", ARCCPU, cfg.byte_order, false), + DEFINE_PROP_BOOL("bitscan", ARCCPU, cfg.bitscan_option, true), + DEFINE_PROP_UINT32("br_bc-entries", ARCCPU, cfg.br_bc_entries, -1), + DEFINE_PROP_UINT32("br_pt-entries", ARCCPU, cfg.br_pt_entries, -1), + DEFINE_PROP_BOOL("full-tag", ARCCPU, cfg.br_bc_full_tag, false), + DEFINE_PROP_UINT8("rs-entries", ARCCPU, cfg.br_rs_entries, -1), + DEFINE_PROP_UINT32("tag-size", ARCCPU, cfg.br_bc_tag_size, -1), + DEFINE_PROP_UINT8("tosq-entries", ARCCPU, cfg.br_tosq_entries, -1), + DEFINE_PROP_UINT8("fb-entries", ARCCPU, cfg.br_fb_entries, -1), + DEFINE_PROP_BOOL("code-density", ARCCPU, cfg.code_density, true), + DEFINE_PROP_BOOL("code-protect", ARCCPU, cfg.code_protect, false), + DEFINE_PROP_UINT8("dcc-memcyc", ARCCPU, cfg.dccm_mem_cycles, -1), + DEFINE_PROP_BOOL("ddcm-posedge", ARCCPU, cfg.dccm_posedge, false), + DEFINE_PROP_UINT8("dcc-mem-banks", ARCCPU, cfg.dccm_mem_bancks, -1), + DEFINE_PROP_UINT8("mem-cycles", ARCCPU, cfg.dc_mem_cycles, -1), + DEFINE_PROP_BOOL("dc-posedge", ARCCPU, cfg.dc_posedge, false), + DEFINE_PROP_BOOL("unaligned", ARCCPU, cfg.dmp_unaligned, true), + DEFINE_PROP_BOOL("ecc-excp", ARCCPU, cfg.ecc_exception, false), + DEFINE_PROP_UINT32("ext-irq", ARCCPU, cfg.external_interrupts, 128), + DEFINE_PROP_UINT8("ecc-option", ARCCPU, cfg.ecc_option, -1), + DEFINE_PROP_BOOL("firq", ARCCPU, cfg.firq_option, true), + DEFINE_PROP_BOOL("fpu-dp", ARCCPU, cfg.fpu_dp_option, false), + DEFINE_PROP_BOOL("fpu-fma", ARCCPU, cfg.fpu_fma_option, false), + DEFINE_PROP_BOOL("fpu-div", ARCCPU, cfg.fpu_div_option, false), + DEFINE_PROP_BOOL("actionpoints", ARCCPU, cfg.has_actionpoints, false), + DEFINE_PROP_BOOL("fpu", ARCCPU, cfg.has_fpu, false), + DEFINE_PROP_BOOL("has-irq", ARCCPU, cfg.has_interrupts, true), + DEFINE_PROP_BOOL("has-mmu", ARCCPU, cfg.has_mmu, true), + DEFINE_PROP_BOOL("has-mpu", ARCCPU, cfg.has_mpu, true), + DEFINE_PROP_BOOL("timer0", ARCCPU, cfg.has_timer_0, true), + DEFINE_PROP_BOOL("timer1", ARCCPU, cfg.has_timer_1, true), + DEFINE_PROP_BOOL("has-pct", ARCCPU, cfg.has_pct, false), + DEFINE_PROP_BOOL("has-rtt", ARCCPU, cfg.has_rtt, false), + DEFINE_PROP_BOOL("has-smart", ARCCPU, cfg.has_smart, false), + DEFINE_PROP_UINT32("intv-base", ARCCPU, cfg.intvbase_preset, 0x0), + DEFINE_PROP_UINT32("lpc-size", ARCCPU, cfg.lpc_size, 32), + DEFINE_PROP_UINT8("mpu-numreg", ARCCPU, cfg.mpu_num_regions, 0), + DEFINE_PROP_UINT8("mpy-option", ARCCPU, cfg.mpy_option, 2), + DEFINE_PROP_UINT32("mmu-pagesize0", ARCCPU, cfg.mmu_page_size_sel0, -1), + DEFINE_PROP_UINT32("mmu-pagesize1", ARCCPU, cfg.mmu_page_size_sel1, -1), + DEFINE_PROP_UINT32("mmu-pae", ARCCPU, cfg.mmu_pae_enabled, -1), + DEFINE_PROP_UINT32("ntlb-numentries", ARCCPU, cfg.ntlb_num_entries, -1), + DEFINE_PROP_UINT32("num-actionpoints", ARCCPU, cfg.num_actionpoints, -1), + DEFINE_PROP_UINT32("num-irq", ARCCPU, cfg.number_of_interrupts, 240), + DEFINE_PROP_UINT32("num-irqlevels", ARCCPU, cfg.number_of_levels, 15), + DEFINE_PROP_UINT32("pct-counters", ARCCPU, cfg.pct_counters, -1), + DEFINE_PROP_UINT32("pct-irq", ARCCPU, cfg.pct_interrupt, -1), + DEFINE_PROP_UINT32("pc-size", ARCCPU, cfg.pc_size, 32), + DEFINE_PROP_UINT32("num-regs", ARCCPU, cfg.rgf_num_regs, 32), + DEFINE_PROP_UINT32("banked-regs", ARCCPU, cfg.rgf_banked_regs, -1), + DEFINE_PROP_UINT32("num-banks", ARCCPU, cfg.rgf_num_banks, 0), + DEFINE_PROP_BOOL("rtc-opt", ARCCPU, cfg.rtc_option, false), + DEFINE_PROP_UINT32("rtt-featurelevel", ARCCPU, cfg.rtt_feature_level, -1), + DEFINE_PROP_BOOL("stack-check", ARCCPU, cfg.stack_checking, false), + DEFINE_PROP_BOOL("swap-option", ARCCPU, cfg.swap_option, true), + DEFINE_PROP_UINT32("smrt-stackentries", ARCCPU, cfg.smar_stack_entries, -1), + DEFINE_PROP_UINT32("smrt-impl", ARCCPU, cfg.smart_implementation, -1), + DEFINE_PROP_UINT32("stlb", ARCCPU, cfg.stlb_num_entries, -1), + DEFINE_PROP_UINT32("slc-size", ARCCPU, cfg.slc_size, -1), + DEFINE_PROP_UINT32("slc-linesize", ARCCPU, cfg.slc_line_size, -1), + DEFINE_PROP_UINT32("slc-ways", ARCCPU, cfg.slc_ways, -1), + DEFINE_PROP_UINT32("slc-tagbanks", ARCCPU, cfg.slc_tag_banks, -1), + DEFINE_PROP_UINT32("slc-tram", ARCCPU, cfg.slc_tram_delay, -1), + DEFINE_PROP_UINT32("slc-dbank", ARCCPU, cfg.slc_dbank_width, -1), + DEFINE_PROP_UINT32("slc-data", ARCCPU, cfg.slc_data_banks, -1), + DEFINE_PROP_UINT32("slc-delay", ARCCPU, cfg.slc_dram_delay, -1), + DEFINE_PROP_BOOL("slc-memwidth", ARCCPU, cfg.slc_mem_bus_width, false), + DEFINE_PROP_UINT32("slc-ecc", ARCCPU, cfg.slc_ecc_option, -1), + DEFINE_PROP_BOOL("slc-datahalf", ARCCPU, cfg.slc_data_halfcycle_steal, false), + DEFINE_PROP_BOOL("slc-dataadd", ARCCPU, cfg.slc_data_add_pre_pipeline, false), + DEFINE_PROP_BOOL("uaux", ARCCPU, cfg.uaux_option, false), + DEFINE_PROP_UINT32("freq_hz", ARCCPU, cfg.freq_hz, 4600000), + DEFINE_PROP_END_OF_LIST(), +}; + +static void arc_cpu_set_pc(CPUState *cs, vaddr value) +{ + ARCCPU *cpu = ARC_CPU(cs); + + CPU_PCL(&cpu->env) = value & 0xfffffffc; + cpu->env.pc = value; +} + +static bool arc_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & CPU_INTERRUPT_HARD; +} + +static void arc_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +{ + ARCCPU *cpu = ARC_CPU(cs); + CPUARCState *env = &cpu->env; + + CPU_PCL(&cpu->env) = tb->pc & 0xfffffffc; + env->pc = tb->pc; +} + +static void arc_cpu_reset(DeviceState *dev) +{ + CPUState *s = CPU(dev); + ARCCPU *cpu = ARC_CPU(s); + ARCCPUClass *arcc = ARC_CPU_GET_CLASS(cpu); + CPUARCState *env = &cpu->env; + + if (qemu_loglevel_mask(CPU_LOG_RESET)) { + qemu_log("CPU Reset (CPU)\n"); + log_cpu_state(s, 0); + } + + /* Initialize mmu/reset it. */ + arc_mmu_init(&env->mmu); + + arc_mpu_init(cpu); + + arc_resetTIMER(cpu); + arc_resetIRQ(cpu); + + arcc->parent_reset(dev); + + memset(env->r, 0, sizeof(env->r)); + env->lock_lf_var = 0; + + env->stat.is_delay_slot_instruction = 0; + /* + * kernel expects MPY support to check for presence of + * extension core regs r58/r59. + * + * VERSION32x32=0x06: ARCv2 32x32 Multiply + * DSP=0x1: MPY_OPTION 7 + */ + env->mpy_build = 0x00001006; +} + +static void arc_cpu_disas_set_info(CPUState *cs, disassemble_info *info) +{ + ARCCPU *cpu = ARC_CPU(cs); + CPUARCState *env = &cpu->env; + + switch (env->family) { + case ARC_OPCODE_ARC700: + info->mach = bfd_mach_arc_arc700; + break; + case ARC_OPCODE_ARC600: + info->mach = bfd_mach_arc_arc600; + break; + case ARC_OPCODE_ARCv2EM: + info->mach = bfd_mach_arc_arcv2em; + break; + case ARC_OPCODE_ARCv2HS: + info->mach = bfd_mach_arc_arcv2hs; + break; + default: + info->mach = bfd_mach_arc_arcv2; + break; + } + + info->print_insn = print_insn_arc; + info->endian = BFD_ENDIAN_LITTLE; +} + + +static void arc_cpu_realizefn(DeviceState *dev, Error **errp) +{ + CPUState *cs = CPU(dev); + ARCCPU *cpu = ARC_CPU(dev); + ARCCPUClass *arcc = ARC_CPU_GET_CLASS(dev); + Error *local_err = NULL; + CPUARCState *env = &cpu->env; + + cpu_exec_realizefn(cs, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + + arc_cpu_register_gdb_regs_for_features(cpu); + + qemu_init_vcpu(cs); + + /* + * Initialize build registers depending on the simulation + * parameters. + */ + env->freq_hz = cpu->cfg.freq_hz; + + env->isa_config = 0x02; + switch (cpu->cfg.pc_size) { + case 16: + break; + case 20: + env->isa_config |= 1 << 8; + break; + case 24: + env->isa_config |= 2 << 8; + break; + case 28: + env->isa_config |= 3 << 8; + break; + default: + env->isa_config |= 4 << 8; + break; + } + + switch (cpu->cfg.lpc_size) { + case 0: + break; + case 8: + env->isa_config |= 1 << 12; + break; + case 12: + env->isa_config |= 2 << 12; + break; + case 16: + env->isa_config |= 3 << 12; + break; + case 20: + env->isa_config |= 4 << 12; + break; + case 24: + env->isa_config |= 5 << 12; + break; + case 28: + env->isa_config |= 6 << 12; + break; + default: + env->isa_config |= 7 << 12; + break; + } + + switch (cpu->cfg.addr_size) { + case 16: + break; + case 20: + env->isa_config |= 1 << 16; + break; + case 24: + env->isa_config |= 2 << 16; + break; + case 28: + env->isa_config |= 3 << 16; + break; + default: + env->isa_config |= 4 << 16; + break; + } + + env->isa_config |= (cpu->cfg.byte_order ? BIT(20) : 0) | BIT(21) + | (cpu->cfg.dmp_unaligned ? BIT(22) : 0) | BIT(23) + | (cpu->cfg.code_density ? (2 << 24) : 0) | BIT(28); + + arc_initializeTIMER(cpu); + arc_initializeIRQ(cpu); + + cpu_reset(cs); + + arcc->parent_realize(dev, errp); +} + +static void arc_cpu_initfn(Object *obj) +{ + ARCCPU *cpu = ARC_CPU(obj); + + /* Initialize aux-regs. */ + arc_aux_regs_init(); + + cpu_set_cpustate_pointers(cpu); +} + +static ObjectClass *arc_cpu_class_by_name(const char *cpu_model) +{ + ObjectClass *oc; + char *typename; + char **cpuname; + + if (!cpu_model) { + return NULL; + } + + cpuname = g_strsplit(cpu_model, ",", 1); + typename = g_strdup_printf("%s-" TYPE_ARC_CPU, cpuname[0]); + oc = object_class_by_name(typename); + + g_strfreev(cpuname); + g_free(typename); + + if (!oc + || !object_class_dynamic_cast(oc, TYPE_ARC_CPU) + || object_class_is_abstract(oc)) { + return NULL; + } + + return oc; +} + +static gchar *arc_gdb_arch_name(CPUState *cs) +{ + return g_strdup("arc:ARCv2"); +} + +static void arc_cpu_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + CPUClass *cc = CPU_CLASS(oc); + ARCCPUClass *arcc = ARC_CPU_CLASS(oc); + + device_class_set_parent_realize(dc, arc_cpu_realizefn, + &arcc->parent_realize); + + device_class_set_parent_reset(dc, arc_cpu_reset, &arcc->parent_reset); + + cc->class_by_name = arc_cpu_class_by_name; + + cc->has_work = arc_cpu_has_work; + cc->do_interrupt = arc_cpu_do_interrupt; + cc->cpu_exec_interrupt = arc_cpu_exec_interrupt; + cc->dump_state = arc_cpu_dump_state; + cc->set_pc = arc_cpu_set_pc; +#ifndef CONFIG_USER_ONLY + cc->memory_rw_debug = arc_cpu_memory_rw_debug; + cc->get_phys_page_debug = arc_cpu_get_phys_page_debug; + cc->vmsd = &vms_arc_cpu; +#endif + cc->disas_set_info = arc_cpu_disas_set_info; + cc->synchronize_from_tb = arc_cpu_synchronize_from_tb; + cc->gdb_read_register = arc_cpu_gdb_read_register; + cc->gdb_write_register = arc_cpu_gdb_write_register; + + /* Core GDB support */ + cc->gdb_core_xml_file = "arc-v2-core.xml"; + cc->gdb_num_core_regs = GDB_REG_LAST; + cc->gdb_arch_name = arc_gdb_arch_name; + +#ifdef CONFIG_TCG + cc->tcg_initialize = arc_translate_init; + cc->tlb_fill = arc_cpu_tlb_fill; +#endif + device_class_set_props(dc, arc_cpu_properties); +} + +static void arc_any_initfn(Object *obj) +{ + /* Set cpu feature flags */ + ARCCPU *cpu = ARC_CPU(obj); + cpu->env.family = ARC_OPCODE_ARC700; +} + +static void arc600_initfn(Object *obj) +{ + ARCCPU *cpu = ARC_CPU(obj); + cpu->env.family = ARC_OPCODE_ARC600; +} + +static void arc700_initfn(Object *obj) +{ + ARCCPU *cpu = ARC_CPU(obj); + cpu->env.family = ARC_OPCODE_ARC700; +} + +static void arcem_initfn(Object *obj) +{ + ARCCPU *cpu = ARC_CPU(obj); + cpu->env.family = ARC_OPCODE_ARCv2EM; +} + +static void archs_initfn(Object *obj) +{ + ARCCPU *cpu = ARC_CPU(obj); + cpu->env.family = ARC_OPCODE_ARCv2HS; +} + +typedef struct ARCCPUInfo { + const char *name; + void (*initfn)(Object *obj); +} ARCCPUInfo; + +static const ARCCPUInfo arc_cpus[] = { + { .name = "arc600", .initfn = arc600_initfn }, + { .name = "arc700", .initfn = arc700_initfn }, + { .name = "arcem", .initfn = arcem_initfn }, + { .name = "archs", .initfn = archs_initfn }, + { .name = "any", .initfn = arc_any_initfn }, +}; + +static void cpu_register(const ARCCPUInfo *info) +{ + TypeInfo type_info = { + .parent = TYPE_ARC_CPU, + .instance_size = sizeof(ARCCPU), + .instance_init = info->initfn, + .class_size = sizeof(ARCCPUClass), + }; + + type_info.name = g_strdup_printf("%s-" TYPE_ARC_CPU, info->name); + type_register(&type_info); + g_free((void *)type_info.name); +} + +static const TypeInfo arc_cpu_type_info = { + .name = TYPE_ARC_CPU, + .parent = TYPE_CPU, + .instance_size = sizeof(ARCCPU), + .instance_init = arc_cpu_initfn, + .class_size = sizeof(ARCCPUClass), + .class_init = arc_cpu_class_init, + .abstract = true, +}; + +static void arc_cpu_register_types(void) +{ + int i; + type_register_static(&arc_cpu_type_info); + + for (i = 0; i < ARRAY_SIZE(arc_cpus); i++) { + cpu_register(&arc_cpus[i]); + } +} + +type_init(arc_cpu_register_types) + + +/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ +/* vim: set ts=4 sw=4 et: */ diff --git a/target/arc/cpu.h b/target/arc/cpu.h new file mode 100644 index 0000000000..d5408c6fea --- /dev/null +++ b/target/arc/cpu.h @@ -0,0 +1,531 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synopsys Inc. + * Contributed by Cupertino Miranda + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef CPU_ARC_H +#define CPU_ARC_H + +#include "cpu-qom.h" +#include "exec/cpu-defs.h" +#include "fpu/softfloat.h" + +#include "target/arc/arc-common.h" +#include "target/arc/mmu.h" +#include "target/arc/mpu.h" +#include "target/arc/cache.h" + +#define ARC_CPU_TYPE_SUFFIX "-" TYPE_ARC_CPU +#define ARC_CPU_TYPE_NAME(model) model ARC_CPU_TYPE_SUFFIX +#define CPU_RESOLVING_TYPE TYPE_ARC_CPU + +#define MMU_IDX 0 + +#define PHYS_BASE_RAM 0x00000000 +#define VIRT_BASE_RAM 0x00000000 + +enum arc_features { + ARC_FEATURE_ARC5, + ARC_FEATURE_ARC600, + ARC_FEATURE_ARC700, + no_features, +}; + +enum arc_endianess { + ARC_ENDIANNESS_LE = 0, + ARC_ENDIANNESS_BE, +}; + +/* U-Boot - kernel ABI */ +#define ARC_UBOOT_CMDLINE 1 +#define ARC_UBOOT_DTB 2 + +enum gdb_regs { + GDB_REG_0 = 0, + GDB_REG_1, + GDB_REG_2, + GDB_REG_3, + GDB_REG_4, + GDB_REG_5, + GDB_REG_6, + GDB_REG_7, + GDB_REG_8, + GDB_REG_9, + GDB_REG_10, + GDB_REG_11, + GDB_REG_12, + GDB_REG_13, + GDB_REG_14, + GDB_REG_15, + GDB_REG_16, + GDB_REG_17, + GDB_REG_18, + GDB_REG_19, + GDB_REG_20, + GDB_REG_21, + GDB_REG_22, + GDB_REG_23, + GDB_REG_24, + GDB_REG_25, + GDB_REG_26, /* GP */ + GDB_REG_27, /* FP */ + GDB_REG_28, /* SP */ + GDB_REG_29, /* ILINK */ + GDB_REG_30, /* R30 */ + GDB_REG_31, /* BLINK */ + GDB_REG_58, /* little_endian? ACCL : ACCH */ + GDB_REG_59, /* little_endian? ACCH : ACCL */ + GDB_REG_60, /* LP */ + GDB_REG_63, /* Immediate */ + GDB_REG_LAST +}; + +enum gdb_aux_min_regs { + GDB_AUX_MIN_REG_PC = 0, /* program counter */ + GDB_AUX_MIN_REG_LPS, /* loop body start */ + GDB_AUX_MIN_REG_LPE, /* loop body end */ + GDB_AUX_MIN_REG_STATUS, /* status flag */ + GDB_AUX_MIN_REG_LAST +}; + +enum gdb_aux_other_regs { + /* builds */ + GDB_AUX_OTHER_REG_TIMER_BUILD = 0, /* timer build */ + GDB_AUX_OTHER_REG_IRQ_BUILD, /* irq build */ + GDB_AUX_OTHER_REG_MPY_BUILD, /* multiply configuration */ + GDB_AUX_OTHER_REG_VECBASE_BUILD, /* vector base address config */ + GDB_AUX_OTHER_REG_ISA_CONFIG, /* isa config */ + /* timers */ + GDB_AUX_OTHER_REG_TIMER_CNT0, /* timer 0 counter */ + GDB_AUX_OTHER_REG_TIMER_CTRL0, /* timer 0 control */ + GDB_AUX_OTHER_REG_TIMER_LIM0, /* timer 0 limit */ + GDB_AUX_OTHER_REG_TIMER_CNT1, /* timer 1 counter */ + GDB_AUX_OTHER_REG_TIMER_CTRL1, /* timer 1 control */ + GDB_AUX_OTHER_REG_TIMER_LIM1, /* timer 1 limit */ + /* mmu */ + GDB_AUX_OTHER_REG_PID, /* process identity */ + GDB_AUX_OTHER_REG_TLBPD0, /* page descriptor 0 */ + GDB_AUX_OTHER_REG_TLBPD1, /* page descriptor 1 */ + GDB_AUX_OTHER_REG_TLB_INDEX, /* tlb index */ + GDB_AUX_OTHER_REG_TLB_CMD, /* tlb command */ + /* mpu */ + GDB_AUX_OTHER_REG_MPU_BUILD, /* MPU build */ + GDB_AUX_OTHER_REG_MPU_EN, /* MPU enable */ + GDB_AUX_OTHER_REG_MPU_ECR, /* MPU exception cause */ + GDB_AUX_OTHER_REG_MPU_BASE0, /* MPU base 0 */ + GDB_AUX_OTHER_REG_MPU_BASE1, /* MPU base 1 */ + GDB_AUX_OTHER_REG_MPU_BASE2, /* MPU base 2 */ + GDB_AUX_OTHER_REG_MPU_BASE3, /* MPU base 3 */ + GDB_AUX_OTHER_REG_MPU_BASE4, /* MPU base 4 */ + GDB_AUX_OTHER_REG_MPU_BASE5, /* MPU base 5 */ + GDB_AUX_OTHER_REG_MPU_BASE6, /* MPU base 6 */ + GDB_AUX_OTHER_REG_MPU_BASE7, /* MPU base 7 */ + GDB_AUX_OTHER_REG_MPU_BASE8, /* MPU base 8 */ + GDB_AUX_OTHER_REG_MPU_BASE9, /* MPU base 9 */ + GDB_AUX_OTHER_REG_MPU_BASE10, /* MPU base 10 */ + GDB_AUX_OTHER_REG_MPU_BASE11, /* MPU base 11 */ + GDB_AUX_OTHER_REG_MPU_BASE12, /* MPU base 12 */ + GDB_AUX_OTHER_REG_MPU_BASE13, /* MPU base 13 */ + GDB_AUX_OTHER_REG_MPU_BASE14, /* MPU base 14 */ + GDB_AUX_OTHER_REG_MPU_BASE15, /* MPU base 15 */ + GDB_AUX_OTHER_REG_MPU_PERM0, /* MPU permission 0 */ + GDB_AUX_OTHER_REG_MPU_PERM1, /* MPU permission 1 */ + GDB_AUX_OTHER_REG_MPU_PERM2, /* MPU permission 2 */ + GDB_AUX_OTHER_REG_MPU_PERM3, /* MPU permission 3 */ + GDB_AUX_OTHER_REG_MPU_PERM4, /* MPU permission 4 */ + GDB_AUX_OTHER_REG_MPU_PERM5, /* MPU permission 5 */ + GDB_AUX_OTHER_REG_MPU_PERM6, /* MPU permission 6 */ + GDB_AUX_OTHER_REG_MPU_PERM7, /* MPU permission 7 */ + GDB_AUX_OTHER_REG_MPU_PERM8, /* MPU permission 8 */ + GDB_AUX_OTHER_REG_MPU_PERM9, /* MPU permission 9 */ + GDB_AUX_OTHER_REG_MPU_PERM10, /* MPU permission 10 */ + GDB_AUX_OTHER_REG_MPU_PERM11, /* MPU permission 11 */ + GDB_AUX_OTHER_REG_MPU_PERM12, /* MPU permission 12 */ + GDB_AUX_OTHER_REG_MPU_PERM13, /* MPU permission 13 */ + GDB_AUX_OTHER_REG_MPU_PERM14, /* MPU permission 14 */ + GDB_AUX_OTHER_REG_MPU_PERM15, /* MPU permission 15 */ + /* excpetions */ + GDB_AUX_OTHER_REG_ERSTATUS, /* exception return status */ + GDB_AUX_OTHER_REG_ERBTA, /* exception return BTA */ + GDB_AUX_OTHER_REG_ECR, /* exception cause register */ + GDB_AUX_OTHER_REG_ERET, /* exception return address */ + GDB_AUX_OTHER_REG_EFA, /* exception fault address */ + /* irq */ + GDB_AUX_OTHER_REG_ICAUSE, /* interrupt cause */ + GDB_AUX_OTHER_REG_IRQ_CTRL, /* context saving control */ + GDB_AUX_OTHER_REG_IRQ_ACT, /* active */ + GDB_AUX_OTHER_REG_IRQ_PRIO_PEND, /* priority pending */ + GDB_AUX_OTHER_REG_IRQ_HINT, /* hint */ + GDB_AUX_OTHER_REG_IRQ_SELECT, /* select */ + GDB_AUX_OTHER_REG_IRQ_ENABLE, /* enable */ + GDB_AUX_OTHER_REG_IRQ_TRIGGER, /* trigger */ + GDB_AUX_OTHER_REG_IRQ_STATUS, /* status */ + GDB_AUX_OTHER_REG_IRQ_PULSE, /* pulse cancel */ + GDB_AUX_OTHER_REG_IRQ_PENDING, /* pending */ + GDB_AUX_OTHER_REG_IRQ_PRIO, /* priority */ + /* miscellaneous */ + GDB_AUX_OTHER_REG_BTA, /* branch target address */ + + GDB_AUX_OTHER_REG_LAST +}; + +#define CPU_GP(env) ((env)->r[26]) +#define CPU_FP(env) ((env)->r[27]) +#define CPU_SP(env) ((env)->r[28]) +#define CPU_ILINK(env) ((env)->r[29]) +#define CPU_ILINK1(env) ((env)->r[29]) +#define CPU_ILINK2(env) ((env)->r[30]) +#define CPU_BLINK(env) ((env)->r[31]) +#define CPU_LP(env) ((env)->r[60]) +#define CPU_IMM(env) ((env)->r[62]) +#define CPU_PCL(env) ((env)->r[63]) + +enum exception_code_list { + EXCP_NO_EXCEPTION = -1, + EXCP_RESET = 0, + EXCP_MEMORY_ERROR, + EXCP_INST_ERROR, + EXCP_MACHINE_CHECK, + EXCP_TLB_MISS_I, + EXCP_TLB_MISS_D, + EXCP_PROTV, + EXCP_PRIVILEGEV, + EXCP_SWI, + EXCP_TRAP, + EXCP_EXTENSION, + EXCP_DIVZERO, + EXCP_DCERROR, + EXCP_MISALIGNED, + EXCP_IRQ, + EXCP_LPEND_REACHED = 9000, + EXCP_FAKE +}; + +typedef struct status_register { + uint32_t Hf; /* halt */ + uint32_t Ef; /* irq priority treshold. */ + uint32_t AEf; + uint32_t DEf; + uint32_t Uf; + uint32_t Vf; /* overflow */ + uint32_t Cf; /* carry */ + uint32_t Nf; /* negative */ + uint32_t Zf; /* zero */ + uint32_t Lf; + uint32_t DZf; + uint32_t SCf; + uint32_t ESf; + uint32_t RBf; + uint32_t ADf; + uint32_t USf; + uint32_t IEf; + + /* Reserved bits */ + + /* Next instruction is a delayslot instruction */ + uint32_t is_delay_slot_instruction; +} status_t; + +/* ARC processor timer module. */ +typedef struct { + /* + * TODO: This volatile is needed to pass RTC tests. We need to + * verify why. + */ + volatile uint32_t T_Cntrl; + volatile uint32_t T_Limit; + volatile uint64_t last_clk; +} arc_timer_t; + +/* ARC PIC interrupt bancked regs. */ +typedef struct { + uint32_t priority; + uint32_t trigger; + uint32_t pulse_cancel; + uint32_t enable; + uint32_t pending; + uint32_t status; +} arc_irq_t; + +typedef struct CPUARCState { + uint32_t r[64]; + + status_t stat, stat_l1, stat_er; + + struct { + uint32_t S2; + uint32_t S1; + uint32_t CS; + } macmod; + + uint32_t intvec; + + uint32_t eret; + uint32_t erbta; + uint32_t ecr; + uint32_t efa; + uint32_t bta; + uint32_t bta_l1; + uint32_t bta_l2; + + uint32_t pc; /* program counter */ + uint32_t lps; /* loops start */ + uint32_t lpe; /* loops end */ + + uint32_t npc; /* required for LP - zero overhead loops. */ + + uint32_t lock_lf_var; + + struct { + uint32_t LD; /* load pending bit */ + uint32_t SH; /* self halt */ + uint32_t BH; /* breakpoint halt */ + uint32_t UB; /* user mode break enabled */ + uint32_t ZZ; /* sleep mode */ + uint32_t RA; /* reset applied */ + uint32_t IS; /* single instruction step */ + uint32_t FH; /* force halt */ + uint32_t SS; /* single step */ + } debug; + +#define TMR_IE (1 << 0) +#define TMR_NH (1 << 1) +#define TMR_W (1 << 2) +#define TMR_IP (1 << 3) +#define TMR_PD (1 << 4) + arc_timer_t timer[2]; /* ARC CPU-Timer 0/1 */ + + arc_irq_t irq_bank[256]; /* IRQ register bank */ + uint32_t irq_select; /* AUX register */ + uint32_t aux_irq_act; /* AUX register */ + uint32_t irq_priority_pending; /* AUX register */ + uint32_t icause[16]; /* Banked cause register */ + uint32_t aux_irq_hint; /* AUX register, used to trigger soft irq */ + uint32_t aux_user_sp; + uint32_t aux_irq_ctrl; + uint32_t aux_rtc_ctrl; + uint32_t aux_rtc_low; + uint32_t aux_rtc_high; + + /* Fields required by exception handling. */ + uint32_t causecode; + uint32_t param; + + struct arc_mmu mmu; /* mmu.h */ + ARCMPU mpu; /* mpu.h */ + struct arc_cache cache; /* cache.h */ + + /* used for propagatinng "hostpc/return address" to sub-functions */ + uintptr_t host_pc; + + bool stopped; + + /* Fields up to this point are cleared by a CPU reset */ + struct {} end_reset_fields; + + /* Fields after this point are preserved across CPU reset. */ + uint64_t features; + uint32_t family; + + uint32_t freq_hz; /* CPU frequency in hz, needed for timers. */ + uint64_t last_clk_rtc; + + void *irq[256]; + QEMUTimer *cpu_timer[2]; /* Internal timer. */ + QEMUTimer *cpu_rtc; /* Internal RTC. */ + + /* Build AUX regs. */ +#define TIMER0_IRQ 16 +#define TIMER1_IRQ 17 +#define TB_T0 (1 << 8) +#define TB_T1 (1 << 9) +#define TB_RTC (1 << 10) +#define TB_P0_MSK (0x0f0000) +#define TB_P1_MSK (0xf00000) + uint32_t timer_build; /* Timer configuration AUX register. */ + uint32_t irq_build; /* Interrupt Build Configuration Register. */ + uint32_t vecbase_build; /* Interrupt Vector Base Address Configuration. */ + uint32_t mpy_build; /* Multiply configuration register. */ + uint32_t isa_config; /* Instruction Set Configuration Register. */ + + const struct arc_boot_info *boot_info; +} CPUARCState; + +/* + * ArcCPU: + * @env: #CPUMBState + * + * An ARC CPU. + */ +struct ARCCPU { + /*< private >*/ + CPUState parent_obj; + + /*< public >*/ + + /* ARC Configuration Settings. */ + struct { + uint32_t addr_size; + bool aps_feature; + bool byte_order; + bool bitscan_option; + uint32_t br_bc_entries; + uint32_t br_pt_entries; + bool br_bc_full_tag; + uint8_t br_rs_entries; + uint32_t br_bc_tag_size; + uint8_t br_tosq_entries; + uint8_t br_fb_entries; + bool code_density; + bool code_protect; + uint8_t dccm_mem_cycles; + bool dccm_posedge; + uint8_t dccm_mem_bancks; + uint8_t dc_mem_cycles; + bool dc_posedge; + bool dmp_unaligned; + bool ecc_exception; + uint32_t external_interrupts; + uint8_t ecc_option; + bool firq_option; + bool fpu_dp_option; + bool fpu_fma_option; + bool fpu_div_option; + bool has_actionpoints; + bool has_fpu; + bool has_interrupts; + bool has_mmu; + bool has_mpu; + bool has_timer_0; + bool has_timer_1; + bool has_pct; + bool has_rtt; + bool has_smart; + uint32_t intvbase_preset; + uint32_t lpc_size; + uint8_t mpu_num_regions; + uint8_t mpy_option; + uint32_t mmu_page_size_sel0; + uint32_t mmu_page_size_sel1; + uint32_t mmu_pae_enabled; + uint32_t ntlb_num_entries; + uint32_t num_actionpoints; + uint32_t number_of_interrupts; + uint32_t number_of_levels; + uint32_t pct_counters; + uint32_t pct_interrupt; + uint32_t pc_size; + uint32_t rgf_num_regs; + uint32_t rgf_banked_regs; + uint32_t rgf_num_banks; + bool rtc_option; + uint32_t rtt_feature_level; + bool stack_checking; + bool swap_option; + uint32_t smar_stack_entries; + uint32_t smart_implementation; + uint32_t stlb_num_entries; + uint32_t slc_size; + uint32_t slc_line_size; + uint32_t slc_ways; + uint32_t slc_tag_banks; + uint32_t slc_tram_delay; + uint32_t slc_dbank_width; + uint32_t slc_data_banks; + uint32_t slc_dram_delay; + bool slc_mem_bus_width; + uint32_t slc_ecc_option; + bool slc_data_halfcycle_steal; + bool slc_data_add_pre_pipeline; + bool uaux_option; + uint32_t freq_hz; /* CPU frequency in hz, needed for timers. */ + } cfg; + + CPUNegativeOffsetState neg; + CPUARCState env; +}; + +/* are we in user mode? */ +static inline bool is_user_mode(const CPUARCState *env) +{ + return env->stat.Uf != false; +} + +static inline int arc_feature(const CPUARCState *env, int feature) +{ + return (env->features & (1U << feature)) != 0; +} + +static inline void arc_set_feature(CPUARCState *env, int feature) +{ + env->features |= (1U << feature); +} + +#define cpu_list arc_cpu_list +#define cpu_signal_handler cpu_arc_signal_handler +#define cpu_init(cpu_model) cpu_generic_init(TYPE_ARC_CPU, cpu_model) + +typedef CPUARCState CPUArchState; +typedef ARCCPU ArchCPU; + +#include "exec/cpu-all.h" + +static inline int cpu_mmu_index(const CPUARCState *env, bool ifetch) +{ + return env->stat.Uf != 0 ? 1 : 0; +} + +static inline void cpu_get_tb_cpu_state(CPUARCState *env, target_ulong *pc, + target_ulong *cs_base, + uint32_t *pflags) +{ + *pc = env->pc; + *cs_base = 0; +#ifdef CONFIG_USER_ONLY + *pflags = TB_FLAGS_FP_ENABLE; +#else + *pflags = cpu_mmu_index(env, 0); +#endif +} + +static inline int cpu_interrupts_enabled(const CPUARCState *env) +{ + return env->stat.IEf; +} + +void arc_translate_init(void); + +void arc_cpu_list(void); +int cpu_arc_exec(CPUState *cpu); +int cpu_arc_signal_handler(int host_signum, void *pinfo, void *puc); +bool arc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); +int arc_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf, + int len, bool is_write); +void arc_cpu_do_interrupt(CPUState *cpu); + +void arc_cpu_dump_state(CPUState *cs, FILE *f, int flags); +hwaddr arc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int arc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); +int arc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); + +void QEMU_NORETURN arc_raise_exception(CPUARCState *env, int32_t excp_idx); + +#include "exec/cpu-all.h" + +#endif /* !defined (CPU_ARC_H) */ diff --git a/target/arc/internals.h b/target/arc/internals.h new file mode 100644 index 0000000000..ee054e186a --- /dev/null +++ b/target/arc/internals.h @@ -0,0 +1,38 @@ +/* + * QEMU ARC CPU -- internal functions + * + * Copyright (c) 2019 Synopsys Inc + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + * + */ + +/* + * This header shares funtions prototypes between codes in + * target/arc/ that must remain private to it and not to be + * used by QEMU itself. + */ + +#ifndef TARGET_ARC_INTERNALS_H +#define TARGET_ARC_INTERNALS_H + +#include "cpu.h" + +/* add auxiliary registers to set of supported registers for GDB */ +void arc_cpu_register_gdb_regs_for_features(ARCCPU *cpu); + +/* these are the helper functions used both by translation and gdbstub */ +target_ulong helper_lr(CPUARCState *env, uint32_t aux); +void helper_sr(CPUARCState *env, uint32_t val, uint32_t aux); + +#endif diff --git a/target/arc/meson.build b/target/arc/meson.build new file mode 100644 index 0000000000..67f1e4bfa2 --- /dev/null +++ b/target/arc/meson.build @@ -0,0 +1,20 @@ +arc_softmmu_ss = ss.source_set() +arc_softmmu_ss.add(files( + 'translate.c', + 'helper.c', + 'cpu.c', + 'op_helper.c', + 'gdbstub.c', + 'decoder.c', + 'regs.c', + 'semfunc.c', + 'semfunc-helper.c', + 'mmu.c', + 'mpu.c', + 'timer.c', + 'irq.c', + 'cache.c', +)) + +target_arch += {'arc': arc_softmmu_ss} +target_softmmu_arch += {'arc': arc_softmmu_ss} From patchwork Wed Nov 11 16:17:45 2020 Content-Type: text/plain; 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[2.80.104.46]) by smtp.gmail.com with ESMTPSA id s188sm3115178wmf.45.2020.11.11.08.18.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2020 08:18:05 -0800 (PST) From: cupertinomiranda@gmail.com To: qemu-devel@nongnu.org Subject: [PATCH 02/15] arc: Decoder code Date: Wed, 11 Nov 2020 16:17:45 +0000 Message-Id: <20201111161758.9636-3-cupertinomiranda@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201111161758.9636-1-cupertinomiranda@gmail.com> References: <20201111161758.9636-1-cupertinomiranda@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201111_111808_826045_68FE83C5 X-CRM114-Status: GOOD ( 27.95 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:444 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [cupertinomiranda[at]gmail.com] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Claudiu Zissulescu , Cupertino Miranda , Shahab Vahedi , Shahab Vahedi , Cupertino Miranda , linux-snps-arc@lists.infradead.org, Claudiu Zissulescu Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Claudiu Zissulescu The decoder and the disassembler inspired by ARC GNU binutils. Signed-off-by: Claudiu Zissulescu --- disas/arc.c | 461 ++++++++++++++ target/arc/decoder.c | 1277 +++++++++++++++++++++++++++++++++++++++ target/arc/decoder.h | 349 +++++++++++ target/arc/flags.def | 85 +++ target/arc/operands.def | 123 ++++ 5 files changed, 2295 insertions(+) create mode 100644 disas/arc.c create mode 100644 target/arc/decoder.c create mode 100644 target/arc/decoder.h create mode 100644 target/arc/flags.def create mode 100644 target/arc/operands.def diff --git a/disas/arc.c b/disas/arc.c new file mode 100644 index 0000000000..fe6b834622 --- /dev/null +++ b/disas/arc.c @@ -0,0 +1,461 @@ +/* + * Disassembler code for ARC. + * + * Copyright 2020 Synopsys Inc. + * Contributed by Claudiu Zissulescu + * + * QEMU ARCv2 Disassembler. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2, or (at your option) any later + * version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "disas/dis-asm.h" +#include "target/arc/arc-common.h" +#include "target/arc/decoder.h" +#include "target/arc/regs.h" + +/* Register names. */ + +static const char * const regnames[64] = { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "fp", "sp", "ilink", "r30", "blink", + + "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", + "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", + "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", + "r56", "r57", "r58", "r59", "lp_count", "rezerved", "LIMM", "pcl" +}; + +#define ARRANGE_ENDIAN(info, buf) \ + (info->endian == BFD_ENDIAN_LITTLE ? bfd_getm32(bfd_getl32(buf)) \ + : bfd_getb32(buf)) + +/* + * Helper function to convert middle-endian data to something more + * meaningful. + */ + +static bfd_vma bfd_getm32(unsigned int data) +{ + bfd_vma value = 0; + + value = (data & 0x0000ffff) << 16; + value |= (data & 0xffff0000) >> 16; + return value; +} + +/* Helper for printing instruction flags. */ + +static bfd_boolean special_flag_p(const char *opname, const char *flgname) +{ + const struct arc_flag_special *flg_spec; + unsigned i, j, flgidx; + + for (i = 0; i < arc_num_flag_special; ++i) { + flg_spec = &arc_flag_special_cases[i]; + + if (strcmp(opname, flg_spec->name) != 0) { + continue; + } + + /* Found potential special case instruction. */ + for (j = 0; ; ++j) { + flgidx = flg_spec->flags[j]; + if (flgidx == 0) { + break; /* End of the array. */ + } + + if (strcmp(flgname, arc_flag_operands[flgidx].name) == 0) { + return TRUE; + } + } + } + return FALSE; +} + +/* Print instruction flags. */ + +static void print_flags(const struct arc_opcode *opcode, + uint64_t insn, + struct disassemble_info *info) +{ + const unsigned char *flgidx; + unsigned int value; + + /* Now extract and print the flags. */ + for (flgidx = opcode->flags; *flgidx; flgidx++) { + /* Get a valid flag class. */ + const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx]; + const unsigned *flgopridx; + + /* Check first the extensions. Not supported yet. */ + if (cl_flags->flag_class & F_CLASS_EXTEND) { + value = insn & 0x1F; + } + + for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx) { + const struct arc_flag_operand *flg_operand = + &arc_flag_operands[*flgopridx]; + + /* Implicit flags are only used for the insn decoder. */ + if (cl_flags->flag_class & F_CLASS_IMPLICIT) { + continue; + } + + if (!flg_operand->favail) { + continue; + } + + value = (insn >> flg_operand->shift) & + ((1 << flg_operand->bits) - 1); + if (value == flg_operand->code) { + /* FIXME!: print correctly nt/t flag. */ + if (!special_flag_p(opcode->name, flg_operand->name)) { + (*info->fprintf_func)(info->stream, "."); + } + (*info->fprintf_func)(info->stream, "%s", flg_operand->name); + } + } + } +} + +/* + * When dealing with auxiliary registers, output the proper name if we + * have it. + */ + +static const char *get_auxreg(const struct arc_opcode *opcode, + int value, + unsigned isa_mask) +{ + unsigned int i; + const struct arc_aux_reg_detail *auxr = &arc_aux_regs_detail[0]; + + if (opcode->insn_class != AUXREG) { + return NULL; + } + + for (i = 0; i < ARRAY_SIZE(arc_aux_regs); i++, auxr++) { + if (!(auxr->cpu & isa_mask)) { + continue; + } + + if (auxr->subclass != NONE) { + return NULL; + } + + if (auxr->address == value) { + return auxr->name; + } + } + return NULL; +} + +/* Print the operands of an instruction. */ + +static void print_operands(const struct arc_opcode *opcode, + bfd_vma memaddr, + uint64_t insn, + uint32_t isa_mask, + insn_t *pinsn, + struct disassemble_info *info) +{ + bfd_boolean need_comma = FALSE; + bfd_boolean open_braket = FALSE; + int value, vpcl = 0; + bfd_boolean rpcl = FALSE, rset = FALSE; + const unsigned char *opidx; + int i; + + for (i = 0, opidx = opcode->operands; *opidx; opidx++) { + const struct arc_operand *operand = &arc_operands[*opidx]; + + if (open_braket && (operand->flags & ARC_OPERAND_BRAKET)) { + (*info->fprintf_func)(info->stream, "]"); + open_braket = FALSE; + continue; + } + + /* Only take input from real operands. */ + if (ARC_OPERAND_IS_FAKE(operand)) { + continue; + } + + if (need_comma) { + (*info->fprintf_func)(info->stream, ","); + } + + if (!open_braket && (operand->flags & ARC_OPERAND_BRAKET)) { + (*info->fprintf_func)(info->stream, "["); + open_braket = TRUE; + need_comma = FALSE; + continue; + } + + need_comma = TRUE; + + /* Get the decoded */ + value = pinsn->operands[i++].value; + + if ((operand->flags & ARC_OPERAND_IGNORE) && + (operand->flags & ARC_OPERAND_IR) && + value == -1) { + need_comma = FALSE; + continue; + } + + if (operand->flags & ARC_OPERAND_PCREL) { + rpcl = TRUE; + vpcl = value; + rset = TRUE; + + info->target = (bfd_vma) (memaddr & ~3) + value; + } else if (!(operand->flags & ARC_OPERAND_IR)) { + vpcl = value; + rset = TRUE; + } + + /* Print the operand as directed by the flags. */ + if (operand->flags & ARC_OPERAND_IR) { + const char *rname; + + assert(value >= 0 && value < 64); + rname = regnames[value]; + (*info->fprintf_func)(info->stream, "%s", rname); + if (operand->flags & ARC_OPERAND_TRUNCATE) { + /* Make sure we print only legal register pairs. */ + if ((value & 0x01) == 0) { + rname = regnames[value + 1]; + } + (*info->fprintf_func)(info->stream, "%s", rname); + } + if (value == 63) { + rpcl = TRUE; + } else { + rpcl = FALSE; + } + } else if (operand->flags & ARC_OPERAND_LIMM) { + value = pinsn->limm; + const char *rname = get_auxreg(opcode, value, isa_mask); + + if (rname && open_braket) { + (*info->fprintf_func)(info->stream, "%s", rname); + } else { + (*info->fprintf_func)(info->stream, "%#x", value); + } + } else if (operand->flags & ARC_OPERAND_SIGNED) { + const char *rname = get_auxreg(opcode, value, isa_mask); + if (rname && open_braket) { + (*info->fprintf_func)(info->stream, "%s", rname); + } else { + (*info->fprintf_func)(info->stream, "%d", value); + } + } else { + if (operand->flags & ARC_OPERAND_TRUNCATE && + !(operand->flags & ARC_OPERAND_ALIGNED32) && + !(operand->flags & ARC_OPERAND_ALIGNED16) && + value >= 0 && value <= 14) { + /* Leave/Enter mnemonics. */ + switch (value) { + case 0: + need_comma = FALSE; + break; + case 1: + (*info->fprintf_func)(info->stream, "r13"); + break; + default: + (*info->fprintf_func)(info->stream, "r13-%s", + regnames[13 + value - 1]); + break; + } + rpcl = FALSE; + rset = FALSE; + } else { + const char *rname = get_auxreg(opcode, value, isa_mask); + if (rname && open_braket) { + (*info->fprintf_func)(info->stream, "%s", rname); + } else { + (*info->fprintf_func)(info->stream, "%#x", value); + } + } + } + } + + /* Pretty print extra info for pc-relative operands. */ + if (rpcl && rset) { + if (info->flags & INSN_HAS_RELOC) { + /* + * If the instruction has a reloc associated with it, then + * the offset field in the instruction will actually be + * the addend for the reloc. (We are using REL type + * relocs). In such cases, we can ignore the pc when + * computing addresses, since the addend is not currently + * pc-relative. + */ + memaddr = 0; + } + + (*info->fprintf_func)(info->stream, "\t;"); + (*info->print_address_func)((memaddr & ~3) + vpcl, info); + } +} + +/* Select the proper instructions set for the given architecture. */ + +static int arc_read_mem(bfd_vma memaddr, + uint64_t *insn, + uint32_t *isa_mask, + struct disassemble_info *info) +{ + bfd_byte buffer[8]; + unsigned int highbyte, lowbyte; + int status; + int insn_len = 0; + + highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0); + lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1); + + switch (info->mach) { + case bfd_mach_arc_arc700: + *isa_mask = ARC_OPCODE_ARC700; + break; + + case bfd_mach_arc_arc601: + case bfd_mach_arc_arc600: + *isa_mask = ARC_OPCODE_ARC600; + break; + + case bfd_mach_arc_arcv2em: + case bfd_mach_arc_arcv2: + *isa_mask = ARC_OPCODE_ARCv2EM; + break; + case bfd_mach_arc_arcv2hs: + *isa_mask = ARC_OPCODE_ARCv2HS; + break; + default: + *isa_mask = ARC_OPCODE_ARCv2EM; + break; + } + + info->bytes_per_line = 8; + info->bytes_per_chunk = 2; + info->display_endian = info->endian; + + /* Read the insn into a host word. */ + status = (*info->read_memory_func)(memaddr, buffer, 2, info); + + if (status != 0) { + (*info->memory_error_func)(status, memaddr, info); + return -1; + } + + insn_len = arc_insn_length((buffer[highbyte] << 8 | + buffer[lowbyte]), *isa_mask); + + switch (insn_len) { + case 2: + *insn = (buffer[highbyte] << 8) | buffer[lowbyte]; + break; + + case 4: + /* This is a long instruction: Read the remaning 2 bytes. */ + status = (*info->read_memory_func)(memaddr + 2, &buffer[2], 2, info); + if (status != 0) { + (*info->memory_error_func)(status, memaddr + 2, info); + return -1; + } + *insn = (uint64_t) ARRANGE_ENDIAN(info, buffer); + break; + + case 6: + status = (*info->read_memory_func)(memaddr + 2, &buffer[2], 4, info); + if (status != 0) { + (*info->memory_error_func)(status, memaddr + 2, info); + return -1; + } + *insn = (uint64_t) ARRANGE_ENDIAN(info, &buffer[2]); + *insn |= ((uint64_t) buffer[highbyte] << 40) | + ((uint64_t) buffer[lowbyte] << 32); + break; + + case 8: + status = (*info->read_memory_func)(memaddr + 2, &buffer[2], 6, info); + if (status != 0) { + (*info->memory_error_func)(status, memaddr + 2, info); + return -1; + } + *insn = ((((uint64_t) ARRANGE_ENDIAN(info, buffer)) << 32) | + ((uint64_t) ARRANGE_ENDIAN(info, &buffer[4]))); + break; + + default: + /* There is no instruction whose length is not 2, 4, 6, or 8. */ + g_assert_not_reached(); + } + return insn_len; +} + +/* Disassembler main entry function. */ + +int print_insn_arc(bfd_vma memaddr, struct disassemble_info *info) +{ + const struct arc_opcode *opcode = NULL; + int insn_len = -1; + uint64_t insn; + uint32_t isa_mask; + insn_t dis_insn; + + insn_len = arc_read_mem(memaddr, &insn, &isa_mask, info); + + if (insn_len < 2) { + return -1; + } + + opcode = arc_find_format(&dis_insn, insn, insn_len, isa_mask); + + /* If limm is required, read it. */ + if (dis_insn.limm_p) { + bfd_byte buffer[4]; + int status = (*info->read_memory_func)(memaddr + insn_len, buffer, + 4, info); + if (status != 0) { + return -1; + } + dis_insn.limm = ARRANGE_ENDIAN(info, buffer); + insn_len += 4; + } + + /* Print the mnemonic. */ + (*info->fprintf_func)(info->stream, "%s", opcode->name); + + print_flags(opcode, insn, info); + + if (opcode->operands[0] != 0) { + (*info->fprintf_func)(info->stream, "\t"); + } + + /* Now extract and print the operands. */ + print_operands(opcode, memaddr, insn, isa_mask, &dis_insn, info); + + /* Say how many bytes we consumed */ + return insn_len; +} + + +/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ +/* vim: set ts=4 sw=4 et: */ diff --git a/target/arc/decoder.c b/target/arc/decoder.c new file mode 100644 index 0000000000..eb4059acaa --- /dev/null +++ b/target/arc/decoder.c @@ -0,0 +1,1277 @@ +/* + * QEMU Decoder for the ARC. + * Copyright (C) 2020 Free Software Foundation, Inc. + + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 of + * the License, or (at your option) any later version. + + * This library is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + + * You should have received a copy of the GNU General Public License + * along with GAS or GDB; see the file COPYING3. If not, write to + * the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include "qemu/osdep.h" +#include "target/arc/decoder.h" +#include "qemu/osdep.h" +#include "qemu/bswap.h" +#include "cpu.h" + +/* Extract functions. */ +static ATTRIBUTE_UNUSED int +extract_limm(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + return value; +} + +/* mask = 00000000000000000000111111000000. */ +static long long int +extract_uimm6_20(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 6) & 0x003f) << 0; + + return value; +} + +/* mask = 00000000000000000000111111222222. */ +static long long int +extract_simm12_20(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 6) & 0x003f) << 0; + value |= ((insn >> 0) & 0x003f) << 6; + + /* Extend the sign. */ + int signbit = 1 << (12 - 1); + value = (value ^ signbit) - signbit; + + return value; +} + +/* mask = 0000011100000000. */ +static ATTRIBUTE_UNUSED int +extract_simm3_5_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 8) & 0x0007) << 0; + + /* Extend the sign. */ + int signbit = 1 << (3 - 1); + value = (value ^ signbit) - signbit; + + return value; +} + +static ATTRIBUTE_UNUSED int +extract_limm_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + return value; +} + +/* mask = 0000000000011111. */ +static long long int +extract_uimm7_a32_11_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 0) & 0x001f) << 2; + + return value; +} + +/* mask = 0000000001111111. */ +static long long int +extract_uimm7_9_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 0) & 0x007f) << 0; + + return value; +} + +/* mask = 0000000000000111. */ +static long long int +extract_uimm3_13_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 0) & 0x0007) << 0; + + return value; +} + +/* mask = 0000000111111111. */ +static long long int +extract_simm11_a32_7_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 0) & 0x01ff) << 2; + + /* Extend the sign. */ + int signbit = 1 << (11 - 1); + value = (value ^ signbit) - signbit; + + return value; +} + +/* mask = 0000000002220111. */ +static long long int +extract_uimm6_13_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 0) & 0x0007) << 0; + value |= ((insn >> 4) & 0x0007) << 3; + + return value; +} + +/* mask = 0000000000011111. */ +static long long int +extract_uimm5_11_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 0) & 0x001f) << 0; + + return value; +} + +/* mask = 00000000111111102000000000000000. */ +static long long int +extract_simm9_a16_8(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 17) & 0x007f) << 1; + value |= ((insn >> 15) & 0x0001) << 8; + + /* Extend the sign. */ + int signbit = 1 << (9 - 1); + value = (value ^ signbit) - signbit; + + return value; +} + +/* mask = 00000000000000000000111111000000. */ +static long long int +extract_uimm6_8(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 6) & 0x003f) << 0; + + return value; +} + +/* mask = 00000111111111102222222222000000. */ +static long long int +extract_simm21_a16_5(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 17) & 0x03ff) << 1; + value |= ((insn >> 6) & 0x03ff) << 11; + + /* Extend the sign. */ + int signbit = 1 << (21 - 1); + value = (value ^ signbit) - signbit; + + return value; +} + +/* mask = 00000111111111102222222222003333. */ +static long long int +extract_simm25_a16_5(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 17) & 0x03ff) << 1; + value |= ((insn >> 6) & 0x03ff) << 11; + value |= ((insn >> 0) & 0x000f) << 21; + + /* Extend the sign. */ + int signbit = 1 << (25 - 1); + value = (value ^ signbit) - signbit; + + return value; +} + +/* mask = 0000000111111111. */ +static long long int +extract_simm10_a16_7_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 0) & 0x01ff) << 1; + + /* Extend the sign. */ + int signbit = 1 << (10 - 1); + value = (value ^ signbit) - signbit; + + return value; +} + +/* mask = 0000000000111111. */ +static long long int +extract_simm7_a16_10_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 0) & 0x003f) << 1; + + /* Extend the sign. */ + int signbit = 1 << (7 - 1); + value = (value ^ signbit) - signbit; + + return value; +} + +/* mask = 00000111111111002222222222000000. */ +static long long int +extract_simm21_a32_5(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 18) & 0x01ff) << 2; + value |= ((insn >> 6) & 0x03ff) << 11; + + /* Extend the sign. */ + int signbit = 1 << (21 - 1); + value = (value ^ signbit) - signbit; + + return value; +} + +/* mask = 00000111111111002222222222003333. */ +static long long int +extract_simm25_a32_5(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 18) & 0x01ff) << 2; + value |= ((insn >> 6) & 0x03ff) << 11; + value |= ((insn >> 0) & 0x000f) << 21; + + /* Extend the sign. */ + int signbit = 1 << (25 - 1); + value = (value ^ signbit) - signbit; + + return value; +} + +/* mask = 0000011111111111. */ +static long long int +extract_simm13_a32_5_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 0) & 0x07ff) << 2; + + /* Extend the sign. */ + int signbit = 1 << (13 - 1); + value = (value ^ signbit) - signbit; + + return value; +} + +/* mask = 0000000001111111. */ +static long long int +extract_simm8_a16_9_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 0) & 0x007f) << 1; + + /* Extend the sign. */ + int signbit = 1 << (8 - 1); + value = (value ^ signbit) - signbit; + + return value; +} + +/* mask = 00000000000000000000000111000000. */ +static long long int +extract_uimm3_23(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 6) & 0x0007) << 0; + + return value; +} + +/* mask = 0000001111111111. */ +static long long int +extract_uimm10_6_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 0) & 0x03ff) << 0; + + return value; +} + +/* mask = 0000002200011110. */ +static long long int +extract_uimm6_11_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 1) & 0x000f) << 0; + value |= ((insn >> 8) & 0x0003) << 4; + + return value; +} + +/* mask = 00000000111111112000000000000000. */ +static long long int +extract_simm9_8(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 16) & 0x00ff) << 0; + value |= ((insn >> 15) & 0x0001) << 8; + + /* Extend the sign. */ + int signbit = 1 << (9 - 1); + value = (value ^ signbit) - signbit; + + return value; +} + +/* mask = 0000000011111111. */ +static long long int +extract_uimm10_a32_8_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 0) & 0x00ff) << 2; + + return value; +} + +/* mask = 0000000111111111. */ +static long long int +extract_simm9_7_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 0) & 0x01ff) << 0; + + /* Extend the sign. */ + int signbit = 1 << (9 - 1); + value = (value ^ signbit) - signbit; + + return value; +} + +/* mask = 0000000000011111. */ +static long long int +extract_uimm6_a16_11_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 0) & 0x001f) << 1; + + return value; +} + +/* mask = 0000020000011000. */ +static long long int +extract_uimm5_a32_11_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 3) & 0x0003) << 2; + value |= ((insn >> 10) & 0x0001) << 4; + + return value; +} + +/* mask = 0000022222200111. */ +static long long int +extract_simm11_a32_13_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 0) & 0x0007) << 2; + value |= ((insn >> 5) & 0x003f) << 5; + + /* Extend the sign. */ + int signbit = 1 << (11 - 1); + value = (value ^ signbit) - signbit; + + return value; +} + +/* mask = 0000000022220111. */ +static long long int +extract_uimm7_13_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 0) & 0x0007) << 0; + value |= ((insn >> 4) & 0x000f) << 3; + + return value; +} + +/* mask = 00000000000000000000011111000000. */ +static long long int +extract_uimm6_a16_21(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 6) & 0x001f) << 1; + + return value; +} + +/* mask = 0000022200011110. */ +static long long int +extract_uimm7_11_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 1) & 0x000f) << 0; + value |= ((insn >> 8) & 0x0007) << 4; + + return value; +} + +/* mask = 00000000000000000000111111000000. */ +static long long int +extract_uimm7_a16_20(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 6) & 0x003f) << 1; + + return value; +} + +/* mask = 00000000000000000000111111222222. */ +static long long int +extract_simm13_a16_20(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 6) & 0x003f) << 1; + value |= ((insn >> 0) & 0x003f) << 7; + + /* Extend the sign. */ + int signbit = 1 << (13 - 1); + value = (value ^ signbit) - signbit; + + return value; +} + +/* mask = 0000000011111111. */ +static long long int +extract_uimm8_8_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 0) & 0x00ff) << 0; + + return value; +} + +/* mask = 0000011111100000. */ +static long long int +extract_uimm6_5_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 5) & 0x003f) << 0; + + return value; +} + +/* mask = 00000000000000000000000000000000. */ +static ATTRIBUTE_UNUSED int +extract_uimm6_axx_(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + return value; +} + +static long long int extract_rb(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07); + + if (value == 0x3e && invalid) { + *invalid = TRUE; + } + + return value; +} + +static long long int extract_rhv1(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7); + + return value; +} + +static long long int extract_rhv2(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3); + + return value; +} + +static long long int extract_r0(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + return 0; +} + +static long long int extract_r1(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + return 1; +} + +static long long int extract_r2(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + return 2; +} + +static long long int extract_r3(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + return 3; +} + +static long long int extract_sp(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + return 28; +} + +static long long int extract_gp(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + return 26; +} + +static long long int extract_pcl(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + return 63; +} + +static long long int extract_blink(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + return 31; +} + +static long long int extract_ilink1(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + return 29; +} + +static long long int extract_ilink2(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + return 30; +} + +static long long int extract_ras(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = insn & 0x07; + if (value > 3) { + return value + 8; + } else { + return value; + } +} + +static long long int extract_rbs(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = (insn >> 8) & 0x07; + if (value > 3) { + return value + 8; + } else { + return value; + } +} + +static long long int extract_rcs(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = (insn >> 5) & 0x07; + if (value > 3) { + return value + 8; + } else { + return value; + } +} + +static long long int extract_simm3s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = (insn >> 8) & 0x07; + if (value == 7) { + return -1; + } else { + return value; + } +} + +static long long int extract_rrange(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + return (insn >> 1) & 0x0F; +} + +static long long int extract_fpel(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + return (insn & 0x0100) ? 27 : -1; +} + +static long long int extract_blinkel(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + return (insn & 0x0200) ? 31 : -1; +} + +static long long int extract_pclel(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + return (insn & 0x0400) ? 63 : -1; +} + +static long long int extract_w6(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + signed value = 0; + + value |= ((insn >> 6) & 0x003f) << 0; + + int signbit = 1 << 5; + value = (value ^ signbit) - signbit; + + return value; +} + +static long long int extract_g_s(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 8) & 0x0007) << 0; + value |= ((insn >> 3) & 0x0003) << 3; + + /* Extend the sign. */ + int signbit = 1 << (6 - 1); + value = (value ^ signbit) - signbit; + + return value; +} + +static long long int extract_uimm12_20(unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean *invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 6) & 0x003f) << 0; + value |= ((insn >> 0) & 0x003f) << 6; + + return value; +} + +/* + * The operands table. + * + * The format of the operands table is: + * + * BITS SHIFT FLAGS EXTRACT_FUN. + */ +const struct arc_operand arc_operands[] = { + { 0, 0, 0, 0 }, +#define ARC_OPERAND(NAME, BITS, SHIFT, RELO, FLAGS, FUN) \ + { BITS, SHIFT, FLAGS, FUN }, +#include "target/arc/operands.def" +#undef ARC_OPERAND + { 0, 0, 0, 0} +}; + +enum arc_operands_map { + OPERAND_UNUSED = 0, +#define ARC_OPERAND(NAME, BITS, SHIFT, RELO, FLAGS, FUN) OPERAND_##NAME, +#include "target/arc/operands.def" +#undef ARC_OPERAND + OPERAND_LAST +}; + +/* + * The flag operands table. + * + * The format of the table is + * NAME CODE BITS SHIFT FAVAIL. + */ +const struct arc_flag_operand arc_flag_operands[] = { + { 0, 0, 0, 0, 0}, +#define ARC_FLAG(NAME, MNEMONIC, CODE, BITS, SHIFT, AVAIL) \ + { MNEMONIC, CODE, BITS, SHIFT, AVAIL }, +#include "target/arc/flags.def" +#undef ARC_FLAG + { 0, 0, 0, 0, 0} +}; + +enum arc_flags_map { + F_NULL = 0, +#define ARC_FLAG(NAME, MNEMONIC, CODE, BITS, SHIFT, AVAIL) F_##NAME, +#include "target/arc/flags.def" +#undef ARC_FLAG + F_LAST +}; + +/* + * Table of the flag classes. + * + * The format of the table is + * CLASS {FLAG_CODE}. + */ +const struct arc_flag_class arc_flag_classes[] = { +#define C_EMPTY 0 + { F_CLASS_NONE, { F_NULL } }, + +#define C_CC_EQ (C_EMPTY + 1) + {F_CLASS_IMPLICIT | F_CLASS_COND, {F_EQUAL, F_NULL} }, + +#define C_CC_GE (C_CC_EQ + 1) + {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GE, F_NULL} }, + +#define C_CC_GT (C_CC_GE + 1) + {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GT, F_NULL} }, + +#define C_CC_HI (C_CC_GT + 1) + {F_CLASS_IMPLICIT | F_CLASS_COND, {F_HI, F_NULL} }, + +#define C_CC_HS (C_CC_HI + 1) + {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTCARRY, F_NULL} }, + +#define C_CC_LE (C_CC_HS + 1) + {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LE, F_NULL} }, + +#define C_CC_LO (C_CC_LE + 1) + {F_CLASS_IMPLICIT | F_CLASS_COND, {F_CARRY, F_NULL} }, + +#define C_CC_LS (C_CC_LO + 1) + {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LS, F_NULL} }, + +#define C_CC_LT (C_CC_LS + 1) + {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LT, F_NULL} }, + +#define C_CC_NE (C_CC_LT + 1) + {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTEQUAL, F_NULL} }, + +#define C_AA_AB (C_CC_NE + 1) + {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AB3, F_NULL} }, + +#define C_AA_AW (C_AA_AB + 1) + {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AW3, F_NULL} }, + +#define C_ZZ_D (C_AA_AW + 1) + {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZED, F_NULL} }, + +#define C_ZZ_H (C_ZZ_D + 1) + {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_H1, F_NULL} }, + +#define C_ZZ_B (C_ZZ_H + 1) + {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZEB1, F_NULL} }, + +#define C_CC (C_ZZ_B + 1) + { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND, + { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, + F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, + F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, + F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, + F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, + F_LE, F_HI, F_LS, F_PNZ, F_NULL + } + }, + +#define C_AA_ADDR3 (C_CC + 1) +#define C_AA27 (C_CC + 1) + { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } }, +#define C_AA_ADDR9 (C_AA_ADDR3 + 1) +#define C_AA21 (C_AA_ADDR3 + 1) + { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } }, +#define C_AA_ADDR22 (C_AA_ADDR9 + 1) +#define C_AA8 (C_AA_ADDR9 + 1) + { F_CLASS_OPTIONAL | F_CLASS_WB, + { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } + }, + +#define C_F (C_AA_ADDR22 + 1) + { F_CLASS_OPTIONAL | F_CLASS_F, { F_FLAG, F_NULL } }, +#define C_FHARD (C_F + 1) + { F_CLASS_OPTIONAL | F_CLASS_F, { F_FFAKE, F_NULL } }, + +#define C_T (C_FHARD + 1) + { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } }, +#define C_D (C_T + 1) + { F_CLASS_OPTIONAL | F_CLASS_D, { F_ND, F_D, F_NULL } }, +#define C_DNZ_D (C_D + 1) + { F_CLASS_OPTIONAL | F_CLASS_D, { F_DNZ_ND, F_DNZ_D, F_NULL } }, + +#define C_DHARD (C_DNZ_D + 1) + { F_CLASS_OPTIONAL | F_CLASS_D, { F_DFAKE, F_NULL } }, + +#define C_DI20 (C_DHARD + 1) + { F_CLASS_OPTIONAL | F_CLASS_DI, { F_DI11, F_NULL } }, +#define C_DI14 (C_DI20 + 1) + { F_CLASS_OPTIONAL | F_CLASS_DI, { F_DI14, F_NULL } }, +#define C_DI16 (C_DI14 + 1) + { F_CLASS_OPTIONAL | F_CLASS_DI, { F_DI15, F_NULL } }, +#define C_DI26 (C_DI16 + 1) + { F_CLASS_OPTIONAL | F_CLASS_DI, { F_DI5, F_NULL } }, + +#define C_X25 (C_DI26 + 1) + { F_CLASS_OPTIONAL | F_CLASS_X, { F_SIGN6, F_NULL } }, +#define C_X15 (C_X25 + 1) + { F_CLASS_OPTIONAL | F_CLASS_X, { F_SIGN16, F_NULL } }, +#define C_XHARD (C_X15 + 1) +#define C_X (C_X15 + 1) + { F_CLASS_OPTIONAL | F_CLASS_X, { F_SIGNX, F_NULL } }, + +#define C_ZZ13 (C_X + 1) + { F_CLASS_OPTIONAL | F_CLASS_ZZ, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL} }, +#define C_ZZ23 (C_ZZ13 + 1) + { F_CLASS_OPTIONAL | F_CLASS_ZZ, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL} }, +#define C_ZZ29 (C_ZZ23 + 1) + { F_CLASS_OPTIONAL | F_CLASS_ZZ, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL} }, + +#define C_AS (C_ZZ29 + 1) + { F_CLASS_IMPLICIT | F_CLASS_OPTIONAL | F_CLASS_WB, { F_ASFAKE, F_NULL} }, + +#define C_NE (C_AS + 1) + { F_CLASS_OPTIONAL | F_CLASS_COND, { F_NE, F_NULL} }, +}; + +/* List with special cases instructions and the applicable flags. */ +const struct arc_flag_special arc_flag_special_cases[] = { + { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, + F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, + F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, + F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, + F_LE, F_HI, F_LS, F_PNZ, F_NULL + } + }, + { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, + F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, + F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, + F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, + F_LE, F_HI, F_LS, F_PNZ, F_NULL + } + }, + { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, + F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, + F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, + F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, + F_LE, F_HI, F_LS, F_PNZ, F_NULL + } + }, + { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, + F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, + F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, + F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, + F_LE, F_HI, F_LS, F_PNZ, F_NULL + } + }, + { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, + F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, + F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, + F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, + F_LE, F_HI, F_LS, F_PNZ, F_NULL + } + }, + { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, + F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, + F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, + F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, + F_LE, F_HI, F_LS, F_PNZ, F_NULL + } + }, + { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, + F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, + F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, + F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, + F_LE, F_HI, F_LS, F_PNZ, F_NULL + } + }, + { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } }, + { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } } +}; + +const unsigned arc_num_flag_special = ARRAY_SIZE(arc_flag_special_cases); + +/* + * The opcode table. + * + * The format of the opcode table is: + * + * NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }. + * + * The table is organised such that, where possible, all instructions with + * the same mnemonic are together in a block. When the assembler searches + * for a suitable instruction the entries are checked in table order, so + * more specific, or specialised cases should appear earlier in the table. + * + * As an example, consider two instructions 'add a,b,u6' and 'add + * a,b,limm'. The first takes a 6-bit immediate that is encoded within the + * 32-bit instruction, while the second takes a 32-bit immediate that is + * encoded in a follow-on 32-bit, making the total instruction length + * 64-bits. In this case the u6 variant must appear first in the table, as + * all u6 immediates could also be encoded using the 'limm' extension, + * however, we want to use the shorter instruction wherever possible. + * + * It is possible though to split instructions with the same mnemonic into + * multiple groups. However, the instructions are still checked in table + * order, even across groups. The only time that instructions with the + * same mnemonic should be split into different groups is when different + * variants of the instruction appear in different architectures, in which + * case, grouping all instructions from a particular architecture together + * might be preferable to merging the instruction into the main instruction + * table. + * + * An example of this split instruction groups can be found with the 'sync' + * instruction. The core arc architecture provides a 'sync' instruction, + * while the nps instruction set extension provides 'sync.rd' and + * 'sync.wr'. The rd/wr flags are instruction flags, not part of the + * mnemonic, so we end up with two groups for the sync instruction, the + * first within the core arc instruction table, and the second within the + * nps extension instructions. + */ +static const struct arc_opcode arc_opcodes[] = { +#include "target/arc/opcodes.def" + { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } } +}; + +/* Return length of an opcode in bytes. */ +static uint8_t arc_opcode_len(const struct arc_opcode *opcode) +{ + if (opcode->mask < 0x10000ull) { + return 2; + } + + if (opcode->mask < 0x100000000ull) { + return 4; + } + + if (opcode->mask < 0x1000000000000ull) { + return 6; + } + + return 8; +} + +/*Helper for arc_find_format. */ +static const struct arc_opcode *find_format(insn_t *pinsn, + uint64_t insn, + uint8_t insn_len, + uint32_t isa_mask) +{ + uint32_t i = 0; + const struct arc_opcode *opcode = NULL; + const uint8_t *opidx; + const uint8_t *flgidx; + bool has_limm = false; + + do { + bool invalid = false; + uint32_t noperands = 0; + + opcode = &arc_opcodes[i++]; + memset(pinsn, 0, sizeof(*pinsn)); + + if (!(opcode->cpu & isa_mask)) { + continue; + } + + if (arc_opcode_len(opcode) != (int) insn_len) { + continue; + } + + if ((insn & opcode->mask) != opcode->opcode) { + continue; + } + + has_limm = false; + + /* Possible candidate, check the operands. */ + for (opidx = opcode->operands; *opidx; ++opidx) { + int value, limmind; + const struct arc_operand *operand = &arc_operands[*opidx]; + + if (operand->flags & ARC_OPERAND_FAKE) { + continue; + } + + if (operand->extract) { + value = (*operand->extract)(insn, &invalid); + } else { + value = (insn >> operand->shift) & ((1 << operand->bits) - 1); + } + + /* + * Check for LIMM indicator. If it is there, then make sure + * we pick the right format. + */ + limmind = (isa_mask & ARC_OPCODE_ARCV2) ? 0x1E : 0x3E; + if (operand->flags & ARC_OPERAND_IR && + !(operand->flags & ARC_OPERAND_LIMM)) { + if ((value == 0x3E && insn_len == 4) || + (value == limmind && insn_len == 2)) { + invalid = TRUE; + break; + } + } + + if (operand->flags & ARC_OPERAND_LIMM && + !(operand->flags & ARC_OPERAND_DUPLICATE)) { + has_limm = true; + } + + pinsn->operands[noperands].value = value; + pinsn->operands[noperands].type = operand->flags; + noperands += 1; + pinsn->n_ops = noperands; + } + + /* Check the flags. */ + for (flgidx = opcode->flags; *flgidx; ++flgidx) { + /* Get a valid flag class. */ + const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx]; + const unsigned *flgopridx; + bool foundA = false, foundB = false; + unsigned int value; + + /* FIXME! Add check for EXTENSION flags. */ + + for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx) { + const struct arc_flag_operand *flg_operand = + &arc_flag_operands[*flgopridx]; + + /* Check for the implicit flags. */ + if (cl_flags->flag_class & F_CLASS_IMPLICIT) { + if (cl_flags->flag_class & F_CLASS_COND) { + pinsn->cc = flg_operand->code; + } else if (cl_flags->flag_class & F_CLASS_WB) { + pinsn->aa = flg_operand->code; + } else if (cl_flags->flag_class & F_CLASS_ZZ) { + pinsn->zz = flg_operand->code; + } + continue; + } + + value = (insn >> flg_operand->shift) & + ((1 << flg_operand->bits) - 1); + if (value == flg_operand->code) { + if (cl_flags->flag_class & F_CLASS_ZZ) { + switch (flg_operand->name[0]) { + case 'b': + pinsn->zz = 1; + break; + case 'h': + case 'w': + pinsn->zz = 2; + break; + default: + pinsn->zz = 4; + break; + } + } + + /* + * TODO: This has a problem: instruction "b label" + * sets this to true. + */ + if (cl_flags->flag_class & F_CLASS_D) { + pinsn->d = value ? true : false; + if (cl_flags->flags[0] == F_DFAKE) { + pinsn->d = true; + } + } + + if (cl_flags->flag_class & F_CLASS_COND) { + pinsn->cc = value; + } + + if (cl_flags->flag_class & F_CLASS_WB) { + pinsn->aa = value; + } + + if (cl_flags->flag_class & F_CLASS_F) { + pinsn->f = true; + } + + if (cl_flags->flag_class & F_CLASS_DI) { + pinsn->di = true; + } + + if (cl_flags->flag_class & F_CLASS_X) { + pinsn->x = true; + } + + foundA = true; + } + if (value) { + foundB = true; + } + } + + if (!foundA && foundB) { + invalid = TRUE; + break; + } + } + + if (invalid) { + continue; + } + + /* The instruction is valid. */ + pinsn->limm_p = has_limm; + pinsn->class = (uint32_t) opcode->insn_class; + + /* + * FIXME: here add extra info about the instruction + * e.g. delay slot, data size, write back, etc. + */ + return opcode; + } while (opcode->mask); + + memset(pinsn, 0, sizeof(*pinsn)); + return NULL; +} + +/* Main entry point for this file. */ +const struct arc_opcode *arc_find_format(insn_t *insnd, + uint64_t insn, + uint8_t insn_len, + uint32_t isa_mask) +{ + memset(insnd, 0, sizeof(*insnd)); + return find_format(insnd, insn, insn_len, isa_mask); +} + +/* + * Calculate the instruction length for an instruction starting with + * MSB and LSB, the most and least significant byte. The ISA_MASK is + * used to filter the instructions considered to only those that are + * part of the current architecture. + * + * The instruction lengths are calculated from the ARC_OPCODE table, + * and cached for later use. + */ +unsigned int arc_insn_length(uint16_t insn, uint16_t cpu_type) +{ + uint8_t major_opcode; + uint8_t msb, lsb; + + msb = (uint8_t)(insn >> 8); + lsb = (uint8_t)(insn & 0xFF); + major_opcode = msb >> 3; + + switch (cpu_type) { + case ARC_OPCODE_ARC700: + if (major_opcode == 0xb) { + uint8_t minor_opcode = lsb & 0x1f; + + if (minor_opcode < 4) { + return 6; + } else if (minor_opcode == 0x10 || minor_opcode == 0x11) { + return 8; + } + } + if (major_opcode == 0xa) { + return 8; + } + /* Fall through. */ + case ARC_OPCODE_ARC600: + return (major_opcode > 0xb) ? 2 : 4; + break; + + case ARC_OPCODE_ARCv2EM: + case ARC_OPCODE_ARCv2HS: + return (major_opcode > 0x7) ? 2 : 4; + break; + + default: + g_assert_not_reached(); + } +} + +/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ +/* vim: set ts=4 sw=4 et: */ diff --git a/target/arc/decoder.h b/target/arc/decoder.h new file mode 100644 index 0000000000..22c6a71607 --- /dev/null +++ b/target/arc/decoder.h @@ -0,0 +1,349 @@ +/* + * Decoder for the ARC. + * Copyright 2020 Free Software Foundation, Inc. + * + * QEMU ARCv2 Decoder. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2, or (at your option) any later + * version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef ARC_DECODER_H +#define ARC_DECODER_H + +#include "arc-common.h" + +#ifndef MAX_INSN_ARGS +#define MAX_INSN_ARGS 16 +#endif + +#ifndef MAX_INSN_FLGS +#define MAX_INSN_FLGS 4 +#endif + +/* Instruction Class. */ +typedef enum { + NADA = 0, + ARC_ACL, + ARITH, + AUXREG, + BBIT0, + BBIT1, + BI, + BIH, + BITOP, + BITSTREAM, + BMU, + BRANCH, + BRCC, + CONTROL, + DIVREM, + DPI, + DSP, + EI, + ENTER, + ARC_FLOAT, + INVALID, + JLI, + JUMP, + KERNEL, + LEAVE, + LOAD, + LOGICAL, + LOOP, + MEMORY, + MOVE, + MPY, + NET, + PROTOCOL_DECODE, + PMU, + POP, + PUSH, + SJLI, + STORE, + SUB, + XY +} insn_class_t; + +/* Instruction Subclass. */ +typedef enum { + NONE = 0, + CVT = (1U << 1), + BTSCN = (1U << 2), + CD = (1U << 3), + CD1 = CD, + CD2 = CD, + COND = (1U << 4), + DIV = (1U << 5), + DP = (1U << 6), + DPA = (1U << 7), + DPX = (1U << 8), + MPY1E = (1U << 9), + MPY6E = (1U << 10), + MPY7E = (1U << 11), + MPY8E = (1U << 12), + MPY9E = (1U << 13), + QUARKSE1 = (1U << 15), + QUARKSE2 = (1U << 16), + SHFT1 = (1U << 17), + SHFT2 = (1U << 18), + SWAP = (1U << 19), + SP = (1U << 20), + SPX = (1U << 21) +} insn_subclass_t; + +/* Flags class. */ +typedef enum { + F_CLASS_NONE = 0, + + /* + * At most one flag from the set of flags can appear in the + * instruction. + */ + F_CLASS_OPTIONAL = (1 << 0), + + /* + * Exactly one from from the set of flags must appear in the + * instruction. + */ + F_CLASS_REQUIRED = (1 << 1), + + /* + * The conditional code can be extended over the standard variants + * via .extCondCode pseudo-op. + */ + F_CLASS_EXTEND = (1 << 2), + + /* Condition code flag. */ + F_CLASS_COND = (1 << 3), + + /* Write back mode. */ + F_CLASS_WB = (1 << 4), + + /* Data size. */ + F_CLASS_ZZ = (1 << 5), + + /* Implicit flag. */ + F_CLASS_IMPLICIT = (1 << 6), + + F_CLASS_F = (1 << 7), + + F_CLASS_DI = (1 << 8), + + F_CLASS_X = (1 << 9), + F_CLASS_D = (1 << 10), + +} flag_class_t; + +/* The opcode table is an array of struct arc_opcode. */ +struct arc_opcode { + /* The opcode name. */ + const char *name; + + /* + * The opcode itself. Those bits which will be filled in with + * operands are zeroes. + */ + unsigned long long opcode; + + /* + * The opcode mask. This is used by the disassembler. This is a + * mask containing ones indicating those bits which must match the + * opcode field, and zeroes indicating those bits which need not + * match (and are presumably filled in by operands). + */ + unsigned long long mask; + + /* + * One bit flags for the opcode. These are primarily used to + * indicate specific processors and environments support the + * instructions. The defined values are listed below. + */ + unsigned cpu; + + /* The instruction class. */ + insn_class_t insn_class; + + /* The instruction subclass. */ + insn_subclass_t subclass; + + /* + * An array of operand codes. Each code is an index into the + * operand table. They appear in the order which the operands must + * appear in assembly code, and are terminated by a zero. + */ + unsigned char operands[MAX_INSN_ARGS + 1]; + + /* + * An array of flag codes. Each code is an index into the flag + * table. They appear in the order which the flags must appear in + * assembly code, and are terminated by a zero. + */ + unsigned char flags[MAX_INSN_FLGS + 1]; +}; + +/* The operands table is an array of struct arc_operand. */ +struct arc_operand { + /* The number of bits in the operand. */ + unsigned int bits; + + /* How far the operand is left shifted in the instruction. */ + unsigned int shift; + + /* One bit syntax flags. */ + unsigned int flags; + + /* + * Extraction function. This is used by the disassembler. To + * extract this operand type from an instruction, check this + * field. + * + * If it is NULL, compute + * op = ((i) >> o->shift) & ((1 << o->bits) - 1); + * if ((o->flags & ARC_OPERAND_SIGNED) != 0 + * && (op & (1 << (o->bits - 1))) != 0) + * op -= 1 << o->bits; + * (i is the instruction, o is a pointer to this structure, and op + * is the result; this assumes twos complement arithmetic). + * + * If this field is not NULL, then simply call it with the + * instruction value. It will return the value of the operand. + * If the INVALID argument is not NULL, *INVALID will be set to + * TRUE if this operand type can not actually be extracted from + * this operand (i.e., the instruction does not match). If the + * operand is valid, *INVALID will not be changed. + */ + long long int (*extract) (unsigned long long instruction, + bool *invalid); +}; + +extern const struct arc_operand arc_operands[]; + +/* Values defined for the flags field of a struct arc_operand. */ + +/* + * This operand does not actually exist in the assembler input. This + * is used to support extended mnemonics, for which two operands + * fields are identical. The assembler should call the insert + * function with any op value. The disassembler should call the + * extract function, ignore the return value, and check the value + * placed in the invalid argument. + */ +#define ARC_OPERAND_FAKE 0x0001 + +/* This operand names an integer register. */ +#define ARC_OPERAND_IR 0x0002 + +/* This operand takes signed values. */ +#define ARC_OPERAND_SIGNED 0x0004 + +/* + * This operand takes unsigned values. This exists primarily so that + * a flags value of 0 can be treated as end-of-arguments. + */ +#define ARC_OPERAND_UNSIGNED 0x0008 + +/* This operand takes short immediate values. */ +#define ARC_OPERAND_SHIMM (ARC_OPERAND_SIGNED | ARC_OPERAND_UNSIGNED) + +/* This operand takes long immediate values. */ +#define ARC_OPERAND_LIMM 0x0010 + +/* This operand is identical like the previous one. */ +#define ARC_OPERAND_DUPLICATE 0x0020 + +/* This operand is PC relative. Used for internal relocs. */ +#define ARC_OPERAND_PCREL 0x0040 + +/* + * This operand is truncated. The truncation is done accordingly to + * operand alignment attribute. + */ +#define ARC_OPERAND_TRUNCATE 0x0080 + +/* This operand is 16bit aligned. */ +#define ARC_OPERAND_ALIGNED16 0x0100 + +/* This operand is 32bit aligned. */ +#define ARC_OPERAND_ALIGNED32 0x0200 + +/* + * This operand can be ignored by matching process if it is not + * present. + */ +#define ARC_OPERAND_IGNORE 0x0400 + +/* Don't check the range when matching. */ +#define ARC_OPERAND_NCHK 0x0800 + +/* Mark the braket possition. */ +#define ARC_OPERAND_BRAKET 0x1000 + +/* Mask for selecting the type for typecheck purposes. */ +#define ARC_OPERAND_TYPECHECK_MASK \ + (ARC_OPERAND_IR \ + | ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED \ + | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET) + +/* Macro to determine if an operand is a fake operand. */ +#define ARC_OPERAND_IS_FAKE(op) \ + ((operand->flags & ARC_OPERAND_FAKE) \ + && !(operand->flags & ARC_OPERAND_BRAKET)) + +/* The flags structure. */ +struct arc_flag_operand { + /* The flag name. */ + const char *name; + + /* The flag code. */ + unsigned code; + + /* The number of bits in the operand. */ + unsigned int bits; + + /* How far the operand is left shifted in the instruction. */ + unsigned int shift; + + /* Available for disassembler. */ + unsigned char favail; +}; + +extern const struct arc_flag_operand arc_flag_operands[]; + +/* The flag's class structure. */ +struct arc_flag_class { + /* Flag class. */ + flag_class_t flag_class; + + /* List of valid flags (codes). */ + unsigned flags[256]; +}; + +extern const struct arc_flag_class arc_flag_classes[]; + +/* Structure for special cases. */ +struct arc_flag_special { + /* Name of special case instruction. */ + const char *name; + + /* List of flags applicable for special case instruction. */ + unsigned flags[32]; +}; + +extern const struct arc_flag_special arc_flag_special_cases[]; +extern const unsigned arc_num_flag_special; + +const struct arc_opcode *arc_find_format(insn_t*, uint64_t, uint8_t, uint32_t); +unsigned int arc_insn_length(uint16_t, uint16_t); + +#endif diff --git a/target/arc/flags.def b/target/arc/flags.def new file mode 100644 index 0000000000..b6c3898698 --- /dev/null +++ b/target/arc/flags.def @@ -0,0 +1,85 @@ +/* + * QEMU ARC operands + * + * Copyright (c) 2020 Synopsys, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +ARC_FLAG(ALWAYS, "al", 0, 0, 0, 0) +ARC_FLAG(RA, "ra", 0, 0, 0, 0) +ARC_FLAG(EQUAL, "eq", 1, 5, 0, 1) +ARC_FLAG(ZERO, "z", 1, 5, 0, 0) +ARC_FLAG(NOTEQUAL, "ne", 2, 5, 0, 1) +ARC_FLAG(NOTZERO, "nz", 2, 5, 0, 0) +ARC_FLAG(POZITIVE, "p", 3, 5, 0, 1) +ARC_FLAG(PL, "pl", 3, 5, 0, 0) +ARC_FLAG(NEGATIVE, "n", 4, 5, 0, 1) +ARC_FLAG(MINUS, "mi", 4, 5, 0, 0) +ARC_FLAG(CARRY, "c", 5, 5, 0, 1) +ARC_FLAG(CARRYSET, "cs", 5, 5, 0, 0) +ARC_FLAG(LOWER, "lo", 5, 5, 0, 0) +ARC_FLAG(CARRYCLR, "cc", 6, 5, 0, 0) +ARC_FLAG(NOTCARRY, "nc", 6, 5, 0, 1) +ARC_FLAG(HIGHER, "hs", 6, 5, 0, 0) +ARC_FLAG(OVERFLOWSET, "vs", 7, 5, 0, 0) +ARC_FLAG(OVERFLOW, "v", 7, 5, 0, 1) +ARC_FLAG(NOTOVERFLOW, "nv", 8, 5, 0, 1) +ARC_FLAG(OVERFLOWCLR, "vc", 8, 5, 0, 0) +ARC_FLAG(GT, "gt", 9, 5, 0, 1) +ARC_FLAG(GE, "ge", 10, 5, 0, 1) +ARC_FLAG(LT, "lt", 11, 5, 0, 1) +ARC_FLAG(LE, "le", 12, 5, 0, 1) +ARC_FLAG(HI, "hi", 13, 5, 0, 1) +ARC_FLAG(LS, "ls", 14, 5, 0, 1) +ARC_FLAG(PNZ, "pnz", 15, 5, 0, 1) +ARC_FLAG(FLAG, "f", 1, 1, 15, 1) +ARC_FLAG(FFAKE, "f", 0, 0, 0, 1) +ARC_FLAG(ND, "nd", 0, 1, 5, 0) +ARC_FLAG(D, "d", 1, 1, 5, 1) +ARC_FLAG(DFAKE, "d", 0, 0, 0, 1) +ARC_FLAG(DNZ_ND, "nd", 0, 1, 16, 0) +ARC_FLAG(DNZ_D, "d", 1, 1, 16, 1) +ARC_FLAG(SIZEB1, "b", 1, 2, 1, 1) +ARC_FLAG(SIZEB7, "b", 1, 2, 7, 1) +ARC_FLAG(SIZEB17, "b", 1, 2, 17, 1) +ARC_FLAG(SIZEW1, "w", 2, 2, 1, 0) +ARC_FLAG(SIZEW7, "w", 2, 2, 7, 0) +ARC_FLAG(SIZEW17, "w", 2, 2, 17, 0) +ARC_FLAG(SIGN6, "x", 1, 1, 6, 1) +ARC_FLAG(SIGN16, "x", 1, 1, 16, 1) +ARC_FLAG(SIGNX, "x", 0, 0, 0, 1) +ARC_FLAG(A3, "a", 1, 2, 3, 0) +ARC_FLAG(A9, "a", 1, 2, 9, 0) +ARC_FLAG(A22, "a", 1, 2, 22, 0) +ARC_FLAG(AW3, "aw", 1, 2, 3, 1) +ARC_FLAG(AW9, "aw", 1, 2, 9, 1) +ARC_FLAG(AW22, "aw", 1, 2, 22, 1) +ARC_FLAG(AB3, "ab", 2, 2, 3, 1) +ARC_FLAG(AB9, "ab", 2, 2, 9, 1) +ARC_FLAG(AB22, "ab", 2, 2, 22, 1) +ARC_FLAG(AS3, "as", 3, 2, 3, 1) +ARC_FLAG(AS9, "as", 3, 2, 9, 1) +ARC_FLAG(AS22, "as", 3, 2, 22, 1) +ARC_FLAG(ASFAKE, "as", 3, 0, 0, 1) +ARC_FLAG(DI5, "di", 1, 1, 5, 1) +ARC_FLAG(DI11, "di", 1, 1, 11, 1) +ARC_FLAG(DI14, "di", 1, 1, 14, 1) +ARC_FLAG(DI15, "di", 1, 1, 15, 1) +ARC_FLAG(NT, "nt", 0, 1, 3, 1) +ARC_FLAG(T, "t", 1, 1, 3, 1) +ARC_FLAG(H1, "h", 2, 2, 1, 1) +ARC_FLAG(H7, "h", 2, 2, 7, 1) +ARC_FLAG(H17, "h", 2, 2, 17, 1) +ARC_FLAG(SIZED, "dd", 3, 0, 0, 0) +ARC_FLAG(NE, "ne", 0, 0, 0, 1) diff --git a/target/arc/operands.def b/target/arc/operands.def new file mode 100644 index 0000000000..34b15e0ec2 --- /dev/null +++ b/target/arc/operands.def @@ -0,0 +1,123 @@ +/* + * QEMU ARC operands + * + * Copyright (c) 2020 Synopsys, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +ARC_OPERAND(IGNORED, 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0) +ARC_OPERAND(RA, 6, 0, 0, ARC_OPERAND_IR, 0) +ARC_OPERAND(RA_CHK, 6, 0, 0, ARC_OPERAND_IR, 0) +ARC_OPERAND(RB, 6, 12, 0, ARC_OPERAND_IR, extract_rb) +ARC_OPERAND(RB_CHK, 6, 12, 0, ARC_OPERAND_IR, extract_rb) +ARC_OPERAND(RC, 6, 6, 0, ARC_OPERAND_IR, 0) +ARC_OPERAND(RBdup, 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, extract_rb) +ARC_OPERAND(RAD, 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, 0) +ARC_OPERAND(RCD, 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, 0) +ARC_OPERAND(RA16, 4, 0, 0, ARC_OPERAND_IR, extract_ras) +ARC_OPERAND(RA_S, 4, 0, 0, ARC_OPERAND_IR, extract_ras) +ARC_OPERAND(RB16, 4, 8, 0, ARC_OPERAND_IR, extract_rbs) +ARC_OPERAND(RB_S, 4, 8, 0, ARC_OPERAND_IR, extract_rbs) +ARC_OPERAND(RB16dup, 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, extract_rbs) +ARC_OPERAND(RB_Sdup, 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, extract_rbs) +ARC_OPERAND(RC16, 4, 5, 0, ARC_OPERAND_IR, extract_rcs) +ARC_OPERAND(RC_S, 4, 5, 0, ARC_OPERAND_IR, extract_rcs) +ARC_OPERAND(R6H, 6, 5, 0, ARC_OPERAND_IR, extract_rhv1) +ARC_OPERAND(R5H, 5, 5, 0, ARC_OPERAND_IR, extract_rhv2) +ARC_OPERAND(RH_S, 5, 5, 0, ARC_OPERAND_IR, extract_rhv2) +ARC_OPERAND(R5Hdup, 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, extract_rhv2) +ARC_OPERAND(RH_Sdup, 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, extract_rhv2) +ARC_OPERAND(RG, 5, 5, 0, ARC_OPERAND_IR, extract_g_s) +ARC_OPERAND(G_S, 5, 5, 0, ARC_OPERAND_IR, extract_g_s) +ARC_OPERAND(R0, 0, 0, 0, ARC_OPERAND_IR, extract_r0) +ARC_OPERAND(R0_S, 0, 0, 0, ARC_OPERAND_IR, extract_r0) +ARC_OPERAND(R1, 1, 0, 0, ARC_OPERAND_IR, extract_r1) +ARC_OPERAND(R1_S, 1, 0, 0, ARC_OPERAND_IR, extract_r1) +ARC_OPERAND(R2, 2, 0, 0, ARC_OPERAND_IR, extract_r2) +ARC_OPERAND(R2_S, 2, 0, 0, ARC_OPERAND_IR, extract_r2) +ARC_OPERAND(R3, 2, 0, 0, ARC_OPERAND_IR, extract_r3) +ARC_OPERAND(R3_S, 2, 0, 0, ARC_OPERAND_IR, extract_r3) +ARC_OPERAND(RSP, 5, 0, 0, ARC_OPERAND_IR, extract_sp) +ARC_OPERAND(SP_S, 5, 0, 0, ARC_OPERAND_IR, extract_sp) +ARC_OPERAND(SPdup, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, extract_sp) +ARC_OPERAND(SP_Sdup, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, extract_sp) +ARC_OPERAND(GP, 5, 0, 0, ARC_OPERAND_IR, extract_gp) +ARC_OPERAND(GP_S, 5, 0, 0, ARC_OPERAND_IR, extract_gp) +ARC_OPERAND(PCL_S, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, extract_pcl) +ARC_OPERAND(BLINK, 5, 0, 0, ARC_OPERAND_IR, extract_blink) +ARC_OPERAND(BLINK_S, 5, 0, 0, ARC_OPERAND_IR, extract_blink) +ARC_OPERAND(ILINK1, 5, 0, 0, ARC_OPERAND_IR, extract_ilink1) +ARC_OPERAND(ILINK2, 5, 0, 0, ARC_OPERAND_IR, extract_ilink2) +ARC_OPERAND(LIMM, 32, 0, 0, ARC_OPERAND_LIMM, 0) +ARC_OPERAND(LIMM_S, 32, 0, 0, ARC_OPERAND_LIMM, 0) +ARC_OPERAND(LIMMdup, 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, 0) +ARC_OPERAND(ZA, 0, 0, 0, ARC_OPERAND_UNSIGNED, 0) +ARC_OPERAND(ZB, 0, 0, 0, ARC_OPERAND_UNSIGNED, 0) +ARC_OPERAND(ZA_S, 0, 0, 0, ARC_OPERAND_UNSIGNED, 0) +ARC_OPERAND(ZB_S, 0, 0, 0, ARC_OPERAND_UNSIGNED, 0) +ARC_OPERAND(ZC_S, 0, 0, 0, ARC_OPERAND_UNSIGNED, 0) +ARC_OPERAND(RRANGE_EL, 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE, extract_rrange) +ARC_OPERAND(R13_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, extract_rrange) +ARC_OPERAND(FP_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, extract_fpel) +ARC_OPERAND(BLINK_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, extract_blinkel) +ARC_OPERAND(PCL_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, extract_pclel) +ARC_OPERAND(BRAKET, 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0) +ARC_OPERAND(BRAKETdup, 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0) +ARC_OPERAND(FKT_T, 1, 3, 0, ARC_OPERAND_FAKE, 0) +ARC_OPERAND(FKT_NT, 1, 3, 0, ARC_OPERAND_FAKE, 0) +ARC_OPERAND(UIMM6_20, 6, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm6_20) +ARC_OPERAND(UIMM6_20R, 6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, extract_uimm6_20) +ARC_OPERAND(SIMM12_20, 12, 0, 0, ARC_OPERAND_SIGNED, extract_simm12_20) +ARC_OPERAND(SIMM12_20R, 12, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL, extract_simm12_20) +ARC_OPERAND(UIMM12_20, 12, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm12_20) +ARC_OPERAND(SIMM3_5_S, 3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK, extract_simm3s) +ARC_OPERAND(UIMM7_A32_11_S, 7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, extract_uimm7_a32_11_s) +ARC_OPERAND(UIMM7_A32_11R_S, 7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL, extract_uimm7_a32_11_s) +ARC_OPERAND(UIMM7_9_S, 7, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm7_9_s) +ARC_OPERAND(UIMM3_13_S, 3, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm3_13_s) +ARC_OPERAND(UIMM3_13R_S, 3, 0, -UIMM3_13R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, extract_uimm3_13_s) +ARC_OPERAND(SIMM11_A32_7_S, 11, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, extract_simm11_a32_7_s) +ARC_OPERAND(UIMM6_13_S, 6, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm6_13_s) +ARC_OPERAND(UIMM5_11_S, 5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, extract_uimm5_11_s) +ARC_OPERAND(SIMM9_A16_8, 9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, extract_simm9_a16_8) +ARC_OPERAND(UIMM6_8, 6, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm6_8) +ARC_OPERAND(SIMM21_A16_5, 21, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm21_a16_5) +ARC_OPERAND(SIMM25_A16_5, 25, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm25_a16_5) +ARC_OPERAND(SIMM10_A16_7_S, 10, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm10_a16_7_s) +ARC_OPERAND(SIMM10_A16_7_Sbis, 10, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE, extract_simm10_a16_7_s) +ARC_OPERAND(SIMM7_A16_10_S, 7, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm7_a16_10_s) +ARC_OPERAND(SIMM21_A32_5, 21, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm21_a32_5) +ARC_OPERAND(SIMM25_A32_5, 25, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm25_a32_5) +ARC_OPERAND(SIMM13_A32_5_S, 13, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm13_a32_5_s) +ARC_OPERAND(SIMM8_A16_9_S, 8, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm8_a16_9_s) +ARC_OPERAND(UIMM10_6_S_JLIOFF, 12, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, extract_uimm10_6_s) +ARC_OPERAND(UIMM3_23, 3, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm3_23) +ARC_OPERAND(UIMM10_6_S, 10, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm10_6_s) +ARC_OPERAND(UIMM6_11_S, 6, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm6_11_s) +ARC_OPERAND(SIMM9_8, 9, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE, extract_simm9_8) +ARC_OPERAND(SIMM9_8R, 9, 0, -SIMM9_8R, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL, extract_simm9_8) +ARC_OPERAND(UIMM10_A32_8_S, 10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_uimm10_a32_8_s) +ARC_OPERAND(SIMM9_7_S, 9, 0, 0, ARC_OPERAND_SIGNED, extract_simm9_7_s) +ARC_OPERAND(UIMM6_A16_11_S, 6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, extract_uimm6_a16_11_s) +ARC_OPERAND(UIMM5_A32_11_S, 5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, extract_uimm5_a32_11_s) +ARC_OPERAND(SIMM11_A32_13_S, 11, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, extract_simm11_a32_13_s) +ARC_OPERAND(UIMM7_13_S, 7, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm7_13_s) +ARC_OPERAND(UIMM6_A16_21, 6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE, extract_uimm6_a16_21) +ARC_OPERAND(UIMM7_11_S, 7, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm7_11_s) +ARC_OPERAND(UIMM7_A16_20, 7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_uimm7_a16_20) +ARC_OPERAND(SIMM13_A16_20, 13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, extract_simm13_a16_20) +ARC_OPERAND(UIMM8_8_S, 8, 0, 0, ARC_OPERAND_UNSIGNED, extract_uimm8_8_s) +ARC_OPERAND(UIMM8_8R_S, 8, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, extract_uimm8_8_s) +ARC_OPERAND(W6, 6, 0, 0, ARC_OPERAND_SIGNED, extract_w6) +ARC_OPERAND(UIMM6_5_S, 6, 0, 0, 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[2.80.104.46]) by smtp.gmail.com with ESMTPSA id s188sm3115178wmf.45.2020.11.11.08.18.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2020 08:18:07 -0800 (PST) From: cupertinomiranda@gmail.com To: qemu-devel@nongnu.org Subject: [PATCH 03/15] arc: Opcode definitions table Date: Wed, 11 Nov 2020 16:17:46 +0000 Message-Id: <20201111161758.9636-4-cupertinomiranda@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201111161758.9636-1-cupertinomiranda@gmail.com> References: <20201111161758.9636-1-cupertinomiranda@gmail.com> MIME-Version: 1.0 X-Spam-Note: CRM114 run bypassed due to message size (1392621 bytes) X-Spam-Note: SpamAssassin run bypassed due to message size (1392621 bytes) X-Mailman-Approved-At: Wed, 11 Nov 2020 13:30:57 -0500 X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Claudiu Zissulescu , Cupertino Miranda , Shahab Vahedi , Shahab Vahedi , Cupertino Miranda , linux-snps-arc@lists.infradead.org, Claudiu Zissulescu Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Claudiu Zissulescu Signed-off-by: Claudiu Zissulescu --- target/arc/opcodes.def | 19976 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 19976 insertions(+) create mode 100644 target/arc/opcodes.def diff --git a/target/arc/opcodes.def b/target/arc/opcodes.def new file mode 100644 index 0000000000..ee831a4bb7 --- /dev/null +++ b/target/arc/opcodes.def @@ -0,0 +1,19976 @@ +/* + * ARC instruction defintions. + * Copyright (C) 2020 Free Software Foundation, Inc. + * + * Contributed by Claudiu Zissulescu (claziss@synopsys.com) + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the OPERAND_GNU OPERAND_General Public + * License as published by the Free Software Foundation; either + * version 3, or (at your option) any later version. + * + * It is distributed in the hope that it will be useful, but + * OPERAND_WITHOUT ANY OPERAND_WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the OPERAND_GNU OPERAND_General Public License for more + * details. + * + * You should have received a copy of the OPERAND_GNU OPERAND_General + * Public License along with this program; if not, write to the Free + * Software Foundation, Inc., 51 Franklin Street - Fifth Floor, + * Boston, MA 02110-1301, USA. + */ + +/* abs<.f> b,c 00100bbb00101111FBBBCCCCCC001001. */ +{ "abs", 0x202F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* abs<.f> 0,c 0010011000101111F111CCCCCC001001. */ +{ "abs", 0x262F7009, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* abs<.f> b,u6 00100bbb01101111FBBBuuuuuu001001. */ +{ "abs", 0x206F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* abs<.f> 0,u6 0010011001101111F111uuuuuu001001. */ +{ "abs", 0x266F7009, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* abs<.f> b,limm 00100bbb00101111FBBB111110001001. */ +{ "abs", 0x202F0F89, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* abs<.f> 0,limm 0010011000101111F111111110001001. */ +{ "abs", 0x262F7F89, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* abss<.f> b,c 00101bbb00101111FBBBCCCCCC000101. */ +{ "abss", 0x282F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* abss<.f> 0,c 0010111000101111F111CCCCCC000101. */ +{ "abss", 0x2E2F7005, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* abss<.f> b,u6 00101bbb01101111FBBBuuuuuu000101. */ +{ "abss", 0x286F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* abss<.f> 0,u6 0010111001101111F111uuuuuu000101. */ +{ "abss", 0x2E6F7005, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* abss<.f> b,limm 00101bbb00101111FBBB111110000101. */ +{ "abss", 0x282F0F85, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* abss<.f> 0,limm 0010111000101111F111111110000101. */ +{ "abss", 0x2E2F7F85, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* abssh<.f> b,c 00101bbb00101111FBBBCCCCCC000100. */ +{ "abssh", 0x282F0004, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { C_F }}, + +/* abssh<.f> 0,c 0010111000101111F111CCCCCC000100. */ +{ "abssh", 0x2E2F7004, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* abssh<.f> b,u6 00101bbb01101111FBBBuuuuuu000100. */ +{ "abssh", 0x286F0004, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { C_F }}, + +/* abssh<.f> 0,u6 0010111001101111F111uuuuuu000100. */ +{ "abssh", 0x2E6F7004, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* abssh<.f> b,limm 00101bbb00101111FBBB111110000100. */ +{ "abssh", 0x282F0F84, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { C_F }}, + +/* abssh<.f> 0,limm 0010111000101111F111111110000100. */ +{ "abssh", 0x2E2F7F84, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* abssw<.f> b,c 00101bbb00101111FBBBCCCCCC000100. */ +{ "abssw", 0x282F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* abssw<.f> 0,c 0010111000101111F111CCCCCC000100. */ +{ "abssw", 0x2E2F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* abssw<.f> b,u6 00101bbb01101111FBBBuuuuuu000100. */ +{ "abssw", 0x286F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* abssw<.f> 0,u6 0010111001101111F111uuuuuu000100. */ +{ "abssw", 0x2E6F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* abssw<.f> b,limm 00101bbb00101111FBBB111110000100. */ +{ "abssw", 0x282F0F84, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* abssw<.f> 0,limm 0010111000101111F111111110000100. */ +{ "abssw", 0x2E2F7F84, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* abs_s b,c 01111bbbccc10001. */ +{ "abs_s", 0x00007811, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, + +/* acm<.f> a,b,c 00110bbb00101000FBBBCCCCCCAAAAAA. */ +{ "acm", 0x30280000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* acm<.f><.cc> b,b,c 00110bbb11101000FBBBCCCCCC0QQQQQ. */ +{ "acm", 0x30E80000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* acm<.f> a,b,u6 00110bbb01101000FBBBuuuuuuAAAAAA. */ +{ "acm", 0x30680000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* acm<.f><.cc> b,b,u6 00110bbb11101000FBBBuuuuuu1QQQQQ. */ +{ "acm", 0x30E80020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* acm<.f> b,b,s12 00110bbb10101000FBBBssssssSSSSSS. */ +{ "acm", 0x30A80000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* acm<.f> a,limm,c 0011011000101000F111CCCCCCAAAAAA. */ +{ "acm", 0x36287000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* acm<.f> a,b,limm 00110bbb00101000FBBB111110AAAAAA. */ +{ "acm", 0x30280F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* acm<.f><.cc> b,b,limm 00110bbb11101000FBBB1111100QQQQQ. */ +{ "acm", 0x30E80F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* adc<.f> a,b,c 00100bbb00000001FBBBCCCCCCAAAAAA. */ +{ "adc", 0x20010000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* adc<.f> 0,b,c 00100bbb00000001FBBBCCCCCC111110. */ +{ "adc", 0x2001003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* adc<.f><.cc> b,b,c 00100bbb11000001FBBBCCCCCC0QQQQQ. */ +{ "adc", 0x20C10000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* adc<.f> a,b,u6 00100bbb01000001FBBBuuuuuuAAAAAA. */ +{ "adc", 0x20410000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* adc<.f> 0,b,u6 00100bbb01000001FBBBuuuuuu111110. */ +{ "adc", 0x2041003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* adc<.f><.cc> b,b,u6 00100bbb11000001FBBBuuuuuu1QQQQQ. */ +{ "adc", 0x20C10020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* adc<.f> b,b,s12 00100bbb10000001FBBBssssssSSSSSS. */ +{ "adc", 0x20810000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* adc<.f> a,limm,c 0010011000000001F111CCCCCCAAAAAA. */ +{ "adc", 0x26017000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* adc<.f> a,b,limm 00100bbb00000001FBBB111110AAAAAA. */ +{ "adc", 0x20010F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* adc<.f> 0,limm,c 0010011000000001F111CCCCCC111110. */ +{ "adc", 0x2601703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* adc<.f> 0,b,limm 00100bbb00000001FBBB111110111110. */ +{ "adc", 0x20010FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* adc<.f><.cc> b,b,limm 00100bbb11000001FBBB1111100QQQQQ. */ +{ "adc", 0x20C10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* adc<.f><.cc> 0,limm,c 0010011011000001F111CCCCCC0QQQQQ. */ +{ "adc", 0x26C17000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* adc<.f> a,limm,u6 0010011001000001F111uuuuuuAAAAAA. */ +{ "adc", 0x26417000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* adc<.f> 0,limm,u6 0010011001000001F111uuuuuu111110. */ +{ "adc", 0x2641703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* adc<.f><.cc> 0,limm,u6 0010011011000001F111uuuuuu1QQQQQ. */ +{ "adc", 0x26C17020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* adc<.f> 0,limm,s12 0010011010000001F111ssssssSSSSSS. */ +{ "adc", 0x26817000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* adc<.f> a,limm,limm 0010011000000001F111111110AAAAAA. */ +{ "adc", 0x26017F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* adc<.f> 0,limm,limm 0010011000000001F111111110111110. */ +{ "adc", 0x26017FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* adc<.f><.cc> 0,limm,limm 0010011011000001F1111111100QQQQQ. */ +{ "adc", 0x26C17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* adc<.f><.cc> 0,limm,limm 0010011011000001F1111111100QQQQQ */ +{ "adc", 0x26C17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* adc<.f> a,limm,limm 0010011000000001F111111110AAAAAA */ +{ "adc", 0x26017F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* adcs<.f><.cc> b,b,c 00101bbb11100110FBBBCCCCCC0QQQQQ */ +{ "adcs", 0x28E60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* adcs<.f> a,b,c 00101bbb00100110FBBBCCCCCCAAAAAA */ +{ "adcs", 0x28260000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* adcs<.f> 0,b,c 00101bbb00100110FBBBCCCCCC111110 */ +{ "adcs", 0x2826003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* adcs<.f> 0,b,u6 00101bbb01100110FBBBuuuuuu111110 */ +{ "adcs", 0x2866003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* adcs<.f> a,b,u6 00101bbb01100110FBBBuuuuuuAAAAAA */ +{ "adcs", 0x28660000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* adcs<.f><.cc> b,b,u6 00101bbb11100110FBBBuuuuuu1QQQQQ */ +{ "adcs", 0x28E60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* adcs<.f> b,b,s12 00101bbb10100110FBBBssssssSSSSSS */ +{ "adcs", 0x28A60000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* adcs<.f><.cc> b,b,limm 00101bbb11100110FBBB1111100QQQQQ */ +{ "adcs", 0x28E60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* adcs<.f><.cc> 0,limm,c 0010111011100110F111CCCCCC0QQQQQ */ +{ "adcs", 0x2EE67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* adcs<.f> a,b,limm 00101bbb00100110FBBB111110AAAAAA */ +{ "adcs", 0x28260F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* adcs<.f> 0,limm,c 0010111001100110F111CCCCCC111110 */ +{ "adcs", 0x2E66703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* adcs<.f> a,limm,c 0010111000100110F111CCCCCCAAAAAA */ +{ "adcs", 0x2E267000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* adcs<.f> 0,b,limm 00101bbb00100110FBBB111110111110 */ +{ "adcs", 0x28260FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* adcs<.f><.cc> 0,limm,u6 0010111011100110F111uuuuuu1QQQQQ */ +{ "adcs", 0x2EE67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* adcs<.f> 0,limm,u6 0010111001100110F111uuuuuu111110 */ +{ "adcs", 0x2E66703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* adcs<.f> a,limm,u6 0010111001100110F111uuuuuuAAAAAA */ +{ "adcs", 0x2E667000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* adcs<.f> 0,limm,s12 0010111010100110F111ssssssSSSSSS */ +{ "adcs", 0x2EA67000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* adcs<.f> 0,limm,limm 0010111000100110F111111110111110 */ +{ "adcs", 0x2E267FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* adcs<.f><.cc> 0,limm,limm 0010111011100110F1111111100QQQQQ */ +{ "adcs", 0x2EE67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* adcs<.f> a,limm,limm 0010111000100110F111111110AAAAAA */ +{ "adcs", 0x2E267F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* add<.f> a,b,c 00100bbb00000000FBBBCCCCCCAAAAAA. */ +{ "add", 0x20000000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* add<.f> 0,b,c 00100bbb00000000FBBBCCCCCC111110. */ +{ "add", 0x2000003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* add<.f><.cc> b,b,c 00100bbb11000000FBBBCCCCCC0QQQQQ. */ +{ "add", 0x20C00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. */ +{ "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* add<.f> 0,b,u6 00100bbb01000000FBBBuuuuuu111110. */ +{ "add", 0x2040003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. */ +{ "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* add<.f> b,b,s12 00100bbb10000000FBBBssssssSSSSSS. */ +{ "add", 0x20800000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* add<.f> a,limm,c 0010011000000000F111CCCCCCAAAAAA. */ +{ "add", 0x26007000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */ +{ "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* add<.f> 0,limm,c 0010011000000000F111CCCCCC111110. */ +{ "add", 0x2600703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* add<.f> 0,b,limm 00100bbb00000000FBBB111110111110. */ +{ "add", 0x20000FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */ +{ "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* add<.f><.cc> 0,limm,c 0010011011000000F111CCCCCC0QQQQQ. */ +{ "add", 0x26C07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* add<.f> a,limm,u6 0010011001000000F111uuuuuuAAAAAA. */ +{ "add", 0x26407000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* add<.f> 0,limm,u6 0010011001000000F111uuuuuu111110. */ +{ "add", 0x2640703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* add<.f><.cc> 0,limm,u6 0010011011000000F111uuuuuu1QQQQQ. */ +{ "add", 0x26C07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* add<.f> 0,limm,s12 0010011010000000F111ssssssSSSSSS. */ +{ "add", 0x26807000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* add<.f> a,limm,limm 0010011000000000F111111110AAAAAA. */ +{ "add", 0x26007F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* add<.f> 0,limm,limm 0010011000000000F111111110111110. */ +{ "add", 0x26007FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* add<.f><.cc> 0,limm,limm 0010011011000000F1111111100QQQQQ. */ +{ "add", 0x26C07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* add1<.f> a,b,c 00100bbb00010100FBBBCCCCCCAAAAAA. */ +{ "add1", 0x20140000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* add1<.f> 0,b,c 00100bbb00010100FBBBCCCCCC111110. */ +{ "add1", 0x2014003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* add1<.f><.cc> b,b,c 00100bbb11010100FBBBCCCCCC0QQQQQ. */ +{ "add1", 0x20D40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* add1<.f> a,b,u6 00100bbb01010100FBBBuuuuuuAAAAAA. */ +{ "add1", 0x20540000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* add1<.f> 0,b,u6 00100bbb01010100FBBBuuuuuu111110. */ +{ "add1", 0x2054003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* add1<.f><.cc> b,b,u6 00100bbb11010100FBBBuuuuuu1QQQQQ. */ +{ "add1", 0x20D40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* add1<.f> b,b,s12 00100bbb10010100FBBBssssssSSSSSS. */ +{ "add1", 0x20940000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* add1<.f> a,limm,c 0010011000010100F111CCCCCCAAAAAA. */ +{ "add1", 0x26147000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* add1<.f> a,b,limm 00100bbb00010100FBBB111110AAAAAA. */ +{ "add1", 0x20140F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* add1<.f> 0,limm,c 0010011000010100F111CCCCCC111110. */ +{ "add1", 0x2614703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* add1<.f> 0,b,limm 00100bbb00010100FBBB111110111110. */ +{ "add1", 0x20140FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* add1<.f><.cc> b,b,limm 00100bbb11010100FBBB1111100QQQQQ. */ +{ "add1", 0x20D40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* add1<.f><.cc> 0,limm,c 0010011011010100F111CCCCCC0QQQQQ. */ +{ "add1", 0x26D47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* add1<.f> a,limm,u6 0010011001010100F111uuuuuuAAAAAA. */ +{ "add1", 0x26547000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* add1<.f> 0,limm,u6 0010011001010100F111uuuuuu111110. */ +{ "add1", 0x2654703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* add1<.f><.cc> 0,limm,u6 0010011011010100F111uuuuuu1QQQQQ. */ +{ "add1", 0x26D47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* add1<.f> 0,limm,s12 0010011010010100F111ssssssSSSSSS. */ +{ "add1", 0x26947000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* add1<.f> a,limm,limm 0010011000010100F111111110AAAAAA. */ +{ "add1", 0x26147F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* add1<.f> 0,limm,limm 0010011000010100F111111110111110. */ +{ "add1", 0x26147FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* add1<.f><.cc> 0,limm,limm 0010011011010100F1111111100QQQQQ. */ +{ "add1", 0x26D47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* add1_s b,b,c 01111bbbccc10100. */ +{ "add1_s", 0x00007814, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, + +/* add2<.f> a,b,c 00100bbb00010101FBBBCCCCCCAAAAAA. */ +{ "add2", 0x20150000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* add2<.f> 0,b,c 00100bbb00010101FBBBCCCCCC111110. */ +{ "add2", 0x2015003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* add2<.f><.cc> b,b,c 00100bbb11010101FBBBCCCCCC0QQQQQ. */ +{ "add2", 0x20D50000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* add2<.f> a,b,u6 00100bbb01010101FBBBuuuuuuAAAAAA. */ +{ "add2", 0x20550000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* add2<.f> 0,b,u6 00100bbb01010101FBBBuuuuuu111110. */ +{ "add2", 0x2055003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* add2<.f><.cc> b,b,u6 00100bbb11010101FBBBuuuuuu1QQQQQ. */ +{ "add2", 0x20D50020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* add2<.f> b,b,s12 00100bbb10010101FBBBssssssSSSSSS. */ +{ "add2", 0x20950000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* add2<.f> a,limm,c 0010011000010101F111CCCCCCAAAAAA. */ +{ "add2", 0x26157000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* add2<.f> a,b,limm 00100bbb00010101FBBB111110AAAAAA. */ +{ "add2", 0x20150F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* add2<.f> 0,limm,c 0010011000010101F111CCCCCC111110. */ +{ "add2", 0x2615703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* add2<.f> 0,b,limm 00100bbb00010101FBBB111110111110. */ +{ "add2", 0x20150FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* add2<.f><.cc> b,b,limm 00100bbb11010101FBBB1111100QQQQQ. */ +{ "add2", 0x20D50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* add2<.f><.cc> 0,limm,c 0010011011010101F111CCCCCC0QQQQQ. */ +{ "add2", 0x26D57000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* add2<.f> a,limm,u6 0010011001010101F111uuuuuuAAAAAA. */ +{ "add2", 0x26557000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* add2<.f> 0,limm,u6 0010011001010101F111uuuuuu111110. */ +{ "add2", 0x2655703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* add2<.f><.cc> 0,limm,u6 0010011011010101F111uuuuuu1QQQQQ. */ +{ "add2", 0x26D57020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* add2<.f> 0,limm,s12 0010011010010101F111ssssssSSSSSS. */ +{ "add2", 0x26957000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* add2<.f> a,limm,limm 0010011000010101F111111110AAAAAA. */ +{ "add2", 0x26157F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* add2<.f> 0,limm,limm 0010011000010101F111111110111110. */ +{ "add2", 0x26157FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* add2<.f><.cc> 0,limm,limm 0010011011010101F1111111100QQQQQ. */ +{ "add2", 0x26D57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* add2_s b,b,c 01111bbbccc10101. */ +{ "add2_s", 0x00007815, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, + +/* add3<.f> a,b,c 00100bbb00010110FBBBCCCCCCAAAAAA. */ +{ "add3", 0x20160000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* add3<.f> 0,b,c 00100bbb00010110FBBBCCCCCC111110. */ +{ "add3", 0x2016003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* add3<.f><.cc> b,b,c 00100bbb11010110FBBBCCCCCC0QQQQQ. */ +{ "add3", 0x20D60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* add3<.f> a,b,u6 00100bbb01010110FBBBuuuuuuAAAAAA. */ +{ "add3", 0x20560000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* add3<.f> 0,b,u6 00100bbb01010110FBBBuuuuuu111110. */ +{ "add3", 0x2056003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* add3<.f><.cc> b,b,u6 00100bbb11010110FBBBuuuuuu1QQQQQ. */ +{ "add3", 0x20D60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* add3<.f> b,b,s12 00100bbb10010110FBBBssssssSSSSSS. */ +{ "add3", 0x20960000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* add3<.f> a,limm,c 0010011000010110F111CCCCCCAAAAAA. */ +{ "add3", 0x26167000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* add3<.f> a,b,limm 00100bbb00010110FBBB111110AAAAAA. */ +{ "add3", 0x20160F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* add3<.f> 0,limm,c 0010011000010110F111CCCCCC111110. */ +{ "add3", 0x2616703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* add3<.f> 0,b,limm 00100bbb00010110FBBB111110111110. */ +{ "add3", 0x20160FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* add3<.f><.cc> b,b,limm 00100bbb11010110FBBB1111100QQQQQ. */ +{ "add3", 0x20D60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* add3<.f><.cc> 0,limm,c 0010011011010110F111CCCCCC0QQQQQ. */ +{ "add3", 0x26D67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* add3<.f> a,limm,u6 0010011001010110F111uuuuuuAAAAAA. */ +{ "add3", 0x26567000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* add3<.f> 0,limm,u6 0010011001010110F111uuuuuu111110. */ +{ "add3", 0x2656703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* add3<.f><.cc> 0,limm,u6 0010011011010110F111uuuuuu1QQQQQ. */ +{ "add3", 0x26D67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* add3<.f> 0,limm,s12 0010011010010110F111ssssssSSSSSS. */ +{ "add3", 0x26967000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* add3<.f> a,limm,limm 0010011000010110F111111110AAAAAA. */ +{ "add3", 0x26167F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* add3<.f> 0,limm,limm 0010011000010110F111111110111110. */ +{ "add3", 0x26167FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* add3<.f><.cc> 0,limm,limm 0010011011010110F1111111100QQQQQ. */ +{ "add3", 0x26D67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* add3_s b,b,c 01111bbbccc10110. */ +{ "add3_s", 0x00007816, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, + +/* addqbs<.f> a,b,c 00110bbb00100100FBBBCCCCCCAAAAAA. */ +{ "addqbs", 0x30240000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* addqbs<.f><.cc> b,b,c 00110bbb11100100FBBBCCCCCC0QQQQQ. */ +{ "addqbs", 0x30E40000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* addqbs<.f> a,b,u6 00110bbb01100100FBBBuuuuuuAAAAAA. */ +{ "addqbs", 0x30640000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* addqbs<.f><.cc> b,b,u6 00110bbb11100100FBBBuuuuuu1QQQQQ. */ +{ "addqbs", 0x30E40020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* addqbs<.f> b,b,s12 00110bbb10100100FBBBssssssSSSSSS. */ +{ "addqbs", 0x30A40000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* addqbs<.f> a,limm,c 0011011000100100F111CCCCCCAAAAAA. */ +{ "addqbs", 0x36247000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* addqbs<.f> a,b,limm 00110bbb00100100FBBB111110AAAAAA. */ +{ "addqbs", 0x30240F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* addqbs<.f><.cc> b,b,limm 00110bbb11100100FBBB1111100QQQQQ. */ +{ "addqbs", 0x30E40F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* adds<.f> a,b,c 00101bbb00000110FBBBCCCCCCAAAAAA. */ +{ "adds", 0x28060000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* adds<.f> 0,b,c 00101bbb00000110FBBBCCCCCC111110. */ +{ "adds", 0x2806003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* adds<.f><.cc> b,b,c 00101bbb11000110FBBBCCCCCC0QQQQQ. */ +{ "adds", 0x28C60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* adds<.f> a,b,u6 00101bbb01000110FBBBuuuuuuAAAAAA. */ +{ "adds", 0x28460000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* adds<.f> 0,b,u6 00101bbb01000110FBBBuuuuuu111110. */ +{ "adds", 0x2846003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* adds<.f><.cc> b,b,u6 00101bbb11000110FBBBuuuuuu1QQQQQ. */ +{ "adds", 0x28C60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* adds<.f> b,b,s12 00101bbb10000110FBBBssssssSSSSSS. */ +{ "adds", 0x28860000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* adds<.f> a,limm,c 0010111000000110F111CCCCCCAAAAAA. */ +{ "adds", 0x2E067000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* adds<.f> a,b,limm 00101bbb00000110FBBB111110AAAAAA. */ +{ "adds", 0x28060F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* adds<.f> 0,limm,c 0010111000000110F111CCCCCC111110. */ +{ "adds", 0x2E06703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* adds<.f> 0,b,limm 00101bbb00000110FBBB111110111110. */ +{ "adds", 0x28060FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* adds<.f><.cc> b,b,limm 00101bbb11000110FBBB1111100QQQQQ. */ +{ "adds", 0x28C60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* adds<.f><.cc> 0,limm,c 0010111011000110F111CCCCCC0QQQQQ. */ +{ "adds", 0x2EC67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* adds<.f> a,limm,u6 0010111001000110F111uuuuuuAAAAAA. */ +{ "adds", 0x2E467000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* adds<.f> 0,limm,u6 0010111001000110F111uuuuuu111110. */ +{ "adds", 0x2E46703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* adds<.f><.cc> 0,limm,u6 0010111011000110F111uuuuuu1QQQQQ. */ +{ "adds", 0x2EC67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* adds<.f> 0,limm,s12 0010111010000110F111ssssssSSSSSS. */ +{ "adds", 0x2E867000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* adds<.f> a,limm,limm 0010111000000110F111111110AAAAAA. */ +{ "adds", 0x2E067F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* adds<.f> 0,limm,limm 0010111000000110F111111110111110. */ +{ "adds", 0x2E067FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* adds<.f><.cc> 0,limm,limm 0010111011000110F1111111100QQQQQ. */ +{ "adds", 0x2EC67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* addsdw<.f> a,b,c 00101bbb00101000FBBBCCCCCCAAAAAA. */ +{ "addsdw", 0x28280000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* addsdw<.f> 0,b,c 00101bbb00101000FBBBCCCCCC111110. */ +{ "addsdw", 0x2828003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* addsdw<.f><.cc> b,b,c 00101bbb11101000FBBBCCCCCC0QQQQQ. */ +{ "addsdw", 0x28E80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* addsdw<.f> a,b,u6 00101bbb01101000FBBBuuuuuuAAAAAA. */ +{ "addsdw", 0x28680000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* addsdw<.f> 0,b,u6 00101bbb01101000FBBBuuuuuu111110. */ +{ "addsdw", 0x2868003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* addsdw<.f><.cc> b,b,u6 00101bbb11101000FBBBuuuuuu1QQQQQ. */ +{ "addsdw", 0x28E80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* addsdw<.f> b,b,s12 00101bbb10101000FBBBssssssSSSSSS. */ +{ "addsdw", 0x28A80000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* addsdw<.f> a,limm,c 0010111000101000F111CCCCCCAAAAAA. */ +{ "addsdw", 0x2E287000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* addsdw<.f> a,b,limm 00101bbb00101000FBBB111110AAAAAA. */ +{ "addsdw", 0x28280F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* addsdw<.f> 0,limm,c 0010111000101000F111CCCCCC111110. */ +{ "addsdw", 0x2E28703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* addsdw<.f> 0,b,limm 00101bbb00101000FBBB111110111110. */ +{ "addsdw", 0x28280FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* addsdw<.f><.cc> b,b,limm 00101bbb11101000FBBB1111100QQQQQ. */ +{ "addsdw", 0x28E80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* addsdw<.f><.cc> 0,limm,c 0010111011101000F111CCCCCC0QQQQQ. */ +{ "addsdw", 0x2EE87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* addsdw<.f> a,limm,u6 0010111001101000F111uuuuuuAAAAAA. */ +{ "addsdw", 0x2E687000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* addsdw<.f> 0,limm,u6 0010111001101000F111uuuuuu111110. */ +{ "addsdw", 0x2E68703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* addsdw<.f><.cc> 0,limm,u6 0010111011101000F111uuuuuu1QQQQQ. */ +{ "addsdw", 0x2EE87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* addsdw<.f> 0,limm,s12 0010111010101000F111ssssssSSSSSS. */ +{ "addsdw", 0x2EA87000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* addsdw<.f> a,limm,limm 0010111000101000F111111110AAAAAA. */ +{ "addsdw", 0x2E287F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* addsdw<.f> 0,limm,limm 0010111000101000F111111110111110. */ +{ "addsdw", 0x2E287FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* addsdw<.f><.cc> 0,limm,limm 0010111011101000F1111111100QQQQQ. */ +{ "addsdw", 0x2EE87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* add_s a,b,c 01100bbbccc11aaa. */ +{ "add_s", 0x00006018, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA_S, OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, + +/* add_s b,b,h 01110bbbhhh00HHH. */ +{ "add_s", 0x00007000, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_R6H }, { 0 }}, + +/* add_s b,b,h 01110bbbhhh000HH. */ +{ "add_s", 0x00007000, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RH_S }, { 0 }}, + +/* add_s h,h,s3 01110ssshhh001HH. */ +{ "add_s", 0x00007004, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RH_S, OPERAND_RH_Sdup, OPERAND_SIMM3_5_S }, { 0 }}, + +/* add_s c,b,u3 01101bbbccc00uuu. */ +{ "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RC_S, OPERAND_RB_S, OPERAND_UIMM3_13_S }, { 0 }}, + +/* add_s OPERAND_R0,b,u6 01001bbb0UUU1uuu. */ +{ "add_s", 0x00004808, 0x0000F888, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, CD2, { OPERAND_R0_S, OPERAND_RB_S, OPERAND_UIMM6_13_S }, { 0 }}, + +/* add_s OPERAND_R1,b,u6 01001bbb1UUU1uuu. */ +{ "add_s", 0x00004888, 0x0000F888, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, CD2, { OPERAND_R1_S, OPERAND_RB_S, OPERAND_UIMM6_13_S }, { 0 }}, + +/* add_s b,sp,u7 11000bbb100uuuuu. */ +{ "add_s", 0x0000C080, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S }, { 0 }}, + +/* add_s b,b,u7 11100bbb0uuuuuuu. */ +{ "add_s", 0x0000E000, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM7_9_S }, { 0 }}, + +/* add_s SP,SP,u7 11000000101uuuuu. */ +{ "add_s", 0x0000C0A0, 0x0000FFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_SP_S, OPERAND_SP_Sdup, OPERAND_UIMM7_A32_11_S }, { 0 }}, + +/* add_s OPERAND_R0,GP,s11 1100111sssssssss. */ +{ "add_s", 0x0000CE00, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_R0_S, OPERAND_GP_S, OPERAND_SIMM11_A32_7_S }, { 0 }}, + +/* add_s b,b,limm 01110bbb11000111. */ +{ "add_s", 0x000070C7, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_LIMM_S }, { 0 }}, + +/* add_s b,b,limm 01110bbb11000011. */ +{ "add_s", 0x000070C3, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_LIMM_S }, { 0 }}, + +/* add_s 0,limm,s3 01110sss11000111. */ +{ "add_s", 0x000070C7, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA_S, OPERAND_LIMM_S, OPERAND_SIMM3_5_S }, { 0 }}, + +/* aex b,c 00100bbb00100111RBBBCCCCCCRRRRRR. */ +{ "aex", 0x20270000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, + +/* aex<.cc> b,c 00100bbb11100111RBBBCCCCCC0QQQQQ. */ +{ "aex", 0x20E70000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }}, + +/* aex b,u6 00100bbb01100111RBBBuuuuuuRRRRRR. */ +{ "aex", 0x20670000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, + +/* aex<.cc> b,u6 00100bbb11100111RBBBuuuuuu1QQQQQ. */ +{ "aex", 0x20E70020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_CC }}, + +/* aex b,s12 00100bbb10100111RBBBssssssSSSSSS. */ +{ "aex", 0x20A70000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, + +/* aex limm,c 0010011000100111R111CCCCCCRRRRRR. */ +{ "aex", 0x26277000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, + +/* aex b,limm 00100bbb00100111RBBB111110RRRRRR. */ +{ "aex", 0x20270F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, + +/* aex<.cc> limm,c 0010011011100111R111CCCCCC0QQQQQ. */ +{ "aex", 0x26E77000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }}, + +/* aex<.cc> b,limm 00100bbb11100111RBBB1111100QQQQQ. */ +{ "aex", 0x20E70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_CC }}, + +/* aex limm,u6 0010011001100111R111uuuuuuRRRRRR. */ +{ "aex", 0x26677000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, + +/* aex<.cc> limm,u6 0010011011100111R111uuuuuu1QQQQQ. */ +{ "aex", 0x26E77020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_CC }}, + +/* aex limm,s12 0010011010100111R111ssssssSSSSSS. */ +{ "aex", 0x26A77000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, + +/* aex limm,limm 0010011000100111R111111110RRRRRR. */ +{ "aex", 0x26277F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { 0 }}, + +/* aex<.cc> limm,limm 0010011011100111R1111111100QQQQQ. */ +{ "aex", 0x26E77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_CC }}, + +/* and<.f> a,b,c 00100bbb00000100FBBBCCCCCCAAAAAA. */ +{ "and", 0x20040000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* and<.f> 0,b,c 00100bbb00000100FBBBCCCCCC111110. */ +{ "and", 0x2004003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* and<.f><.cc> b,b,c 00100bbb11000100FBBBCCCCCC0QQQQQ. */ +{ "and", 0x20C40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* and<.f> a,b,u6 00100bbb01000100FBBBuuuuuuAAAAAA. */ +{ "and", 0x20440000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* and<.f> 0,b,u6 00100bbb01000100FBBBuuuuuu111110. */ +{ "and", 0x2044003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* and<.f><.cc> b,b,u6 00100bbb11000100FBBBuuuuuu1QQQQQ. */ +{ "and", 0x20C40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* and<.f> b,b,s12 00100bbb10000100FBBBssssssSSSSSS. */ +{ "and", 0x20840000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* and<.f> a,limm,c 0010011000000100F111CCCCCCAAAAAA. */ +{ "and", 0x26047000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* and<.f> a,b,limm 00100bbb00000100FBBB111110AAAAAA. */ +{ "and", 0x20040F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* and<.f> 0,limm,c 0010011000000100F111CCCCCC111110. */ +{ "and", 0x2604703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* and<.f> 0,b,limm 00100bbb00000100FBBB111110111110. */ +{ "and", 0x20040FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* and<.f><.cc> b,b,limm 00100bbb11000100FBBB1111100QQQQQ. */ +{ "and", 0x20C40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* and<.f><.cc> 0,limm,c 0010011011000100F111CCCCCC0QQQQQ. */ +{ "and", 0x26C47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* and<.f> a,limm,u6 0010011001000100F111uuuuuuAAAAAA. */ +{ "and", 0x26447000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* and<.f> 0,limm,u6 0010011001000100F111uuuuuu111110. */ +{ "and", 0x2644703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* and<.f><.cc> 0,limm,u6 0010011011000100F111uuuuuu1QQQQQ. */ +{ "and", 0x26C47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* and<.f> 0,limm,s12 0010011010000100F111ssssssSSSSSS. */ +{ "and", 0x26847000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* and<.f> a,limm,limm 0010011000000100F111111110AAAAAA. */ +{ "and", 0x26047F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* and<.f> 0,limm,limm 0010011000000100F111111110111110. */ +{ "and", 0x26047FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* and<.f><.cc> 0,limm,limm 0010011011000100F1111111100QQQQQ. */ +{ "and", 0x26C47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* and_s b,b,c 01111bbbccc00100. */ +{ "and_s", 0x00007804, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, + +/* asl<.f> b,c 00100bbb00101111FBBBCCCCCC000000. */ +{ "asl", 0x202F0000, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* asl<.f> 0,c 0010011000101111F111CCCCCC000000. */ +{ "asl", 0x262F7000, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* asl<.f> a,b,c 00101bbb00000000FBBBCCCCCCAAAAAA. */ +{ "asl", 0x28000000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* asl<.f> 0,b,c 00101bbb00000000FBBBCCCCCC111110. */ +{ "asl", 0x2800003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* asl<.f><.cc> b,b,c 00101bbb11000000FBBBCCCCCC0QQQQQ. */ +{ "asl", 0x28C00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* asl<.f> b,u6 00100bbb01101111FBBBuuuuuu000000. */ +{ "asl", 0x206F0000, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* asl<.f> 0,u6 0010011001101111F111uuuuuu000000. */ +{ "asl", 0x266F7000, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* asl<.f> a,b,u6 00101bbb01000000FBBBuuuuuuAAAAAA. */ +{ "asl", 0x28400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* asl<.f> 0,b,u6 00101bbb01000000FBBBuuuuuu111110. */ +{ "asl", 0x2840003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* asl<.f><.cc> b,b,u6 00101bbb11000000FBBBuuuuuu1QQQQQ. */ +{ "asl", 0x28C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* asl<.f> b,b,s12 00101bbb10000000FBBBssssssSSSSSS. */ +{ "asl", 0x28800000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* asl<.f> b,limm 00100bbb00101111FBBB111110000000. */ +{ "asl", 0x202F0F80, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* asl<.f> 0,limm 0010011000101111F111111110000000. */ +{ "asl", 0x262F7F80, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* asl<.f> a,limm,c 0010111000000000F111CCCCCCAAAAAA. */ +{ "asl", 0x2E007000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* asl<.f> a,b,limm 00101bbb00000000FBBB111110AAAAAA. */ +{ "asl", 0x28000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* asl<.f> 0,limm,c 0010111000000000F111CCCCCC111110. */ +{ "asl", 0x2E00703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* asl<.f> 0,b,limm 00101bbb00000000FBBB111110111110. */ +{ "asl", 0x28000FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* asl<.f><.cc> b,b,limm 00101bbb11000000FBBB1111100QQQQQ. */ +{ "asl", 0x28C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* asl<.f><.cc> 0,limm,c 0010111011000000F111CCCCCC0QQQQQ. */ +{ "asl", 0x2EC07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* asl<.f> a,limm,u6 0010111001000000F111uuuuuuAAAAAA. */ +{ "asl", 0x2E407000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* asl<.f> 0,limm,u6 0010111001000000F111uuuuuu111110. */ +{ "asl", 0x2E40703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* asl<.f><.cc> 0,limm,u6 0010111011000000F111uuuuuu1QQQQQ. */ +{ "asl", 0x2EC07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* asl<.f> 0,limm,s12 0010111010000000F111ssssssSSSSSS. */ +{ "asl", 0x2E807000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* asl<.f> a,limm,limm 0010111000000000F111111110AAAAAA. */ +{ "asl", 0x2E007F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* asl<.f> 0,limm,limm 0010111000000000F111111110111110. */ +{ "asl", 0x2E007FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* asl<.f><.cc> 0,limm,limm 0010111011000000F1111111100QQQQQ. */ +{ "asl", 0x2EC07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* aslacc c 00101000001011110000CCCCCC111111. */ +{ "aslacc", 0x282F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RC }, { 0 }}, + +/* aslacc u6 00101000011011110000uuuuuu111111. */ +{ "aslacc", 0x286F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_UIMM6_20 }, { 0 }}, + +/* asldw<.f> a,b,c 00101bbb00100001FBBBCCCCCCAAAAAA. */ +{ "asldw", 0x28210000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* asldw<.f> 0,b,c 00101bbb00100001FBBBCCCCCC111110. */ +{ "asldw", 0x2821003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* asldw<.f><.cc> b,b,c 00101bbb11100001FBBBCCCCCC0QQQQQ. */ +{ "asldw", 0x28E10000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* asldw<.f> a,b,u6 00101bbb01100001FBBBuuuuuuAAAAAA. */ +{ "asldw", 0x28610000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* asldw<.f> 0,b,u6 00101bbb01100001FBBBuuuuuu111110. */ +{ "asldw", 0x2861003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* asldw<.f><.cc> b,b,u6 00101bbb11100001FBBBuuuuuu1QQQQQ. */ +{ "asldw", 0x28E10020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* asldw<.f> b,b,s12 00101bbb10100001FBBBssssssSSSSSS. */ +{ "asldw", 0x28A10000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* asldw<.f> a,limm,c 0010111000100001F111CCCCCCAAAAAA. */ +{ "asldw", 0x2E217000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* asldw<.f> a,b,limm 00101bbb00100001FBBB111110AAAAAA. */ +{ "asldw", 0x28210F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* asldw<.f> 0,limm,c 0010111000100001F111CCCCCC111110. */ +{ "asldw", 0x2E21703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* asldw<.f> 0,b,limm 00101bbb00100001FBBB111110111110. */ +{ "asldw", 0x28210FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* asldw<.f><.cc> 0,limm,c 0010111011100001F111CCCCCC0QQQQQ. */ +{ "asldw", 0x2EE17000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* asldw<.f><.cc> b,b,limm 00101bbb11100001FBBB1111100QQQQQ. */ +{ "asldw", 0x28E10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* asldw<.f> a,limm,u6 0010111001100001F111uuuuuuAAAAAA. */ +{ "asldw", 0x2E617000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* asldw<.f> 0,limm,u6 0010111001100001F111uuuuuu111110. */ +{ "asldw", 0x2E61703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* asldw<.f><.cc> 0,limm,u6 0010111011100001F111uuuuuu1QQQQQ. */ +{ "asldw", 0x2EE17020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* asldw<.f> 0,limm,s12 0010111010100001F111ssssssSSSSSS. */ +{ "asldw", 0x2EA17000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* asldw<.f> a,limm,limm 0010111000100001F111111110AAAAAA. */ +{ "asldw", 0x2E217F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* asldw<.f> 0,limm,limm 0010111000100001F111111110111110. */ +{ "asldw", 0x2E217FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* asldw<.f><.cc> 0,limm,limm 0010111011100001F1111111100QQQQQ. */ +{ "asldw", 0x2EE17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* asls<.f> a,b,c 00101bbb00001010FBBBCCCCCCAAAAAA. */ +{ "asls", 0x280A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* asls<.f> 0,b,c 00101bbb00001010FBBBCCCCCC111110. */ +{ "asls", 0x280A003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* asls<.f><.cc> b,b,c 00101bbb11001010FBBBCCCCCC0QQQQQ. */ +{ "asls", 0x28CA0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* asls<.f> a,b,u6 00101bbb01001010FBBBuuuuuuAAAAAA. */ +{ "asls", 0x284A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* asls<.f> 0,b,u6 00101bbb01001010FBBBuuuuuu111110. */ +{ "asls", 0x284A003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* asls<.f><.cc> b,b,u6 00101bbb11001010FBBBuuuuuu1QQQQQ. */ +{ "asls", 0x28CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* asls<.f> b,b,s12 00101bbb10001010FBBBssssssSSSSSS. */ +{ "asls", 0x288A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* asls<.f> a,limm,c 0010111000001010F111CCCCCCAAAAAA. */ +{ "asls", 0x2E0A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* asls<.f> a,b,limm 00101bbb00001010FBBB111110AAAAAA. */ +{ "asls", 0x280A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* asls<.f> 0,limm,c 0010111000001010F111CCCCCC111110. */ +{ "asls", 0x2E0A703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* asls<.f> 0,b,limm 00101bbb00001010FBBB111110111110. */ +{ "asls", 0x280A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* asls<.f><.cc> b,b,limm 00101bbb11001010FBBB1111100QQQQQ. */ +{ "asls", 0x28CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* asls<.f><.cc> 0,limm,c 0010111011001010F111CCCCCC0QQQQQ. */ +{ "asls", 0x2ECA7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* asls<.f> a,limm,u6 0010111001001010F111uuuuuuAAAAAA. */ +{ "asls", 0x2E4A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* asls<.f> 0,limm,u6 0010111001001010F111uuuuuu111110. */ +{ "asls", 0x2E4A703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* asls<.f><.cc> 0,limm,u6 0010111011001010F111uuuuuu1QQQQQ. */ +{ "asls", 0x2ECA7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* asls<.f> 0,limm,s12 0010111010001010F111ssssssSSSSSS. */ +{ "asls", 0x2E8A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* asls<.f> a,limm,limm 0010111000001010F111111110AAAAAA. */ +{ "asls", 0x2E0A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* asls<.f> 0,limm,limm 0010111000001010F111111110111110. */ +{ "asls", 0x2E0A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* asls<.f><.cc> 0,limm,limm 0010111011001010F1111111100QQQQQ. */ +{ "asls", 0x2ECA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* aslsacc c 00101001001011110000CCCCCC111111. */ +{ "aslsacc", 0x292F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RC }, { 0 }}, + +/* aslsacc u6 00101001011011110000uuuuuu111111. */ +{ "aslsacc", 0x296F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_UIMM6_20 }, { 0 }}, + +/* aslsdw<.f> a,b,c 00101bbb00100100FBBBCCCCCCAAAAAA. */ +{ "aslsdw", 0x28240000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* aslsdw<.f> 0,b,c 00101bbb00100100FBBBCCCCCC111110. */ +{ "aslsdw", 0x2824003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* aslsdw<.f><.cc> b,b,c 00101bbb11100100FBBBCCCCCC0QQQQQ. */ +{ "aslsdw", 0x28E40000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* aslsdw<.f> a,b,u6 00101bbb01100100FBBBuuuuuuAAAAAA. */ +{ "aslsdw", 0x28640000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* aslsdw<.f> 0,b,u6 00101bbb01100100FBBBuuuuuu111110. */ +{ "aslsdw", 0x2864003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* aslsdw<.f><.cc> b,b,u6 00101bbb11100100FBBBuuuuuu1QQQQQ. */ +{ "aslsdw", 0x28E40020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* aslsdw<.f> b,b,s12 00101bbb10100100FBBBssssssSSSSSS. */ +{ "aslsdw", 0x28A40000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* aslsdw<.f> a,limm,c 0010111000100100F111CCCCCCAAAAAA. */ +{ "aslsdw", 0x2E247000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* aslsdw<.f> a,b,limm 00101bbb00100100FBBB111110AAAAAA. */ +{ "aslsdw", 0x28240F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* aslsdw<.f> 0,limm,c 0010111000100100F111CCCCCC111110. */ +{ "aslsdw", 0x2E24703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* aslsdw<.f> 0,b,limm 00101bbb00100100FBBB111110111110. */ +{ "aslsdw", 0x28240FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* aslsdw<.f><.cc> 0,limm,c 0010111011100100F111CCCCCC0QQQQQ. */ +{ "aslsdw", 0x2EE47000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* aslsdw<.f><.cc> b,b,limm 00101bbb11100100FBBB1111100QQQQQ. */ +{ "aslsdw", 0x28E40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* aslsdw<.f> a,limm,u6 0010111001100100F111uuuuuuAAAAAA. */ +{ "aslsdw", 0x2E647000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* aslsdw<.f> 0,limm,u6 0010111001100100F111uuuuuu111110. */ +{ "aslsdw", 0x2E64703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* aslsdw<.f><.cc> 0,limm,u6 0010111011100100F111uuuuuu1QQQQQ. */ +{ "aslsdw", 0x2EE47020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* aslsdw<.f> 0,limm,s12 0010111010100100F111ssssssSSSSSS. */ +{ "aslsdw", 0x2EA47000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* aslsdw<.f> a,limm,limm 0010111000100100F111111110AAAAAA. */ +{ "aslsdw", 0x2E247F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* aslsdw<.f> 0,limm,limm 0010111000100100F111111110111110. */ +{ "aslsdw", 0x2E247FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* aslsdw<.f><.cc> 0,limm,limm 0010111011100100F1111111100QQQQQ. */ +{ "aslsdw", 0x2EE47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* asl_s b,c 01111bbbccc11011. */ +{ "asl_s", 0x0000781B, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, + +/* asl_s b,b,c 01111bbbccc11000. */ +{ "asl_s", 0x00007818, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, + +/* asl_s c,b,u3 01101bbbccc10uuu. */ +{ "asl_s", 0x00006810, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RC_S, OPERAND_RB_S, OPERAND_UIMM3_13_S }, { 0 }}, + +/* asl_s b,b,u5 10111bbb000uuuuu. */ +{ "asl_s", 0x0000B800, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }}, + +/* asr<.f> b,c 00100bbb00101111FBBBCCCCCC000001. */ +{ "asr", 0x202F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* asr<.f> 0,c 0010011000101111F111CCCCCC000001. */ +{ "asr", 0x262F7001, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* asr<.f> a,b,c 00101bbb00000010FBBBCCCCCCAAAAAA. */ +{ "asr", 0x28020000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* asr<.f> 0,b,c 00101bbb00000010FBBBCCCCCC111110. */ +{ "asr", 0x2802003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* asr<.f><.cc> b,b,c 00101bbb11000010FBBBCCCCCC0QQQQQ. */ +{ "asr", 0x28C20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* asr<.f> b,u6 00100bbb01101111FBBBuuuuuu000001. */ +{ "asr", 0x206F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* asr<.f> 0,u6 0010011001101111F111uuuuuu000001. */ +{ "asr", 0x266F7001, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* asr<.f> a,b,u6 00101bbb01000010FBBBuuuuuuAAAAAA. */ +{ "asr", 0x28420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* asr<.f> 0,b,u6 00101bbb01000010FBBBuuuuuu111110. */ +{ "asr", 0x2842003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* asr<.f><.cc> b,b,u6 00101bbb11000010FBBBuuuuuu1QQQQQ. */ +{ "asr", 0x28C20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* asr<.f> b,b,s12 00101bbb10000010FBBBssssssSSSSSS. */ +{ "asr", 0x28820000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* asr<.f> b,limm 00100bbb00101111FBBB111110000001. */ +{ "asr", 0x202F0F81, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* asr<.f> 0,limm 0010011000101111F111111110000001. */ +{ "asr", 0x262F7F81, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* asr<.f> a,limm,c 0010111000000010F111CCCCCCAAAAAA. */ +{ "asr", 0x2E027000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* asr<.f> a,b,limm 00101bbb00000010FBBB111110AAAAAA. */ +{ "asr", 0x28020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* asr<.f> 0,limm,c 0010111000000010F111CCCCCC111110. */ +{ "asr", 0x2E02703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* asr<.f> 0,b,limm 00101bbb00000010FBBB111110111110. */ +{ "asr", 0x28020FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* asr<.f><.cc> b,b,limm 00101bbb11000010FBBB1111100QQQQQ. */ +{ "asr", 0x28C20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* asr<.f><.cc> 0,limm,c 0010111011000010F111CCCCCC0QQQQQ. */ +{ "asr", 0x2EC27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* asr<.f> a,limm,u6 0010111001000010F111uuuuuuAAAAAA. */ +{ "asr", 0x2E427000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* asr<.f> 0,limm,u6 0010111001000010F111uuuuuu111110. */ +{ "asr", 0x2E42703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* asr<.f><.cc> 0,limm,u6 0010111011000010F111uuuuuu1QQQQQ. */ +{ "asr", 0x2EC27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* asr<.f> 0,limm,s12 0010111010000010F111ssssssSSSSSS. */ +{ "asr", 0x2E827000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* asr<.f> a,limm,limm 0010111000000010F111111110AAAAAA. */ +{ "asr", 0x2E027F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* asr<.f> 0,limm,limm 0010111000000010F111111110111110. */ +{ "asr", 0x2E027FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* asr<.f><.cc> 0,limm,limm 0010111011000010F1111111100QQQQQ. */ +{ "asr", 0x2EC27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* asr16<.f> b,c 00101bbb00101111FBBBCCCCCC001100. */ +{ "asr16", 0x282F000C, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* asr16<.f> 0,c 0010111000101111F111CCCCCC001100. */ +{ "asr16", 0x2E2F700C, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* asr16<.f> b,u6 00101bbb01101111FBBBuuuuuu001100. */ +{ "asr16", 0x286F000C, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* asr16<.f> 0,u6 0010111001101111F111uuuuuu001100. */ +{ "asr16", 0x2E6F700C, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* asr16<.f> b,limm 00101bbb00101111FBBB111110001100. */ +{ "asr16", 0x282F0F8C, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* asr16<.f> 0,limm 0010111000101111F111111110001100. */ +{ "asr16", 0x2E2F7F8C, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* asr8<.f> b,c 00101bbb00101111FBBBCCCCCC001101. */ +{ "asr8", 0x282F000D, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* asr8<.f> 0,c 0010111000101111F111CCCCCC001101. */ +{ "asr8", 0x2E2F700D, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* asr8<.f> b,u6 00101bbb01101111FBBBuuuuuu001101. */ +{ "asr8", 0x286F000D, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* asr8<.f> 0,u6 0010111001101111F111uuuuuu001101. */ +{ "asr8", 0x2E6F700D, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* asr8<.f> b,limm 00101bbb00101111FBBB111110001101. */ +{ "asr8", 0x282F0F8D, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* asr8<.f> 0,limm 0010111000101111F111111110001101. */ +{ "asr8", 0x2E2F7F8D, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* asrdw<.f> a,b,c 00101bbb00100010FBBBCCCCCCAAAAAA. */ +{ "asrdw", 0x28220000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* asrdw<.f> 0,b,c 00101bbb00100010FBBBCCCCCC111110. */ +{ "asrdw", 0x2822003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* asrdw<.f><.cc> b,b,c 00101bbb11100010FBBBCCCCCC0QQQQQ. */ +{ "asrdw", 0x28E20000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* asrdw<.f> a,b,u6 00101bbb01100010FBBBuuuuuuAAAAAA. */ +{ "asrdw", 0x28620000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* asrdw<.f> 0,b,u6 00101bbb01100010FBBBuuuuuu111110. */ +{ "asrdw", 0x2862003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* asrdw<.f><.cc> b,b,u6 00101bbb11100010FBBBuuuuuu1QQQQQ. */ +{ "asrdw", 0x28E20020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* asrdw<.f> b,b,s12 00101bbb10100010FBBBssssssSSSSSS. */ +{ "asrdw", 0x28A20000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* asrdw<.f> a,limm,c 0010111000100010F111CCCCCCAAAAAA. */ +{ "asrdw", 0x2E227000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* asrdw<.f> a,b,limm 00101bbb00100010FBBB111110AAAAAA. */ +{ "asrdw", 0x28220F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* asrdw<.f> 0,limm,c 0010111000100010F111CCCCCC111110. */ +{ "asrdw", 0x2E22703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* asrdw<.f> 0,b,limm 00101bbb00100010FBBB111110111110. */ +{ "asrdw", 0x28220FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* asrdw<.f><.cc> 0,limm,c 0010111011100010F111CCCCCC0QQQQQ. */ +{ "asrdw", 0x2EE27000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* asrdw<.f><.cc> b,b,limm 00101bbb11100010FBBB1111100QQQQQ. */ +{ "asrdw", 0x28E20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* asrdw<.f> a,limm,u6 0010111001100010F111uuuuuuAAAAAA. */ +{ "asrdw", 0x2E627000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* asrdw<.f> 0,limm,u6 0010111001100010F111uuuuuu111110. */ +{ "asrdw", 0x2E62703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* asrdw<.f><.cc> 0,limm,u6 0010111011100010F111uuuuuu1QQQQQ. */ +{ "asrdw", 0x2EE27020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* asrdw<.f> 0,limm,s12 0010111010100010F111ssssssSSSSSS. */ +{ "asrdw", 0x2EA27000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* asrdw<.f> a,limm,limm 0010111000100010F111111110AAAAAA. */ +{ "asrdw", 0x2E227F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* asrdw<.f> 0,limm,limm 0010111000100010F111111110111110. */ +{ "asrdw", 0x2E227FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* asrdw<.f><.cc> 0,limm,limm 0010111011100010F1111111100QQQQQ. */ +{ "asrdw", 0x2EE27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* asrs<.f> a,b,c 00101bbb00001011FBBBCCCCCCAAAAAA. */ +{ "asrs", 0x280B0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* asrs<.f> 0,b,c 00101bbb00001011FBBBCCCCCC111110. */ +{ "asrs", 0x280B003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* asrs<.f><.cc> b,b,c 00101bbb11001011FBBBCCCCCC0QQQQQ. */ +{ "asrs", 0x28CB0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* asrs<.f> a,b,u6 00101bbb01001011FBBBuuuuuuAAAAAA. */ +{ "asrs", 0x284B0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* asrs<.f> 0,b,u6 00101bbb01001011FBBBuuuuuu111110. */ +{ "asrs", 0x284B003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* asrs<.f><.cc> b,b,u6 00101bbb11001011FBBBuuuuuu1QQQQQ. */ +{ "asrs", 0x28CB0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* asrs<.f> b,b,s12 00101bbb10001011FBBBssssssSSSSSS. */ +{ "asrs", 0x288B0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* asrs<.f> a,limm,c 0010111000001011F111CCCCCCAAAAAA. */ +{ "asrs", 0x2E0B7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* asrs<.f> a,b,limm 00101bbb00001011FBBB111110AAAAAA. */ +{ "asrs", 0x280B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* asrs<.f> 0,limm,c 0010111000001011F111CCCCCC111110. */ +{ "asrs", 0x2E0B703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* asrs<.f> 0,b,limm 00101bbb00001011FBBB111110111110. */ +{ "asrs", 0x280B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* asrs<.f><.cc> b,b,limm 00101bbb11001011FBBB1111100QQQQQ. */ +{ "asrs", 0x28CB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* asrs<.f><.cc> 0,limm,c 0010111011001011F111CCCCCC0QQQQQ. */ +{ "asrs", 0x2ECB7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* asrs<.f> a,limm,u6 0010111001001011F111uuuuuuAAAAAA. */ +{ "asrs", 0x2E4B7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* asrs<.f> 0,limm,u6 0010111001001011F111uuuuuu111110. */ +{ "asrs", 0x2E4B703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* asrs<.f><.cc> 0,limm,u6 0010111011001011F111uuuuuu1QQQQQ. */ +{ "asrs", 0x2ECB7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* asrs<.f> 0,limm,s12 0010111010001011F111ssssssSSSSSS. */ +{ "asrs", 0x2E8B7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* asrs<.f> a,limm,limm 0010111000001011F111111110AAAAAA. */ +{ "asrs", 0x2E0B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* asrs<.f> 0,limm,limm 0010111000001011F111111110111110. */ +{ "asrs", 0x2E0B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* asrs<.f><.cc> 0,limm,limm 0010111011001011F1111111100QQQQQ. */ +{ "asrs", 0x2ECB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* asrsdw<.f> a,b,c 00101bbb00100101FBBBCCCCCCAAAAAA. */ +{ "asrsdw", 0x28250000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* asrsdw<.f> 0,b,c 00101bbb00100101FBBBCCCCCC111110. */ +{ "asrsdw", 0x2825003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* asrsdw<.f><.cc> b,b,c 00101bbb11100101FBBBCCCCCC0QQQQQ. */ +{ "asrsdw", 0x28E50000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* asrsdw<.f> a,b,u6 00101bbb01100101FBBBuuuuuuAAAAAA. */ +{ "asrsdw", 0x28650000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* asrsdw<.f> 0,b,u6 00101bbb01100101FBBBuuuuuu111110. */ +{ "asrsdw", 0x2865003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* asrsdw<.f><.cc> b,b,u6 00101bbb11100101FBBBuuuuuu1QQQQQ. */ +{ "asrsdw", 0x28E50020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* asrsdw<.f> b,b,s12 00101bbb10100101FBBBssssssSSSSSS. */ +{ "asrsdw", 0x28A50000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* asrsdw<.f> a,limm,c 0010111000100101F111CCCCCCAAAAAA. */ +{ "asrsdw", 0x2E257000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* asrsdw<.f> a,b,limm 00101bbb00100101FBBB111110AAAAAA. */ +{ "asrsdw", 0x28250F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* asrsdw<.f> 0,limm,c 0010111000100101F111CCCCCC111110. */ +{ "asrsdw", 0x2E25703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* asrsdw<.f> 0,b,limm 00101bbb00100101FBBB111110111110. */ +{ "asrsdw", 0x28250FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* asrsdw<.f><.cc> 0,limm,c 0010111011100101F111CCCCCC0QQQQQ. */ +{ "asrsdw", 0x2EE57000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* asrsdw<.f><.cc> b,b,limm 00101bbb11100101FBBB1111100QQQQQ. */ +{ "asrsdw", 0x28E50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* asrsdw<.f> a,limm,u6 0010111001100101F111uuuuuuAAAAAA. */ +{ "asrsdw", 0x2E657000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* asrsdw<.f> 0,limm,u6 0010111001100101F111uuuuuu111110. */ +{ "asrsdw", 0x2E65703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* asrsdw<.f><.cc> 0,limm,u6 0010111011100101F111uuuuuu1QQQQQ. */ +{ "asrsdw", 0x2EE57020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* asrsdw<.f> 0,limm,s12 0010111010100101F111ssssssSSSSSS. */ +{ "asrsdw", 0x2EA57000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* asrsdw<.f> a,limm,limm 0010111000100101F111111110AAAAAA. */ +{ "asrsdw", 0x2E257F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* asrsdw<.f> 0,limm,limm 0010111000100101F111111110111110. */ +{ "asrsdw", 0x2E257FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* asrsdw<.f><.cc> 0,limm,limm 0010111011100101F1111111100QQQQQ. */ +{ "asrsdw", 0x2EE57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* asrsr<.f> a,b,c 00101bbb00001100FBBBCCCCCCAAAAAA. */ +{ "asrsr", 0x280C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* asrsr<.f> 0,b,c 00101bbb00001100FBBBCCCCCC111110. */ +{ "asrsr", 0x280C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* asrsr<.f><.cc> b,b,c 00101bbb11001100FBBBCCCCCC0QQQQQ. */ +{ "asrsr", 0x28CC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* asrsr<.f> a,b,u6 00101bbb01001100FBBBuuuuuuAAAAAA. */ +{ "asrsr", 0x284C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* asrsr<.f> 0,b,u6 00101bbb01001100FBBBuuuuuu111110. */ +{ "asrsr", 0x284C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* asrsr<.f><.cc> b,b,u6 00101bbb11001100FBBBuuuuuu1QQQQQ. */ +{ "asrsr", 0x28CC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* asrsr<.f> b,b,s12 00101bbb10001100FBBBssssssSSSSSS. */ +{ "asrsr", 0x288C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* asrsr<.f> a,limm,c 0010111000001100F111CCCCCCAAAAAA. */ +{ "asrsr", 0x2E0C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* asrsr<.f> a,b,limm 00101bbb00001100FBBB111110AAAAAA. */ +{ "asrsr", 0x280C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* asrsr<.f> 0,limm,c 0010111000001100F111CCCCCC111110. */ +{ "asrsr", 0x2E0C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* asrsr<.f> 0,b,limm 00101bbb00001100FBBB111110111110. */ +{ "asrsr", 0x280C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* asrsr<.f><.cc> b,b,limm 00101bbb11001100FBBB1111100QQQQQ. */ +{ "asrsr", 0x28CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* asrsr<.f><.cc> 0,limm,c 0010111011001100F111CCCCCC0QQQQQ. */ +{ "asrsr", 0x2ECC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* asrsr<.f> a,limm,u6 0010111001001100F111uuuuuuAAAAAA. */ +{ "asrsr", 0x2E4C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* asrsr<.f> 0,limm,u6 0010111001001100F111uuuuuu111110. */ +{ "asrsr", 0x2E4C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* asrsr<.f><.cc> 0,limm,u6 0010111011001100F111uuuuuu1QQQQQ. */ +{ "asrsr", 0x2ECC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* asrsr<.f> 0,limm,s12 0010111010001100F111ssssssSSSSSS. */ +{ "asrsr", 0x2E8C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* asrsr<.f> a,limm,limm 0010111000001100F111111110AAAAAA. */ +{ "asrsr", 0x2E0C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* asrsr<.f> 0,limm,limm 0010111000001100F111111110111110. */ +{ "asrsr", 0x2E0C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* asrsr<.f><.cc> 0,limm,limm 0010111011001100F1111111100QQQQQ. */ +{ "asrsr", 0x2ECC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* asr_s b,c 01111bbbccc11100. */ +{ "asr_s", 0x0000781C, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, + +/* asr_s b,b,c 01111bbbccc11010. */ +{ "asr_s", 0x0000781A, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, + +/* asr_s c,b,u3 01101bbbccc11uuu. */ +{ "asr_s", 0x00006818, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RC_S, OPERAND_RB_S, OPERAND_UIMM3_13_S }, { 0 }}, + +/* asr_s b,b,u5 10111bbb010uuuuu. */ +{ "asr_s", 0x0000B840, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }}, + +/* avgqb<.f> a,b,c 00110bbb00100011FBBBCCCCCCAAAAAA. */ +{ "avgqb", 0x30230000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* avgqb<.f><.cc> b,b,c 00110bbb11100011FBBBCCCCCC0QQQQQ. */ +{ "avgqb", 0x30E30000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* avgqb<.f> a,b,u6 00110bbb01100011FBBBuuuuuuAAAAAA. */ +{ "avgqb", 0x30630000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* avgqb<.f><.cc> b,b,u6 00110bbb11100011FBBBuuuuuu1QQQQQ. */ +{ "avgqb", 0x30E30020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* avgqb<.f> b,b,s12 00110bbb10100011FBBBssssssSSSSSS. */ +{ "avgqb", 0x30A30000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* avgqb<.f> a,limm,c 0011011000100011F111CCCCCCAAAAAA. */ +{ "avgqb", 0x36237000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* avgqb<.f> a,b,limm 00110bbb00100011FBBB111110AAAAAA. */ +{ "avgqb", 0x30230F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* avgqb<.f><.cc> b,b,limm 00110bbb11100011FBBB1111100QQQQQ. */ +{ "avgqb", 0x30E30F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */ +{ "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { OPERAND_SIMM25_A16_5 }, { C_D }}, + +/* b<.d> s21 00000ssssssssss0SSSSSSSSSSNQQQQQ. */ +{ "b", 0x00000000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { OPERAND_SIMM21_A16_5 }, { C_CC, C_D }}, + +/* bbit0<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01110. */ +{ "bbit0", 0x0801000E, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT0, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D }}, + +/* bbit0<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y110. */ +{ "bbit0", 0x08010006, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT0, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_T }}, + +/* bbit0<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11110. */ +{ "bbit0", 0x0801001E, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT0, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D }}, + +/* bbit0<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y110. */ +{ "bbit0", 0x08010016, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT0, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_T }}, + +/* bbit0 b,limm,s9 00001bbbsssssss1SBBB111110001110. */ +{ "bbit0", 0x08010F8E, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT0, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { 0 }}, + +/* bbit0 limm,c,s9 00001110sssssss1S111CCCCCC001110. */ +{ "bbit0", 0x0E01700E, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT0, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { 0 }}, + +/* bbit0<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y110. */ +{ "bbit0", 0x08010F86, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT0, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_T }}, + +/* bbit0<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y110. */ +{ "bbit0", 0x0E017006, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT0, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_T }}, + +/* bbit0 limm,u6,s9 00001110sssssss1S111uuuuuu011110. */ +{ "bbit0", 0x0E01701E, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT0, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { 0 }}, + +/* bbit0<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y110. */ +{ "bbit0", 0x0E017016, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT0, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_T }}, + +/* bbit0 limm,limm,s9 00001110sssssss1S111111110001110. */ +{ "bbit0", 0x0E017F8E, 0xFF017FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT0, COND, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { 0 }}, + +/* bbit0<.T> limm,limm,s9 00001110sssssss1S11111111000Y110. */ +{ "bbit0", 0x0E017F86, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT0, COND, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_T }}, + +/* bbit1<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01111. */ +{ "bbit1", 0x0801000F, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT1, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D }}, + +/* bbit1<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y111. */ +{ "bbit1", 0x08010007, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT1, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_T }}, + +/* bbit1<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11111. */ +{ "bbit1", 0x0801001F, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT1, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D }}, + +/* bbit1<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y111. */ +{ "bbit1", 0x08010017, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT1, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_T }}, + +/* bbit1 b,limm,s9 00001bbbsssssss1SBBB111110001111. */ +{ "bbit1", 0x08010F8F, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT1, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { 0 }}, + +/* bbit1 limm,c,s9 00001110sssssss1S111CCCCCC001111. */ +{ "bbit1", 0x0E01700F, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT1, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { 0 }}, + +/* bbit1<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y111. */ +{ "bbit1", 0x08010F87, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT1, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_T }}, + +/* bbit1<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y111. */ +{ "bbit1", 0x0E017007, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT1, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_T }}, + +/* bbit1 limm,u6,s9 00001110sssssss1S111uuuuuu011111. */ +{ "bbit1", 0x0E01701F, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT1, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { 0 }}, + +/* bbit1<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y111. */ +{ "bbit1", 0x0E017017, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT1, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_T }}, + +/* bbit1 limm,limm,s9 00001110sssssss1S111111110001111. */ +{ "bbit1", 0x0E017F8F, 0xFF017FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BBIT1, COND, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { 0 }}, + +/* bbit1<.T> limm,limm,s9 00001110sssssss1S11111111000Y111. */ +{ "bbit1", 0x0E017F87, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BBIT1, COND, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_T }}, + +/* bclr<.f> a,b,c 00100bbb00010000FBBBCCCCCCAAAAAA. */ +{ "bclr", 0x20100000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* bclr<.f> 0,b,c 00100bbb00010000FBBBCCCCCC111110. */ +{ "bclr", 0x2010003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* bclr<.f><.cc> b,b,c 00100bbb11010000FBBBCCCCCC0QQQQQ. */ +{ "bclr", 0x20D00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* bclr<.f> a,b,u6 00100bbb01010000FBBBuuuuuuAAAAAA. */ +{ "bclr", 0x20500000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* bclr<.f> 0,b,u6 00100bbb01010000FBBBuuuuuu111110. */ +{ "bclr", 0x2050003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* bclr<.f><.cc> b,b,u6 00100bbb11010000FBBBuuuuuu1QQQQQ. */ +{ "bclr", 0x20D00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* bclr<.f> b,b,s12 00100bbb10010000FBBBssssssSSSSSS. */ +{ "bclr", 0x20900000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* bclr<.f> a,limm,c 0010011000010000F111CCCCCCAAAAAA. */ +{ "bclr", 0x26107000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* bclr<.f> a,b,limm 00100bbb00010000FBBB111110AAAAAA. */ +{ "bclr", 0x20100F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* bclr<.f> 0,limm,c 0010011000010000F111CCCCCC111110. */ +{ "bclr", 0x2610703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* bclr<.f> 0,b,limm 00100bbb00010000FBBB111110111110. */ +{ "bclr", 0x20100FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* bclr<.f><.cc> b,b,limm 00100bbb11010000FBBB1111100QQQQQ. */ +{ "bclr", 0x20D00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* bclr<.f><.cc> 0,limm,c 0010011011010000F111CCCCCC0QQQQQ. */ +{ "bclr", 0x26D07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* bclr<.f> a,limm,u6 0010011001010000F111uuuuuuAAAAAA. */ +{ "bclr", 0x26507000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* bclr<.f> 0,limm,u6 0010011001010000F111uuuuuu111110. */ +{ "bclr", 0x2650703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* bclr<.f><.cc> 0,limm,u6 0010011011010000F111uuuuuu1QQQQQ. */ +{ "bclr", 0x26D07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* bclr<.f> 0,limm,s12 0010011010010000F111ssssssSSSSSS. */ +{ "bclr", 0x26907000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* bclr<.f> a,limm,limm 0010011000010000F111111110AAAAAA. */ +{ "bclr", 0x26107F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* bclr<.f> 0,limm,limm 0010011000010000F111111110111110. */ +{ "bclr", 0x26107FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* bclr<.f><.cc> 0,limm,limm 0010011011010000F1111111100QQQQQ. */ +{ "bclr", 0x26D07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* bclr_s b,b,u5 10111bbb101uuuuu. */ +{ "bclr_s", 0x0000B8A0, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }}, + +/* beq_s s10 1111001sssssssss. */ +{ "beq_s", 0x0000F200, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM10_A16_7_S }, { C_CC_EQ }}, + +/* bge_s s7 1111011001ssssss. */ +{ "bge_s", 0x0000F640, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_GE }}, + +/* bgt_s s7 1111011000ssssss. */ +{ "bgt_s", 0x0000F600, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_GT }}, + +/* bhi_s s7 1111011100ssssss. */ +{ "bhi_s", 0x0000F700, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_HI }}, + +/* bhs_s s7 1111011101ssssss. */ +{ "bhs_s", 0x0000F740, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_HS }}, + +/* bi c 00100RRR001001000RRRCCCCCCRRRRRR. */ +{ "bi", 0x20240000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BI, CD1, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, + +/* bi limm 00100RRR001001000RRR111110RRRRRR. */ +{ "bi", 0x20240F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BI, CD1, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, + +/* bic<.f> a,b,c 00100bbb00000110FBBBCCCCCCAAAAAA. */ +{ "bic", 0x20060000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* bic<.f> 0,b,c 00100bbb00000110FBBBCCCCCC111110. */ +{ "bic", 0x2006003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* bic<.f><.cc> b,b,c 00100bbb11000110FBBBCCCCCC0QQQQQ. */ +{ "bic", 0x20C60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* bic<.f> a,b,u6 00100bbb01000110FBBBuuuuuuAAAAAA. */ +{ "bic", 0x20460000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* bic<.f> 0,b,u6 00100bbb01000110FBBBuuuuuu111110. */ +{ "bic", 0x2046003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* bic<.f><.cc> b,b,u6 00100bbb11000110FBBBuuuuuu1QQQQQ. */ +{ "bic", 0x20C60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* bic<.f> b,b,s12 00100bbb10000110FBBBssssssSSSSSS. */ +{ "bic", 0x20860000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* bic<.f> a,limm,c 0010011000000110F111CCCCCCAAAAAA. */ +{ "bic", 0x26067000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* bic<.f> a,b,limm 00100bbb00000110FBBB111110AAAAAA. */ +{ "bic", 0x20060F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* bic<.f> 0,limm,c 0010011000000110F111CCCCCC111110. */ +{ "bic", 0x2606703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* bic<.f> 0,b,limm 00100bbb00000110FBBB111110111110. */ +{ "bic", 0x20060FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* bic<.f><.cc> b,b,limm 00100bbb11000110FBBB1111100QQQQQ. */ +{ "bic", 0x20C60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* bic<.f><.cc> 0,limm,c 0010011011000110F111CCCCCC0QQQQQ. */ +{ "bic", 0x26C67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* bic<.f> a,limm,u6 0010011001000110F111uuuuuuAAAAAA. */ +{ "bic", 0x26467000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* bic<.f> 0,limm,u6 0010011001000110F111uuuuuu111110. */ +{ "bic", 0x2646703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* bic<.f><.cc> 0,limm,u6 0010011011000110F111uuuuuu1QQQQQ. */ +{ "bic", 0x26C67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* bic<.f> 0,limm,s12 0010011010000110F111ssssssSSSSSS. */ +{ "bic", 0x26867000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* bic<.f> a,limm,limm 0010011000000110F111111110AAAAAA. */ +{ "bic", 0x26067F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* bic<.f> 0,limm,limm 0010011000000110F111111110111110. */ +{ "bic", 0x26067FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* bic<.f><.cc> 0,limm,limm 0010011011000110F1111111100QQQQQ. */ +{ "bic", 0x26C67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* bic_s b,b,c 01111bbbccc00110. */ +{ "bic_s", 0x00007806, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, + +/* bih c 00100RRR001001010RRRCCCCCCRRRRRR. */ +{ "bih", 0x20250000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BIH, CD1, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, + +/* bih limm 00100RRR001001010RRR111110RRRRRR. */ +{ "bih", 0x20250F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BIH, CD1, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, + +/* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */ +{ "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { OPERAND_SIMM25_A32_5 }, { C_D }}, + +/* bl<.cc><.d> s21 00001sssssssss00SSSSSSSSSSNQQQQQ. */ +{ "bl", 0x08000000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { OPERAND_SIMM21_A32_5 }, { C_CC, C_D }}, + +/* ble_s s7 1111011011ssssss. */ +{ "ble_s", 0x0000F6C0, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_LE }}, + +/* blo_s s7 1111011110ssssss. */ +{ "blo_s", 0x0000F780, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_LO }}, + +/* bls_s s7 1111011111ssssss. */ +{ "bls_s", 0x0000F7C0, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_LS }}, + +/* blt_s s7 1111011010ssssss. */ +{ "blt_s", 0x0000F680, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM7_A16_10_S }, { C_CC_LT }}, + +/* bl_s s13 11111sssssssssss. */ +{ "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { OPERAND_SIMM13_A32_5_S }, { 0 }}, + +/* bmsk<.f> a,b,c 00100bbb00010011FBBBCCCCCCAAAAAA. */ +{ "bmsk", 0x20130000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* bmsk<.f> 0,b,c 00100bbb00010011FBBBCCCCCC111110. */ +{ "bmsk", 0x2013003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* bmsk<.f><.cc> b,b,c 00100bbb11010011FBBBCCCCCC0QQQQQ. */ +{ "bmsk", 0x20D30000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* bmsk<.f> a,b,u6 00100bbb01010011FBBBuuuuuuAAAAAA. */ +{ "bmsk", 0x20530000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* bmsk<.f> 0,b,u6 00100bbb01010011FBBBuuuuuu111110. */ +{ "bmsk", 0x2053003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* bmsk<.f><.cc> b,b,u6 00100bbb11010011FBBBuuuuuu1QQQQQ. */ +{ "bmsk", 0x20D30020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* bmsk<.f> b,b,s12 00100bbb10010011FBBBssssssSSSSSS. */ +{ "bmsk", 0x20930000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* bmsk<.f> a,limm,c 0010011000010011F111CCCCCCAAAAAA. */ +{ "bmsk", 0x26137000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* bmsk<.f> a,b,limm 00100bbb00010011FBBB111110AAAAAA. */ +{ "bmsk", 0x20130F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* bmsk<.f> 0,limm,c 0010011000010011F111CCCCCC111110. */ +{ "bmsk", 0x2613703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* bmsk<.f> 0,b,limm 00100bbb00010011FBBB111110111110. */ +{ "bmsk", 0x20130FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* bmsk<.f><.cc> b,b,limm 00100bbb11010011FBBB1111100QQQQQ. */ +{ "bmsk", 0x20D30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* bmsk<.f><.cc> 0,limm,c 0010011011010011F111CCCCCC0QQQQQ. */ +{ "bmsk", 0x26D37000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* bmsk<.f> a,limm,u6 0010011001010011F111uuuuuuAAAAAA. */ +{ "bmsk", 0x26537000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* bmsk<.f> 0,limm,u6 0010011001010011F111uuuuuu111110. */ +{ "bmsk", 0x2653703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* bmsk<.f><.cc> 0,limm,u6 0010011011010011F111uuuuuu1QQQQQ. */ +{ "bmsk", 0x26D37020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* bmsk<.f> 0,limm,s12 0010011010010011F111ssssssSSSSSS. */ +{ "bmsk", 0x26937000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* bmsk<.f> a,limm,limm 0010011000010011F111111110AAAAAA. */ +{ "bmsk", 0x26137F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* bmsk<.f> 0,limm,limm 0010011000010011F111111110111110. */ +{ "bmsk", 0x26137FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* bmsk<.f><.cc> 0,limm,limm 0010011011010011F1111111100QQQQQ. */ +{ "bmsk", 0x26D37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* bmskn<.f> a,b,c 00100bbb00101100FBBBCCCCCCAAAAAA. */ +{ "bmskn", 0x202C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* bmskn<.f> 0,b,c 00100bbb00101100FBBBCCCCCC111110. */ +{ "bmskn", 0x202C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* bmskn<.f><.cc> b,b,c 00100bbb11101100FBBBCCCCCC0QQQQQ. */ +{ "bmskn", 0x20EC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* bmskn<.f> a,b,u6 00100bbb01101100FBBBuuuuuuAAAAAA. */ +{ "bmskn", 0x206C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* bmskn<.f> 0,b,u6 00100bbb01101100FBBBuuuuuu111110. */ +{ "bmskn", 0x206C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* bmskn<.f><.cc> b,b,u6 00100bbb11101100FBBBuuuuuu1QQQQQ. */ +{ "bmskn", 0x20EC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* bmskn<.f> b,b,s12 00100bbb10101100FBBBssssssSSSSSS. */ +{ "bmskn", 0x20AC0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* bmskn<.f> a,limm,c 0010011000101100F111CCCCCCAAAAAA. */ +{ "bmskn", 0x262C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* bmskn<.f> a,b,limm 00100bbb00101100FBBB111110AAAAAA. */ +{ "bmskn", 0x202C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* bmskn<.f> 0,limm,c 0010011000101100F111CCCCCC111110. */ +{ "bmskn", 0x262C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* bmskn<.f> 0,b,limm 00100bbb00101100FBBB111110111110. */ +{ "bmskn", 0x202C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* bmskn<.f><.cc> b,b,limm 00100bbb11101100FBBB1111100QQQQQ. */ +{ "bmskn", 0x20EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* bmskn<.f><.cc> 0,limm,c 0010011011101100F111CCCCCC0QQQQQ. */ +{ "bmskn", 0x26EC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* bmskn<.f> a,limm,u6 0010011001101100F111uuuuuuAAAAAA. */ +{ "bmskn", 0x266C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* bmskn<.f> 0,limm,u6 0010011001101100F111uuuuuu111110. */ +{ "bmskn", 0x266C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* bmskn<.f><.cc> 0,limm,u6 0010011011101100F111uuuuuu1QQQQQ. */ +{ "bmskn", 0x26EC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* bmskn<.f> 0,limm,s12 0010011010101100F111ssssssSSSSSS. */ +{ "bmskn", 0x26AC7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* bmskn<.f> a,limm,limm 0010011000101100F111111110AAAAAA. */ +{ "bmskn", 0x262C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* bmskn<.f> 0,limm,limm 0010011000101100F111111110111110. */ +{ "bmskn", 0x262C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* bmskn<.f><.cc> 0,limm,limm 0010011011101100F1111111100QQQQQ. */ +{ "bmskn", 0x26EC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* bmsk_s b,b,u5 10111bbb110uuuuu. */ +{ "bmsk_s", 0x0000B8C0, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }}, + +/* bne_s s10 1111010sssssssss. */ +{ "bne_s", 0x0000F400, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { OPERAND_SIMM10_A16_7_S }, { C_CC_NE }}, + +/* breq<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00000. */ +{ "breq", 0x08010000, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_EQ }}, + +/* breq<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y000. */ +{ "breq", 0x08010000, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_EQ }}, + +/* breq<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10000. */ +{ "breq", 0x08010010, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_EQ }}, + +/* breq<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y000. */ +{ "breq", 0x08010010, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_EQ }}, + +/* breq b,limm,s9 00001bbbsssssss1SBBB111110000000. */ +{ "breq", 0x08010F80, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_CC_EQ }}, + +/* breq limm,c,s9 00001110sssssss1S111CCCCCC000000. */ +{ "breq", 0x0E017000, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_CC_EQ }}, + +/* breq<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y000. */ +{ "breq", 0x08010F80, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_EQ }}, + +/* breq<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y000. */ +{ "breq", 0x0E017000, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_EQ }}, + +/* breq limm,u6,s9 00001110sssssss1S111uuuuuu010000. */ +{ "breq", 0x0E017010, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_CC_EQ }}, + +/* breq<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y000. */ +{ "breq", 0x0E017010, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_EQ }}, + +/* breq<.T> limm,limm,s9 00001110sssssss1S11111111000Y000. */ +{ "breq", 0x0E017F80, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_EQ }}, + +/* breq_s b,0,s8 11101bbb0sssssss. */ +{ "breq_s", 0x0000E800, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB_S, OPERAND_ZB_S, OPERAND_SIMM8_A16_9_S }, { C_CC_EQ }}, + +/* brge<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00011. */ +{ "brge", 0x08010003, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_GE }}, + +/* brge<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y011. */ +{ "brge", 0x08010003, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_GE }}, + +/* brge<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10011. */ +{ "brge", 0x08010013, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_GE }}, + +/* brge<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y011. */ +{ "brge", 0x08010013, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_GE }}, + +/* brge b,limm,s9 00001bbbsssssss1SBBB111110000011. */ +{ "brge", 0x08010F83, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_CC_GE }}, + +/* brge limm,c,s9 00001110sssssss1S111CCCCCC000011. */ +{ "brge", 0x0E017003, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_CC_GE }}, + +/* brge<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y011. */ +{ "brge", 0x08010F83, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_GE }}, + +/* brge<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y011. */ +{ "brge", 0x0E017003, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_GE }}, + +/* brge limm,u6,s9 00001110sssssss1S111uuuuuu010011. */ +{ "brge", 0x0E017013, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_CC_GE }}, + +/* brge<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y011. */ +{ "brge", 0x0E017013, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_GE }}, + +/* brge<.T> limm,limm,s9 00001110sssssss1S11111111000Y011. */ +{ "brge", 0x0E017F83, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_GE }}, + +/* brhs<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00101. */ +{ "brhs", 0x08010005, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_HS }}, + +/* brhs<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y101. */ +{ "brhs", 0x08010005, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_HS }}, + +/* brhs<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10101. */ +{ "brhs", 0x08010015, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_HS }}, + +/* brhs<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y101. */ +{ "brhs", 0x08010015, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_HS }}, + +/* brhs b,limm,s9 00001bbbsssssss1SBBB111110000101. */ +{ "brhs", 0x08010F85, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_CC_HS }}, + +/* brhs limm,c,s9 00001110sssssss1S111CCCCCC000101. */ +{ "brhs", 0x0E017005, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_CC_HS }}, + +/* brhs<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y101. */ +{ "brhs", 0x08010F85, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_HS }}, + +/* brhs<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y101. */ +{ "brhs", 0x0E017005, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_HS }}, + +/* brhs limm,u6,s9 00001110sssssss1S111uuuuuu010101. */ +{ "brhs", 0x0E017015, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_CC_HS }}, + +/* brhs<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y101. */ +{ "brhs", 0x0E017015, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_HS }}, + +/* brhs<.T> limm,limm,s9 00001110sssssss1S11111111000Y101. */ +{ "brhs", 0x0E017F85, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_HS }}, + +/* brk 00100101011011110000000000111111. */ +{ "brk", 0x256F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { C_CC_HS }}, + +/* brk_s 0111111111111111. */ +{ "brk_s", 0x00007FFF, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }}, + +/* brlo<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00100. */ +{ "brlo", 0x08010004, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_LO }}, + +/* brlo<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y100. */ +{ "brlo", 0x08010004, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_LO }}, + +/* brlo<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10100. */ +{ "brlo", 0x08010014, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_LO }}, + +/* brlo<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y100. */ +{ "brlo", 0x08010014, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_LO }}, + +/* brlo b,limm,s9 00001bbbsssssss1SBBB111110000100. */ +{ "brlo", 0x08010F84, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_CC_LO }}, + +/* brlo limm,c,s9 00001110sssssss1S111CCCCCC000100. */ +{ "brlo", 0x0E017004, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_CC_LO }}, + +/* brlo<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y100. */ +{ "brlo", 0x08010F84, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_LO }}, + +/* brlo<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y100. */ +{ "brlo", 0x0E017004, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_LO }}, + +/* brlo limm,u6,s9 00001110sssssss1S111uuuuuu010100. */ +{ "brlo", 0x0E017014, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_CC_LO }}, + +/* brlo<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y100. */ +{ "brlo", 0x0E017014, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_LO }}, + +/* brlo<.T> limm,limm,s9 00001110sssssss1S11111111000Y100. */ +{ "brlo", 0x0E017F84, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_LO }}, + +/* brlt<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00010. */ +{ "brlt", 0x08010002, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_LT }}, + +/* brlt<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y010. */ +{ "brlt", 0x08010002, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_LT }}, + +/* brlt<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10010. */ +{ "brlt", 0x08010012, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_LT }}, + +/* brlt<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y010. */ +{ "brlt", 0x08010012, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_LT }}, + +/* brlt b,limm,s9 00001bbbsssssss1SBBB111110000010. */ +{ "brlt", 0x08010F82, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_CC_LT }}, + +/* brlt limm,c,s9 00001110sssssss1S111CCCCCC000010. */ +{ "brlt", 0x0E017002, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_CC_LT }}, + +/* brlt<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y010. */ +{ "brlt", 0x08010F82, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_LT }}, + +/* brlt<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y010. */ +{ "brlt", 0x0E017002, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_LT }}, + +/* brlt limm,u6,s9 00001110sssssss1S111uuuuuu010010. */ +{ "brlt", 0x0E017012, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_CC_LT }}, + +/* brlt<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y010. */ +{ "brlt", 0x0E017012, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_LT }}, + +/* brlt<.T> limm,limm,s9 00001110sssssss1S11111111000Y010. */ +{ "brlt", 0x0E017F82, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_LT }}, + +/* brne<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00001. */ +{ "brne", 0x08010001, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_NE }}, + +/* brne<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y001. */ +{ "brne", 0x08010001, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_NE }}, + +/* brne<.d> b,u6,s9 00001bbbsssssss1SBBBUUUUUUN10001. */ +{ "brne", 0x08010011, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_CC_NE }}, + +/* brne<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y001. */ +{ "brne", 0x08010011, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_D, C_T, C_CC_NE }}, + +/* brne b,limm,s9 00001bbbsssssss1SBBB111110000001. */ +{ "brne", 0x08010F81, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_CC_NE }}, + +/* brne limm,c,s9 00001110sssssss1S111CCCCCC000001. */ +{ "brne", 0x0E017001, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_CC_NE }}, + +/* brne<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y001. */ +{ "brne", 0x08010F81, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB, OPERAND_LIMM, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_NE }}, + +/* brne<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y001. */ +{ "brne", 0x0E017001, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_RC, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_NE }}, + +/* brne limm,u6,s9 00001110sssssss1S111uuuuuu010001. */ +{ "brne", 0x0E017011, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_CC_NE }}, + +/* brne<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y001. */ +{ "brne", 0x0E017011, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_UIMM6_8, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_NE }}, + +/* brne<.T> limm,limm,s9 00001110sssssss1S11111111000Y001. */ +{ "brne", 0x0E017F81, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_SIMM9_A16_8 }, { C_T, C_CC_NE }}, + +/* brne_s b,0,s8 11101bbb1sssssss. */ +{ "brne_s", 0x0000E880, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRCC, COND, { OPERAND_RB_S, OPERAND_ZB_S, OPERAND_SIMM8_A16_9_S }, { C_CC_NE }}, + +/* bset<.f> a,b,c 00100bbb00001111FBBBCCCCCCAAAAAA. */ +{ "bset", 0x200F0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* bset<.f> 0,b,c 00100bbb00001111FBBBCCCCCC111110. */ +{ "bset", 0x200F003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* bset<.f><.cc> b,b,c 00100bbb11001111FBBBCCCCCC0QQQQQ. */ +{ "bset", 0x20CF0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* bset<.f> a,b,u6 00100bbb01001111FBBBuuuuuuAAAAAA. */ +{ "bset", 0x204F0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* bset<.f> 0,b,u6 00100bbb01001111FBBBuuuuuu111110. */ +{ "bset", 0x204F003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* bset<.f><.cc> b,b,u6 00100bbb11001111FBBBuuuuuu1QQQQQ. */ +{ "bset", 0x20CF0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* bset<.f> b,b,s12 00100bbb10001111FBBBssssssSSSSSS. */ +{ "bset", 0x208F0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* bset<.f> a,limm,c 0010011000001111F111CCCCCCAAAAAA. */ +{ "bset", 0x260F7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* bset<.f> a,b,limm 00100bbb00001111FBBB111110AAAAAA. */ +{ "bset", 0x200F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* bset<.f> 0,limm,c 0010011000001111F111CCCCCC111110. */ +{ "bset", 0x260F703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* bset<.f> 0,b,limm 00100bbb00001111FBBB111110111110. */ +{ "bset", 0x200F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* bset<.f><.cc> b,b,limm 00100bbb11001111FBBB1111100QQQQQ. */ +{ "bset", 0x20CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* bset<.f><.cc> 0,limm,c 0010011011001111F111CCCCCC0QQQQQ. */ +{ "bset", 0x26CF7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* bset<.f> a,limm,u6 0010011001001111F111uuuuuuAAAAAA. */ +{ "bset", 0x264F7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* bset<.f> 0,limm,u6 0010011001001111F111uuuuuu111110. */ +{ "bset", 0x264F703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* bset<.f><.cc> 0,limm,u6 0010011011001111F111uuuuuu1QQQQQ. */ +{ "bset", 0x26CF7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* bset<.f> 0,limm,s12 0010011010001111F111ssssssSSSSSS. */ +{ "bset", 0x268F7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* bset<.f> a,limm,limm 0010011000001111F111111110AAAAAA. */ +{ "bset", 0x260F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* bset<.f> 0,limm,limm 0010011000001111F111111110111110. */ +{ "bset", 0x260F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* bset<.f><.cc> 0,limm,limm 0010011011001111F1111111100QQQQQ. */ +{ "bset", 0x26CF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* bset_s b,b,u5 10111bbb100uuuuu. */ +{ "bset_s", 0x0000B880, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }}, + +/* btst b,c 00100bbb000100011BBBCCCCCCRRRRRR. */ +{ "btst", 0x20118000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* btst b,c 00100bbb000100011BBBCCCCCC000000. */ +{ "btst", 0x20118000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* btst<.cc> b,c 00100bbb110100011BBBCCCCCC0QQQQQ. */ +{ "btst", 0x20D18000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }}, + +/* btst b,u6 00100bbb010100011BBBuuuuuuRRRRRR. */ +{ "btst", 0x20518000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* btst b,u6 00100bbb010100011BBBuuuuuu000000. */ +{ "btst", 0x20518000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* btst<.cc> b,u6 00100bbb110100011BBBuuuuuu1QQQQQ. */ +{ "btst", 0x20D18020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, + +/* btst b,s12 00100bbb100100011BBBssssssSSSSSS. */ +{ "btst", 0x20918000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, + +/* btst limm,c 00100110000100011111CCCCCCRRRRRR. */ +{ "btst", 0x2611F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* btst b,limm 00100bbb000100011BBB111110RRRRRR. */ +{ "btst", 0x20118F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* btst limm,c 00100110000100011111CCCCCC000000. */ +{ "btst", 0x2611F000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* btst b,limm 00100bbb000100011BBB111110000000. */ +{ "btst", 0x20118F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* btst<.cc> b,limm 00100bbb110100011BBB1111100QQQQQ. */ +{ "btst", 0x20D18F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, + +/* btst<.cc> limm,c 00100110110100011111CCCCCC0QQQQQ. */ +{ "btst", 0x26D1F000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* btst limm,u6 00100110010100011111uuuuuuRRRRRR. */ +{ "btst", 0x2651F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* btst limm,u6 00100110010100011111uuuuuu000000. */ +{ "btst", 0x2651F000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* btst<.cc> limm,u6 00100110110100011111uuuuuu1QQQQQ. */ +{ "btst", 0x26D1F020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* btst limm,s12 00100110100100011111ssssssSSSSSS. */ +{ "btst", 0x2691F000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* btst limm,limm 00100110000100011111111110RRRRRR. */ +{ "btst", 0x2611FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* btst limm,limm 00100110000100011111111110000000. */ +{ "btst", 0x2611FF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* btst<.cc> limm,limm 001001101101000111111111100QQQQQ. */ +{ "btst", 0x26D1FF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* btst_s b,u5 10111bbb111uuuuu. */ +{ "btst_s", 0x0000B8E0, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_UIMM5_11_S }, { 0 }}, + +/* bxor<.f> a,b,c 00100bbb00010010FBBBCCCCCCAAAAAA. */ +{ "bxor", 0x20120000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* bxor<.f> 0,b,c 00100bbb00010010FBBBCCCCCC111110. */ +{ "bxor", 0x2012003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* bxor<.f><.cc> b,b,c 00100bbb11010010FBBBCCCCCC0QQQQQ. */ +{ "bxor", 0x20D20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* bxor<.f> a,b,u6 00100bbb01010010FBBBuuuuuuAAAAAA. */ +{ "bxor", 0x20520000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* bxor<.f> 0,b,u6 00100bbb01010010FBBBuuuuuu111110. */ +{ "bxor", 0x2052003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* bxor<.f><.cc> b,b,u6 00100bbb11010010FBBBuuuuuu1QQQQQ. */ +{ "bxor", 0x20D20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* bxor<.f> b,b,s12 00100bbb10010010FBBBssssssSSSSSS. */ +{ "bxor", 0x20920000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* bxor<.f> a,limm,c 0010011000010010F111CCCCCCAAAAAA. */ +{ "bxor", 0x26127000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* bxor<.f> a,b,limm 00100bbb00010010FBBB111110AAAAAA. */ +{ "bxor", 0x20120F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* bxor<.f> 0,limm,c 0010011000010010F111CCCCCC111110. */ +{ "bxor", 0x2612703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* bxor<.f> 0,b,limm 00100bbb00010010FBBB111110111110. */ +{ "bxor", 0x20120FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* bxor<.f><.cc> b,b,limm 00100bbb11010010FBBB1111100QQQQQ. */ +{ "bxor", 0x20D20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* bxor<.f><.cc> 0,limm,c 0010011011010010F111CCCCCC0QQQQQ. */ +{ "bxor", 0x26D27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* bxor<.f> a,limm,u6 0010011001010010F111uuuuuuAAAAAA. */ +{ "bxor", 0x26527000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* bxor<.f> 0,limm,u6 0010011001010010F111uuuuuu111110. */ +{ "bxor", 0x2652703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* bxor<.f><.cc> 0,limm,u6 0010011011010010F111uuuuuu1QQQQQ. */ +{ "bxor", 0x26D27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* bxor<.f> 0,limm,s12 0010011010010010F111ssssssSSSSSS. */ +{ "bxor", 0x26927000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* bxor<.f> a,limm,limm 0010011000010010F111111110AAAAAA. */ +{ "bxor", 0x26127F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* bxor<.f> 0,limm,limm 0010011000010010F111111110111110. */ +{ "bxor", 0x26127FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* bxor<.f><.cc> 0,limm,limm 0010011011010010F1111111100QQQQQ. */ +{ "bxor", 0x26D27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* b_s s10 1111000sssssssss. */ +{ "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { OPERAND_SIMM10_A16_7_S }, { 0 }}, + +/* cbflyhf0r a,b,c 00110bbb000110111BBBCCCCCCAAAAAA. */ +{ "cbflyhf0r", 0x301B8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* cbflyhf0r 0,b,c 00110bbb000110111BBBCCCCCC111110. */ +{ "cbflyhf0r", 0x301B803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* cbflyhf0r<.cc> b,b,c 00110bbb110110111BBBCCCCCC0QQQQQ. */ +{ "cbflyhf0r", 0x30DB8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* cbflyhf0r a,b,u6 00110bbb010110111BBBuuuuuuAAAAAA. */ +{ "cbflyhf0r", 0x305B8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* cbflyhf0r 0,b,u6 00110bbb010110111BBBuuuuuu111110. */ +{ "cbflyhf0r", 0x305B803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* cbflyhf0r<.cc> b,b,u6 00110bbb110110111BBBuuuuuu1QQQQQ. */ +{ "cbflyhf0r", 0x30DB8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* cbflyhf0r b,b,s12 00110bbb100110111BBBssssssSSSSSS. */ +{ "cbflyhf0r", 0x309B8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* cbflyhf0r a,limm,c 00110110000110111111CCCCCCAAAAAA. */ +{ "cbflyhf0r", 0x361BF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* cbflyhf0r a,b,limm 00110bbb000110111BBB111110AAAAAA. */ +{ "cbflyhf0r", 0x301B8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* cbflyhf0r 0,limm,c 00110110000110111111CCCCCC111110. */ +{ "cbflyhf0r", 0x361BF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* cbflyhf0r 0,b,limm 00110bbb000110111BBB111110111110. */ +{ "cbflyhf0r", 0x301B8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* cbflyhf0r<.cc> b,b,limm 00110bbb110110111BBB1111100QQQQQ. */ +{ "cbflyhf0r", 0x30DB8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* cbflyhf0r<.cc> 0,limm,c 00110110110110111111CCCCCC0QQQQQ. */ +{ "cbflyhf0r", 0x36DBF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* cbflyhf0r a,limm,u6 00110110010110111111uuuuuuAAAAAA. */ +{ "cbflyhf0r", 0x365BF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* cbflyhf0r 0,limm,u6 00110110010110111111uuuuuu111110. */ +{ "cbflyhf0r", 0x365BF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* cbflyhf0r<.cc> 0,limm,u6 00110110110110111111uuuuuu1QQQQQ. */ +{ "cbflyhf0r", 0x36DBF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* cbflyhf0r 0,limm,s12 00110110100110111111ssssssSSSSSS. */ +{ "cbflyhf0r", 0x369BF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* cbflyhf0r a,limm,limm 00110110000110111111111110AAAAAA. */ +{ "cbflyhf0r", 0x361BFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* cbflyhf0r 0,limm,limm 00110110000110111111111110111110. */ +{ "cbflyhf0r", 0x361BFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* cbflyhf0r<.cc> 0,limm,limm 001101101101101111111111100QQQQQ. */ +{ "cbflyhf0r", 0x36DBFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* cbflyhf1r b,c 00110bbb001011110BBBCCCCCC111001. */ +{ "cbflyhf1r", 0x302F0039, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, + +/* cbflyhf1r 0,c 00110110001011110111CCCCCC011001. */ +{ "cbflyhf1r", 0x362F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, + +/* cbflyhf1r b,u6 00110bbb011011110BBBuuuuuu011001. */ +{ "cbflyhf1r", 0x306F0019, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, + +/* cbflyhf1r 0,u6 00110110011011110111uuuuuu011001. */ +{ "cbflyhf1r", 0x366F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, + +/* cbflyhf1r b,limm 00110bbb001011110BBB111110011001. */ +{ "cbflyhf1r", 0x302F0F99, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, + +/* cbflyhf1r 0,limm 00110110001011110111111110011001. */ +{ "cbflyhf1r", 0x362F7F99, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, + +/* clamp<.f> a,b,c 00110bbb00101010FBBBCCCCCCAAAAAA. */ +{ "clamp", 0x302A0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* clamp<.f><.cc> b,b,c 00110bbb11101010FBBBCCCCCC0QQQQQ. */ +{ "clamp", 0x30EA0000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* clamp<.f> a,b,u6 00110bbb01101010FBBBuuuuuuAAAAAA. */ +{ "clamp", 0x306A0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* clamp<.f><.cc> b,b,u6 00110bbb11101010FBBBuuuuuu1QQQQQ. */ +{ "clamp", 0x30EA0020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* clamp<.f> b,b,s12 00110bbb10101010FBBBssssssSSSSSS. */ +{ "clamp", 0x30AA0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* clamp<.f> a,limm,c 0011011000101010F111CCCCCCAAAAAA. */ +{ "clamp", 0x362A7000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* clamp<.f> a,b,limm 00110bbb00101010FBBB111110AAAAAA. */ +{ "clamp", 0x302A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* clamp<.f><.cc> b,b,limm 00110bbb11101010FBBB1111100QQQQQ. */ +{ "clamp", 0x30EA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* clri c 00100111001011110000CCCCCC111111. */ +{ "clri", 0x272F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_RC }, { 0 }}, + +/* clri u6 00100111011011110000uuuuuu111111. */ +{ "clri", 0x276F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_UIMM6_20 }, { 0 }}, + +/* clri 00100111011011110000uuuuuu111111. */ +{ "clri", 0x276F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }}, + +/* cmacchfr a,b,c 00110bbb000010011BBBCCCCCCAAAAAA. */ +{ "cmacchfr", 0x30098000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* cmacchfr 0,b,c 00110bbb000010011BBBCCCCCC111110. */ +{ "cmacchfr", 0x3009803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* cmacchfr<.cc> b,b,c 00110bbb110010011BBBCCCCCC0QQQQQ. */ +{ "cmacchfr", 0x30C98000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* cmacchfr a,b,u6 00110bbb010010011BBBuuuuuuAAAAAA. */ +{ "cmacchfr", 0x30498000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmacchfr 0,b,u6 00110bbb010010011BBBuuuuuu111110. */ +{ "cmacchfr", 0x3049803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmacchfr<.cc> b,b,u6 00110bbb110010011BBBuuuuuu1QQQQQ. */ +{ "cmacchfr", 0x30C98020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* cmacchfr b,b,s12 00110bbb100010011BBBssssssSSSSSS. */ +{ "cmacchfr", 0x30898000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* cmacchfr a,limm,c 00110110000010011111CCCCCCAAAAAA. */ +{ "cmacchfr", 0x3609F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* cmacchfr a,b,limm 00110bbb000010011BBB111110AAAAAA. */ +{ "cmacchfr", 0x30098F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* cmacchfr 0,limm,c 00110110000010011111CCCCCC111110. */ +{ "cmacchfr", 0x3609F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* cmacchfr 0,b,limm 00110bbb000010011BBB111110111110. */ +{ "cmacchfr", 0x30098FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* cmacchfr<.cc> 0,limm,c 00110bbb110010011BBB1111100QQQQQ. */ +{ "cmacchfr", 0x30C98F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* cmacchfr<.cc> b,b,limm 00110110110010011111CCCCCC0QQQQQ. */ +{ "cmacchfr", 0x36C9F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* cmacchfr a,limm,u6 00110110010010011111uuuuuuAAAAAA. */ +{ "cmacchfr", 0x3649F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmacchfr 0,limm,u6 00110110010010011111uuuuuu111110. */ +{ "cmacchfr", 0x3649F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmacchfr<.cc> 0,limm,u6 00110110110010011111uuuuuu1QQQQQ. */ +{ "cmacchfr", 0x36C9F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* cmacchfr 0,limm,s12 00110110100010011111ssssssSSSSSS. */ +{ "cmacchfr", 0x3689F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* cmacchfr a,limm,limm 00110110000010011111111110AAAAAA. */ +{ "cmacchfr", 0x3609FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* cmacchfr 0,limm,limm 00110110000010011111111110111110. */ +{ "cmacchfr", 0x3609FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* cmacchfr<.cc> 0,limm,limm 001101101100100111111111100QQQQQ. */ +{ "cmacchfr", 0x36C9FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* cmacchnfr a,b,c 00110bbb000010001BBBCCCCCCAAAAAA. */ +{ "cmacchnfr", 0x30088000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* cmacchnfr 0,b,c 00110bbb000010001BBBCCCCCC111110. */ +{ "cmacchnfr", 0x3008803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* cmacchnfr<.cc> b,b,c 00110bbb110010001BBBCCCCCC0QQQQQ. */ +{ "cmacchnfr", 0x30C88000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* cmacchnfr a,b,u6 00110bbb010010001BBBuuuuuuAAAAAA. */ +{ "cmacchnfr", 0x30488000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmacchnfr 0,b,u6 00110bbb010010001BBBuuuuuu111110. */ +{ "cmacchnfr", 0x3048803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmacchnfr<.cc> b,b,u6 00110bbb110010001BBBuuuuuu1QQQQQ. */ +{ "cmacchnfr", 0x30C88020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* cmacchnfr b,b,s12 00110bbb100010001BBBssssssSSSSSS. */ +{ "cmacchnfr", 0x30888000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* cmacchnfr a,limm,c 00110110000010001111CCCCCCAAAAAA. */ +{ "cmacchnfr", 0x3608F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* cmacchnfr a,b,limm 00110bbb000010001BBB111110AAAAAA. */ +{ "cmacchnfr", 0x30088F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* cmacchnfr 0,limm,c 00110110000010001111CCCCCC111110. */ +{ "cmacchnfr", 0x3608F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* cmacchnfr 0,b,limm 00110bbb000010001BBB111110111110. */ +{ "cmacchnfr", 0x30088FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* cmacchnfr<.cc> 0,limm,c 00110bbb110010001BBB1111100QQQQQ. */ +{ "cmacchnfr", 0x30C88F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* cmacchnfr<.cc> b,b,limm 00110110110010001111CCCCCC0QQQQQ. */ +{ "cmacchnfr", 0x36C8F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* cmacchnfr a,limm,u6 00110110010010001111uuuuuuAAAAAA. */ +{ "cmacchnfr", 0x3648F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmacchnfr 0,limm,u6 00110110010010001111uuuuuu111110. */ +{ "cmacchnfr", 0x3648F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmacchnfr<.cc> 0,limm,u6 00110110110010001111uuuuuu1QQQQQ. */ +{ "cmacchnfr", 0x36C8F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* cmacchnfr 0,limm,s12 00110110100010001111ssssssSSSSSS. */ +{ "cmacchnfr", 0x3688F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* cmacchnfr a,limm,limm 00110110000010001111111110AAAAAA. */ +{ "cmacchnfr", 0x3608FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* cmacchnfr 0,limm,limm 00110110000010001111111110111110. */ +{ "cmacchnfr", 0x3608FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* cmacchnfr<.cc> 0,limm,limm 001101101100100011111111100QQQQQ. */ +{ "cmacchnfr", 0x36C8FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* cmachfr a,b,c 00110bbb000001111BBBCCCCCCAAAAAA. */ +{ "cmachfr", 0x30078000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* cmachfr 0,b,c 00110bbb000001111BBBCCCCCC111110. */ +{ "cmachfr", 0x3007803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* cmachfr<.cc> b,b,c 00110bbb110001111BBBCCCCCC0QQQQQ. */ +{ "cmachfr", 0x30C78000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* cmachfr a,b,u6 00110bbb010001111BBBuuuuuuAAAAAA. */ +{ "cmachfr", 0x30478000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmachfr 0,b,u6 00110bbb010001111BBBuuuuuu111110. */ +{ "cmachfr", 0x3047803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmachfr<.cc> b,b,u6 00110bbb110001111BBBuuuuuu1QQQQQ. */ +{ "cmachfr", 0x30C78020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* cmachfr b,b,s12 00110bbb100001111BBBssssssSSSSSS. */ +{ "cmachfr", 0x30878000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* cmachfr a,limm,c 00110110000001111111CCCCCCAAAAAA. */ +{ "cmachfr", 0x3607F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* cmachfr a,b,limm 00110bbb000001111BBB111110AAAAAA. */ +{ "cmachfr", 0x30078F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* cmachfr 0,limm,c 00110110000001111111CCCCCC111110. */ +{ "cmachfr", 0x3607F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* cmachfr 0,b,limm 00110bbb000001111BBB111110111110. */ +{ "cmachfr", 0x30078FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* cmachfr<.cc> 0,limm,c 00110bbb110001111BBB1111100QQQQQ. */ +{ "cmachfr", 0x30C78F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* cmachfr<.cc> b,b,limm 00110110110001111111CCCCCC0QQQQQ. */ +{ "cmachfr", 0x36C7F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* cmachfr a,limm,u6 00110110010001111111uuuuuuAAAAAA. */ +{ "cmachfr", 0x3647F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmachfr 0,limm,u6 00110110010001111111uuuuuu111110. */ +{ "cmachfr", 0x3647F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmachfr<.cc> 0,limm,u6 00110110110001111111uuuuuu1QQQQQ. */ +{ "cmachfr", 0x36C7F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* cmachfr 0,limm,s12 00110110100001111111ssssssSSSSSS. */ +{ "cmachfr", 0x3687F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* cmachfr a,limm,limm 00110110000001111111111110AAAAAA. */ +{ "cmachfr", 0x3607FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* cmachfr 0,limm,limm 00110110000001111111111110111110. */ +{ "cmachfr", 0x3607FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* cmachfr<.cc> 0,limm,limm 001101101100011111111111100QQQQQ. */ +{ "cmachfr", 0x36C7FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* cmachnfr a,b,c 00110bbb000001101BBBCCCCCCAAAAAA. */ +{ "cmachnfr", 0x30068000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* cmachnfr 0,b,c 00110bbb000001101BBBCCCCCC111110. */ +{ "cmachnfr", 0x3006803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* cmachnfr<.cc> b,b,c 00110bbb110001101BBBCCCCCC0QQQQQ. */ +{ "cmachnfr", 0x30C68000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* cmachnfr a,b,u6 00110bbb010001101BBBuuuuuuAAAAAA. */ +{ "cmachnfr", 0x30468000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmachnfr 0,b,u6 00110bbb010001101BBBuuuuuu111110. */ +{ "cmachnfr", 0x3046803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmachnfr<.cc> b,b,u6 00110bbb110001101BBBuuuuuu1QQQQQ. */ +{ "cmachnfr", 0x30C68020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* cmachnfr b,b,s12 00110bbb100001101BBBssssssSSSSSS. */ +{ "cmachnfr", 0x30868000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* cmachnfr a,limm,c 00110110000001101111CCCCCCAAAAAA. */ +{ "cmachnfr", 0x3606F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* cmachnfr a,b,limm 00110bbb000001101BBB111110AAAAAA. */ +{ "cmachnfr", 0x30068F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* cmachnfr 0,limm,c 00110110000001101111CCCCCC111110. */ +{ "cmachnfr", 0x3606F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* cmachnfr 0,b,limm 00110bbb000001101BBB111110111110. */ +{ "cmachnfr", 0x30068FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* cmachnfr<.cc> 0,limm,c 00110bbb110001101BBB1111100QQQQQ. */ +{ "cmachnfr", 0x30C68F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* cmachnfr<.cc> b,b,limm 00110110110001101111CCCCCC0QQQQQ. */ +{ "cmachnfr", 0x36C6F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* cmachnfr a,limm,u6 00110110010001101111uuuuuuAAAAAA. */ +{ "cmachnfr", 0x3646F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmachnfr 0,limm,u6 00110110010001101111uuuuuu111110. */ +{ "cmachnfr", 0x3646F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmachnfr<.cc> 0,limm,u6 00110110110001101111uuuuuu1QQQQQ. */ +{ "cmachnfr", 0x36C6F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* cmachnfr 0,limm,s12 00110110100001101111ssssssSSSSSS. */ +{ "cmachnfr", 0x3686F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* cmachnfr a,limm,limm 00110110000001101111111110AAAAAA. */ +{ "cmachnfr", 0x3606FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* cmachnfr 0,limm,limm 00110110000001101111111110111110. */ +{ "cmachnfr", 0x3606FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* cmachnfr<.cc> 0,limm,limm 001101101100011011111111100QQQQQ. */ +{ "cmachnfr", 0x36C6FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* cmacrdw<.f> a,b,c 00101bbb00100110FBBBCCCCCCAAAAAA. */ +{ "cmacrdw", 0x28260000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* cmacrdw<.f> 0,b,c 00101bbb00100110FBBBCCCCCC111110. */ +{ "cmacrdw", 0x2826003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* cmacrdw<.f><.cc> b,b,c 00101bbb11100110FBBBCCCCCC0QQQQQ. */ +{ "cmacrdw", 0x28E60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* cmacrdw<.f> a,b,u6 00101bbb01100110FBBBuuuuuuAAAAAA. */ +{ "cmacrdw", 0x28660000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* cmacrdw<.f> 0,b,u6 00101bbb01100110FBBBuuuuuu111110. */ +{ "cmacrdw", 0x2866003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* cmacrdw<.f><.cc> b,b,u6 00101bbb11100110FBBBuuuuuu1QQQQQ. */ +{ "cmacrdw", 0x28E60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* cmacrdw<.f> b,b,s12 00101bbb10100110FBBBssssssSSSSSS. */ +{ "cmacrdw", 0x28A60000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* cmacrdw<.f> a,limm,c 0010111000100110F111CCCCCCAAAAAA. */ +{ "cmacrdw", 0x2E267000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* cmacrdw<.f> a,b,limm 00101bbb00100110FBBB111110AAAAAA. */ +{ "cmacrdw", 0x28260F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* cmacrdw<.f> 0,limm,c 0010111000100110F111CCCCCC111110. */ +{ "cmacrdw", 0x2E26703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* cmacrdw<.f> 0,b,limm 00101bbb00100110FBBB111110111110. */ +{ "cmacrdw", 0x28260FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* cmacrdw<.f><.cc> 0,limm,c 0010111011100110F111CCCCCC0QQQQQ. */ +{ "cmacrdw", 0x2EE67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* cmacrdw<.f><.cc> b,b,limm 00101bbb11100110FBBB1111100QQQQQ. */ +{ "cmacrdw", 0x28E60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* cmacrdw<.f> a,limm,u6 0010111001100110F111uuuuuuAAAAAA. */ +{ "cmacrdw", 0x2E667000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* cmacrdw<.f> 0,limm,u6 0010111001100110F111uuuuuu111110. */ +{ "cmacrdw", 0x2E66703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* cmacrdw<.f><.cc> 0,limm,u6 0010111011100110F111uuuuuu1QQQQQ. */ +{ "cmacrdw", 0x2EE67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* cmacrdw<.f> 0,limm,s12 0010111010100110F111ssssssSSSSSS. */ +{ "cmacrdw", 0x2EA67000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* cmacrdw<.f> a,limm,limm 0010111000100110F111111110AAAAAA. */ +{ "cmacrdw", 0x2E267F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* cmacrdw<.f> 0,limm,limm 0010111000100110F111111110111110. */ +{ "cmacrdw", 0x2E267FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* cmacrdw<.f><.cc> 0,limm,limm 0010111011100110F1111111100QQQQQ. */ +{ "cmacrdw", 0x2EE67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* cmp b,c 00100bbb000011001BBBCCCCCCRRRRRR. */ +{ "cmp", 0x200C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* cmp b,c 00100bbb000011001BBBCCCCCC000000. */ +{ "cmp", 0x200C8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* cmp<.cc> b,c 00100bbb110011001BBBCCCCCC0QQQQQ. */ +{ "cmp", 0x20CC8000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }}, + +/* cmp b,u6 00100bbb010011001BBBuuuuuuRRRRRR. */ +{ "cmp", 0x204C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmp b,u6 00100bbb010011001BBBuuuuuu000000. */ +{ "cmp", 0x204C8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmp<.cc> b,u6 00100bbb110011001BBBuuuuuu1QQQQQ. */ +{ "cmp", 0x20CC8020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, + +/* cmp b,s12 00100bbb100011001BBBssssssSSSSSS. */ +{ "cmp", 0x208C8000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, + +/* cmp limm,c 00100110000011001111CCCCCCRRRRRR. */ +{ "cmp", 0x260CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* cmp b,limm 00100bbb000011001BBB111110RRRRRR. */ +{ "cmp", 0x200C8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* cmp limm,c 00100110000011001111CCCCCC000000. */ +{ "cmp", 0x260CF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* cmp b,limm 00100bbb000011001BBB111110000000. */ +{ "cmp", 0x200C8F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* cmp<.cc> b,limm 00100bbb110011001BBB1111100QQQQQ. */ +{ "cmp", 0x20CC8F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, + +/* cmp<.cc> limm,c 00100110110011001111CCCCCC0QQQQQ. */ +{ "cmp", 0x26CCF000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* cmp limm,u6 00100110010011001111uuuuuuRRRRRR. */ +{ "cmp", 0x264CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmp limm,u6 00100110010011001111uuuuuu000000. */ +{ "cmp", 0x264CF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmp<.cc> limm,u6 00100110110011001111uuuuuu1QQQQQ. */ +{ "cmp", 0x26CCF020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* cmp limm,s12 00100110100011001111ssssssSSSSSS. */ +{ "cmp", 0x268CF000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* cmp limm,limm 00100110000011001111111110RRRRRR. */ +{ "cmp", 0x260CFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* cmp limm,limm 00100110000011001111111110000000. */ +{ "cmp", 0x260CFF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* cmp<.cc> limm,limm 001001101100110011111111100QQQQQ. */ +{ "cmp", 0x26CCFF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* cmpychfr a,b,c 00110bbb000001011BBBCCCCCCAAAAAA. */ +{ "cmpychfr", 0x30058000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* cmpychfr 0,b,c 00110bbb000001011BBBCCCCCC111110. */ +{ "cmpychfr", 0x3005803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* cmpychfr<.cc> b,b,c 00110bbb110001011BBBCCCCCC0QQQQQ. */ +{ "cmpychfr", 0x30C58000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* cmpychfr a,b,u6 00110bbb010001011BBBuuuuuuAAAAAA. */ +{ "cmpychfr", 0x30458000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmpychfr 0,b,u6 00110bbb010001011BBBuuuuuu111110. */ +{ "cmpychfr", 0x3045803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmpychfr<.cc> b,b,u6 00110bbb110001011BBBuuuuuu1QQQQQ. */ +{ "cmpychfr", 0x30C58020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* cmpychfr b,b,s12 00110bbb100001011BBBssssssSSSSSS. */ +{ "cmpychfr", 0x30858000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* cmpychfr a,limm,c 00110110000001011111CCCCCCAAAAAA. */ +{ "cmpychfr", 0x3605F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* cmpychfr a,b,limm 00110bbb000001011BBB111110AAAAAA. */ +{ "cmpychfr", 0x30058F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* cmpychfr 0,limm,c 00110110000001011111CCCCCC111110. */ +{ "cmpychfr", 0x3605F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* cmpychfr 0,b,limm 00110bbb000001011BBB111110111110. */ +{ "cmpychfr", 0x30058FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* cmpychfr<.cc> 0,limm,c 00110bbb110001011BBB1111100QQQQQ. */ +{ "cmpychfr", 0x30C58F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* cmpychfr<.cc> b,b,limm 00110110110001011111CCCCCC0QQQQQ. */ +{ "cmpychfr", 0x36C5F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* cmpychfr a,limm,u6 00110110010001011111uuuuuuAAAAAA. */ +{ "cmpychfr", 0x3645F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmpychfr 0,limm,u6 00110110010001011111uuuuuu111110. */ +{ "cmpychfr", 0x3645F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmpychfr<.cc> 0,limm,u6 00110110110001011111uuuuuu1QQQQQ. */ +{ "cmpychfr", 0x36C5F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* cmpychfr 0,limm,s12 00110110100001011111ssssssSSSSSS. */ +{ "cmpychfr", 0x3685F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* cmpychfr a,limm,limm 00110110000001011111111110AAAAAA. */ +{ "cmpychfr", 0x3605FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* cmpychfr 0,limm,limm 00110110000001011111111110111110. */ +{ "cmpychfr", 0x3605FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* cmpychfr<.cc> 0,limm,limm 001101101100010111111111100QQQQQ. */ +{ "cmpychfr", 0x36C5FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* cmpychnfr a,b,c 00110bbb000000101BBBCCCCCCAAAAAA. */ +{ "cmpychnfr", 0x30028000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* cmpychnfr 0,b,c 00110bbb000000001BBBCCCCCC111110. */ +{ "cmpychnfr", 0x3000803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* cmpychnfr<.cc> b,b,c 00110bbb110000001BBBCCCCCC0QQQQQ. */ +{ "cmpychnfr", 0x30C08000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* cmpychnfr a,b,u6 00110bbb010000001BBBuuuuuuAAAAAA. */ +{ "cmpychnfr", 0x30408000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmpychnfr 0,b,u6 00110bbb010000001BBBuuuuuu111110. */ +{ "cmpychnfr", 0x3040803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmpychnfr<.cc> b,b,u6 00110bbb110000001BBBuuuuuu1QQQQQ. */ +{ "cmpychnfr", 0x30C08020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* cmpychnfr b,b,s12 00110bbb100000001BBBssssssSSSSSS. */ +{ "cmpychnfr", 0x30808000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* cmpychnfr a,limm,c 00110110000000001111CCCCCCAAAAAA. */ +{ "cmpychnfr", 0x3600F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* cmpychnfr a,b,limm 00110bbb000000001BBB111110AAAAAA. */ +{ "cmpychnfr", 0x30008F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* cmpychnfr 0,limm,c 00110110000000001111CCCCCC111110. */ +{ "cmpychnfr", 0x3600F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* cmpychnfr 0,b,limm 00110bbb000000001BBB111110111110. */ +{ "cmpychnfr", 0x30008FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* cmpychnfr<.cc> 0,limm,c 00110bbb110000001BBB1111100QQQQQ. */ +{ "cmpychnfr", 0x30C08F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* cmpychnfr<.cc> b,b,limm 00110110110000001111CCCCCC0QQQQQ. */ +{ "cmpychnfr", 0x36C0F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* cmpychnfr a,limm,u6 00110110010000001111uuuuuuAAAAAA. */ +{ "cmpychnfr", 0x3640F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmpychnfr 0,limm,u6 00110110010000001111uuuuuu111110. */ +{ "cmpychnfr", 0x3640F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmpychnfr<.cc> 0,limm,u6 00110110110000001111uuuuuu1QQQQQ. */ +{ "cmpychnfr", 0x36C0F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* cmpychnfr 0,limm,s12 00110110100000001111ssssssSSSSSS. */ +{ "cmpychnfr", 0x3680F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* cmpychnfr a,limm,limm 00110110000000001111111110AAAAAA. */ +{ "cmpychnfr", 0x3600FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* cmpychnfr 0,limm,limm 00110110000000001111111110111110. */ +{ "cmpychnfr", 0x3600FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* cmpychnfr<.cc> 0,limm,limm 001101101100000011111111100QQQQQ. */ +{ "cmpychnfr", 0x36C0FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* cmpyhfmr a,b,c 00110bbb000110110BBBCCCCCCAAAAAA. */ +{ "cmpyhfmr", 0x301B0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* cmpyhfmr 0,b,c 00110bbb000110110BBBCCCCCC111110. */ +{ "cmpyhfmr", 0x301B003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* cmpyhfmr<.cc> b,b,c 00110bbb110110110BBBCCCCCC0QQQQQ. */ +{ "cmpyhfmr", 0x30DB0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* cmpyhfmr a,b,u6 00110bbb010110110BBBuuuuuuAAAAAA. */ +{ "cmpyhfmr", 0x305B0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmpyhfmr 0,b,u6 00110bbb010110110BBBuuuuuu111110. */ +{ "cmpyhfmr", 0x305B003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmpyhfmr<.cc> b,b,u6 00110bbb110110110BBBuuuuuu1QQQQQ. */ +{ "cmpyhfmr", 0x30DB0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* cmpyhfmr b,b,s12 00110bbb100110110BBBssssssSSSSSS. */ +{ "cmpyhfmr", 0x309B0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* cmpyhfmr a,limm,c 00110110000110110111CCCCCCAAAAAA. */ +{ "cmpyhfmr", 0x361B7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* cmpyhfmr a,b,limm 00110bbb000110110BBB111110AAAAAA. */ +{ "cmpyhfmr", 0x301B0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* cmpyhfmr 0,limm,c 00110110000110110111CCCCCC111110. */ +{ "cmpyhfmr", 0x361B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* cmpyhfmr 0,b,limm 00110bbb000110110BBB111110111110. */ +{ "cmpyhfmr", 0x301B0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* cmpyhfmr<.cc> 0,limm,c 00110bbb110110110BBB1111100QQQQQ. */ +{ "cmpyhfmr", 0x30DB0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* cmpyhfmr<.cc> b,b,limm 00110110110110110111CCCCCC0QQQQQ. */ +{ "cmpyhfmr", 0x36DB7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* cmpyhfmr a,limm,u6 00110110010110110111uuuuuuAAAAAA. */ +{ "cmpyhfmr", 0x365B7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmpyhfmr 0,limm,u6 00110110010110110111uuuuuu111110. */ +{ "cmpyhfmr", 0x365B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmpyhfmr<.cc> 0,limm,u6 00110110110110110111uuuuuu1QQQQQ. */ +{ "cmpyhfmr", 0x36DB7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* cmpyhfmr 0,limm,s12 00110110100110110111ssssssSSSSSS. */ +{ "cmpyhfmr", 0x369B7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* cmpyhfmr a,limm,limm 00110110000110110111111110AAAAAA. */ +{ "cmpyhfmr", 0x361B7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* cmpyhfmr 0,limm,limm 00110110000110110111111110111110. */ +{ "cmpyhfmr", 0x361B7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* cmpyhfmr<.cc> 0,limm,limm 001101101101101101111111100QQQQQ. */ +{ "cmpyhfmr", 0x36DB7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* cmpyhfr a,b,c 00110bbb000000011BBBCCCCCCAAAAAA. */ +{ "cmpyhfr", 0x30018000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* cmpyhfr 0,b,c 00110bbb000000011BBBCCCCCC111110. */ +{ "cmpyhfr", 0x3001803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* cmpyhfr<.cc> b,b,c 00110bbb110000011BBBCCCCCC0QQQQQ. */ +{ "cmpyhfr", 0x30C18000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* cmpyhfr a,b,u6 00110bbb010000011BBBuuuuuuAAAAAA. */ +{ "cmpyhfr", 0x30418000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmpyhfr 0,b,u6 00110bbb010000011BBBuuuuuu111110. */ +{ "cmpyhfr", 0x3041803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmpyhfr<.cc> b,b,u6 00110bbb110000011BBBuuuuuu1QQQQQ. */ +{ "cmpyhfr", 0x30C18020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* cmpyhfr b,b,s12 00110bbb100000011BBBssssssSSSSSS. */ +{ "cmpyhfr", 0x30818000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* cmpyhfr a,limm,c 00110110000000011111CCCCCCAAAAAA. */ +{ "cmpyhfr", 0x3601F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* cmpyhfr a,b,limm 00110bbb000000011BBB111110AAAAAA. */ +{ "cmpyhfr", 0x30018F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* cmpyhfr 0,limm,c 00110110000000011111CCCCCC111110. */ +{ "cmpyhfr", 0x3601F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* cmpyhfr 0,b,limm 00110bbb000000011BBB111110111110. */ +{ "cmpyhfr", 0x30018FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* cmpyhfr<.cc> 0,limm,c 00110bbb110000011BBB1111100QQQQQ. */ +{ "cmpyhfr", 0x30C18F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* cmpyhfr<.cc> b,b,limm 00110110110000011111CCCCCC0QQQQQ. */ +{ "cmpyhfr", 0x36C1F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* cmpyhfr a,limm,u6 00110110010000011111uuuuuuAAAAAA. */ +{ "cmpyhfr", 0x3641F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmpyhfr 0,limm,u6 00110110010000011111uuuuuu111110. */ +{ "cmpyhfr", 0x3641F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmpyhfr<.cc> 0,limm,u6 00110110110000011111uuuuuu1QQQQQ. */ +{ "cmpyhfr", 0x36C1F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* cmpyhfr 0,limm,s12 00110110100000011111ssssssSSSSSS. */ +{ "cmpyhfr", 0x3681F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* cmpyhfr a,limm,limm 00110110000000011111111110AAAAAA. */ +{ "cmpyhfr", 0x3601FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* cmpyhfr 0,limm,limm 00110110000000011111111110111110. */ +{ "cmpyhfr", 0x3601FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* cmpyhfr<.cc> 0,limm,limm 001101101100000111111111100QQQQQ. */ +{ "cmpyhfr", 0x36C1FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* cmpyhnfr a,b,c 00110bbb000000001BBBCCCCCCAAAAAA. */ +{ "cmpyhnfr", 0x30008000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* cmpyhnfr 0,b,c 00110bbb000000101BBBCCCCCC111110. */ +{ "cmpyhnfr", 0x3002803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* cmpyhnfr<.cc> b,b,c 00110bbb110000101BBBCCCCCC0QQQQQ. */ +{ "cmpyhnfr", 0x30C28000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* cmpyhnfr a,b,u6 00110bbb010000101BBBuuuuuuAAAAAA. */ +{ "cmpyhnfr", 0x30428000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmpyhnfr 0,b,u6 00110bbb010000101BBBuuuuuu111110. */ +{ "cmpyhnfr", 0x3042803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmpyhnfr<.cc> b,b,u6 00110bbb110000101BBBuuuuuu1QQQQQ. */ +{ "cmpyhnfr", 0x30C28020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* cmpyhnfr b,b,s12 00110bbb100000101BBBssssssSSSSSS. */ +{ "cmpyhnfr", 0x30828000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* cmpyhnfr a,limm,c 00110110000000101111CCCCCCAAAAAA. */ +{ "cmpyhnfr", 0x3602F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* cmpyhnfr a,b,limm 00110bbb000000101BBB111110AAAAAA. */ +{ "cmpyhnfr", 0x30028F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* cmpyhnfr 0,limm,c 00110110000000101111CCCCCC111110. */ +{ "cmpyhnfr", 0x3602F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* cmpyhnfr 0,b,limm 00110bbb000000101BBB111110111110. */ +{ "cmpyhnfr", 0x30028FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* cmpyhnfr<.cc> 0,limm,c 00110bbb110000101BBB1111100QQQQQ. */ +{ "cmpyhnfr", 0x30C28F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* cmpyhnfr<.cc> b,b,limm 00110110110000101111CCCCCC0QQQQQ. */ +{ "cmpyhnfr", 0x36C2F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* cmpyhnfr a,limm,u6 00110110010000101111uuuuuuAAAAAA. */ +{ "cmpyhnfr", 0x3642F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmpyhnfr 0,limm,u6 00110110010000101111uuuuuu111110. */ +{ "cmpyhnfr", 0x3642F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* cmpyhnfr<.cc> 0,limm,u6 00110110110000101111uuuuuu1QQQQQ. */ +{ "cmpyhnfr", 0x36C2F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* cmpyhnfr 0,limm,s12 00110110100000101111ssssssSSSSSS. */ +{ "cmpyhnfr", 0x3682F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* cmpyhnfr a,limm,limm 00110110000000101111111110AAAAAA. */ +{ "cmpyhnfr", 0x3602FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* cmpyhnfr 0,limm,limm 00110110000000101111111110111110. */ +{ "cmpyhnfr", 0x3602FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* cmpyhnfr<.cc> 0,limm,limm 001101101100001011111111100QQQQQ. */ +{ "cmpyhnfr", 0x36C2FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* cmp_s b,h 01110bbbhhh10HHH. */ +{ "cmp_s", 0x00007010, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB_S, OPERAND_R6H }, { 0 }}, + +/* cmp_s b,h 01110bbbhhh100HH. */ +{ "cmp_s", 0x00007010, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RH_S }, { 0 }}, + +/* cmp_s h,s3 01110ssshhh101HH. */ +{ "cmp_s", 0x00007014, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RH_S, OPERAND_SIMM3_5_S }, { 0 }}, + +/* cmp_s b,u7 11100bbb1uuuuuuu. */ +{ "cmp_s", 0x0000E080, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_UIMM7_9_S }, { 0 }}, + +/* cmp_s b,limm 01110bbb11010111. */ +{ "cmp_s", 0x000070D7, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB_S, OPERAND_LIMM_S }, { 0 }}, + +/* cmp_s b,limm 01110bbb11010011. */ +{ "cmp_s", 0x000070D3, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_LIMM_S }, { 0 }}, + +/* cmp_s limm,s3 01110sss11010111. */ +{ "cmp_s", 0x000070D7, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM_S, OPERAND_SIMM3_5_S }, { 0 }}, + +/* crc<.f> a,b,c 00101bbb00101100FBBBCCCCCCAAAAAA. */ +{ "crc", 0x282C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* crc<.f> 0,b,c 00101bbb00101100FBBBCCCCCC111110. */ +{ "crc", 0x282C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* crc<.f><.cc> b,b,c 00101bbb11101100FBBBCCCCCC0QQQQQ. */ +{ "crc", 0x28EC0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* crc<.f> a,b,u6 00101bbb01101100FBBBuuuuuuAAAAAA. */ +{ "crc", 0x286C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* crc<.f> 0,b,u6 00101bbb01101100FBBBuuuuuu111110. */ +{ "crc", 0x286C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* crc<.f><.cc> b,b,u6 00101bbb11101100FBBBuuuuuu1QQQQQ. */ +{ "crc", 0x28EC0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* crc<.f> b,b,s12 00101bbb10101100FBBBssssssSSSSSS. */ +{ "crc", 0x28AC0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* crc<.f> a,limm,c 0010111000101100F111CCCCCCAAAAAA. */ +{ "crc", 0x2E2C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* crc<.f> a,b,limm 00101bbb00101100FBBB111110AAAAAA. */ +{ "crc", 0x282C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* crc<.f> 0,limm,c 0010111000101100F111CCCCCC111110. */ +{ "crc", 0x2E2C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* crc<.f> 0,b,limm 00101bbb00101100FBBB111110111110. */ +{ "crc", 0x282C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* crc<.f><.cc> 0,limm,c 0010111011101100F111CCCCCC0QQQQQ. */ +{ "crc", 0x2EEC7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* crc<.f><.cc> b,b,limm 00101bbb11101100FBBB1111100QQQQQ. */ +{ "crc", 0x28EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* crc<.f> a,limm,u6 0010111001101100F111uuuuuuAAAAAA. */ +{ "crc", 0x2E6C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* crc<.f> 0,limm,u6 0010111001101100F111uuuuuu111110. */ +{ "crc", 0x2E6C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* crc<.f><.cc> 0,limm,u6 0010111011101100F111uuuuuu1QQQQQ. */ +{ "crc", 0x2EEC7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* crc<.f> 0,limm,s12 0010111010101100F111ssssssSSSSSS. */ +{ "crc", 0x2EAC7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* crc<.f> a,limm,limm 0010111000101100F111111110AAAAAA. */ +{ "crc", 0x2E2C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* crc<.f> 0,limm,limm 0010111000101100F111111110111110. */ +{ "crc", 0x2E2C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* crc<.f><.cc> 0,limm,limm 0010111011101100F1111111100QQQQQ. */ +{ "crc", 0x2EEC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* daddh11<.f> a,b,c 00110bbb00001100FBBBCCCCCCAAAAAA. */ +{ "daddh11", 0x300C0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* daddh11<.f> 0,b,c 00110bbb00001100FBBBCCCCCC111110. */ +{ "daddh11", 0x300C003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* daddh11<.f><.cc> b,b,c 00110bbb11001100FBBBCCCCCC0QQQQQ. */ +{ "daddh11", 0x30CC0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* daddh11<.f> a,b,c 00110bbb00110100FBBBCCCCCCAAAAAA. */ +{ "daddh11", 0x30340000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* daddh11<.f> 0,b,c 00110bbb00110100FBBBCCCCCC111110. */ +{ "daddh11", 0x3034003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* daddh11<.f><.cc> b,b,c 00110bbb11110100FBBBCCCCCC0QQQQQ. */ +{ "daddh11", 0x30F40000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* daddh11<.f> a,b,u6 00110bbb01001100FBBBuuuuuuAAAAAA. */ +{ "daddh11", 0x304C0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh11<.f> 0,b,u6 00110bbb01001100FBBBuuuuuu111110. */ +{ "daddh11", 0x304C003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh11<.f><.cc> b,b,u6 00110bbb11001100FBBBuuuuuu1QQQQQ. */ +{ "daddh11", 0x30CC0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* daddh11<.f> a,b,u6 00110bbb01110100FBBBuuuuuuAAAAAA. */ +{ "daddh11", 0x30740000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh11<.f> 0,b,u6 00110bbb01110100FBBBuuuuuu111110. */ +{ "daddh11", 0x3074003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh11<.f><.cc> b,b,u6 00110bbb11110100FBBBuuuuuu1QQQQQ. */ +{ "daddh11", 0x30F40020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* daddh11<.f> b,b,s12 00110bbb10001100FBBBssssssSSSSSS. */ +{ "daddh11", 0x308C0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* daddh11<.f> b,b,s12 00110bbb10110100FBBBssssssSSSSSS. */ +{ "daddh11", 0x30B40000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* daddh11<.f> a,limm,c 0011011000001100F111CCCCCCAAAAAA. */ +{ "daddh11", 0x360C7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* daddh11<.f> a,b,limm 00110bbb00001100FBBB111110AAAAAA. */ +{ "daddh11", 0x300C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* daddh11<.f> 0,limm,c 0011011000001100F111CCCCCC111110. */ +{ "daddh11", 0x360C703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* daddh11<.f> 0,b,limm 00110bbb00001100FBBB111110111110. */ +{ "daddh11", 0x300C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* daddh11<.f><.cc> 0,limm,c 0011011011001100F111CCCCCC0QQQQQ. */ +{ "daddh11", 0x36CC7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* daddh11<.f><.cc> b,b,limm 00110bbb11001100FBBB1111100QQQQQ. */ +{ "daddh11", 0x30CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* daddh11<.f> a,limm,c 0011011000110100F111CCCCCCAAAAAA. */ +{ "daddh11", 0x36347000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* daddh11<.f> a,b,limm 00110bbb00110100FBBB111110AAAAAA. */ +{ "daddh11", 0x30340F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* daddh11<.f> 0,limm,c 0011011000110100F111CCCCCC111110. */ +{ "daddh11", 0x3634703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* daddh11<.f> 0,b,limm 00110bbb00110100FBBB111110111110. */ +{ "daddh11", 0x30340FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* daddh11<.f><.cc> 0,limm,c 0011011011110100F111CCCCCC0QQQQQ. */ +{ "daddh11", 0x36F47000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* daddh11<.f><.cc> b,b,limm 00110bbb11110100FBBB1111100QQQQQ. */ +{ "daddh11", 0x30F40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* daddh11<.f> a,limm,u6 0011011001001100F111uuuuuuAAAAAA. */ +{ "daddh11", 0x364C7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh11<.f> 0,limm,u6 0011011001001100F111uuuuuu111110. */ +{ "daddh11", 0x364C703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh11<.f><.cc> 0,limm,u6 0011011011001100F111uuuuuu1QQQQQ. */ +{ "daddh11", 0x36CC7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* daddh11<.f> a,limm,u6 0011011001110100F111uuuuuuAAAAAA. */ +{ "daddh11", 0x36747000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh11<.f> 0,limm,u6 0011011001110100F111uuuuuu111110. */ +{ "daddh11", 0x3674703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh11<.f><.cc> 0,limm,u6 0011011011110100F111uuuuuu1QQQQQ. */ +{ "daddh11", 0x36F47020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* daddh11<.f> 0,limm,s12 0011011010001100F111ssssssSSSSSS. */ +{ "daddh11", 0x368C7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* daddh11<.f> 0,limm,s12 0011011010110100F111ssssssSSSSSS. */ +{ "daddh11", 0x36B47000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* daddh11<.f> a,limm,limm 0011011000001100F111111110AAAAAA. */ +{ "daddh11", 0x360C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* daddh11<.f> 0,limm,limm 0011011000001100F111111110111110. */ +{ "daddh11", 0x360C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* daddh11<.f><.cc> 0,limm,limm 0011011011001100F1111111100QQQQQ. */ +{ "daddh11", 0x36CC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* daddh11<.f> a,limm,limm 0011011000110100F111111110AAAAAA. */ +{ "daddh11", 0x36347F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* daddh11<.f> 0,limm,limm 0011011000110100F111111110111110. */ +{ "daddh11", 0x36347FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* daddh11<.f><.cc> 0,limm,limm 0011011011110100F1111111100QQQQQ. */ +{ "daddh11", 0x36F47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* daddh12<.f> a,b,c 00110bbb00001101FBBBCCCCCCAAAAAA. */ +{ "daddh12", 0x300D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* daddh12<.f> 0,b,c 00110bbb00001101FBBBCCCCCC111110. */ +{ "daddh12", 0x300D003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* daddh12<.f><.cc> b,b,c 00110bbb11001101FBBBCCCCCC0QQQQQ. */ +{ "daddh12", 0x30CD0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* daddh12<.f> a,b,c 00110bbb00110101FBBBCCCCCCAAAAAA. */ +{ "daddh12", 0x30350000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* daddh12<.f> 0,b,c 00110bbb00110101FBBBCCCCCC111110. */ +{ "daddh12", 0x3035003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* daddh12<.f><.cc> b,b,c 00110bbb11110101FBBBCCCCCC0QQQQQ. */ +{ "daddh12", 0x30F50000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* daddh12<.f> a,b,u6 00110bbb01001101FBBBuuuuuuAAAAAA. */ +{ "daddh12", 0x304D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh12<.f> 0,b,u6 00110bbb01001101FBBBuuuuuu111110. */ +{ "daddh12", 0x304D003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh12<.f><.cc> b,b,u6 00110bbb11001101FBBBuuuuuu1QQQQQ. */ +{ "daddh12", 0x30CD0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* daddh12<.f> a,b,u6 00110bbb01110101FBBBuuuuuuAAAAAA. */ +{ "daddh12", 0x30750000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh12<.f> 0,b,u6 00110bbb01110101FBBBuuuuuu111110. */ +{ "daddh12", 0x3075003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh12<.f><.cc> b,b,u6 00110bbb11110101FBBBuuuuuu1QQQQQ. */ +{ "daddh12", 0x30F50020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* daddh12<.f> b,b,s12 00110bbb10001101FBBBssssssSSSSSS. */ +{ "daddh12", 0x308D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* daddh12<.f> b,b,s12 00110bbb10110101FBBBssssssSSSSSS. */ +{ "daddh12", 0x30B50000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* daddh12<.f> a,limm,c 0011011000001101F111CCCCCCAAAAAA. */ +{ "daddh12", 0x360D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* daddh12<.f> a,b,limm 00110bbb00001101FBBB111110AAAAAA. */ +{ "daddh12", 0x300D0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* daddh12<.f> 0,limm,c 0011011000001101F111CCCCCC111110. */ +{ "daddh12", 0x360D703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* daddh12<.f> 0,b,limm 00110bbb00001101FBBB111110111110. */ +{ "daddh12", 0x300D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* daddh12<.f><.cc> 0,limm,c 0011011011001101F111CCCCCC0QQQQQ. */ +{ "daddh12", 0x36CD7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* daddh12<.f><.cc> b,b,limm 00110bbb11001101FBBB1111100QQQQQ. */ +{ "daddh12", 0x30CD0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* daddh12<.f> a,limm,c 0011011000110101F111CCCCCCAAAAAA. */ +{ "daddh12", 0x36357000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* daddh12<.f> a,b,limm 00110bbb00110101FBBB111110AAAAAA. */ +{ "daddh12", 0x30350F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* daddh12<.f> 0,limm,c 0011011000110101F111CCCCCC111110. */ +{ "daddh12", 0x3635703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* daddh12<.f> 0,b,limm 00110bbb00110101FBBB111110111110. */ +{ "daddh12", 0x30350FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* daddh12<.f><.cc> 0,limm,c 0011011011110101F111CCCCCC0QQQQQ. */ +{ "daddh12", 0x36F57000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* daddh12<.f><.cc> b,b,limm 00110bbb11110101FBBB1111100QQQQQ. */ +{ "daddh12", 0x30F50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* daddh12<.f> a,limm,u6 0011011001001101F111uuuuuuAAAAAA. */ +{ "daddh12", 0x364D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh12<.f> 0,limm,u6 0011011001001101F111uuuuuu111110. */ +{ "daddh12", 0x364D703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh12<.f><.cc> 0,limm,u6 0011011011001101F111uuuuuu1QQQQQ. */ +{ "daddh12", 0x36CD7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* daddh12<.f> a,limm,u6 0011011001110101F111uuuuuuAAAAAA. */ +{ "daddh12", 0x36757000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh12<.f> 0,limm,u6 0011011001110101F111uuuuuu111110. */ +{ "daddh12", 0x3675703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh12<.f><.cc> 0,limm,u6 0011011011110101F111uuuuuu1QQQQQ. */ +{ "daddh12", 0x36F57020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* daddh12<.f> 0,limm,s12 0011011010001101F111ssssssSSSSSS. */ +{ "daddh12", 0x368D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* daddh12<.f> 0,limm,s12 0011011010110101F111ssssssSSSSSS. */ +{ "daddh12", 0x36B57000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* daddh12<.f> a,limm,limm 0011011000001101F111111110AAAAAA. */ +{ "daddh12", 0x360D7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* daddh12<.f> 0,limm,limm 0011011000001101F111111110111110. */ +{ "daddh12", 0x360D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* daddh12<.f><.cc> 0,limm,limm 0011011011001101F1111111100QQQQQ. */ +{ "daddh12", 0x36CD7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* daddh12<.f> a,limm,limm 0011011000110101F111111110AAAAAA. */ +{ "daddh12", 0x36357F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* daddh12<.f> 0,limm,limm 0011011000110101F111111110111110. */ +{ "daddh12", 0x36357FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* daddh12<.f><.cc> 0,limm,limm 0011011011110101F1111111100QQQQQ. */ +{ "daddh12", 0x36F57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* daddh21<.f> a,b,c 00110bbb00001110FBBBCCCCCCAAAAAA. */ +{ "daddh21", 0x300E0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* daddh21<.f> 0,b,c 00110bbb00001110FBBBCCCCCC111110. */ +{ "daddh21", 0x300E003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* daddh21<.f><.cc> b,b,c 00110bbb11001110FBBBCCCCCC0QQQQQ. */ +{ "daddh21", 0x30CE0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* daddh21<.f> a,b,c 00110bbb00110110FBBBCCCCCCAAAAAA. */ +{ "daddh21", 0x30360000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* daddh21<.f> 0,b,c 00110bbb00110110FBBBCCCCCC111110. */ +{ "daddh21", 0x3036003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* daddh21<.f><.cc> b,b,c 00110bbb11110110FBBBCCCCCC0QQQQQ. */ +{ "daddh21", 0x30F60000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* daddh21<.f> a,b,u6 00110bbb01001110FBBBuuuuuuAAAAAA. */ +{ "daddh21", 0x304E0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh21<.f> 0,b,u6 00110bbb01001110FBBBuuuuuu111110. */ +{ "daddh21", 0x304E003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh21<.f><.cc> b,b,u6 00110bbb11001110FBBBuuuuuu1QQQQQ. */ +{ "daddh21", 0x30CE0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* daddh21<.f> a,b,u6 00110bbb01110110FBBBuuuuuuAAAAAA. */ +{ "daddh21", 0x30760000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh21<.f> 0,b,u6 00110bbb01110110FBBBuuuuuu111110. */ +{ "daddh21", 0x3076003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh21<.f><.cc> b,b,u6 00110bbb11110110FBBBuuuuuu1QQQQQ. */ +{ "daddh21", 0x30F60020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* daddh21<.f> b,b,s12 00110bbb10001110FBBBssssssSSSSSS. */ +{ "daddh21", 0x308E0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* daddh21<.f> b,b,s12 00110bbb10110110FBBBssssssSSSSSS. */ +{ "daddh21", 0x30B60000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* daddh21<.f> a,limm,c 0011011000001110F111CCCCCCAAAAAA. */ +{ "daddh21", 0x360E7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* daddh21<.f> a,b,limm 00110bbb00001110FBBB111110AAAAAA. */ +{ "daddh21", 0x300E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* daddh21<.f> 0,limm,c 0011011000001110F111CCCCCC111110. */ +{ "daddh21", 0x360E703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* daddh21<.f> 0,b,limm 00110bbb00001110FBBB111110111110. */ +{ "daddh21", 0x300E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* daddh21<.f><.cc> 0,limm,c 0011011011001110F111CCCCCC0QQQQQ. */ +{ "daddh21", 0x36CE7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* daddh21<.f><.cc> b,b,limm 00110bbb11001110FBBB1111100QQQQQ. */ +{ "daddh21", 0x30CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* daddh21<.f> a,limm,c 0011011000110110F111CCCCCCAAAAAA. */ +{ "daddh21", 0x36367000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* daddh21<.f> a,b,limm 00110bbb00110110FBBB111110AAAAAA. */ +{ "daddh21", 0x30360F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* daddh21<.f> 0,limm,c 0011011000110110F111CCCCCC111110. */ +{ "daddh21", 0x3636703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* daddh21<.f> 0,b,limm 00110bbb00110110FBBB111110111110. */ +{ "daddh21", 0x30360FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* daddh21<.f><.cc> 0,limm,c 0011011011110110F111CCCCCC0QQQQQ. */ +{ "daddh21", 0x36F67000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* daddh21<.f><.cc> b,b,limm 00110bbb11110110FBBB1111100QQQQQ. */ +{ "daddh21", 0x30F60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* daddh21<.f> a,limm,u6 0011011001001110F111uuuuuuAAAAAA. */ +{ "daddh21", 0x364E7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh21<.f> 0,limm,u6 0011011001001110F111uuuuuu111110. */ +{ "daddh21", 0x364E703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh21<.f><.cc> 0,limm,u6 0011011011001110F111uuuuuu1QQQQQ. */ +{ "daddh21", 0x36CE7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* daddh21<.f> a,limm,u6 0011011001110110F111uuuuuuAAAAAA. */ +{ "daddh21", 0x36767000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh21<.f> 0,limm,u6 0011011001110110F111uuuuuu111110. */ +{ "daddh21", 0x3676703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh21<.f><.cc> 0,limm,u6 0011011011110110F111uuuuuu1QQQQQ. */ +{ "daddh21", 0x36F67020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* daddh21<.f> 0,limm,s12 0011011010001110F111ssssssSSSSSS. */ +{ "daddh21", 0x368E7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* daddh21<.f> 0,limm,s12 0011011010110110F111ssssssSSSSSS. */ +{ "daddh21", 0x36B67000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* daddh21<.f> a,limm,limm 0011011000001110F111111110AAAAAA. */ +{ "daddh21", 0x360E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* daddh21<.f> 0,limm,limm 0011011000001110F111111110111110. */ +{ "daddh21", 0x360E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* daddh21<.f><.cc> 0,limm,limm 0011011011001110F1111111100QQQQQ. */ +{ "daddh21", 0x36CE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* daddh21<.f> a,limm,limm 0011011000110110F111111110AAAAAA. */ +{ "daddh21", 0x36367F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* daddh21<.f> 0,limm,limm 0011011000110110F111111110111110. */ +{ "daddh21", 0x36367FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* daddh21<.f><.cc> 0,limm,limm 0011011011110110F1111111100QQQQQ. */ +{ "daddh21", 0x36F67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* daddh22<.f> a,b,c 00110bbb00001111FBBBCCCCCCAAAAAA. */ +{ "daddh22", 0x300F0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* daddh22<.f> 0,b,c 00110bbb00001111FBBBCCCCCC111110. */ +{ "daddh22", 0x300F003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* daddh22<.f><.cc> b,b,c 00110bbb11001111FBBBCCCCCC0QQQQQ. */ +{ "daddh22", 0x30CF0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* daddh22<.f> a,b,c 00110bbb00110111FBBBCCCCCCAAAAAA. */ +{ "daddh22", 0x30370000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* daddh22<.f> 0,b,c 00110bbb00110111FBBBCCCCCC111110. */ +{ "daddh22", 0x3037003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* daddh22<.f><.cc> b,b,c 00110bbb11110111FBBBCCCCCC0QQQQQ. */ +{ "daddh22", 0x30F70000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* daddh22<.f> a,b,u6 00110bbb01001111FBBBuuuuuuAAAAAA. */ +{ "daddh22", 0x304F0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh22<.f> 0,b,u6 00110bbb01001111FBBBuuuuuu111110. */ +{ "daddh22", 0x304F003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh22<.f><.cc> b,b,u6 00110bbb11001111FBBBuuuuuu1QQQQQ. */ +{ "daddh22", 0x30CF0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* daddh22<.f> a,b,u6 00110bbb01110111FBBBuuuuuuAAAAAA. */ +{ "daddh22", 0x30770000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh22<.f> 0,b,u6 00110bbb01110111FBBBuuuuuu111110. */ +{ "daddh22", 0x3077003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh22<.f><.cc> b,b,u6 00110bbb11110111FBBBuuuuuu1QQQQQ. */ +{ "daddh22", 0x30F70020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* daddh22<.f> b,b,s12 00110bbb10001111FBBBssssssSSSSSS. */ +{ "daddh22", 0x308F0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* daddh22<.f> b,b,s12 00110bbb10110111FBBBssssssSSSSSS. */ +{ "daddh22", 0x30B70000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* daddh22<.f> a,limm,c 0011011000001111F111CCCCCCAAAAAA. */ +{ "daddh22", 0x360F7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* daddh22<.f> a,b,limm 00110bbb00001111FBBB111110AAAAAA. */ +{ "daddh22", 0x300F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* daddh22<.f> 0,limm,c 0011011000001111F111CCCCCC111110. */ +{ "daddh22", 0x360F703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* daddh22<.f> 0,b,limm 00110bbb00001111FBBB111110111110. */ +{ "daddh22", 0x300F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* daddh22<.f><.cc> 0,limm,c 0011011011001111F111CCCCCC0QQQQQ. */ +{ "daddh22", 0x36CF7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* daddh22<.f><.cc> b,b,limm 00110bbb11001111FBBB1111100QQQQQ. */ +{ "daddh22", 0x30CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* daddh22<.f> a,limm,c 0011011000110111F111CCCCCCAAAAAA. */ +{ "daddh22", 0x36377000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* daddh22<.f> a,b,limm 00110bbb00110111FBBB111110AAAAAA. */ +{ "daddh22", 0x30370F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* daddh22<.f> 0,limm,c 0011011000110111F111CCCCCC111110. */ +{ "daddh22", 0x3637703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* daddh22<.f> 0,b,limm 00110bbb00110111FBBB111110111110. */ +{ "daddh22", 0x30370FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* daddh22<.f><.cc> 0,limm,c 0011011011110111F111CCCCCC0QQQQQ. */ +{ "daddh22", 0x36F77000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* daddh22<.f><.cc> b,b,limm 00110bbb11110111FBBB1111100QQQQQ. */ +{ "daddh22", 0x30F70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* daddh22<.f> a,limm,u6 0011011001001111F111uuuuuuAAAAAA. */ +{ "daddh22", 0x364F7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh22<.f> 0,limm,u6 0011011001001111F111uuuuuu111110. */ +{ "daddh22", 0x364F703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh22<.f><.cc> 0,limm,u6 0011011011001111F111uuuuuu1QQQQQ. */ +{ "daddh22", 0x36CF7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* daddh22<.f> a,limm,u6 0011011001110111F111uuuuuuAAAAAA. */ +{ "daddh22", 0x36777000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh22<.f> 0,limm,u6 0011011001110111F111uuuuuu111110. */ +{ "daddh22", 0x3677703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* daddh22<.f><.cc> 0,limm,u6 0011011011110111F111uuuuuu1QQQQQ. */ +{ "daddh22", 0x36F77020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* daddh22<.f> 0,limm,s12 0011011010001111F111ssssssSSSSSS. */ +{ "daddh22", 0x368F7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* daddh22<.f> 0,limm,s12 0011011010110111F111ssssssSSSSSS. */ +{ "daddh22", 0x36B77000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* daddh22<.f> a,limm,limm 0011011000001111F111111110AAAAAA. */ +{ "daddh22", 0x360F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* daddh22<.f> 0,limm,limm 0011011000001111F111111110111110. */ +{ "daddh22", 0x360F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* daddh22<.f><.cc> 0,limm,limm 0011011011001111F1111111100QQQQQ. */ +{ "daddh22", 0x36CF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* daddh22<.f> a,limm,limm 0011011000110111F111111110AAAAAA. */ +{ "daddh22", 0x36377F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* daddh22<.f> 0,limm,limm 0011011000110111F111111110111110. */ +{ "daddh22", 0x36377FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* daddh22<.f><.cc> 0,limm,limm 0011011011110111F1111111100QQQQQ. */ +{ "daddh22", 0x36F77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dbnz<.d> b,s13 00100bbb1000110N0BBBssssssSSSSSS. */ +{ "dbnz", 0x208C0000, 0xF8FE8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { OPERAND_RB, OPERAND_SIMM13_A16_20}, { C_DNZ_D }}, + +/* dexcl1<.f> a,b,c 00110bbb00011000FBBBCCCCCCAAAAAA. */ +{ "dexcl1", 0x30180000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dexcl1<.f> 0,b,c 00110bbb00011000FBBBCCCCCC111110. */ +{ "dexcl1", 0x3018003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dexcl1<.f><.cc> b,b,c 00110bbb11011000FBBBCCCCCC0QQQQQ. */ +{ "dexcl1", 0x30D80000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dexcl1<.f> a,b,c 00110bbb00111100FBBBCCCCCCAAAAAA. */ +{ "dexcl1", 0x303C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dexcl1<.f> 0,b,c 00110bbb00111100FBBBCCCCCC111110. */ +{ "dexcl1", 0x303C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dexcl1<.f><.cc> b,b,c 00110bbb11111100FBBBCCCCCC0QQQQQ. */ +{ "dexcl1", 0x30FC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dexcl1<.f> a,b,u6 00110bbb01011000FBBBuuuuuuAAAAAA. */ +{ "dexcl1", 0x30580000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dexcl1<.f> 0,b,u6 00110bbb01011000FBBBuuuuuu111110. */ +{ "dexcl1", 0x3058003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dexcl1<.f><.cc> b,b,u6 00110bbb11011000FBBBuuuuuu1QQQQQ. */ +{ "dexcl1", 0x30D80020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dexcl1<.f> a,b,u6 00110bbb01111100FBBBuuuuuuAAAAAA. */ +{ "dexcl1", 0x307C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dexcl1<.f> 0,b,u6 00110bbb01111100FBBBuuuuuu111110. */ +{ "dexcl1", 0x307C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dexcl1<.f><.cc> b,b,u6 00110bbb11111100FBBBuuuuuu1QQQQQ. */ +{ "dexcl1", 0x30FC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dexcl1<.f> b,b,s12 00110bbb10011000FBBBssssssSSSSSS. */ +{ "dexcl1", 0x30980000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dexcl1<.f> b,b,s12 00110bbb10111100FBBBssssssSSSSSS. */ +{ "dexcl1", 0x30BC0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dexcl1<.f> a,limm,c 0011011000011000F111CCCCCCAAAAAA. */ +{ "dexcl1", 0x36187000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dexcl1<.f> a,b,limm 00110bbb00011000FBBB111110AAAAAA. */ +{ "dexcl1", 0x30180F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dexcl1<.f> 0,limm,c 0011011000011000F111CCCCCC111110. */ +{ "dexcl1", 0x3618703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dexcl1<.f> 0,b,limm 00110bbb00011000FBBB111110111110. */ +{ "dexcl1", 0x30180FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dexcl1<.f><.cc> 0,limm,c 0011011011011000F111CCCCCC0QQQQQ. */ +{ "dexcl1", 0x36D87000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dexcl1<.f><.cc> b,b,limm 00110bbb11011000FBBB1111100QQQQQ. */ +{ "dexcl1", 0x30D80F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dexcl1<.f> a,limm,c 0011011000111100F111CCCCCCAAAAAA. */ +{ "dexcl1", 0x363C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dexcl1<.f> a,b,limm 00110bbb00111100FBBB111110AAAAAA. */ +{ "dexcl1", 0x303C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dexcl1<.f> 0,limm,c 0011011000111100F111CCCCCC111110. */ +{ "dexcl1", 0x363C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dexcl1<.f> 0,b,limm 00110bbb00111100FBBB111110111110. */ +{ "dexcl1", 0x303C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dexcl1<.f><.cc> 0,limm,c 0011011011111100F111CCCCCC0QQQQQ. */ +{ "dexcl1", 0x36FC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dexcl1<.f><.cc> b,b,limm 00110bbb11111100FBBB1111100QQQQQ. */ +{ "dexcl1", 0x30FC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dexcl1<.f> a,limm,u6 0011011001011000F111uuuuuuAAAAAA. */ +{ "dexcl1", 0x36587000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dexcl1<.f> 0,limm,u6 0011011001011000F111uuuuuu111110. */ +{ "dexcl1", 0x3658703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dexcl1<.f><.cc> 0,limm,u6 0011011011011000F111uuuuuu1QQQQQ. */ +{ "dexcl1", 0x36D87020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dexcl1<.f> a,limm,u6 0011011001111100F111uuuuuuAAAAAA. */ +{ "dexcl1", 0x367C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dexcl1<.f> 0,limm,u6 0011011001111100F111uuuuuu111110. */ +{ "dexcl1", 0x367C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dexcl1<.f><.cc> 0,limm,u6 0011011011111100F111uuuuuu1QQQQQ. */ +{ "dexcl1", 0x36FC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dexcl1<.f> 0,limm,s12 0011011010011000F111ssssssSSSSSS. */ +{ "dexcl1", 0x36987000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dexcl1<.f> 0,limm,s12 0011011010111100F111ssssssSSSSSS. */ +{ "dexcl1", 0x36BC7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dexcl1<.f> a,limm,limm 0011011000011000F111111110AAAAAA. */ +{ "dexcl1", 0x36187F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dexcl1<.f> 0,limm,limm 0011011000011000F111111110111110. */ +{ "dexcl1", 0x36187FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dexcl1<.f><.cc> 0,limm,limm 0011011011011000F1111111100QQQQQ. */ +{ "dexcl1", 0x36D87F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dexcl1<.f> a,limm,limm 0011011000111100F111111110AAAAAA. */ +{ "dexcl1", 0x363C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dexcl1<.f> 0,limm,limm 0011011000111100F111111110111110. */ +{ "dexcl1", 0x363C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dexcl1<.f><.cc> 0,limm,limm 0011011011111100F1111111100QQQQQ. */ +{ "dexcl1", 0x36FC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dexcl2<.f> a,b,c 00110bbb00011001FBBBCCCCCCAAAAAA. */ +{ "dexcl2", 0x30190000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dexcl2<.f> 0,b,c 00110bbb00011001FBBBCCCCCC111110. */ +{ "dexcl2", 0x3019003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dexcl2<.f><.cc> b,b,c 00110bbb11011001FBBBCCCCCC0QQQQQ. */ +{ "dexcl2", 0x30D90000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dexcl2<.f> a,b,c 00110bbb00111101FBBBCCCCCCAAAAAA. */ +{ "dexcl2", 0x303D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dexcl2<.f> 0,b,c 00110bbb00111101FBBBCCCCCC111110. */ +{ "dexcl2", 0x303D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dexcl2<.f><.cc> b,b,c 00110bbb11111101FBBBCCCCCC0QQQQQ. */ +{ "dexcl2", 0x30FD0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dexcl2<.f> a,b,u6 00110bbb01011001FBBBuuuuuuAAAAAA. */ +{ "dexcl2", 0x30590000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dexcl2<.f> 0,b,u6 00110bbb01011001FBBBuuuuuu111110. */ +{ "dexcl2", 0x3059003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dexcl2<.f><.cc> b,b,u6 00110bbb11011001FBBBuuuuuu1QQQQQ. */ +{ "dexcl2", 0x30D90020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dexcl2<.f> a,b,u6 00110bbb01111101FBBBuuuuuuAAAAAA. */ +{ "dexcl2", 0x307D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dexcl2<.f> 0,b,u6 00110bbb01111101FBBBuuuuuu111110. */ +{ "dexcl2", 0x307D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dexcl2<.f><.cc> b,b,u6 00110bbb11111101FBBBuuuuuu1QQQQQ. */ +{ "dexcl2", 0x30FD0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dexcl2<.f> b,b,s12 00110bbb10011001FBBBssssssSSSSSS. */ +{ "dexcl2", 0x30990000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dexcl2<.f> b,b,s12 00110bbb10111101FBBBssssssSSSSSS. */ +{ "dexcl2", 0x30BD0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dexcl2<.f> a,limm,c 0011011000011001F111CCCCCCAAAAAA. */ +{ "dexcl2", 0x36197000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dexcl2<.f> a,b,limm 00110bbb00011001FBBB111110AAAAAA. */ +{ "dexcl2", 0x30190F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dexcl2<.f> 0,limm,c 0011011000011001F111CCCCCC111110. */ +{ "dexcl2", 0x3619703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dexcl2<.f> 0,b,limm 00110bbb00011001FBBB111110111110. */ +{ "dexcl2", 0x30190FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dexcl2<.f><.cc> 0,limm,c 0011011011011001F111CCCCCC0QQQQQ. */ +{ "dexcl2", 0x36D97000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dexcl2<.f><.cc> b,b,limm 00110bbb11011001FBBB1111100QQQQQ. */ +{ "dexcl2", 0x30D90F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dexcl2<.f> a,limm,c 0011011000111101F111CCCCCCAAAAAA. */ +{ "dexcl2", 0x363D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dexcl2<.f> a,b,limm 00110bbb00111101FBBB111110AAAAAA. */ +{ "dexcl2", 0x303D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dexcl2<.f> 0,limm,c 0011011000111101F111CCCCCC111110. */ +{ "dexcl2", 0x363D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dexcl2<.f> 0,b,limm 00110bbb00111101FBBB111110111110. */ +{ "dexcl2", 0x303D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dexcl2<.f><.cc> 0,limm,c 0011011011111101F111CCCCCC0QQQQQ. */ +{ "dexcl2", 0x36FD7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dexcl2<.f><.cc> b,b,limm 00110bbb11111101FBBB1111100QQQQQ. */ +{ "dexcl2", 0x30FD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dexcl2<.f> a,limm,u6 0011011001011001F111uuuuuuAAAAAA. */ +{ "dexcl2", 0x36597000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dexcl2<.f> 0,limm,u6 0011011001011001F111uuuuuu111110. */ +{ "dexcl2", 0x3659703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dexcl2<.f><.cc> 0,limm,u6 0011011011011001F111uuuuuu1QQQQQ. */ +{ "dexcl2", 0x36D97020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dexcl2<.f> a,limm,u6 0011011001111101F111uuuuuuAAAAAA. */ +{ "dexcl2", 0x367D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dexcl2<.f> 0,limm,u6 0011011001111101F111uuuuuu111110. */ +{ "dexcl2", 0x367D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dexcl2<.f><.cc> 0,limm,u6 0011011011111101F111uuuuuu1QQQQQ. */ +{ "dexcl2", 0x36FD7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dexcl2<.f> 0,limm,s12 0011011010011001F111ssssssSSSSSS. */ +{ "dexcl2", 0x36997000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dexcl2<.f> 0,limm,s12 0011011010111101F111ssssssSSSSSS. */ +{ "dexcl2", 0x36BD7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dexcl2<.f> a,limm,limm 0011011000011001F111111110AAAAAA. */ +{ "dexcl2", 0x36197F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dexcl2<.f> 0,limm,limm 0011011000011001F111111110111110. */ +{ "dexcl2", 0x36197FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dexcl2<.f><.cc> 0,limm,limm 0011011011011001F1111111100QQQQQ. */ +{ "dexcl2", 0x36D97F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dexcl2<.f> a,limm,limm 0011011000111101F111111110AAAAAA. */ +{ "dexcl2", 0x363D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dexcl2<.f> 0,limm,limm 0011011000111101F111111110111110. */ +{ "dexcl2", 0x363D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dexcl2<.f><.cc> 0,limm,limm 0011011011111101F1111111100QQQQQ. */ +{ "dexcl2", 0x36FD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* div<.f> a,b,c 00101bbb00000100FBBBCCCCCCAAAAAA. */ +{ "div", 0x28040000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* div<.f> 0,b,c 00101bbb00000100FBBBCCCCCC111110. */ +{ "div", 0x2804003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* div<.f><.cc> b,b,c 00101bbb11000100FBBBCCCCCC0QQQQQ. */ +{ "div", 0x28C40000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* div<.f> a,b,u6 00101bbb01000100FBBBuuuuuuAAAAAA. */ +{ "div", 0x28440000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* div<.f> 0,b,u6 00101bbb01000100FBBBuuuuuu111110. */ +{ "div", 0x2844003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* div<.f><.cc> b,b,u6 00101bbb11000100FBBBuuuuuu1QQQQQ. */ +{ "div", 0x28C40020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* div<.f> b,b,s12 00101bbb10000100FBBBssssssSSSSSS. */ +{ "div", 0x28840000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* div<.f> a,limm,c 0010111000000100F111CCCCCCAAAAAA. */ +{ "div", 0x2E047000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* div<.f> a,b,limm 00101bbb00000100FBBB111110AAAAAA. */ +{ "div", 0x28040F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* div<.f> 0,limm,c 0010111000000100F111CCCCCC111110. */ +{ "div", 0x2E04703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* div<.f> 0,b,limm 00101bbb00000100FBBB111110111110. */ +{ "div", 0x28040FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* div<.f><.cc> b,b,limm 00101bbb11000100FBBB1111100QQQQQ. */ +{ "div", 0x28C40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* div<.f><.cc> 0,limm,c 0010111011000100F111CCCCCC0QQQQQ. */ +{ "div", 0x2EC47000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* div<.f> a,limm,u6 0010111001000100F111uuuuuuAAAAAA. */ +{ "div", 0x2E447000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* div<.f> 0,limm,u6 0010111001000100F111uuuuuu111110. */ +{ "div", 0x2E44703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* div<.f><.cc> 0,limm,u6 0010111011000100F111uuuuuu1QQQQQ. */ +{ "div", 0x2EC47020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* div<.f> 0,limm,s12 0010111010000100F111ssssssSSSSSS. */ +{ "div", 0x2E847000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* div<.f> a,limm,limm 0010111000000100F111111110AAAAAA. */ +{ "div", 0x2E047F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* div<.f> 0,limm,limm 0010111000000100F111111110111110. */ +{ "div", 0x2E047FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* div<.f><.cc> 0,limm,limm 0010111011000100F1111111100QQQQQ. */ +{ "div", 0x2EC47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* divacc c 00101011001011110000CCCCCC111111. */ +{ "divacc", 0x2B2F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RC }, { 0 }}, + +/* divacc u6 00101011011011110000uuuuuu111111. */ +{ "divacc", 0x2B6F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_UIMM6_20 }, { 0 }}, + +/* divaw<.f> a,b,c 00101bbb00001000FBBBCCCCCCAAAAAA. */ +{ "divaw", 0x28080000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* divaw<.f> 0,b,c 00101bbb00001000FBBBCCCCCC111110. */ +{ "divaw", 0x2808003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* divaw<.f><.cc> b,b,c 00101bbb11001000FBBBCCCCCC0QQQQQ. */ +{ "divaw", 0x28C80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* divaw<.f> a,b,u6 00101bbb01001000FBBBuuuuuuAAAAAA. */ +{ "divaw", 0x28480000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* divaw<.f> 0,b,u6 00101bbb01001000FBBBuuuuuu111110. */ +{ "divaw", 0x2848003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* divaw<.f><.cc> b,b,u6 00101bbb11001000FBBBuuuuuu1QQQQQ. */ +{ "divaw", 0x28C80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* divaw<.f> b,b,s12 00101bbb10001000FBBBssssssSSSSSS. */ +{ "divaw", 0x28880000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* divaw<.f> a,limm,c 0010111000001000F111CCCCCCAAAAAA. */ +{ "divaw", 0x2E087000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* divaw<.f> a,b,limm 00101bbb00001000FBBB111110AAAAAA. */ +{ "divaw", 0x28080F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* divaw<.f> 0,limm,c 0010111000001000F111CCCCCC111110. */ +{ "divaw", 0x2E08703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* divaw<.f> 0,b,limm 00101bbb00001000FBBB111110111110. */ +{ "divaw", 0x28080FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* divaw<.f><.cc> b,b,limm 00101bbb11001000FBBB1111100QQQQQ. */ +{ "divaw", 0x28C80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* divaw<.f><.cc> 0,limm,c 0010111011001000F111CCCCCC0QQQQQ. */ +{ "divaw", 0x2EC87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* divaw<.f> a,limm,u6 0010111001001000F111uuuuuuAAAAAA. */ +{ "divaw", 0x2E487000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* divaw<.f> 0,limm,u6 0010111001001000F111uuuuuu111110. */ +{ "divaw", 0x2E48703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* divaw<.f><.cc> 0,limm,u6 0010111011001000F111uuuuuu1QQQQQ. */ +{ "divaw", 0x2EC87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* divaw<.f> 0,limm,s12 0010111010001000F111ssssssSSSSSS. */ +{ "divaw", 0x2E887000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* divaw<.f> a,limm,limm 0010111000001000F111111110AAAAAA. */ +{ "divaw", 0x2E087F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* divaw<.f> 0,limm,limm 0010111000001000F111111110111110. */ +{ "divaw", 0x2E087FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* divaw<.f><.cc> 0,limm,limm 0010111011001000F1111111100QQQQQ. */ +{ "divaw", 0x2EC87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* divf<.f><.cc> b,b,c 00110bbb11010000FBBBCCCCCC0QQQQQ */ +{ "divf", 0x30D00000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* divf<.f> a,b,c 00110bbb00010000FBBBCCCCCCAAAAAA */ +{ "divf", 0x30100000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* divf<.f> 0,b,c 00110bbb00010000FBBBCCCCCC111110 */ +{ "divf", 0x3010003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* divf<.f> a,b,u6 00110bbb01010000FBBBuuuuuuAAAAAA */ +{ "divf", 0x30500000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* divf<.f> 0,b,u6 00110bbb01010000FBBBuuuuuu111110 */ +{ "divf", 0x3050003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* divf<.f><.cc> b,b,u6 00110bbb11010000FBBBuuuuuu1QQQQQ */ +{ "divf", 0x30D00020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* divf<.f> b,b,s12 00110bbb10010000FBBBssssssSSSSSS */ +{ "divf", 0x30900000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* divf<.f> a,b,limm 00110bbb00010000FBBB111110AAAAAA */ +{ "divf", 0x30100F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* divf<.f><.cc> b,b,limm 0011011011010000F111CCCCCC0QQQQQ */ +{ "divf", 0x36D07000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* divf<.f><.cc> 0,limm,c 00110bbb11010000FBBB1111100QQQQQ */ +{ "divf", 0x30D00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* divf<.f> 0,limm,c 0011011000010000F111CCCCCC111110 */ +{ "divf", 0x3610703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* divf<.f> 0,b,limm 00110bbb00010000FBBB111110111110 */ +{ "divf", 0x30100FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* divf<.f> a,limm,c 0011011000010000F111CCCCCCAAAAAA */ +{ "divf", 0x36107000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* divf<.f> 0,limm,u6 0011011001010000F111uuuuuu111110 */ +{ "divf", 0x3650703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* divf<.f> a,limm,u6 0011011001010000F111uuuuuuAAAAAA */ +{ "divf", 0x36507000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* divf<.f><.cc> 0,limm,u6 0011011011010000F111uuuuuu1QQQQQ */ +{ "divf", 0x36D07020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* divf<.f> 0,limm,s12 0011011010010000F111ssssssSSSSSS */ +{ "divf", 0x36907000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* divf<.f> 0,limm,limm 0011011000010000F111111110111110 */ +{ "divf", 0x36107FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* divf<.f> a,limm,limm 0011011000010000F111111110AAAAAA */ +{ "divf", 0x36107F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* divf<.f><.cc> 0,limm,limm 0011011011010000F1111111100QQQQQ */ +{ "divf", 0x36D07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* divu<.f> a,b,c 00101bbb00000101FBBBCCCCCCAAAAAA. */ +{ "divu", 0x28050000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* divu<.f> 0,b,c 00101bbb00000101FBBBCCCCCC111110. */ +{ "divu", 0x2805003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* divu<.f><.cc> b,b,c 00101bbb11000101FBBBCCCCCC0QQQQQ. */ +{ "divu", 0x28C50000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* divu<.f> a,b,u6 00101bbb01000101FBBBuuuuuuAAAAAA. */ +{ "divu", 0x28450000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* divu<.f> 0,b,u6 00101bbb01000101FBBBuuuuuu111110. */ +{ "divu", 0x2845003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* divu<.f><.cc> b,b,u6 00101bbb11000101FBBBuuuuuu1QQQQQ. */ +{ "divu", 0x28C50020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* divu<.f> b,b,s12 00101bbb10000101FBBBssssssSSSSSS. */ +{ "divu", 0x28850000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* divu<.f> a,limm,c 0010111000000101F111CCCCCCAAAAAA. */ +{ "divu", 0x2E057000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* divu<.f> a,b,limm 00101bbb00000101FBBB111110AAAAAA. */ +{ "divu", 0x28050F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* divu<.f> 0,limm,c 0010111000000101F111CCCCCC111110. */ +{ "divu", 0x2E05703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* divu<.f> 0,b,limm 00101bbb00000101FBBB111110111110. */ +{ "divu", 0x28050FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* divu<.f><.cc> b,b,limm 00101bbb11000101FBBB1111100QQQQQ. */ +{ "divu", 0x28C50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* divu<.f><.cc> 0,limm,c 0010111011000101F111CCCCCC0QQQQQ. */ +{ "divu", 0x2EC57000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* divu<.f> a,limm,u6 0010111001000101F111uuuuuuAAAAAA. */ +{ "divu", 0x2E457000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* divu<.f> 0,limm,u6 0010111001000101F111uuuuuu111110. */ +{ "divu", 0x2E45703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* divu<.f><.cc> 0,limm,u6 0010111011000101F111uuuuuu1QQQQQ. */ +{ "divu", 0x2EC57020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* divu<.f> 0,limm,s12 0010111010000101F111ssssssSSSSSS. */ +{ "divu", 0x2E857000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* divu<.f> a,limm,limm 0010111000000101F111111110AAAAAA. */ +{ "divu", 0x2E057F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* divu<.f> 0,limm,limm 0010111000000101F111111110111110. */ +{ "divu", 0x2E057FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* divu<.f><.cc> 0,limm,limm 0010111011000101F1111111100QQQQQ. */ +{ "divu", 0x2EC57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmach<.f> a,b,c 00101bbb00010010FBBBCCCCCCAAAAAA. */ +{ "dmach", 0x28120000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmach<.f> 0,b,c 00101bbb00010010FBBBCCCCCC111110. */ +{ "dmach", 0x2812003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmach<.f><.cc> b,b,c 00101bbb11010010FBBBCCCCCC0QQQQQ. */ +{ "dmach", 0x28D20000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmach<.f> a,b,u6 00101bbb01010010FBBBuuuuuuAAAAAA. */ +{ "dmach", 0x28520000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmach<.f> 0,b,u6 00101bbb01010010FBBBuuuuuu111110. */ +{ "dmach", 0x2852003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmach<.f><.cc> b,b,u6 00101bbb11010010FBBBuuuuuu1QQQQQ. */ +{ "dmach", 0x28D20020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmach<.f> b,b,s12 00101bbb10010010FBBBssssssSSSSSS. */ +{ "dmach", 0x28920000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmach<.f> a,limm,c 0010111000010010F111CCCCCCAAAAAA. */ +{ "dmach", 0x2E127000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmach<.f> a,b,limm 00101bbb00010010FBBB111110AAAAAA. */ +{ "dmach", 0x28120F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmach<.f> 0,limm,c 0010111000010010F111CCCCCC111110. */ +{ "dmach", 0x2E12703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmach<.f> 0,b,limm 00101bbb00010010FBBB111110111110. */ +{ "dmach", 0x28120FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmach<.f><.cc> b,b,limm 00101bbb11010010FBBB1111100QQQQQ. */ +{ "dmach", 0x28D20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmach<.f><.cc> 0,limm,c 0010111011010010F111CCCCCC0QQQQQ. */ +{ "dmach", 0x2ED27000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmach<.f> a,limm,u6 0010111001010010F111uuuuuuAAAAAA. */ +{ "dmach", 0x2E527000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmach<.f> 0,limm,u6 0010111001010010F111uuuuuu111110. */ +{ "dmach", 0x2E52703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmach<.f><.cc> 0,limm,u6 0010111011010010F111uuuuuu1QQQQQ. */ +{ "dmach", 0x2ED27020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmach<.f> 0,limm,s12 0010111010010010F111ssssssSSSSSS. */ +{ "dmach", 0x2E927000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmach<.f> a,limm,limm 0010111000010010F111111110AAAAAA. */ +{ "dmach", 0x2E127F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmach<.f> 0,limm,limm 0010111000010010F111111110111110. */ +{ "dmach", 0x2E127FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmach<.f><.cc> 0,limm,limm 0010111011010010F1111111100QQQQQ. */ +{ "dmach", 0x2ED27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmachbl<.f> a,b,c 00110bbb00011000FBBBCCCCCCAAAAAA. */ +{ "dmachbl", 0x30180000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmachbl<.f> 0,b,c 00110bbb00011000FBBBCCCCCC111110. */ +{ "dmachbl", 0x3018003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmachbl<.f><.cc> b,b,c 00110bbb11011000FBBBCCCCCC0QQQQQ. */ +{ "dmachbl", 0x30D80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmachbl<.f> a,b,u6 00110bbb01011000FBBBuuuuuuAAAAAA. */ +{ "dmachbl", 0x30580000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmachbl<.f> 0,b,u6 00110bbb01011000FBBBuuuuuu111110. */ +{ "dmachbl", 0x3058003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmachbl<.f><.cc> b,b,u6 00110bbb11011000FBBBuuuuuu1QQQQQ. */ +{ "dmachbl", 0x30D80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmachbl<.f> b,b,s12 00110bbb10011000FBBBssssssSSSSSS. */ +{ "dmachbl", 0x30980000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmachbl<.f> a,limm,c 0011011000011000F111CCCCCCAAAAAA. */ +{ "dmachbl", 0x36187000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmachbl<.f> a,b,limm 00110bbb00011000FBBB111110AAAAAA. */ +{ "dmachbl", 0x30180F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmachbl<.f> 0,limm,c 0011011000011000F111CCCCCC111110. */ +{ "dmachbl", 0x3618703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmachbl<.f> 0,b,limm 00110bbb00011000FBBB111110111110. */ +{ "dmachbl", 0x30180FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmachbl<.f><.cc> b,b,limm 00110bbb11011000FBBB1111100QQQQQ. */ +{ "dmachbl", 0x30D80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmachbl<.f><.cc> 0,limm,c 0011011011011000F111CCCCCC0QQQQQ. */ +{ "dmachbl", 0x36D87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmachbl<.f> a,limm,u6 0011011001011000F111uuuuuuAAAAAA. */ +{ "dmachbl", 0x36587000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmachbl<.f> 0,limm,u6 0011011001011000F111uuuuuu111110. */ +{ "dmachbl", 0x3658703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmachbl<.f><.cc> 0,limm,u6 0011011011011000F111uuuuuu1QQQQQ. */ +{ "dmachbl", 0x36D87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmachbl<.f> 0,limm,s12 0011011010011000F111ssssssSSSSSS. */ +{ "dmachbl", 0x36987000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmachbl<.f> a,limm,limm 0011011000011000F111111110AAAAAA. */ +{ "dmachbl", 0x36187F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmachbl<.f> 0,limm,limm 0011011000011000F111111110111110. */ +{ "dmachbl", 0x36187FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmachbl<.f><.cc> 0,limm,limm 0011011011011000F1111111100QQQQQ. */ +{ "dmachbl", 0x36D87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmachbm<.f> a,b,c 00110bbb00011001FBBBCCCCCCAAAAAA. */ +{ "dmachbm", 0x30190000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmachbm<.f> 0,b,c 00110bbb00011001FBBBCCCCCC111110. */ +{ "dmachbm", 0x3019003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmachbm<.f><.cc> b,b,c 00110bbb11011001FBBBCCCCCC0QQQQQ. */ +{ "dmachbm", 0x30D90000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmachbm<.f> a,b,u6 00110bbb01011001FBBBuuuuuuAAAAAA. */ +{ "dmachbm", 0x30590000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmachbm<.f> 0,b,u6 00110bbb01011001FBBBuuuuuu111110. */ +{ "dmachbm", 0x3059003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmachbm<.f><.cc> b,b,u6 00110bbb11011001FBBBuuuuuu1QQQQQ. */ +{ "dmachbm", 0x30D90020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmachbm<.f> b,b,s12 00110bbb10011001FBBBssssssSSSSSS. */ +{ "dmachbm", 0x30990000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmachbm<.f> a,limm,c 0011011000011001F111CCCCCCAAAAAA. */ +{ "dmachbm", 0x36197000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmachbm<.f> a,b,limm 00110bbb00011001FBBB111110AAAAAA. */ +{ "dmachbm", 0x30190F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmachbm<.f> 0,limm,c 0011011000011001F111CCCCCC111110. */ +{ "dmachbm", 0x3619703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmachbm<.f> 0,b,limm 00110bbb00011001FBBB111110111110. */ +{ "dmachbm", 0x30190FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmachbm<.f><.cc> b,b,limm 00110bbb11011001FBBB1111100QQQQQ. */ +{ "dmachbm", 0x30D90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmachbm<.f><.cc> 0,limm,c 0011011011011001F111CCCCCC0QQQQQ. */ +{ "dmachbm", 0x36D97000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmachbm<.f> a,limm,u6 0011011001011001F111uuuuuuAAAAAA. */ +{ "dmachbm", 0x36597000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmachbm<.f> 0,limm,u6 0011011001011001F111uuuuuu111110. */ +{ "dmachbm", 0x3659703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmachbm<.f><.cc> 0,limm,u6 0011011011011001F111uuuuuu1QQQQQ. */ +{ "dmachbm", 0x36D97020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmachbm<.f> 0,limm,s12 0011011010011001F111ssssssSSSSSS. */ +{ "dmachbm", 0x36997000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmachbm<.f> a,limm,limm 0011011000011001F111111110AAAAAA. */ +{ "dmachbm", 0x36197F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmachbm<.f> 0,limm,limm 0011011000011001F111111110111110. */ +{ "dmachbm", 0x36197FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmachbm<.f><.cc> 0,limm,limm 0011011011011001F1111111100QQQQQ. */ +{ "dmachbm", 0x36D97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmachf<.f> a,b,c 00101bbb00101100FBBBCCCCCCAAAAAA. */ +{ "dmachf", 0x282C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmachf<.f> 0,b,c 00101bbb00101100FBBBCCCCCC111110. */ +{ "dmachf", 0x282C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmachf<.f><.cc> b,b,c 00101bbb11101100FBBBCCCCCC0QQQQQ. */ +{ "dmachf", 0x28EC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmachf<.f> a,b,u6 00101bbb01101100FBBBuuuuuuAAAAAA. */ +{ "dmachf", 0x286C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmachf<.f> 0,b,u6 00101bbb01101100FBBBuuuuuu111110. */ +{ "dmachf", 0x286C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmachf<.f><.cc> b,b,u6 00101bbb11101100FBBBuuuuuu1QQQQQ. */ +{ "dmachf", 0x28EC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmachf<.f> b,b,s12 00101bbb10101100FBBBssssssSSSSSS. */ +{ "dmachf", 0x28AC0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmachf<.f> a,limm,c 0010111000101100F111CCCCCCAAAAAA. */ +{ "dmachf", 0x2E2C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmachf<.f> a,b,limm 00101bbb00101100FBBB111110AAAAAA. */ +{ "dmachf", 0x282C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmachf<.f> 0,limm,c 0010111001101100F111CCCCCC111110. */ +{ "dmachf", 0x2E6C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmachf<.f> 0,b,limm 00101bbb00101100FBBB111110111110. */ +{ "dmachf", 0x282C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmachf<.f><.cc> b,b,limm 00101bbb11101100FBBB1111100QQQQQ. */ +{ "dmachf", 0x28EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmachf<.f><.cc> 0,limm,c 0010111011101100F111CCCCCC0QQQQQ. */ +{ "dmachf", 0x2EEC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmachf<.f> a,limm,u6 0010111001101100F111uuuuuuAAAAAA. */ +{ "dmachf", 0x2E6C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmachf<.f> 0,limm,u6 0010111001101100F111uuuuuu111110. */ +{ "dmachf", 0x2E6C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmachf<.f><.cc> 0,limm,u6 0010111011101100F111uuuuuu1QQQQQ. */ +{ "dmachf", 0x2EEC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmachf<.f> 0,limm,s12 0010111010101100F111ssssssSSSSSS. */ +{ "dmachf", 0x2EAC7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmachf<.f> a,limm,limm 0010111000101100F111111110AAAAAA. */ +{ "dmachf", 0x2E2C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmachf<.f> 0,limm,limm 0010111000101100F111111110111110. */ +{ "dmachf", 0x2E2C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmachf<.f><.cc> 0,limm,limm 0010111011101100F1111111100QQQQQ. */ +{ "dmachf", 0x2EEC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmachfr<.f> a,b,c 00101bbb00101101FBBBCCCCCCAAAAAA. */ +{ "dmachfr", 0x282D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmachfr<.f> 0,b,c 00101bbb00101101FBBBCCCCCC111110. */ +{ "dmachfr", 0x282D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmachfr<.f><.cc> b,b,c 00101bbb11101101FBBBCCCCCC0QQQQQ. */ +{ "dmachfr", 0x28ED0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmachfr<.f> a,b,u6 00101bbb01101101FBBBuuuuuuAAAAAA. */ +{ "dmachfr", 0x286D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmachfr<.f> 0,b,u6 00101bbb01101101FBBBuuuuuu111110. */ +{ "dmachfr", 0x286D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmachfr<.f><.cc> b,b,u6 00101bbb11101101FBBBuuuuuu1QQQQQ. */ +{ "dmachfr", 0x28ED0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmachfr<.f> b,b,s12 00101bbb10101101FBBBssssssSSSSSS. */ +{ "dmachfr", 0x28AD0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmachfr<.f> a,limm,c 0010111000101101F111CCCCCCAAAAAA. */ +{ "dmachfr", 0x2E2D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmachfr<.f> a,b,limm 00101bbb00101101FBBB111110AAAAAA. */ +{ "dmachfr", 0x282D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmachfr<.f> 0,limm,c 0010111001101101F111CCCCCC111110. */ +{ "dmachfr", 0x2E6D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmachfr<.f> 0,b,limm 00101bbb00101101FBBB111110111110. */ +{ "dmachfr", 0x282D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmachfr<.f><.cc> b,b,limm 00101bbb11101101FBBB1111100QQQQQ. */ +{ "dmachfr", 0x28ED0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmachfr<.f><.cc> 0,limm,c 0010111011101101F111CCCCCC0QQQQQ. */ +{ "dmachfr", 0x2EED7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmachfr<.f> a,limm,u6 0010111001101101F111uuuuuuAAAAAA. */ +{ "dmachfr", 0x2E6D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmachfr<.f> 0,limm,u6 0010111001101101F111uuuuuu111110. */ +{ "dmachfr", 0x2E6D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmachfr<.f><.cc> 0,limm,u6 0010111011101101F111uuuuuu1QQQQQ. */ +{ "dmachfr", 0x2EED7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmachfr<.f> 0,limm,s12 0010111010101101F111ssssssSSSSSS. */ +{ "dmachfr", 0x2EAD7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmachfr<.f> a,limm,limm 0010111000101101F111111110AAAAAA. */ +{ "dmachfr", 0x2E2D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmachfr<.f> 0,limm,limm 0010111000101101F111111110111110. */ +{ "dmachfr", 0x2E2D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmachfr<.f><.cc> 0,limm,limm 0010111011101101F1111111100QQQQQ. */ +{ "dmachfr", 0x2EED7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmachu<.f> a,b,c 00101bbb00010011FBBBCCCCCCAAAAAA. */ +{ "dmachu", 0x28130000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmachu<.f> 0,b,c 00101bbb00010011FBBBCCCCCC111110. */ +{ "dmachu", 0x2813003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmachu<.f><.cc> b,b,c 00101bbb11010011FBBBCCCCCC0QQQQQ. */ +{ "dmachu", 0x28D30000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmachu<.f> a,b,u6 00101bbb01010011FBBBuuuuuuAAAAAA. */ +{ "dmachu", 0x28530000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmachu<.f> 0,b,u6 00101bbb01010011FBBBuuuuuu111110. */ +{ "dmachu", 0x2853003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmachu<.f><.cc> b,b,u6 00101bbb11010011FBBBuuuuuu1QQQQQ. */ +{ "dmachu", 0x28D30020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmachu<.f> b,b,s12 00101bbb10010011FBBBssssssSSSSSS. */ +{ "dmachu", 0x28930000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmachu<.f> a,limm,c 0010111000010011F111CCCCCCAAAAAA. */ +{ "dmachu", 0x2E137000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmachu<.f> a,b,limm 00101bbb00010011FBBB111110AAAAAA. */ +{ "dmachu", 0x28130F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmachu<.f> 0,limm,c 0010111000010011F111CCCCCC111110. */ +{ "dmachu", 0x2E13703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmachu<.f> 0,b,limm 00101bbb00010011FBBB111110111110. */ +{ "dmachu", 0x28130FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmachu<.f><.cc> b,b,limm 00101bbb11010011FBBB1111100QQQQQ. */ +{ "dmachu", 0x28D30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmachu<.f><.cc> 0,limm,c 0010111011010011F111CCCCCC0QQQQQ. */ +{ "dmachu", 0x2ED37000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmachu<.f> a,limm,u6 0010111001010011F111uuuuuuAAAAAA. */ +{ "dmachu", 0x2E537000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmachu<.f> 0,limm,u6 0010111001010011F111uuuuuu111110. */ +{ "dmachu", 0x2E53703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmachu<.f><.cc> 0,limm,u6 0010111011010011F111uuuuuu1QQQQQ. */ +{ "dmachu", 0x2ED37020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmachu<.f> 0,limm,s12 0010111010010011F111ssssssSSSSSS. */ +{ "dmachu", 0x2E937000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmachu<.f> a,limm,limm 0010111000010011F111111110AAAAAA. */ +{ "dmachu", 0x2E137F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmachu<.f> 0,limm,limm 0010111000010011F111111110111110. */ +{ "dmachu", 0x2E137FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmachu<.f><.cc> 0,limm,limm 0010111011010011F1111111100QQQQQ. */ +{ "dmachu", 0x2ED37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmacpf<.f> a,b,c 00101bbb00111011FBBBCCCCCCAAAAAA. */ +{ "dmacpf", 0x283B0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmacpf<.f><.cc> b,b,c 00101bbb11111011FBBBCCCCCC0QQQQQ. */ +{ "dmacpf", 0x28FB0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmacpf<.f> 0,b,c 00101bbb00111011FBBBCCCCCC111110. */ +{ "dmacpf", 0x283B003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmacpf<.f> a,b,limm 00101bbb00111011FBBB111110AAAAAA. */ +{ "dmacpf", 0x283B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmacpf<.f><.cc> b,b,limm 00101bbb11111011FBBB1111100QQQQQ. */ +{ "dmacpf", 0x28FB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmacwh<.f> a,b,c 00101bbb00110110FBBBCCCCCCAAAAAA. */ +{ "dmacwh", 0x28360000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmacwh<.f> 0,b,c 00101bbb00110110FBBBCCCCCC111110. */ +{ "dmacwh", 0x2836003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmacwh<.f><.cc> b,b,c 00101bbb11110110FBBBCCCCCC0QQQQQ. */ +{ "dmacwh", 0x28F60000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmacwh<.f> a,b,u6 00101bbb01110110FBBBuuuuuuAAAAAA. */ +{ "dmacwh", 0x28760000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmacwh<.f> 0,b,u6 00101bbb01110110FBBBuuuuuu111110. */ +{ "dmacwh", 0x2876003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmacwh<.f><.cc> b,b,u6 00101bbb11110110FBBBuuuuuu1QQQQQ. */ +{ "dmacwh", 0x28F60020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmacwh<.f> b,b,s12 00101bbb10110110FBBBssssssSSSSSS. */ +{ "dmacwh", 0x28B60000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmacwh<.f> a,limm,c 0010111000110110F111CCCCCCAAAAAA. */ +{ "dmacwh", 0x2E367000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmacwh<.f> a,b,limm 00101bbb00110110FBBB111110AAAAAA. */ +{ "dmacwh", 0x28360F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmacwh<.f> 0,limm,c 0010111000110110F111CCCCCC111110. */ +{ "dmacwh", 0x2E36703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmacwh<.f> 0,b,limm 00101bbb00110110FBBB111110111110. */ +{ "dmacwh", 0x28360FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmacwh<.f><.cc> b,b,limm 00101bbb11110110FBBB1111100QQQQQ. */ +{ "dmacwh", 0x28F60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmacwh<.f><.cc> 0,limm,c 0010111011110110F111CCCCCC0QQQQQ. */ +{ "dmacwh", 0x2EF67000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmacwh<.f> a,limm,u6 0010111001110110F111uuuuuuAAAAAA. */ +{ "dmacwh", 0x2E767000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmacwh<.f> 0,limm,u6 0010111001110110F111uuuuuu111110. */ +{ "dmacwh", 0x2E76703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmacwh<.f><.cc> 0,limm,u6 0010111011110110F111uuuuuu1QQQQQ. */ +{ "dmacwh", 0x2EF67020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmacwh<.f> 0,limm,s12 0010111010110110F111ssssssSSSSSS. */ +{ "dmacwh", 0x2EB67000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmacwh<.f> a,limm,limm 0010111000110110F111111110AAAAAA. */ +{ "dmacwh", 0x2E367F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmacwh<.f> 0,limm,limm 0010111000110110F111111110111110. */ +{ "dmacwh", 0x2E367FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmacwh<.f><.cc> 0,limm,limm 0010111011110110F1111111100QQQQQ. */ +{ "dmacwh", 0x2EF67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmacwhf<.f><.cc> b,b,c 00110bbb11110111FBBBCCCCCC0QQQQQ */ +{ "dmacwhf", 0x30F70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmacwhf<.f> a,b,c 00110bbb00110111FBBBCCCCCCAAAAAA */ +{ "dmacwhf", 0x30370000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmacwhf<.f> 0,b,c 00110bbb00110111FBBBCCCCCC111110 */ +{ "dmacwhf", 0x3037003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmacwhf<.f><.cc> b,b,u6 00110bbb11110111FBBBuuuuuu1QQQQQ */ +{ "dmacwhf", 0x30F70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmacwhf<.f> a,b,u6 00110bbb01110111FBBBuuuuuuAAAAAA */ +{ "dmacwhf", 0x30770000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmacwhf<.f> 0,b,u6 00110bbb01110111FBBBuuuuuu111110 */ +{ "dmacwhf", 0x3077003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmacwhf<.f> b,b,s12 00110bbb10110111FBBBssssssSSSSSS */ +{ "dmacwhf", 0x30B70000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmacwhf<.f><.cc> 0,limm,c 0011011011110111F111CCCCCC0QQQQQ */ +{ "dmacwhf", 0x36F77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmacwhf<.f> 0,b,limm 00110bbb00110111FBBB111110111110 */ +{ "dmacwhf", 0x30370FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmacwhf<.f><.cc> b,b,limm 00110bbb11110111FBBB1111100QQQQQ */ +{ "dmacwhf", 0x30F70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmacwhf<.f> a,b,limm 00110bbb00110111FBBB111110AAAAAA */ +{ "dmacwhf", 0x30370F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmacwhf<.f> a,limm,c 0011011000110111F111CCCCCCAAAAAA */ +{ "dmacwhf", 0x36377000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmacwhf<.f> 0,limm,c 0011011000110111F111CCCCCC111110 */ +{ "dmacwhf", 0x3637703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmacwhf<.f><.cc> 0,limm,u6 0011011011110111F111uuuuuu1QQQQQ */ +{ "dmacwhf", 0x36F77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmacwhf<.f> a,limm,u6 0011011001110111F111uuuuuuAAAAAA */ +{ "dmacwhf", 0x36777000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmacwhf<.f> 0,limm,u6 0011011001110111F111uuuuuu111110 */ +{ "dmacwhf", 0x3677703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmacwhf<.f> 0,limm,s12 0011011010110111F111ssssssSSSSSS */ +{ "dmacwhf", 0x36B77000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmacwhf<.f><.cc> 0,limm,limm 0011011011110111F1111111100QQQQQ */ +{ "dmacwhf", 0x36F77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmacwhf<.f> 0,limm,limm 0011011000110111F111111110111110 */ +{ "dmacwhf", 0x36377FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmacwhf<.f> a,limm,limm 0011011000110111F111111110AAAAAA */ +{ "dmacwhf", 0x36377F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmacwhu<.f> a,b,c 00101bbb00110111FBBBCCCCCCAAAAAA. */ +{ "dmacwhu", 0x28370000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmacwhu<.f> 0,b,c 00101bbb00110111FBBBCCCCCC111110. */ +{ "dmacwhu", 0x2837003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmacwhu<.f><.cc> b,b,c 00101bbb11110111FBBBCCCCCC0QQQQQ. */ +{ "dmacwhu", 0x28F70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmacwhu<.f> a,b,u6 00101bbb01110111FBBBuuuuuuAAAAAA. */ +{ "dmacwhu", 0x28770000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmacwhu<.f> 0,b,u6 00101bbb01110111FBBBuuuuuu111110. */ +{ "dmacwhu", 0x2877003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmacwhu<.f><.cc> b,b,u6 00101bbb11110111FBBBuuuuuu1QQQQQ. */ +{ "dmacwhu", 0x28F70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmacwhu<.f> b,b,s12 00101bbb10110111FBBBssssssSSSSSS. */ +{ "dmacwhu", 0x28B70000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmacwhu<.f> a,limm,c 0010111000110111F111CCCCCCAAAAAA. */ +{ "dmacwhu", 0x2E377000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmacwhu<.f> a,b,limm 00101bbb00110111FBBB111110AAAAAA. */ +{ "dmacwhu", 0x28370F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmacwhu<.f> 0,limm,c 0010111000110111F111CCCCCC111110. */ +{ "dmacwhu", 0x2E37703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmacwhu<.f> 0,b,limm 00101bbb00110111FBBB111110111110. */ +{ "dmacwhu", 0x28370FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmacwhu<.f><.cc> b,b,limm 00101bbb11110111FBBB1111100QQQQQ. */ +{ "dmacwhu", 0x28F70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmacwhu<.f><.cc> 0,limm,c 0010111011110111F111CCCCCC0QQQQQ. */ +{ "dmacwhu", 0x2EF77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmacwhu<.f> a,limm,u6 0010111001110111F111uuuuuuAAAAAA. */ +{ "dmacwhu", 0x2E777000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmacwhu<.f> 0,limm,u6 0010111001110111F111uuuuuu111110. */ +{ "dmacwhu", 0x2E77703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmacwhu<.f><.cc> 0,limm,u6 0010111011110111F111uuuuuu1QQQQQ. */ +{ "dmacwhu", 0x2EF77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmacwhu<.f> 0,limm,s12 0010111010110111F111ssssssSSSSSS. */ +{ "dmacwhu", 0x2EB77000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmacwhu<.f> a,limm,limm 0010111000110111F111111110AAAAAA. */ +{ "dmacwhu", 0x2E377F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmacwhu<.f> 0,limm,limm 0010111000110111F111111110111110. */ +{ "dmacwhu", 0x2E377FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmacwhu<.f><.cc> 0,limm,limm 0010111011110111F1111111100QQQQQ. */ +{ "dmacwhu", 0x2EF77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmb u3 00100011011011110001RRRuuu111111. */ +{ "dmb", 0x236F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_UIMM3_23 }, { 0 }}, + +/* dmb 00100011011011110001RRR000111111. */ +{ "dmb", 0x236F103F, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }}, + +/* dmpyh<.f> a,b,c 00101bbb00010000FBBBCCCCCCAAAAAA. */ +{ "dmpyh", 0x28100000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmpyh<.f> 0,b,c 00101bbb00010000FBBBCCCCCC111110. */ +{ "dmpyh", 0x2810003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmpyh<.f><.cc> b,b,c 00101bbb11010000FBBBCCCCCC0QQQQQ. */ +{ "dmpyh", 0x28D00000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmpyh<.f> a,b,u6 00101bbb01010000FBBBuuuuuuAAAAAA. */ +{ "dmpyh", 0x28500000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyh<.f> 0,b,u6 00101bbb01010000FBBBuuuuuu111110. */ +{ "dmpyh", 0x2850003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyh<.f><.cc> b,b,u6 00101bbb11010000FBBBuuuuuu1QQQQQ. */ +{ "dmpyh", 0x28D00020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyh<.f> b,b,s12 00101bbb10010000FBBBssssssSSSSSS. */ +{ "dmpyh", 0x28900000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmpyh<.f> a,limm,c 0010111000010000F111CCCCCCAAAAAA. */ +{ "dmpyh", 0x2E107000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmpyh<.f> a,b,limm 00101bbb00010000FBBB111110AAAAAA. */ +{ "dmpyh", 0x28100F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmpyh<.f> 0,limm,c 0010111000010000F111CCCCCC111110. */ +{ "dmpyh", 0x2E10703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmpyh<.f> 0,b,limm 00101bbb00010000FBBB111110111110. */ +{ "dmpyh", 0x28100FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmpyh<.f><.cc> b,b,limm 00101bbb11010000FBBB1111100QQQQQ. */ +{ "dmpyh", 0x28D00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmpyh<.f><.cc> 0,limm,c 0010111011010000F111CCCCCC0QQQQQ. */ +{ "dmpyh", 0x2ED07000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmpyh<.f> a,limm,u6 0010111001010000F111uuuuuuAAAAAA. */ +{ "dmpyh", 0x2E507000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyh<.f> 0,limm,u6 0010111001010000F111uuuuuu111110. */ +{ "dmpyh", 0x2E50703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyh<.f><.cc> 0,limm,u6 0010111011010000F111uuuuuu1QQQQQ. */ +{ "dmpyh", 0x2ED07020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyh<.f> 0,limm,s12 0010111010010000F111ssssssSSSSSS. */ +{ "dmpyh", 0x2E907000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmpyh<.f> a,limm,limm 0010111000010000F111111110AAAAAA. */ +{ "dmpyh", 0x2E107F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmpyh<.f> 0,limm,limm 0010111000010000F111111110111110. */ +{ "dmpyh", 0x2E107FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmpyh<.f><.cc> 0,limm,limm 0010111011010000F1111111100QQQQQ. */ +{ "dmpyh", 0x2ED07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmpyhbl<.f> a,b,c 00110bbb00010110FBBBCCCCCCAAAAAA. */ +{ "dmpyhbl", 0x30160000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmpyhbl<.f> 0,b,c 00110bbb00010110FBBBCCCCCC111110. */ +{ "dmpyhbl", 0x3016003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmpyhbl<.f><.cc> b,b,c 00110bbb11010110FBBBCCCCCC0QQQQQ. */ +{ "dmpyhbl", 0x30D60000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmpyhbl<.f> a,b,u6 00110bbb01010110FBBBuuuuuuAAAAAA. */ +{ "dmpyhbl", 0x30560000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhbl<.f> 0,b,u6 00110bbb01010110FBBBuuuuuu111110. */ +{ "dmpyhbl", 0x3056003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhbl<.f><.cc> b,b,u6 00110bbb11010110FBBBuuuuuu1QQQQQ. */ +{ "dmpyhbl", 0x30D60020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhbl<.f> b,b,s12 00110bbb10010110FBBBssssssSSSSSS. */ +{ "dmpyhbl", 0x30960000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmpyhbl<.f> a,limm,c 0011011000010110F111CCCCCCAAAAAA. */ +{ "dmpyhbl", 0x36167000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmpyhbl<.f> a,b,limm 00110bbb00010110FBBB111110AAAAAA. */ +{ "dmpyhbl", 0x30160F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmpyhbl<.f> 0,limm,c 0011011000010110F111CCCCCC111110. */ +{ "dmpyhbl", 0x3616703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmpyhbl<.f> 0,b,limm 00110bbb00010110FBBB111110111110. */ +{ "dmpyhbl", 0x30160FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmpyhbl<.f><.cc> b,b,limm 00110bbb11010110FBBB1111100QQQQQ. */ +{ "dmpyhbl", 0x30D60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmpyhbl<.f><.cc> 0,limm,c 0011011011010110F111CCCCCC0QQQQQ. */ +{ "dmpyhbl", 0x36D67000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmpyhbl<.f> a,limm,u6 0011011001010110F111uuuuuuAAAAAA. */ +{ "dmpyhbl", 0x36567000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhbl<.f> 0,limm,u6 0011011001010110F111uuuuuu111110. */ +{ "dmpyhbl", 0x3656703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhbl<.f><.cc> 0,limm,u6 0011011011010110F111uuuuuu1QQQQQ. */ +{ "dmpyhbl", 0x36D67020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhbl<.f> 0,limm,s12 0011011010010110F111ssssssSSSSSS. */ +{ "dmpyhbl", 0x36967000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmpyhbl<.f> a,limm,limm 0011011000010110F111111110AAAAAA. */ +{ "dmpyhbl", 0x36167F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmpyhbl<.f> 0,limm,limm 0011011000010110F111111110111110. */ +{ "dmpyhbl", 0x36167FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmpyhbl<.f><.cc> 0,limm,limm 0011011011010110F1111111100QQQQQ. */ +{ "dmpyhbl", 0x36D67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmpyhbm<.f> a,b,c 00110bbb00010111FBBBCCCCCCAAAAAA. */ +{ "dmpyhbm", 0x30170000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmpyhbm<.f> 0,b,c 00110bbb00010111FBBBCCCCCC111110. */ +{ "dmpyhbm", 0x3017003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmpyhbm<.f><.cc> b,b,c 00110bbb11010111FBBBCCCCCC0QQQQQ. */ +{ "dmpyhbm", 0x30D70000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmpyhbm<.f> a,b,u6 00110bbb01010111FBBBuuuuuuAAAAAA. */ +{ "dmpyhbm", 0x30570000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhbm<.f> 0,b,u6 00110bbb01010111FBBBuuuuuu111110. */ +{ "dmpyhbm", 0x3057003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhbm<.f><.cc> b,b,u6 00110bbb11010111FBBBuuuuuu1QQQQQ. */ +{ "dmpyhbm", 0x30D70020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhbm<.f> b,b,s12 00110bbb10010111FBBBssssssSSSSSS. */ +{ "dmpyhbm", 0x30970000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmpyhbm<.f> a,limm,c 0011011000010111F111CCCCCCAAAAAA. */ +{ "dmpyhbm", 0x36177000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmpyhbm<.f> a,b,limm 00110bbb00010111FBBB111110AAAAAA. */ +{ "dmpyhbm", 0x30170F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmpyhbm<.f> 0,limm,c 0011011000010111F111CCCCCC111110. */ +{ "dmpyhbm", 0x3617703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmpyhbm<.f> 0,b,limm 00110bbb00010111FBBB111110111110. */ +{ "dmpyhbm", 0x30170FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmpyhbm<.f><.cc> b,b,limm 00110bbb11010111FBBB1111100QQQQQ. */ +{ "dmpyhbm", 0x30D70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmpyhbm<.f><.cc> 0,limm,c 0011011011010111F111CCCCCC0QQQQQ. */ +{ "dmpyhbm", 0x36D77000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmpyhbm<.f> a,limm,u6 0011011001010111F111uuuuuuAAAAAA. */ +{ "dmpyhbm", 0x36577000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhbm<.f> 0,limm,u6 0011011001010111F111uuuuuu111110. */ +{ "dmpyhbm", 0x3657703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhbm<.f><.cc> 0,limm,u6 0011011011010111F111uuuuuu1QQQQQ. */ +{ "dmpyhbm", 0x36D77020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhbm<.f> 0,limm,s12 0011011010010111F111ssssssSSSSSS. */ +{ "dmpyhbm", 0x36977000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmpyhbm<.f> a,limm,limm 0011011000010111F111111110AAAAAA. */ +{ "dmpyhbm", 0x36177F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmpyhbm<.f> 0,limm,limm 0011011000010111F111111110111110. */ +{ "dmpyhbm", 0x36177FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmpyhbm<.f><.cc> 0,limm,limm 0011011011010111F1111111100QQQQQ. */ +{ "dmpyhbm", 0x36D77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmpyhf<.f> a,b,c 00101bbb00101010FBBBCCCCCCAAAAAA. */ +{ "dmpyhf", 0x282A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmpyhf<.f> 0,b,c 00101bbb00101010FBBBCCCCCC111110. */ +{ "dmpyhf", 0x282A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmpyhf<.f><.cc> b,b,c 00101bbb11101010FBBBCCCCCC0QQQQQ. */ +{ "dmpyhf", 0x28EA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmpyhf<.f> a,b,u6 00101bbb01101010FBBBuuuuuuAAAAAA. */ +{ "dmpyhf", 0x286A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhf<.f> 0,b,u6 00101bbb01101010FBBBuuuuuu111110. */ +{ "dmpyhf", 0x286A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhf<.f><.cc> b,b,u6 00101bbb11101010FBBBuuuuuu1QQQQQ. */ +{ "dmpyhf", 0x28EA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhf<.f> b,b,s12 00101bbb10101010FBBBssssssSSSSSS. */ +{ "dmpyhf", 0x28AA0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmpyhf<.f> a,limm,c 0010111000101010F111CCCCCCAAAAAA. */ +{ "dmpyhf", 0x2E2A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmpyhf<.f> a,b,limm 00101bbb00101010FBBB111110AAAAAA. */ +{ "dmpyhf", 0x282A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmpyhf<.f> 0,limm,c 0010111001101010F111CCCCCC111110. */ +{ "dmpyhf", 0x2E6A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmpyhf<.f> 0,b,limm 00101bbb00101010FBBB111110111110. */ +{ "dmpyhf", 0x282A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmpyhf<.f><.cc> b,b,limm 00101bbb11101010FBBB1111100QQQQQ. */ +{ "dmpyhf", 0x28EA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmpyhf<.f><.cc> 0,limm,c 0010111011101010F111CCCCCC0QQQQQ. */ +{ "dmpyhf", 0x2EEA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmpyhf<.f> a,limm,u6 0010111001101010F111uuuuuuAAAAAA. */ +{ "dmpyhf", 0x2E6A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhf<.f> 0,limm,u6 0010111001101010F111uuuuuu111110. */ +{ "dmpyhf", 0x2E6A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhf<.f><.cc> 0,limm,u6 0010111011101010F111uuuuuu1QQQQQ. */ +{ "dmpyhf", 0x2EEA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhf<.f> 0,limm,s12 0010111010101010F111ssssssSSSSSS. */ +{ "dmpyhf", 0x2EAA7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmpyhf<.f> a,limm,limm 0010111000101010F111111110AAAAAA. */ +{ "dmpyhf", 0x2E2A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmpyhf<.f> 0,limm,limm 0010111000101010F111111110111110. */ +{ "dmpyhf", 0x2E2A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmpyhf<.f><.cc> 0,limm,limm 0010111011101010F1111111100QQQQQ. */ +{ "dmpyhf", 0x2EEA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmpyhfr<.f> a,b,c 00101bbb00101011FBBBCCCCCCAAAAAA. */ +{ "dmpyhfr", 0x282B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmpyhfr<.f> 0,b,c 00101bbb00101011FBBBCCCCCC111110. */ +{ "dmpyhfr", 0x282B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmpyhfr<.f><.cc> b,b,c 00101bbb11101011FBBBCCCCCC0QQQQQ. */ +{ "dmpyhfr", 0x28EB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmpyhfr<.f> a,b,u6 00101bbb01101011FBBBuuuuuuAAAAAA. */ +{ "dmpyhfr", 0x286B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhfr<.f> 0,b,u6 00101bbb01101011FBBBuuuuuu111110. */ +{ "dmpyhfr", 0x286B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhfr<.f><.cc> b,b,u6 00101bbb11101011FBBBuuuuuu1QQQQQ. */ +{ "dmpyhfr", 0x28EB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhfr<.f> b,b,s12 00101bbb10101011FBBBssssssSSSSSS. */ +{ "dmpyhfr", 0x28AB0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmpyhfr<.f> a,limm,c 0010111000101011F111CCCCCCAAAAAA. */ +{ "dmpyhfr", 0x2E2B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmpyhfr<.f> a,b,limm 00101bbb00101011FBBB111110AAAAAA. */ +{ "dmpyhfr", 0x282B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmpyhfr<.f> 0,limm,c 0010111001101011F111CCCCCC111110. */ +{ "dmpyhfr", 0x2E6B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmpyhfr<.f> 0,b,limm 00101bbb00101011FBBB111110111110. */ +{ "dmpyhfr", 0x282B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmpyhfr<.f><.cc> b,b,limm 00101bbb11101011FBBB1111100QQQQQ. */ +{ "dmpyhfr", 0x28EB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmpyhfr<.f><.cc> 0,limm,c 0010111011101011F111CCCCCC0QQQQQ. */ +{ "dmpyhfr", 0x2EEB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmpyhfr<.f> a,limm,u6 0010111001101011F111uuuuuuAAAAAA. */ +{ "dmpyhfr", 0x2E6B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhfr<.f> 0,limm,u6 0010111001101011F111uuuuuu111110. */ +{ "dmpyhfr", 0x2E6B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhfr<.f><.cc> 0,limm,u6 0010111011101011F111uuuuuu1QQQQQ. */ +{ "dmpyhfr", 0x2EEB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhfr<.f> 0,limm,s12 0010111010101011F111ssssssSSSSSS. */ +{ "dmpyhfr", 0x2EAB7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmpyhfr<.f> a,limm,limm 0010111000101011F111111110AAAAAA. */ +{ "dmpyhfr", 0x2E2B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmpyhfr<.f> 0,limm,limm 0010111000101011F111111110111110. */ +{ "dmpyhfr", 0x2E2B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmpyhfr<.f><.cc> 0,limm,limm 0010111011101011F1111111100QQQQQ. */ +{ "dmpyhfr", 0x2EEB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmpyhu<.f> a,b,c 00101bbb00010001FBBBCCCCCCAAAAAA. */ +{ "dmpyhu", 0x28110000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmpyhu<.f> 0,b,c 00101bbb00010001FBBBCCCCCC111110. */ +{ "dmpyhu", 0x2811003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmpyhu<.f><.cc> b,b,c 00101bbb11010001FBBBCCCCCC0QQQQQ. */ +{ "dmpyhu", 0x28D10000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmpyhu<.f> a,b,u6 00101bbb01010001FBBBuuuuuuAAAAAA. */ +{ "dmpyhu", 0x28510000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhu<.f> 0,b,u6 00101bbb01010001FBBBuuuuuu111110. */ +{ "dmpyhu", 0x2851003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhu<.f><.cc> b,b,u6 00101bbb11010001FBBBuuuuuu1QQQQQ. */ +{ "dmpyhu", 0x28D10020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhu<.f> b,b,s12 00101bbb10010001FBBBssssssSSSSSS. */ +{ "dmpyhu", 0x28910000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmpyhu<.f> a,limm,c 0010111000010001F111CCCCCCAAAAAA. */ +{ "dmpyhu", 0x2E117000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmpyhu<.f> a,b,limm 00101bbb00010001FBBB111110AAAAAA. */ +{ "dmpyhu", 0x28110F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmpyhu<.f> 0,limm,c 0010111000010001F111CCCCCC111110. */ +{ "dmpyhu", 0x2E11703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmpyhu<.f> 0,b,limm 00101bbb00010001FBBB111110111110. */ +{ "dmpyhu", 0x28110FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmpyhu<.f><.cc> b,b,limm 00101bbb11010001FBBB1111100QQQQQ. */ +{ "dmpyhu", 0x28D10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmpyhu<.f><.cc> 0,limm,c 0010111011010001F111CCCCCC0QQQQQ. */ +{ "dmpyhu", 0x2ED17000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmpyhu<.f> a,limm,u6 0010111001010001F111uuuuuuAAAAAA. */ +{ "dmpyhu", 0x2E517000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhu<.f> 0,limm,u6 0010111001010001F111uuuuuu111110. */ +{ "dmpyhu", 0x2E51703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhu<.f><.cc> 0,limm,u6 0010111011010001F111uuuuuu1QQQQQ. */ +{ "dmpyhu", 0x2ED17020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhu<.f> 0,limm,s12 0010111010010001F111ssssssSSSSSS. */ +{ "dmpyhu", 0x2E917000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmpyhu<.f> a,limm,limm 0010111000010001F111111110AAAAAA. */ +{ "dmpyhu", 0x2E117F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmpyhu<.f> 0,limm,limm 0010111000010001F111111110111110. */ +{ "dmpyhu", 0x2E117FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmpyhu<.f><.cc> 0,limm,limm 0010111011010001F1111111100QQQQQ. */ +{ "dmpyhu", 0x2ED17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmpyhwf<.f> a,b,c 00101bbb00101000FBBBCCCCCCAAAAAA. */ +{ "dmpyhwf", 0x28280000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmpyhwf<.f> 0,b,c 00101bbb00101000FBBBCCCCCC111110. */ +{ "dmpyhwf", 0x2828003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmpyhwf<.f><.cc> b,b,c 00101bbb11101000FBBBCCCCCC0QQQQQ. */ +{ "dmpyhwf", 0x28E80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmpyhwf<.f> a,b,u6 00101bbb01101000FBBBuuuuuuAAAAAA. */ +{ "dmpyhwf", 0x28680000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhwf<.f> 0,b,u6 00101bbb01101000FBBBuuuuuu111110. */ +{ "dmpyhwf", 0x2868003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhwf<.f><.cc> b,b,u6 00101bbb11101000FBBBuuuuuu1QQQQQ. */ +{ "dmpyhwf", 0x28E80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhwf<.f> b,b,s12 00101bbb10101000FBBBssssssSSSSSS. */ +{ "dmpyhwf", 0x28A80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmpyhwf<.f> a,limm,c 0010111000101000F111CCCCCCAAAAAA. */ +{ "dmpyhwf", 0x2E287000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmpyhwf<.f> a,b,limm 00101bbb00101000FBBB111110AAAAAA. */ +{ "dmpyhwf", 0x28280F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmpyhwf<.f> 0,limm,c 0010111001101000F111CCCCCC111110. */ +{ "dmpyhwf", 0x2E68703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmpyhwf<.f> 0,b,limm 00101bbb00101000FBBB111110111110. */ +{ "dmpyhwf", 0x28280FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmpyhwf<.f><.cc> b,b,limm 00101bbb11101000FBBB1111100QQQQQ. */ +{ "dmpyhwf", 0x28E80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmpyhwf<.f><.cc> 0,limm,c 0010111011101000F111CCCCCC0QQQQQ. */ +{ "dmpyhwf", 0x2EE87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmpyhwf<.f> a,limm,u6 0010111001101000F111uuuuuuAAAAAA. */ +{ "dmpyhwf", 0x2E687000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhwf<.f> 0,limm,u6 0010111001101000F111uuuuuu111110. */ +{ "dmpyhwf", 0x2E68703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpyhwf<.f><.cc> 0,limm,u6 0010111011101000F111uuuuuu1QQQQQ. */ +{ "dmpyhwf", 0x2EE87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhwf<.f> 0,limm,s12 0010111010101000F111ssssssSSSSSS. */ +{ "dmpyhwf", 0x2EA87000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmpyhwf<.f> a,limm,limm 0010111000101000F111111110AAAAAA. */ +{ "dmpyhwf", 0x2E287F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmpyhwf<.f> 0,limm,limm 0010111000101000F111111110111110. */ +{ "dmpyhwf", 0x2E287FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmpyhwf<.f><.cc> 0,limm,limm 0010111011101000F1111111100QQQQQ. */ +{ "dmpyhwf", 0x2EE87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmpywh<.f> a,b,c 00101bbb00110010FBBBCCCCCCAAAAAA. */ +{ "dmpywh", 0x28320000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmpywh<.f> 0,b,c 00101bbb00110010FBBBCCCCCC111110. */ +{ "dmpywh", 0x2832003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmpywh<.f><.cc> b,b,c 00101bbb11110010FBBBCCCCCC0QQQQQ. */ +{ "dmpywh", 0x28F20000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmpywh<.f> a,b,u6 00101bbb01110010FBBBuuuuuuAAAAAA. */ +{ "dmpywh", 0x28720000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpywh<.f> 0,b,u6 00101bbb01110010FBBBuuuuuu111110. */ +{ "dmpywh", 0x2872003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpywh<.f><.cc> b,b,u6 00101bbb11110010FBBBuuuuuu1QQQQQ. */ +{ "dmpywh", 0x28F20020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmpywh<.f> b,b,s12 00101bbb10110010FBBBssssssSSSSSS. */ +{ "dmpywh", 0x28B20000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmpywh<.f> a,limm,c 0010111000110010F111CCCCCCAAAAAA. */ +{ "dmpywh", 0x2E327000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmpywh<.f> a,b,limm 00101bbb00110010FBBB111110AAAAAA. */ +{ "dmpywh", 0x28320F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmpywh<.f> 0,limm,c 0010111000110010F111CCCCCC111110. */ +{ "dmpywh", 0x2E32703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmpywh<.f> 0,b,limm 00101bbb00110010FBBB111110111110. */ +{ "dmpywh", 0x28320FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmpywh<.f><.cc> b,b,limm 00101bbb11110010FBBB1111100QQQQQ. */ +{ "dmpywh", 0x28F20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmpywh<.f><.cc> 0,limm,c 0010111011110010F111CCCCCC0QQQQQ. */ +{ "dmpywh", 0x2EF27000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmpywh<.f> a,limm,u6 0010111001110010F111uuuuuuAAAAAA. */ +{ "dmpywh", 0x2E727000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpywh<.f> 0,limm,u6 0010111001110010F111uuuuuu111110. */ +{ "dmpywh", 0x2E72703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpywh<.f><.cc> 0,limm,u6 0010111011110010F111uuuuuu1QQQQQ. */ +{ "dmpywh", 0x2EF27020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmpywh<.f> 0,limm,s12 0010111010110010F111ssssssSSSSSS. */ +{ "dmpywh", 0x2EB27000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmpywh<.f> a,limm,limm 0010111000110010F111111110AAAAAA. */ +{ "dmpywh", 0x2E327F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmpywh<.f> 0,limm,limm 0010111000110010F111111110111110. */ +{ "dmpywh", 0x2E327FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmpywh<.f><.cc> 0,limm,limm 0010111011110010F1111111100QQQQQ. */ +{ "dmpywh", 0x2EF27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmpywhf<.f> 0,b,c 00110bbb00110011FBBBCCCCCC111110 */ +{ "dmpywhf", 0x3033003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmpywhf<.f><.cc> b,b,c 00110bbb11110011FBBBCCCCCC0QQQQQ */ +{ "dmpywhf", 0x30F30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmpywhf<.f> a,b,c 00110bbb00110011FBBBCCCCCCAAAAAA */ +{ "dmpywhf", 0x30330000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmpywhf<.f> a,b,u6 00110bbb01110011FBBBuuuuuuAAAAAA */ +{ "dmpywhf", 0x30730000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpywhf<.f><.cc> b,b,u6 00110bbb11110011FBBBuuuuuu1QQQQQ */ +{ "dmpywhf", 0x30F30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmpywhf<.f> 0,b,u6 00110bbb01110011FBBBuuuuuu111110 */ +{ "dmpywhf", 0x3073003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpywhf<.f> b,b,s12 00110bbb10110011FBBBssssssSSSSSS */ +{ "dmpywhf", 0x30B30000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmpywhf<.f><.cc> 0,limm,c 0011011011110011F111CCCCCC0QQQQQ */ +{ "dmpywhf", 0x36F37000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmpywhf<.f> a,limm,c 0011011000110011F111CCCCCCAAAAAA */ +{ "dmpywhf", 0x36337000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmpywhf<.f> a,b,limm 00110bbb00110011FBBB111110AAAAAA */ +{ "dmpywhf", 0x30330F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmpywhf<.f> 0,limm,c 0011011000110011F111CCCCCC111110 */ +{ "dmpywhf", 0x3633703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmpywhf<.f> 0,b,limm 00110bbb00110011FBBB111110111110 */ +{ "dmpywhf", 0x30330FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmpywhf<.f><.cc> b,b,limm 00110bbb11110011FBBB1111100QQQQQ */ +{ "dmpywhf", 0x30F30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmpywhf<.f><.cc> 0,limm,u6 0011011011110011F111uuuuuu1QQQQQ */ +{ "dmpywhf", 0x36F37020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmpywhf<.f> a,limm,u6 0011011001110011F111uuuuuuAAAAAA */ +{ "dmpywhf", 0x36737000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpywhf<.f> 0,limm,u6 0011011001110011F111uuuuuu111110 */ +{ "dmpywhf", 0x3673703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpywhf<.f> 0,limm,s12 0011011010110011F111ssssssSSSSSS */ +{ "dmpywhf", 0x36B37000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmpywhf<.f> a,limm,limm 0011011000110011F111111110AAAAAA */ +{ "dmpywhf", 0x36337F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmpywhf<.f> 0,limm,limm 0011011000110011F111111110111110 */ +{ "dmpywhf", 0x36337FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmpywhf<.f><.cc> 0,limm,limm 0011011011110011F1111111100QQQQQ */ +{ "dmpywhf", 0x36F37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmpywhu<.f> a,b,c 00101bbb00110011FBBBCCCCCCAAAAAA. */ +{ "dmpywhu", 0x28330000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmpywhu<.f> 0,b,c 00101bbb00110011FBBBCCCCCC111110. */ +{ "dmpywhu", 0x2833003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmpywhu<.f><.cc> b,b,c 00101bbb11110011FBBBCCCCCC0QQQQQ. */ +{ "dmpywhu", 0x28F30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmpywhu<.f> a,b,u6 00101bbb01110011FBBBuuuuuuAAAAAA. */ +{ "dmpywhu", 0x28730000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpywhu<.f> 0,b,u6 00101bbb01110011FBBBuuuuuu111110. */ +{ "dmpywhu", 0x2873003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpywhu<.f><.cc> b,b,u6 00101bbb11110011FBBBuuuuuu1QQQQQ. */ +{ "dmpywhu", 0x28F30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmpywhu<.f> b,b,s12 00101bbb10110011FBBBssssssSSSSSS. */ +{ "dmpywhu", 0x28B30000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmpywhu<.f> a,limm,c 0010111000110011F111CCCCCCAAAAAA. */ +{ "dmpywhu", 0x2E337000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmpywhu<.f> a,b,limm 00101bbb00110011FBBB111110AAAAAA. */ +{ "dmpywhu", 0x28330F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmpywhu<.f> 0,limm,c 0010111000110011F111CCCCCC111110. */ +{ "dmpywhu", 0x2E33703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmpywhu<.f> 0,b,limm 00101bbb00110011FBBB111110111110. */ +{ "dmpywhu", 0x28330FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmpywhu<.f><.cc> b,b,limm 00101bbb11110011FBBB1111100QQQQQ. */ +{ "dmpywhu", 0x28F30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmpywhu<.f><.cc> 0,limm,c 0010111011110011F111CCCCCC0QQQQQ. */ +{ "dmpywhu", 0x2EF37000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmpywhu<.f> a,limm,u6 0010111001110011F111uuuuuuAAAAAA. */ +{ "dmpywhu", 0x2E737000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpywhu<.f> 0,limm,u6 0010111001110011F111uuuuuu111110. */ +{ "dmpywhu", 0x2E73703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmpywhu<.f><.cc> 0,limm,u6 0010111011110011F111uuuuuu1QQQQQ. */ +{ "dmpywhu", 0x2EF37020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmpywhu<.f> 0,limm,s12 0010111010110011F111ssssssSSSSSS. */ +{ "dmpywhu", 0x2EB37000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmpywhu<.f> a,limm,limm 0010111000110011F111111110AAAAAA. */ +{ "dmpywhu", 0x2E337F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmpywhu<.f> 0,limm,limm 0010111000110011F111111110111110. */ +{ "dmpywhu", 0x2E337FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmpywhu<.f><.cc> 0,limm,limm 0010111011110011F1111111100QQQQQ. */ +{ "dmpywhu", 0x2EF37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmulh11<.f> a,b,c 00110bbb00001000FBBBCCCCCCAAAAAA. */ +{ "dmulh11", 0x30080000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmulh11<.f> 0,b,c 00110bbb00001000FBBBCCCCCC111110. */ +{ "dmulh11", 0x3008003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmulh11<.f><.cc> b,b,c 00110bbb11001000FBBBCCCCCC0QQQQQ. */ +{ "dmulh11", 0x30C80000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmulh11<.f> a,b,c 00110bbb00110000FBBBCCCCCCAAAAAA. */ +{ "dmulh11", 0x30300000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmulh11<.f> 0,b,c 00110bbb00110000FBBBCCCCCC111110. */ +{ "dmulh11", 0x3030003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmulh11<.f><.cc> b,b,c 00110bbb11110000FBBBCCCCCC0QQQQQ. */ +{ "dmulh11", 0x30F00000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmulh11<.f> a,b,u6 00110bbb01001000FBBBuuuuuuAAAAAA. */ +{ "dmulh11", 0x30480000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh11<.f> 0,b,u6 00110bbb01001000FBBBuuuuuu111110. */ +{ "dmulh11", 0x3048003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh11<.f><.cc> b,b,u6 00110bbb11001000FBBBuuuuuu1QQQQQ. */ +{ "dmulh11", 0x30C80020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh11<.f> a,b,u6 00110bbb01110000FBBBuuuuuuAAAAAA. */ +{ "dmulh11", 0x30700000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh11<.f> 0,b,u6 00110bbb01110000FBBBuuuuuu111110. */ +{ "dmulh11", 0x3070003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh11<.f><.cc> b,b,u6 00110bbb11110000FBBBuuuuuu1QQQQQ. */ +{ "dmulh11", 0x30F00020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh11<.f> b,b,s12 00110bbb10001000FBBBssssssSSSSSS. */ +{ "dmulh11", 0x30880000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmulh11<.f> b,b,s12 00110bbb10110000FBBBssssssSSSSSS. */ +{ "dmulh11", 0x30B00000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmulh11<.f> a,limm,c 0011011000001000F111CCCCCCAAAAAA. */ +{ "dmulh11", 0x36087000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmulh11<.f> a,b,limm 00110bbb00001000FBBB111110AAAAAA. */ +{ "dmulh11", 0x30080F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmulh11<.f> 0,limm,c 0011011000001000F111CCCCCC111110. */ +{ "dmulh11", 0x3608703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmulh11<.f> 0,b,limm 00110bbb00001000FBBB111110111110. */ +{ "dmulh11", 0x30080FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmulh11<.f><.cc> 0,limm,c 0011011011001000F111CCCCCC0QQQQQ. */ +{ "dmulh11", 0x36C87000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmulh11<.f><.cc> b,b,limm 00110bbb11001000FBBB1111100QQQQQ. */ +{ "dmulh11", 0x30C80F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmulh11<.f> a,limm,c 0011011000110000F111CCCCCCAAAAAA. */ +{ "dmulh11", 0x36307000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmulh11<.f> a,b,limm 00110bbb00110000FBBB111110AAAAAA. */ +{ "dmulh11", 0x30300F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmulh11<.f> 0,limm,c 0011011000110000F111CCCCCC111110. */ +{ "dmulh11", 0x3630703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmulh11<.f> 0,b,limm 00110bbb00110000FBBB111110111110. */ +{ "dmulh11", 0x30300FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmulh11<.f><.cc> 0,limm,c 0011011011110000F111CCCCCC0QQQQQ. */ +{ "dmulh11", 0x36F07000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmulh11<.f><.cc> b,b,limm 00110bbb11110000FBBB1111100QQQQQ. */ +{ "dmulh11", 0x30F00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmulh11<.f> a,limm,u6 0011011001001000F111uuuuuuAAAAAA. */ +{ "dmulh11", 0x36487000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh11<.f> 0,limm,u6 0011011001001000F111uuuuuu111110. */ +{ "dmulh11", 0x3648703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh11<.f><.cc> 0,limm,u6 0011011011001000F111uuuuuu1QQQQQ. */ +{ "dmulh11", 0x36C87020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh11<.f> a,limm,u6 0011011001110000F111uuuuuuAAAAAA. */ +{ "dmulh11", 0x36707000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh11<.f> 0,limm,u6 0011011001110000F111uuuuuu111110. */ +{ "dmulh11", 0x3670703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh11<.f><.cc> 0,limm,u6 0011011011110000F111uuuuuu1QQQQQ. */ +{ "dmulh11", 0x36F07020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh11<.f> 0,limm,s12 0011011010001000F111ssssssSSSSSS. */ +{ "dmulh11", 0x36887000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmulh11<.f> 0,limm,s12 0011011010110000F111ssssssSSSSSS. */ +{ "dmulh11", 0x36B07000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmulh11<.f> a,limm,limm 0011011000001000F111111110AAAAAA. */ +{ "dmulh11", 0x36087F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmulh11<.f> 0,limm,limm 0011011000001000F111111110111110. */ +{ "dmulh11", 0x36087FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmulh11<.f><.cc> 0,limm,limm 0011011011001000F1111111100QQQQQ. */ +{ "dmulh11", 0x36C87F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmulh11<.f> a,limm,limm 0011011000110000F111111110AAAAAA. */ +{ "dmulh11", 0x36307F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmulh11<.f> 0,limm,limm 0011011000110000F111111110111110. */ +{ "dmulh11", 0x36307FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmulh11<.f><.cc> 0,limm,limm 0011011011110000F1111111100QQQQQ. */ +{ "dmulh11", 0x36F07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmulh12<.f> a,b,c 00110bbb00001001FBBBCCCCCCAAAAAA. */ +{ "dmulh12", 0x30090000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmulh12<.f> 0,b,c 00110bbb00001001FBBBCCCCCC111110. */ +{ "dmulh12", 0x3009003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmulh12<.f><.cc> b,b,c 00110bbb11001001FBBBCCCCCC0QQQQQ. */ +{ "dmulh12", 0x30C90000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmulh12<.f> a,b,c 00110bbb00110001FBBBCCCCCCAAAAAA. */ +{ "dmulh12", 0x30310000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmulh12<.f> 0,b,c 00110bbb00110001FBBBCCCCCC111110. */ +{ "dmulh12", 0x3031003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmulh12<.f><.cc> b,b,c 00110bbb11110001FBBBCCCCCC0QQQQQ. */ +{ "dmulh12", 0x30F10000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmulh12<.f> a,b,u6 00110bbb01001001FBBBuuuuuuAAAAAA. */ +{ "dmulh12", 0x30490000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh12<.f> 0,b,u6 00110bbb01001001FBBBuuuuuu111110. */ +{ "dmulh12", 0x3049003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh12<.f><.cc> b,b,u6 00110bbb11001001FBBBuuuuuu1QQQQQ. */ +{ "dmulh12", 0x30C90020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh12<.f> a,b,u6 00110bbb01110001FBBBuuuuuuAAAAAA. */ +{ "dmulh12", 0x30710000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh12<.f> 0,b,u6 00110bbb01110001FBBBuuuuuu111110. */ +{ "dmulh12", 0x3071003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh12<.f><.cc> b,b,u6 00110bbb11110001FBBBuuuuuu1QQQQQ. */ +{ "dmulh12", 0x30F10020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh12<.f> b,b,s12 00110bbb10001001FBBBssssssSSSSSS. */ +{ "dmulh12", 0x30890000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmulh12<.f> b,b,s12 00110bbb10110001FBBBssssssSSSSSS. */ +{ "dmulh12", 0x30B10000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmulh12<.f> a,limm,c 0011011000001001F111CCCCCCAAAAAA. */ +{ "dmulh12", 0x36097000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmulh12<.f> a,b,limm 00110bbb00001001FBBB111110AAAAAA. */ +{ "dmulh12", 0x30090F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmulh12<.f> 0,limm,c 0011011000001001F111CCCCCC111110. */ +{ "dmulh12", 0x3609703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmulh12<.f> 0,b,limm 00110bbb00001001FBBB111110111110. */ +{ "dmulh12", 0x30090FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmulh12<.f><.cc> 0,limm,c 0011011011001001F111CCCCCC0QQQQQ. */ +{ "dmulh12", 0x36C97000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmulh12<.f><.cc> b,b,limm 00110bbb11001001FBBB1111100QQQQQ. */ +{ "dmulh12", 0x30C90F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmulh12<.f> a,limm,c 0011011000110001F111CCCCCCAAAAAA. */ +{ "dmulh12", 0x36317000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmulh12<.f> a,b,limm 00110bbb00110001FBBB111110AAAAAA. */ +{ "dmulh12", 0x30310F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmulh12<.f> 0,limm,c 0011011000110001F111CCCCCC111110. */ +{ "dmulh12", 0x3631703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmulh12<.f> 0,b,limm 00110bbb00110001FBBB111110111110. */ +{ "dmulh12", 0x30310FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmulh12<.f><.cc> 0,limm,c 0011011011110001F111CCCCCC0QQQQQ. */ +{ "dmulh12", 0x36F17000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmulh12<.f><.cc> b,b,limm 00110bbb11110001FBBB1111100QQQQQ. */ +{ "dmulh12", 0x30F10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmulh12<.f> a,limm,u6 0011011001001001F111uuuuuuAAAAAA. */ +{ "dmulh12", 0x36497000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh12<.f> 0,limm,u6 0011011001001001F111uuuuuu111110. */ +{ "dmulh12", 0x3649703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh12<.f><.cc> 0,limm,u6 0011011011001001F111uuuuuu1QQQQQ. */ +{ "dmulh12", 0x36C97020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh12<.f> a,limm,u6 0011011001110001F111uuuuuuAAAAAA. */ +{ "dmulh12", 0x36717000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh12<.f> 0,limm,u6 0011011001110001F111uuuuuu111110. */ +{ "dmulh12", 0x3671703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh12<.f><.cc> 0,limm,u6 0011011011110001F111uuuuuu1QQQQQ. */ +{ "dmulh12", 0x36F17020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh12<.f> 0,limm,s12 0011011010001001F111ssssssSSSSSS. */ +{ "dmulh12", 0x36897000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmulh12<.f> 0,limm,s12 0011011010110001F111ssssssSSSSSS. */ +{ "dmulh12", 0x36B17000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmulh12<.f> a,limm,limm 0011011000001001F111111110AAAAAA. */ +{ "dmulh12", 0x36097F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmulh12<.f> 0,limm,limm 0011011000001001F111111110111110. */ +{ "dmulh12", 0x36097FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmulh12<.f><.cc> 0,limm,limm 0011011011001001F1111111100QQQQQ. */ +{ "dmulh12", 0x36C97F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmulh12<.f> a,limm,limm 0011011000110001F111111110AAAAAA. */ +{ "dmulh12", 0x36317F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmulh12<.f> 0,limm,limm 0011011000110001F111111110111110. */ +{ "dmulh12", 0x36317FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmulh12<.f><.cc> 0,limm,limm 0011011011110001F1111111100QQQQQ. */ +{ "dmulh12", 0x36F17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmulh21<.f> a,b,c 00110bbb00001010FBBBCCCCCCAAAAAA. */ +{ "dmulh21", 0x300A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmulh21<.f> 0,b,c 00110bbb00001010FBBBCCCCCC111110. */ +{ "dmulh21", 0x300A003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmulh21<.f><.cc> b,b,c 00110bbb11001010FBBBCCCCCC0QQQQQ. */ +{ "dmulh21", 0x30CA0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmulh21<.f> a,b,c 00110bbb00110010FBBBCCCCCCAAAAAA. */ +{ "dmulh21", 0x30320000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmulh21<.f> 0,b,c 00110bbb00110010FBBBCCCCCC111110. */ +{ "dmulh21", 0x3032003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmulh21<.f><.cc> b,b,c 00110bbb11110010FBBBCCCCCC0QQQQQ. */ +{ "dmulh21", 0x30F20000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmulh21<.f> a,b,u6 00110bbb01001010FBBBuuuuuuAAAAAA. */ +{ "dmulh21", 0x304A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh21<.f> 0,b,u6 00110bbb01001010FBBBuuuuuu111110. */ +{ "dmulh21", 0x304A003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh21<.f><.cc> b,b,u6 00110bbb11001010FBBBuuuuuu1QQQQQ. */ +{ "dmulh21", 0x30CA0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh21<.f> a,b,u6 00110bbb01110010FBBBuuuuuuAAAAAA. */ +{ "dmulh21", 0x30720000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh21<.f> 0,b,u6 00110bbb01110010FBBBuuuuuu111110. */ +{ "dmulh21", 0x3072003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh21<.f><.cc> b,b,u6 00110bbb11110010FBBBuuuuuu1QQQQQ. */ +{ "dmulh21", 0x30F20020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh21<.f> b,b,s12 00110bbb10001010FBBBssssssSSSSSS. */ +{ "dmulh21", 0x308A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmulh21<.f> b,b,s12 00110bbb10110010FBBBssssssSSSSSS. */ +{ "dmulh21", 0x30B20000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmulh21<.f> a,limm,c 0011011000001010F111CCCCCCAAAAAA. */ +{ "dmulh21", 0x360A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmulh21<.f> a,b,limm 00110bbb00001010FBBB111110AAAAAA. */ +{ "dmulh21", 0x300A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmulh21<.f> 0,limm,c 0011011000001010F111CCCCCC111110. */ +{ "dmulh21", 0x360A703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmulh21<.f> 0,b,limm 00110bbb00001010FBBB111110111110. */ +{ "dmulh21", 0x300A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmulh21<.f><.cc> 0,limm,c 0011011011001010F111CCCCCC0QQQQQ. */ +{ "dmulh21", 0x36CA7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmulh21<.f><.cc> b,b,limm 00110bbb11001010FBBB1111100QQQQQ. */ +{ "dmulh21", 0x30CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmulh21<.f> a,limm,c 0011011000110010F111CCCCCCAAAAAA. */ +{ "dmulh21", 0x36327000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmulh21<.f> a,b,limm 00110bbb00110010FBBB111110AAAAAA. */ +{ "dmulh21", 0x30320F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmulh21<.f> 0,limm,c 0011011000110010F111CCCCCC111110. */ +{ "dmulh21", 0x3632703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmulh21<.f> 0,b,limm 00110bbb00110010FBBB111110111110. */ +{ "dmulh21", 0x30320FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmulh21<.f><.cc> 0,limm,c 0011011011110010F111CCCCCC0QQQQQ. */ +{ "dmulh21", 0x36F27000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmulh21<.f><.cc> b,b,limm 00110bbb11110010FBBB1111100QQQQQ. */ +{ "dmulh21", 0x30F20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmulh21<.f> a,limm,u6 0011011001001010F111uuuuuuAAAAAA. */ +{ "dmulh21", 0x364A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh21<.f> 0,limm,u6 0011011001001010F111uuuuuu111110. */ +{ "dmulh21", 0x364A703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh21<.f><.cc> 0,limm,u6 0011011011001010F111uuuuuu1QQQQQ. */ +{ "dmulh21", 0x36CA7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh21<.f> a,limm,u6 0011011001110010F111uuuuuuAAAAAA. */ +{ "dmulh21", 0x36727000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh21<.f> 0,limm,u6 0011011001110010F111uuuuuu111110. */ +{ "dmulh21", 0x3672703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh21<.f><.cc> 0,limm,u6 0011011011110010F111uuuuuu1QQQQQ. */ +{ "dmulh21", 0x36F27020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh21<.f> 0,limm,s12 0011011010001010F111ssssssSSSSSS. */ +{ "dmulh21", 0x368A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmulh21<.f> 0,limm,s12 0011011010110010F111ssssssSSSSSS. */ +{ "dmulh21", 0x36B27000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmulh21<.f> a,limm,limm 0011011000001010F111111110AAAAAA. */ +{ "dmulh21", 0x360A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmulh21<.f> 0,limm,limm 0011011000001010F111111110111110. */ +{ "dmulh21", 0x360A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmulh21<.f><.cc> 0,limm,limm 0011011011001010F1111111100QQQQQ. */ +{ "dmulh21", 0x36CA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmulh21<.f> a,limm,limm 0011011000110010F111111110AAAAAA. */ +{ "dmulh21", 0x36327F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmulh21<.f> 0,limm,limm 0011011000110010F111111110111110. */ +{ "dmulh21", 0x36327FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmulh21<.f><.cc> 0,limm,limm 0011011011110010F1111111100QQQQQ. */ +{ "dmulh21", 0x36F27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmulh22<.f> a,b,c 00110bbb00001011FBBBCCCCCCAAAAAA. */ +{ "dmulh22", 0x300B0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmulh22<.f> 0,b,c 00110bbb00001011FBBBCCCCCC111110. */ +{ "dmulh22", 0x300B003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmulh22<.f><.cc> b,b,c 00110bbb11001011FBBBCCCCCC0QQQQQ. */ +{ "dmulh22", 0x30CB0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmulh22<.f> a,b,c 00110bbb00110011FBBBCCCCCCAAAAAA. */ +{ "dmulh22", 0x30330000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmulh22<.f> 0,b,c 00110bbb00110011FBBBCCCCCC111110. */ +{ "dmulh22", 0x3033003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmulh22<.f><.cc> b,b,c 00110bbb11110011FBBBCCCCCC0QQQQQ. */ +{ "dmulh22", 0x30F30000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmulh22<.f> a,b,u6 00110bbb01001011FBBBuuuuuuAAAAAA. */ +{ "dmulh22", 0x304B0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh22<.f> 0,b,u6 00110bbb01001011FBBBuuuuuu111110. */ +{ "dmulh22", 0x304B003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh22<.f><.cc> b,b,u6 00110bbb11001011FBBBuuuuuu1QQQQQ. */ +{ "dmulh22", 0x30CB0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh22<.f> a,b,u6 00110bbb01110011FBBBuuuuuuAAAAAA. */ +{ "dmulh22", 0x30730000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh22<.f> 0,b,u6 00110bbb01110011FBBBuuuuuu111110. */ +{ "dmulh22", 0x3073003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh22<.f><.cc> b,b,u6 00110bbb11110011FBBBuuuuuu1QQQQQ. */ +{ "dmulh22", 0x30F30020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh22<.f> b,b,s12 00110bbb10001011FBBBssssssSSSSSS. */ +{ "dmulh22", 0x308B0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmulh22<.f> b,b,s12 00110bbb10110011FBBBssssssSSSSSS. */ +{ "dmulh22", 0x30B30000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmulh22<.f> a,limm,c 0011011000001011F111CCCCCCAAAAAA. */ +{ "dmulh22", 0x360B7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmulh22<.f> a,b,limm 00110bbb00001011FBBB111110AAAAAA. */ +{ "dmulh22", 0x300B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmulh22<.f> 0,limm,c 0011011000001011F111CCCCCC111110. */ +{ "dmulh22", 0x360B703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmulh22<.f> 0,b,limm 00110bbb00001011FBBB111110111110. */ +{ "dmulh22", 0x300B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmulh22<.f><.cc> 0,limm,c 0011011011001011F111CCCCCC0QQQQQ. */ +{ "dmulh22", 0x36CB7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmulh22<.f><.cc> b,b,limm 00110bbb11001011FBBB1111100QQQQQ. */ +{ "dmulh22", 0x30CB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmulh22<.f> a,limm,c 0011011000110011F111CCCCCCAAAAAA. */ +{ "dmulh22", 0x36337000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmulh22<.f> a,b,limm 00110bbb00110011FBBB111110AAAAAA. */ +{ "dmulh22", 0x30330F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmulh22<.f> 0,limm,c 0011011000110011F111CCCCCC111110. */ +{ "dmulh22", 0x3633703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dmulh22<.f> 0,b,limm 00110bbb00110011FBBB111110111110. */ +{ "dmulh22", 0x30330FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmulh22<.f><.cc> 0,limm,c 0011011011110011F111CCCCCC0QQQQQ. */ +{ "dmulh22", 0x36F37000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dmulh22<.f><.cc> b,b,limm 00110bbb11110011FBBB1111100QQQQQ. */ +{ "dmulh22", 0x30F30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dmulh22<.f> a,limm,u6 0011011001001011F111uuuuuuAAAAAA. */ +{ "dmulh22", 0x364B7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh22<.f> 0,limm,u6 0011011001001011F111uuuuuu111110. */ +{ "dmulh22", 0x364B703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh22<.f><.cc> 0,limm,u6 0011011011001011F111uuuuuu1QQQQQ. */ +{ "dmulh22", 0x36CB7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh22<.f> a,limm,u6 0011011001110011F111uuuuuuAAAAAA. */ +{ "dmulh22", 0x36737000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh22<.f> 0,limm,u6 0011011001110011F111uuuuuu111110. */ +{ "dmulh22", 0x3673703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dmulh22<.f><.cc> 0,limm,u6 0011011011110011F111uuuuuu1QQQQQ. */ +{ "dmulh22", 0x36F37020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh22<.f> 0,limm,s12 0011011010001011F111ssssssSSSSSS. */ +{ "dmulh22", 0x368B7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmulh22<.f> 0,limm,s12 0011011010110011F111ssssssSSSSSS. */ +{ "dmulh22", 0x36B37000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dmulh22<.f> a,limm,limm 0011011000001011F111111110AAAAAA. */ +{ "dmulh22", 0x360B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmulh22<.f> 0,limm,limm 0011011000001011F111111110111110. */ +{ "dmulh22", 0x360B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmulh22<.f><.cc> 0,limm,limm 0011011011001011F1111111100QQQQQ. */ +{ "dmulh22", 0x36CB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmulh22<.f> a,limm,limm 0011011000110011F111111110AAAAAA. */ +{ "dmulh22", 0x36337F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmulh22<.f> 0,limm,limm 0011011000110011F111111110111110. */ +{ "dmulh22", 0x36337FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dmulh22<.f><.cc> 0,limm,limm 0011011011110011F1111111100QQQQQ. */ +{ "dmulh22", 0x36F37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dmulpf<.f> a,b,c 00101bbb00111010FBBBCCCCCCAAAAAA. */ +{ "dmulpf", 0x283A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmulpf<.f><.cc> b,b,c 00101bbb11111010FBBBCCCCCC0QQQQQ. */ +{ "dmulpf", 0x28FA0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dmulpf<.f> 0,b,c 00101bbb00111010FBBBCCCCCC111110. */ +{ "dmulpf", 0x283A003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dmulpf<.f> a,b,limm 00101bbb00111010FBBB111110AAAAAA. */ +{ "dmulpf", 0x283A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dmulpf<.f><.cc> b,b,limm 00101bbb11111010FBBB1111100QQQQQ. */ +{ "dmulpf", 0x28FA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* drsubh11<.f> a,b,c 00110bbb00010100FBBBCCCCCCAAAAAA. */ +{ "drsubh11", 0x30140000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* drsubh11<.f> 0,b,c 00110bbb00010100FBBBCCCCCC111110. */ +{ "drsubh11", 0x3014003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* drsubh11<.f><.cc> b,b,c 00110bbb11010100FBBBCCCCCC0QQQQQ. */ +{ "drsubh11", 0x30D40000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* drsubh11<.f> a,b,u6 00110bbb01010100FBBBuuuuuuAAAAAA. */ +{ "drsubh11", 0x30540000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* drsubh11<.f> 0,b,u6 00110bbb01010100FBBBuuuuuu111110. */ +{ "drsubh11", 0x3054003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* drsubh11<.f><.cc> b,b,u6 00110bbb11010100FBBBuuuuuu1QQQQQ. */ +{ "drsubh11", 0x30D40020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* drsubh11<.f> b,b,s12 00110bbb10010100FBBBssssssSSSSSS. */ +{ "drsubh11", 0x30940000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* drsubh11<.f> a,limm,c 0011011000010100F111CCCCCCAAAAAA. */ +{ "drsubh11", 0x36147000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* drsubh11<.f> a,b,limm 00110bbb00010100FBBB111110AAAAAA. */ +{ "drsubh11", 0x30140F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* drsubh11<.f> 0,limm,c 0011011000010100F111CCCCCC111110. */ +{ "drsubh11", 0x3614703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* drsubh11<.f> 0,b,limm 00110bbb00010100FBBB111110111110. */ +{ "drsubh11", 0x30140FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* drsubh11<.f><.cc> 0,limm,c 0011011011010100F111CCCCCC0QQQQQ. */ +{ "drsubh11", 0x36D47000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* drsubh11<.f><.cc> b,b,limm 00110bbb11010100FBBB1111100QQQQQ. */ +{ "drsubh11", 0x30D40F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* drsubh11<.f> a,limm,u6 0011011001010100F111uuuuuuAAAAAA. */ +{ "drsubh11", 0x36547000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* drsubh11<.f> 0,limm,u6 0011011001010100F111uuuuuu111110. */ +{ "drsubh11", 0x3654703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* drsubh11<.f><.cc> 0,limm,u6 0011011011010100F111uuuuuu1QQQQQ. */ +{ "drsubh11", 0x36D47020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* drsubh11<.f> 0,limm,s12 0011011010010100F111ssssssSSSSSS. */ +{ "drsubh11", 0x36947000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* drsubh11<.f> a,limm,limm 0011011000010100F111111110AAAAAA. */ +{ "drsubh11", 0x36147F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* drsubh11<.f> 0,limm,limm 0011011000010100F111111110111110. */ +{ "drsubh11", 0x36147FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* drsubh11<.f><.cc> 0,limm,limm 0011011011010100F1111111100QQQQQ. */ +{ "drsubh11", 0x36D47F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* drsubh12<.f> a,b,c 00110bbb00010101FBBBCCCCCCAAAAAA. */ +{ "drsubh12", 0x30150000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* drsubh12<.f> 0,b,c 00110bbb00010101FBBBCCCCCC111110. */ +{ "drsubh12", 0x3015003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* drsubh12<.f><.cc> b,b,c 00110bbb11010101FBBBCCCCCC0QQQQQ. */ +{ "drsubh12", 0x30D50000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* drsubh12<.f> a,b,u6 00110bbb01010101FBBBuuuuuuAAAAAA. */ +{ "drsubh12", 0x30550000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* drsubh12<.f> 0,b,u6 00110bbb01010101FBBBuuuuuu111110. */ +{ "drsubh12", 0x3055003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* drsubh12<.f><.cc> b,b,u6 00110bbb11010101FBBBuuuuuu1QQQQQ. */ +{ "drsubh12", 0x30D50020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* drsubh12<.f> b,b,s12 00110bbb10010101FBBBssssssSSSSSS. */ +{ "drsubh12", 0x30950000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* drsubh12<.f> a,limm,c 0011011000010101F111CCCCCCAAAAAA. */ +{ "drsubh12", 0x36157000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* drsubh12<.f> a,b,limm 00110bbb00010101FBBB111110AAAAAA. */ +{ "drsubh12", 0x30150F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* drsubh12<.f> 0,limm,c 0011011000010101F111CCCCCC111110. */ +{ "drsubh12", 0x3615703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* drsubh12<.f> 0,b,limm 00110bbb00010101FBBB111110111110. */ +{ "drsubh12", 0x30150FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* drsubh12<.f><.cc> 0,limm,c 0011011011010101F111CCCCCC0QQQQQ. */ +{ "drsubh12", 0x36D57000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* drsubh12<.f><.cc> b,b,limm 00110bbb11010101FBBB1111100QQQQQ. */ +{ "drsubh12", 0x30D50F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* drsubh12<.f> a,limm,u6 0011011001010101F111uuuuuuAAAAAA. */ +{ "drsubh12", 0x36557000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* drsubh12<.f> 0,limm,u6 0011011001010101F111uuuuuu111110. */ +{ "drsubh12", 0x3655703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* drsubh12<.f><.cc> 0,limm,u6 0011011011010101F111uuuuuu1QQQQQ. */ +{ "drsubh12", 0x36D57020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* drsubh12<.f> 0,limm,s12 0011011010010101F111ssssssSSSSSS. */ +{ "drsubh12", 0x36957000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* drsubh12<.f> a,limm,limm 0011011000010101F111111110AAAAAA. */ +{ "drsubh12", 0x36157F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* drsubh12<.f> 0,limm,limm 0011011000010101F111111110111110. */ +{ "drsubh12", 0x36157FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* drsubh12<.f><.cc> 0,limm,limm 0011011011010101F1111111100QQQQQ. */ +{ "drsubh12", 0x36D57F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* drsubh21<.f> a,b,c 00110bbb00010110FBBBCCCCCCAAAAAA. */ +{ "drsubh21", 0x30160000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* drsubh21<.f> 0,b,c 00110bbb00010110FBBBCCCCCC111110. */ +{ "drsubh21", 0x3016003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* drsubh21<.f><.cc> b,b,c 00110bbb11010110FBBBCCCCCC0QQQQQ. */ +{ "drsubh21", 0x30D60000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* drsubh21<.f> a,b,u6 00110bbb01010110FBBBuuuuuuAAAAAA. */ +{ "drsubh21", 0x30560000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* drsubh21<.f> 0,b,u6 00110bbb01010110FBBBuuuuuu111110. */ +{ "drsubh21", 0x3056003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* drsubh21<.f><.cc> b,b,u6 00110bbb11010110FBBBuuuuuu1QQQQQ. */ +{ "drsubh21", 0x30D60020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* drsubh21<.f> b,b,s12 00110bbb10010110FBBBssssssSSSSSS. */ +{ "drsubh21", 0x30960000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* drsubh21<.f> a,limm,c 0011011000010110F111CCCCCCAAAAAA. */ +{ "drsubh21", 0x36167000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* drsubh21<.f> a,b,limm 00110bbb00010110FBBB111110AAAAAA. */ +{ "drsubh21", 0x30160F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* drsubh21<.f> 0,limm,c 0011011000010110F111CCCCCC111110. */ +{ "drsubh21", 0x3616703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* drsubh21<.f> 0,b,limm 00110bbb00010110FBBB111110111110. */ +{ "drsubh21", 0x30160FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* drsubh21<.f><.cc> 0,limm,c 0011011011010110F111CCCCCC0QQQQQ. */ +{ "drsubh21", 0x36D67000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* drsubh21<.f><.cc> b,b,limm 00110bbb11010110FBBB1111100QQQQQ. */ +{ "drsubh21", 0x30D60F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* drsubh21<.f> a,limm,u6 0011011001010110F111uuuuuuAAAAAA. */ +{ "drsubh21", 0x36567000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* drsubh21<.f> 0,limm,u6 0011011001010110F111uuuuuu111110. */ +{ "drsubh21", 0x3656703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* drsubh21<.f><.cc> 0,limm,u6 0011011011010110F111uuuuuu1QQQQQ. */ +{ "drsubh21", 0x36D67020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* drsubh21<.f> 0,limm,s12 0011011010010110F111ssssssSSSSSS. */ +{ "drsubh21", 0x36967000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* drsubh21<.f> a,limm,limm 0011011000010110F111111110AAAAAA. */ +{ "drsubh21", 0x36167F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* drsubh21<.f> 0,limm,limm 0011011000010110F111111110111110. */ +{ "drsubh21", 0x36167FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* drsubh21<.f><.cc> 0,limm,limm 0011011011010110F1111111100QQQQQ. */ +{ "drsubh21", 0x36D67F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* drsubh22<.f> a,b,c 00110bbb00010111FBBBCCCCCCAAAAAA. */ +{ "drsubh22", 0x30170000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* drsubh22<.f> 0,b,c 00110bbb00010111FBBBCCCCCC111110. */ +{ "drsubh22", 0x3017003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* drsubh22<.f><.cc> b,b,c 00110bbb11010111FBBBCCCCCC0QQQQQ. */ +{ "drsubh22", 0x30D70000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* drsubh22<.f> a,b,u6 00110bbb01010111FBBBuuuuuuAAAAAA. */ +{ "drsubh22", 0x30570000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* drsubh22<.f> 0,b,u6 00110bbb01010111FBBBuuuuuu111110. */ +{ "drsubh22", 0x3057003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* drsubh22<.f><.cc> b,b,u6 00110bbb11010111FBBBuuuuuu1QQQQQ. */ +{ "drsubh22", 0x30D70020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* drsubh22<.f> b,b,s12 00110bbb10010111FBBBssssssSSSSSS. */ +{ "drsubh22", 0x30970000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* drsubh22<.f> a,limm,c 0011011000010111F111CCCCCCAAAAAA. */ +{ "drsubh22", 0x36177000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* drsubh22<.f> a,b,limm 00110bbb00010111FBBB111110AAAAAA. */ +{ "drsubh22", 0x30170F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* drsubh22<.f> 0,limm,c 0011011000010111F111CCCCCC111110. */ +{ "drsubh22", 0x3617703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* drsubh22<.f> 0,b,limm 00110bbb00010111FBBB111110111110. */ +{ "drsubh22", 0x30170FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* drsubh22<.f><.cc> 0,limm,c 0011011011010111F111CCCCCC0QQQQQ. */ +{ "drsubh22", 0x36D77000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* drsubh22<.f><.cc> b,b,limm 00110bbb11010111FBBB1111100QQQQQ. */ +{ "drsubh22", 0x30D70F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* drsubh22<.f> a,limm,u6 0011011001010111F111uuuuuuAAAAAA. */ +{ "drsubh22", 0x36577000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* drsubh22<.f> 0,limm,u6 0011011001010111F111uuuuuu111110. */ +{ "drsubh22", 0x3657703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* drsubh22<.f><.cc> 0,limm,u6 0011011011010111F111uuuuuu1QQQQQ. */ +{ "drsubh22", 0x36D77020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* drsubh22<.f> 0,limm,s12 0011011010010111F111ssssssSSSSSS. */ +{ "drsubh22", 0x36977000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* drsubh22<.f> a,limm,limm 0011011000010111F111111110AAAAAA. */ +{ "drsubh22", 0x36177F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* drsubh22<.f> 0,limm,limm 0011011000010111F111111110111110. */ +{ "drsubh22", 0x36177FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* drsubh22<.f><.cc> 0,limm,limm 0011011011010111F1111111100QQQQQ. */ +{ "drsubh22", 0x36D77F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dsubh11<.f> a,b,c 00110bbb00010000FBBBCCCCCCAAAAAA. */ +{ "dsubh11", 0x30100000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dsubh11<.f> 0,b,c 00110bbb00010000FBBBCCCCCC111110. */ +{ "dsubh11", 0x3010003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dsubh11<.f><.cc> b,b,c 00110bbb11010000FBBBCCCCCC0QQQQQ. */ +{ "dsubh11", 0x30D00000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dsubh11<.f> a,b,c 00110bbb00111000FBBBCCCCCCAAAAAA. */ +{ "dsubh11", 0x30380000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dsubh11<.f> 0,b,c 00110bbb00111000FBBBCCCCCC111110. */ +{ "dsubh11", 0x3038003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dsubh11<.f><.cc> b,b,c 00110bbb11111000FBBBCCCCCC0QQQQQ. */ +{ "dsubh11", 0x30F80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dsubh11<.f> a,b,u6 00110bbb01010000FBBBuuuuuuAAAAAA. */ +{ "dsubh11", 0x30500000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh11<.f> 0,b,u6 00110bbb01010000FBBBuuuuuu111110. */ +{ "dsubh11", 0x3050003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh11<.f><.cc> b,b,u6 00110bbb11010000FBBBuuuuuu1QQQQQ. */ +{ "dsubh11", 0x30D00020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh11<.f> a,b,u6 00110bbb01111000FBBBuuuuuuAAAAAA. */ +{ "dsubh11", 0x30780000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh11<.f> 0,b,u6 00110bbb01111000FBBBuuuuuu111110. */ +{ "dsubh11", 0x3078003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh11<.f><.cc> b,b,u6 00110bbb11111000FBBBuuuuuu1QQQQQ. */ +{ "dsubh11", 0x30F80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh11<.f> b,b,s12 00110bbb10010000FBBBssssssSSSSSS. */ +{ "dsubh11", 0x30900000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dsubh11<.f> b,b,s12 00110bbb10111000FBBBssssssSSSSSS. */ +{ "dsubh11", 0x30B80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dsubh11<.f> a,limm,c 0011011000010000F111CCCCCCAAAAAA. */ +{ "dsubh11", 0x36107000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dsubh11<.f> a,b,limm 00110bbb00010000FBBB111110AAAAAA. */ +{ "dsubh11", 0x30100F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dsubh11<.f> 0,limm,c 0011011000010000F111CCCCCC111110. */ +{ "dsubh11", 0x3610703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dsubh11<.f> 0,b,limm 00110bbb00010000FBBB111110111110. */ +{ "dsubh11", 0x30100FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dsubh11<.f><.cc> 0,limm,c 0011011011010000F111CCCCCC0QQQQQ. */ +{ "dsubh11", 0x36D07000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dsubh11<.f><.cc> b,b,limm 00110bbb11010000FBBB1111100QQQQQ. */ +{ "dsubh11", 0x30D00F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dsubh11<.f> a,limm,c 0011011000111000F111CCCCCCAAAAAA. */ +{ "dsubh11", 0x36387000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dsubh11<.f> a,b,limm 00110bbb00111000FBBB111110AAAAAA. */ +{ "dsubh11", 0x30380F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dsubh11<.f> 0,limm,c 0011011000111000F111CCCCCC111110. */ +{ "dsubh11", 0x3638703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dsubh11<.f> 0,b,limm 00110bbb00111000FBBB111110111110. */ +{ "dsubh11", 0x30380FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dsubh11<.f><.cc> 0,limm,c 0011011011111000F111CCCCCC0QQQQQ. */ +{ "dsubh11", 0x36F87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dsubh11<.f><.cc> b,b,limm 00110bbb11111000FBBB1111100QQQQQ. */ +{ "dsubh11", 0x30F80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dsubh11<.f> a,limm,u6 0011011001010000F111uuuuuuAAAAAA. */ +{ "dsubh11", 0x36507000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh11<.f> 0,limm,u6 0011011001010000F111uuuuuu111110. */ +{ "dsubh11", 0x3650703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh11<.f><.cc> 0,limm,u6 0011011011010000F111uuuuuu1QQQQQ. */ +{ "dsubh11", 0x36D07020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh11<.f> a,limm,u6 0011011001111000F111uuuuuuAAAAAA. */ +{ "dsubh11", 0x36787000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh11<.f> 0,limm,u6 0011011001111000F111uuuuuu111110. */ +{ "dsubh11", 0x3678703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh11<.f><.cc> 0,limm,u6 0011011011111000F111uuuuuu1QQQQQ. */ +{ "dsubh11", 0x36F87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh11<.f> 0,limm,s12 0011011010010000F111ssssssSSSSSS. */ +{ "dsubh11", 0x36907000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dsubh11<.f> 0,limm,s12 0011011010111000F111ssssssSSSSSS. */ +{ "dsubh11", 0x36B87000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dsubh11<.f> a,limm,limm 0011011000010000F111111110AAAAAA. */ +{ "dsubh11", 0x36107F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dsubh11<.f> 0,limm,limm 0011011000010000F111111110111110. */ +{ "dsubh11", 0x36107FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dsubh11<.f><.cc> 0,limm,limm 0011011011010000F1111111100QQQQQ. */ +{ "dsubh11", 0x36D07F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dsubh11<.f> a,limm,limm 0011011000111000F111111110AAAAAA. */ +{ "dsubh11", 0x36387F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dsubh11<.f> 0,limm,limm 0011011000111000F111111110111110. */ +{ "dsubh11", 0x36387FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dsubh11<.f><.cc> 0,limm,limm 0011011011111000F1111111100QQQQQ. */ +{ "dsubh11", 0x36F87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dsubh12<.f> a,b,c 00110bbb00010001FBBBCCCCCCAAAAAA. */ +{ "dsubh12", 0x30110000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dsubh12<.f> 0,b,c 00110bbb00010001FBBBCCCCCC111110. */ +{ "dsubh12", 0x3011003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dsubh12<.f><.cc> b,b,c 00110bbb11010001FBBBCCCCCC0QQQQQ. */ +{ "dsubh12", 0x30D10000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dsubh12<.f> a,b,c 00110bbb00111001FBBBCCCCCCAAAAAA. */ +{ "dsubh12", 0x30390000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dsubh12<.f> 0,b,c 00110bbb00111001FBBBCCCCCC111110. */ +{ "dsubh12", 0x3039003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dsubh12<.f><.cc> b,b,c 00110bbb11111001FBBBCCCCCC0QQQQQ. */ +{ "dsubh12", 0x30F90000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dsubh12<.f> a,b,u6 00110bbb01010001FBBBuuuuuuAAAAAA. */ +{ "dsubh12", 0x30510000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh12<.f> 0,b,u6 00110bbb01010001FBBBuuuuuu111110. */ +{ "dsubh12", 0x3051003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh12<.f><.cc> b,b,u6 00110bbb11010001FBBBuuuuuu1QQQQQ. */ +{ "dsubh12", 0x30D10020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh12<.f> a,b,u6 00110bbb01111001FBBBuuuuuuAAAAAA. */ +{ "dsubh12", 0x30790000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh12<.f> 0,b,u6 00110bbb01111001FBBBuuuuuu111110. */ +{ "dsubh12", 0x3079003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh12<.f><.cc> b,b,u6 00110bbb11111001FBBBuuuuuu1QQQQQ. */ +{ "dsubh12", 0x30F90020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh12<.f> b,b,s12 00110bbb10010001FBBBssssssSSSSSS. */ +{ "dsubh12", 0x30910000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dsubh12<.f> b,b,s12 00110bbb10111001FBBBssssssSSSSSS. */ +{ "dsubh12", 0x30B90000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dsubh12<.f> a,limm,c 0011011000010001F111CCCCCCAAAAAA. */ +{ "dsubh12", 0x36117000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dsubh12<.f> a,b,limm 00110bbb00010001FBBB111110AAAAAA. */ +{ "dsubh12", 0x30110F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dsubh12<.f> 0,limm,c 0011011000010001F111CCCCCC111110. */ +{ "dsubh12", 0x3611703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dsubh12<.f> 0,b,limm 00110bbb00010001FBBB111110111110. */ +{ "dsubh12", 0x30110FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dsubh12<.f><.cc> 0,limm,c 0011011011010001F111CCCCCC0QQQQQ. */ +{ "dsubh12", 0x36D17000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dsubh12<.f><.cc> b,b,limm 00110bbb11010001FBBB1111100QQQQQ. */ +{ "dsubh12", 0x30D10F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dsubh12<.f> a,limm,c 0011011000111001F111CCCCCCAAAAAA. */ +{ "dsubh12", 0x36397000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dsubh12<.f> a,b,limm 00110bbb00111001FBBB111110AAAAAA. */ +{ "dsubh12", 0x30390F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dsubh12<.f> 0,limm,c 0011011000111001F111CCCCCC111110. */ +{ "dsubh12", 0x3639703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dsubh12<.f> 0,b,limm 00110bbb00111001FBBB111110111110. */ +{ "dsubh12", 0x30390FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dsubh12<.f><.cc> 0,limm,c 0011011011111001F111CCCCCC0QQQQQ. */ +{ "dsubh12", 0x36F97000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dsubh12<.f><.cc> b,b,limm 00110bbb11111001FBBB1111100QQQQQ. */ +{ "dsubh12", 0x30F90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dsubh12<.f> a,limm,u6 0011011001010001F111uuuuuuAAAAAA. */ +{ "dsubh12", 0x36517000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh12<.f> 0,limm,u6 0011011001010001F111uuuuuu111110. */ +{ "dsubh12", 0x3651703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh12<.f><.cc> 0,limm,u6 0011011011010001F111uuuuuu1QQQQQ. */ +{ "dsubh12", 0x36D17020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh12<.f> a,limm,u6 0011011001111001F111uuuuuuAAAAAA. */ +{ "dsubh12", 0x36797000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh12<.f> 0,limm,u6 0011011001111001F111uuuuuu111110. */ +{ "dsubh12", 0x3679703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh12<.f><.cc> 0,limm,u6 0011011011111001F111uuuuuu1QQQQQ. */ +{ "dsubh12", 0x36F97020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh12<.f> 0,limm,s12 0011011010010001F111ssssssSSSSSS. */ +{ "dsubh12", 0x36917000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dsubh12<.f> 0,limm,s12 0011011010111001F111ssssssSSSSSS. */ +{ "dsubh12", 0x36B97000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dsubh12<.f> a,limm,limm 0011011000010001F111111110AAAAAA. */ +{ "dsubh12", 0x36117F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dsubh12<.f> 0,limm,limm 0011011000010001F111111110111110. */ +{ "dsubh12", 0x36117FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dsubh12<.f><.cc> 0,limm,limm 0011011011010001F1111111100QQQQQ. */ +{ "dsubh12", 0x36D17F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dsubh12<.f> a,limm,limm 0011011000111001F111111110AAAAAA. */ +{ "dsubh12", 0x36397F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dsubh12<.f> 0,limm,limm 0011011000111001F111111110111110. */ +{ "dsubh12", 0x36397FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dsubh12<.f><.cc> 0,limm,limm 0011011011111001F1111111100QQQQQ. */ +{ "dsubh12", 0x36F97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dsubh21<.f> a,b,c 00110bbb00010010FBBBCCCCCCAAAAAA. */ +{ "dsubh21", 0x30120000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dsubh21<.f> 0,b,c 00110bbb00010010FBBBCCCCCC111110. */ +{ "dsubh21", 0x3012003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dsubh21<.f><.cc> b,b,c 00110bbb11010010FBBBCCCCCC0QQQQQ. */ +{ "dsubh21", 0x30D20000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dsubh21<.f> a,b,c 00110bbb00111010FBBBCCCCCCAAAAAA. */ +{ "dsubh21", 0x303A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dsubh21<.f> 0,b,c 00110bbb00111010FBBBCCCCCC111110. */ +{ "dsubh21", 0x303A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dsubh21<.f><.cc> b,b,c 00110bbb11111010FBBBCCCCCC0QQQQQ. */ +{ "dsubh21", 0x30FA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dsubh21<.f> a,b,u6 00110bbb01010010FBBBuuuuuuAAAAAA. */ +{ "dsubh21", 0x30520000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh21<.f> 0,b,u6 00110bbb01010010FBBBuuuuuu111110. */ +{ "dsubh21", 0x3052003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh21<.f><.cc> b,b,u6 00110bbb11010010FBBBuuuuuu1QQQQQ. */ +{ "dsubh21", 0x30D20020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh21<.f> a,b,u6 00110bbb01111010FBBBuuuuuuAAAAAA. */ +{ "dsubh21", 0x307A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh21<.f> 0,b,u6 00110bbb01111010FBBBuuuuuu111110. */ +{ "dsubh21", 0x307A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh21<.f><.cc> b,b,u6 00110bbb11111010FBBBuuuuuu1QQQQQ. */ +{ "dsubh21", 0x30FA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh21<.f> b,b,s12 00110bbb10010010FBBBssssssSSSSSS. */ +{ "dsubh21", 0x30920000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dsubh21<.f> b,b,s12 00110bbb10111010FBBBssssssSSSSSS. */ +{ "dsubh21", 0x30BA0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dsubh21<.f> a,limm,c 0011011000010010F111CCCCCCAAAAAA. */ +{ "dsubh21", 0x36127000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dsubh21<.f> a,b,limm 00110bbb00010010FBBB111110AAAAAA. */ +{ "dsubh21", 0x30120F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dsubh21<.f> 0,limm,c 0011011000010010F111CCCCCC111110. */ +{ "dsubh21", 0x3612703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dsubh21<.f> 0,b,limm 00110bbb00010010FBBB111110111110. */ +{ "dsubh21", 0x30120FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dsubh21<.f><.cc> 0,limm,c 0011011011010010F111CCCCCC0QQQQQ. */ +{ "dsubh21", 0x36D27000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dsubh21<.f><.cc> b,b,limm 00110bbb11010010FBBB1111100QQQQQ. */ +{ "dsubh21", 0x30D20F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dsubh21<.f> a,limm,c 0011011000111010F111CCCCCCAAAAAA. */ +{ "dsubh21", 0x363A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dsubh21<.f> a,b,limm 00110bbb00111010FBBB111110AAAAAA. */ +{ "dsubh21", 0x303A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dsubh21<.f> 0,limm,c 0011011000111010F111CCCCCC111110. */ +{ "dsubh21", 0x363A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dsubh21<.f> 0,b,limm 00110bbb00111010FBBB111110111110. */ +{ "dsubh21", 0x303A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dsubh21<.f><.cc> 0,limm,c 0011011011111010F111CCCCCC0QQQQQ. */ +{ "dsubh21", 0x36FA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dsubh21<.f><.cc> b,b,limm 00110bbb11111010FBBB1111100QQQQQ. */ +{ "dsubh21", 0x30FA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dsubh21<.f> a,limm,u6 0011011001010010F111uuuuuuAAAAAA. */ +{ "dsubh21", 0x36527000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh21<.f> 0,limm,u6 0011011001010010F111uuuuuu111110. */ +{ "dsubh21", 0x3652703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh21<.f><.cc> 0,limm,u6 0011011011010010F111uuuuuu1QQQQQ. */ +{ "dsubh21", 0x36D27020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh21<.f> a,limm,u6 0011011001111010F111uuuuuuAAAAAA. */ +{ "dsubh21", 0x367A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh21<.f> 0,limm,u6 0011011001111010F111uuuuuu111110. */ +{ "dsubh21", 0x367A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh21<.f><.cc> 0,limm,u6 0011011011111010F111uuuuuu1QQQQQ. */ +{ "dsubh21", 0x36FA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh21<.f> 0,limm,s12 0011011010010010F111ssssssSSSSSS. */ +{ "dsubh21", 0x36927000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dsubh21<.f> 0,limm,s12 0011011010111010F111ssssssSSSSSS. */ +{ "dsubh21", 0x36BA7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dsubh21<.f> a,limm,limm 0011011000010010F111111110AAAAAA. */ +{ "dsubh21", 0x36127F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dsubh21<.f> 0,limm,limm 0011011000010010F111111110111110. */ +{ "dsubh21", 0x36127FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dsubh21<.f><.cc> 0,limm,limm 0011011011010010F1111111100QQQQQ. */ +{ "dsubh21", 0x36D27F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dsubh21<.f> a,limm,limm 0011011000111010F111111110AAAAAA. */ +{ "dsubh21", 0x363A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dsubh21<.f> 0,limm,limm 0011011000111010F111111110111110. */ +{ "dsubh21", 0x363A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dsubh21<.f><.cc> 0,limm,limm 0011011011111010F1111111100QQQQQ. */ +{ "dsubh21", 0x36FA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dsubh22<.f> a,b,c 00110bbb00010011FBBBCCCCCCAAAAAA. */ +{ "dsubh22", 0x30130000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dsubh22<.f> 0,b,c 00110bbb00010011FBBBCCCCCC111110. */ +{ "dsubh22", 0x3013003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dsubh22<.f><.cc> b,b,c 00110bbb11010011FBBBCCCCCC0QQQQQ. */ +{ "dsubh22", 0x30D30000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dsubh22<.f> a,b,c 00110bbb00111011FBBBCCCCCCAAAAAA. */ +{ "dsubh22", 0x303B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dsubh22<.f> 0,b,c 00110bbb00111011FBBBCCCCCC111110. */ +{ "dsubh22", 0x303B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* dsubh22<.f><.cc> b,b,c 00110bbb11111011FBBBCCCCCC0QQQQQ. */ +{ "dsubh22", 0x30FB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* dsubh22<.f> a,b,u6 00110bbb01010011FBBBuuuuuuAAAAAA. */ +{ "dsubh22", 0x30530000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh22<.f> 0,b,u6 00110bbb01010011FBBBuuuuuu111110. */ +{ "dsubh22", 0x3053003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh22<.f><.cc> b,b,u6 00110bbb11010011FBBBuuuuuu1QQQQQ. */ +{ "dsubh22", 0x30D30020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh22<.f> a,b,u6 00110bbb01111011FBBBuuuuuuAAAAAA. */ +{ "dsubh22", 0x307B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh22<.f> 0,b,u6 00110bbb01111011FBBBuuuuuu111110. */ +{ "dsubh22", 0x307B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh22<.f><.cc> b,b,u6 00110bbb11111011FBBBuuuuuu1QQQQQ. */ +{ "dsubh22", 0x30FB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh22<.f> b,b,s12 00110bbb10010011FBBBssssssSSSSSS. */ +{ "dsubh22", 0x30930000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dsubh22<.f> b,b,s12 00110bbb10111011FBBBssssssSSSSSS. */ +{ "dsubh22", 0x30BB0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* dsubh22<.f> a,limm,c 0011011000010011F111CCCCCCAAAAAA. */ +{ "dsubh22", 0x36137000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dsubh22<.f> a,b,limm 00110bbb00010011FBBB111110AAAAAA. */ +{ "dsubh22", 0x30130F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dsubh22<.f> 0,limm,c 0011011000010011F111CCCCCC111110. */ +{ "dsubh22", 0x3613703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dsubh22<.f> 0,b,limm 00110bbb00010011FBBB111110111110. */ +{ "dsubh22", 0x30130FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dsubh22<.f><.cc> 0,limm,c 0011011011010011F111CCCCCC0QQQQQ. */ +{ "dsubh22", 0x36D37000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dsubh22<.f><.cc> b,b,limm 00110bbb11010011FBBB1111100QQQQQ. */ +{ "dsubh22", 0x30D30F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dsubh22<.f> a,limm,c 0011011000111011F111CCCCCCAAAAAA. */ +{ "dsubh22", 0x363B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dsubh22<.f> a,b,limm 00110bbb00111011FBBB111110AAAAAA. */ +{ "dsubh22", 0x303B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dsubh22<.f> 0,limm,c 0011011000111011F111CCCCCC111110. */ +{ "dsubh22", 0x363B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* dsubh22<.f> 0,b,limm 00110bbb00111011FBBB111110111110. */ +{ "dsubh22", 0x303B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* dsubh22<.f><.cc> 0,limm,c 0011011011111011F111CCCCCC0QQQQQ. */ +{ "dsubh22", 0x36FB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* dsubh22<.f><.cc> b,b,limm 00110bbb11111011FBBB1111100QQQQQ. */ +{ "dsubh22", 0x30FB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* dsubh22<.f> a,limm,u6 0011011001010011F111uuuuuuAAAAAA. */ +{ "dsubh22", 0x36537000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh22<.f> 0,limm,u6 0011011001010011F111uuuuuu111110. */ +{ "dsubh22", 0x3653703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh22<.f><.cc> 0,limm,u6 0011011011010011F111uuuuuu1QQQQQ. */ +{ "dsubh22", 0x36D37020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh22<.f> a,limm,u6 0011011001111011F111uuuuuuAAAAAA. */ +{ "dsubh22", 0x367B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh22<.f> 0,limm,u6 0011011001111011F111uuuuuu111110. */ +{ "dsubh22", 0x367B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* dsubh22<.f><.cc> 0,limm,u6 0011011011111011F111uuuuuu1QQQQQ. */ +{ "dsubh22", 0x36FB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh22<.f> 0,limm,s12 0011011010010011F111ssssssSSSSSS. */ +{ "dsubh22", 0x36937000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dsubh22<.f> 0,limm,s12 0011011010111011F111ssssssSSSSSS. */ +{ "dsubh22", 0x36BB7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* dsubh22<.f> a,limm,limm 0011011000010011F111111110AAAAAA. */ +{ "dsubh22", 0x36137F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dsubh22<.f> 0,limm,limm 0011011000010011F111111110111110. */ +{ "dsubh22", 0x36137FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dsubh22<.f><.cc> 0,limm,limm 0011011011010011F1111111100QQQQQ. */ +{ "dsubh22", 0x36D37F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dsubh22<.f> a,limm,limm 0011011000111011F111111110AAAAAA. */ +{ "dsubh22", 0x363B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dsubh22<.f> 0,limm,limm 0011011000111011F111111110111110. */ +{ "dsubh22", 0x363B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* dsubh22<.f><.cc> 0,limm,limm 0011011011111011F1111111100QQQQQ. */ +{ "dsubh22", 0x36FB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARC_FLOAT, DPA, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* dsync 00100010011011110001RRRRRR111111. */ +{ "dsync", 0x226F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }}, + +/* ei_s u10 010111uuuuuuuuuu. */ +{ "ei_s", 0x00005C00, 0x0000FC00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, EI, CD2, { OPERAND_UIMM10_6_S }, { 0 }}, + +/* enter_s u6 110000UU111uuuu0. */ +{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ENTER, CD1, { OPERAND_UIMM6_11_S }, { 0 }}, + +/* ex<.di> b,c 00100bbb00101111DBBBCCCCCC001100. */ +{ "ex", 0x202F000C, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* ex<.di> b,u6 00100bbb01101111DBBBuuuuuu001100. */ +{ "ex", 0x206F000C, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* ex<.di> b,limm 00100bbb00101111DBBB111110001100. */ +{ "ex", 0x202F0F8C, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* ex<.di> limm,c 0010011000101111D111CCCCCC001100. */ +{ "ex", 0x262F700C, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* ex<.di> limm,u6 0010011001101111D111uuuuuu001100. */ +{ "ex", 0x266F700C, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* ex<.di> limm,limm 0010011000101111D111111110001100. */ +{ "ex", 0x262F7F8C, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* extb<.f> b,c 00100bbb00101111FBBBCCCCCC000111. */ +{ "extb", 0x202F0007, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* extb<.f> 0,c 0010011000101111F111CCCCCC000111. */ +{ "extb", 0x262F7007, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* extb<.f> b,u6 00100bbb01101111FBBBuuuuuu000111. */ +{ "extb", 0x206F0007, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* extb<.f> 0,u6 0010011001101111F111uuuuuu000111. */ +{ "extb", 0x266F7007, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* extb<.f> b,limm 00100bbb00101111FBBB111110000111. */ +{ "extb", 0x202F0F87, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* extb<.f> 0,limm 0010011000101111F111111110000111. */ +{ "extb", 0x262F7F87, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* extb_s b,c 01111bbbccc01111. */ +{ "extb_s", 0x0000780F, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, + +/* exth<.f> b,c 00100bbb00101111FBBBCCCCCC001000. */ +{ "exth", 0x202F0008, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* exth<.f> 0,c 0010011000101111F111CCCCCC001000. */ +{ "exth", 0x262F7008, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* exth<.f> b,u6 00100bbb01101111FBBBuuuuuu001000. */ +{ "exth", 0x206F0008, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* exth<.f> 0,u6 0010011001101111F111uuuuuu001000. */ +{ "exth", 0x266F7008, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* exth<.f> b,limm 00100bbb00101111FBBB111110001000. */ +{ "exth", 0x202F0F88, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* exth<.f> 0,limm 0010011000101111F111111110001000. */ +{ "exth", 0x262F7F88, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* exth_s b,c 01111bbbccc10000. */ +{ "exth_s", 0x00007810, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, + +/* extw<.f> b,c 00100bbb00101111FBBBCCCCCC001000. */ +{ "extw", 0x202F0008, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* extw<.f> 0,c 0010011000101111F111CCCCCC001000. */ +{ "extw", 0x262F7008, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* extw<.f> b,u6 00100bbb01101111FBBBuuuuuu001000. */ +{ "extw", 0x206F0008, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* extw<.f> 0,u6 0010011001101111F111uuuuuu001000. */ +{ "extw", 0x266F7008, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* extw<.f> b,limm 00100bbb00101111FBBB111110001000. */ +{ "extw", 0x202F0F88, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* extw<.f> 0,limm 0010011000101111F111111110001000. */ +{ "extw", 0x262F7F88, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* extw_s b,c 01111bbbccc10000. */ +{ "extw_s", 0x00007810, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, + +/* fadd<.f> a,b,c 00110bbb00000001FBBBCCCCCCAAAAAA. */ +{ "fadd", 0x30010000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* fadd<.f> 0,b,c 00110bbb00000001FBBBCCCCCC111110. */ +{ "fadd", 0x3001003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* fadd<.f><.cc> b,b,c 00110bbb11000001FBBBCCCCCC0QQQQQ. */ +{ "fadd", 0x30C10000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* fadd<.f> a,b,u6 00110bbb01000001FBBBuuuuuuAAAAAA. */ +{ "fadd", 0x30410000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* fadd<.f> 0,b,u6 00110bbb01000001FBBBuuuuuu111110. */ +{ "fadd", 0x3041003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* fadd<.f><.cc> b,b,u6 00110bbb11000001FBBBuuuuuu1QQQQQ. */ +{ "fadd", 0x30C10020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* fadd<.f> b,b,s12 00110bbb10000001FBBBssssssSSSSSS. */ +{ "fadd", 0x30810000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* fadd<.f> a,limm,c 0011011000000001F111CCCCCCAAAAAA. */ +{ "fadd", 0x36017000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* fadd<.f> a,b,limm 00110bbb00000001FBBB111110AAAAAA. */ +{ "fadd", 0x30010F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* fadd<.f> 0,limm,c 0011011000000001F111CCCCCC111110. */ +{ "fadd", 0x3601703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* fadd<.f> 0,b,limm 00110bbb00000001FBBB111110111110. */ +{ "fadd", 0x30010FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* fadd<.f><.cc> 0,limm,c 0011011011000001F111CCCCCC0QQQQQ. */ +{ "fadd", 0x36C17000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* fadd<.f><.cc> b,b,limm 00110bbb11000001FBBB1111100QQQQQ. */ +{ "fadd", 0x30C10F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* fadd<.f> a,limm,u6 0011011001000001F111uuuuuuAAAAAA. */ +{ "fadd", 0x36417000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* fadd<.f> 0,limm,u6 0011011001000001F111uuuuuu111110. */ +{ "fadd", 0x3641703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* fadd<.f><.cc> 0,limm,u6 0011011011000001F111uuuuuu1QQQQQ. */ +{ "fadd", 0x36C17020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* fadd<.f> 0,limm,s12 0011011010000001F111ssssssSSSSSS. */ +{ "fadd", 0x36817000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* fadd<.f> a,limm,limm 0011011000000001F111111110AAAAAA. */ +{ "fadd", 0x36017F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* fadd<.f> 0,limm,limm 0011011000000001F111111110111110. */ +{ "fadd", 0x36017FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* fadd<.f><.cc> 0,limm,limm 0011011011000001F1111111100QQQQQ. */ +{ "fadd", 0x36C17F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* fbfdw<.f> b,c 00101bbb00101111FBBBCCCCCC001011. */ +{ "fbfdw", 0x282F000B, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { C_F }}, + +/* fbfdw<.f> 0,c 0010111000101111F111CCCCCC001011. */ +{ "fbfdw", 0x2E2F700B, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* fbfdw<.f> b,u6 00101bbb01101111FBBBuuuuuu001011. */ +{ "fbfdw", 0x286F000B, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { C_F }}, + +/* fbfdw<.f> 0,u6 0010111001101111F111uuuuuu001011. */ +{ "fbfdw", 0x2E6F700B, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* fbfdw<.f> b,limm 00101bbb00101111FBBB111110001011. */ +{ "fbfdw", 0x282F0F8B, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { C_F }}, + +/* fbfdw<.f> 0,limm 0010111000101111F111111110001011. */ +{ "fbfdw", 0x2E2F7F8B, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* fcvt32 a,b,c 00110bbb000010000BBBCCCCCCAAAAAA. */ +{ "fcvt32", 0x30080000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fcvt32 0,b,c 00110bbb000010000BBBCCCCCC111110. */ +{ "fcvt32", 0x3008003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fcvt32<.cc> b,b,c 00110bbb110010000BBBCCCCCC0QQQQQ. */ +{ "fcvt32", 0x30C80000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* fcvt32 a,b,u6 00110bbb010010000BBBuuuuuuAAAAAA. */ +{ "fcvt32", 0x30480000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fcvt32 0,b,u6 00110bbb010010000BBBuuuuuu111110. */ +{ "fcvt32", 0x3048003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fcvt32<.cc> b,b,u6 00110bbb110010000BBBuuuuuu1QQQQQ. */ +{ "fcvt32", 0x30C80020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fcvt32 b,b,s12 00110bbb100010000BBBssssssSSSSSS. */ +{ "fcvt32", 0x30880000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* fcvt32 a,limm,c 00110110000010000111CCCCCCAAAAAA. */ +{ "fcvt32", 0x36087000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fcvt32 a,b,limm 00110bbb000010000BBB111110AAAAAA. */ +{ "fcvt32", 0x30080F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fcvt32 0,limm,c 00110110000010000111CCCCCC111110. */ +{ "fcvt32", 0x3608703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fcvt32 0,b,limm 00110bbb000010000BBB111110111110. */ +{ "fcvt32", 0x30080FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fcvt32<.cc> b,b,limm 00110bbb110010000BBB1111100QQQQQ. */ +{ "fcvt32", 0x30C80F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* fcvt32<.cc> 0,limm,c 00110110110010000111CCCCCC0QQQQQ. */ +{ "fcvt32", 0x36C87000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* fcvt32 a,limm,u6 00110110010010000111uuuuuuAAAAAA. */ +{ "fcvt32", 0x36487000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fcvt32 0,limm,u6 00110110010010000111uuuuuu111110. */ +{ "fcvt32", 0x3648703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fcvt32<.cc> 0,limm,u6 00110110110010000111uuuuuu1QQQQQ. */ +{ "fcvt32", 0x36C87020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fcvt32 0,limm,s12 00110110100010000111ssssssSSSSSS. */ +{ "fcvt32", 0x36887000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* fcvt32 a,limm,limm 00110110000010000111111110AAAAAA. */ +{ "fcvt32", 0x36087F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fcvt32 0,limm,limm 00110110000010000111111110111110. */ +{ "fcvt32", 0x36087FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fcvt32<.cc> 0,limm,limm 001101101100100001111111100QQQQQ. */ +{ "fcvt32", 0x36C87F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* fcvt32_64 a,b,c 00110bbb000010010BBBCCCCCCAAAAAA. */ +{ "fcvt32_64", 0x30090000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fcvt32_64 0,b,c 00110bbb000010010BBBCCCCCC111110. */ +{ "fcvt32_64", 0x3009003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fcvt32_64<.cc> b,b,c 00110bbb110010010BBBCCCCCC0QQQQQ. */ +{ "fcvt32_64", 0x30C90000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* fcvt32_64 a,b,u6 00110bbb010010010BBBuuuuuuAAAAAA. */ +{ "fcvt32_64", 0x30490000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fcvt32_64 0,b,u6 00110bbb010010010BBBuuuuuu111110. */ +{ "fcvt32_64", 0x3049003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fcvt32_64<.cc> b,b,u6 00110bbb110010010BBBuuuuuu1QQQQQ. */ +{ "fcvt32_64", 0x30C90020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fcvt32_64 b,b,s12 00110bbb100010010BBBssssssSSSSSS. */ +{ "fcvt32_64", 0x30890000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* fcvt32_64 a,limm,c 00110110000010010111CCCCCCAAAAAA. */ +{ "fcvt32_64", 0x36097000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fcvt32_64 a,b,limm 00110bbb000010010BBB111110AAAAAA. */ +{ "fcvt32_64", 0x30090F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fcvt32_64 0,limm,c 00110110000010010111CCCCCC111110. */ +{ "fcvt32_64", 0x3609703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fcvt32_64 0,b,limm 00110bbb000010010BBB111110111110. */ +{ "fcvt32_64", 0x30090FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fcvt32_64<.cc> b,b,limm 00110bbb110010010BBB1111100QQQQQ. */ +{ "fcvt32_64", 0x30C90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* fcvt32_64<.cc> 0,limm,c 00110110110010010111CCCCCC0QQQQQ. */ +{ "fcvt32_64", 0x36C97000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* fcvt32_64 a,limm,u6 00110110010010010111uuuuuuAAAAAA. */ +{ "fcvt32_64", 0x36497000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fcvt32_64 0,limm,u6 00110110010010010111uuuuuu111110. */ +{ "fcvt32_64", 0x3649703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fcvt32_64<.cc> 0,limm,u6 00110110110010010111uuuuuu1QQQQQ. */ +{ "fcvt32_64", 0x36C97020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fcvt32_64 0,limm,s12 00110110100010010111ssssssSSSSSS. */ +{ "fcvt32_64", 0x36897000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* fcvt32_64 a,limm,limm 00110110000010010111111110AAAAAA. */ +{ "fcvt32_64", 0x36097F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fcvt32_64 0,limm,limm 00110110000010010111111110111110. */ +{ "fcvt32_64", 0x36097FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fcvt32_64<.cc> 0,limm,limm 001101101100100101111111100QQQQQ. */ +{ "fcvt32_64", 0x36C97F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* fcvt64 a,b,c 00110bbb001110000BBBCCCCCCAAAAAA. */ +{ "fcvt64", 0x30380000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fcvt64 0,b,c 00110bbb001110000BBBCCCCCC111110. */ +{ "fcvt64", 0x3038003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fcvt64<.cc> b,b,c 00110bbb111110000BBBCCCCCC0QQQQQ. */ +{ "fcvt64", 0x30F80000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* fcvt64 a,b,u6 00110bbb011110000BBBuuuuuuAAAAAA. */ +{ "fcvt64", 0x30780000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fcvt64 0,b,u6 00110bbb011110000BBBuuuuuu111110. */ +{ "fcvt64", 0x3078003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fcvt64<.cc> b,b,u6 00110bbb111110000BBBuuuuuu1QQQQQ. */ +{ "fcvt64", 0x30F80020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fcvt64 b,b,s12 00110bbb101110000BBBssssssSSSSSS. */ +{ "fcvt64", 0x30B80000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* fcvt64 a,limm,c 00110110001110000111CCCCCCAAAAAA. */ +{ "fcvt64", 0x36387000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fcvt64 a,b,limm 00110bbb001110000BBB111110AAAAAA. */ +{ "fcvt64", 0x30380F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fcvt64 0,limm,c 00110110001110000111CCCCCC111110. */ +{ "fcvt64", 0x3638703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fcvt64 0,b,limm 00110bbb001110000BBB111110111110. */ +{ "fcvt64", 0x30380FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fcvt64<.cc> b,b,limm 00110bbb111110000BBB1111100QQQQQ. */ +{ "fcvt64", 0x30F80F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* fcvt64<.cc> 0,limm,c 00110110111110000111CCCCCC0QQQQQ. */ +{ "fcvt64", 0x36F87000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* fcvt64 a,limm,u6 00110110011110000111uuuuuuAAAAAA. */ +{ "fcvt64", 0x36787000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fcvt64 0,limm,u6 00110110011110000111uuuuuu111110. */ +{ "fcvt64", 0x3678703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fcvt64<.cc> 0,limm,u6 00110110111110000111uuuuuu1QQQQQ. */ +{ "fcvt64", 0x36F87020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fcvt64 0,limm,s12 00110110101110000111ssssssSSSSSS. */ +{ "fcvt64", 0x36B87000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* fcvt64 a,limm,limm 00110110001110000111111110AAAAAA. */ +{ "fcvt64", 0x36387F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fcvt64 0,limm,limm 00110110001110000111111110111110. */ +{ "fcvt64", 0x36387FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fcvt64<.cc> 0,limm,limm 001101101111100001111111100QQQQQ. */ +{ "fcvt64", 0x36F87F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* fcvt64_32 a,b,c 00110bbb001110010BBBCCCCCCAAAAAA. */ +{ "fcvt64_32", 0x30390000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fcvt64_32 0,b,c 00110bbb001110010BBBCCCCCC111110. */ +{ "fcvt64_32", 0x3039003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fcvt64_32<.cc> b,b,c 00110bbb111110010BBBCCCCCC0QQQQQ. */ +{ "fcvt64_32", 0x30F90000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* fcvt64_32 a,b,u6 00110bbb011110010BBBuuuuuuAAAAAA. */ +{ "fcvt64_32", 0x30790000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fcvt64_32 0,b,u6 00110bbb011110010BBBuuuuuu111110. */ +{ "fcvt64_32", 0x3079003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fcvt64_32<.cc> b,b,u6 00110bbb111110010BBBuuuuuu1QQQQQ. */ +{ "fcvt64_32", 0x30F90020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fcvt64_32 b,b,s12 00110bbb101110010BBBssssssSSSSSS. */ +{ "fcvt64_32", 0x30B90000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* fcvt64_32 a,limm,c 00110110001110010111CCCCCCAAAAAA. */ +{ "fcvt64_32", 0x36397000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fcvt64_32 a,b,limm 00110bbb001110010BBB111110AAAAAA. */ +{ "fcvt64_32", 0x30390F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fcvt64_32 0,limm,c 00110110001110010111CCCCCC111110. */ +{ "fcvt64_32", 0x3639703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fcvt64_32 0,b,limm 00110bbb001110010BBB111110111110. */ +{ "fcvt64_32", 0x30390FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fcvt64_32<.cc> b,b,limm 00110bbb111110010BBB1111100QQQQQ. */ +{ "fcvt64_32", 0x30F90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* fcvt64_32<.cc> 0,limm,c 00110110111110010111CCCCCC0QQQQQ. */ +{ "fcvt64_32", 0x36F97000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* fcvt64_32 a,limm,u6 00110110011110010111uuuuuuAAAAAA. */ +{ "fcvt64_32", 0x36797000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fcvt64_32 0,limm,u6 00110110011110010111uuuuuu111110. */ +{ "fcvt64_32", 0x3679703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fcvt64_32<.cc> 0,limm,u6 00110110111110010111uuuuuu1QQQQQ. */ +{ "fcvt64_32", 0x36F97020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fcvt64_32 0,limm,s12 00110110101110010111ssssssSSSSSS. */ +{ "fcvt64_32", 0x36B97000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* fcvt64_32 a,limm,limm 00110110001110010111111110AAAAAA. */ +{ "fcvt64_32", 0x36397F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fcvt64_32 0,limm,limm 00110110001110010111111110111110. */ +{ "fcvt64_32", 0x36397FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fcvt64_32<.cc> 0,limm,limm 001101101111100101111111100QQQQQ. */ +{ "fcvt64_32", 0x36F97F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, CVT, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* fdadd a,b,c 00110bbb001100010BBBCCCCCCAAAAAA. */ +{ "fdadd", 0x30310000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fdadd 0,b,c 00110bbb001100010BBBCCCCCC111110. */ +{ "fdadd", 0x3031003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fdadd<.cc> b,b,c 00110bbb111100010BBBCCCCCC0QQQQQ. */ +{ "fdadd", 0x30F10000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* fdadd a,b,u6 00110bbb011100010BBBuuuuuuAAAAAA. */ +{ "fdadd", 0x30710000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdadd 0,b,u6 00110bbb011100010BBBuuuuuu111110. */ +{ "fdadd", 0x3071003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdadd<.cc> b,b,u6 00110bbb111100010BBBuuuuuu1QQQQQ. */ +{ "fdadd", 0x30F10020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fdadd b,b,s12 00110bbb101100010BBBssssssSSSSSS. */ +{ "fdadd", 0x30B10000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* fdadd a,limm,c 00110110001100010111CCCCCCAAAAAA. */ +{ "fdadd", 0x36317000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fdadd a,b,limm 00110bbb001100010BBB111110AAAAAA. */ +{ "fdadd", 0x30310F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fdadd 0,limm,c 00110110001100010111CCCCCC111110. */ +{ "fdadd", 0x3631703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fdadd 0,b,limm 00110bbb001100010BBB111110111110. */ +{ "fdadd", 0x30310FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fdadd<.cc> b,b,limm 00110bbb111100010BBB1111100QQQQQ. */ +{ "fdadd", 0x30F10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* fdadd<.cc> 0,limm,c 00110110111100010111CCCCCC0QQQQQ. */ +{ "fdadd", 0x36F17000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* fdadd a,limm,u6 00110110011100010111uuuuuuAAAAAA. */ +{ "fdadd", 0x36717000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdadd 0,limm,u6 00110110011100010111uuuuuu111110. */ +{ "fdadd", 0x3671703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdadd<.cc> 0,limm,u6 00110110111100010111uuuuuu1QQQQQ. */ +{ "fdadd", 0x36F17020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fdadd 0,limm,s12 00110110101100010111ssssssSSSSSS. */ +{ "fdadd", 0x36B17000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* fdadd a,limm,limm 00110110001100010111111110AAAAAA. */ +{ "fdadd", 0x36317F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fdadd 0,limm,limm 00110110001100010111111110111110. */ +{ "fdadd", 0x36317FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fdadd<.cc> 0,limm,limm 001101101111000101111111100QQQQQ. */ +{ "fdadd", 0x36F17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* fdcmp b,c 00110bbb001100111BBBCCCCCC000000. */ +{ "fdcmp", 0x30338000, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fdcmp<.cc> b,c 00110bbb111100111BBBCCCCCC0QQQQQ. */ +{ "fdcmp", 0x30F38000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RC }, { C_CC }}, + +/* fdcmp b,u6 00110bbb011100111BBBuuuuuu000000. */ +{ "fdcmp", 0x30738000, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdcmp<.cc> b,u6 00110bbb111100111BBBuuuuuu1QQQQQ. */ +{ "fdcmp", 0x30F38020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fdcmp b,s12 00110bbb101100111BBBssssssSSSSSS. */ +{ "fdcmp", 0x30B38000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, + +/* fdcmp limm,c 00110110001100111111CCCCCC000000. */ +{ "fdcmp", 0x3633F000, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fdcmp b,limm 00110bbb001100111BBB111110000000. */ +{ "fdcmp", 0x30338F80, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fdcmp<.cc> b,limm 00110bbb111100111BBB1111100QQQQQ. */ +{ "fdcmp", 0x30F38F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, + +/* fdcmp<.cc> limm,c 00110110111100111111CCCCCC0QQQQQ. */ +{ "fdcmp", 0x36F3F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* fdcmp limm,u6 00110110011100111111uuuuuu000000. */ +{ "fdcmp", 0x3673F000, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdcmp<.cc> limm,u6 00110110111100111111uuuuuu1QQQQQ. */ +{ "fdcmp", 0x36F3F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fdcmp limm,s12 00110110101100111111ssssssSSSSSS. */ +{ "fdcmp", 0x36B3F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* fdcmp limm,limm 00110110001100111111111110000000. */ +{ "fdcmp", 0x3633FF80, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fdcmp<.cc> limm,limm 001101101111001111111111100QQQQQ. */ +{ "fdcmp", 0x36F3FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* fdcmpf b,c 00110bbb001101001BBBCCCCCC000000. */ +{ "fdcmpf", 0x30348000, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fdcmpf<.cc> b,c 00110bbb111101001BBBCCCCCC0QQQQQ. */ +{ "fdcmpf", 0x30F48000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RC }, { C_CC }}, + +/* fdcmpf b,u6 00110bbb011101001BBBuuuuuu000000. */ +{ "fdcmpf", 0x30748000, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdcmpf<.cc> b,u6 00110bbb111101001BBBuuuuuu1QQQQQ. */ +{ "fdcmpf", 0x30F48020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fdcmpf b,s12 00110bbb101101001BBBssssssSSSSSS. */ +{ "fdcmpf", 0x30B48000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, + +/* fdcmpf limm,c 00110110001101001111CCCCCC000000. */ +{ "fdcmpf", 0x3634F000, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fdcmpf b,limm 00110bbb001101001BBB111110000000. */ +{ "fdcmpf", 0x30348F80, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fdcmpf<.cc> b,limm 00110bbb111101001BBB1111100QQQQQ. */ +{ "fdcmpf", 0x30F48F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, + +/* fdcmpf<.cc> limm,c 00110110111101001111CCCCCC0QQQQQ. */ +{ "fdcmpf", 0x36F4F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* fdcmpf limm,u6 00110110011101001111uuuuuu000000. */ +{ "fdcmpf", 0x3674F000, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdcmpf<.cc> limm,u6 00110110111101001111uuuuuu1QQQQQ. */ +{ "fdcmpf", 0x36F4F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fdcmpf limm,s12 00110110101101001111ssssssSSSSSS. */ +{ "fdcmpf", 0x36B4F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* fdcmpf limm,limm 00110110001101001111111110000000. */ +{ "fdcmpf", 0x3634FF80, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fdcmpf<.cc> limm,limm 001101101111010011111111100QQQQQ. */ +{ "fdcmpf", 0x36F4FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* fddiv a,b,c 00110bbb001101110BBBCCCCCCAAAAAA. */ +{ "fddiv", 0x30370000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fddiv 0,b,c 00110bbb001101110BBBCCCCCC111110. */ +{ "fddiv", 0x3037003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fddiv<.cc> b,b,c 00110bbb111101110BBBCCCCCC0QQQQQ. */ +{ "fddiv", 0x30F70000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* fddiv a,b,u6 00110bbb011101110BBBuuuuuuAAAAAA. */ +{ "fddiv", 0x30770000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fddiv 0,b,u6 00110bbb011101110BBBuuuuuu111110. */ +{ "fddiv", 0x3077003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fddiv<.cc> b,b,u6 00110bbb111101110BBBuuuuuu1QQQQQ. */ +{ "fddiv", 0x30F70020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fddiv b,b,s12 00110bbb101101110BBBssssssSSSSSS. */ +{ "fddiv", 0x30B70000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* fddiv a,limm,c 00110110001101110111CCCCCCAAAAAA. */ +{ "fddiv", 0x36377000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fddiv a,b,limm 00110bbb001101110BBB111110AAAAAA. */ +{ "fddiv", 0x30370F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fddiv 0,limm,c 00110110001101110111CCCCCC111110. */ +{ "fddiv", 0x3637703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fddiv 0,b,limm 00110bbb001101110BBB111110111110. */ +{ "fddiv", 0x30370FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fddiv<.cc> b,b,limm 00110bbb111101110BBB1111100QQQQQ. */ +{ "fddiv", 0x30F70F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* fddiv<.cc> 0,limm,c 00110110111101110111CCCCCC0QQQQQ. */ +{ "fddiv", 0x36F77000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* fddiv a,limm,u6 00110110011101110111uuuuuuAAAAAA. */ +{ "fddiv", 0x36777000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fddiv 0,limm,u6 00110110011101110111uuuuuu111110. */ +{ "fddiv", 0x3677703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fddiv<.cc> 0,limm,u6 00110110111101110111uuuuuu1QQQQQ. */ +{ "fddiv", 0x36F77020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fddiv 0,limm,s12 00110110101101110111ssssssSSSSSS. */ +{ "fddiv", 0x36B77000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* fddiv a,limm,limm 00110110001101110111111110AAAAAA. */ +{ "fddiv", 0x36377F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fddiv 0,limm,limm 00110110001101110111111110111110. */ +{ "fddiv", 0x36377FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fddiv<.cc> 0,limm,limm 001101101111011101111111100QQQQQ. */ +{ "fddiv", 0x36F77F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* fdmadd a,b,c 00110bbb001101010BBBCCCCCCAAAAAA. */ +{ "fdmadd", 0x30350000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fdmadd 0,b,c 00110bbb001101010BBBCCCCCC111110. */ +{ "fdmadd", 0x3035003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fdmadd<.cc> b,b,c 00110bbb111101010BBBCCCCCC0QQQQQ. */ +{ "fdmadd", 0x30F50000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* fdmadd a,b,u6 00110bbb011101010BBBuuuuuuAAAAAA. */ +{ "fdmadd", 0x30750000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdmadd 0,b,u6 00110bbb011101010BBBuuuuuu111110. */ +{ "fdmadd", 0x3075003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdmadd<.cc> b,b,u6 00110bbb111101010BBBuuuuuu1QQQQQ. */ +{ "fdmadd", 0x30F50020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fdmadd b,b,s12 00110bbb101101010BBBssssssSSSSSS. */ +{ "fdmadd", 0x30B50000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* fdmadd a,limm,c 00110110001101010111CCCCCCAAAAAA. */ +{ "fdmadd", 0x36357000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fdmadd a,b,limm 00110bbb001101010BBB111110AAAAAA. */ +{ "fdmadd", 0x30350F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fdmadd 0,limm,c 00110110001101010111CCCCCC111110. */ +{ "fdmadd", 0x3635703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fdmadd 0,b,limm 00110bbb001101010BBB111110111110. */ +{ "fdmadd", 0x30350FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fdmadd<.cc> b,b,limm 00110bbb111101010BBB1111100QQQQQ. */ +{ "fdmadd", 0x30F50F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* fdmadd<.cc> 0,limm,c 00110110111101010111CCCCCC0QQQQQ. */ +{ "fdmadd", 0x36F57000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* fdmadd a,limm,u6 00110110011101010111uuuuuuAAAAAA. */ +{ "fdmadd", 0x36757000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdmadd 0,limm,u6 00110110011101010111uuuuuu111110. */ +{ "fdmadd", 0x3675703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdmadd<.cc> 0,limm,u6 00110110111101010111uuuuuu1QQQQQ. */ +{ "fdmadd", 0x36F57020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fdmadd 0,limm,s12 00110110101101010111ssssssSSSSSS. */ +{ "fdmadd", 0x36B57000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* fdmadd a,limm,limm 00110110001101010111111110AAAAAA. */ +{ "fdmadd", 0x36357F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fdmadd 0,limm,limm 00110110001101010111111110111110. */ +{ "fdmadd", 0x36357FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fdmadd<.cc> 0,limm,limm 001101101111010101111111100QQQQQ. */ +{ "fdmadd", 0x36F57F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* fdmsub a,b,c 00110bbb001101100BBBCCCCCCAAAAAA. */ +{ "fdmsub", 0x30360000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fdmsub 0,b,c 00110bbb001101100BBBCCCCCC111110. */ +{ "fdmsub", 0x3036003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fdmsub<.cc> b,b,c 00110bbb111101100BBBCCCCCC0QQQQQ. */ +{ "fdmsub", 0x30F60000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* fdmsub a,b,u6 00110bbb011101100BBBuuuuuuAAAAAA. */ +{ "fdmsub", 0x30760000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdmsub 0,b,u6 00110bbb011101100BBBuuuuuu111110. */ +{ "fdmsub", 0x3076003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdmsub<.cc> b,b,u6 00110bbb111101100BBBuuuuuu1QQQQQ. */ +{ "fdmsub", 0x30F60020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fdmsub b,b,s12 00110bbb101101100BBBssssssSSSSSS. */ +{ "fdmsub", 0x30B60000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* fdmsub a,limm,c 00110110001101100111CCCCCCAAAAAA. */ +{ "fdmsub", 0x36367000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fdmsub a,b,limm 00110bbb001101100BBB111110AAAAAA. */ +{ "fdmsub", 0x30360F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fdmsub 0,limm,c 00110110001101100111CCCCCC111110. */ +{ "fdmsub", 0x3636703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fdmsub 0,b,limm 00110bbb001101100BBB111110111110. */ +{ "fdmsub", 0x30360FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fdmsub<.cc> b,b,limm 00110bbb111101100BBB1111100QQQQQ. */ +{ "fdmsub", 0x30F60F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* fdmsub<.cc> 0,limm,c 00110110111101100111CCCCCC0QQQQQ. */ +{ "fdmsub", 0x36F67000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* fdmsub a,limm,u6 00110110011101100111uuuuuuAAAAAA. */ +{ "fdmsub", 0x36767000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdmsub 0,limm,u6 00110110011101100111uuuuuu111110. */ +{ "fdmsub", 0x3676703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdmsub<.cc> 0,limm,u6 00110110111101100111uuuuuu1QQQQQ. */ +{ "fdmsub", 0x36F67020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fdmsub 0,limm,s12 00110110101101100111ssssssSSSSSS. */ +{ "fdmsub", 0x36B67000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* fdmsub a,limm,limm 00110110001101100111111110AAAAAA. */ +{ "fdmsub", 0x36367F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fdmsub 0,limm,limm 00110110001101100111111110111110. */ +{ "fdmsub", 0x36367FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fdmsub<.cc> 0,limm,limm 001101101111011001111111100QQQQQ. */ +{ "fdmsub", 0x36F67F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* fdmul a,b,c 00110bbb001100000BBBCCCCCCAAAAAA. */ +{ "fdmul", 0x30300000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fdmul 0,b,c 00110bbb001100000BBBCCCCCC111110. */ +{ "fdmul", 0x3030003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fdmul<.cc> b,b,c 00110bbb111100000BBBCCCCCC0QQQQQ. */ +{ "fdmul", 0x30F00000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* fdmul a,b,u6 00110bbb011100000BBBuuuuuuAAAAAA. */ +{ "fdmul", 0x30700000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdmul 0,b,u6 00110bbb011100000BBBuuuuuu111110. */ +{ "fdmul", 0x3070003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdmul<.cc> b,b,u6 00110bbb111100000BBBuuuuuu1QQQQQ. */ +{ "fdmul", 0x30F00020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fdmul b,b,s12 00110bbb101100000BBBssssssSSSSSS. */ +{ "fdmul", 0x30B00000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* fdmul a,limm,c 00110110001100000111CCCCCCAAAAAA. */ +{ "fdmul", 0x36307000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fdmul a,b,limm 00110bbb001100000BBB111110AAAAAA. */ +{ "fdmul", 0x30300F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fdmul 0,limm,c 00110110001100000111CCCCCC111110. */ +{ "fdmul", 0x3630703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fdmul 0,b,limm 00110bbb001100000BBB111110111110. */ +{ "fdmul", 0x30300FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fdmul<.cc> b,b,limm 00110bbb111100000BBB1111100QQQQQ. */ +{ "fdmul", 0x30F00F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* fdmul<.cc> 0,limm,c 00110110111100000111CCCCCC0QQQQQ. */ +{ "fdmul", 0x36F07000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* fdmul a,limm,u6 00110110011100000111uuuuuuAAAAAA. */ +{ "fdmul", 0x36707000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdmul 0,limm,u6 00110110011100000111uuuuuu111110. */ +{ "fdmul", 0x3670703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdmul<.cc> 0,limm,u6 00110110111100000111uuuuuu1QQQQQ. */ +{ "fdmul", 0x36F07020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fdmul 0,limm,s12 00110110101100000111ssssssSSSSSS. */ +{ "fdmul", 0x36B07000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* fdmul a,limm,limm 00110110001100000111111110AAAAAA. */ +{ "fdmul", 0x36307F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fdmul 0,limm,limm 00110110001100000111111110111110. */ +{ "fdmul", 0x36307FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fdmul<.cc> 0,limm,limm 001101101111000001111111100QQQQQ. */ +{ "fdmul", 0x36F07F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* fdsqrt b,c 00110bbb001011110BBBCCCCCC000001. */ +{ "fdsqrt", 0x302F0001, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fdsqrt 0,c 00110110001011110111CCCCCC000001. */ +{ "fdsqrt", 0x362F7001, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RC }, { 0 }}, + +/* fdsqrt b,u6 00110bbb011011110BBBuuuuuu000001. */ +{ "fdsqrt", 0x306F0001, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdsqrt 0,u6 00110110011011110111uuuuuu000001. */ +{ "fdsqrt", 0x366F7001, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdsqrt b,limm 00110bbb001011110BBB111110000001. */ +{ "fdsqrt", 0x302F0F81, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fdsqrt 0,limm 00110110001011110111111110000001. */ +{ "fdsqrt", 0x362F7F81, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, + +/* fdsub a,b,c 00110bbb001100100BBBCCCCCCAAAAAA. */ +{ "fdsub", 0x30320000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fdsub 0,b,c 00110bbb001100100BBBCCCCCC111110. */ +{ "fdsub", 0x3032003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fdsub<.cc> b,b,c 00110bbb111100100BBBCCCCCC0QQQQQ. */ +{ "fdsub", 0x30F20000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* fdsub a,b,u6 00110bbb011100100BBBuuuuuuAAAAAA. */ +{ "fdsub", 0x30720000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdsub 0,b,u6 00110bbb011100100BBBuuuuuu111110. */ +{ "fdsub", 0x3072003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdsub<.cc> b,b,u6 00110bbb111100100BBBuuuuuu1QQQQQ. */ +{ "fdsub", 0x30F20020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fdsub b,b,s12 00110bbb101100100BBBssssssSSSSSS. */ +{ "fdsub", 0x30B20000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* fdsub a,limm,c 00110110001100100111CCCCCCAAAAAA. */ +{ "fdsub", 0x36327000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fdsub a,b,limm 00110bbb001100100BBB111110AAAAAA. */ +{ "fdsub", 0x30320F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fdsub 0,limm,c 00110110001100100111CCCCCC111110. */ +{ "fdsub", 0x3632703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fdsub 0,b,limm 00110bbb001100100BBB111110111110. */ +{ "fdsub", 0x30320FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fdsub<.cc> b,b,limm 00110bbb111100100BBB1111100QQQQQ. */ +{ "fdsub", 0x30F20F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* fdsub<.cc> 0,limm,c 00110110111100100111CCCCCC0QQQQQ. */ +{ "fdsub", 0x36F27000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* fdsub a,limm,u6 00110110011100100111uuuuuuAAAAAA. */ +{ "fdsub", 0x36727000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdsub 0,limm,u6 00110110011100100111uuuuuu111110. */ +{ "fdsub", 0x3672703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fdsub<.cc> 0,limm,u6 00110110111100100111uuuuuu1QQQQQ. */ +{ "fdsub", 0x36F27020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fdsub 0,limm,s12 00110110101100100111ssssssSSSSSS. */ +{ "fdsub", 0x36B27000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* fdsub a,limm,limm 00110110001100100111111110AAAAAA. */ +{ "fdsub", 0x36327F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fdsub 0,limm,limm 00110110001100100111111110111110. */ +{ "fdsub", 0x36327FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fdsub<.cc> 0,limm,limm 001101101111001001111111100QQQQQ. */ +{ "fdsub", 0x36F27F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARC_FLOAT, DP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* ffs<.f> b,c 00101bbb00101111FBBBCCCCCC010010. */ +{ "ffs", 0x282F0012, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* ffs<.f> 0,c 0010111000101111F111CCCCCC010010. */ +{ "ffs", 0x2E2F7012, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* ffs<.f> b,u6 00101bbb01101111FBBBuuuuuu010010. */ +{ "ffs", 0x286F0012, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* ffs<.f> 0,u6 0010111001101111F111uuuuuu010010. */ +{ "ffs", 0x2E6F7012, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* ffs<.f> b,limm 00101bbb00101111FBBB111110010010. */ +{ "ffs", 0x282F0F92, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* ffs<.f> 0,limm 0010111000101111F111111110010010. */ +{ "ffs", 0x2E2F7F92, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* flag c 00100RRR001010010RRRCCCCCCRRRRRR. */ +{ "flag", 0x20290000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_RC }, { 0 }}, + +/* flag<.cc> c 00100RRR111010010RRRCCCCCC0QQQQQ. */ +{ "flag", 0x20E90000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_RC }, { C_CC }}, + +/* flag u6 00100RRR011010010RRRuuuuuuRRRRRR. */ +{ "flag", 0x20690000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_UIMM6_20 }, { 0 }}, + +/* flag<.cc> u6 00100RRR111010010RRRuuuuuu1QQQQQ. */ +{ "flag", 0x20E90020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_UIMM6_20 }, { C_CC }}, + +/* flag s12 00100RRR101010010RRRssssssSSSSSS. */ +{ "flag", 0x20A90000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_SIMM12_20 }, { 0 }}, + +/* flag limm 00100RRR001010010RRR111110RRRRRR. */ +{ "flag", 0x20290F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_LIMM }, { 0 }}, + +/* flag<.cc> limm 00100RRR111010010RRR1111100QQQQQ. */ +{ "flag", 0x20E90F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_LIMM }, { C_CC }}, + +/* flagacc c 00101100001011111000CCCCCC111111. */ +{ "flagacc", 0x2C2F803F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RC }, { 0 }}, + +/* flagacc u6 00101100011011111000uuuuuu111111. */ +{ "flagacc", 0x2C6F803F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_UIMM6_20 }, { 0 }}, + +/* fls<.f> b,c 00101bbb00101111FBBBCCCCCC010011. */ +{ "fls", 0x282F0013, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* fls<.f> 0,c 0010111000101111F111CCCCCC010011. */ +{ "fls", 0x2E2F7013, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* fls<.f> b,u6 00101bbb01101111FBBBuuuuuu010011. */ +{ "fls", 0x286F0013, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* fls<.f> 0,u6 0010111001101111F111uuuuuu010011. */ +{ "fls", 0x2E6F7013, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* fls<.f> b,limm 00101bbb00101111FBBB111110010011. */ +{ "fls", 0x282F0F93, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* fls<.f> 0,limm 0010111000101111F111111110010011. */ +{ "fls", 0x2E2F7F93, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* fmul<.f> a,b,c 00110bbb00000000FBBBCCCCCCAAAAAA. */ +{ "fmul", 0x30000000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* fmul<.f> 0,b,c 00110bbb00000000FBBBCCCCCC111110. */ +{ "fmul", 0x3000003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* fmul<.f><.cc> b,b,c 00110bbb11000000FBBBCCCCCC0QQQQQ. */ +{ "fmul", 0x30C00000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* fmul<.f> a,b,u6 00110bbb01000000FBBBuuuuuuAAAAAA. */ +{ "fmul", 0x30400000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* fmul<.f> 0,b,u6 00110bbb01000000FBBBuuuuuu111110. */ +{ "fmul", 0x3040003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* fmul<.f><.cc> b,b,u6 00110bbb11000000FBBBuuuuuu1QQQQQ. */ +{ "fmul", 0x30C00020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* fmul<.f> b,b,s12 00110bbb10000000FBBBssssssSSSSSS. */ +{ "fmul", 0x30800000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* fmul<.f> a,limm,c 0011011000000000F111CCCCCCAAAAAA. */ +{ "fmul", 0x36007000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* fmul<.f> a,b,limm 00110bbb00000000FBBB111110AAAAAA. */ +{ "fmul", 0x30000F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* fmul<.f> 0,limm,c 0011011000000000F111CCCCCC111110. */ +{ "fmul", 0x3600703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* fmul<.f> 0,b,limm 00110bbb00000000FBBB111110111110. */ +{ "fmul", 0x30000FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* fmul<.f><.cc> 0,limm,c 0011011011000000F111CCCCCC0QQQQQ. */ +{ "fmul", 0x36C07000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* fmul<.f><.cc> b,b,limm 00110bbb11000000FBBB1111100QQQQQ. */ +{ "fmul", 0x30C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* fmul<.f> a,limm,u6 0011011001000000F111uuuuuuAAAAAA. */ +{ "fmul", 0x36407000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* fmul<.f> 0,limm,u6 0011011001000000F111uuuuuu111110. */ +{ "fmul", 0x3640703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* fmul<.f><.cc> 0,limm,u6 0011011011000000F111uuuuuu1QQQQQ. */ +{ "fmul", 0x36C07020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* fmul<.f> 0,limm,s12 0011011010000000F111ssssssSSSSSS. */ +{ "fmul", 0x36807000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* fmul<.f> a,limm,limm 0011011000000000F111111110AAAAAA. */ +{ "fmul", 0x36007F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* fmul<.f> 0,limm,limm 0011011000000000F111111110111110. */ +{ "fmul", 0x36007FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* fmul<.f><.cc> 0,limm,limm 0011011011000000F1111111100QQQQQ. */ +{ "fmul", 0x36C07F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* fsadd a,b,c 00110bbb000000010BBBCCCCCCAAAAAA. */ +{ "fsadd", 0x30010000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fsadd 0,b,c 00110bbb000000010BBBCCCCCC111110. */ +{ "fsadd", 0x3001003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fsadd<.cc> b,b,c 00110bbb110000010BBBCCCCCC0QQQQQ. */ +{ "fsadd", 0x30C10000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* fsadd a,b,u6 00110bbb010000010BBBuuuuuuAAAAAA. */ +{ "fsadd", 0x30410000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fsadd 0,b,u6 00110bbb010000010BBBuuuuuu111110. */ +{ "fsadd", 0x3041003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fsadd<.cc> b,b,u6 00110bbb110000010BBBuuuuuu1QQQQQ. */ +{ "fsadd", 0x30C10020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fsadd b,b,s12 00110bbb100000010BBBssssssSSSSSS. */ +{ "fsadd", 0x30810000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* fsadd a,limm,c 00110110000000010111CCCCCCAAAAAA. */ +{ "fsadd", 0x36017000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fsadd a,b,limm 00110bbb000000010BBB111110AAAAAA. */ +{ "fsadd", 0x30010F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fsadd 0,limm,c 00110110000000010111CCCCCC111110. */ +{ "fsadd", 0x3601703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fsadd 0,b,limm 00110bbb000000010BBB111110111110. */ +{ "fsadd", 0x30010FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fsadd<.cc> b,b,limm 00110bbb110000010BBB1111100QQQQQ. */ +{ "fsadd", 0x30C10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* fsadd<.cc> 0,limm,c 00110110110000010111CCCCCC0QQQQQ. */ +{ "fsadd", 0x36C17000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* fsadd a,limm,u6 00110110010000010111uuuuuuAAAAAA. */ +{ "fsadd", 0x36417000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fsadd 0,limm,u6 00110110010000010111uuuuuu111110. */ +{ "fsadd", 0x3641703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fsadd<.cc> 0,limm,u6 00110110110000010111uuuuuu1QQQQQ. */ +{ "fsadd", 0x36C17020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fsadd 0,limm,s12 00110110100000010111ssssssSSSSSS. */ +{ "fsadd", 0x36817000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* fsadd a,limm,limm 00110110000000010111111110AAAAAA. */ +{ "fsadd", 0x36017F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fsadd 0,limm,limm 00110110000000010111111110111110. */ +{ "fsadd", 0x36017FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fsadd<.cc> 0,limm,limm 001101101100000101111111100QQQQQ. */ +{ "fsadd", 0x36C17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* fscmp b,c 00110bbb000000111BBBCCCCCC000000. */ +{ "fscmp", 0x30038000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fscmp<.cc> b,c 00110bbb110000111BBBCCCCCC0QQQQQ. */ +{ "fscmp", 0x30C38000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RC }, { C_CC }}, + +/* fscmp b,u6 00110bbb010000111BBBuuuuuu000000. */ +{ "fscmp", 0x30438000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fscmp<.cc> b,u6 00110bbb110000111BBBuuuuuu1QQQQQ. */ +{ "fscmp", 0x30C38020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fscmp b,s12 00110bbb100000111BBBssssssSSSSSS. */ +{ "fscmp", 0x30838000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, + +/* fscmp limm,c 00110110000000111111CCCCCC000000. */ +{ "fscmp", 0x3603F000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fscmp b,limm 00110bbb000000111BBB111110000000. */ +{ "fscmp", 0x30038F80, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fscmp<.cc> b,limm 00110bbb110000111BBB1111100QQQQQ. */ +{ "fscmp", 0x30C38F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, + +/* fscmp<.cc> limm,c 00110110110000111111CCCCCC0QQQQQ. */ +{ "fscmp", 0x36C3F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* fscmp limm,u6 00110110010000111111uuuuuu000000. */ +{ "fscmp", 0x3643F000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fscmp<.cc> limm,u6 00110110110000111111uuuuuu1QQQQQ. */ +{ "fscmp", 0x36C3F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fscmp limm,s12 00110110100000111111ssssssSSSSSS. */ +{ "fscmp", 0x3683F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* fscmp limm,limm 00110110000000111111111110000000. */ +{ "fscmp", 0x3603FF80, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fscmp<.cc> limm,limm 001101101100001111111111100QQQQQ. */ +{ "fscmp", 0x36C3FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* fscmpf b,c 00110bbb000001001BBBCCCCCC000000. */ +{ "fscmpf", 0x30048000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fscmpf<.cc> b,c 00110bbb110001001BBBCCCCCC0QQQQQ. */ +{ "fscmpf", 0x30C48000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RC }, { C_CC }}, + +/* fscmpf b,u6 00110bbb010001001BBBuuuuuu000000. */ +{ "fscmpf", 0x30448000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fscmpf<.cc> b,u6 00110bbb110001001BBBuuuuuu1QQQQQ. */ +{ "fscmpf", 0x30C48020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fscmpf b,s12 00110bbb100001001BBBssssssSSSSSS. */ +{ "fscmpf", 0x30848000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, + +/* fscmpf limm,c 00110110000001001111CCCCCC000000. */ +{ "fscmpf", 0x3604F000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fscmpf b,limm 00110bbb000001001BBB111110000000. */ +{ "fscmpf", 0x30048F80, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fscmpf<.cc> b,limm 00110bbb110001001BBB1111100QQQQQ. */ +{ "fscmpf", 0x30C48F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, + +/* fscmpf<.cc> limm,c 00110110110001001111CCCCCC0QQQQQ. */ +{ "fscmpf", 0x36C4F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* fscmpf limm,u6 00110110010001001111uuuuuu000000. */ +{ "fscmpf", 0x3644F000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fscmpf<.cc> limm,u6 00110110110001001111uuuuuu1QQQQQ. */ +{ "fscmpf", 0x36C4F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fscmpf limm,s12 00110110100001001111ssssssSSSSSS. */ +{ "fscmpf", 0x3684F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* fscmpf limm,limm 00110110000001001111111110000000. */ +{ "fscmpf", 0x3604FF80, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fscmpf<.cc> limm,limm 001101101100010011111111100QQQQQ. */ +{ "fscmpf", 0x36C4FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* fsdiv a,b,c 00110bbb000001110BBBCCCCCCAAAAAA. */ +{ "fsdiv", 0x30070000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fsdiv 0,b,c 00110bbb000001110BBBCCCCCC111110. */ +{ "fsdiv", 0x3007003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fsdiv<.cc> b,b,c 00110bbb110001110BBBCCCCCC0QQQQQ. */ +{ "fsdiv", 0x30C70000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* fsdiv a,b,u6 00110bbb010001110BBBuuuuuuAAAAAA. */ +{ "fsdiv", 0x30470000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fsdiv 0,b,u6 00110bbb010001110BBBuuuuuu111110. */ +{ "fsdiv", 0x3047003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fsdiv<.cc> b,b,u6 00110bbb110001110BBBuuuuuu1QQQQQ. */ +{ "fsdiv", 0x30C70020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fsdiv b,b,s12 00110bbb100001110BBBssssssSSSSSS. */ +{ "fsdiv", 0x30870000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* fsdiv a,limm,c 00110110000001110111CCCCCCAAAAAA. */ +{ "fsdiv", 0x36077000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fsdiv a,b,limm 00110bbb000001110BBB111110AAAAAA. */ +{ "fsdiv", 0x30070F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fsdiv 0,limm,c 00110110000001110111CCCCCC111110. */ +{ "fsdiv", 0x3607703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fsdiv 0,b,limm 00110bbb000001110BBB111110111110. */ +{ "fsdiv", 0x30070FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fsdiv<.cc> b,b,limm 00110bbb110001110BBB1111100QQQQQ. */ +{ "fsdiv", 0x30C70F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* fsdiv<.cc> 0,limm,c 00110110110001110111CCCCCC0QQQQQ. */ +{ "fsdiv", 0x36C77000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* fsdiv a,limm,u6 00110110010001110111uuuuuuAAAAAA. */ +{ "fsdiv", 0x36477000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fsdiv 0,limm,u6 00110110010001110111uuuuuu111110. */ +{ "fsdiv", 0x3647703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fsdiv<.cc> 0,limm,u6 00110110110001110111uuuuuu1QQQQQ. */ +{ "fsdiv", 0x36C77020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fsdiv 0,limm,s12 00110110100001110111ssssssSSSSSS. */ +{ "fsdiv", 0x36877000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* fsdiv a,limm,limm 00110110000001110111111110AAAAAA. */ +{ "fsdiv", 0x36077F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fsdiv 0,limm,limm 00110110000001110111111110111110. */ +{ "fsdiv", 0x36077FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fsdiv<.cc> 0,limm,limm 001101101100011101111111100QQQQQ. */ +{ "fsdiv", 0x36C77F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* fsmadd a,b,c 00110bbb000001010BBBCCCCCCAAAAAA. */ +{ "fsmadd", 0x30050000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fsmadd 0,b,c 00110bbb000001010BBBCCCCCC111110. */ +{ "fsmadd", 0x3005003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fsmadd<.cc> b,b,c 00110bbb110001010BBBCCCCCC0QQQQQ. */ +{ "fsmadd", 0x30C50000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* fsmadd a,b,u6 00110bbb010001010BBBuuuuuuAAAAAA. */ +{ "fsmadd", 0x30450000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fsmadd 0,b,u6 00110bbb010001010BBBuuuuuu111110. */ +{ "fsmadd", 0x3045003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fsmadd<.cc> b,b,u6 00110bbb110001010BBBuuuuuu1QQQQQ. */ +{ "fsmadd", 0x30C50020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fsmadd b,b,s12 00110bbb100001010BBBssssssSSSSSS. */ +{ "fsmadd", 0x30850000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* fsmadd a,limm,c 00110110000001010111CCCCCCAAAAAA. */ +{ "fsmadd", 0x36057000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fsmadd a,b,limm 00110bbb000001010BBB111110AAAAAA. */ +{ "fsmadd", 0x30050F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fsmadd 0,limm,c 00110110000001010111CCCCCC111110. */ +{ "fsmadd", 0x3605703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fsmadd 0,b,limm 00110bbb000001010BBB111110111110. */ +{ "fsmadd", 0x30050FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fsmadd<.cc> b,b,limm 00110bbb110001010BBB1111100QQQQQ. */ +{ "fsmadd", 0x30C50F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* fsmadd<.cc> 0,limm,c 00110110110001010111CCCCCC0QQQQQ. */ +{ "fsmadd", 0x36C57000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* fsmadd a,limm,u6 00110110010001010111uuuuuuAAAAAA. */ +{ "fsmadd", 0x36457000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fsmadd 0,limm,u6 00110110010001010111uuuuuu111110. */ +{ "fsmadd", 0x3645703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fsmadd<.cc> 0,limm,u6 00110110110001010111uuuuuu1QQQQQ. */ +{ "fsmadd", 0x36C57020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fsmadd 0,limm,s12 00110110100001010111ssssssSSSSSS. */ +{ "fsmadd", 0x36857000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* fsmadd a,limm,limm 00110110000001010111111110AAAAAA. */ +{ "fsmadd", 0x36057F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fsmadd 0,limm,limm 00110110000001010111111110111110. */ +{ "fsmadd", 0x36057FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fsmadd<.cc> 0,limm,limm 001101101100010101111111100QQQQQ. */ +{ "fsmadd", 0x36C57F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* fsmsub a,b,c 00110bbb000001100BBBCCCCCCAAAAAA. */ +{ "fsmsub", 0x30060000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fsmsub 0,b,c 00110bbb000001100BBBCCCCCC111110. */ +{ "fsmsub", 0x3006003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fsmsub<.cc> b,b,c 00110bbb110001100BBBCCCCCC0QQQQQ. */ +{ "fsmsub", 0x30C60000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* fsmsub a,b,u6 00110bbb010001100BBBuuuuuuAAAAAA. */ +{ "fsmsub", 0x30460000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fsmsub 0,b,u6 00110bbb010001100BBBuuuuuu111110. */ +{ "fsmsub", 0x3046003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fsmsub<.cc> b,b,u6 00110bbb110001100BBBuuuuuu1QQQQQ. */ +{ "fsmsub", 0x30C60020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fsmsub b,b,s12 00110bbb100001100BBBssssssSSSSSS. */ +{ "fsmsub", 0x30860000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* fsmsub a,limm,c 00110110000001100111CCCCCCAAAAAA. */ +{ "fsmsub", 0x36067000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fsmsub a,b,limm 00110bbb000001100BBB111110AAAAAA. */ +{ "fsmsub", 0x30060F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fsmsub 0,limm,c 00110110000001100111CCCCCC111110. */ +{ "fsmsub", 0x3606703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fsmsub 0,b,limm 00110bbb000001100BBB111110111110. */ +{ "fsmsub", 0x30060FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fsmsub<.cc> b,b,limm 00110bbb110001100BBB1111100QQQQQ. */ +{ "fsmsub", 0x30C60F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* fsmsub<.cc> 0,limm,c 00110110110001100111CCCCCC0QQQQQ. */ +{ "fsmsub", 0x36C67000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* fsmsub a,limm,u6 00110110010001100111uuuuuuAAAAAA. */ +{ "fsmsub", 0x36467000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fsmsub 0,limm,u6 00110110010001100111uuuuuu111110. */ +{ "fsmsub", 0x3646703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fsmsub<.cc> 0,limm,u6 00110110110001100111uuuuuu1QQQQQ. */ +{ "fsmsub", 0x36C67020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fsmsub 0,limm,s12 00110110100001100111ssssssSSSSSS. */ +{ "fsmsub", 0x36867000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* fsmsub a,limm,limm 00110110000001100111111110AAAAAA. */ +{ "fsmsub", 0x36067F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fsmsub 0,limm,limm 00110110000001100111111110111110. */ +{ "fsmsub", 0x36067FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fsmsub<.cc> 0,limm,limm 001101101100011001111111100QQQQQ. */ +{ "fsmsub", 0x36C67F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* fsmul a,b,c 00110bbb000000000BBBCCCCCCAAAAAA. */ +{ "fsmul", 0x30000000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fsmul 0,b,c 00110bbb000000000BBBCCCCCC111110. */ +{ "fsmul", 0x3000003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fsmul<.cc> b,b,c 00110bbb110000000BBBCCCCCC0QQQQQ. */ +{ "fsmul", 0x30C00000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* fsmul a,b,u6 00110bbb010000000BBBuuuuuuAAAAAA. */ +{ "fsmul", 0x30400000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fsmul 0,b,u6 00110bbb010000000BBBuuuuuu111110. */ +{ "fsmul", 0x3040003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fsmul<.cc> b,b,u6 00110bbb110000000BBBuuuuuu1QQQQQ. */ +{ "fsmul", 0x30C00020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fsmul b,b,s12 00110bbb100000000BBBssssssSSSSSS. */ +{ "fsmul", 0x30800000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* fsmul a,limm,c 00110110000000000111CCCCCCAAAAAA. */ +{ "fsmul", 0x36007000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fsmul a,b,limm 00110bbb000000000BBB111110AAAAAA. */ +{ "fsmul", 0x30000F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fsmul 0,limm,c 00110110000000000111CCCCCC111110. */ +{ "fsmul", 0x3600703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fsmul 0,b,limm 00110bbb000000000BBB111110111110. */ +{ "fsmul", 0x30000FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fsmul<.cc> b,b,limm 00110bbb110000000BBB1111100QQQQQ. */ +{ "fsmul", 0x30C00F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* fsmul<.cc> 0,limm,c 00110110110000000111CCCCCC0QQQQQ. */ +{ "fsmul", 0x36C07000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* fsmul a,limm,u6 00110110010000000111uuuuuuAAAAAA. */ +{ "fsmul", 0x36407000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fsmul 0,limm,u6 00110110010000000111uuuuuu111110. */ +{ "fsmul", 0x3640703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fsmul<.cc> 0,limm,u6 00110110110000000111uuuuuu1QQQQQ. */ +{ "fsmul", 0x36C07020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fsmul 0,limm,s12 00110110100000000111ssssssSSSSSS. */ +{ "fsmul", 0x36807000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* fsmul a,limm,limm 00110110000000000111111110AAAAAA. */ +{ "fsmul", 0x36007F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fsmul 0,limm,limm 00110110000000000111111110111110. */ +{ "fsmul", 0x36007FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fsmul<.cc> 0,limm,limm 001101101100000001111111100QQQQQ. */ +{ "fsmul", 0x36C07F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* fssqrt b,c 00110bbb001011110BBBCCCCCC000000. */ +{ "fssqrt", 0x302F0000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fssqrt 0,c 00110110001011110111CCCCCC000000. */ +{ "fssqrt", 0x362F7000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RC }, { 0 }}, + +/* fssqrt b,u6 00110bbb011011110BBBuuuuuu000000. */ +{ "fssqrt", 0x306F0000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fssqrt 0,u6 00110110011011110111uuuuuu000000. */ +{ "fssqrt", 0x366F7000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, + +/* fssqrt b,limm 00110bbb001011110BBB111110000000. */ +{ "fssqrt", 0x302F0F80, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fssqrt 0,limm 00110110001011110111111110000000. */ +{ "fssqrt", 0x362F7F80, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, + +/* fssub a,b,c 00110bbb000000100BBBCCCCCCAAAAAA. */ +{ "fssub", 0x30020000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fssub 0,b,c 00110bbb000000100BBBCCCCCC111110. */ +{ "fssub", 0x3002003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* fssub<.cc> b,b,c 00110bbb110000100BBBCCCCCC0QQQQQ. */ +{ "fssub", 0x30C20000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* fssub a,b,u6 00110bbb010000100BBBuuuuuuAAAAAA. */ +{ "fssub", 0x30420000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fssub 0,b,u6 00110bbb010000100BBBuuuuuu111110. */ +{ "fssub", 0x3042003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* fssub<.cc> b,b,u6 00110bbb110000100BBBuuuuuu1QQQQQ. */ +{ "fssub", 0x30C20020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fssub b,b,s12 00110bbb100000100BBBssssssSSSSSS. */ +{ "fssub", 0x30820000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* fssub a,limm,c 00110110000000100111CCCCCCAAAAAA. */ +{ "fssub", 0x36027000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fssub a,b,limm 00110bbb000000100BBB111110AAAAAA. */ +{ "fssub", 0x30020F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fssub 0,limm,c 00110110000000100111CCCCCC111110. */ +{ "fssub", 0x3602703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* fssub 0,b,limm 00110bbb000000100BBB111110111110. */ +{ "fssub", 0x30020FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* fssub<.cc> b,b,limm 00110bbb110000100BBB1111100QQQQQ. */ +{ "fssub", 0x30C20F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* fssub<.cc> 0,limm,c 00110110110000100111CCCCCC0QQQQQ. */ +{ "fssub", 0x36C27000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* fssub a,limm,u6 00110110010000100111uuuuuuAAAAAA. */ +{ "fssub", 0x36427000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fssub 0,limm,u6 00110110010000100111uuuuuu111110. */ +{ "fssub", 0x3642703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* fssub<.cc> 0,limm,u6 00110110110000100111uuuuuu1QQQQQ. */ +{ "fssub", 0x36C27020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* fssub 0,limm,s12 00110110100000100111ssssssSSSSSS. */ +{ "fssub", 0x36827000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* fssub a,limm,limm 00110110000000100111111110AAAAAA. */ +{ "fssub", 0x36027F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fssub 0,limm,limm 00110110000000100111111110111110. */ +{ "fssub", 0x36027FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* fssub<.cc> 0,limm,limm 001101101100001001111111100QQQQQ. */ +{ "fssub", 0x36C27F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARC_FLOAT, SP, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* fsub<.f> a,b,c 00110bbb00000010FBBBCCCCCCAAAAAA. */ +{ "fsub", 0x30020000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* fsub<.f> 0,b,c 00110bbb00000010FBBBCCCCCC111110. */ +{ "fsub", 0x3002003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* fsub<.f><.cc> b,b,c 00110bbb11000010FBBBCCCCCC0QQQQQ. */ +{ "fsub", 0x30C20000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* fsub<.f> a,b,u6 00110bbb01000010FBBBuuuuuuAAAAAA. */ +{ "fsub", 0x30420000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* fsub<.f> 0,b,u6 00110bbb01000010FBBBuuuuuu111110. */ +{ "fsub", 0x3042003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* fsub<.f><.cc> b,b,u6 00110bbb11000010FBBBuuuuuu1QQQQQ. */ +{ "fsub", 0x30C20020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* fsub<.f> b,b,s12 00110bbb10000010FBBBssssssSSSSSS. */ +{ "fsub", 0x30820000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* fsub<.f> a,limm,c 0011011000000010F111CCCCCCAAAAAA. */ +{ "fsub", 0x36027000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* fsub<.f> a,b,limm 00110bbb00000010FBBB111110AAAAAA. */ +{ "fsub", 0x30020F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* fsub<.f> 0,limm,c 0011011000000010F111CCCCCC111110. */ +{ "fsub", 0x3602703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* fsub<.f> 0,b,limm 00110bbb00000010FBBB111110111110. */ +{ "fsub", 0x30020FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* fsub<.f><.cc> 0,limm,c 0011011011000010F111CCCCCC0QQQQQ. */ +{ "fsub", 0x36C27000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* fsub<.f><.cc> b,b,limm 00110bbb11000010FBBB1111100QQQQQ. */ +{ "fsub", 0x30C20F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* fsub<.f> a,limm,u6 0011011001000010F111uuuuuuAAAAAA. */ +{ "fsub", 0x36427000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* fsub<.f> 0,limm,u6 0011011001000010F111uuuuuu111110. */ +{ "fsub", 0x3642703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* fsub<.f><.cc> 0,limm,u6 0011011011000010F111uuuuuu1QQQQQ. */ +{ "fsub", 0x36C27020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* fsub<.f> 0,limm,s12 0011011010000010F111ssssssSSSSSS. */ +{ "fsub", 0x36827000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* fsub<.f> a,limm,limm 0011011000000010F111111110AAAAAA. */ +{ "fsub", 0x36027F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* fsub<.f> 0,limm,limm 0011011000000010F111111110111110. */ +{ "fsub", 0x36027FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* fsub<.f><.cc> 0,limm,limm 0011011011000010F1111111100QQQQQ. */ +{ "fsub", 0x36C27F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARC_FLOAT, SPX, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* fxtr<.f> a,b,c 00110bbb00100110FBBBCCCCCCAAAAAA. */ +{ "fxtr", 0x30260000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* fxtr<.f><.cc> b,b,c 00110bbb11100110FBBBCCCCCC0QQQQQ. */ +{ "fxtr", 0x30E60000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* fxtr<.f> a,b,u6 00110bbb01100110FBBBuuuuuuAAAAAA. */ +{ "fxtr", 0x30660000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* fxtr<.f><.cc> b,b,u6 00110bbb11100110FBBBuuuuuu1QQQQQ. */ +{ "fxtr", 0x30E60020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* fxtr<.f> b,b,s12 00110bbb10100110FBBBssssssSSSSSS. */ +{ "fxtr", 0x30A60000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* fxtr<.f> a,limm,c 0011011000100110F111CCCCCCAAAAAA. */ +{ "fxtr", 0x36267000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* fxtr<.f> a,b,limm 00110bbb00100110FBBB111110AAAAAA. */ +{ "fxtr", 0x30260F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* fxtr<.f><.cc> b,b,limm 00110bbb11100110FBBB1111100QQQQQ. */ +{ "fxtr", 0x30E60F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* getacc b,c 00101bbb001011110BBBCCCCCC011000. */ +{ "getacc", 0x282F0018, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, + +/* getacc 0,c 00101110001011110111CCCCCC011000. */ +{ "getacc", 0x2E2F7018, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, + +/* getacc b,u6 00101bbb011011110BBBuuuuuu011000. */ +{ "getacc", 0x286F0018, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, + +/* getacc 0,u6 00101110011011110111uuuuuu011000. */ +{ "getacc", 0x2E6F7018, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, + +/* getacc b,limm 00101bbb001011110BBB111110011000. */ +{ "getacc", 0x282F0F98, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, + +/* getacc 0,limm 00101110001011110111111110011000. */ +{ "getacc", 0x2E2F7F98, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, + +/* iaddr<.f> a,b,c 00110bbb00100111FBBBCCCCCCAAAAAA. */ +{ "iaddr", 0x30270000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* iaddr<.f><.cc> b,b,c 00110bbb11100111FBBBCCCCCC0QQQQQ. */ +{ "iaddr", 0x30E70000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* iaddr<.f> a,b,u6 00110bbb01100111FBBBuuuuuuAAAAAA. */ +{ "iaddr", 0x30670000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* iaddr<.f><.cc> b,b,u6 00110bbb11100111FBBBuuuuuu1QQQQQ. */ +{ "iaddr", 0x30E70020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* iaddr<.f> b,b,s12 00110bbb10100111FBBBssssssSSSSSS. */ +{ "iaddr", 0x30A70000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* iaddr<.f> a,limm,c 0011011000100111F111CCCCCCAAAAAA. */ +{ "iaddr", 0x36277000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* iaddr<.f> a,b,limm 00110bbb00100111FBBB111110AAAAAA. */ +{ "iaddr", 0x30270F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* iaddr<.f><.cc> b,b,limm 00110bbb11100111FBBB1111100QQQQQ. */ +{ "iaddr", 0x30E70F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* j c 00100RRR001000000RRRCCCCCCRRRRRR. */ +{ "j", 0x20200000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, + +/* j OPERAND_BLINK 00100RRR001000000RRR011111RRRRRR. */ +{ "j", 0x202007C0, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { 0 }}, + +/* j.F OPERAND_ILINK1 00100RRR001000001RRR011101RRRRRR. */ +{ "j", 0x20208740, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_ILINK1, OPERAND_BRAKETdup }, { C_FHARD }}, + +/* j.F OPERAND_ILINK2 00100RRR001000001RRR011110RRRRRR. */ +{ "j", 0x20208780, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_ILINK2, OPERAND_BRAKETdup }, { C_FHARD }}, + +/* jcc c 00100RRR111000000RRRCCCCCC0QQQQQ. */ +{ "j", 0x20E00000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }}, + +/* jcc OPERAND_BLINK 00100RRR111000000RRR0111110QQQQQ. */ +{ "j", 0x20E007C0, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_CC }}, + +/* j.Fcc OPERAND_ILINK1 00100RRR111000001RRR0111010QQQQQ. */ +{ "j", 0x20E08740, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_ILINK1, OPERAND_BRAKETdup }, { C_FHARD, C_CC }}, + +/* j.Fcc OPERAND_ILINK2 00100RRR111000001RRR0111100QQQQQ. */ +{ "j", 0x20E08780, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_ILINK2, OPERAND_BRAKETdup }, { C_FHARD, C_CC }}, + +/* j.D c 00100RRR001000010RRRCCCCCCRRRRRR. */ +{ "j", 0x20210000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DHARD }}, + +/* j.D OPERAND_BLINK 00100RRR001000010RRR011111RRRRRR. */ +{ "j", 0x202107C0, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_DHARD }}, + +/* jcc.D c 00100RRR111000010RRRCCCCCC0QQQQQ. */ +{ "j", 0x20E10000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC, C_DHARD }}, + +/* jcc.D OPERAND_BLINK 00100RRR111000010RRR0111110QQQQQ. */ +{ "j", 0x20E107C0, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_CC, C_DHARD }}, + +/* j c 00100RRR00100000RRRRCCCCCCRRRRRR. */ +{ "j", 0x20200000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, + +/* j OPERAND_BLINK 00100RRR00100000RRRR011111RRRRRR. */ +{ "j", 0x202007C0, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { 0 }}, + +/* jcc c 00100RRR11100000RRRRCCCCCC0QQQQQ. */ +{ "j", 0x20E00000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }}, + +/* jcc OPERAND_BLINK 00100RRR11100000RRRR0111110QQQQQ. */ +{ "j", 0x20E007C0, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_CC }}, + +/* j.D c 00100RRR00100001RRRRCCCCCCRRRRRR. */ +{ "j", 0x20210000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DHARD }}, + +/* j.D OPERAND_BLINK 00100RRR00100001RRRR011111RRRRRR. */ +{ "j", 0x202107C0, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_DHARD }}, + +/* jcc.D c 00100RRR11100001RRRRCCCCCC0QQQQQ. */ +{ "j", 0x20E10000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC, C_DHARD }}, + +/* jcc.D OPERAND_BLINK 00100RRR11100001RRRR0111110QQQQQ. */ +{ "j", 0x20E107C0, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK, OPERAND_BRAKETdup }, { C_CC, C_DHARD }}, + +/* j s12 00100RRR101000000RRRssssssSSSSSS. */ +{ "j", 0x20A00000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_SIMM12_20 }, { 0 }}, + +/* j.D s12 00100RRR101000010RRRssssssSSSSSS. */ +{ "j", 0x20A10000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_SIMM12_20 }, { C_DHARD }}, + +/* j s12 00100RRR10100000RRRRssssssSSSSSS. */ +{ "j", 0x20A00000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_SIMM12_20 }, { 0 }}, + +/* j.D s12 00100RRR10100001RRRRssssssSSSSSS. */ +{ "j", 0x20A10000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_SIMM12_20 }, { C_DHARD }}, + +/* j u6 00100RRR011000000RRRuuuuuuRRRRRR. */ +{ "j", 0x20600000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { 0 }}, + +/* jcc u6 00100RRR111000000RRRuuuuuu1QQQQQ. */ +{ "j", 0x20E00020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC }}, + +/* j.D u6 00100RRR011000010RRRuuuuuuRRRRRR. */ +{ "j", 0x20610000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_DHARD }}, + +/* jcc.D u6 00100RRR111000010RRRuuuuuu1QQQQQ. */ +{ "j", 0x20E10020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC, C_DHARD }}, + +/* j u6 00100RRR01100000RRRRuuuuuuRRRRRR. */ +{ "j", 0x20600000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { 0 }}, + +/* jcc u6 00100RRR11100000RRRRuuuuuu1QQQQQ. */ +{ "j", 0x20E00020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC }}, + +/* j.D u6 00100RRR01100001RRRRuuuuuuRRRRRR. */ +{ "j", 0x20610000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_DHARD }}, + +/* jcc.D u6 00100RRR11100001RRRRuuuuuu1QQQQQ. */ +{ "j", 0x20E10020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC, C_DHARD }}, + +/* j limm 00100RRR001000000RRR111110RRRRRR. */ +{ "j", 0x20200F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_LIMM }, { 0 }}, + +/* jcc limm 00100RRR111000000RRR1111100QQQQQ. */ +{ "j", 0x20E00F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_LIMM }, { C_CC }}, + +/* j limm 00100RRR00100000RRRR111110RRRRRR. */ +{ "j", 0x20200F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_LIMM }, { 0 }}, + +/* jcc limm 00100RRR11100000RRRR1111100QQQQQ. */ +{ "j", 0x20E00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_LIMM }, { C_CC }}, + +/* jeq_s OPERAND_BLINK 0111110011100000. */ +{ "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, COND, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { C_CC_EQ }}, + +/* jeq_s OPERAND_BLINK 0111110011100000. */ +{ "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, COND, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { C_CC_EQ }}, + +/* jl c 00100RRR001000100RRRCCCCCCRRRRRR. */ +{ "jl", 0x20220000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, + +/* jlcc c 00100RRR111000100RRRCCCCCC0QQQQQ. */ +{ "jl", 0x20E20000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }}, + +/* jl.D c 00100RRR001000110RRRCCCCCCRRRRRR. */ +{ "jl", 0x20230000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DHARD }}, + +/* jlcc.D c 00100RRR111000110RRRCCCCCC0QQQQQ. */ +{ "jl", 0x20E30000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC, C_DHARD }}, + +/* jl c 00100RRR00100010RRRRCCCCCCRRRRRR. */ +{ "jl", 0x20220000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, + +/* jlcc c 00100RRR11100010RRRRCCCCCC0QQQQQ. */ +{ "jl", 0x20E20000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC }}, + +/* jl.D c 00100RRR00100011RRRRCCCCCCRRRRRR. */ +{ "jl", 0x20230000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DHARD }}, + +/* jlcc.D c 00100RRR11100011RRRRCCCCCC0QQQQQ. */ +{ "jl", 0x20E30000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_CC, C_DHARD }}, + +/* jl s12 00100RRR101000100RRRssssssSSSSSS. */ +{ "jl", 0x20A20000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_SIMM12_20 }, { 0 }}, + +/* jl.D s12 00100RRR101000110RRRssssssSSSSSS. */ +{ "jl", 0x20A30000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_SIMM12_20 }, { C_DHARD }}, + +/* jl s12 00100RRR10100010RRRRssssssSSSSSS. */ +{ "jl", 0x20A20000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_SIMM12_20 }, { 0 }}, + +/* jl.D s12 00100RRR10100011RRRRssssssSSSSSS. */ +{ "jl", 0x20A30000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_SIMM12_20 }, { C_DHARD }}, + +/* jl u6 00100RRR011000100RRRuuuuuuRRRRRR. */ +{ "jl", 0x20620000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { 0 }}, + +/* jlcc u6 00100RRR111000100RRRuuuuuu1QQQQQ. */ +{ "jl", 0x20E20020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC }}, + +/* jl.D u6 00100RRR011000110RRRuuuuuuRRRRRR. */ +{ "jl", 0x20630000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_DHARD }}, + +/* jlcc.D u6 00100RRR111000110RRRuuuuuu1QQQQQ. */ +{ "jl", 0x20E30020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC, C_DHARD }}, + +/* jl u6 00100RRR01100010RRRRuuuuuuRRRRRR. */ +{ "jl", 0x20620000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { 0 }}, + +/* jlcc u6 00100RRR11100010RRRRuuuuuu1QQQQQ. */ +{ "jl", 0x20E20020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC }}, + +/* jl.D u6 00100RRR01100011RRRRuuuuuuRRRRRR. */ +{ "jl", 0x20630000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_DHARD }}, + +/* jlcc.D u6 00100RRR11100011RRRRuuuuuu1QQQQQ. */ +{ "jl", 0x20E30020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_UIMM6_20 }, { C_CC, C_DHARD }}, + +/* jl limm 00100RRR001000100RRR111110RRRRRR. */ +{ "jl", 0x20220F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_LIMM }, { 0 }}, + +/* jlcc limm 00100RRR111000100RRR1111100QQQQQ. */ +{ "jl", 0x20E20F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_LIMM }, { C_CC }}, + +/* jl limm 00100RRR00100010RRRR111110RRRRRR. */ +{ "jl", 0x20220F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_LIMM }, { 0 }}, + +/* jlcc limm 00100RRR11100010RRRR1111100QQQQQ. */ +{ "jl", 0x20E20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_LIMM }, { C_CC }}, + +/* jli_s u10 010110uuuuuuuuuu. */ +{ "jli_s", 0x00005800, 0x0000FC00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JLI, CD1, { OPERAND_UIMM10_6_S }, { 0 }}, +{ "jli_s", 0x00005800, 0x0000FC00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JLI, CD1, { OPERAND_UIMM10_6_S_JLIOFF }, { 0 }}, + +/* jl_s b 01111bbb01000000. */ +{ "jl_s", 0x00007840, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { 0 }}, + +/* jl_s.D b 01111bbb01100000. */ +{ "jl_s", 0x00007860, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { C_DHARD }}, + +/* jl_s b 01111bbb01000000. */ +{ "jl_s", 0x00007840, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { 0 }}, + +/* jl_s.D b 01111bbb01100000. */ +{ "jl_s", 0x00007860, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { C_DHARD }}, + +/* jne_s OPERAND_BLINK 0111110111100000. */ +{ "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, COND, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { C_CC_NE }}, + +/* jne_s OPERAND_BLINK 0111110111100000. */ +{ "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, COND, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { C_CC_NE }}, + +/* j_s b 01111bbb00000000. */ +{ "j_s", 0x00007800, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { 0 }}, + +/* j_s.D b 01111bbb00100000. */ +{ "j_s", 0x00007820, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { C_DHARD }}, + +/* j_s OPERAND_BLINK 0111111011100000. */ +{ "j_s", 0x00007EE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { 0 }}, + +/* j_s.D OPERAND_BLINK 0111111111100000. */ +{ "j_s", 0x00007FE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { C_DHARD }}, + +/* j_s b 01111bbb00000000. */ +{ "j_s", 0x00007800, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { 0 }}, + +/* j_s.D b 01111bbb00100000. */ +{ "j_s", 0x00007820, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_RB_S, OPERAND_BRAKETdup }, { C_DHARD }}, + +/* j_s OPERAND_BLINK 0111111011100000. */ +{ "j_s", 0x00007EE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { 0 }}, + +/* j_s.D OPERAND_BLINK 0111111111100000. */ +{ "j_s", 0x00007FE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { OPERAND_BRAKET, OPERAND_BLINK_S, OPERAND_BRAKETdup }, { C_DHARD }}, + +/* kflag c 00100RRR001010011RRRCCCCCCRRRRRR. */ +{ "kflag", 0x20298000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_RC }, { 0 }}, + +/* kflag<.cc> c 00100RRR111010011RRRCCCCCC0QQQQQ. */ +{ "kflag", 0x20E98000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_RC }, { C_CC }}, + +/* kflag u6 00100RRR011010011RRRuuuuuuRRRRRR. */ +{ "kflag", 0x20698000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_UIMM6_20 }, { 0 }}, + +/* kflag<.cc> u6 00100RRR111010011RRRuuuuuu1QQQQQ. */ +{ "kflag", 0x20E98020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_UIMM6_20 }, { C_CC }}, + +/* kflag s12 00100RRR101010011RRRssssssSSSSSS. */ +{ "kflag", 0x20A98000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_SIMM12_20 }, { 0 }}, + +/* kflag limm 00100RRR001010011RRR111110RRRRRR. */ +{ "kflag", 0x20298F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_LIMM }, { 0 }}, + +/* kflag<.cc> limm 00100RRR111010011RRR1111100QQQQQ. */ +{ "kflag", 0x20E98F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_LIMM }, { C_CC }}, + +/* prefetch<.aa> b,c 00100bbbaa1100000BBBCCCCCC111110. */ +{ "prefetch", 0x2030003E, 0xF83F803F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_AA8 }}, + +/* prefetch b 00010bbb000000000BBB0RR000111110. */ +{ "prefetch", 0x1000003E, 0xF8FF89FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { 0 }}, + +/* prefetch<.aa> b,s9 00010bbbssssssssSBBB0aa000111110. */ +{ "prefetch", 0x1000003E, 0xF80009FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_AA21 }}, + +/* prefetch<.aa> b,limm 00100bbbaa1100000BBB111110111110. */ +{ "prefetch", 0x20300FBE, 0xF83F8FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_AA8 }}, + +/* prefetch<.aa> limm,c 00100110aa1100000111CCCCCC111110. */ +{ "prefetch", 0x2630703E, 0xFF3FF03F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_AA8 }}, + +/* prefetch limm,c 00100110RR1100000111CCCCCC111110. */ +{ "prefetch", 0x2630703E, 0xFF3FF03F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, + +/* prefetch limm 000101100000000001110RR000111110. */ +{ "prefetch", 0x1600703E, 0xFFFFF9FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, + +/* prefetch<.aa> limm,s9 00010110ssssssssS1110aa000111110. */ +{ "prefetch", 0x1600703E, 0xFF0079FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_AA21 }}, + +/* prefetch limm,s9 00010110ssssssssS1110RR000111110. */ +{ "prefetch", 0x1600703E, 0xFF0079FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { 0 }}, + +/* prefetch<.aa> limm,limm 00100110aa1100000111111110111110. */ +{ "prefetch", 0x26307FBE, 0xFF3FFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_AA8 }}, + +/* prealloc<.aa> b,c 00100bbbaa1100010BBBCCCCCC111110. */ +{ "prealloc", 0x2031003E, 0xF83F803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_AA8 }}, + +/* prealloc<.aa> b,s9 00010bbbssssssssSBBB0aa001111110. */ +{ "prealloc", 0x1000007E, 0xF80009FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_AA21 }}, + +/* prealloc<.aa> b,limm 00100bbbaa1100010BBB111110111110. */ +{ "prealloc", 0x20310FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_AA8 }}, + +/* prealloc limm,c 00100110RR1100010111CCCCCC111110. */ +{ "prealloc", 0x2631703E, 0xFF3FF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, + +/* prealloc limm 000101100000000001110RR001111110. */ +{ "prealloc", 0x1600707E, 0xFFFFF9FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, + +/* prealloc limm,s9 00010110ssssssssS1110RR001111110. */ +{ "prealloc", 0x1600707E, 0xFF0079FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { 0 }}, + +/* prefetchl2<.aa> b,c 00100bbbaa1100100BBBCCCCCC111110. */ +{ "prefetchl2", 0x2032003E, 0xF83F803F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_RC }, { C_AA8 }}, + +/* prefetchl2 b 00010bbb000000000BBB0RR000111110. */ +{ "prefetchl2", 0x1000003E, 0xF8FF89FF, 0, MEMORY, NONE, { OPERAND_RB }, { 0 }}, + +/* prefetchl2<.aa> b,s9 00010bbbssssssssSBBB0aa010111110. */ +{ "prefetchl2", 0x100000BE, 0xF80009FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_SIMM9_8 }, { C_AA21 }}, + +/* prefetchl2<.aa> b,limm 00100bbbaa1100100BBB111110111110. */ +{ "prefetchl2", 0x20320FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_AA8 }}, + +/* prefetchl2<.aa> limm,c 00100110aa1100000111CCCCCC111110. */ +{ "prefetchl2", 0x2630703E, 0xFF3FF03F, 0, MEMORY, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_AA8 }}, + +/* prefetchl2 limm,c 00100110RR1100100111CCCCCC111110. */ +{ "prefetchl2", 0x2632703E, 0xFF3FF03F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* prefetchl2 limm 000101100000000001110RR010111110. */ +{ "prefetchl2", 0x160070BE, 0xFFFFF9FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_LIMM }, { 0 }}, + +/* prefetchl2<.aa> limm,s9 00010110ssssssssS1110aa000111110. */ +{ "prefetchl2", 0x1600703E, 0xFF0079FF, 0, MEMORY, NONE, { OPERAND_LIMM, OPERAND_SIMM9_8 }, { C_AA21 }}, + +/* prefetchl2 limm,s9 00010110ssssssssS1110RR010111110. */ +{ "prefetchl2", 0x160070BE, 0xFF0079FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_LIMM, OPERAND_SIMM9_8 }, { 0 }}, + +/* prefetchl2<.aa> limm,limm 00100110aa1100000111111110111110. */ +{ "prefetchl2", 0x26307FBE, 0xFF3FFFFF, 0, MEMORY, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_AA8 }}, + +/* prefetchw<.aa> b,c 00100bbbaa1100001BBBCCCCCC111110. */ +{ "prefetchw", 0x2030803E, 0xF83F803F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_AA8 }}, + +/* prefetchw<.aa> b,s9 00010bbbssssssssSBBB1aa000111110. */ +{ "prefetchw", 0x1000083E, 0xF80009FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_AA21 }}, + +/* prefetchw<.aa> b,limm 00100bbbaa1100001BBB111110111110. */ +{ "prefetchw", 0x20308FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_AA8 }}, + +/* prefetchw limm,c 00100110RR1100001111CCCCCC111110. */ +{ "prefetchw", 0x2630F03E, 0xFF3FF03F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, + +/* prefetchw limm 000101100000000001111RR000111110. */ +{ "prefetchw", 0x1600783E, 0xFFFFF9FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, + +/* prefetchw limm,s9 00010110ssssssssS1111RR000111110. */ +{ "prefetchw", 0x1600783E, 0xFF0079FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { 0 }}, + +/* ld<.di><.aa><.x> a,b 00010bbb000000000BBBDaaZZXAAAAAA. */ +{ "ld", 0x10000000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }}, + +/* ld<.di><.aa><.x> a,b,c 00100bbbaa110ZZXDBBBCCCCCCAAAAAA. */ +{ "ld", 0x20300000, 0xF8380000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, + +/* ld<.di><.aa><.x> 0,b 00010bbb000000000BBBDaaZZX111110. */ +{ "ld", 0x1000003E, 0xF8FF803F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }}, + +/* ld<.di><.aa><.x> 0,b,c 00100bbbaa110ZZXDBBBCCCCCC111110. */ +{ "ld", 0x2030003E, 0xF838003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, + +/* ld<.di><.aa><.x> a,b,s9 00010bbbssssssssSBBBDaaZZXAAAAAA. */ +{ "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }}, + +/* ld<.di><.aa><.x> 0,b,s9 00010bbbssssssssSBBBDaaZZX111110. */ +{ "ld", 0x1000003E, 0xF800003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }}, + +/* ld<.di><.x> a,limm 00010110000000000111DRRZZXAAAAAA. */ +{ "ld", 0x16007000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_X25 }}, + +/* ld<.di><.aa><.x> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */ +{ "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, + +/* ld<.di><.aa><.x> a,limm,c 00100110aa110ZZXD111CCCCCCAAAAAA. */ +{ "ld", 0x26307000, 0xFF387000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, + +/* ld<.di><.x> a,limm,c 00100110RR110ZZXD111CCCCCCAAAAAA. */ +{ "ld", 0x26307000, 0xFF387000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_X15 }}, + +/* ld<.di><.x> 0,limm 00010110000000000111DRRZZX111110. */ +{ "ld", 0x1600703E, 0xFFFFF03F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_X25 }}, + +/* ld<.di><.aa><.x> 0,b,limm 00100bbbaa110ZZXDBBB111110111110. */ +{ "ld", 0x20300FBE, 0xF8380FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, + +/* ld<.di><.aa><.x> 0,limm,c 00100110aa110ZZXD111CCCCCC111110. */ +{ "ld", 0x2630703E, 0xFF38703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, + +/* ld<.di><.x> 0,limm,c 00100110RR110ZZXD111CCCCCC111110. */ +{ "ld", 0x2630703E, 0xFF38703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_X15 }}, + +/* ld<.di><.aa><.x> a,limm,s9 00010110ssssssssS111DaaZZXAAAAAA. */ +{ "ld", 0x16007000, 0xFF007000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }}, + +/* ld<.di><.aa><.x> 0,limm,s9 00010110ssssssssS111DaaZZX111110. */ +{ "ld", 0x1600703E, 0xFF00703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }}, + +/* ld<.di><.aa><.x> a,limm,limm 00100110aa110ZZXD111111110AAAAAA. */ +{ "ld", 0x26307F80, 0xFF387FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, + +/* ld<.di><.aa><.x> 0,limm,limm 00100110aa110ZZXD111111110111110. */ +{ "ld", 0x26307FBE, 0xFF387FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, + +/* ldb_s a,b,c 01100bbbccc01aaa. */ +{ "ldb_s", 0x00006008, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_RC_S, OPERAND_BRAKETdup }, { C_ZZ_B }}, + +/* ldb_s c,b,u5 10001bbbcccuuuuu. */ +{ "ldb_s", 0x00008800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM5_11_S, OPERAND_BRAKETdup }, { C_ZZ_B }}, + +/* ldb_s b,SP,u7 11000bbb001uuuuu. */ +{ "ldb_s", 0x0000C020, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { C_ZZ_B }}, + +/* ldb_s OPERAND_R0,GP,s9 1100101sssssssss. */ +{ "ldb_s", 0x0000CA00, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM9_7_S, OPERAND_BRAKETdup }, { C_ZZ_B }}, + +/* ldd<.di><.aa> a,b 00010bbb000000000BBBDaa110AAAAAA. */ +{ "ldd", 0x10000180, 0xF8FF81C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }}, + +/* ldd<.di><.aa> a,b,c 00100bbbaa110110DBBBCCCCCCAAAAAA. */ +{ "ldd", 0x20360000, 0xF83F0000, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }}, + +/* ldd<.di><.aa> 0,b 00010bbb000000000BBBDaa110111110. */ +{ "ldd", 0x100001BE, 0xF8FF81FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }}, + +/* ldd<.di><.aa> 0,b,c 00100bbbaa110110DBBBCCCCCC111110. */ +{ "ldd", 0x2036003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }}, + +/* ldd<.di><.aa> a,b,s9 00010bbbssssssssSBBBDaa110AAAAAA. */ +{ "ldd", 0x10000180, 0xF80001C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }}, + +/* ldd<.di><.aa> 0,b,s9 00010bbbssssssssSBBBDaa110111110. */ +{ "ldd", 0x100001BE, 0xF80001FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }}, + +/* ldd<.di> a,limm 00010110000000000111DRR110AAAAAA. */ +{ "ldd", 0x16007180, 0xFFFFF1C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI20, C_ZZ_D }}, + +/* ldd<.di><.aa> a,b,limm 00100bbbaa110110DBBB111110AAAAAA. */ +{ "ldd", 0x20360F80, 0xF83F0FC0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }}, + +/* ldd<.di> a,limm,c 00100110RR110110D111CCCCCCAAAAAA. */ +{ "ldd", 0x26367000, 0xFF3F7000, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16, C_ZZ_D }}, + +/* ldd<.di> 0,limm 00010110000000000111DRR110111110. */ +{ "ldd", 0x160071BE, 0xFFFFF1FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI20, C_ZZ_D }}, + +/* ldd<.di><.aa> 0,b,limm 00100bbbaa110110DBBB111110111110. */ +{ "ldd", 0x20360FBE, 0xF83F0FFF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RB, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }}, + +/* ldd<.di> 0,limm,c 00100110RR110110D111CCCCCC111110. */ +{ "ldd", 0x2636703E, 0xFF3F703F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16, C_ZZ_D }}, + +/* ldd<.di><.aa> a,limm,s9 00010110ssssssssS111Daa110AAAAAA. */ +{ "ldd", 0x16007180, 0xFF0071C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RAD, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }}, + +/* ldd<.di><.aa> 0,limm,s9 00010110ssssssssS111Daa110111110. */ +{ "ldd", 0x160071BE, 0xFF0071FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }}, + +/* ldh_s a,b,c 01100bbbccc10aaa. */ +{ "ldh_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_RC_S, OPERAND_BRAKETdup }, { C_ZZ_H }}, + +/* ldh_s c,b,u6 10010bbbcccuuuuu. */ +{ "ldh_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_ZZ_H }}, + +/* ldh_s.X c,b,u6 10011bbbcccuuuuu. */ +{ "ldh_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_XHARD, C_ZZ_H }}, + +/* ldh_s OPERAND_R0,GP,s10 1100110sssssssss. */ +{ "ldh_s", 0x0000CC00, 0x0000FE00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM10_A16_7_Sbis, OPERAND_BRAKETdup }, { C_ZZ_H }}, + +/* ldi b,c 00100bbb00100110RBBBCCCCCCRRRRRR. */ +{ "ldi", 0x20260000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, + +/* ldi 0,c 0010011000100110R111CCCCCCRRRRRR. */ +{ "ldi", 0x26267000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, + +/* ldi b,u6 00100bbb01100110RBBBuuuuuu000000. */ +{ "ldi", 0x20660000, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, + +/* ldi 0,u6 0010011001100110R111uuuuuu000000. */ +{ "ldi", 0x26667000, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, + +/* ldi<.cc> b,u6 00100bbb11100110RBBBuuuuuu1QQQQQ. */ +{ "ldi", 0x20E60020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, LOAD, CD2, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_CC }}, + +/* ldi<.cc> 0,u6 0010011011100110R111uuuuuu1QQQQQ. */ +{ "ldi", 0x26E67020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, LOAD, CD2, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_CC }}, + +/* ldi b,s12 00100bbb10100110RBBBssssssSSSSSS. */ +{ "ldi", 0x20A60000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, + +/* ldi 0,s12 0010011010100110R111ssssssSSSSSS. */ +{ "ldi", 0x26A67000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, + +/* ldi b,limm 00100bbb00100110RBBB111110RRRRRR. */ +{ "ldi", 0x20260F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, + +/* ldi 0,limm 0010011000100110R111111110RRRRRR. */ +{ "ldi", 0x26267F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, + +/* ldi_s b,u7 01010bbbUUUU1uuu. */ +{ "ldi_s", 0x00005008, 0x0000F808, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_UIMM7_13_S, OPERAND_BRAKETdup }, { 0 }}, + +/* ldm a,u6,b 00101bbb01001100RBBBRuuuuuAAAAAA. */ +{ "ldm", 0x284C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_UIMM6_A16_21, OPERAND_RB }, { 0 }}, + +/* ldm 0,u6,b 00101bbb01001100RBBBRuuuuu111110. */ +{ "ldm", 0x284C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_UIMM6_A16_21, OPERAND_RB }, { 0 }}, + +/* ldm a,u6,limm 0010111001001100R111RuuuuuAAAAAA. */ +{ "ldm", 0x2E4C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_CHK, OPERAND_UIMM6_A16_21, OPERAND_LIMM }, { 0 }}, + +/* ldm 0,u6,limm 0010111001001100R111Ruuuuu111110. */ +{ "ldm", 0x2E4C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_ZA, OPERAND_UIMM6_A16_21, OPERAND_LIMM }, { 0 }}, + +/* ldw_s a,b,c 01100bbbccc10aaa. */ +{ "ldw_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, NONE, { OPERAND_RA_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_RC_S, OPERAND_BRAKETdup }, { C_ZZ_H }}, + +/* ldw_s c,b,u6 10010bbbcccuuuuu. */ +{ "ldw_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_ZZ_H }}, + +/* ldw_s.X c,b,u6 10011bbbcccuuuuu. */ +{ "ldw_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_XHARD, C_ZZ_H }}, + +/* ldw_s OPERAND_R0,GP,s10 1100110sssssssss. */ +{ "ldw_s", 0x0000CC00, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOAD, NONE, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM10_A16_7_Sbis, OPERAND_BRAKETdup }, { C_ZZ_H }}, + +/* ld_s a,b,c 01100bbbccc00aaa. */ +{ "ld_s", 0x00006000, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RA_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_RC_S, OPERAND_BRAKETdup }, { 0 }}, + +/* ld_s.AS a,b,c 01001bbbccc00aaa. */ +{ "ld_s", 0x00004800, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_RA_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_RC_S, OPERAND_BRAKETdup }, { C_AS }}, + +/* ld_s OPERAND_R0,h,u5 01000U00hhhuu1HH. */ +{ "ld_s", 0x00004004, 0x0000FB04, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_RH_S, OPERAND_UIMM5_A32_11_S, OPERAND_BRAKETdup }, { 0 }}, + +/* ld_s OPERAND_R1,h,u5 01000U01hhhuu1HH. */ +{ "ld_s", 0x00004104, 0x0000FB04, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_R1_S, OPERAND_BRAKET, OPERAND_RH_S, OPERAND_UIMM5_A32_11_S, OPERAND_BRAKETdup }, { 0 }}, + +/* ld_s OPERAND_R2,h,u5 01000U10hhhuu1HH. */ +{ "ld_s", 0x00004204, 0x0000FB04, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_R2_S, OPERAND_BRAKET, OPERAND_RH_S, OPERAND_UIMM5_A32_11_S, OPERAND_BRAKETdup }, { 0 }}, + +/* ld_s OPERAND_R3,h,u5 01000U11hhhuu1HH. */ +{ "ld_s", 0x00004304, 0x0000FB04, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_R3_S, OPERAND_BRAKET, OPERAND_RH_S, OPERAND_UIMM5_A32_11_S, OPERAND_BRAKETdup }, { 0 }}, + +/* ld_s b,SP,u7 11000bbb000uuuuu. */ +{ "ld_s", 0x0000C000, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { 0 }}, + +/* ld_s c,b,u7 10000bbbcccuuuuu. */ +{ "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { 0 }}, + +/* ld_s b,PCL,u10 11010bbbuuuuuuuu. */ +{ "ld_s", 0x0000D000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_PCL_S, OPERAND_UIMM10_A32_8_S, OPERAND_BRAKETdup }, { 0 }}, + +/* ld_s OPERAND_R0,GP,s11 1100100sssssssss. */ +{ "ld_s", 0x0000C800, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM11_A32_7_S, OPERAND_BRAKETdup }, { 0 }}, + +/* ld_s OPERAND_R1,GP,s11 01010SSSSSS00sss. */ +{ "ld_s", 0x00005000, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, CD2, { OPERAND_R1_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM11_A32_13_S, OPERAND_BRAKETdup }, { 0 }}, + +/* leave_s u7 11000UUU110uuuu0. */ +{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LEAVE, CD1, { OPERAND_UIMM7_11_S }, { 0 }}, + +/* llock<.di> b,c 00100bbb00101111DBBBCCCCCC010000. */ +{ "llock", 0x202F0010, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* llock<.di> 0,c 0010011000101111D111CCCCCC010000. */ +{ "llock", 0x262F7010, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* llock<.di> b,u6 00100bbb01101111DBBBuuuuuu010000. */ +{ "llock", 0x206F0010, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* llock<.di> 0,u6 0010011001101111D111uuuuuu010000. */ +{ "llock", 0x266F7010, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* llock<.di> b,limm 00100bbb00101111DBBB111110010000. */ +{ "llock", 0x202F0F90, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* llock<.di> 0,limm 0010011000101111D111111110010000. */ +{ "llock", 0x262F7F90, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* llockd<.di> b,c 00100bbb00101111DBBBCCCCCC010010. */ +{ "llockd", 0x202F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* llockd<.di> 0,c 0010011000101111D111CCCCCC010010. */ +{ "llockd", 0x262F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* llockd<.di> b,u6 00100bbb01101111DBBBuuuuuu010010. */ +{ "llockd", 0x206F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* llockd<.di> 0,u6 0010011001101111D111uuuuuu010010. */ +{ "llockd", 0x266F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* llockd<.di> b,limm 00100bbb00101111DBBB111110010010. */ +{ "llockd", 0x202F0F92, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* llockd<.di> 0,limm 0010011000101111D111111110010010. */ +{ "llockd", 0x262F7F92, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* lp s13 00100RRR101010000RRRssssssSSSSSS. */ +{ "lp", 0x20A80000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOOP, NONE, { OPERAND_SIMM13_A16_20 }, { 0 }}, + +/* lp s13 00100RRR10101000RRRRssssssSSSSSS. */ +{ "lp", 0x20A80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOOP, NONE, { OPERAND_SIMM13_A16_20 }, { 0 }}, + +/* lp u7 00100RRR111010000RRRuuuuuu1QQQQQ. */ +{ "lp", 0x20E80020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, LOOP, NONE, { OPERAND_UIMM7_A16_20 }, { C_CC }}, + +/* lp u7 00100RRR011010000RRRuuuuuuRRRRRR. */ +{ "lp", 0x20680000, 0xF8FF8000, ARC_OPCODE_ARC600, LOOP, NONE, { OPERAND_UIMM7_A16_20 }, { 0 }}, + +/* lp u7 00100RRR11101000RRRRuuuuuu1QQQQQ. */ +{ "lp", 0x20E80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOOP, NONE, { OPERAND_UIMM7_A16_20 }, { C_CC }}, + +/* lp u7 00100RRR01101000RRRRuuuuuuRRRRRR. */ +{ "lp", 0x20680000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOOP, NONE, { OPERAND_UIMM7_A16_20 }, { 0 }}, + +/* lr b,c 00100bbb001010100BBBCCCCCCRRRRRR. */ +{ "lr", 0x202A0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, + +/* lr 0,c 00100110001010100111CCCCCCRRRRRR. */ +{ "lr", 0x262A7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, + +/* lr b,c 00100bbb00101010RBBBCCCCCCRRRRRR. */ +{ "lr", 0x202A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, + +/* lr 0,c 0010011000101010R111CCCCCCRRRRRR. */ +{ "lr", 0x262A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, + +/* lr b,u6 00100bbb011010100BBBuuuuuu000000. */ +{ "lr", 0x206A0000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, + +/* lr 0,u6 00100110011010100111uuuuuu000000. */ +{ "lr", 0x266A7000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, + +/* lr b,u6 00100bbb01101010RBBBuuuuuu000000. */ +{ "lr", 0x206A0000, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, + +/* lr 0,u6 0010011001101010R111uuuuuu000000. */ +{ "lr", 0x266A7000, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, + +/* lr b,s12 00100bbb101010100BBBssssssSSSSSS. */ +{ "lr", 0x20AA0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, + +/* lr 0,s12 00100110101010100111ssssssSSSSSS. */ +{ "lr", 0x26AA7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, + +/* lr b,s12 00100bbb10101010RBBBssssssSSSSSS. */ +{ "lr", 0x20AA0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, + +/* lr 0,s12 0010011010101010R111ssssssSSSSSS. */ +{ "lr", 0x26AA7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, + +/* lr b,limm 00100bbb001010100BBB111110RRRRRR. */ +{ "lr", 0x202A0F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, + +/* lr 0,limm 00100110001010100111111110RRRRRR. */ +{ "lr", 0x262A7F80, 0xFFFFFFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, + +/* lr b,limm 00100bbb00101010RBBB111110RRRRRR. */ +{ "lr", 0x202A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB_CHK, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, + +/* lr 0,limm 0010011000101010R111111110RRRRRR. */ +{ "lr", 0x262A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_ZA, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, + +/* lsl16<.f> b,c 00101bbb00101111FBBBCCCCCC001010. */ +{ "lsl16", 0x282F000A, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* lsl16<.f> 0,c 0010111000101111F111CCCCCC001010. */ +{ "lsl16", 0x2E2F700A, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* lsl16<.f> b,u6 00101bbb01101111FBBBuuuuuu001010. */ +{ "lsl16", 0x286F000A, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* lsl16<.f> 0,u6 0010111001101111F111uuuuuu001010. */ +{ "lsl16", 0x2E6F700A, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* lsl16<.f> b,limm 00101bbb00101111FBBB111110001010. */ +{ "lsl16", 0x282F0F8A, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* lsl16<.f> 0,limm 0010111000101111F111111110001010. */ +{ "lsl16", 0x2E2F7F8A, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* lsl8<.f> b,c 00101bbb00101111FBBBCCCCCC001111. */ +{ "lsl8", 0x282F000F, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* lsl8<.f> 0,c 0010111000101111F111CCCCCC001111. */ +{ "lsl8", 0x2E2F700F, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* lsl8<.f> b,u6 00101bbb01101111FBBBuuuuuu001111. */ +{ "lsl8", 0x286F000F, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* lsl8<.f> 0,u6 0010111001101111F111uuuuuu001111. */ +{ "lsl8", 0x2E6F700F, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* lsl8<.f> b,limm 00101bbb00101111FBBB111110001111. */ +{ "lsl8", 0x282F0F8F, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* lsl8<.f> 0,limm 0010111000101111F111111110001111. */ +{ "lsl8", 0x2E2F7F8F, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* lsr<.f> b,c 00100bbb00101111FBBBCCCCCC000010. */ +{ "lsr", 0x202F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* lsr<.f> 0,c 0010011000101111F111CCCCCC000010. */ +{ "lsr", 0x262F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* lsr<.f> a,b,c 00101bbb00000001FBBBCCCCCCAAAAAA. */ +{ "lsr", 0x28010000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* lsr<.f> 0,b,c 00101bbb00000001FBBBCCCCCC111110. */ +{ "lsr", 0x2801003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* lsr<.f><.cc> b,b,c 00101bbb11000001FBBBCCCCCC0QQQQQ. */ +{ "lsr", 0x28C10000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* lsr<.f> b,u6 00100bbb01101111FBBBuuuuuu000010. */ +{ "lsr", 0x206F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* lsr<.f> 0,u6 0010011001101111F111uuuuuu000010. */ +{ "lsr", 0x266F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* lsr<.f> a,b,u6 00101bbb01000001FBBBuuuuuuAAAAAA. */ +{ "lsr", 0x28410000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* lsr<.f> 0,b,u6 00101bbb01000001FBBBuuuuuu111110. */ +{ "lsr", 0x2841003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* lsr<.f><.cc> b,b,u6 00101bbb11000001FBBBuuuuuu1QQQQQ. */ +{ "lsr", 0x28C10020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* lsr<.f> b,b,s12 00101bbb10000001FBBBssssssSSSSSS. */ +{ "lsr", 0x28810000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* lsr<.f> b,limm 00100bbb00101111FBBB111110000010. */ +{ "lsr", 0x202F0F82, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* lsr<.f> 0,limm 0010011000101111F111111110000010. */ +{ "lsr", 0x262F7F82, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* lsr<.f> a,limm,c 0010111000000001F111CCCCCCAAAAAA. */ +{ "lsr", 0x2E017000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* lsr<.f> a,b,limm 00101bbb00000001FBBB111110AAAAAA. */ +{ "lsr", 0x28010F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* lsr<.f> 0,limm,c 0010111000000001F111CCCCCC111110. */ +{ "lsr", 0x2E01703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* lsr<.f> 0,b,limm 00101bbb00000001FBBB111110111110. */ +{ "lsr", 0x28010FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* lsr<.f><.cc> b,b,limm 00101bbb11000001FBBB1111100QQQQQ. */ +{ "lsr", 0x28C10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* lsr<.f><.cc> 0,limm,c 0010111011000001F111CCCCCC0QQQQQ. */ +{ "lsr", 0x2EC17000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* lsr<.f> a,limm,u6 0010111001000001F111uuuuuuAAAAAA. */ +{ "lsr", 0x2E417000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* lsr<.f> 0,limm,u6 0010111001000001F111uuuuuu111110. */ +{ "lsr", 0x2E41703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* lsr<.f><.cc> 0,limm,u6 0010111011000001F111uuuuuu1QQQQQ. */ +{ "lsr", 0x2EC17020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* lsr<.f> 0,limm,s12 0010111010000001F111ssssssSSSSSS. */ +{ "lsr", 0x2E817000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* lsr<.f> a,limm,limm 0010111000000001F111111110AAAAAA. */ +{ "lsr", 0x2E017F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* lsr<.f> 0,limm,limm 0010111000000001F111111110111110. */ +{ "lsr", 0x2E017FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* lsr<.f><.cc> 0,limm,limm 0010111011000001F1111111100QQQQQ. */ +{ "lsr", 0x2EC17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* lsr16<.f> b,c 00101bbb00101111FBBBCCCCCC001011. */ +{ "lsr16", 0x282F000B, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* lsr16<.f> 0,c 0010111000101111F111CCCCCC001011. */ +{ "lsr16", 0x2E2F700B, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* lsr16<.f> b,u6 00101bbb01101111FBBBuuuuuu001011. */ +{ "lsr16", 0x286F000B, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* lsr16<.f> 0,u6 0010111001101111F111uuuuuu001011. */ +{ "lsr16", 0x2E6F700B, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* lsr16<.f> b,limm 00101bbb00101111FBBB111110001011. */ +{ "lsr16", 0x282F0F8B, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* lsr16<.f> 0,limm 0010111000101111F111111110001011. */ +{ "lsr16", 0x2E2F7F8B, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* lsr8<.f> b,c 00101bbb00101111FBBBCCCCCC001110. */ +{ "lsr8", 0x282F000E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* lsr8<.f> 0,c 0010111000101111F111CCCCCC001110. */ +{ "lsr8", 0x2E2F700E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* lsr8<.f> b,u6 00101bbb01101111FBBBuuuuuu001110. */ +{ "lsr8", 0x286F000E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* lsr8<.f> 0,u6 0010111001101111F111uuuuuu001110. */ +{ "lsr8", 0x2E6F700E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* lsr8<.f> b,limm 00101bbb00101111FBBB111110001110. */ +{ "lsr8", 0x282F0F8E, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* lsr8<.f> 0,limm 0010111000101111F111111110001110. */ +{ "lsr8", 0x2E2F7F8E, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* lsrdw<.f> a,b,c 00101bbb00100011FBBBCCCCCCAAAAAA. */ +{ "lsrdw", 0x28230000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* lsrdw<.f> 0,b,c 00101bbb00100011FBBBCCCCCC111110. */ +{ "lsrdw", 0x2823003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* lsrdw<.f><.cc> b,b,c 00101bbb11100011FBBBCCCCCC0QQQQQ. */ +{ "lsrdw", 0x28E30000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* lsrdw<.f> a,b,u6 00101bbb01100011FBBBuuuuuuAAAAAA. */ +{ "lsrdw", 0x28630000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* lsrdw<.f> 0,b,u6 00101bbb01100011FBBBuuuuuu111110. */ +{ "lsrdw", 0x2863003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* lsrdw<.f><.cc> b,b,u6 00101bbb11100011FBBBuuuuuu1QQQQQ. */ +{ "lsrdw", 0x28E30020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* lsrdw<.f> b,b,s12 00101bbb10100011FBBBssssssSSSSSS. */ +{ "lsrdw", 0x28A30000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* lsrdw<.f> a,limm,c 0010111000100011F111CCCCCCAAAAAA. */ +{ "lsrdw", 0x2E237000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* lsrdw<.f> a,b,limm 00101bbb00100011FBBB111110AAAAAA. */ +{ "lsrdw", 0x28230F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* lsrdw<.f> 0,limm,c 0010111000100011F111CCCCCC111110. */ +{ "lsrdw", 0x2E23703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* lsrdw<.f> 0,b,limm 00101bbb00100011FBBB111110111110. */ +{ "lsrdw", 0x28230FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* lsrdw<.f><.cc> 0,limm,c 0010111011100011F111CCCCCC0QQQQQ. */ +{ "lsrdw", 0x2EE37000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* lsrdw<.f><.cc> b,b,limm 00101bbb11100011FBBB1111100QQQQQ. */ +{ "lsrdw", 0x28E30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* lsrdw<.f> a,limm,u6 0010111001100011F111uuuuuuAAAAAA. */ +{ "lsrdw", 0x2E637000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* lsrdw<.f> 0,limm,u6 0010111001100011F111uuuuuu111110. */ +{ "lsrdw", 0x2E63703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* lsrdw<.f><.cc> 0,limm,u6 0010111011100011F111uuuuuu1QQQQQ. */ +{ "lsrdw", 0x2EE37020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* lsrdw<.f> 0,limm,s12 0010111010100011F111ssssssSSSSSS. */ +{ "lsrdw", 0x2EA37000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* lsrdw<.f> a,limm,limm 0010111000100011F111111110AAAAAA. */ +{ "lsrdw", 0x2E237F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* lsrdw<.f> 0,limm,limm 0010111000100011F111111110111110. */ +{ "lsrdw", 0x2E237FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* lsrdw<.f><.cc> 0,limm,limm 0010111011100011F1111111100QQQQQ. */ +{ "lsrdw", 0x2EE37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* lsr_s b,c 01111bbbccc11101. */ +{ "lsr_s", 0x0000781D, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, + +/* lsr_s b,b,c 01111bbbccc11001. */ +{ "lsr_s", 0x00007819, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, + +/* lsr_s b,b,u5 10111bbb001uuuuu. */ +{ "lsr_s", 0x0000B820, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }}, + +/* mac<.f> a,b,c 00101bbb00001110FBBBCCCCCCAAAAAA. */ +{ "mac", 0x280E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mac<.f> 0,b,c 00101bbb00001110FBBBCCCCCC111110. */ +{ "mac", 0x280E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mac<.f><.cc> b,b,c 00101bbb11001110FBBBCCCCCC0QQQQQ. */ +{ "mac", 0x28CE0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mac<.f> a,b,u6 00101bbb01001110FBBBuuuuuuAAAAAA. */ +{ "mac", 0x284E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mac<.f> 0,b,u6 00101bbb01001110FBBBuuuuuu111110. */ +{ "mac", 0x284E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mac<.f><.cc> b,b,u6 00101bbb11001110FBBBuuuuuu1QQQQQ. */ +{ "mac", 0x28CE0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mac<.f> b,b,s12 00101bbb10001110FBBBssssssSSSSSS. */ +{ "mac", 0x288E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mac<.f> a,limm,c 0010111000001110F111CCCCCCAAAAAA. */ +{ "mac", 0x2E0E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mac<.f> a,b,limm 00101bbb00001110FBBB111110AAAAAA. */ +{ "mac", 0x280E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mac<.f> 0,limm,c 0010111000001110F111CCCCCC111110. */ +{ "mac", 0x2E0E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mac<.f> 0,b,limm 00101bbb00001110FBBB111110111110. */ +{ "mac", 0x280E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mac<.f><.cc> b,b,limm 00101bbb11001110FBBB1111100QQQQQ. */ +{ "mac", 0x28CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mac<.f><.cc> 0,limm,c 0010111011001110F111CCCCCC0QQQQQ. */ +{ "mac", 0x2ECE7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mac<.f> a,limm,u6 0010111001001110F111uuuuuuAAAAAA. */ +{ "mac", 0x2E4E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mac<.f> 0,limm,u6 0010111001001110F111uuuuuu111110. */ +{ "mac", 0x2E4E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mac<.f><.cc> 0,limm,u6 0010111011001110F111uuuuuu1QQQQQ. */ +{ "mac", 0x2ECE7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mac<.f> 0,limm,s12 0010111010001110F111ssssssSSSSSS. */ +{ "mac", 0x2E8E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mac<.f> a,limm,limm 0010111000001110F111111110AAAAAA. */ +{ "mac", 0x2E0E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mac<.f> 0,limm,limm 0010111000001110F111111110111110. */ +{ "mac", 0x2E0E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mac<.f><.cc> 0,limm,limm 0010111011001110F1111111100QQQQQ. */ +{ "mac", 0x2ECE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* macd<.f> a,b,c 00101bbb00011010FBBBCCCCCCAAAAAA. */ +{ "macd", 0x281A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macd<.f> 0,b,c 00101bbb00011010FBBBCCCCCC111110. */ +{ "macd", 0x281A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macd<.f><.cc> b,b,c 00101bbb11011010FBBBCCCCCC0QQQQQ. */ +{ "macd", 0x28DA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* macd<.f> a,b,u6 00101bbb01011010FBBBuuuuuuAAAAAA. */ +{ "macd", 0x285A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macd<.f> 0,b,u6 00101bbb01011010FBBBuuuuuu111110. */ +{ "macd", 0x285A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macd<.f><.cc> b,b,u6 00101bbb11011010FBBBuuuuuu1QQQQQ. */ +{ "macd", 0x28DA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macd<.f> b,b,s12 00101bbb10011010FBBBssssssSSSSSS. */ +{ "macd", 0x289A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* macd<.f> a,limm,c 0010111000011010F111CCCCCCAAAAAA. */ +{ "macd", 0x2E1A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macd<.f> a,b,limm 00101bbb00011010FBBB111110AAAAAA. */ +{ "macd", 0x281A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macd<.f> 0,limm,c 0010111000011010F111CCCCCC111110. */ +{ "macd", 0x2E1A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macd<.f> 0,b,limm 00101bbb00011010FBBB111110111110. */ +{ "macd", 0x281A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macd<.f><.cc> b,b,limm 00101bbb11011010FBBB1111100QQQQQ. */ +{ "macd", 0x28DA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* macd<.f><.cc> 0,limm,c 0010111011011010F111CCCCCC0QQQQQ. */ +{ "macd", 0x2EDA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* macd<.f> a,limm,u6 0010111001011010F111uuuuuuAAAAAA. */ +{ "macd", 0x2E5A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macd<.f> 0,limm,u6 0010111001011010F111uuuuuu111110. */ +{ "macd", 0x2E5A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macd<.f><.cc> 0,limm,u6 0010111011011010F111uuuuuu1QQQQQ. */ +{ "macd", 0x2EDA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macd<.f> 0,limm,s12 0010111010011010F111ssssssSSSSSS. */ +{ "macd", 0x2E9A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* macd<.f> a,limm,limm 0010111000011010F111111110AAAAAA. */ +{ "macd", 0x2E1A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macd<.f> 0,limm,limm 0010111000011010F111111110111110. */ +{ "macd", 0x2E1A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macd<.f><.cc> 0,limm,limm 0010111011011010F1111111100QQQQQ. */ +{ "macd", 0x2EDA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* macdf<.f> a,b,c 00110bbb00010011FBBBCCCCCCAAAAAA. */ +{ "macdf", 0x30130000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macdf<.f> 0,b,c 00110bbb00010011FBBBCCCCCC111110. */ +{ "macdf", 0x3013003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macdf<.f><.cc> b,b,c 00110bbb11010011FBBBCCCCCC0QQQQQ. */ +{ "macdf", 0x30D30000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* macdf<.f> a,b,u6 00110bbb01010011FBBBuuuuuuAAAAAA. */ +{ "macdf", 0x30530000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macdf<.f> 0,b,u6 00110bbb01010011FBBBuuuuuu111110. */ +{ "macdf", 0x3053003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macdf<.f><.cc> b,b,u6 00110bbb11010011FBBBuuuuuu1QQQQQ. */ +{ "macdf", 0x30D30020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macdf<.f> b,b,s12 00110bbb10010011FBBBssssssSSSSSS. */ +{ "macdf", 0x30930000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* macdf<.f> a,limm,c 0011011000010011F111CCCCCCAAAAAA. */ +{ "macdf", 0x36137000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macdf<.f> a,b,limm 00110bbb00010011FBBB111110AAAAAA. */ +{ "macdf", 0x30130F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macdf<.f> 0,limm,c 0011011000010011F111CCCCCC111110. */ +{ "macdf", 0x3613703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macdf<.f> 0,b,limm 00110bbb00010011FBBB111110111110. */ +{ "macdf", 0x30130FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macdf<.f><.cc> b,b,limm 00110bbb11010011FBBB1111100QQQQQ. */ +{ "macdf", 0x30D30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* macdf<.f><.cc> 0,limm,c 0011011011010011F111CCCCCC0QQQQQ. */ +{ "macdf", 0x36D37000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* macdf<.f> a,limm,u6 0011011001010011F111uuuuuuAAAAAA. */ +{ "macdf", 0x36537000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macdf<.f> 0,limm,u6 0011011001010011F111uuuuuu111110. */ +{ "macdf", 0x3653703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macdf<.f><.cc> 0,limm,u6 0011011011010011F111uuuuuu1QQQQQ. */ +{ "macdf", 0x36D37020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macdf<.f> 0,limm,s12 0011011010010011F111ssssssSSSSSS. */ +{ "macdf", 0x36937000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* macdf<.f> a,limm,limm 0011011000010011F111111110AAAAAA. */ +{ "macdf", 0x36137F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macdf<.f> 0,limm,limm 0011011000010011F111111110111110. */ +{ "macdf", 0x36137FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macdf<.f><.cc> 0,limm,limm 0011011011010011F1111111100QQQQQ. */ +{ "macdf", 0x36D37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* macdu<.f> a,b,c 00101bbb00011011FBBBCCCCCCAAAAAA. */ +{ "macdu", 0x281B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macdu<.f> 0,b,c 00101bbb00011011FBBBCCCCCC111110. */ +{ "macdu", 0x281B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macdu<.f><.cc> b,b,c 00101bbb11011011FBBBCCCCCC0QQQQQ. */ +{ "macdu", 0x28DB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* macdu<.f> a,b,u6 00101bbb01011011FBBBuuuuuuAAAAAA. */ +{ "macdu", 0x285B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macdu<.f> 0,b,u6 00101bbb01011011FBBBuuuuuu111110. */ +{ "macdu", 0x285B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macdu<.f><.cc> b,b,u6 00101bbb11011011FBBBuuuuuu1QQQQQ. */ +{ "macdu", 0x28DB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macdu<.f> b,b,s12 00101bbb10011011FBBBssssssSSSSSS. */ +{ "macdu", 0x289B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* macdu<.f> a,limm,c 0010111000011011F111CCCCCCAAAAAA. */ +{ "macdu", 0x2E1B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macdu<.f> a,b,limm 00101bbb00011011FBBB111110AAAAAA. */ +{ "macdu", 0x281B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macdu<.f> 0,limm,c 0010111000011011F111CCCCCC111110. */ +{ "macdu", 0x2E1B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macdu<.f> 0,b,limm 00101bbb00011011FBBB111110111110. */ +{ "macdu", 0x281B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macdu<.f><.cc> b,b,limm 00101bbb11011011FBBB1111100QQQQQ. */ +{ "macdu", 0x28DB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* macdu<.f><.cc> 0,limm,c 0010111011011011F111CCCCCC0QQQQQ. */ +{ "macdu", 0x2EDB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* macdu<.f> a,limm,u6 0010111001011011F111uuuuuuAAAAAA. */ +{ "macdu", 0x2E5B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macdu<.f> 0,limm,u6 0010111001011011F111uuuuuu111110. */ +{ "macdu", 0x2E5B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macdu<.f><.cc> 0,limm,u6 0010111011011011F111uuuuuu1QQQQQ. */ +{ "macdu", 0x2EDB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macdu<.f> 0,limm,s12 0010111010011011F111ssssssSSSSSS. */ +{ "macdu", 0x2E9B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* macdu<.f> a,limm,limm 0010111000011011F111111110AAAAAA. */ +{ "macdu", 0x2E1B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macdu<.f> 0,limm,limm 0010111000011011F111111110111110. */ +{ "macdu", 0x2E1B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macdu<.f><.cc> 0,limm,limm 0010111011011011F1111111100QQQQQ. */ +{ "macdu", 0x2EDB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* macdw<.f> a,b,c 00101bbb00010000FBBBCCCCCCAAAAAA. */ +{ "macdw", 0x28100000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macdw<.f> 0,b,c 00101bbb00010000FBBBCCCCCC111110. */ +{ "macdw", 0x2810003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macdw<.f><.cc> b,b,c 00101bbb11010000FBBBCCCCCC0QQQQQ. */ +{ "macdw", 0x28D00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* macdw<.f> a,b,u6 00101bbb01010000FBBBuuuuuuAAAAAA. */ +{ "macdw", 0x28500000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macdw<.f> 0,b,u6 00101bbb01010000FBBBuuuuuu111110. */ +{ "macdw", 0x2850003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macdw<.f><.cc> b,b,u6 00101bbb11010000FBBBuuuuuu1QQQQQ. */ +{ "macdw", 0x28D00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macdw<.f> b,b,s12 00101bbb10010000FBBBssssssSSSSSS. */ +{ "macdw", 0x28900000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* macdw<.f> a,limm,c 0010111000010000F111CCCCCCAAAAAA. */ +{ "macdw", 0x2E107000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macdw<.f> a,b,limm 00101bbb00010000FBBB111110AAAAAA. */ +{ "macdw", 0x28100F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macdw<.f> 0,limm,c 0010111000010000F111CCCCCC111110. */ +{ "macdw", 0x2E10703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macdw<.f> 0,b,limm 00101bbb00010000FBBB111110111110. */ +{ "macdw", 0x28100FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macdw<.f><.cc> 0,limm,c 0010111011010000F111CCCCCC0QQQQQ. */ +{ "macdw", 0x2ED07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* macdw<.f><.cc> b,b,limm 00101bbb11010000FBBB1111100QQQQQ. */ +{ "macdw", 0x28D00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* macdw<.f> a,limm,u6 0010111001010000F111uuuuuuAAAAAA. */ +{ "macdw", 0x2E507000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macdw<.f> 0,limm,u6 0010111001010000F111uuuuuu111110. */ +{ "macdw", 0x2E50703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macdw<.f><.cc> 0,limm,u6 0010111011010000F111uuuuuu1QQQQQ. */ +{ "macdw", 0x2ED07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macdw<.f> 0,limm,s12 0010111010010000F111ssssssSSSSSS. */ +{ "macdw", 0x2E907000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* macdw<.f> a,limm,limm 0010111000010000F111111110AAAAAA. */ +{ "macdw", 0x2E107F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macdw<.f> 0,limm,limm 0010111000010000F111111110111110. */ +{ "macdw", 0x2E107FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macdw<.f><.cc> 0,limm,limm 0010111011010000F1111111100QQQQQ. */ +{ "macdw", 0x2ED07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* macf<.f> a,b,c 00110bbb00001100FBBBCCCCCCAAAAAA. */ +{ "macf", 0x300C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macf<.f> 0,b,c 00110bbb00001100FBBBCCCCCC111110. */ +{ "macf", 0x300C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macf<.f><.cc> b,b,c 00110bbb11001100FBBBCCCCCC0QQQQQ. */ +{ "macf", 0x30CC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* macf<.f> a,b,u6 00110bbb01001100FBBBuuuuuuAAAAAA. */ +{ "macf", 0x304C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macf<.f> 0,b,u6 00110bbb01001100FBBBuuuuuu111110. */ +{ "macf", 0x304C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macf<.f><.cc> b,b,u6 00110bbb11001100FBBBuuuuuu1QQQQQ. */ +{ "macf", 0x30CC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macf<.f> b,b,s12 00110bbb10001100FBBBssssssSSSSSS. */ +{ "macf", 0x308C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* macf<.f> a,limm,c 0011011000001100F111CCCCCCAAAAAA. */ +{ "macf", 0x360C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macf<.f> a,b,limm 00110bbb00001100FBBB111110AAAAAA. */ +{ "macf", 0x300C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macf<.f> 0,limm,c 0011011000001100F111CCCCCC111110. */ +{ "macf", 0x360C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macf<.f> 0,b,limm 00110bbb00001100FBBB111110111110. */ +{ "macf", 0x300C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macf<.f><.cc> 0,limm,c 00110bbb11001100FBBB1111100QQQQQ. */ +{ "macf", 0x30CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* macf<.f><.cc> b,b,limm 0011011011001100F111CCCCCC0QQQQQ. */ +{ "macf", 0x36CC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* macf<.f> a,limm,u6 0011011001001100F111uuuuuuAAAAAA. */ +{ "macf", 0x364C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macf<.f> 0,limm,u6 0011011001001100F111uuuuuu111110. */ +{ "macf", 0x364C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macf<.f><.cc> 0,limm,u6 0011011011001100F111uuuuuu1QQQQQ. */ +{ "macf", 0x36CC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macf<.f> 0,limm,s12 0011011010001100F111ssssssSSSSSS. */ +{ "macf", 0x368C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* macf<.f> a,limm,limm 0011011000001100F111111110AAAAAA. */ +{ "macf", 0x360C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macf<.f> 0,limm,limm 0011011000001100F111111110111110. */ +{ "macf", 0x360C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macf<.f><.cc> 0,limm,limm 0011011011001100F1111111100QQQQQ. */ +{ "macf", 0x36CC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* macflw<.f> a,b,c 00101bbb00110100FBBBCCCCCCAAAAAA. */ +{ "macflw", 0x28340000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macflw<.f> 0,b,c 00101bbb00110100FBBBCCCCCC111110. */ +{ "macflw", 0x2834003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macflw<.f><.cc> b,b,c 00101bbb11110100FBBBCCCCCC0QQQQQ. */ +{ "macflw", 0x28F40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* macflw<.f> a,b,u6 00101bbb01110100FBBBuuuuuuAAAAAA. */ +{ "macflw", 0x28740000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macflw<.f> 0,b,u6 00101bbb01110100FBBBuuuuuu111110. */ +{ "macflw", 0x2874003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macflw<.f><.cc> b,b,u6 00101bbb11110100FBBBuuuuuu1QQQQQ. */ +{ "macflw", 0x28F40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macflw<.f> b,b,s12 00101bbb10110100FBBBssssssSSSSSS. */ +{ "macflw", 0x28B40000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* macflw<.f> a,limm,c 0010111000110100F111CCCCCCAAAAAA. */ +{ "macflw", 0x2E347000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macflw<.f> a,b,limm 00101bbb00110100FBBB111110AAAAAA. */ +{ "macflw", 0x28340F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macflw<.f> 0,limm,c 0010111000110100F111CCCCCC111110. */ +{ "macflw", 0x2E34703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macflw<.f> 0,b,limm 00101bbb00110100FBBB111110111110. */ +{ "macflw", 0x28340FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macflw<.f><.cc> 0,limm,c 0010111011110100F111CCCCCC0QQQQQ. */ +{ "macflw", 0x2EF47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* macflw<.f><.cc> b,b,limm 00101bbb11110100FBBB1111100QQQQQ. */ +{ "macflw", 0x28F40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* macflw<.f> a,limm,u6 0010111001110100F111uuuuuuAAAAAA. */ +{ "macflw", 0x2E747000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macflw<.f> 0,limm,u6 0010111001110100F111uuuuuu111110. */ +{ "macflw", 0x2E74703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macflw<.f><.cc> 0,limm,u6 0010111011110100F111uuuuuu1QQQQQ. */ +{ "macflw", 0x2EF47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macflw<.f> 0,limm,s12 0010111010110100F111ssssssSSSSSS. */ +{ "macflw", 0x2EB47000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* macflw<.f> a,limm,limm 0010111000110100F111111110AAAAAA. */ +{ "macflw", 0x2E347F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macflw<.f> 0,limm,limm 0010111000110100F111111110111110. */ +{ "macflw", 0x2E347FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macflw<.f><.cc> 0,limm,limm 0010111011110100F1111111100QQQQQ. */ +{ "macflw", 0x2EF47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* macfr<.f> a,b,c 00110bbb00001101FBBBCCCCCCAAAAAA. */ +{ "macfr", 0x300D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macfr<.f> 0,b,c 00110bbb00001101FBBBCCCCCC111110. */ +{ "macfr", 0x300D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macfr<.f><.cc> b,b,c 00110bbb11001101FBBBCCCCCC0QQQQQ. */ +{ "macfr", 0x30CD0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* macfr<.f> a,b,u6 00110bbb01001101FBBBuuuuuuAAAAAA. */ +{ "macfr", 0x304D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macfr<.f> 0,b,u6 00110bbb01001101FBBBuuuuuu111110. */ +{ "macfr", 0x304D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macfr<.f><.cc> b,b,u6 00110bbb11001101FBBBuuuuuu1QQQQQ. */ +{ "macfr", 0x30CD0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macfr<.f> b,b,s12 00110bbb10001101FBBBssssssSSSSSS. */ +{ "macfr", 0x308D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* macfr<.f> a,limm,c 0011011000001101F111CCCCCCAAAAAA. */ +{ "macfr", 0x360D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macfr<.f> a,b,limm 00110bbb00001101FBBB111110AAAAAA. */ +{ "macfr", 0x300D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macfr<.f> 0,limm,c 0011011000001101F111CCCCCC111110. */ +{ "macfr", 0x360D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macfr<.f> 0,b,limm 00110bbb00001101FBBB111110111110. */ +{ "macfr", 0x300D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macfr<.f><.cc> 0,limm,c 00110bbb11001101FBBB1111100QQQQQ. */ +{ "macfr", 0x30CD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* macfr<.f><.cc> b,b,limm 0011011011001101F111CCCCCC0QQQQQ. */ +{ "macfr", 0x36CD7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* macfr<.f> a,limm,u6 0011011001001101F111uuuuuuAAAAAA. */ +{ "macfr", 0x364D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macfr<.f> 0,limm,u6 0011011001001101F111uuuuuu111110. */ +{ "macfr", 0x364D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macfr<.f><.cc> 0,limm,u6 0011011011001101F111uuuuuu1QQQQQ. */ +{ "macfr", 0x36CD7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macfr<.f> 0,limm,s12 0011011010001101F111ssssssSSSSSS. */ +{ "macfr", 0x368D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* macfr<.f> a,limm,limm 0011011000001101F111111110AAAAAA. */ +{ "macfr", 0x360D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macfr<.f> 0,limm,limm 0011011000001101F111111110111110. */ +{ "macfr", 0x360D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macfr<.f><.cc> 0,limm,limm 0011011011001101F1111111100QQQQQ. */ +{ "macfr", 0x36CD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* machflw<.f> a,b,c 00101bbb00110111FBBBCCCCCCAAAAAA. */ +{ "machflw", 0x28370000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* machflw<.f> 0,b,c 00101bbb00110111FBBBCCCCCC111110. */ +{ "machflw", 0x2837003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* machflw<.f><.cc> b,b,c 00101bbb11110111FBBBCCCCCC0QQQQQ. */ +{ "machflw", 0x28F70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* machflw<.f> a,b,u6 00101bbb01110111FBBBuuuuuuAAAAAA. */ +{ "machflw", 0x28770000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* machflw<.f> 0,b,u6 00101bbb01110111FBBBuuuuuu111110. */ +{ "machflw", 0x2877003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* machflw<.f><.cc> b,b,u6 00101bbb11110111FBBBuuuuuu1QQQQQ. */ +{ "machflw", 0x28F70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* machflw<.f> b,b,s12 00101bbb10110111FBBBssssssSSSSSS. */ +{ "machflw", 0x28B70000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* machflw<.f> a,limm,c 0010111000110111F111CCCCCCAAAAAA. */ +{ "machflw", 0x2E377000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* machflw<.f> a,b,limm 00101bbb00110111FBBB111110AAAAAA. */ +{ "machflw", 0x28370F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* machflw<.f> 0,limm,c 0010111000110111F111CCCCCC111110. */ +{ "machflw", 0x2E37703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* machflw<.f> 0,b,limm 00101bbb00110111FBBB111110111110. */ +{ "machflw", 0x28370FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* machflw<.f><.cc> 0,limm,c 0010111011110111F111CCCCCC0QQQQQ. */ +{ "machflw", 0x2EF77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* machflw<.f><.cc> b,b,limm 00101bbb11110111FBBB1111100QQQQQ. */ +{ "machflw", 0x28F70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* machflw<.f> a,limm,u6 0010111001110111F111uuuuuuAAAAAA. */ +{ "machflw", 0x2E777000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* machflw<.f> 0,limm,u6 0010111001110111F111uuuuuu111110. */ +{ "machflw", 0x2E77703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* machflw<.f><.cc> 0,limm,u6 0010111011110111F111uuuuuu1QQQQQ. */ +{ "machflw", 0x2EF77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* machflw<.f> 0,limm,s12 0010111010110111F111ssssssSSSSSS. */ +{ "machflw", 0x2EB77000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* machflw<.f> a,limm,limm 0010111000110111F111111110AAAAAA. */ +{ "machflw", 0x2E377F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* machflw<.f> 0,limm,limm 0010111000110111F111111110111110. */ +{ "machflw", 0x2E377FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* machflw<.f><.cc> 0,limm,limm 0010111011110111F1111111100QQQQQ. */ +{ "machflw", 0x2EF77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* machlw<.f> a,b,c 00101bbb00110110FBBBCCCCCCAAAAAA. */ +{ "machlw", 0x28360000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* machlw<.f> 0,b,c 00101bbb00110110FBBBCCCCCC111110. */ +{ "machlw", 0x2836003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* machlw<.f><.cc> b,b,c 00101bbb11110110FBBBCCCCCC0QQQQQ. */ +{ "machlw", 0x28F60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* machlw<.f> a,b,u6 00101bbb01110110FBBBuuuuuuAAAAAA. */ +{ "machlw", 0x28760000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* machlw<.f> 0,b,u6 00101bbb01110110FBBBuuuuuu111110. */ +{ "machlw", 0x2876003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* machlw<.f><.cc> b,b,u6 00101bbb11110110FBBBuuuuuu1QQQQQ. */ +{ "machlw", 0x28F60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* machlw<.f> b,b,s12 00101bbb10110110FBBBssssssSSSSSS. */ +{ "machlw", 0x28B60000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* machlw<.f> a,limm,c 0010111000110110F111CCCCCCAAAAAA. */ +{ "machlw", 0x2E367000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* machlw<.f> a,b,limm 00101bbb00110110FBBB111110AAAAAA. */ +{ "machlw", 0x28360F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* machlw<.f> 0,limm,c 0010111000110110F111CCCCCC111110. */ +{ "machlw", 0x2E36703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* machlw<.f> 0,b,limm 00101bbb00110110FBBB111110111110. */ +{ "machlw", 0x28360FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* machlw<.f><.cc> 0,limm,c 0010111011110110F111CCCCCC0QQQQQ. */ +{ "machlw", 0x2EF67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* machlw<.f><.cc> b,b,limm 00101bbb11110110FBBB1111100QQQQQ. */ +{ "machlw", 0x28F60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* machlw<.f> a,limm,u6 0010111001110110F111uuuuuuAAAAAA. */ +{ "machlw", 0x2E767000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* machlw<.f> 0,limm,u6 0010111001110110F111uuuuuu111110. */ +{ "machlw", 0x2E76703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* machlw<.f><.cc> 0,limm,u6 0010111011110110F111uuuuuu1QQQQQ. */ +{ "machlw", 0x2EF67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* machlw<.f> 0,limm,s12 0010111010110110F111ssssssSSSSSS. */ +{ "machlw", 0x2EB67000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* machlw<.f> a,limm,limm 0010111000110110F111111110AAAAAA. */ +{ "machlw", 0x2E367F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* machlw<.f> 0,limm,limm 0010111000110110F111111110111110. */ +{ "machlw", 0x2E367FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* machlw<.f><.cc> 0,limm,limm 0010111011110110F1111111100QQQQQ. */ +{ "machlw", 0x2EF67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* machulw<.f> a,b,c 00101bbb00110101FBBBCCCCCCAAAAAA. */ +{ "machulw", 0x28350000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* machulw<.f> 0,b,c 00101bbb00110101FBBBCCCCCC111110. */ +{ "machulw", 0x2835003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* machulw<.f><.cc> b,b,c 00101bbb11110101FBBBCCCCCC0QQQQQ. */ +{ "machulw", 0x28F50000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* machulw<.f> a,b,u6 00101bbb01110101FBBBuuuuuuAAAAAA. */ +{ "machulw", 0x28750000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* machulw<.f> 0,b,u6 00101bbb01110101FBBBuuuuuu111110. */ +{ "machulw", 0x2875003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* machulw<.f><.cc> b,b,u6 00101bbb11110101FBBBuuuuuu1QQQQQ. */ +{ "machulw", 0x28F50020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* machulw<.f> b,b,s12 00101bbb10110101FBBBssssssSSSSSS. */ +{ "machulw", 0x28B50000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* machulw<.f> a,limm,c 0010111000110101F111CCCCCCAAAAAA. */ +{ "machulw", 0x2E357000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* machulw<.f> a,b,limm 00101bbb00110101FBBB111110AAAAAA. */ +{ "machulw", 0x28350F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* machulw<.f> 0,limm,c 0010111000110101F111CCCCCC111110. */ +{ "machulw", 0x2E35703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* machulw<.f> 0,b,limm 00101bbb00110101FBBB111110111110. */ +{ "machulw", 0x28350FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* machulw<.f><.cc> 0,limm,c 0010111011110101F111CCCCCC0QQQQQ. */ +{ "machulw", 0x2EF57000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* machulw<.f><.cc> b,b,limm 00101bbb11110101FBBB1111100QQQQQ. */ +{ "machulw", 0x28F50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* machulw<.f> a,limm,u6 0010111001110101F111uuuuuuAAAAAA. */ +{ "machulw", 0x2E757000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* machulw<.f> 0,limm,u6 0010111001110101F111uuuuuu111110. */ +{ "machulw", 0x2E75703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* machulw<.f><.cc> 0,limm,u6 0010111011110101F111uuuuuu1QQQQQ. */ +{ "machulw", 0x2EF57020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* machulw<.f> 0,limm,s12 0010111010110101F111ssssssSSSSSS. */ +{ "machulw", 0x2EB57000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* machulw<.f> a,limm,limm 0010111000110101F111111110AAAAAA. */ +{ "machulw", 0x2E357F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* machulw<.f> 0,limm,limm 0010111000110101F111111110111110. */ +{ "machulw", 0x2E357FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* machulw<.f><.cc> 0,limm,limm 0010111011110101F1111111100QQQQQ. */ +{ "machulw", 0x2EF57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* maclw<.f> a,b,c 00101bbb00110011FBBBCCCCCCAAAAAA. */ +{ "maclw", 0x28330000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* maclw<.f> 0,b,c 00101bbb00110011FBBBCCCCCC111110. */ +{ "maclw", 0x2833003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* maclw<.f><.cc> b,b,c 00101bbb11110011FBBBCCCCCC0QQQQQ. */ +{ "maclw", 0x28F30000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* maclw<.f> a,b,u6 00101bbb01110011FBBBuuuuuuAAAAAA. */ +{ "maclw", 0x28730000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* maclw<.f> 0,b,u6 00101bbb01110011FBBBuuuuuu111110. */ +{ "maclw", 0x2873003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* maclw<.f><.cc> b,b,u6 00101bbb11110011FBBBuuuuuu1QQQQQ. */ +{ "maclw", 0x28F30020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* maclw<.f> b,b,s12 00101bbb10110011FBBBssssssSSSSSS. */ +{ "maclw", 0x28B30000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* maclw<.f> a,limm,c 0010111000110011F111CCCCCCAAAAAA. */ +{ "maclw", 0x2E337000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* maclw<.f> a,b,limm 00101bbb00110011FBBB111110AAAAAA. */ +{ "maclw", 0x28330F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* maclw<.f> 0,limm,c 0010111000110011F111CCCCCC111110. */ +{ "maclw", 0x2E33703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* maclw<.f> 0,b,limm 00101bbb00110011FBBB111110111110. */ +{ "maclw", 0x28330FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* maclw<.f><.cc> 0,limm,c 0010111011110011F111CCCCCC0QQQQQ. */ +{ "maclw", 0x2EF37000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* maclw<.f><.cc> b,b,limm 00101bbb11110011FBBB1111100QQQQQ. */ +{ "maclw", 0x28F30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* maclw<.f> a,limm,u6 0010111001110011F111uuuuuuAAAAAA. */ +{ "maclw", 0x2E737000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* maclw<.f> 0,limm,u6 0010111001110011F111uuuuuu111110. */ +{ "maclw", 0x2E73703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* maclw<.f><.cc> 0,limm,u6 0010111011110011F111uuuuuu1QQQQQ. */ +{ "maclw", 0x2EF37020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* maclw<.f> 0,limm,s12 0010111010110011F111ssssssSSSSSS. */ +{ "maclw", 0x2EB37000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* maclw<.f> a,limm,limm 0010111000110011F111111110AAAAAA. */ +{ "maclw", 0x2E337F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* maclw<.f> 0,limm,limm 0010111000110011F111111110111110. */ +{ "maclw", 0x2E337FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* maclw<.f><.cc> 0,limm,limm 0010111011110011F1111111100QQQQQ. */ +{ "maclw", 0x2EF37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* macrdw<.f> a,b,c 00101bbb00010010FBBBCCCCCCAAAAAA. */ +{ "macrdw", 0x28120000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macrdw<.f> 0,b,c 00101bbb00010010FBBBCCCCCC111110. */ +{ "macrdw", 0x2812003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macrdw<.f><.cc> b,b,c 00101bbb11010010FBBBCCCCCC0QQQQQ. */ +{ "macrdw", 0x28D20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* macrdw<.f> a,b,u6 00101bbb01010010FBBBuuuuuuAAAAAA. */ +{ "macrdw", 0x28520000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macrdw<.f> 0,b,u6 00101bbb01010010FBBBuuuuuu111110. */ +{ "macrdw", 0x2852003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macrdw<.f><.cc> b,b,u6 00101bbb11010010FBBBuuuuuu1QQQQQ. */ +{ "macrdw", 0x28D20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macrdw<.f> b,b,s12 00101bbb10010010FBBBssssssSSSSSS. */ +{ "macrdw", 0x28920000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* macrdw<.f> a,limm,c 0010111000010010F111CCCCCCAAAAAA. */ +{ "macrdw", 0x2E127000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macrdw<.f> a,b,limm 00101bbb00010010FBBB111110AAAAAA. */ +{ "macrdw", 0x28120F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macrdw<.f> 0,limm,c 0010111000010010F111CCCCCC111110. */ +{ "macrdw", 0x2E12703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macrdw<.f> 0,b,limm 00101bbb00010010FBBB111110111110. */ +{ "macrdw", 0x28120FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macrdw<.f><.cc> 0,limm,c 0010111011010010F111CCCCCC0QQQQQ. */ +{ "macrdw", 0x2ED27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* macrdw<.f><.cc> b,b,limm 00101bbb11010010FBBB1111100QQQQQ. */ +{ "macrdw", 0x28D20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* macrdw<.f> a,limm,u6 0010111001010010F111uuuuuuAAAAAA. */ +{ "macrdw", 0x2E527000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macrdw<.f> 0,limm,u6 0010111001010010F111uuuuuu111110. */ +{ "macrdw", 0x2E52703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macrdw<.f><.cc> 0,limm,u6 0010111011010010F111uuuuuu1QQQQQ. */ +{ "macrdw", 0x2ED27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macrdw<.f> 0,limm,s12 0010111010010010F111ssssssSSSSSS. */ +{ "macrdw", 0x2E927000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* macrdw<.f> a,limm,limm 0010111000010010F111111110AAAAAA. */ +{ "macrdw", 0x2E127F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macrdw<.f> 0,limm,limm 0010111000010010F111111110111110. */ +{ "macrdw", 0x2E127FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macrdw<.f><.cc> 0,limm,limm 0010111011010010F1111111100QQQQQ. */ +{ "macrdw", 0x2ED27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* macrt<.f> a,b,c 00101bbb00011110FBBBCCCCCCAAAAAA. */ +{ "macrt", 0x281E0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macrt<.f> 0,b,c 00101bbb00011110FBBBCCCCCC111110. */ +{ "macrt", 0x281E003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macrt<.f><.cc> b,b,c 00101bbb11011110FBBBCCCCCC0QQQQQ. */ +{ "macrt", 0x28DE0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* macrt<.f> a,b,u6 00101bbb01011110FBBBuuuuuuAAAAAA. */ +{ "macrt", 0x285E0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macrt<.f> 0,b,u6 00101bbb01011110FBBBuuuuuu111110. */ +{ "macrt", 0x285E003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macrt<.f><.cc> b,b,u6 00101bbb11011110FBBBuuuuuu1QQQQQ. */ +{ "macrt", 0x28DE0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macrt<.f> b,b,s12 00101bbb10011110FBBBssssssSSSSSS. */ +{ "macrt", 0x289E0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* macrt<.f> a,limm,c 0010111000011110F111CCCCCCAAAAAA. */ +{ "macrt", 0x2E1E7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macrt<.f> a,b,limm 00101bbb00011110FBBB111110AAAAAA. */ +{ "macrt", 0x281E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macrt<.f> 0,limm,c 0010111000011110F111CCCCCC111110. */ +{ "macrt", 0x2E1E703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macrt<.f> 0,b,limm 00101bbb00011110FBBB111110111110. */ +{ "macrt", 0x281E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macrt<.f><.cc> 0,limm,c 0010111011011110F111CCCCCC0QQQQQ. */ +{ "macrt", 0x2EDE7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* macrt<.f><.cc> b,b,limm 00101bbb11011110FBBB1111100QQQQQ. */ +{ "macrt", 0x28DE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* macrt<.f> a,limm,u6 0010111001011110F111uuuuuuAAAAAA. */ +{ "macrt", 0x2E5E7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macrt<.f> 0,limm,u6 0010111001011110F111uuuuuu111110. */ +{ "macrt", 0x2E5E703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macrt<.f><.cc> 0,limm,u6 0010111011011110F111uuuuuu1QQQQQ. */ +{ "macrt", 0x2EDE7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macrt<.f> 0,limm,s12 0010111010011110F111ssssssSSSSSS. */ +{ "macrt", 0x2E9E7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* macrt<.f> a,limm,limm 0010111000011110F111111110AAAAAA. */ +{ "macrt", 0x2E1E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macrt<.f> 0,limm,limm 0010111000011110F111111110111110. */ +{ "macrt", 0x2E1E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macrt<.f><.cc> 0,limm,limm 0010111011011110F1111111100QQQQQ. */ +{ "macrt", 0x2EDE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mact<.f> a,b,c 00101bbb00011100FBBBCCCCCCAAAAAA. */ +{ "mact", 0x281C0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mact<.f> 0,b,c 00101bbb00011100FBBBCCCCCC111110. */ +{ "mact", 0x281C003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mact<.f><.cc> b,b,c 00101bbb11011100FBBBCCCCCC0QQQQQ. */ +{ "mact", 0x28DC0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mact<.f> a,b,u6 00101bbb01011100FBBBuuuuuuAAAAAA. */ +{ "mact", 0x285C0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mact<.f> 0,b,u6 00101bbb01011100FBBBuuuuuu111110. */ +{ "mact", 0x285C003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mact<.f><.cc> b,b,u6 00101bbb11011100FBBBuuuuuu1QQQQQ. */ +{ "mact", 0x28DC0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mact<.f> b,b,s12 00101bbb10011100FBBBssssssSSSSSS. */ +{ "mact", 0x289C0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mact<.f> a,limm,c 0010111000011100F111CCCCCCAAAAAA. */ +{ "mact", 0x2E1C7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mact<.f> a,b,limm 00101bbb00011100FBBB111110AAAAAA. */ +{ "mact", 0x281C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mact<.f> 0,limm,c 0010111000011100F111CCCCCC111110. */ +{ "mact", 0x2E1C703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mact<.f> 0,b,limm 00101bbb00011100FBBB111110111110. */ +{ "mact", 0x281C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mact<.f><.cc> 0,limm,c 0010111011011100F111CCCCCC0QQQQQ. */ +{ "mact", 0x2EDC7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mact<.f><.cc> b,b,limm 00101bbb11011100FBBB1111100QQQQQ. */ +{ "mact", 0x28DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mact<.f> a,limm,u6 0010111001011100F111uuuuuuAAAAAA. */ +{ "mact", 0x2E5C7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mact<.f> 0,limm,u6 0010111001011100F111uuuuuu111110. */ +{ "mact", 0x2E5C703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mact<.f><.cc> 0,limm,u6 0010111011011100F111uuuuuu1QQQQQ. */ +{ "mact", 0x2EDC7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mact<.f> 0,limm,s12 0010111010011100F111ssssssSSSSSS. */ +{ "mact", 0x2E9C7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mact<.f> a,limm,limm 0010111000011100F111111110AAAAAA. */ +{ "mact", 0x2E1C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mact<.f> 0,limm,limm 0010111000011100F111111110111110. */ +{ "mact", 0x2E1C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mact<.f><.cc> 0,limm,limm 0010111011011100F1111111100QQQQQ. */ +{ "mact", 0x2EDC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* macu<.f> a,b,c 00101bbb00001111FBBBCCCCCCAAAAAA. */ +{ "macu", 0x280F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macu<.f> 0,b,c 00101bbb00001111FBBBCCCCCC111110. */ +{ "macu", 0x280F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macu<.f><.cc> b,b,c 00101bbb11001111FBBBCCCCCC0QQQQQ. */ +{ "macu", 0x28CF0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* macu<.f> a,b,u6 00101bbb01001111FBBBuuuuuuAAAAAA. */ +{ "macu", 0x284F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macu<.f> 0,b,u6 00101bbb01001111FBBBuuuuuu111110. */ +{ "macu", 0x284F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macu<.f><.cc> b,b,u6 00101bbb11001111FBBBuuuuuu1QQQQQ. */ +{ "macu", 0x28CF0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macu<.f> b,b,s12 00101bbb10001111FBBBssssssSSSSSS. */ +{ "macu", 0x288F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* macu<.f> a,limm,c 0010111000001111F111CCCCCCAAAAAA. */ +{ "macu", 0x2E0F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macu<.f> a,b,limm 00101bbb00001111FBBB111110AAAAAA. */ +{ "macu", 0x280F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macu<.f> 0,limm,c 0010111000001111F111CCCCCC111110. */ +{ "macu", 0x2E0F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macu<.f> 0,b,limm 00101bbb00001111FBBB111110111110. */ +{ "macu", 0x280F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macu<.f><.cc> b,b,limm 00101bbb11001111FBBB1111100QQQQQ. */ +{ "macu", 0x28CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* macu<.f><.cc> 0,limm,c 0010111011001111F111CCCCCC0QQQQQ. */ +{ "macu", 0x2ECF7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* macu<.f> a,limm,u6 0010111001001111F111uuuuuuAAAAAA. */ +{ "macu", 0x2E4F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macu<.f> 0,limm,u6 0010111001001111F111uuuuuu111110. */ +{ "macu", 0x2E4F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macu<.f><.cc> 0,limm,u6 0010111011001111F111uuuuuu1QQQQQ. */ +{ "macu", 0x2ECF7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macu<.f> 0,limm,s12 0010111010001111F111ssssssSSSSSS. */ +{ "macu", 0x2E8F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* macu<.f> a,limm,limm 0010111000001111F111111110AAAAAA. */ +{ "macu", 0x2E0F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macu<.f> 0,limm,limm 0010111000001111F111111110111110. */ +{ "macu", 0x2E0F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macu<.f><.cc> 0,limm,limm 0010111011001111F1111111100QQQQQ. */ +{ "macu", 0x2ECF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* macudw<.f> a,b,c 00101bbb00010001FBBBCCCCCCAAAAAA. */ +{ "macudw", 0x28110000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macudw<.f> 0,b,c 00101bbb00010001FBBBCCCCCC111110. */ +{ "macudw", 0x2811003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macudw<.f><.cc> b,b,c 00101bbb11010001FBBBCCCCCC0QQQQQ. */ +{ "macudw", 0x28D10000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* macudw<.f> a,b,u6 00101bbb01010001FBBBuuuuuuAAAAAA. */ +{ "macudw", 0x28510000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macudw<.f> 0,b,u6 00101bbb01010001FBBBuuuuuu111110. */ +{ "macudw", 0x2851003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macudw<.f><.cc> b,b,u6 00101bbb11010001FBBBuuuuuu1QQQQQ. */ +{ "macudw", 0x28D10020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macudw<.f> b,b,s12 00101bbb10010001FBBBssssssSSSSSS. */ +{ "macudw", 0x28910000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* macudw<.f> a,limm,c 0010111000010001F111CCCCCCAAAAAA. */ +{ "macudw", 0x2E117000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macudw<.f> a,b,limm 00101bbb00010001FBBB111110AAAAAA. */ +{ "macudw", 0x28110F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macudw<.f> 0,limm,c 0010111000010001F111CCCCCC111110. */ +{ "macudw", 0x2E11703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macudw<.f> 0,b,limm 00101bbb00010001FBBB111110111110. */ +{ "macudw", 0x28110FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macudw<.f><.cc> 0,limm,c 0010111011010001F111CCCCCC0QQQQQ. */ +{ "macudw", 0x2ED17000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* macudw<.f><.cc> b,b,limm 00101bbb11010001FBBB1111100QQQQQ. */ +{ "macudw", 0x28D10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* macudw<.f> a,limm,u6 0010111001010001F111uuuuuuAAAAAA. */ +{ "macudw", 0x2E517000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macudw<.f> 0,limm,u6 0010111001010001F111uuuuuu111110. */ +{ "macudw", 0x2E51703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macudw<.f><.cc> 0,limm,u6 0010111011010001F111uuuuuu1QQQQQ. */ +{ "macudw", 0x2ED17020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macudw<.f> 0,limm,s12 0010111010010001F111ssssssSSSSSS. */ +{ "macudw", 0x2E917000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* macudw<.f> a,limm,limm 0010111000010001F111111110AAAAAA. */ +{ "macudw", 0x2E117F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macudw<.f> 0,limm,limm 0010111000010001F111111110111110. */ +{ "macudw", 0x2E117FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macudw<.f><.cc> 0,limm,limm 0010111011010001F1111111100QQQQQ. */ +{ "macudw", 0x2ED17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* macwhfm<.f> a,b,c 00110bbb00100010FBBBCCCCCCAAAAAA. */ +{ "macwhfm", 0x30220000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macwhfm<.f> 0,b,c 00110bbb00100010FBBBCCCCCC111110. */ +{ "macwhfm", 0x3022003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macwhfl<.f> a,b,c 00110bbb00100110FBBBCCCCCCAAAAAA */ +{ "macwhfl", 0x30260000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macwhfl<.f> 0,b,c 00110bbb00100110FBBBCCCCCC111110 */ +{ "macwhfl", 0x3026003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macwhfl<.f><.cc> b,b,c 00110bbb11100110FBBBCCCCCC0QQQQQ */ +{ "macwhfl", 0x30E60000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* macwhfl<.f> a,b,u6 00110bbb01100110FBBBuuuuuuAAAAAA */ +{ "macwhfl", 0x30660000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhfl<.f><.cc> b,b,u6 00110bbb11100110FBBBuuuuuu1QQQQQ */ +{ "macwhfl", 0x30E60020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macwhfl<.f> 0,b,u6 00110bbb01100110FBBBuuuuuu111110 */ +{ "macwhfl", 0x3066003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhfl<.f> b,b,s12 00110bbb10100110FBBBssssssSSSSSS */ +{ "macwhfl", 0x30A60000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* macwhfl<.f> 0,limm,c 0011011001100110F111CCCCCC111110 */ +{ "macwhfl", 0x3666703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macwhfl<.f> 0,b,limm 00110bbb00100110FBBB111110111110 */ +{ "macwhfl", 0x30260FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macwhfl<.f> a,b,limm 00110bbb00100110FBBB111110AAAAAA */ +{ "macwhfl", 0x30260F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macwhfl<.f><.cc> b,b,limm 0011011011100110F111CCCCCC0QQQQQ */ +{ "macwhfl", 0x36E67000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* macwhfl<.f><.cc> 0,limm,c 00110bbb11100110FBBB1111100QQQQQ */ +{ "macwhfl", 0x30E60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* macwhfl<.f> a,limm,c 0011011000100110F111CCCCCCAAAAAA */ +{ "macwhfl", 0x36267000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macwhfl<.f><.cc> 0,limm,u6 0011011011100110F111uuuuuu1QQQQQ */ +{ "macwhfl", 0x36E67020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macwhfl<.f> 0,limm,u6 0011011001100110F111uuuuuu111110 */ +{ "macwhfl", 0x3666703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhfl<.f> a,limm,u6 0011011001100110F111uuuuuuAAAAAA */ +{ "macwhfl", 0x36667000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhfl<.f> 0,limm,s12 0011011010100110F111ssssssSSSSSS */ +{ "macwhfl", 0x36A67000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* macwhfl<.f><.cc> 0,limm,limm 0011011011100110F1111111100QQQQQ */ +{ "macwhfl", 0x36E67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* macwhfl<.f> 0,limm,limm 0011011000100110F111111110111110 */ +{ "macwhfl", 0x36267FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macwhfl<.f> a,limm,limm 0011011000100110F111111110AAAAAA */ +{ "macwhfl", 0x36267F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macwhflr<.f><.cc> b,b,c 00110bbb11100111FBBBCCCCCC0QQQQQ */ +{ "macwhflr", 0x30E70000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* macwhflr<.f> 0,b,c 00110bbb00100111FBBBCCCCCC111110 */ +{ "macwhflr", 0x3027003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macwhflr<.f> a,b,c 00110bbb00100111FBBBCCCCCCAAAAAA */ +{ "macwhflr", 0x30270000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macwhflr<.f> 0,b,u6 00110bbb01100111FBBBuuuuuu111110 */ +{ "macwhflr", 0x3067003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhflr<.f> a,b,u6 00110bbb01100111FBBBuuuuuuAAAAAA */ +{ "macwhflr", 0x30670000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhflr<.f><.cc> b,b,u6 00110bbb11100111FBBBuuuuuu1QQQQQ */ +{ "macwhflr", 0x30E70020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macwhflr<.f> b,b,s12 00110bbb10100111FBBBssssssSSSSSS */ +{ "macwhflr", 0x30A70000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* macwhflr<.f> a,b,limm 00110bbb00100111FBBB111110AAAAAA */ +{ "macwhflr", 0x30270F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macwhflr<.f><.cc> 0,limm,c 00110bbb11100111FBBB1111100QQQQQ */ +{ "macwhflr", 0x30E70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* macwhflr<.f><.cc> b,b,limm 0011011011100111F111CCCCCC0QQQQQ */ +{ "macwhflr", 0x36E77000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* macwhflr<.f> 0,b,limm 00110bbb00100111FBBB111110111110 */ +{ "macwhflr", 0x30270FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macwhflr<.f> 0,limm,c 0011011001100111F111CCCCCC111110 */ +{ "macwhflr", 0x3667703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macwhflr<.f> a,limm,c 0011011000100111F111CCCCCCAAAAAA */ +{ "macwhflr", 0x36277000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macwhflr<.f><.cc> 0,limm,u6 0011011011100111F111uuuuuu1QQQQQ */ +{ "macwhflr", 0x36E77020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macwhflr<.f> 0,limm,u6 0011011001100111F111uuuuuu111110 */ +{ "macwhflr", 0x3667703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhflr<.f> a,limm,u6 0011011001100111F111uuuuuuAAAAAA */ +{ "macwhflr", 0x36677000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhflr<.f> 0,limm,s12 0011011010100111F111ssssssSSSSSS */ +{ "macwhflr", 0x36A77000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* macwhflr<.f><.cc> 0,limm,limm 0011011011100111F1111111100QQQQQ */ +{ "macwhflr", 0x36E77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* macwhflr<.f> a,limm,limm 0011011000100111F111111110AAAAAA */ +{ "macwhflr", 0x36277F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macwhflr<.f> 0,limm,limm 0011011000100111F111111110111110 */ +{ "macwhflr", 0x36277FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macwhfm<.f><.cc> b,b,c 00110bbb11100010FBBBCCCCCC0QQQQQ. */ +{ "macwhfm", 0x30E20000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* macwhfm<.f> a,b,u6 00110bbb01100010FBBBuuuuuuAAAAAA. */ +{ "macwhfm", 0x30620000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhfm<.f> 0,b,u6 00110bbb01100010FBBBuuuuuu111110. */ +{ "macwhfm", 0x3062003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhfm<.f><.cc> b,b,u6 00110bbb11100010FBBBuuuuuu1QQQQQ. */ +{ "macwhfm", 0x30E20020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macwhfm<.f> b,b,s12 00110bbb10100010FBBBssssssSSSSSS. */ +{ "macwhfm", 0x30A20000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* macwhfm<.f> a,limm,c 0011011000100010F111CCCCCCAAAAAA. */ +{ "macwhfm", 0x36227000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macwhfm<.f> a,b,limm 00110bbb00100010FBBB111110AAAAAA. */ +{ "macwhfm", 0x30220F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macwhfm<.f> 0,limm,c 0011011001100010F111CCCCCC111110. */ +{ "macwhfm", 0x3662703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macwhfm<.f> 0,b,limm 00110bbb00100010FBBB111110111110. */ +{ "macwhfm", 0x30220FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macwhfm<.f><.cc> 0,limm,c 00110bbb11100010FBBB1111100QQQQQ. */ +{ "macwhfm", 0x30E20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* macwhfm<.f><.cc> b,b,limm 0011011011100010F111CCCCCC0QQQQQ. */ +{ "macwhfm", 0x36E27000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* macwhfm<.f> a,limm,u6 0011011001100010F111uuuuuuAAAAAA. */ +{ "macwhfm", 0x36627000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhfm<.f> 0,limm,u6 0011011001100010F111uuuuuu111110. */ +{ "macwhfm", 0x3662703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhfm<.f><.cc> 0,limm,u6 0011011011100010F111uuuuuu1QQQQQ. */ +{ "macwhfm", 0x36E27020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macwhfm<.f> 0,limm,s12 0011011010100010F111ssssssSSSSSS. */ +{ "macwhfm", 0x36A27000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* macwhfm<.f> a,limm,limm 0011011000100010F111111110AAAAAA. */ +{ "macwhfm", 0x36227F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macwhfm<.f> 0,limm,limm 0011011000100010F111111110111110. */ +{ "macwhfm", 0x36227FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macwhfm<.f><.cc> 0,limm,limm 0011011011100010F1111111100QQQQQ. */ +{ "macwhfm", 0x36E27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* macwhfmr<.f> a,b,c 00110bbb00100011FBBBCCCCCCAAAAAA. */ +{ "macwhfmr", 0x30230000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macwhfmr<.f> 0,b,c 00110bbb00100011FBBBCCCCCC111110. */ +{ "macwhfmr", 0x3023003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macwhfmr<.f><.cc> b,b,c 00110bbb11100011FBBBCCCCCC0QQQQQ. */ +{ "macwhfmr", 0x30E30000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* macwhfmr<.f> a,b,u6 00110bbb01100011FBBBuuuuuuAAAAAA. */ +{ "macwhfmr", 0x30630000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhfmr<.f> 0,b,u6 00110bbb01100011FBBBuuuuuu111110. */ +{ "macwhfmr", 0x3063003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhfmr<.f><.cc> b,b,u6 00110bbb11100011FBBBuuuuuu1QQQQQ. */ +{ "macwhfmr", 0x30E30020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macwhfmr<.f> b,b,s12 00110bbb10100011FBBBssssssSSSSSS. */ +{ "macwhfmr", 0x30A30000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* macwhfmr<.f> a,limm,c 0011011000100011F111CCCCCCAAAAAA. */ +{ "macwhfmr", 0x36237000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macwhfmr<.f> a,b,limm 00110bbb00100011FBBB111110AAAAAA. */ +{ "macwhfmr", 0x30230F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macwhfmr<.f> 0,limm,c 0011011001100011F111CCCCCC111110. */ +{ "macwhfmr", 0x3663703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macwhfmr<.f> 0,b,limm 00110bbb00100011FBBB111110111110. */ +{ "macwhfmr", 0x30230FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macwhfmr<.f><.cc> 0,limm,c 00110bbb11100011FBBB1111100QQQQQ. */ +{ "macwhfmr", 0x30E30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* macwhfmr<.f><.cc> b,b,limm 0011011011100011F111CCCCCC0QQQQQ. */ +{ "macwhfmr", 0x36E37000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* macwhfmr<.f> a,limm,u6 0011011001100011F111uuuuuuAAAAAA. */ +{ "macwhfmr", 0x36637000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhfmr<.f> 0,limm,u6 0011011001100011F111uuuuuu111110. */ +{ "macwhfmr", 0x3663703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhfmr<.f><.cc> 0,limm,u6 0011011011100011F111uuuuuu1QQQQQ. */ +{ "macwhfmr", 0x36E37020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macwhfmr<.f> 0,limm,s12 0011011010100011F111ssssssSSSSSS. */ +{ "macwhfmr", 0x36A37000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* macwhfmr<.f> a,limm,limm 0011011000100011F111111110AAAAAA. */ +{ "macwhfmr", 0x36237F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macwhfmr<.f> 0,limm,limm 0011011000100011F111111110111110. */ +{ "macwhfmr", 0x36237FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macwhfmr<.f><.cc> 0,limm,limm 0011011011100011F1111111100QQQQQ. */ +{ "macwhfmr", 0x36E37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* macwhkl<.f> a,b,c 00110bbb00101000FBBBCCCCCCAAAAAA */ +{ "macwhkl", 0x30280000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macwhkl<.f> 0,b,c 00110bbb00101000FBBBCCCCCC111110 */ +{ "macwhkl", 0x3028003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macwhkl<.f><.cc> b,b,c 00110bbb11101000FBBBCCCCCC0QQQQQ */ +{ "macwhkl", 0x30E80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* macwhkl<.f> 0,b,u6 00110bbb01101000FBBBuuuuuu111110 */ +{ "macwhkl", 0x3068003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhkl<.f> a,b,u6 00110bbb01101000FBBBuuuuuuAAAAAA */ +{ "macwhkl", 0x30680000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhkl<.f><.cc> b,b,u6 00110bbb11101000FBBBuuuuuu1QQQQQ */ +{ "macwhkl", 0x30E80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macwhkl<.f> b,b,s12 00110bbb10101000FBBBssssssSSSSSS */ +{ "macwhkl", 0x30A80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* macwhkl<.f> a,b,limm 00110bbb00101000FBBB111110AAAAAA */ +{ "macwhkl", 0x30280F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macwhkl<.f><.cc> 0,limm,c 00110bbb11101000FBBB1111100QQQQQ */ +{ "macwhkl", 0x30E80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* macwhkl<.f> 0,limm,c 0011011001101000F111CCCCCC111110 */ +{ "macwhkl", 0x3668703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macwhkl<.f> 0,b,limm 00110bbb00101000FBBB111110111110 */ +{ "macwhkl", 0x30280FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macwhkl<.f> a,limm,c 0011011000101000F111CCCCCCAAAAAA */ +{ "macwhkl", 0x36287000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macwhkl<.f><.cc> b,b,limm 0011011011101000F111CCCCCC0QQQQQ */ +{ "macwhkl", 0x36E87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* macwhkl<.f> 0,limm,u6 0011011001101000F111uuuuuu111110 */ +{ "macwhkl", 0x3668703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhkl<.f><.cc> 0,limm,u6 0011011011101000F111uuuuuu1QQQQQ */ +{ "macwhkl", 0x36E87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macwhkl<.f> a,limm,u6 0011011001101000F111uuuuuuAAAAAA */ +{ "macwhkl", 0x36687000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhkl<.f> 0,limm,s12 0011011010101000F111ssssssSSSSSS */ +{ "macwhkl", 0x36A87000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* macwhkl<.f><.cc> 0,limm,limm 0011011011101000F1111111100QQQQQ */ +{ "macwhkl", 0x36E87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* macwhkl<.f> 0,limm,limm 0011011000101000F111111110111110 */ +{ "macwhkl", 0x36287FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macwhkl<.f> a,limm,limm 0011011000101000F111111110AAAAAA */ +{ "macwhkl", 0x36287F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macwhkul<.f> a,b,c 00110bbb00101001FBBBCCCCCCAAAAAA */ +{ "macwhkul", 0x30290000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macwhkul<.f> 0,b,c 00110bbb00101001FBBBCCCCCC111110 */ +{ "macwhkul", 0x3029003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macwhkul<.f><.cc> b,b,c 00110bbb11101001FBBBCCCCCC0QQQQQ */ +{ "macwhkul", 0x30E90000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* macwhkul<.f> a,b,u6 00110bbb01101001FBBBuuuuuuAAAAAA */ +{ "macwhkul", 0x30690000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhkul<.f> 0,b,u6 00110bbb01101001FBBBuuuuuu111110 */ +{ "macwhkul", 0x3069003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhkul<.f><.cc> b,b,u6 00110bbb11101001FBBBuuuuuu1QQQQQ */ +{ "macwhkul", 0x30E90020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macwhkul<.f> b,b,s12 00110bbb10101001FBBBssssssSSSSSS */ +{ "macwhkul", 0x30A90000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* macwhkul<.f> a,b,limm 00110bbb00101001FBBB111110AAAAAA */ +{ "macwhkul", 0x30290F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macwhkul<.f><.cc> 0,limm,c 00110bbb11101001FBBB1111100QQQQQ */ +{ "macwhkul", 0x30E90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* macwhkul<.f><.cc> b,b,limm 0011011011101001F111CCCCCC0QQQQQ */ +{ "macwhkul", 0x36E97000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* macwhkul<.f> a,limm,c 0011011000101001F111CCCCCCAAAAAA */ +{ "macwhkul", 0x36297000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macwhkul<.f> 0,limm,c 0011011001101001F111CCCCCC111110 */ +{ "macwhkul", 0x3669703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macwhkul<.f> 0,b,limm 00110bbb00101001FBBB111110111110 */ +{ "macwhkul", 0x30290FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macwhkul<.f> a,limm,u6 0011011001101001F111uuuuuuAAAAAA */ +{ "macwhkul", 0x36697000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhkul<.f><.cc> 0,limm,u6 0011011011101001F111uuuuuu1QQQQQ */ +{ "macwhkul", 0x36E97020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macwhkul<.f> 0,limm,u6 0011011001101001F111uuuuuu111110 */ +{ "macwhkul", 0x3669703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhkul<.f> 0,limm,s12 0011011010101001F111ssssssSSSSSS */ +{ "macwhkul", 0x36A97000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* macwhkul<.f> a,limm,limm 0011011000101001F111111110AAAAAA */ +{ "macwhkul", 0x36297F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macwhkul<.f> 0,limm,limm 0011011000101001F111111110111110 */ +{ "macwhkul", 0x36297FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macwhkul<.f><.cc> 0,limm,limm 0011011011101001F1111111100QQQQQ */ +{ "macwhkul", 0x36E97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* macwhl<.f> a,b,c 00110bbb00011101FBBBCCCCCCAAAAAA. */ +{ "macwhl", 0x301D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macwhl<.f> 0,b,c 00110bbb00011101FBBBCCCCCC111110. */ +{ "macwhl", 0x301D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macwhl<.f><.cc> b,b,c 00110bbb11011101FBBBCCCCCC0QQQQQ. */ +{ "macwhl", 0x30DD0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* macwhl<.f> a,b,u6 00110bbb01011101FBBBuuuuuuAAAAAA. */ +{ "macwhl", 0x305D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhl<.f> 0,b,u6 00110bbb01011101FBBBuuuuuu111110. */ +{ "macwhl", 0x305D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhl<.f><.cc> b,b,u6 00110bbb11011101FBBBuuuuuu1QQQQQ. */ +{ "macwhl", 0x30DD0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macwhl<.f> b,b,s12 00110bbb10011101FBBBssssssSSSSSS. */ +{ "macwhl", 0x309D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* macwhl<.f> a,limm,c 0011011000011101F111CCCCCCAAAAAA. */ +{ "macwhl", 0x361D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macwhl<.f> a,b,limm 00110bbb00011101FBBB111110AAAAAA. */ +{ "macwhl", 0x301D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macwhl<.f> 0,limm,c 0011011000011101F111CCCCCC111110. */ +{ "macwhl", 0x361D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macwhl<.f> 0,b,limm 00110bbb00011101FBBB111110111110. */ +{ "macwhl", 0x301D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macwhl<.f><.cc> 0,limm,c 00110bbb11011101FBBB1111100QQQQQ. */ +{ "macwhl", 0x30DD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* macwhl<.f><.cc> b,b,limm 0011011011011101F111CCCCCC0QQQQQ. */ +{ "macwhl", 0x36DD7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* macwhl<.f> a,limm,u6 0011011001011101F111uuuuuuAAAAAA. */ +{ "macwhl", 0x365D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhl<.f> 0,limm,u6 0011011001011101F111uuuuuu111110. */ +{ "macwhl", 0x365D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhl<.f><.cc> 0,limm,u6 0011011011011101F111uuuuuu1QQQQQ. */ +{ "macwhl", 0x36DD7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macwhl<.f> 0,limm,s12 0011011010011101F111ssssssSSSSSS. */ +{ "macwhl", 0x369D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* macwhl<.f> a,limm,limm 0011011000011101F111111110AAAAAA. */ +{ "macwhl", 0x361D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macwhl<.f> 0,limm,limm 0011011000011101F111111110111110. */ +{ "macwhl", 0x361D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macwhl<.f><.cc> 0,limm,limm 0011011011011101F1111111100QQQQQ. */ +{ "macwhl", 0x36DD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* macwhul<.f> a,b,c 00110bbb00011111FBBBCCCCCCAAAAAA. */ +{ "macwhul", 0x301F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macwhul<.f> 0,b,c 00110bbb00011111FBBBCCCCCC111110. */ +{ "macwhul", 0x301F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* macwhul<.f><.cc> b,b,c 00110bbb11011111FBBBCCCCCC0QQQQQ. */ +{ "macwhul", 0x30DF0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* macwhul<.f> a,b,u6 00110bbb01011111FBBBuuuuuuAAAAAA. */ +{ "macwhul", 0x305F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhul<.f> 0,b,u6 00110bbb01011111FBBBuuuuuu111110. */ +{ "macwhul", 0x305F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhul<.f><.cc> b,b,u6 00110bbb11011111FBBBuuuuuu1QQQQQ. */ +{ "macwhul", 0x30DF0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macwhul<.f> b,b,s12 00110bbb10011111FBBBssssssSSSSSS. */ +{ "macwhul", 0x309F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* macwhul<.f> a,limm,c 0011011000011111F111CCCCCCAAAAAA. */ +{ "macwhul", 0x361F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macwhul<.f> a,b,limm 00110bbb00011111FBBB111110AAAAAA. */ +{ "macwhul", 0x301F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macwhul<.f> 0,limm,c 0011011000011111F111CCCCCC111110. */ +{ "macwhul", 0x361F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* macwhul<.f> 0,b,limm 00110bbb00011111FBBB111110111110. */ +{ "macwhul", 0x301F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* macwhul<.f><.cc> 0,limm,c 00110bbb11011111FBBB1111100QQQQQ. */ +{ "macwhul", 0x30DF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* macwhul<.f><.cc> b,b,limm 0011011011011111F111CCCCCC0QQQQQ. */ +{ "macwhul", 0x36DF7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* macwhul<.f> a,limm,u6 0011011001011111F111uuuuuuAAAAAA. */ +{ "macwhul", 0x365F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhul<.f> 0,limm,u6 0011011001011111F111uuuuuu111110. */ +{ "macwhul", 0x365F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* macwhul<.f><.cc> 0,limm,u6 0011011011011111F111uuuuuu1QQQQQ. */ +{ "macwhul", 0x36DF7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* macwhul<.f> 0,limm,s12 0011011010011111F111ssssssSSSSSS. */ +{ "macwhul", 0x369F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* macwhul<.f> a,limm,limm 0011011000011111F111111110AAAAAA. */ +{ "macwhul", 0x361F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macwhul<.f> 0,limm,limm 0011011000011111F111111110111110. */ +{ "macwhul", 0x361F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* macwhul<.f><.cc> 0,limm,limm 0011011011011111F1111111100QQQQQ. */ +{ "macwhul", 0x36DF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* max<.f> a,b,c 00100bbb00001000FBBBCCCCCCAAAAAA. */ +{ "max", 0x20080000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* max<.f> 0,b,c 00100bbb00001000FBBBCCCCCC111110. */ +{ "max", 0x2008003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* max<.f><.cc> b,b,c 00100bbb11001000FBBBCCCCCC0QQQQQ. */ +{ "max", 0x20C80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* max<.f> a,b,u6 00100bbb01001000FBBBuuuuuuAAAAAA. */ +{ "max", 0x20480000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* max<.f> 0,b,u6 00100bbb01001000FBBBuuuuuu111110. */ +{ "max", 0x2048003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* max<.f><.cc> b,b,u6 00100bbb11001000FBBBuuuuuu1QQQQQ. */ +{ "max", 0x20C80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* max<.f> b,b,s12 00100bbb10001000FBBBssssssSSSSSS. */ +{ "max", 0x20880000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* max<.f> a,limm,c 0010011000001000F111CCCCCCAAAAAA. */ +{ "max", 0x26087000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* max<.f> a,b,limm 00100bbb00001000FBBB111110AAAAAA. */ +{ "max", 0x20080F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* max<.f> 0,limm,c 0010011000001000F111CCCCCC111110. */ +{ "max", 0x2608703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* max<.f> 0,b,limm 00100bbb00001000FBBB111110111110. */ +{ "max", 0x20080FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* max<.f><.cc> b,b,limm 00100bbb11001000FBBB1111100QQQQQ. */ +{ "max", 0x20C80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* max<.f><.cc> 0,limm,c 0010011011001000F111CCCCCC0QQQQQ. */ +{ "max", 0x26C87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* max<.f> a,limm,u6 0010011001001000F111uuuuuuAAAAAA. */ +{ "max", 0x26487000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* max<.f> 0,limm,u6 0010011001001000F111uuuuuu111110. */ +{ "max", 0x2648703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* max<.f><.cc> 0,limm,u6 0010011011001000F111uuuuuu1QQQQQ. */ +{ "max", 0x26C87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* max<.f> 0,limm,s12 0010011010001000F111ssssssSSSSSS. */ +{ "max", 0x26887000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* max<.f> a,limm,limm 0010011000001000F111111110AAAAAA. */ +{ "max", 0x26087F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* max<.f> 0,limm,limm 0010011000001000F111111110111110. */ +{ "max", 0x26087FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* max<.f><.cc> 0,limm,limm 0010011011001000F1111111100QQQQQ. */ +{ "max", 0x26C87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* maxabssdw<.f> a,b,c 00101bbb00101011FBBBCCCCCCAAAAAA. */ +{ "maxabssdw", 0x282B0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* maxabssdw<.f> 0,b,c 00101bbb00101011FBBBCCCCCC111110. */ +{ "maxabssdw", 0x282B003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* maxabssdw<.f><.cc> b,b,c 00101bbb11101011FBBBCCCCCC0QQQQQ. */ +{ "maxabssdw", 0x28EB0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* maxabssdw<.f> a,b,u6 00101bbb01101011FBBBuuuuuuAAAAAA. */ +{ "maxabssdw", 0x286B0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* maxabssdw<.f> 0,b,u6 00101bbb01101011FBBBuuuuuu111110. */ +{ "maxabssdw", 0x286B003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* maxabssdw<.f><.cc> b,b,u6 00101bbb11101011FBBBuuuuuu1QQQQQ. */ +{ "maxabssdw", 0x28EB0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* maxabssdw<.f> b,b,s12 00101bbb10101011FBBBssssssSSSSSS. */ +{ "maxabssdw", 0x28AB0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* maxabssdw<.f> a,limm,c 0010111000101011F111CCCCCCAAAAAA. */ +{ "maxabssdw", 0x2E2B7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* maxabssdw<.f> a,b,limm 00101bbb00101011FBBB111110AAAAAA. */ +{ "maxabssdw", 0x282B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* maxabssdw<.f> 0,limm,c 0010111000101011F111CCCCCC111110. */ +{ "maxabssdw", 0x2E2B703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* maxabssdw<.f> 0,b,limm 00101bbb00101011FBBB111110111110. */ +{ "maxabssdw", 0x282B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* maxabssdw<.f><.cc> 0,limm,c 0010111011101011F111CCCCCC0QQQQQ. */ +{ "maxabssdw", 0x2EEB7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* maxabssdw<.f><.cc> b,b,limm 00101bbb11101011FBBB1111100QQQQQ. */ +{ "maxabssdw", 0x28EB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* maxabssdw<.f> a,limm,u6 0010111001101011F111uuuuuuAAAAAA. */ +{ "maxabssdw", 0x2E6B7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* maxabssdw<.f> 0,limm,u6 0010111001101011F111uuuuuu111110. */ +{ "maxabssdw", 0x2E6B703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* maxabssdw<.f><.cc> 0,limm,u6 0010111011101011F111uuuuuu1QQQQQ. */ +{ "maxabssdw", 0x2EEB7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* maxabssdw<.f> 0,limm,s12 0010111010101011F111ssssssSSSSSS. */ +{ "maxabssdw", 0x2EAB7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* maxabssdw<.f> a,limm,limm 0010111000101011F111111110AAAAAA. */ +{ "maxabssdw", 0x2E2B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* maxabssdw<.f> 0,limm,limm 0010111000101011F111111110111110. */ +{ "maxabssdw", 0x2E2B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* maxabssdw<.f><.cc> 0,limm,limm 0010111011101011F1111111100QQQQQ. */ +{ "maxabssdw", 0x2EEB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* maxidl<.f> a,b,c 00101bbb00001111FBBBCCCCCCAAAAAA. */ +{ "maxidl", 0x280F0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* maxidl<.f> 0,b,c 00101bbb00001111FBBBCCCCCC111110. */ +{ "maxidl", 0x280F003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* maxidl<.f><.cc> b,b,c 00101bbb11001111FBBBCCCCCC0QQQQQ. */ +{ "maxidl", 0x28CF0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* maxidl<.f> a,b,u6 00101bbb01001111FBBBuuuuuuAAAAAA. */ +{ "maxidl", 0x284F0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* maxidl<.f> 0,b,u6 00101bbb01001111FBBBuuuuuu111110. */ +{ "maxidl", 0x284F003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* maxidl<.f><.cc> b,b,u6 00101bbb11001111FBBBuuuuuu1QQQQQ. */ +{ "maxidl", 0x28CF0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* maxidl<.f> b,b,s12 00101bbb10001111FBBBssssssSSSSSS. */ +{ "maxidl", 0x288F0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* maxidl<.f> a,limm,c 0010111000001111F111CCCCCCAAAAAA. */ +{ "maxidl", 0x2E0F7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* maxidl<.f> a,b,limm 00101bbb00001111FBBB111110AAAAAA. */ +{ "maxidl", 0x280F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* maxidl<.f> 0,limm,c 0010111000001111F111CCCCCC111110. */ +{ "maxidl", 0x2E0F703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* maxidl<.f> 0,b,limm 00101bbb00001111FBBB111110111110. */ +{ "maxidl", 0x280F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* maxidl<.f><.cc> 0,limm,c 0010111011001111F111CCCCCC0QQQQQ. */ +{ "maxidl", 0x2ECF7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* maxidl<.f><.cc> b,b,limm 00101bbb11001111FBBB1111100QQQQQ. */ +{ "maxidl", 0x28CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* maxidl<.f> a,limm,u6 0010111001001111F111uuuuuuAAAAAA. */ +{ "maxidl", 0x2E4F7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* maxidl<.f> 0,limm,u6 0010111001001111F111uuuuuu111110. */ +{ "maxidl", 0x2E4F703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* maxidl<.f><.cc> 0,limm,u6 0010111011001111F111uuuuuu1QQQQQ. */ +{ "maxidl", 0x2ECF7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* maxidl<.f> 0,limm,s12 0010111010001111F111ssssssSSSSSS. */ +{ "maxidl", 0x2E8F7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* maxidl<.f> a,limm,limm 0010111000001111F111111110AAAAAA. */ +{ "maxidl", 0x2E0F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* maxidl<.f> 0,limm,limm 0010111000001111F111111110111110. */ +{ "maxidl", 0x2E0F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* maxidl<.f><.cc> 0,limm,limm 0010111011001111F1111111100QQQQQ. */ +{ "maxidl", 0x2ECF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* min<.f> a,b,c 00100bbb00001001FBBBCCCCCCAAAAAA. */ +{ "min", 0x20090000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* min<.f> 0,b,c 00100bbb00001001FBBBCCCCCC111110. */ +{ "min", 0x2009003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* min<.f><.cc> b,b,c 00100bbb11001001FBBBCCCCCC0QQQQQ. */ +{ "min", 0x20C90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* min<.f> a,b,u6 00100bbb01001001FBBBuuuuuuAAAAAA. */ +{ "min", 0x20490000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* min<.f> 0,b,u6 00100bbb01001001FBBBuuuuuu111110. */ +{ "min", 0x2049003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* min<.f><.cc> b,b,u6 00100bbb11001001FBBBuuuuuu1QQQQQ. */ +{ "min", 0x20C90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* min<.f> b,b,s12 00100bbb10001001FBBBssssssSSSSSS. */ +{ "min", 0x20890000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* min<.f> a,limm,c 0010011000001001F111CCCCCCAAAAAA. */ +{ "min", 0x26097000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* min<.f> a,b,limm 00100bbb00001001FBBB111110AAAAAA. */ +{ "min", 0x20090F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* min<.f> 0,limm,c 0010011000001001F111CCCCCC111110. */ +{ "min", 0x2609703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* min<.f> 0,b,limm 00100bbb00001001FBBB111110111110. */ +{ "min", 0x20090FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* min<.f><.cc> b,b,limm 00100bbb11001001FBBB1111100QQQQQ. */ +{ "min", 0x20C90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* min<.f><.cc> 0,limm,c 0010011011001001F111CCCCCC0QQQQQ. */ +{ "min", 0x26C97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* min<.f> a,limm,u6 0010011001001001F111uuuuuuAAAAAA. */ +{ "min", 0x26497000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* min<.f> 0,limm,u6 0010011001001001F111uuuuuu111110. */ +{ "min", 0x2649703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* min<.f><.cc> 0,limm,u6 0010011011001001F111uuuuuu1QQQQQ. */ +{ "min", 0x26C97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* min<.f> 0,limm,s12 0010011010001001F111ssssssSSSSSS. */ +{ "min", 0x26897000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* min<.f> a,limm,limm 0010011000001001F111111110AAAAAA. */ +{ "min", 0x26097F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* min<.f> 0,limm,limm 0010011000001001F111111110111110. */ +{ "min", 0x26097FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* min<.f><.cc> 0,limm,limm 0010011011001001F1111111100QQQQQ. */ +{ "min", 0x26C97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* minidl<.f> a,b,c 00101bbb00001001FBBBCCCCCCAAAAAA. */ +{ "minidl", 0x28090000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* minidl<.f> 0,b,c 00101bbb00001001FBBBCCCCCC111110. */ +{ "minidl", 0x2809003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* minidl<.f><.cc> b,b,c 00101bbb11001001FBBBCCCCCC0QQQQQ. */ +{ "minidl", 0x28C90000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* minidl<.f> a,b,u6 00101bbb01001001FBBBuuuuuuAAAAAA. */ +{ "minidl", 0x28490000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* minidl<.f> 0,b,u6 00101bbb01001001FBBBuuuuuu111110. */ +{ "minidl", 0x2849003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* minidl<.f><.cc> b,b,u6 00101bbb11001001FBBBuuuuuu1QQQQQ. */ +{ "minidl", 0x28C90020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* minidl<.f> b,b,s12 00101bbb10001001FBBBssssssSSSSSS. */ +{ "minidl", 0x28890000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* minidl<.f> a,limm,c 0010111000001001F111CCCCCCAAAAAA. */ +{ "minidl", 0x2E097000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* minidl<.f> a,b,limm 00101bbb00001001FBBB111110AAAAAA. */ +{ "minidl", 0x28090F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* minidl<.f> 0,limm,c 0010111000001001F111CCCCCC111110. */ +{ "minidl", 0x2E09703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* minidl<.f> 0,b,limm 00101bbb00001001FBBB111110111110. */ +{ "minidl", 0x28090FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* minidl<.f><.cc> 0,limm,c 0010111011001001F111CCCCCC0QQQQQ. */ +{ "minidl", 0x2EC97000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* minidl<.f><.cc> b,b,limm 00101bbb11001001FBBB1111100QQQQQ. */ +{ "minidl", 0x28C90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* minidl<.f> a,limm,u6 0010111001001001F111uuuuuuAAAAAA. */ +{ "minidl", 0x2E497000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* minidl<.f> 0,limm,u6 0010111001001001F111uuuuuu111110. */ +{ "minidl", 0x2E49703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* minidl<.f><.cc> 0,limm,u6 0010111011001001F111uuuuuu1QQQQQ. */ +{ "minidl", 0x2EC97020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* minidl<.f> 0,limm,s12 0010111010001001F111ssssssSSSSSS. */ +{ "minidl", 0x2E897000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* minidl<.f> a,limm,limm 0010111000001001F111111110AAAAAA. */ +{ "minidl", 0x2E097F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* minidl<.f> 0,limm,limm 0010111000001001F111111110111110. */ +{ "minidl", 0x2E097FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* minidl<.f><.cc> 0,limm,limm 0010111011001001F1111111100QQQQQ. */ +{ "minidl", 0x2EC97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* nop 00100110010010100111000000000000. */ +{ "nop", 0x264A7000, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }}, + +/* mov<.f> b,c 00100bbb00001010FBBBCCCCCCRRRRRR. */ +{ "mov", 0x200A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mov<.f> 0,c 0010011000001010F111CCCCCCRRRRRR. */ +{ "mov", 0x260A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* mov<.f><.cc> b,c 00100bbb11001010FBBBCCCCCC0QQQQQ. */ +{ "mov", 0x20CA0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB, OPERAND_RC }, { C_F, C_CC }}, + +/* mov<.f><.cc> 0,c 0010011011001010F111CCCCCC0QQQQQ. */ +{ "mov", 0x26CA7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F, C_CC }}, + +/* mov<.f> b,u6 00100bbb01001010FBBBuuuuuuRRRRRR. */ +{ "mov", 0x204A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mov<.f> 0,u6 0010011001001010F111uuuuuuRRRRRR. */ +{ "mov", 0x264A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. */ +{ "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mov<.f><.cc> 0,u6 0010011011001010F111uuuuuu1QQQQQ. */ +{ "mov", 0x26CA7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. */ +{ "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { C_F }}, + +/* mov<.f> 0,s12 0010011010001010F111ssssssSSSSSS. */ +{ "mov", 0x268A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA, OPERAND_SIMM12_20 }, { C_F }}, + +/* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */ +{ "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mov<.f> 0,limm 0010011000001010F111111110RRRRRR. */ +{ "mov", 0x260A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */ +{ "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mov<.f><.cc> 0,limm 0010011011001010F1111111100QQQQQ. */ +{ "mov", 0x26CA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mov_s b,h 01110bbbhhh01HHH. */ +{ "mov_s", 0x00007008, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MOVE, NONE, { OPERAND_RB_S, OPERAND_R6H }, { 0 }}, + +/* mov_s b,h 01110bbbhhh010HH. */ +{ "mov_s", 0x00007008, 0x0000F81C, 0, MOVE, NONE, { OPERAND_RB_S, OPERAND_RH_S }, { 0 }}, + +/* mov_s h,b 01110bbbhhh11HHH. */ +{ "mov_s", 0x00007018, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MOVE, NONE, { OPERAND_R6H, OPERAND_RB_S }, { 0 }}, + +/* mov_s h,b 01110bbbhhh110HH. */ +{ "mov_s", 0x00007018, 0x0000F81C, 0, MOVE, NONE, { OPERAND_RH_S, OPERAND_RB_S }, { 0 }}, + +/* mov_s 0,b 01110bbb1101111H. */ +{ "mov_s", 0x000070DE, 0x0000F8FE, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MOVE, NONE, { OPERAND_ZA_S, OPERAND_RB_S }, { 0 }}, + +/* mov_s 0,b 01110bbb11011011. */ +{ "mov_s", 0x000070DB, 0x0000F8FF, 0, MOVE, NONE, { OPERAND_ZA_S, OPERAND_RB_S }, { 0 }}, + +/* mov_s g,h 01000ggghhhGG0HH. */ +{ "mov_s", 0x00004000, 0x0000F804, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_G_S, OPERAND_RH_S }, { 0 }}, + +/* mov_s 0,h 01000110hhh110HH. */ +{ "mov_s", 0x00004618, 0x0000FF1C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA_S, OPERAND_RH_S }, { 0 }}, + +/* mov_s h,s3 01110ssshhh011HH. */ +{ "mov_s", 0x0000700C, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RH_S, OPERAND_SIMM3_5_S }, { 0 }}, + +/* mov_s 0,s3 01110sss11001111. */ +{ "mov_s", 0x000070CF, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA_S, OPERAND_SIMM3_5_S }, { 0 }}, + +/* mov_s b,u8 11011bbbuuuuuuuu. */ +{ "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB_S, OPERAND_UIMM8_8_S }, { 0 }}, + +/* mov_s b,limm 01110bbb11001111. */ +{ "mov_s", 0x000070CF, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MOVE, NONE, { OPERAND_RB_S, OPERAND_LIMM_S }, { 0 }}, + +/* mov_s b,limm 01110bbb11001011. */ +{ "mov_s", 0x000070CB, 0x0000F8FF, 0, MOVE, NONE, { OPERAND_RB_S, OPERAND_LIMM_S }, { 0 }}, + +/* mov_s g,limm 01000ggg110GG011. */ +{ "mov_s", 0x000040C3, 0x0000F8E7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_G_S, OPERAND_LIMM_S }, { 0 }}, + +/* mov_s 0,limm 0100011011011011. */ +{ "mov_s", 0x000046DB, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_ZA_S, OPERAND_LIMM_S }, { 0 }}, + +/* mov_s.ne b,h 01110bbbhhh111HH. */ +{ "mov_s", 0x0000701C, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB_S, OPERAND_RH_S }, { C_NE, C_CC_NE }}, + +/* mov_s.ne b,limm 01110bbb11011111. */ +{ "mov_s", 0x000070DF, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MOVE, NONE, { OPERAND_RB_S, OPERAND_LIMM_S }, { C_NE, C_CC_NE }}, + +/* mpy<.f> a,b,c 00100bbb00011010FBBBCCCCCCAAAAAA. */ +{ "mpy", 0x201A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpy<.f> 0,b,c 00100bbb00011010FBBBCCCCCC111110. */ +{ "mpy", 0x201A003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpy<.f><.cc> b,b,c 00100bbb11011010FBBBCCCCCC0QQQQQ. */ +{ "mpy", 0x20DA0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. */ +{ "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpy<.f> 0,b,u6 00100bbb01011010FBBBuuuuuu111110. */ +{ "mpy", 0x205A003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpy<.f><.cc> b,b,u6 00100bbb11011010FBBBuuuuuu1QQQQQ. */ +{ "mpy", 0x20DA0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpy<.f> b,b,s12 00100bbb10011010FBBBssssssSSSSSS. */ +{ "mpy", 0x209A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpy<.f> a,limm,c 0010011000011010F111CCCCCCAAAAAA. */ +{ "mpy", 0x261A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */ +{ "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpy<.f> 0,limm,c 0010011000011010F111CCCCCC111110. */ +{ "mpy", 0x261A703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpy<.f> 0,b,limm 00100bbb00011010FBBB111110111110. */ +{ "mpy", 0x201A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpy<.f><.cc> b,b,limm 00100bbb11011010FBBB1111100QQQQQ. */ +{ "mpy", 0x20DA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpy<.f><.cc> 0,limm,c 0010011011011010F111CCCCCC0QQQQQ. */ +{ "mpy", 0x26DA7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mpy<.f> a,limm,u6 0010011001011010F111uuuuuuAAAAAA. */ +{ "mpy", 0x265A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpy<.f> 0,limm,u6 0010011001011010F111uuuuuu111110. */ +{ "mpy", 0x265A703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpy<.f><.cc> 0,limm,u6 0010011011011010F111uuuuuu1QQQQQ. */ +{ "mpy", 0x26DA7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpy<.f> 0,limm,s12 0010011010011010F111ssssssSSSSSS. */ +{ "mpy", 0x269A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpy<.f> a,limm,limm 0010011000011010F111111110AAAAAA. */ +{ "mpy", 0x261A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpy<.f> 0,limm,limm 0010011000011010F111111110111110. */ +{ "mpy", 0x261A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpy<.f><.cc> 0,limm,limm 0010011011011010F1111111100QQQQQ. */ +{ "mpy", 0x26DA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mpyd<.f> a,b,c 00101bbb00011000FBBBCCCCCCAAAAAA. */ +{ "mpyd", 0x28180000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpyd<.f> 0,b,c 00101bbb00011000FBBBCCCCCC111110. */ +{ "mpyd", 0x2818003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpyd<.f><.cc> b,b,c 00101bbb11011000FBBBCCCCCC0QQQQQ. */ +{ "mpyd", 0x28D80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpyd<.f> a,b,u6 00101bbb01011000FBBBuuuuuuAAAAAA. */ +{ "mpyd", 0x28580000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyd<.f> 0,b,u6 00101bbb01011000FBBBuuuuuu111110. */ +{ "mpyd", 0x2858003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyd<.f><.cc> b,b,u6 00101bbb11011000FBBBuuuuuu1QQQQQ. */ +{ "mpyd", 0x28D80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpyd<.f> b,b,s12 00101bbb10011000FBBBssssssSSSSSS. */ +{ "mpyd", 0x28980000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpyd<.f> a,limm,c 0010111000011000F111CCCCCCAAAAAA. */ +{ "mpyd", 0x2E187000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpyd<.f> a,b,limm 00101bbb00011000FBBB111110AAAAAA. */ +{ "mpyd", 0x28180F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpyd<.f> 0,limm,c 0010111000011000F111CCCCCC111110. */ +{ "mpyd", 0x2E18703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpyd<.f> 0,b,limm 00101bbb00011000FBBB111110111110. */ +{ "mpyd", 0x28180FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpyd<.f><.cc> b,b,limm 00101bbb11011000FBBB1111100QQQQQ. */ +{ "mpyd", 0x28D80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpyd<.f><.cc> 0,limm,c 0010111011011000F111CCCCCC0QQQQQ. */ +{ "mpyd", 0x2ED87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mpyd<.f> a,limm,u6 0010111001011000F111uuuuuuAAAAAA. */ +{ "mpyd", 0x2E587000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyd<.f> 0,limm,u6 0010111001011000F111uuuuuu111110. */ +{ "mpyd", 0x2E58703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyd<.f><.cc> 0,limm,u6 0010111011011000F111uuuuuu1QQQQQ. */ +{ "mpyd", 0x2ED87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpyd<.f> 0,limm,s12 0010111010011000F111ssssssSSSSSS. */ +{ "mpyd", 0x2E987000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpyd<.f> a,limm,limm 0010111000011000F111111110AAAAAA. */ +{ "mpyd", 0x2E187F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpyd<.f> 0,limm,limm 0010111000011000F111111110111110. */ +{ "mpyd", 0x2E187FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpyd<.f><.cc> 0,limm,limm 0010111011011000F1111111100QQQQQ. */ +{ "mpyd", 0x2ED87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mpydf<.f> a,b,c 00110bbb00010010FBBBCCCCCCAAAAAA. */ +{ "mpydf", 0x30120000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpydf<.f> 0,b,c 00110bbb00010010FBBBCCCCCC111110. */ +{ "mpydf", 0x3012003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpydf<.f><.cc> b,b,c 00110bbb11010010FBBBCCCCCC0QQQQQ. */ +{ "mpydf", 0x30D20000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpydf<.f> a,b,u6 00110bbb01010010FBBBuuuuuuAAAAAA. */ +{ "mpydf", 0x30520000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpydf<.f> 0,b,u6 00110bbb01010010FBBBuuuuuu111110. */ +{ "mpydf", 0x3052003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpydf<.f><.cc> b,b,u6 00110bbb11010010FBBBuuuuuu1QQQQQ. */ +{ "mpydf", 0x30D20020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpydf<.f> b,b,s12 00110bbb10010010FBBBssssssSSSSSS. */ +{ "mpydf", 0x30920000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpydf<.f> a,limm,c 0011011000010010F111CCCCCCAAAAAA. */ +{ "mpydf", 0x36127000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpydf<.f> a,b,limm 00110bbb00010010FBBB111110AAAAAA. */ +{ "mpydf", 0x30120F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpydf<.f> 0,limm,c 0011011000010010F111CCCCCC111110. */ +{ "mpydf", 0x3612703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpydf<.f> 0,b,limm 00110bbb00010010FBBB111110111110. */ +{ "mpydf", 0x30120FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpydf<.f><.cc> b,b,limm 00110bbb11010010FBBB1111100QQQQQ. */ +{ "mpydf", 0x30D20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpydf<.f><.cc> 0,limm,c 0011011011010010F111CCCCCC0QQQQQ. */ +{ "mpydf", 0x36D27000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mpydf<.f> a,limm,u6 0011011001010010F111uuuuuuAAAAAA. */ +{ "mpydf", 0x36527000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpydf<.f> 0,limm,u6 0011011001010010F111uuuuuu111110. */ +{ "mpydf", 0x3652703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpydf<.f><.cc> 0,limm,u6 0011011011010010F111uuuuuu1QQQQQ. */ +{ "mpydf", 0x36D27020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpydf<.f> 0,limm,s12 0011011010010010F111ssssssSSSSSS. */ +{ "mpydf", 0x36927000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpydf<.f> a,limm,limm 0011011000010010F111111110AAAAAA. */ +{ "mpydf", 0x36127F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpydf<.f> 0,limm,limm 0011011000010010F111111110111110. */ +{ "mpydf", 0x36127FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpydf<.f><.cc> 0,limm,limm 0011011011010010F1111111100QQQQQ. */ +{ "mpydf", 0x36D27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mpydu<.f> a,b,c 00101bbb00011001FBBBCCCCCCAAAAAA. */ +{ "mpydu", 0x28190000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpydu<.f> 0,b,c 00101bbb00011001FBBBCCCCCC111110. */ +{ "mpydu", 0x2819003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpydu<.f><.cc> b,b,c 00101bbb11011001FBBBCCCCCC0QQQQQ. */ +{ "mpydu", 0x28D90000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpydu<.f> a,b,u6 00101bbb01011001FBBBuuuuuuAAAAAA. */ +{ "mpydu", 0x28590000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpydu<.f> 0,b,u6 00101bbb01011001FBBBuuuuuu111110. */ +{ "mpydu", 0x2859003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpydu<.f><.cc> b,b,u6 00101bbb11011001FBBBuuuuuu1QQQQQ. */ +{ "mpydu", 0x28D90020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpydu<.f> b,b,s12 00101bbb10011001FBBBssssssSSSSSS. */ +{ "mpydu", 0x28990000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpydu<.f> a,limm,c 0010111000011001F111CCCCCCAAAAAA. */ +{ "mpydu", 0x2E197000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpydu<.f> a,b,limm 00101bbb00011001FBBB111110AAAAAA. */ +{ "mpydu", 0x28190F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpydu<.f> 0,limm,c 0010111000011001F111CCCCCC111110. */ +{ "mpydu", 0x2E19703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpydu<.f> 0,b,limm 00101bbb00011001FBBB111110111110. */ +{ "mpydu", 0x28190FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpydu<.f><.cc> b,b,limm 00101bbb11011001FBBB1111100QQQQQ. */ +{ "mpydu", 0x28D90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpydu<.f><.cc> 0,limm,c 0010111011011001F111CCCCCC0QQQQQ. */ +{ "mpydu", 0x2ED97000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mpydu<.f> a,limm,u6 0010111001011001F111uuuuuuAAAAAA. */ +{ "mpydu", 0x2E597000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpydu<.f> 0,limm,u6 0010111001011001F111uuuuuu111110. */ +{ "mpydu", 0x2E59703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpydu<.f><.cc> 0,limm,u6 0010111011011001F111uuuuuu1QQQQQ. */ +{ "mpydu", 0x2ED97020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpydu<.f> 0,limm,s12 0010111010011001F111ssssssSSSSSS. */ +{ "mpydu", 0x2E997000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpydu<.f> a,limm,limm 0010111000011001F111111110AAAAAA. */ +{ "mpydu", 0x2E197F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpydu<.f> 0,limm,limm 0010111000011001F111111110111110. */ +{ "mpydu", 0x2E197FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpydu<.f><.cc> 0,limm,limm 0010111011011001F1111111100QQQQQ. */ +{ "mpydu", 0x2ED97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mpyf<.f> a,b,c 00110bbb00001010FBBBCCCCCCAAAAAA. */ +{ "mpyf", 0x300A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpyf<.f> 0,b,c 00110bbb00001010FBBBCCCCCC111110. */ +{ "mpyf", 0x300A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpyf<.f><.cc> b,b,c 00110bbb11001010FBBBCCCCCC0QQQQQ. */ +{ "mpyf", 0x30CA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpyf<.f> a,b,u6 00110bbb01001010FBBBuuuuuuAAAAAA. */ +{ "mpyf", 0x304A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyf<.f> 0,b,u6 00110bbb01001010FBBBuuuuuu111110. */ +{ "mpyf", 0x304A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyf<.f><.cc> b,b,u6 00110bbb11001010FBBBuuuuuu1QQQQQ. */ +{ "mpyf", 0x30CA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpyf<.f> b,b,s12 00110bbb10001010FBBBssssssSSSSSS. */ +{ "mpyf", 0x308A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpyf<.f> a,limm,c 0011011000001010F111CCCCCCAAAAAA. */ +{ "mpyf", 0x360A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpyf<.f> a,b,limm 00110bbb00001010FBBB111110AAAAAA. */ +{ "mpyf", 0x300A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpyf<.f> 0,limm,c 0011011000001010F111CCCCCC111110. */ +{ "mpyf", 0x360A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpyf<.f> 0,b,limm 00110bbb00001010FBBB111110111110. */ +{ "mpyf", 0x300A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpyf<.f><.cc> b,b,limm 00110bbb11001010FBBB1111100QQQQQ. */ +{ "mpyf", 0x30CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpyf<.f><.cc> 0,limm,c 0011011011001010F111CCCCCC0QQQQQ. */ +{ "mpyf", 0x36CA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mpyf<.f> a,limm,u6 0011011001001010F111uuuuuuAAAAAA. */ +{ "mpyf", 0x364A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyf<.f> 0,limm,u6 0011011001001010F111uuuuuu111110. */ +{ "mpyf", 0x364A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyf<.f><.cc> 0,limm,u6 0011011011001010F111uuuuuu1QQQQQ. */ +{ "mpyf", 0x36CA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpyf<.f> 0,limm,s12 0011011010001010F111ssssssSSSSSS. */ +{ "mpyf", 0x368A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpyf<.f> a,limm,limm 0011011000001010F111111110AAAAAA. */ +{ "mpyf", 0x360A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpyf<.f> 0,limm,limm 0011011000001010F111111110111110. */ +{ "mpyf", 0x360A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpyf<.f><.cc> 0,limm,limm 0011011011001010F1111111100QQQQQ. */ +{ "mpyf", 0x36CA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mpyfr<.f> a,b,c 00110bbb00001011FBBBCCCCCCAAAAAA. */ +{ "mpyfr", 0x300B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpyfr<.f> 0,b,c 00110bbb00001011FBBBCCCCCC111110. */ +{ "mpyfr", 0x300B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpyfr<.f><.cc> b,b,c 00110bbb11001011FBBBCCCCCC0QQQQQ. */ +{ "mpyfr", 0x30CB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpyfr<.f> a,b,u6 00110bbb01001011FBBBuuuuuuAAAAAA. */ +{ "mpyfr", 0x304B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyfr<.f> 0,b,u6 00110bbb01001011FBBBuuuuuu111110. */ +{ "mpyfr", 0x304B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyfr<.f><.cc> b,b,u6 00110bbb11001011FBBBuuuuuu1QQQQQ. */ +{ "mpyfr", 0x30CB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpyfr<.f> b,b,s12 00110bbb10001011FBBBssssssSSSSSS. */ +{ "mpyfr", 0x308B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpyfr<.f> a,limm,c 0011011000001011F111CCCCCCAAAAAA. */ +{ "mpyfr", 0x360B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpyfr<.f> a,b,limm 00110bbb00001011FBBB111110AAAAAA. */ +{ "mpyfr", 0x300B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpyfr<.f> 0,limm,c 0011011000001011F111CCCCCC111110. */ +{ "mpyfr", 0x360B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpyfr<.f> 0,b,limm 00110bbb00001011FBBB111110111110. */ +{ "mpyfr", 0x300B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpyfr<.f><.cc> b,b,limm 00110bbb11001011FBBB1111100QQQQQ. */ +{ "mpyfr", 0x30CB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpyfr<.f><.cc> 0,limm,c 0011011011001011F111CCCCCC0QQQQQ. */ +{ "mpyfr", 0x36CB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mpyfr<.f> a,limm,u6 0011011001001011F111uuuuuuAAAAAA. */ +{ "mpyfr", 0x364B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyfr<.f> 0,limm,u6 0011011001001011F111uuuuuu111110. */ +{ "mpyfr", 0x364B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyfr<.f><.cc> 0,limm,u6 0011011011001011F111uuuuuu1QQQQQ. */ +{ "mpyfr", 0x36CB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpyfr<.f> 0,limm,s12 0011011010001011F111ssssssSSSSSS. */ +{ "mpyfr", 0x368B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpyfr<.f> a,limm,limm 0011011000001011F111111110AAAAAA. */ +{ "mpyfr", 0x360B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpyfr<.f> 0,limm,limm 0011011000001011F111111110111110. */ +{ "mpyfr", 0x360B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpyfr<.f><.cc> 0,limm,limm 0011011011001011F1111111100QQQQQ. */ +{ "mpyfr", 0x36CB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mpyh<.f> a,b,c 00100bbb00011011FBBBCCCCCCAAAAAA. */ +{ "mpyh", 0x201B0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpyh<.f> 0,b,c 00100bbb00011011FBBBCCCCCC111110. */ +{ "mpyh", 0x201B003E, 0xF8FF003F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpyh<.f><.cc> b,b,c 00100bbb11011011FBBBCCCCCC0QQQQQ. */ +{ "mpyh", 0x20DB0000, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpyh<.f> a,b,u6 00100bbb01011011FBBBuuuuuuAAAAAA. */ +{ "mpyh", 0x205B0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyh<.f> 0,b,u6 00100bbb01011011FBBBuuuuuu111110. */ +{ "mpyh", 0x205B003E, 0xF8FF003F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyh<.f><.cc> b,b,u6 00100bbb11011011FBBBuuuuuu1QQQQQ. */ +{ "mpyh", 0x20DB0020, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpyh<.f> b,b,s12 00100bbb10011011FBBBssssssSSSSSS. */ +{ "mpyh", 0x209B0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpyh<.f> a,limm,c 0010011000011011F111CCCCCCAAAAAA. */ +{ "mpyh", 0x261B7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpyh<.f> a,b,limm 00100bbb00011011FBBB111110AAAAAA. */ +{ "mpyh", 0x201B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpyh<.f> 0,limm,c 0010011000011011F111CCCCCC111110. */ +{ "mpyh", 0x261B703E, 0xFFFF703F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpyh<.f> 0,b,limm 00100bbb00011011FBBB111110111110. */ +{ "mpyh", 0x201B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpyh<.f><.cc> b,b,limm 00100bbb11011011FBBB1111100QQQQQ. */ +{ "mpyh", 0x20DB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpyh<.f><.cc> 0,limm,c 0010011011011011F111CCCCCC0QQQQQ. */ +{ "mpyh", 0x26DB7000, 0xFFFF7020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mpyh<.f> a,limm,u6 0010011001011011F111uuuuuuAAAAAA. */ +{ "mpyh", 0x265B7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyh<.f> 0,limm,u6 0010011001011011F111uuuuuu111110. */ +{ "mpyh", 0x265B703E, 0xFFFF703F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyh<.f><.cc> 0,limm,u6 0010011011011011F111uuuuuu1QQQQQ. */ +{ "mpyh", 0x26DB7020, 0xFFFF7020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpyh<.f> 0,limm,s12 0010011010011011F111ssssssSSSSSS. */ +{ "mpyh", 0x269B7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpyh<.f> a,limm,limm 0010011000011011F111111110AAAAAA. */ +{ "mpyh", 0x261B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpyh<.f> 0,limm,limm 0010011000011011F111111110111110. */ +{ "mpyh", 0x261B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpyh<.f><.cc> 0,limm,limm 0010011011011011F1111111100QQQQQ. */ +{ "mpyh", 0x26DB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mpyhu<.f> a,b,c 00100bbb00011100FBBBCCCCCCAAAAAA. */ +{ "mpyhu", 0x201C0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpyhu<.f> 0,b,c 00100bbb00011100FBBBCCCCCC111110. */ +{ "mpyhu", 0x201C003E, 0xF8FF003F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpyhu<.f><.cc> b,b,c 00100bbb11011100FBBBCCCCCC0QQQQQ. */ +{ "mpyhu", 0x20DC0000, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpyhu<.f> a,b,u6 00100bbb01011100FBBBuuuuuuAAAAAA. */ +{ "mpyhu", 0x205C0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyhu<.f> 0,b,u6 00100bbb01011100FBBBuuuuuu111110. */ +{ "mpyhu", 0x205C003E, 0xF8FF003F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyhu<.f><.cc> b,b,u6 00100bbb11011100FBBBuuuuuu1QQQQQ. */ +{ "mpyhu", 0x20DC0020, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpyhu<.f> b,b,s12 00100bbb10011100FBBBssssssSSSSSS. */ +{ "mpyhu", 0x209C0000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpyhu<.f> a,limm,c 0010011000011100F111CCCCCCAAAAAA. */ +{ "mpyhu", 0x261C7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpyhu<.f> a,b,limm 00100bbb00011100FBBB111110AAAAAA. */ +{ "mpyhu", 0x201C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpyhu<.f> 0,limm,c 0010011000011100F111CCCCCC111110. */ +{ "mpyhu", 0x261C703E, 0xFFFF703F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpyhu<.f> 0,b,limm 00100bbb00011100FBBB111110111110. */ +{ "mpyhu", 0x201C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpyhu<.f><.cc> b,b,limm 00100bbb11011100FBBB1111100QQQQQ. */ +{ "mpyhu", 0x20DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpyhu<.f><.cc> 0,limm,c 0010011011011100F111CCCCCC0QQQQQ. */ +{ "mpyhu", 0x26DC7000, 0xFFFF7020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mpyhu<.f> a,limm,u6 0010011001011100F111uuuuuuAAAAAA. */ +{ "mpyhu", 0x265C7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyhu<.f> 0,limm,u6 0010011001011100F111uuuuuu111110. */ +{ "mpyhu", 0x265C703E, 0xFFFF703F, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyhu<.f><.cc> 0,limm,u6 0010011011011100F111uuuuuu1QQQQQ. */ +{ "mpyhu", 0x26DC7020, 0xFFFF7020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpyhu<.f> 0,limm,s12 0010011010011100F111ssssssSSSSSS. */ +{ "mpyhu", 0x269C7000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpyhu<.f> a,limm,limm 0010011000011100F111111110AAAAAA. */ +{ "mpyhu", 0x261C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpyhu<.f> 0,limm,limm 0010011000011100F111111110111110. */ +{ "mpyhu", 0x261C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpyhu<.f><.cc> 0,limm,limm 0010011011011100F1111111100QQQQQ. */ +{ "mpyhu", 0x26DC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mpym<.f> a,b,c 00100bbb00011011FBBBCCCCCCAAAAAA. */ +{ "mpym", 0x201B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpym<.f> 0,b,c 00100bbb00011011FBBBCCCCCC111110. */ +{ "mpym", 0x201B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpym<.f><.cc> b,b,c 00100bbb11011011FBBBCCCCCC0QQQQQ. */ +{ "mpym", 0x20DB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpym<.f> a,b,u6 00100bbb01011011FBBBuuuuuuAAAAAA. */ +{ "mpym", 0x205B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpym<.f> 0,b,u6 00100bbb01011011FBBBuuuuuu111110. */ +{ "mpym", 0x205B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpym<.f><.cc> b,b,u6 00100bbb11011011FBBBuuuuuu1QQQQQ. */ +{ "mpym", 0x20DB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpym<.f> b,b,s12 00100bbb10011011FBBBssssssSSSSSS. */ +{ "mpym", 0x209B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpym<.f> a,limm,c 0010011000011011F111CCCCCCAAAAAA. */ +{ "mpym", 0x261B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpym<.f> a,b,limm 00100bbb00011011FBBB111110AAAAAA. */ +{ "mpym", 0x201B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpym<.f> 0,limm,c 0010011000011011F111CCCCCC111110. */ +{ "mpym", 0x261B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpym<.f> 0,b,limm 00100bbb00011011FBBB111110111110. */ +{ "mpym", 0x201B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpym<.f><.cc> b,b,limm 00100bbb11011011FBBB1111100QQQQQ. */ +{ "mpym", 0x20DB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpym<.f><.cc> 0,limm,c 0010011011011011F111CCCCCC0QQQQQ. */ +{ "mpym", 0x26DB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mpym<.f> a,limm,u6 0010011001011011F111uuuuuuAAAAAA. */ +{ "mpym", 0x265B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpym<.f> 0,limm,u6 0010011001011011F111uuuuuu111110. */ +{ "mpym", 0x265B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpym<.f><.cc> 0,limm,u6 0010011011011011F111uuuuuu1QQQQQ. */ +{ "mpym", 0x26DB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpym<.f> 0,limm,s12 0010011010011011F111ssssssSSSSSS. */ +{ "mpym", 0x269B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpym<.f> a,limm,limm 0010011000011011F111111110AAAAAA. */ +{ "mpym", 0x261B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpym<.f> 0,limm,limm 0010011000011011F111111110111110. */ +{ "mpym", 0x261B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpym<.f><.cc> 0,limm,limm 0010011011011011F1111111100QQQQQ. */ +{ "mpym", 0x26DB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mpymu<.f> a,b,c 00100bbb00011100FBBBCCCCCCAAAAAA. */ +{ "mpymu", 0x201C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpymu<.f> 0,b,c 00100bbb00011100FBBBCCCCCC111110. */ +{ "mpymu", 0x201C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpymu<.f><.cc> b,b,c 00100bbb11011100FBBBCCCCCC0QQQQQ. */ +{ "mpymu", 0x20DC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpymu<.f> a,b,u6 00100bbb01011100FBBBuuuuuuAAAAAA. */ +{ "mpymu", 0x205C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpymu<.f> 0,b,u6 00100bbb01011100FBBBuuuuuu111110. */ +{ "mpymu", 0x205C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpymu<.f><.cc> b,b,u6 00100bbb11011100FBBBuuuuuu1QQQQQ. */ +{ "mpymu", 0x20DC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpymu<.f> b,b,s12 00100bbb10011100FBBBssssssSSSSSS. */ +{ "mpymu", 0x209C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpymu<.f> a,limm,c 0010011000011100F111CCCCCCAAAAAA. */ +{ "mpymu", 0x261C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpymu<.f> a,b,limm 00100bbb00011100FBBB111110AAAAAA. */ +{ "mpymu", 0x201C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpymu<.f> 0,limm,c 0010011000011100F111CCCCCC111110. */ +{ "mpymu", 0x261C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpymu<.f> 0,b,limm 00100bbb00011100FBBB111110111110. */ +{ "mpymu", 0x201C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpymu<.f><.cc> b,b,limm 00100bbb11011100FBBB1111100QQQQQ. */ +{ "mpymu", 0x20DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpymu<.f><.cc> 0,limm,c 0010011011011100F111CCCCCC0QQQQQ. */ +{ "mpymu", 0x26DC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mpymu<.f> a,limm,u6 0010011001011100F111uuuuuuAAAAAA. */ +{ "mpymu", 0x265C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpymu<.f> 0,limm,u6 0010011001011100F111uuuuuu111110. */ +{ "mpymu", 0x265C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpymu<.f><.cc> 0,limm,u6 0010011011011100F111uuuuuu1QQQQQ. */ +{ "mpymu", 0x26DC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpymu<.f> 0,limm,s12 0010011010011100F111ssssssSSSSSS. */ +{ "mpymu", 0x269C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpymu<.f> a,limm,limm 0010011000011100F111111110AAAAAA. */ +{ "mpymu", 0x261C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpymu<.f> 0,limm,limm 0010011000011100F111111110111110. */ +{ "mpymu", 0x261C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpymu<.f><.cc> 0,limm,limm 0010011011011100F1111111100QQQQQ. */ +{ "mpymu", 0x26DC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mpyqb<.f><.cc> b,b,c 00110bbb11100101FBBBCCCCCC0QQQQQ. */ +{ "mpyqb", 0x30E50000, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpyqb<.f> a,b,u6 00110bbb01100101FBBBuuuuuuAAAAAA. */ +{ "mpyqb", 0x30650000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyqb<.f><.cc> b,b,u6 00110bbb11100101FBBBuuuuuu1QQQQQ. */ +{ "mpyqb", 0x30E50020, 0xF8FF0020, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpyqb<.f> b,b,s12 00110bbb10100101FBBBssssssSSSSSS. */ +{ "mpyqb", 0x30A50000, 0xF8FF0000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpyqb<.f> a,limm,c 0011011000100101F111CCCCCCAAAAAA. */ +{ "mpyqb", 0x36257000, 0xFFFF7000, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpyqb<.f> a,b,limm 00110bbb00100101FBBB111110AAAAAA. */ +{ "mpyqb", 0x30250F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpyqb<.f><.cc> b,b,limm 00110bbb11100101FBBB1111100QQQQQ. */ +{ "mpyqb", 0x30E50F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpyu<.f> a,b,c 00100bbb00011101FBBBCCCCCCAAAAAA. */ +{ "mpyu", 0x201D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpyu<.f> 0,b,c 00100bbb00011101FBBBCCCCCC111110. */ +{ "mpyu", 0x201D003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpyu<.f><.cc> b,b,c 00100bbb11011101FBBBCCCCCC0QQQQQ. */ +{ "mpyu", 0x20DD0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpyu<.f> a,b,u6 00100bbb01011101FBBBuuuuuuAAAAAA. */ +{ "mpyu", 0x205D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyu<.f> 0,b,u6 00100bbb01011101FBBBuuuuuu111110. */ +{ "mpyu", 0x205D003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyu<.f><.cc> b,b,u6 00100bbb11011101FBBBuuuuuu1QQQQQ. */ +{ "mpyu", 0x20DD0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpyu<.f> b,b,s12 00100bbb10011101FBBBssssssSSSSSS. */ +{ "mpyu", 0x209D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpyu<.f> a,limm,c 0010011000011101F111CCCCCCAAAAAA. */ +{ "mpyu", 0x261D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpyu<.f> a,b,limm 00100bbb00011101FBBB111110AAAAAA. */ +{ "mpyu", 0x201D0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpyu<.f> 0,limm,c 0010011000011101F111CCCCCC111110. */ +{ "mpyu", 0x261D703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpyu<.f> 0,b,limm 00100bbb00011101FBBB111110111110. */ +{ "mpyu", 0x201D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpyu<.f><.cc> b,b,limm 00100bbb11011101FBBB1111100QQQQQ. */ +{ "mpyu", 0x20DD0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpyu<.f><.cc> 0,limm,c 0010011011011101F111CCCCCC0QQQQQ. */ +{ "mpyu", 0x26DD7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mpyu<.f> a,limm,u6 0010011001011101F111uuuuuuAAAAAA. */ +{ "mpyu", 0x265D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyu<.f> 0,limm,u6 0010011001011101F111uuuuuu111110. */ +{ "mpyu", 0x265D703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyu<.f><.cc> 0,limm,u6 0010011011011101F111uuuuuu1QQQQQ. */ +{ "mpyu", 0x26DD7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpyu<.f> 0,limm,s12 0010011010011101F111ssssssSSSSSS. */ +{ "mpyu", 0x269D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpyu<.f> a,limm,limm 0010011000011101F111111110AAAAAA. */ +{ "mpyu", 0x261D7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpyu<.f> 0,limm,limm 0010011000011101F111111110111110. */ +{ "mpyu", 0x261D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpyu<.f><.cc> 0,limm,limm 0010011011011101F1111111100QQQQQ. */ +{ "mpyu", 0x26DD7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mpyuw<.f> a,b,c 00100bbb00111111FBBBCCCCCCAAAAAA. */ +{ "mpyuw", 0x203F0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpyuw<.f> 0,b,c 00100bbb00111111FBBBCCCCCC111110. */ +{ "mpyuw", 0x203F003E, 0xF8FF003F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpyuw<.f><.cc> b,b,c 00100bbb11111111FBBBCCCCCC0QQQQQ. */ +{ "mpyuw", 0x20FF0000, 0xF8FF0020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpyuw<.f> a,b,c 00100bbb00011111FBBBCCCCCCAAAAAA. */ +{ "mpyuw", 0x201F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpyuw<.f> 0,b,c 00100bbb00011111FBBBCCCCCC111110. */ +{ "mpyuw", 0x201F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpyuw<.f><.cc> b,b,c 00100bbb11011111FBBBCCCCCC0QQQQQ. */ +{ "mpyuw", 0x20DF0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpyuw<.f> a,b,u6 00100bbb01111111FBBBuuuuuuAAAAAA. */ +{ "mpyuw", 0x207F0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyuw<.f> 0,b,u6 00100bbb01111111FBBBuuuuuu111110. */ +{ "mpyuw", 0x207F003E, 0xF8FF003F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyuw<.f><.cc> b,b,u6 00100bbb11111111FBBBuuuuuu1QQQQQ. */ +{ "mpyuw", 0x20FF0020, 0xF8FF0020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpyuw<.f> a,b,u6 00100bbb01011111FBBBuuuuuuAAAAAA. */ +{ "mpyuw", 0x205F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyuw<.f> 0,b,u6 00100bbb01011111FBBBuuuuuu111110. */ +{ "mpyuw", 0x205F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyuw<.f><.cc> b,b,u6 00100bbb11011111FBBBuuuuuu1QQQQQ. */ +{ "mpyuw", 0x20DF0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpyuw<.f> b,b,s12 00100bbb10111111FBBBssssssSSSSSS. */ +{ "mpyuw", 0x20BF0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpyuw<.f> b,b,s12 00100bbb10011111FBBBssssssSSSSSS. */ +{ "mpyuw", 0x209F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpyuw<.f> a,limm,c 0010011000111111F111CCCCCCAAAAAA. */ +{ "mpyuw", 0x263F7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpyuw<.f> a,b,limm 00100bbb00111111FBBB111110AAAAAA. */ +{ "mpyuw", 0x203F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpyuw<.f> 0,limm,c 0010011000111111F111CCCCCC111110. */ +{ "mpyuw", 0x263F703E, 0xFFFF703F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpyuw<.f> 0,b,limm 00100bbb00111111FBBB111110111110. */ +{ "mpyuw", 0x203F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpyuw<.f><.cc> b,b,limm 00100bbb11111111FBBB1111100QQQQQ. */ +{ "mpyuw", 0x20FF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpyuw<.f><.cc> 0,limm,c 0010011011111111F111CCCCCC0QQQQQ. */ +{ "mpyuw", 0x26FF7000, 0xFFFF7020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mpyuw<.f> a,limm,c 0010011000011111F111CCCCCCAAAAAA. */ +{ "mpyuw", 0x261F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpyuw<.f> a,b,limm 00100bbb00011111FBBB111110AAAAAA. */ +{ "mpyuw", 0x201F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpyuw<.f> 0,limm,c 0010011000011111F111CCCCCC111110. */ +{ "mpyuw", 0x261F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpyuw<.f> 0,b,limm 00100bbb00011111FBBB111110111110. */ +{ "mpyuw", 0x201F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpyuw<.f><.cc> b,b,limm 00100bbb11011111FBBB1111100QQQQQ. */ +{ "mpyuw", 0x20DF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpyuw<.f><.cc> 0,limm,c 0010011011011111F111CCCCCC0QQQQQ. */ +{ "mpyuw", 0x26DF7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mpyuw<.f> a,limm,u6 0010011001111111F111uuuuuuAAAAAA. */ +{ "mpyuw", 0x267F7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyuw<.f> 0,limm,u6 0010011001111111F111uuuuuu111110. */ +{ "mpyuw", 0x267F703E, 0xFFFF703F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyuw<.f><.cc> 0,limm,u6 0010011011111111F111uuuuuu1QQQQQ. */ +{ "mpyuw", 0x26FF7020, 0xFFFF7020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpyuw<.f> a,limm,u6 0010011001011111F111uuuuuuAAAAAA. */ +{ "mpyuw", 0x265F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyuw<.f> 0,limm,u6 0010011001011111F111uuuuuu111110. */ +{ "mpyuw", 0x265F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyuw<.f><.cc> 0,limm,u6 0010011011011111F111uuuuuu1QQQQQ. */ +{ "mpyuw", 0x26DF7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpyuw<.f> 0,limm,s12 0010011010111111F111ssssssSSSSSS. */ +{ "mpyuw", 0x26BF7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpyuw<.f> 0,limm,s12 0010011010011111F111ssssssSSSSSS. */ +{ "mpyuw", 0x269F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpyuw<.f> a,limm,limm 0010011000111111F111111110AAAAAA. */ +{ "mpyuw", 0x263F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpyuw<.f> 0,limm,limm 0010011000111111F111111110111110. */ +{ "mpyuw", 0x263F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpyuw<.f><.cc> 0,limm,limm 0010011011111111F1111111100QQQQQ. */ +{ "mpyuw", 0x26FF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mpyuw<.f> a,limm,limm 0010011000011111F111111110AAAAAA. */ +{ "mpyuw", 0x261F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpyuw<.f> 0,limm,limm 0010011000011111F111111110111110. */ +{ "mpyuw", 0x261F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpyuw<.f><.cc> 0,limm,limm 0010011011011111F1111111100QQQQQ. */ +{ "mpyuw", 0x26DF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mpyuw_s b,b,c 01111bbbccc01010. */ +{ "mpyuw_s", 0x0000780A, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, + +/* mpyw<.f> a,b,c 00100bbb00111110FBBBCCCCCCAAAAAA. */ +{ "mpyw", 0x203E0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpyw<.f> 0,b,c 00100bbb00111110FBBBCCCCCC111110. */ +{ "mpyw", 0x203E003E, 0xF8FF003F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpyw<.f><.cc> b,b,c 00100bbb11111110FBBBCCCCCC0QQQQQ. */ +{ "mpyw", 0x20FE0000, 0xF8FF0020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpyw<.f> a,b,c 00100bbb00011110FBBBCCCCCCAAAAAA. */ +{ "mpyw", 0x201E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpyw<.f> 0,b,c 00100bbb00011110FBBBCCCCCC111110. */ +{ "mpyw", 0x201E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpyw<.f><.cc> b,b,c 00100bbb11011110FBBBCCCCCC0QQQQQ. */ +{ "mpyw", 0x20DE0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpyw<.f> a,b,u6 00100bbb01111110FBBBuuuuuuAAAAAA. */ +{ "mpyw", 0x207E0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyw<.f> 0,b,u6 00100bbb01111110FBBBuuuuuu111110. */ +{ "mpyw", 0x207E003E, 0xF8FF003F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyw<.f><.cc> b,b,u6 00100bbb11111110FBBBuuuuuu1QQQQQ. */ +{ "mpyw", 0x20FE0020, 0xF8FF0020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpyw<.f> a,b,u6 00100bbb01011110FBBBuuuuuuAAAAAA. */ +{ "mpyw", 0x205E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyw<.f> 0,b,u6 00100bbb01011110FBBBuuuuuu111110. */ +{ "mpyw", 0x205E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyw<.f><.cc> b,b,u6 00100bbb11011110FBBBuuuuuu1QQQQQ. */ +{ "mpyw", 0x20DE0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpyw<.f> b,b,s12 00100bbb10111110FBBBssssssSSSSSS. */ +{ "mpyw", 0x20BE0000, 0xF8FF0000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpyw<.f> b,b,s12 00100bbb10011110FBBBssssssSSSSSS. */ +{ "mpyw", 0x209E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpyw<.f> a,limm,c 0010011000111110F111CCCCCCAAAAAA. */ +{ "mpyw", 0x263E7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpyw<.f> a,b,limm 00100bbb00111110FBBB111110AAAAAA. */ +{ "mpyw", 0x203E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpyw<.f> 0,limm,c 0010011000111110F111CCCCCC111110. */ +{ "mpyw", 0x263E703E, 0xFFFF703F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpyw<.f> 0,b,limm 00100bbb00111110FBBB111110111110. */ +{ "mpyw", 0x203E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpyw<.f><.cc> b,b,limm 00100bbb11111110FBBB1111100QQQQQ. */ +{ "mpyw", 0x20FE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpyw<.f><.cc> 0,limm,c 0010011011111110F111CCCCCC0QQQQQ. */ +{ "mpyw", 0x26FE7000, 0xFFFF7020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mpyw<.f> a,limm,c 0010011000011110F111CCCCCCAAAAAA. */ +{ "mpyw", 0x261E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpyw<.f> a,b,limm 00100bbb00011110FBBB111110AAAAAA. */ +{ "mpyw", 0x201E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpyw<.f> 0,limm,c 0010011000011110F111CCCCCC111110. */ +{ "mpyw", 0x261E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpyw<.f> 0,b,limm 00100bbb00011110FBBB111110111110. */ +{ "mpyw", 0x201E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpyw<.f><.cc> b,b,limm 00100bbb11011110FBBB1111100QQQQQ. */ +{ "mpyw", 0x20DE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpyw<.f><.cc> 0,limm,c 0010011011011110F111CCCCCC0QQQQQ. */ +{ "mpyw", 0x26DE7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mpyw<.f> a,limm,u6 0010011001111110F111uuuuuuAAAAAA. */ +{ "mpyw", 0x267E7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyw<.f> 0,limm,u6 0010011001111110F111uuuuuu111110. */ +{ "mpyw", 0x267E703E, 0xFFFF703F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyw<.f><.cc> 0,limm,u6 0010011011111110F111uuuuuu1QQQQQ. */ +{ "mpyw", 0x26FE7020, 0xFFFF7020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpyw<.f> a,limm,u6 0010011001011110F111uuuuuuAAAAAA. */ +{ "mpyw", 0x265E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyw<.f> 0,limm,u6 0010011001011110F111uuuuuu111110. */ +{ "mpyw", 0x265E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpyw<.f><.cc> 0,limm,u6 0010011011011110F111uuuuuu1QQQQQ. */ +{ "mpyw", 0x26DE7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpyw<.f> 0,limm,s12 0010011010111110F111ssssssSSSSSS. */ +{ "mpyw", 0x26BE7000, 0xFFFF7000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpyw<.f> 0,limm,s12 0010011010011110F111ssssssSSSSSS. */ +{ "mpyw", 0x269E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpyw<.f> a,limm,limm 0010011000111110F111111110AAAAAA. */ +{ "mpyw", 0x263E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpyw<.f> 0,limm,limm 0010011000111110F111111110111110. */ +{ "mpyw", 0x263E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpyw<.f><.cc> 0,limm,limm 0010011011111110F1111111100QQQQQ. */ +{ "mpyw", 0x26FE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mpyw<.f> a,limm,limm 0010011000011110F111111110AAAAAA. */ +{ "mpyw", 0x261E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpyw<.f> 0,limm,limm 0010011000011110F111111110111110. */ +{ "mpyw", 0x261E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpyw<.f><.cc> 0,limm,limm 0010011011011110F1111111100QQQQQ. */ +{ "mpyw", 0x26DE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mpywhfl<.f> a,b,c 00110bbb00100100FBBBCCCCCCAAAAAA. */ +{ "mpywhfl", 0x30240000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpywhfl<.f> 0,b,c 00110bbb00100100FBBBCCCCCC111110. */ +{ "mpywhfl", 0x3024003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpywhfl<.f><.cc> b,b,c 00110bbb11100100FBBBCCCCCC0QQQQQ. */ +{ "mpywhfl", 0x30E40000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpywhfl<.f> a,b,u6 00110bbb01100100FBBBuuuuuuAAAAAA. */ +{ "mpywhfl", 0x30640000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhfl<.f> 0,b,u6 00110bbb01100100FBBBuuuuuu111110. */ +{ "mpywhfl", 0x3064003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhfl<.f><.cc> b,b,u6 00110bbb11100100FBBBuuuuuu1QQQQQ. */ +{ "mpywhfl", 0x30E40020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhfl<.f> b,b,s12 00110bbb10100100FBBBssssssSSSSSS. */ +{ "mpywhfl", 0x30A40000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpywhfl<.f> a,limm,c 0011011000100100F111CCCCCCAAAAAA. */ +{ "mpywhfl", 0x36247000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpywhfl<.f> a,b,limm 00110bbb00100100FBBB111110AAAAAA. */ +{ "mpywhfl", 0x30240F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpywhfl<.f> 0,limm,c 0011011001100100F111CCCCCC111110. */ +{ "mpywhfl", 0x3664703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpywhfl<.f> 0,b,limm 00110bbb00100100FBBB111110111110. */ +{ "mpywhfl", 0x30240FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpywhfl<.f><.cc> 0,limm,c 00110bbb11100100FBBB1111100QQQQQ. */ +{ "mpywhfl", 0x30E40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mpywhfl<.f><.cc> b,b,limm 0011011011100100F111CCCCCC0QQQQQ. */ +{ "mpywhfl", 0x36E47000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpywhfl<.f> a,limm,u6 0011011001100100F111uuuuuuAAAAAA. */ +{ "mpywhfl", 0x36647000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhfl<.f> 0,limm,u6 0011011001100100F111uuuuuu111110. */ +{ "mpywhfl", 0x3664703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhfl<.f><.cc> 0,limm,u6 0011011011100100F111uuuuuu1QQQQQ. */ +{ "mpywhfl", 0x36E47020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhfl<.f> 0,limm,s12 0011011010100100F111ssssssSSSSSS. */ +{ "mpywhfl", 0x36A47000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpywhfl<.f> a,limm,limm 0011011000100100F111111110AAAAAA. */ +{ "mpywhfl", 0x36247F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpywhfl<.f> 0,limm,limm 0011011000100100F111111110111110. */ +{ "mpywhfl", 0x36247FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpywhfl<.f><.cc> 0,limm,limm 0011011011100100F1111111100QQQQQ. */ +{ "mpywhfl", 0x36E47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mpywhflr<.f> a,b,c 00110bbb00100101FBBBCCCCCCAAAAAA. */ +{ "mpywhflr", 0x30250000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpywhflr<.f> 0,b,c 00110bbb00100101FBBBCCCCCC111110. */ +{ "mpywhflr", 0x3025003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpywhflr<.f><.cc> b,b,c 00110bbb11100101FBBBCCCCCC0QQQQQ. */ +{ "mpywhflr", 0x30E50000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpywhflr<.f> a,b,u6 00110bbb01100101FBBBuuuuuuAAAAAA. */ +{ "mpywhflr", 0x30650000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhflr<.f> 0,b,u6 00110bbb01100101FBBBuuuuuu111110. */ +{ "mpywhflr", 0x3065003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhflr<.f><.cc> b,b,u6 00110bbb11100101FBBBuuuuuu1QQQQQ. */ +{ "mpywhflr", 0x30E50020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhflr<.f> b,b,s12 00110bbb10100101FBBBssssssSSSSSS. */ +{ "mpywhflr", 0x30A50000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpywhflr<.f> a,limm,c 0011011000100101F111CCCCCCAAAAAA. */ +{ "mpywhflr", 0x36257000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpywhflr<.f> a,b,limm 00110bbb00100101FBBB111110AAAAAA. */ +{ "mpywhflr", 0x30250F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpywhflr<.f> 0,limm,c 0011011001100101F111CCCCCC111110. */ +{ "mpywhflr", 0x3665703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpywhflr<.f> 0,b,limm 00110bbb00100101FBBB111110111110. */ +{ "mpywhflr", 0x30250FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpywhflr<.f><.cc> 0,limm,c 00110bbb11100101FBBB1111100QQQQQ. */ +{ "mpywhflr", 0x30E50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mpywhflr<.f><.cc> b,b,limm 0011011011100101F111CCCCCC0QQQQQ. */ +{ "mpywhflr", 0x36E57000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpywhflr<.f> a,limm,u6 0011011001100101F111uuuuuuAAAAAA. */ +{ "mpywhflr", 0x36657000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhflr<.f> 0,limm,u6 0011011001100101F111uuuuuu111110. */ +{ "mpywhflr", 0x3665703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhflr<.f><.cc> 0,limm,u6 0011011011100101F111uuuuuu1QQQQQ. */ +{ "mpywhflr", 0x36E57020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhflr<.f> 0,limm,s12 0011011010100101F111ssssssSSSSSS. */ +{ "mpywhflr", 0x36A57000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpywhflr<.f> a,limm,limm 0011011000100101F111111110AAAAAA. */ +{ "mpywhflr", 0x36257F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpywhflr<.f> 0,limm,limm 0011011000100101F111111110111110. */ +{ "mpywhflr", 0x36257FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpywhflr<.f><.cc> 0,limm,limm 0011011011100101F1111111100QQQQQ. */ +{ "mpywhflr", 0x36E57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mpywhfm<.f> a,b,c 00110bbb00100000FBBBCCCCCCAAAAAA. */ +{ "mpywhfm", 0x30200000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpywhfm<.f> 0,b,c 00110bbb00100000FBBBCCCCCC111110. */ +{ "mpywhfm", 0x3020003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpywhfm<.f><.cc> b,b,c 00110bbb11100000FBBBCCCCCC0QQQQQ. */ +{ "mpywhfm", 0x30E00000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpywhfm<.f> a,b,u6 00110bbb01100000FBBBuuuuuuAAAAAA. */ +{ "mpywhfm", 0x30600000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhfm<.f> 0,b,u6 00110bbb01100000FBBBuuuuuu111110. */ +{ "mpywhfm", 0x3060003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhfm<.f><.cc> b,b,u6 00110bbb11100000FBBBuuuuuu1QQQQQ. */ +{ "mpywhfm", 0x30E00020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhfm<.f> b,b,s12 00110bbb10100000FBBBssssssSSSSSS. */ +{ "mpywhfm", 0x30A00000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpywhfm<.f> a,limm,c 0011011000100000F111CCCCCCAAAAAA. */ +{ "mpywhfm", 0x36207000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpywhfm<.f> a,b,limm 00110bbb00100000FBBB111110AAAAAA. */ +{ "mpywhfm", 0x30200F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpywhfm<.f> 0,limm,c 0011011001100000F111CCCCCC111110. */ +{ "mpywhfm", 0x3660703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpywhfm<.f> 0,b,limm 00110bbb00100000FBBB111110111110. */ +{ "mpywhfm", 0x30200FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpywhfm<.f><.cc> 0,limm,c 00110bbb11100000FBBB1111100QQQQQ. */ +{ "mpywhfm", 0x30E00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mpywhfm<.f><.cc> b,b,limm 0011011011100000F111CCCCCC0QQQQQ. */ +{ "mpywhfm", 0x36E07000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpywhfm<.f> a,limm,u6 0011011001100000F111uuuuuuAAAAAA. */ +{ "mpywhfm", 0x36607000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhfm<.f> 0,limm,u6 0011011001100000F111uuuuuu111110. */ +{ "mpywhfm", 0x3660703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhfm<.f><.cc> 0,limm,u6 0011011011100000F111uuuuuu1QQQQQ. */ +{ "mpywhfm", 0x36E07020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhfm<.f> 0,limm,s12 0011011010100000F111ssssssSSSSSS. */ +{ "mpywhfm", 0x36A07000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpywhfm<.f> a,limm,limm 0011011000100000F111111110AAAAAA. */ +{ "mpywhfm", 0x36207F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpywhfm<.f> 0,limm,limm 0011011000100000F111111110111110. */ +{ "mpywhfm", 0x36207FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpywhfm<.f><.cc> 0,limm,limm 0011011011100000F1111111100QQQQQ. */ +{ "mpywhfm", 0x36E07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mpywhfmr<.f> a,b,c 00110bbb00100001FBBBCCCCCCAAAAAA. */ +{ "mpywhfmr", 0x30210000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpywhfmr<.f> 0,b,c 00110bbb00100001FBBBCCCCCC111110. */ +{ "mpywhfmr", 0x3021003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpywhfmr<.f><.cc> b,b,c 00110bbb11100001FBBBCCCCCC0QQQQQ. */ +{ "mpywhfmr", 0x30E10000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpywhfmr<.f> a,b,u6 00110bbb01100001FBBBuuuuuuAAAAAA. */ +{ "mpywhfmr", 0x30610000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhfmr<.f> 0,b,u6 00110bbb01100001FBBBuuuuuu111110. */ +{ "mpywhfmr", 0x3061003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhfmr<.f><.cc> b,b,u6 00110bbb11100001FBBBuuuuuu1QQQQQ. */ +{ "mpywhfmr", 0x30E10020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhfmr<.f> b,b,s12 00110bbb10100001FBBBssssssSSSSSS. */ +{ "mpywhfmr", 0x30A10000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpywhfmr<.f> a,limm,c 0011011000100001F111CCCCCCAAAAAA. */ +{ "mpywhfmr", 0x36217000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpywhfmr<.f> a,b,limm 00110bbb00100001FBBB111110AAAAAA. */ +{ "mpywhfmr", 0x30210F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpywhfmr<.f> 0,limm,c 0011011001100001F111CCCCCC111110. */ +{ "mpywhfmr", 0x3661703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpywhfmr<.f> 0,b,limm 00110bbb00100001FBBB111110111110. */ +{ "mpywhfmr", 0x30210FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpywhfmr<.f><.cc> 0,limm,c 00110bbb11100001FBBB1111100QQQQQ. */ +{ "mpywhfmr", 0x30E10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mpywhfmr<.f><.cc> b,b,limm 0011011011100001F111CCCCCC0QQQQQ. */ +{ "mpywhfmr", 0x36E17000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpywhfmr<.f> a,limm,u6 0011011001100001F111uuuuuuAAAAAA. */ +{ "mpywhfmr", 0x36617000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhfmr<.f> 0,limm,u6 0011011001100001F111uuuuuu111110. */ +{ "mpywhfmr", 0x3661703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhfmr<.f><.cc> 0,limm,u6 0011011011100001F111uuuuuu1QQQQQ. */ +{ "mpywhfmr", 0x36E17020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhfmr<.f> 0,limm,s12 0011011010100001F111ssssssSSSSSS. */ +{ "mpywhfmr", 0x36A17000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpywhfmr<.f> a,limm,limm 0011011000100001F111111110AAAAAA. */ +{ "mpywhfmr", 0x36217F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpywhfmr<.f> 0,limm,limm 0011011000100001F111111110111110. */ +{ "mpywhfmr", 0x36217FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpywhfmr<.f><.cc> 0,limm,limm 0011011011100001F1111111100QQQQQ. */ +{ "mpywhfmr", 0x36E17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mpywhkl<.f><.cc> b,b,c 00110bbb11101010FBBBCCCCCC0QQQQQ */ +{ "mpywhkl", 0x30EA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpywhkl<.f> 0,b,c 00110bbb00101010FBBBCCCCCC111110 */ +{ "mpywhkl", 0x302A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpywhkl<.f> a,b,c 00110bbb00101010FBBBCCCCCCAAAAAA */ +{ "mpywhkl", 0x302A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpywhkl<.f> a,b,u6 00110bbb01101010FBBBuuuuuuAAAAAA */ +{ "mpywhkl", 0x306A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhkl<.f><.cc> b,b,u6 00110bbb11101010FBBBuuuuuu1QQQQQ */ +{ "mpywhkl", 0x30EA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhkl<.f> 0,b,u6 00110bbb01101010FBBBuuuuuu111110 */ +{ "mpywhkl", 0x306A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhkl<.f> b,b,s12 00110bbb10101010FBBBssssssSSSSSS */ +{ "mpywhkl", 0x30AA0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpywhkl<.f> a,b,limm 00110bbb00101010FBBB111110AAAAAA */ +{ "mpywhkl", 0x302A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpywhkl<.f><.cc> 0,limm,c 00110bbb11101010FBBB1111100QQQQQ */ +{ "mpywhkl", 0x30EA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mpywhkl<.f><.cc> b,b,limm 0011011011101010F111CCCCCC0QQQQQ */ +{ "mpywhkl", 0x36EA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpywhkl<.f> 0,limm,c 0011011001101010F111CCCCCC111110 */ +{ "mpywhkl", 0x366A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpywhkl<.f> a,limm,c 0011011000101010F111CCCCCCAAAAAA */ +{ "mpywhkl", 0x362A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpywhkl<.f> 0,b,limm 00110bbb00101010FBBB111110111110 */ +{ "mpywhkl", 0x302A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpywhkl<.f> 0,limm,u6 0011011001101010F111uuuuuu111110 */ +{ "mpywhkl", 0x366A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhkl<.f><.cc> 0,limm,u6 0011011011101010F111uuuuuu1QQQQQ */ +{ "mpywhkl", 0x36EA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhkl<.f> a,limm,u6 0011011001101010F111uuuuuuAAAAAA */ +{ "mpywhkl", 0x366A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhkl<.f> 0,limm,s12 0011011010101010F111ssssssSSSSSS */ +{ "mpywhkl", 0x36AA7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpywhkl<.f> 0,limm,limm 0011011000101010F111111110111110 */ +{ "mpywhkl", 0x362A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpywhkl<.f><.cc> 0,limm,limm 0011011011101010F1111111100QQQQQ */ +{ "mpywhkl", 0x36EA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mpywhkl<.f> a,limm,limm 0011011000101010F111111110AAAAAA */ +{ "mpywhkl", 0x362A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpywhkul<.f> 0,b,c 00110bbb00101011FBBBCCCCCC111110 */ +{ "mpywhkul", 0x302B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpywhkul<.f> a,b,c 00110bbb00101011FBBBCCCCCCAAAAAA */ +{ "mpywhkul", 0x302B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpywhkul<.f><.cc> b,b,c 00110bbb11101011FBBBCCCCCC0QQQQQ */ +{ "mpywhkul", 0x30EB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpywhkul<.f><.cc> b,b,u6 00110bbb11101011FBBBuuuuuu1QQQQQ */ +{ "mpywhkul", 0x30EB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhkul<.f> 0,b,u6 00110bbb01101011FBBBuuuuuu111110 */ +{ "mpywhkul", 0x306B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhkul<.f> a,b,u6 00110bbb01101011FBBBuuuuuuAAAAAA */ +{ "mpywhkul", 0x306B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhkul<.f> b,b,s12 00110bbb10101011FBBBssssssSSSSSS */ +{ "mpywhkul", 0x30AB0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpywhkul<.f> a,b,limm 00110bbb00101011FBBB111110AAAAAA */ +{ "mpywhkul", 0x302B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpywhkul<.f><.cc> b,b,limm 0011011011101011F111CCCCCC0QQQQQ */ +{ "mpywhkul", 0x36EB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpywhkul<.f> 0,b,limm 00110bbb00101011FBBB111110111110 */ +{ "mpywhkul", 0x302B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpywhkul<.f><.cc> 0,limm,c 00110bbb11101011FBBB1111100QQQQQ */ +{ "mpywhkul", 0x30EB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mpywhkul<.f> 0,limm,c 0011011001101011F111CCCCCC111110 */ +{ "mpywhkul", 0x366B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpywhkul<.f> a,limm,c 0011011000101011F111CCCCCCAAAAAA */ +{ "mpywhkul", 0x362B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpywhkul<.f> 0,limm,u6 0011011001101011F111uuuuuu111110 */ +{ "mpywhkul", 0x366B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhkul<.f> a,limm,u6 0011011001101011F111uuuuuuAAAAAA */ +{ "mpywhkul", 0x366B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhkul<.f><.cc> 0,limm,u6 0011011011101011F111uuuuuu1QQQQQ */ +{ "mpywhkul", 0x36EB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhkul<.f> 0,limm,s12 0011011010101011F111ssssssSSSSSS */ +{ "mpywhkul", 0x36AB7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpywhkul<.f> 0,limm,limm 0011011000101011F111111110111110 */ +{ "mpywhkul", 0x362B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpywhkul<.f><.cc> 0,limm,limm 0011011011101011F1111111100QQQQQ */ +{ "mpywhkul", 0x36EB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mpywhkul<.f> a,limm,limm 0011011000101011F111111110AAAAAA */ +{ "mpywhkul", 0x362B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpywhl<.f> a,b,c 00110bbb00011100FBBBCCCCCCAAAAAA. */ +{ "mpywhl", 0x301C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpywhl<.f> 0,b,c 00110bbb00011100FBBBCCCCCC111110. */ +{ "mpywhl", 0x301C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpywhl<.f><.cc> b,b,c 00110bbb11011100FBBBCCCCCC0QQQQQ. */ +{ "mpywhl", 0x30DC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpywhl<.f> a,b,u6 00110bbb01011100FBBBuuuuuuAAAAAA. */ +{ "mpywhl", 0x305C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhl<.f> 0,b,u6 00110bbb01011100FBBBuuuuuu111110. */ +{ "mpywhl", 0x305C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhl<.f><.cc> b,b,u6 00110bbb11011100FBBBuuuuuu1QQQQQ. */ +{ "mpywhl", 0x30DC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhl<.f> b,b,s12 00110bbb10011100FBBBssssssSSSSSS. */ +{ "mpywhl", 0x309C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpywhl<.f> a,limm,c 0011011000011100F111CCCCCCAAAAAA. */ +{ "mpywhl", 0x361C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpywhl<.f> a,b,limm 00110bbb00011100FBBB111110AAAAAA. */ +{ "mpywhl", 0x301C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpywhl<.f> 0,limm,c 0011011000011100F111CCCCCC111110. */ +{ "mpywhl", 0x361C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpywhl<.f> 0,b,limm 00110bbb00011100FBBB111110111110. */ +{ "mpywhl", 0x301C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpywhl<.f><.cc> 0,limm,c 00110bbb11011100FBBB1111100QQQQQ. */ +{ "mpywhl", 0x30DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mpywhl<.f><.cc> b,b,limm 0011011011011100F111CCCCCC0QQQQQ. */ +{ "mpywhl", 0x36DC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpywhl<.f> a,limm,u6 0011011001011100F111uuuuuuAAAAAA. */ +{ "mpywhl", 0x365C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhl<.f> 0,limm,u6 0011011001011100F111uuuuuu111110. */ +{ "mpywhl", 0x365C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhl<.f><.cc> 0,limm,u6 0011011011011100F111uuuuuu1QQQQQ. */ +{ "mpywhl", 0x36DC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhl<.f> 0,limm,s12 0011011010011100F111ssssssSSSSSS. */ +{ "mpywhl", 0x369C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpywhl<.f> a,limm,limm 0011011000011100F111111110AAAAAA. */ +{ "mpywhl", 0x361C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpywhl<.f> 0,limm,limm 0011011000011100F111111110111110. */ +{ "mpywhl", 0x361C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpywhl<.f><.cc> 0,limm,limm 0011011011011100F1111111100QQQQQ. */ +{ "mpywhl", 0x36DC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mpywhul<.f> a,b,c 00110bbb00011110FBBBCCCCCCAAAAAA. */ +{ "mpywhul", 0x301E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpywhul<.f> 0,b,c 00110bbb00011110FBBBCCCCCC111110. */ +{ "mpywhul", 0x301E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mpywhul<.f><.cc> b,b,c 00110bbb11011110FBBBCCCCCC0QQQQQ. */ +{ "mpywhul", 0x30DE0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mpywhul<.f> a,b,u6 00110bbb01011110FBBBuuuuuuAAAAAA. */ +{ "mpywhul", 0x305E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhul<.f> 0,b,u6 00110bbb01011110FBBBuuuuuu111110. */ +{ "mpywhul", 0x305E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhul<.f><.cc> b,b,u6 00110bbb11011110FBBBuuuuuu1QQQQQ. */ +{ "mpywhul", 0x30DE0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhul<.f> b,b,s12 00110bbb10011110FBBBssssssSSSSSS. */ +{ "mpywhul", 0x309E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpywhul<.f> a,limm,c 0011011000011110F111CCCCCCAAAAAA. */ +{ "mpywhul", 0x361E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpywhul<.f> a,b,limm 00110bbb00011110FBBB111110AAAAAA. */ +{ "mpywhul", 0x301E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpywhul<.f> 0,limm,c 0011011000011110F111CCCCCC111110. */ +{ "mpywhul", 0x361E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mpywhul<.f> 0,b,limm 00110bbb00011110FBBB111110111110. */ +{ "mpywhul", 0x301E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mpywhul<.f><.cc> 0,limm,c 00110bbb11011110FBBB1111100QQQQQ. */ +{ "mpywhul", 0x30DE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mpywhul<.f><.cc> b,b,limm 0011011011011110F111CCCCCC0QQQQQ. */ +{ "mpywhul", 0x36DE7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mpywhul<.f> a,limm,u6 0011011001011110F111uuuuuuAAAAAA. */ +{ "mpywhul", 0x365E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhul<.f> 0,limm,u6 0011011001011110F111uuuuuu111110. */ +{ "mpywhul", 0x365E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mpywhul<.f><.cc> 0,limm,u6 0011011011011110F111uuuuuu1QQQQQ. */ +{ "mpywhul", 0x36DE7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhul<.f> 0,limm,s12 0011011010011110F111ssssssSSSSSS. */ +{ "mpywhul", 0x369E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mpywhul<.f> a,limm,limm 0011011000011110F111111110AAAAAA. */ +{ "mpywhul", 0x361E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpywhul<.f> 0,limm,limm 0011011000011110F111111110111110. */ +{ "mpywhul", 0x361E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mpywhul<.f><.cc> 0,limm,limm 0011011011011110F1111111100QQQQQ. */ +{ "mpywhul", 0x36DE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mpyw_s b,b,c 01111bbbccc01001. */ +{ "mpyw_s", 0x00007809, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY1E, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, + +/* mpy_s b,b,c 01111bbbccc01100. */ +{ "mpy_s", 0x0000780C, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY6E, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, + +/* msubdf<.f> a,b,c 00110bbb00010101FBBBCCCCCCAAAAAA. */ +{ "msubdf", 0x30150000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* msubdf<.f> 0,b,c 00110bbb00010101FBBBCCCCCC111110. */ +{ "msubdf", 0x3015003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* msubdf<.f><.cc> b,b,c 00110bbb11010101FBBBCCCCCC0QQQQQ. */ +{ "msubdf", 0x30D50000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* msubdf<.f> a,b,u6 00110bbb01010101FBBBuuuuuuAAAAAA. */ +{ "msubdf", 0x30550000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubdf<.f> 0,b,u6 00110bbb01010101FBBBuuuuuu111110. */ +{ "msubdf", 0x3055003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubdf<.f><.cc> b,b,u6 00110bbb11010101FBBBuuuuuu1QQQQQ. */ +{ "msubdf", 0x30D50020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* msubdf<.f> b,b,s12 00110bbb10010101FBBBssssssSSSSSS. */ +{ "msubdf", 0x30950000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* msubdf<.f> a,limm,c 0011011000010101F111CCCCCCAAAAAA. */ +{ "msubdf", 0x36157000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* msubdf<.f> a,b,limm 00110bbb00010101FBBB111110AAAAAA. */ +{ "msubdf", 0x30150F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* msubdf<.f> 0,limm,c 0011011000010101F111CCCCCC111110. */ +{ "msubdf", 0x3615703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* msubdf<.f> 0,b,limm 00110bbb00010101FBBB111110111110. */ +{ "msubdf", 0x30150FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* msubdf<.f><.cc> 0,limm,c 00110bbb11010101FBBB1111100QQQQQ. */ +{ "msubdf", 0x30D50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* msubdf<.f><.cc> b,b,limm 0011011011010101F111CCCCCC0QQQQQ. */ +{ "msubdf", 0x36D57000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* msubdf<.f> a,limm,u6 0011011001010101F111uuuuuuAAAAAA. */ +{ "msubdf", 0x36557000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubdf<.f> 0,limm,u6 0011011001010101F111uuuuuu111110. */ +{ "msubdf", 0x3655703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubdf<.f><.cc> 0,limm,u6 0011011011010101F111uuuuuu1QQQQQ. */ +{ "msubdf", 0x36D57020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* msubdf<.f> 0,limm,s12 0011011010010101F111ssssssSSSSSS. */ +{ "msubdf", 0x36957000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* msubdf<.f> a,limm,limm 0011011000010101F111111110AAAAAA. */ +{ "msubdf", 0x36157F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* msubdf<.f> 0,limm,limm 0011011000010101F111111110111110. */ +{ "msubdf", 0x36157FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* msubdf<.f><.cc> 0,limm,limm 0011011011010101F1111111100QQQQQ. */ +{ "msubdf", 0x36D57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* msubdw<.f> a,b,c 00101bbb00010100FBBBCCCCCCAAAAAA. */ +{ "msubdw", 0x28140000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* msubdw<.f> 0,b,c 00101bbb00010100FBBBCCCCCC111110. */ +{ "msubdw", 0x2814003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* msubdw<.f><.cc> b,b,c 00101bbb11010100FBBBCCCCCC0QQQQQ. */ +{ "msubdw", 0x28D40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* msubdw<.f> a,b,u6 00101bbb01010100FBBBuuuuuuAAAAAA. */ +{ "msubdw", 0x28540000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubdw<.f> 0,b,u6 00101bbb01010100FBBBuuuuuu111110. */ +{ "msubdw", 0x2854003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubdw<.f><.cc> b,b,u6 00101bbb11010100FBBBuuuuuu1QQQQQ. */ +{ "msubdw", 0x28D40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* msubdw<.f> b,b,s12 00101bbb10010100FBBBssssssSSSSSS. */ +{ "msubdw", 0x28940000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* msubdw<.f> a,limm,c 0010111000010100F111CCCCCCAAAAAA. */ +{ "msubdw", 0x2E147000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* msubdw<.f> a,b,limm 00101bbb00010100FBBB111110AAAAAA. */ +{ "msubdw", 0x28140F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* msubdw<.f> 0,limm,c 0010111000010100F111CCCCCC111110. */ +{ "msubdw", 0x2E14703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* msubdw<.f> 0,b,limm 00101bbb00010100FBBB111110111110. */ +{ "msubdw", 0x28140FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* msubdw<.f><.cc> 0,limm,c 0010111011010100F111CCCCCC0QQQQQ. */ +{ "msubdw", 0x2ED47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* msubdw<.f><.cc> b,b,limm 00101bbb11010100FBBB1111100QQQQQ. */ +{ "msubdw", 0x28D40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* msubdw<.f> a,limm,u6 0010111001010100F111uuuuuuAAAAAA. */ +{ "msubdw", 0x2E547000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubdw<.f> 0,limm,u6 0010111001010100F111uuuuuu111110. */ +{ "msubdw", 0x2E54703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubdw<.f><.cc> 0,limm,u6 0010111011010100F111uuuuuu1QQQQQ. */ +{ "msubdw", 0x2ED47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* msubdw<.f> 0,limm,s12 0010111010010100F111ssssssSSSSSS. */ +{ "msubdw", 0x2E947000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* msubdw<.f> a,limm,limm 0010111000010100F111111110AAAAAA. */ +{ "msubdw", 0x2E147F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* msubdw<.f> 0,limm,limm 0010111000010100F111111110111110. */ +{ "msubdw", 0x2E147FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* msubdw<.f><.cc> 0,limm,limm 0010111011010100F1111111100QQQQQ. */ +{ "msubdw", 0x2ED47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* msubf<.f> a,b,c 00110bbb00001110FBBBCCCCCCAAAAAA. */ +{ "msubf", 0x300E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* msubf<.f> 0,b,c 00110bbb00001110FBBBCCCCCC111110. */ +{ "msubf", 0x300E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* msubf<.f><.cc> b,b,c 00110bbb11001110FBBBCCCCCC0QQQQQ. */ +{ "msubf", 0x30CE0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* msubf<.f> a,b,u6 00110bbb01001110FBBBuuuuuuAAAAAA. */ +{ "msubf", 0x304E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubf<.f> 0,b,u6 00110bbb01001110FBBBuuuuuu111110. */ +{ "msubf", 0x304E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubf<.f><.cc> b,b,u6 00110bbb11001110FBBBuuuuuu1QQQQQ. */ +{ "msubf", 0x30CE0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* msubf<.f> b,b,s12 00110bbb10001110FBBBssssssSSSSSS. */ +{ "msubf", 0x308E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* msubf<.f> a,limm,c 0011011000001110F111CCCCCCAAAAAA. */ +{ "msubf", 0x360E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* msubf<.f> a,b,limm 00110bbb00001110FBBB111110AAAAAA. */ +{ "msubf", 0x300E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* msubf<.f> 0,limm,c 0011011000001110F111CCCCCC111110. */ +{ "msubf", 0x360E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* msubf<.f> 0,b,limm 00110bbb00001110FBBB111110111110. */ +{ "msubf", 0x300E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* msubf<.f><.cc> 0,limm,c 00110bbb11001110FBBB1111100QQQQQ. */ +{ "msubf", 0x30CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* msubf<.f><.cc> b,b,limm 0011011011001110F111CCCCCC0QQQQQ. */ +{ "msubf", 0x36CE7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* msubf<.f> a,limm,u6 0011011001001110F111uuuuuuAAAAAA. */ +{ "msubf", 0x364E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubf<.f> 0,limm,u6 0011011001001110F111uuuuuu111110. */ +{ "msubf", 0x364E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubf<.f><.cc> 0,limm,u6 0011011011001110F111uuuuuu1QQQQQ. */ +{ "msubf", 0x36CE7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* msubf<.f> 0,limm,s12 0011011010001110F111ssssssSSSSSS. */ +{ "msubf", 0x368E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* msubf<.f> a,limm,limm 0011011000001110F111111110AAAAAA. */ +{ "msubf", 0x360E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* msubf<.f> 0,limm,limm 0011011000001110F111111110111110. */ +{ "msubf", 0x360E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* msubf<.f><.cc> 0,limm,limm 0011011011001110F1111111100QQQQQ. */ +{ "msubf", 0x36CE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* msubfr<.f> a,b,c 00110bbb00001111FBBBCCCCCCAAAAAA. */ +{ "msubfr", 0x300F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* msubfr<.f> 0,b,c 00110bbb00001111FBBBCCCCCC111110. */ +{ "msubfr", 0x300F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* msubfr<.f><.cc> b,b,c 00110bbb11001111FBBBCCCCCC0QQQQQ. */ +{ "msubfr", 0x30CF0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* msubfr<.f> a,b,u6 00110bbb01001111FBBBuuuuuuAAAAAA. */ +{ "msubfr", 0x304F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubfr<.f> 0,b,u6 00110bbb01001111FBBBuuuuuu111110. */ +{ "msubfr", 0x304F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubfr<.f><.cc> b,b,u6 00110bbb11001111FBBBuuuuuu1QQQQQ. */ +{ "msubfr", 0x30CF0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* msubfr<.f> b,b,s12 00110bbb10001111FBBBssssssSSSSSS. */ +{ "msubfr", 0x308F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* msubfr<.f> a,limm,c 0011011000001111F111CCCCCCAAAAAA. */ +{ "msubfr", 0x360F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* msubfr<.f> a,b,limm 00110bbb00001111FBBB111110AAAAAA. */ +{ "msubfr", 0x300F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* msubfr<.f> 0,limm,c 0011011000001111F111CCCCCC111110. */ +{ "msubfr", 0x360F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* msubfr<.f> 0,b,limm 00110bbb00001111FBBB111110111110. */ +{ "msubfr", 0x300F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* msubfr<.f><.cc> 0,limm,c 00110bbb11001111FBBB1111100QQQQQ. */ +{ "msubfr", 0x30CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* msubfr<.f><.cc> b,b,limm 0011011011001111F111CCCCCC0QQQQQ. */ +{ "msubfr", 0x36CF7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* msubfr<.f> a,limm,u6 0011011001001111F111uuuuuuAAAAAA. */ +{ "msubfr", 0x364F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubfr<.f> 0,limm,u6 0011011001001111F111uuuuuu111110. */ +{ "msubfr", 0x364F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubfr<.f><.cc> 0,limm,u6 0011011011001111F111uuuuuu1QQQQQ. */ +{ "msubfr", 0x36CF7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* msubfr<.f> 0,limm,s12 0011011010001111F111ssssssSSSSSS. */ +{ "msubfr", 0x368F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* msubfr<.f> a,limm,limm 0011011000001111F111111110AAAAAA. */ +{ "msubfr", 0x360F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* msubfr<.f> 0,limm,limm 0011011000001111F111111110111110. */ +{ "msubfr", 0x360F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* msubfr<.f><.cc> 0,limm,limm 0011011011001111F1111111100QQQQQ. */ +{ "msubfr", 0x36CF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* msubt<.f> a,b,c 00101bbb00100000FBBBCCCCCCAAAAAA. */ +{ "msubt", 0x28200000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* msubt<.f> 0,b,c 00101bbb00100000FBBBCCCCCC111110. */ +{ "msubt", 0x2820003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* msubt<.f><.cc> b,b,c 00101bbb11100000FBBBCCCCCC0QQQQQ. */ +{ "msubt", 0x28E00000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* msubt<.f> a,b,u6 00101bbb01100000FBBBuuuuuuAAAAAA. */ +{ "msubt", 0x28600000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubt<.f> 0,b,u6 00101bbb01100000FBBBuuuuuu111110. */ +{ "msubt", 0x2860003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubt<.f><.cc> b,b,u6 00101bbb11100000FBBBuuuuuu1QQQQQ. */ +{ "msubt", 0x28E00020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* msubt<.f> b,b,s12 00101bbb10100000FBBBssssssSSSSSS. */ +{ "msubt", 0x28A00000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* msubt<.f> a,limm,c 0010111000100000F111CCCCCCAAAAAA. */ +{ "msubt", 0x2E207000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* msubt<.f> a,b,limm 00101bbb00100000FBBB111110AAAAAA. */ +{ "msubt", 0x28200F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* msubt<.f> 0,limm,c 0010111000100000F111CCCCCC111110. */ +{ "msubt", 0x2E20703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* msubt<.f> 0,b,limm 00101bbb00100000FBBB111110111110. */ +{ "msubt", 0x28200FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* msubt<.f><.cc> 0,limm,c 0010111011100000F111CCCCCC0QQQQQ. */ +{ "msubt", 0x2EE07000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* msubt<.f><.cc> b,b,limm 00101bbb11100000FBBB1111100QQQQQ. */ +{ "msubt", 0x28E00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* msubt<.f> a,limm,u6 0010111001100000F111uuuuuuAAAAAA. */ +{ "msubt", 0x2E607000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubt<.f> 0,limm,u6 0010111001100000F111uuuuuu111110. */ +{ "msubt", 0x2E60703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubt<.f><.cc> 0,limm,u6 0010111011100000F111uuuuuu1QQQQQ. */ +{ "msubt", 0x2EE07020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* msubt<.f> 0,limm,s12 0010111010100000F111ssssssSSSSSS. */ +{ "msubt", 0x2EA07000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* msubt<.f> a,limm,limm 0010111000100000F111111110AAAAAA. */ +{ "msubt", 0x2E207F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* msubt<.f> 0,limm,limm 0010111000100000F111111110111110. */ +{ "msubt", 0x2E207FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* msubt<.f><.cc> 0,limm,limm 0010111011100000F1111111100QQQQQ. */ +{ "msubt", 0x2EE07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* msubwhfl<.f><.cc> b,b,c 00110bbb11010100FBBBCCCCCC0QQQQQ */ +{ "msubwhfl", 0x30D40000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* msubwhfl<.f> 0,b,c 00110bbb00010100FBBBCCCCCC111110 */ +{ "msubwhfl", 0x3014003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* msubwhfl<.f> a,b,u6 00110bbb01010100FBBBuuuuuuAAAAAA */ +{ "msubwhfl", 0x30540000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubwhfl<.f><.cc> b,b,u6 00110bbb11010100FBBBuuuuuu1QQQQQ */ +{ "msubwhfl", 0x30D40020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* msubwhfl<.f> 0,b,u6 00110bbb01010100FBBBuuuuuu111110 */ +{ "msubwhfl", 0x3054003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubwhfl<.f> b,b,s12 00110bbb10010100FBBBssssssSSSSSS */ +{ "msubwhfl", 0x30940000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* msubwhfl<.f> a,limm,c 0011011000010100F111CCCCCCAAAAAA */ +{ "msubwhfl", 0x36147000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* msubwhfl<.f><.cc> 0,limm,c 00110bbb11010100FBBB1111100QQQQQ */ +{ "msubwhfl", 0x30D40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* msubwhfl<.f> a,b,limm 00110bbb00010100FBBB111110AAAAAA */ +{ "msubwhfl", 0x30140F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* msubwhfl<.f> 0,limm,c 0011011000010100F111CCCCCC111110 */ +{ "msubwhfl", 0x3614703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* msubwhfl<.f><.cc> b,b,limm 0011011011010100F111CCCCCC0QQQQQ */ +{ "msubwhfl", 0x36D47000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* msubwhfl<.f> 0,b,limm 00110bbb00010100FBBB111110111110 */ +{ "msubwhfl", 0x30140FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* msubwhfl<.f> 0,limm,u6 0011011001010100F111uuuuuu111110 */ +{ "msubwhfl", 0x3654703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubwhfl<.f> a,limm,u6 0011011001010100F111uuuuuuAAAAAA */ +{ "msubwhfl", 0x36547000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubwhfl<.f><.cc> 0,limm,u6 0011011011010100F111uuuuuu1QQQQQ */ +{ "msubwhfl", 0x36D47020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* msubwhfl<.f> 0,limm,s12 0011011010010100F111ssssssSSSSSS */ +{ "msubwhfl", 0x36947000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* msubwhfl<.f> 0,limm,limm 0011011000010100F111111110111110 */ +{ "msubwhfl", 0x36147FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* msubwhfl<.f> a,limm,limm 0011011000010100F111111110AAAAAA */ +{ "msubwhfl", 0x36147F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* msubwhfl<.f><.cc> 0,limm,limm 0011011011010100F1111111100QQQQQ */ +{ "msubwhfl", 0x36D47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* msubwhflr<.f> 0,b,c 00110bbb00011010FBBBCCCCCC111110 */ +{ "msubwhflr", 0x301A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* msubwhflr<.f><.cc> b,b,c 00110bbb11011010FBBBCCCCCC0QQQQQ */ +{ "msubwhflr", 0x30DA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* msubwhflr<.f> a,b,c 00110bbb00011010FBBBCCCCCCAAAAAA */ +{ "msubwhflr", 0x301A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* msubwhflr<.f> a,b,u6 00110bbb01011010FBBBuuuuuuAAAAAA */ +{ "msubwhflr", 0x305A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubwhflr<.f><.cc> b,b,u6 00110bbb11011010FBBBuuuuuu1QQQQQ */ +{ "msubwhflr", 0x30DA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* msubwhflr<.f> 0,b,u6 00110bbb01011010FBBBuuuuuu111110 */ +{ "msubwhflr", 0x305A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubwhflr<.f> b,b,s12 00110bbb10011010FBBBssssssSSSSSS */ +{ "msubwhflr", 0x309A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* msubwhflr<.f><.cc> b,b,limm 0011011011011010F111CCCCCC0QQQQQ */ +{ "msubwhflr", 0x36DA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* msubwhflr<.f><.cc> 0,limm,c 00110bbb11011010FBBB1111100QQQQQ */ +{ "msubwhflr", 0x30DA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* msubwhflr<.f> a,b,limm 00110bbb00011010FBBB111110AAAAAA */ +{ "msubwhflr", 0x301A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* msubwhflr<.f> 0,b,limm 00110bbb00011010FBBB111110111110 */ +{ "msubwhflr", 0x301A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* msubwhflr<.f> 0,limm,c 0011011000011010F111CCCCCC111110 */ +{ "msubwhflr", 0x361A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* msubwhflr<.f> a,limm,c 0011011000011010F111CCCCCCAAAAAA */ +{ "msubwhflr", 0x361A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* msubwhflr<.f><.cc> 0,limm,u6 0011011011011010F111uuuuuu1QQQQQ */ +{ "msubwhflr", 0x36DA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* msubwhflr<.f> 0,limm,u6 0011011001011010F111uuuuuu111110 */ +{ "msubwhflr", 0x365A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubwhflr<.f> a,limm,u6 0011011001011010F111uuuuuuAAAAAA */ +{ "msubwhflr", 0x365A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubwhflr<.f> 0,limm,s12 0011011010011010F111ssssssSSSSSS */ +{ "msubwhflr", 0x369A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* msubwhflr<.f><.cc> 0,limm,limm 0011011011011010F1111111100QQQQQ */ +{ "msubwhflr", 0x36DA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* msubwhflr<.f> a,limm,limm 0011011000011010F111111110AAAAAA */ +{ "msubwhflr", 0x361A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* msubwhflr<.f> 0,limm,limm 0011011000011010F111111110111110 */ +{ "msubwhflr", 0x361A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* msubwhfm<.f> 0,b,c 00110bbb00101100FBBBCCCCCC111110 */ +{ "msubwhfm", 0x302C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* msubwhfm<.f><.cc> b,b,c 00110bbb11101100FBBBCCCCCC0QQQQQ */ +{ "msubwhfm", 0x30EC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* msubwhfm<.f> a,b,c 00110bbb00101100FBBBCCCCCCAAAAAA */ +{ "msubwhfm", 0x302C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* msubwhfm<.f><.cc> b,b,u6 00110bbb11101100FBBBuuuuuu1QQQQQ */ +{ "msubwhfm", 0x30EC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* msubwhfm<.f> a,b,u6 00110bbb01101100FBBBuuuuuuAAAAAA */ +{ "msubwhfm", 0x306C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubwhfm<.f> 0,b,u6 00110bbb01101100FBBBuuuuuu111110 */ +{ "msubwhfm", 0x306C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubwhfm<.f> b,b,s12 00110bbb10101100FBBBssssssSSSSSS */ +{ "msubwhfm", 0x30AC0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* msubwhfm<.f> 0,limm,c 0011011001101100F111CCCCCC111110 */ +{ "msubwhfm", 0x366C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* msubwhfm<.f><.cc> 0,limm,c 00110bbb11101100FBBB1111100QQQQQ */ +{ "msubwhfm", 0x30EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* msubwhfm<.f> a,limm,c 0011011000101100F111CCCCCCAAAAAA */ +{ "msubwhfm", 0x362C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* msubwhfm<.f><.cc> b,b,limm 0011011011101100F111CCCCCC0QQQQQ */ +{ "msubwhfm", 0x36EC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* msubwhfm<.f> a,b,limm 00110bbb00101100FBBB111110AAAAAA */ +{ "msubwhfm", 0x302C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* msubwhfm<.f> 0,b,limm 00110bbb00101100FBBB111110111110 */ +{ "msubwhfm", 0x302C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* msubwhfm<.f> 0,limm,u6 0011011001101100F111uuuuuu111110 */ +{ "msubwhfm", 0x366C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubwhfm<.f> a,limm,u6 0011011001101100F111uuuuuuAAAAAA */ +{ "msubwhfm", 0x366C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubwhfm<.f><.cc> 0,limm,u6 0011011011101100F111uuuuuu1QQQQQ */ +{ "msubwhfm", 0x36EC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* msubwhfm<.f> 0,limm,s12 0011011010101100F111ssssssSSSSSS */ +{ "msubwhfm", 0x36AC7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* msubwhfm<.f> 0,limm,limm 0011011000101100F111111110111110 */ +{ "msubwhfm", 0x362C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* msubwhfm<.f> a,limm,limm 0011011000101100F111111110AAAAAA */ +{ "msubwhfm", 0x362C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* msubwhfm<.f><.cc> 0,limm,limm 0011011011101100F1111111100QQQQQ */ +{ "msubwhfm", 0x36EC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* msubwhfmr<.f> a,b,c 00110bbb00101101FBBBCCCCCCAAAAAA */ +{ "msubwhfmr", 0x302D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* msubwhfmr<.f> 0,b,c 00110bbb00101101FBBBCCCCCC111110 */ +{ "msubwhfmr", 0x302D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* msubwhfmr<.f><.cc> b,b,c 00110bbb11101101FBBBCCCCCC0QQQQQ */ +{ "msubwhfmr", 0x30ED0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* msubwhfmr<.f> a,b,u6 00110bbb01101101FBBBuuuuuuAAAAAA */ +{ "msubwhfmr", 0x306D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubwhfmr<.f><.cc> b,b,u6 00110bbb11101101FBBBuuuuuu1QQQQQ */ +{ "msubwhfmr", 0x30ED0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* msubwhfmr<.f> 0,b,u6 00110bbb01101101FBBBuuuuuu111110 */ +{ "msubwhfmr", 0x306D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubwhfmr<.f> b,b,s12 00110bbb10101101FBBBssssssSSSSSS */ +{ "msubwhfmr", 0x30AD0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* msubwhfmr<.f> a,limm,c 0011011000101101F111CCCCCCAAAAAA */ +{ "msubwhfmr", 0x362D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* msubwhfmr<.f> 0,b,limm 00110bbb00101101FBBB111110111110 */ +{ "msubwhfmr", 0x302D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* msubwhfmr<.f> a,b,limm 00110bbb00101101FBBB111110AAAAAA */ +{ "msubwhfmr", 0x302D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* msubwhfmr<.f><.cc> b,b,limm 0011011011101101F111CCCCCC0QQQQQ */ +{ "msubwhfmr", 0x36ED7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* msubwhfmr<.f><.cc> 0,limm,c 00110bbb11101101FBBB1111100QQQQQ */ +{ "msubwhfmr", 0x30ED0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* msubwhfmr<.f> 0,limm,c 0011011001101101F111CCCCCC111110 */ +{ "msubwhfmr", 0x366D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* msubwhfmr<.f><.cc> 0,limm,u6 0011011011101101F111uuuuuu1QQQQQ */ +{ "msubwhfmr", 0x36ED7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* msubwhfmr<.f> a,limm,u6 0011011001101101F111uuuuuuAAAAAA */ +{ "msubwhfmr", 0x366D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubwhfmr<.f> 0,limm,u6 0011011001101101F111uuuuuu111110 */ +{ "msubwhfmr", 0x366D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* msubwhfmr<.f> 0,limm,s12 0011011010101101F111ssssssSSSSSS */ +{ "msubwhfmr", 0x36AD7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* msubwhfmr<.f><.cc> 0,limm,limm 0011011011101101F1111111100QQQQQ */ +{ "msubwhfmr", 0x36ED7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* msubwhfmr<.f> 0,limm,limm 0011011000101101F111111110111110 */ +{ "msubwhfmr", 0x362D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* msubwhfmr<.f> a,limm,limm 0011011000101101F111111110AAAAAA */ +{ "msubwhfmr", 0x362D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mul64 0,b,c 00101bbb000001000BBBCCCCCC111110. */ +{ "mul64", 0x2804003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* mul64<.cc> 0,b,c 00101bbb110001000BBBCCCCCC0QQQQQ. */ +{ "mul64", 0x28C40000, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_CC }}, + +/* mul64 0,b,u6 00101bbb010001000BBBuuuuuu111110. */ +{ "mul64", 0x2844003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* mul64<.cc> 0,b,u6 00101bbb110001000BBBuuuuuu1QQQQQ. */ +{ "mul64", 0x28C40020, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, + +/* mul64 0,b,s12 00101bbb100001000BBBssssssSSSSSS. */ +{ "mul64", 0x28840000, 0xF8FF8000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, + +/* mul64 0,limm,c 00101110000001000111CCCCCC111110. */ +{ "mul64", 0x2E04703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* mul64 0,b,limm 00101bbb000001000BBB111110111110. */ +{ "mul64", 0x28040FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* mul64<.cc> 0,limm,c 00101110110001000111CCCCCC0QQQQQ. */ +{ "mul64", 0x2EC47000, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* mul64<.cc> 0,b,limm 00101bbb110001000BBB1111100QQQQQ. */ +{ "mul64", 0x28C40F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_CC }}, + +/* mul64 0,limm,u6 00101110010001000111uuuuuu111110. */ +{ "mul64", 0x2E44703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* mul64<.cc> 0,limm,u6 00101110110001000111uuuuuu1QQQQQ. */ +{ "mul64", 0x2EC47020, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* mul64 0,limm,s12 00101110100001000111ssssssSSSSSS. */ +{ "mul64", 0x2E847000, 0xFFFFF000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* mul64 0,limm,limm 00101110000001000111111110111110. */ +{ "mul64", 0x2E047FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* mul64<.cc> 0,limm,limm 001011101100010001111111100QQQQQ. */ +{ "mul64", 0x2EC47F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* mul64 0,b,c 00101bbb000001000BBBCCCCCC111110. */ +{ "mul64", 0x2804003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* mul64<.cc> 0,b,c 00101bbb110001000BBBCCCCCC0QQQQQ. */ +{ "mul64", 0x28C40000, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }}, + +/* mul64 0,b,u6 00101bbb010001000BBBuuuuuu111110. */ +{ "mul64", 0x2844003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* mul64<.cc> 0,b,u6 00101bbb110001000BBBuuuuuu1QQQQQ. */ +{ "mul64", 0x28C40020, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, + +/* mul64 0,b,s12 00101bbb100001000BBBssssssSSSSSS. */ +{ "mul64", 0x28840000, 0xF8FF8000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, + +/* mul64 0,limm,c 00101110000001000111CCCCCC111110. */ +{ "mul64", 0x2E04703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* mul64 0,b,limm 00101bbb000001000BBB111110111110. */ +{ "mul64", 0x28040FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* mul64<.cc> 0,limm,c 00101110110001000111CCCCCC0QQQQQ. */ +{ "mul64", 0x2EC47000, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* mul64<.cc> 0,b,limm 00101bbb110001000BBB1111100QQQQQ. */ +{ "mul64", 0x28C40F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, + +/* mul64 0,limm,u6 00101110010001000111uuuuuu111110. */ +{ "mul64", 0x2E44703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* mul64<.cc> 0,limm,u6 00101110110001000111uuuuuu1QQQQQ. */ +{ "mul64", 0x2EC47020, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* mul64 0,limm,s12 00101110100001000111ssssssSSSSSS. */ +{ "mul64", 0x2E847000, 0xFFFFF000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* mul64 0,limm,limm 00101110000001000111111110111110. */ +{ "mul64", 0x2E047FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* mul64<.cc> 0,limm,limm 001011101100010001111111100QQQQQ. */ +{ "mul64", 0x2EC47F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* mul64_s 0,b,c 01111bbbccc01100. */ +{ "mul64_s", 0x0000780C, 0x0000F81F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA_S, OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, + +/* mul64_s 0,b,c 01111bbbccc01100. */ +{ "mul64_s", 0x0000780C, 0x0000F81F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, + +/* muldw<.f> a,b,c 00101bbb00001100FBBBCCCCCCAAAAAA. */ +{ "muldw", 0x280C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* muldw<.f> 0,b,c 00101bbb00001100FBBBCCCCCC111110. */ +{ "muldw", 0x280C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* muldw<.f><.cc> b,b,c 00101bbb11001100FBBBCCCCCC0QQQQQ. */ +{ "muldw", 0x28CC0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* muldw<.f> a,b,u6 00101bbb01001100FBBBuuuuuuAAAAAA. */ +{ "muldw", 0x284C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* muldw<.f> 0,b,u6 00101bbb01001100FBBBuuuuuu111110. */ +{ "muldw", 0x284C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* muldw<.f><.cc> b,b,u6 00101bbb11001100FBBBuuuuuu1QQQQQ. */ +{ "muldw", 0x28CC0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* muldw<.f> b,b,s12 00101bbb10001100FBBBssssssSSSSSS. */ +{ "muldw", 0x288C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* muldw<.f> a,limm,c 0010111000001100F111CCCCCCAAAAAA. */ +{ "muldw", 0x2E0C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* muldw<.f> a,b,limm 00101bbb00001100FBBB111110AAAAAA. */ +{ "muldw", 0x280C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* muldw<.f> 0,limm,c 0010111000001100F111CCCCCC111110. */ +{ "muldw", 0x2E0C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* muldw<.f> 0,b,limm 00101bbb00001100FBBB111110111110. */ +{ "muldw", 0x280C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* muldw<.f><.cc> 0,limm,c 0010111011001100F111CCCCCC0QQQQQ. */ +{ "muldw", 0x2ECC7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* muldw<.f><.cc> b,b,limm 00101bbb11001100FBBB1111100QQQQQ. */ +{ "muldw", 0x28CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* muldw<.f> a,limm,u6 0010111001001100F111uuuuuuAAAAAA. */ +{ "muldw", 0x2E4C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* muldw<.f> 0,limm,u6 0010111001001100F111uuuuuu111110. */ +{ "muldw", 0x2E4C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* muldw<.f><.cc> 0,limm,u6 0010111011001100F111uuuuuu1QQQQQ. */ +{ "muldw", 0x2ECC7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* muldw<.f> 0,limm,s12 0010111010001100F111ssssssSSSSSS. */ +{ "muldw", 0x2E8C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* muldw<.f> a,limm,limm 0010111000001100F111111110AAAAAA. */ +{ "muldw", 0x2E0C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* muldw<.f> 0,limm,limm 0010111000001100F111111110111110. */ +{ "muldw", 0x2E0C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* muldw<.f><.cc> 0,limm,limm 0010111011001100F1111111100QQQQQ. */ +{ "muldw", 0x2ECC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mulflw<.f> a,b,c 00101bbb00110010FBBBCCCCCCAAAAAA. */ +{ "mulflw", 0x28320000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mulflw<.f> 0,b,c 00101bbb00110010FBBBCCCCCC111110. */ +{ "mulflw", 0x2832003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mulflw<.f><.cc> b,b,c 00101bbb11110010FBBBCCCCCC0QQQQQ. */ +{ "mulflw", 0x28F20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mulflw<.f> a,b,u6 00101bbb01110010FBBBuuuuuuAAAAAA. */ +{ "mulflw", 0x28720000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulflw<.f> 0,b,u6 00101bbb01110010FBBBuuuuuu111110. */ +{ "mulflw", 0x2872003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulflw<.f><.cc> b,b,u6 00101bbb11110010FBBBuuuuuu1QQQQQ. */ +{ "mulflw", 0x28F20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mulflw<.f> b,b,s12 00101bbb10110010FBBBssssssSSSSSS. */ +{ "mulflw", 0x28B20000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mulflw<.f> a,limm,c 0010111000110010F111CCCCCCAAAAAA. */ +{ "mulflw", 0x2E327000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mulflw<.f> a,b,limm 00101bbb00110010FBBB111110AAAAAA. */ +{ "mulflw", 0x28320F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mulflw<.f> 0,limm,c 0010111000110010F111CCCCCC111110. */ +{ "mulflw", 0x2E32703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mulflw<.f> 0,b,limm 00101bbb00110010FBBB111110111110. */ +{ "mulflw", 0x28320FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mulflw<.f><.cc> 0,limm,c 0010111011110010F111CCCCCC0QQQQQ. */ +{ "mulflw", 0x2EF27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mulflw<.f><.cc> b,b,limm 00101bbb11110010FBBB1111100QQQQQ. */ +{ "mulflw", 0x28F20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mulflw<.f> a,limm,u6 0010111001110010F111uuuuuuAAAAAA. */ +{ "mulflw", 0x2E727000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulflw<.f> 0,limm,u6 0010111001110010F111uuuuuu111110. */ +{ "mulflw", 0x2E72703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulflw<.f><.cc> 0,limm,u6 0010111011110010F111uuuuuu1QQQQQ. */ +{ "mulflw", 0x2EF27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mulflw<.f> 0,limm,s12 0010111010110010F111ssssssSSSSSS. */ +{ "mulflw", 0x2EB27000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mulflw<.f> a,limm,limm 0010111000110010F111111110AAAAAA. */ +{ "mulflw", 0x2E327F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mulflw<.f> 0,limm,limm 0010111000110010F111111110111110. */ +{ "mulflw", 0x2E327FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mulflw<.f><.cc> 0,limm,limm 0010111011110010F1111111100QQQQQ. */ +{ "mulflw", 0x2EF27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mulhflw<.f> a,b,c 00101bbb00111001FBBBCCCCCCAAAAAA. */ +{ "mulhflw", 0x28390000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mulhflw<.f> 0,b,c 00101bbb00111001FBBBCCCCCC111110. */ +{ "mulhflw", 0x2839003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mulhflw<.f><.cc> b,b,c 00101bbb11111001FBBBCCCCCC0QQQQQ. */ +{ "mulhflw", 0x28F90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mulhflw<.f> a,b,u6 00101bbb01111001FBBBuuuuuuAAAAAA. */ +{ "mulhflw", 0x28790000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulhflw<.f> 0,b,u6 00101bbb01111001FBBBuuuuuu111110. */ +{ "mulhflw", 0x2879003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulhflw<.f><.cc> b,b,u6 00101bbb11111001FBBBuuuuuu1QQQQQ. */ +{ "mulhflw", 0x28F90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mulhflw<.f> b,b,s12 00101bbb10111001FBBBssssssSSSSSS. */ +{ "mulhflw", 0x28B90000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mulhflw<.f> a,limm,c 0010111000111001F111CCCCCCAAAAAA. */ +{ "mulhflw", 0x2E397000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mulhflw<.f> a,b,limm 00101bbb00111001FBBB111110AAAAAA. */ +{ "mulhflw", 0x28390F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mulhflw<.f> 0,limm,c 0010111000111001F111CCCCCC111110. */ +{ "mulhflw", 0x2E39703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mulhflw<.f> 0,b,limm 00101bbb00111001FBBB111110111110. */ +{ "mulhflw", 0x28390FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mulhflw<.f><.cc> 0,limm,c 0010111011111001F111CCCCCC0QQQQQ. */ +{ "mulhflw", 0x2EF97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mulhflw<.f><.cc> b,b,limm 00101bbb11111001FBBB1111100QQQQQ. */ +{ "mulhflw", 0x28F90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mulhflw<.f> a,limm,u6 0010111001111001F111uuuuuuAAAAAA. */ +{ "mulhflw", 0x2E797000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulhflw<.f> 0,limm,u6 0010111001111001F111uuuuuu111110. */ +{ "mulhflw", 0x2E79703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulhflw<.f><.cc> 0,limm,u6 0010111011111001F111uuuuuu1QQQQQ. */ +{ "mulhflw", 0x2EF97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mulhflw<.f> 0,limm,s12 0010111010111001F111ssssssSSSSSS. */ +{ "mulhflw", 0x2EB97000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mulhflw<.f> a,limm,limm 0010111000111001F111111110AAAAAA. */ +{ "mulhflw", 0x2E397F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mulhflw<.f> 0,limm,limm 0010111000111001F111111110111110. */ +{ "mulhflw", 0x2E397FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mulhflw<.f><.cc> 0,limm,limm 0010111011111001F1111111100QQQQQ. */ +{ "mulhflw", 0x2EF97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mulhlw<.f> a,b,c 00101bbb00111000FBBBCCCCCCAAAAAA. */ +{ "mulhlw", 0x28380000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mulhlw<.f> 0,b,c 00101bbb00111000FBBBCCCCCC111110. */ +{ "mulhlw", 0x2838003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mulhlw<.f><.cc> b,b,c 00101bbb11111000FBBBCCCCCC0QQQQQ. */ +{ "mulhlw", 0x28F80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mulhlw<.f> a,b,u6 00101bbb01111000FBBBuuuuuuAAAAAA. */ +{ "mulhlw", 0x28780000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulhlw<.f> 0,b,u6 00101bbb01111000FBBBuuuuuu111110. */ +{ "mulhlw", 0x2878003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulhlw<.f><.cc> b,b,u6 00101bbb11111000FBBBuuuuuu1QQQQQ. */ +{ "mulhlw", 0x28F80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mulhlw<.f> b,b,s12 00101bbb10111000FBBBssssssSSSSSS. */ +{ "mulhlw", 0x28B80000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mulhlw<.f> a,limm,c 0010111000111000F111CCCCCCAAAAAA. */ +{ "mulhlw", 0x2E387000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mulhlw<.f> a,b,limm 00101bbb00111000FBBB111110AAAAAA. */ +{ "mulhlw", 0x28380F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mulhlw<.f> 0,limm,c 0010111000111000F111CCCCCC111110. */ +{ "mulhlw", 0x2E38703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mulhlw<.f> 0,b,limm 00101bbb00111000FBBB111110111110. */ +{ "mulhlw", 0x28380FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mulhlw<.f><.cc> 0,limm,c 0010111011111000F111CCCCCC0QQQQQ. */ +{ "mulhlw", 0x2EF87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mulhlw<.f><.cc> b,b,limm 00101bbb11111000FBBB1111100QQQQQ. */ +{ "mulhlw", 0x28F80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mulhlw<.f> a,limm,u6 0010111001111000F111uuuuuuAAAAAA. */ +{ "mulhlw", 0x2E787000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulhlw<.f> 0,limm,u6 0010111001111000F111uuuuuu111110. */ +{ "mulhlw", 0x2E78703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulhlw<.f><.cc> 0,limm,u6 0010111011111000F111uuuuuu1QQQQQ. */ +{ "mulhlw", 0x2EF87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mulhlw<.f> 0,limm,s12 0010111010111000F111ssssssSSSSSS. */ +{ "mulhlw", 0x2EB87000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mulhlw<.f> a,limm,limm 0010111000111000F111111110AAAAAA. */ +{ "mulhlw", 0x2E387F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mulhlw<.f> 0,limm,limm 0010111000111000F111111110111110. */ +{ "mulhlw", 0x2E387FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mulhlw<.f><.cc> 0,limm,limm 0010111011111000F1111111100QQQQQ. */ +{ "mulhlw", 0x2EF87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mullw<.f> a,b,c 00101bbb00110001FBBBCCCCCCAAAAAA. */ +{ "mullw", 0x28310000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mullw<.f> 0,b,c 00101bbb00110001FBBBCCCCCC111110. */ +{ "mullw", 0x2831003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mullw<.f><.cc> b,b,c 00101bbb11110001FBBBCCCCCC0QQQQQ. */ +{ "mullw", 0x28F10000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mullw<.f> a,b,u6 00101bbb01110001FBBBuuuuuuAAAAAA. */ +{ "mullw", 0x28710000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mullw<.f> 0,b,u6 00101bbb01110001FBBBuuuuuu111110. */ +{ "mullw", 0x2871003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mullw<.f><.cc> b,b,u6 00101bbb11110001FBBBuuuuuu1QQQQQ. */ +{ "mullw", 0x28F10020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mullw<.f> b,b,s12 00101bbb10110001FBBBssssssSSSSSS. */ +{ "mullw", 0x28B10000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mullw<.f> a,limm,c 0010111000110001F111CCCCCCAAAAAA. */ +{ "mullw", 0x2E317000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mullw<.f> a,b,limm 00101bbb00110001FBBB111110AAAAAA. */ +{ "mullw", 0x28310F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mullw<.f> 0,limm,c 0010111000110001F111CCCCCC111110. */ +{ "mullw", 0x2E31703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mullw<.f> 0,b,limm 00101bbb00110001FBBB111110111110. */ +{ "mullw", 0x28310FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mullw<.f><.cc> 0,limm,c 0010111011110001F111CCCCCC0QQQQQ. */ +{ "mullw", 0x2EF17000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mullw<.f><.cc> b,b,limm 00101bbb11110001FBBB1111100QQQQQ. */ +{ "mullw", 0x28F10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mullw<.f> a,limm,u6 0010111001110001F111uuuuuuAAAAAA. */ +{ "mullw", 0x2E717000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mullw<.f> 0,limm,u6 0010111001110001F111uuuuuu111110. */ +{ "mullw", 0x2E71703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mullw<.f><.cc> 0,limm,u6 0010111011110001F111uuuuuu1QQQQQ. */ +{ "mullw", 0x2EF17020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mullw<.f> 0,limm,s12 0010111010110001F111ssssssSSSSSS. */ +{ "mullw", 0x2EB17000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mullw<.f> a,limm,limm 0010111000110001F111111110AAAAAA. */ +{ "mullw", 0x2E317F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mullw<.f> 0,limm,limm 0010111000110001F111111110111110. */ +{ "mullw", 0x2E317FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mullw<.f><.cc> 0,limm,limm 0010111011110001F1111111100QQQQQ. */ +{ "mullw", 0x2EF17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mulrdw<.f> a,b,c 00101bbb00001110FBBBCCCCCCAAAAAA. */ +{ "mulrdw", 0x280E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mulrdw<.f> 0,b,c 00101bbb00001110FBBBCCCCCC111110. */ +{ "mulrdw", 0x280E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mulrdw<.f><.cc> b,b,c 00101bbb11001110FBBBCCCCCC0QQQQQ. */ +{ "mulrdw", 0x28CE0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mulrdw<.f> a,b,u6 00101bbb01001110FBBBuuuuuuAAAAAA. */ +{ "mulrdw", 0x284E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulrdw<.f> 0,b,u6 00101bbb01001110FBBBuuuuuu111110. */ +{ "mulrdw", 0x284E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulrdw<.f><.cc> b,b,u6 00101bbb11001110FBBBuuuuuu1QQQQQ. */ +{ "mulrdw", 0x28CE0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mulrdw<.f> b,b,s12 00101bbb10001110FBBBssssssSSSSSS. */ +{ "mulrdw", 0x288E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mulrdw<.f> a,limm,c 0010111000001110F111CCCCCCAAAAAA. */ +{ "mulrdw", 0x2E0E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mulrdw<.f> a,b,limm 00101bbb00001110FBBB111110AAAAAA. */ +{ "mulrdw", 0x280E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mulrdw<.f> 0,limm,c 0010111000001110F111CCCCCC111110. */ +{ "mulrdw", 0x2E0E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mulrdw<.f> 0,b,limm 00101bbb00001110FBBB111110111110. */ +{ "mulrdw", 0x280E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mulrdw<.f><.cc> 0,limm,c 0010111011001110F111CCCCCC0QQQQQ. */ +{ "mulrdw", 0x2ECE7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mulrdw<.f><.cc> b,b,limm 00101bbb11001110FBBB1111100QQQQQ. */ +{ "mulrdw", 0x28CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mulrdw<.f> a,limm,u6 0010111001001110F111uuuuuuAAAAAA. */ +{ "mulrdw", 0x2E4E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulrdw<.f> 0,limm,u6 0010111001001110F111uuuuuu111110. */ +{ "mulrdw", 0x2E4E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulrdw<.f><.cc> 0,limm,u6 0010111011001110F111uuuuuu1QQQQQ. */ +{ "mulrdw", 0x2ECE7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mulrdw<.f> 0,limm,s12 0010111010001110F111ssssssSSSSSS. */ +{ "mulrdw", 0x2E8E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mulrdw<.f> a,limm,limm 0010111000001110F111111110AAAAAA. */ +{ "mulrdw", 0x2E0E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mulrdw<.f> 0,limm,limm 0010111000001110F111111110111110. */ +{ "mulrdw", 0x2E0E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mulrdw<.f><.cc> 0,limm,limm 0010111011001110F1111111100QQQQQ. */ +{ "mulrdw", 0x2ECE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mulrt<.f> a,b,c 00101bbb00011010FBBBCCCCCCAAAAAA. */ +{ "mulrt", 0x281A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mulrt<.f> 0,b,c 00101bbb00011010FBBBCCCCCC111110. */ +{ "mulrt", 0x281A003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mulrt<.f><.cc> b,b,c 00101bbb11011010FBBBCCCCCC0QQQQQ. */ +{ "mulrt", 0x28DA0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mulrt<.f> a,b,u6 00101bbb01011010FBBBuuuuuuAAAAAA. */ +{ "mulrt", 0x285A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulrt<.f> 0,b,u6 00101bbb01011010FBBBuuuuuu111110. */ +{ "mulrt", 0x285A003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulrt<.f><.cc> b,b,u6 00101bbb11011010FBBBuuuuuu1QQQQQ. */ +{ "mulrt", 0x28DA0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mulrt<.f> b,b,s12 00101bbb10011010FBBBssssssSSSSSS. */ +{ "mulrt", 0x289A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mulrt<.f> a,limm,c 0010111000011010F111CCCCCCAAAAAA. */ +{ "mulrt", 0x2E1A7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mulrt<.f> a,b,limm 00101bbb00011010FBBB111110AAAAAA. */ +{ "mulrt", 0x281A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mulrt<.f> 0,limm,c 0010111000011010F111CCCCCC111110. */ +{ "mulrt", 0x2E1A703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mulrt<.f> 0,b,limm 00101bbb00011010FBBB111110111110. */ +{ "mulrt", 0x281A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mulrt<.f><.cc> 0,limm,c 0010111011011010F111CCCCCC0QQQQQ. */ +{ "mulrt", 0x2EDA7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mulrt<.f><.cc> b,b,limm 00101bbb11011010FBBB1111100QQQQQ. */ +{ "mulrt", 0x28DA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mulrt<.f> a,limm,u6 0010111001011010F111uuuuuuAAAAAA. */ +{ "mulrt", 0x2E5A7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulrt<.f> 0,limm,u6 0010111001011010F111uuuuuu111110. */ +{ "mulrt", 0x2E5A703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulrt<.f><.cc> 0,limm,u6 0010111011011010F111uuuuuu1QQQQQ. */ +{ "mulrt", 0x2EDA7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mulrt<.f> 0,limm,s12 0010111010011010F111ssssssSSSSSS. */ +{ "mulrt", 0x2E9A7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mulrt<.f> a,limm,limm 0010111000011010F111111110AAAAAA. */ +{ "mulrt", 0x2E1A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mulrt<.f> 0,limm,limm 0010111000011010F111111110111110. */ +{ "mulrt", 0x2E1A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mulrt<.f><.cc> 0,limm,limm 0010111011011010F1111111100QQQQQ. */ +{ "mulrt", 0x2EDA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mult<.f> a,b,c 00101bbb00011000FBBBCCCCCCAAAAAA. */ +{ "mult", 0x28180000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mult<.f> 0,b,c 00101bbb00011000FBBBCCCCCC111110. */ +{ "mult", 0x2818003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mult<.f><.cc> b,b,c 00101bbb11011000FBBBCCCCCC0QQQQQ. */ +{ "mult", 0x28D80000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mult<.f> a,b,u6 00101bbb01011000FBBBuuuuuuAAAAAA. */ +{ "mult", 0x28580000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mult<.f> 0,b,u6 00101bbb01011000FBBBuuuuuu111110. */ +{ "mult", 0x2858003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mult<.f><.cc> b,b,u6 00101bbb11011000FBBBuuuuuu1QQQQQ. */ +{ "mult", 0x28D80020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mult<.f> b,b,s12 00101bbb10011000FBBBssssssSSSSSS. */ +{ "mult", 0x28980000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mult<.f> a,limm,c 0010111000011000F111CCCCCCAAAAAA. */ +{ "mult", 0x2E187000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mult<.f> a,b,limm 00101bbb00011000FBBB111110AAAAAA. */ +{ "mult", 0x28180F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mult<.f> 0,limm,c 0010111000011000F111CCCCCC111110. */ +{ "mult", 0x2E18703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mult<.f> 0,b,limm 00101bbb00011000FBBB111110111110. */ +{ "mult", 0x28180FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mult<.f><.cc> 0,limm,c 0010111011011000F111CCCCCC0QQQQQ. */ +{ "mult", 0x2ED87000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mult<.f><.cc> b,b,limm 00101bbb11011000FBBB1111100QQQQQ. */ +{ "mult", 0x28D80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mult<.f> a,limm,u6 0010111001011000F111uuuuuuAAAAAA. */ +{ "mult", 0x2E587000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mult<.f> 0,limm,u6 0010111001011000F111uuuuuu111110. */ +{ "mult", 0x2E58703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mult<.f><.cc> 0,limm,u6 0010111011011000F111uuuuuu1QQQQQ. */ +{ "mult", 0x2ED87020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mult<.f> 0,limm,s12 0010111010011000F111ssssssSSSSSS. */ +{ "mult", 0x2E987000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mult<.f> a,limm,limm 0010111000011000F111111110AAAAAA. */ +{ "mult", 0x2E187F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mult<.f> 0,limm,limm 0010111000011000F111111110111110. */ +{ "mult", 0x2E187FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mult<.f><.cc> 0,limm,limm 0010111011011000F1111111100QQQQQ. */ +{ "mult", 0x2ED87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mulu64 0,b,c 00101bbb000001010BBBCCCCCC111110. */ +{ "mulu64", 0x2805003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* mulu64<.cc> 0,b,c 00101bbb110001010BBBCCCCCC0QQQQQ. */ +{ "mulu64", 0x28C50000, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_CC }}, + +/* mulu64 0,b,u6 00101bbb010001010BBBuuuuuu111110. */ +{ "mulu64", 0x2845003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* mulu64<.cc> 0,b,u6 00101bbb110001010BBBuuuuuu1QQQQQ. */ +{ "mulu64", 0x28C50020, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, + +/* mulu64 0,b,s12 00101bbb100001010BBBssssssSSSSSS. */ +{ "mulu64", 0x28850000, 0xF8FF8000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, + +/* mulu64 0,limm,c 00101110000001010111CCCCCC111110. */ +{ "mulu64", 0x2E05703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* mulu64 0,b,limm 00101bbb000001010BBB111110111110. */ +{ "mulu64", 0x28050FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* mulu64<.cc> 0,limm,c 00101110110001010111CCCCCC0QQQQQ. */ +{ "mulu64", 0x2EC57000, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* mulu64<.cc> 0,b,limm 00101bbb110001010BBB1111100QQQQQ. */ +{ "mulu64", 0x28C50F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_CC }}, + +/* mulu64 0,limm,u6 00101110010001010111uuuuuu111110. */ +{ "mulu64", 0x2E45703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* mulu64<.cc> 0,limm,u6 00101110110001010111uuuuuu1QQQQQ. */ +{ "mulu64", 0x2EC57020, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* mulu64 0,limm,s12 00101110100001010111ssssssSSSSSS. */ +{ "mulu64", 0x2E857000, 0xFFFFF000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* mulu64 0,limm,limm 00101110000001010111111110111110. */ +{ "mulu64", 0x2E057FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* mulu64<.cc> 0,limm,limm 001011101100010101111111100QQQQQ. */ +{ "mulu64", 0x2EC57F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* mulu64 0,b,c 00101bbb000001010BBBCCCCCC111110. */ +{ "mulu64", 0x2805003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* mulu64<.cc> 0,b,c 00101bbb110001010BBBCCCCCC0QQQQQ. */ +{ "mulu64", 0x28C50000, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }}, + +/* mulu64 0,b,u6 00101bbb010001010BBBuuuuuu111110. */ +{ "mulu64", 0x2845003E, 0xF8FF803F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* mulu64<.cc> 0,b,u6 00101bbb110001010BBBuuuuuu1QQQQQ. */ +{ "mulu64", 0x28C50020, 0xF8FF8020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, + +/* mulu64 0,b,s12 00101bbb100001010BBBssssssSSSSSS. */ +{ "mulu64", 0x28850000, 0xF8FF8000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, + +/* mulu64 0,limm,c 00101110000001010111CCCCCC111110. */ +{ "mulu64", 0x2E05703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* mulu64 0,b,limm 00101bbb000001010BBB111110111110. */ +{ "mulu64", 0x28050FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* mulu64<.cc> 0,limm,c 00101110110001010111CCCCCC0QQQQQ. */ +{ "mulu64", 0x2EC57000, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* mulu64<.cc> 0,b,limm 00101bbb110001010BBB1111100QQQQQ. */ +{ "mulu64", 0x28C50F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, + +/* mulu64 0,limm,u6 00101110010001010111uuuuuu111110. */ +{ "mulu64", 0x2E45703E, 0xFFFFF03F, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* mulu64<.cc> 0,limm,u6 00101110110001010111uuuuuu1QQQQQ. */ +{ "mulu64", 0x2EC57020, 0xFFFFF020, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* mulu64 0,limm,s12 00101110100001010111ssssssSSSSSS. */ +{ "mulu64", 0x2E857000, 0xFFFFF000, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* mulu64 0,limm,limm 00101110000001010111111110111110. */ +{ "mulu64", 0x2E057FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* mulu64<.cc> 0,limm,limm 001011101100010101111111100QQQQQ. */ +{ "mulu64", 0x2EC57F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, MPY, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* muludw<.f> a,b,c 00101bbb00001101FBBBCCCCCCAAAAAA. */ +{ "muludw", 0x280D0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* muludw<.f> 0,b,c 00101bbb00001101FBBBCCCCCC111110. */ +{ "muludw", 0x280D003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* muludw<.f><.cc> b,b,c 00101bbb11001101FBBBCCCCCC0QQQQQ. */ +{ "muludw", 0x28CD0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* muludw<.f> a,b,u6 00101bbb01001101FBBBuuuuuuAAAAAA. */ +{ "muludw", 0x284D0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* muludw<.f> 0,b,u6 00101bbb01001101FBBBuuuuuu111110. */ +{ "muludw", 0x284D003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* muludw<.f><.cc> b,b,u6 00101bbb11001101FBBBuuuuuu1QQQQQ. */ +{ "muludw", 0x28CD0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* muludw<.f> b,b,s12 00101bbb10001101FBBBssssssSSSSSS. */ +{ "muludw", 0x288D0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* muludw<.f> a,limm,c 0010111000001101F111CCCCCCAAAAAA. */ +{ "muludw", 0x2E0D7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* muludw<.f> a,b,limm 00101bbb00001101FBBB111110AAAAAA. */ +{ "muludw", 0x280D0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* muludw<.f> 0,limm,c 0010111000001101F111CCCCCC111110. */ +{ "muludw", 0x2E0D703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* muludw<.f> 0,b,limm 00101bbb00001101FBBB111110111110. */ +{ "muludw", 0x280D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* muludw<.f><.cc> 0,limm,c 0010111011001101F111CCCCCC0QQQQQ. */ +{ "muludw", 0x2ECD7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* muludw<.f><.cc> b,b,limm 00101bbb11001101FBBB1111100QQQQQ. */ +{ "muludw", 0x28CD0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* muludw<.f> a,limm,u6 0010111001001101F111uuuuuuAAAAAA. */ +{ "muludw", 0x2E4D7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* muludw<.f> 0,limm,u6 0010111001001101F111uuuuuu111110. */ +{ "muludw", 0x2E4D703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* muludw<.f><.cc> 0,limm,u6 0010111011001101F111uuuuuu1QQQQQ. */ +{ "muludw", 0x2ECD7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* muludw<.f> 0,limm,s12 0010111010001101F111ssssssSSSSSS. */ +{ "muludw", 0x2E8D7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* muludw<.f> a,limm,limm 0010111000001101F111111110AAAAAA. */ +{ "muludw", 0x2E0D7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* muludw<.f> 0,limm,limm 0010111000001101F111111110111110. */ +{ "muludw", 0x2E0D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* muludw<.f><.cc> 0,limm,limm 0010111011001101F1111111100QQQQQ. */ +{ "muludw", 0x2ECD7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mululw<.f> a,b,c 00101bbb00110000FBBBCCCCCCAAAAAA. */ +{ "mululw", 0x28300000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mululw<.f> 0,b,c 00101bbb00110000FBBBCCCCCC111110. */ +{ "mululw", 0x2830003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mululw<.f><.cc> b,b,c 00101bbb11110000FBBBCCCCCC0QQQQQ. */ +{ "mululw", 0x28F00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mululw<.f> a,b,u6 00101bbb01110000FBBBuuuuuuAAAAAA. */ +{ "mululw", 0x28700000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mululw<.f> 0,b,u6 00101bbb01110000FBBBuuuuuu111110. */ +{ "mululw", 0x2870003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mululw<.f><.cc> b,b,u6 00101bbb11110000FBBBuuuuuu1QQQQQ. */ +{ "mululw", 0x28F00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mululw<.f> b,b,s12 00101bbb10110000FBBBssssssSSSSSS. */ +{ "mululw", 0x28B00000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mululw<.f> a,limm,c 0010111000110000F111CCCCCCAAAAAA. */ +{ "mululw", 0x2E307000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mululw<.f> a,b,limm 00101bbb00110000FBBB111110AAAAAA. */ +{ "mululw", 0x28300F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mululw<.f> 0,limm,c 0010111000110000F111CCCCCC111110. */ +{ "mululw", 0x2E30703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mululw<.f> 0,b,limm 00101bbb00110000FBBB111110111110. */ +{ "mululw", 0x28300FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mululw<.f><.cc> 0,limm,c 0010111011110000F111CCCCCC0QQQQQ. */ +{ "mululw", 0x2EF07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mululw<.f><.cc> b,b,limm 00101bbb11110000FBBB1111100QQQQQ. */ +{ "mululw", 0x28F00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mululw<.f> a,limm,u6 0010111001110000F111uuuuuuAAAAAA. */ +{ "mululw", 0x2E707000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mululw<.f> 0,limm,u6 0010111001110000F111uuuuuu111110. */ +{ "mululw", 0x2E70703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mululw<.f><.cc> 0,limm,u6 0010111011110000F111uuuuuu1QQQQQ. */ +{ "mululw", 0x2EF07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mululw<.f> 0,limm,s12 0010111010110000F111ssssssSSSSSS. */ +{ "mululw", 0x2EB07000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mululw<.f> a,limm,limm 0010111000110000F111111110AAAAAA. */ +{ "mululw", 0x2E307F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mululw<.f> 0,limm,limm 0010111000110000F111111110111110. */ +{ "mululw", 0x2E307FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mululw<.f><.cc> 0,limm,limm 0010111011110000F1111111100QQQQQ. */ +{ "mululw", 0x2EF07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* mulut<.f> a,b,c 00101bbb00011001FBBBCCCCCCAAAAAA. */ +{ "mulut", 0x28190000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mulut<.f> 0,b,c 00101bbb00011001FBBBCCCCCC111110. */ +{ "mulut", 0x2819003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* mulut<.f><.cc> b,b,c 00101bbb11011001FBBBCCCCCC0QQQQQ. */ +{ "mulut", 0x28D90000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* mulut<.f> a,b,u6 00101bbb01011001FBBBuuuuuuAAAAAA. */ +{ "mulut", 0x28590000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulut<.f> 0,b,u6 00101bbb01011001FBBBuuuuuu111110. */ +{ "mulut", 0x2859003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulut<.f><.cc> b,b,u6 00101bbb11011001FBBBuuuuuu1QQQQQ. */ +{ "mulut", 0x28D90020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mulut<.f> b,b,s12 00101bbb10011001FBBBssssssSSSSSS. */ +{ "mulut", 0x28990000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* mulut<.f> a,limm,c 0010111000011001F111CCCCCCAAAAAA. */ +{ "mulut", 0x2E197000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mulut<.f> a,b,limm 00101bbb00011001FBBB111110AAAAAA. */ +{ "mulut", 0x28190F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mulut<.f> 0,limm,c 0010111000011001F111CCCCCC111110. */ +{ "mulut", 0x2E19703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* mulut<.f> 0,b,limm 00101bbb00011001FBBB111110111110. */ +{ "mulut", 0x28190FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* mulut<.f><.cc> 0,limm,c 0010111011011001F111CCCCCC0QQQQQ. */ +{ "mulut", 0x2ED97000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* mulut<.f><.cc> b,b,limm 00101bbb11011001FBBB1111100QQQQQ. */ +{ "mulut", 0x28D90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* mulut<.f> a,limm,u6 0010111001011001F111uuuuuuAAAAAA. */ +{ "mulut", 0x2E597000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulut<.f> 0,limm,u6 0010111001011001F111uuuuuu111110. */ +{ "mulut", 0x2E59703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* mulut<.f><.cc> 0,limm,u6 0010111011011001F111uuuuuu1QQQQQ. */ +{ "mulut", 0x2ED97020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* mulut<.f> 0,limm,s12 0010111010011001F111ssssssSSSSSS. */ +{ "mulut", 0x2E997000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* mulut<.f> a,limm,limm 0010111000011001F111111110AAAAAA. */ +{ "mulut", 0x2E197F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mulut<.f> 0,limm,limm 0010111000011001F111111110111110. */ +{ "mulut", 0x2E197FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* mulut<.f><.cc> 0,limm,limm 0010111011011001F1111111100QQQQQ. */ +{ "mulut", 0x2ED97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* neg<.f> a,b 00100bbb01001110FBBB000000AAAAAA. */ +{ "neg", 0x204E0000, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB }, { C_F }}, + +/* neg<.f> 0,b 00100bbb01001110FBBB000000111110. */ +{ "neg", 0x204E0000, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB }, { C_F }}, + +/* neg<.f><.cc> b,b 00100bbb11001110FBBB0000001QQQQQ. */ +{ "neg", 0x20CE0020, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup }, { C_F, C_CC }}, + +/* neg<.f> a,limm 0010011001001110F111000000AAAAAA. */ +{ "neg", 0x264E7000, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM }, { C_F }}, + +/* neg<.f><.cc> 0,limm 0010011011001110F1110000001QQQQQ. */ +{ "neg", 0x26CE7020, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F, C_CC }}, + +/* negs<.f> b,c 00101bbb00101111FBBBCCCCCC000111. */ +{ "negs", 0x282F0007, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* negs<.f> 0,c 0010111000101111F111CCCCCC000111. */ +{ "negs", 0x2E2F7007, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* negs<.f> b,u6 00101bbb01101111FBBBuuuuuu000111. */ +{ "negs", 0x286F0007, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* negs<.f> 0,u6 0010111001101111F111uuuuuu000111. */ +{ "negs", 0x2E6F7007, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* negs<.f> b,limm 00101bbb00101111FBBB111110000111. */ +{ "negs", 0x282F0F87, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* negs<.f> 0,limm 0010111000101111F111111110000111. */ +{ "negs", 0x2E2F7F87, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* negsh<.f> b,c 00101bbb00101111FBBBCCCCCC000110. */ +{ "negsh", 0x282F0006, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { C_F }}, + +/* negsh<.f> 0,c 0010111000101111F111CCCCCC000110. */ +{ "negsh", 0x2E2F7006, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* negsh<.f> b,u6 00101bbb01101111FBBBuuuuuu000110. */ +{ "negsh", 0x286F0006, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { C_F }}, + +/* negsh<.f> 0,u6 0010111001101111F111uuuuuu000110. */ +{ "negsh", 0x2E6F7006, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* negsh<.f> b,limm 00101bbb00101111FBBB111110000110. */ +{ "negsh", 0x282F0F86, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { C_F }}, + +/* negsh<.f> 0,limm 0010111000101111F111111110000110. */ +{ "negsh", 0x2E2F7F86, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* negsw<.f> b,c 00101bbb00101111FBBBCCCCCC000110. */ +{ "negsw", 0x282F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* negsw<.f> 0,c 0010111000101111F111CCCCCC000110. */ +{ "negsw", 0x2E2F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* negsw<.f> b,u6 00101bbb01101111FBBBuuuuuu000110. */ +{ "negsw", 0x286F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* negsw<.f> 0,u6 0010111001101111F111uuuuuu000110. */ +{ "negsw", 0x2E6F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* negsw<.f> b,limm 00101bbb00101111FBBB111110000110. */ +{ "negsw", 0x282F0F86, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* negsw<.f> 0,limm 0010111000101111F111111110000110. */ +{ "negsw", 0x2E2F7F86, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* neg_s b,c 01111bbbccc10011. */ +{ "neg_s", 0x00007813, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, + +/* nop_s 0111100011100000. */ +{ "nop_s", 0x000078E0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }}, + +/* norm<.f> b,c 00101bbb00101111FBBBCCCCCC000001. */ +{ "norm", 0x282F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* norm<.f> 0,c 0010111000101111F111CCCCCC000001. */ +{ "norm", 0x2E2F7001, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* norm<.f> b,u6 00101bbb01101111FBBBuuuuuu000001. */ +{ "norm", 0x286F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* norm<.f> 0,u6 0010111001101111F111uuuuuu000001. */ +{ "norm", 0x2E6F7001, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* norm<.f> b,limm 00101bbb00101111FBBB111110000001. */ +{ "norm", 0x282F0F81, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* norm<.f> 0,limm 0010111000101111F111111110000001. */ +{ "norm", 0x2E2F7F81, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* normacc b,c 00101bbb001011110BBBCCCCCC011001. */ +{ "normacc", 0x282F0019, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, + +/* normacc 0,c 00101110001011110111CCCCCC011001. */ +{ "normacc", 0x2E2F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, + +/* normacc b,u6 00101bbb011011110BBBuuuuuu011001. */ +{ "normacc", 0x286F0019, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, + +/* normacc 0,u6 00101110011011110111uuuuuu011001. */ +{ "normacc", 0x2E6F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, + +/* normacc b,limm 00101bbb001011110BBB111110011001. */ +{ "normacc", 0x282F0F99, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, + +/* normacc 0,limm 00101110001011110111111110011001. */ +{ "normacc", 0x2E2F7F99, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, + +/* normh<.f> b,c 00101bbb00101111FBBBCCCCCC001000. */ +{ "normh", 0x282F0008, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* normh<.f> 0,c 0010111000101111F111CCCCCC001000. */ +{ "normh", 0x2E2F7008, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* normh<.f> b,u6 00101bbb01101111FBBBuuuuuu001000. */ +{ "normh", 0x286F0008, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* normh<.f> 0,u6 0010111001101111F111uuuuuu001000. */ +{ "normh", 0x2E6F7008, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* normh<.f> b,limm 00101bbb00101111FBBB111110001000. */ +{ "normh", 0x282F0F88, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* normh<.f> 0,limm 0010111000101111F111111110001000. */ +{ "normh", 0x2E2F7F88, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* normw<.f> b,c 00101bbb00101111FBBBCCCCCC001000. */ +{ "normw", 0x282F0008, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* normw<.f> 0,c 0010111000101111F111CCCCCC001000. */ +{ "normw", 0x2E2F7008, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* normw<.f> b,u6 00101bbb01101111FBBBuuuuuu001000. */ +{ "normw", 0x286F0008, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* normw<.f> 0,u6 0010111001101111F111uuuuuu001000. */ +{ "normw", 0x2E6F7008, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* normw<.f> b,limm 00101bbb00101111FBBB111110001000. */ +{ "normw", 0x282F0F88, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* normw<.f> 0,limm 0010111000101111F111111110001000. */ +{ "normw", 0x2E2F7F88, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* not<.f> b,c 00100bbb00101111FBBBCCCCCC001010. */ +{ "not", 0x202F000A, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* not<.f> 0,c 0010011000101111F111CCCCCC001010. */ +{ "not", 0x262F700A, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* not<.f> b,u6 00100bbb01101111FBBBuuuuuu001010. */ +{ "not", 0x206F000A, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* not<.f> 0,u6 0010011001101111F111uuuuuu001010. */ +{ "not", 0x266F700A, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* not<.f> b,limm 00100bbb00101111FBBB111110001010. */ +{ "not", 0x202F0F8A, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* not<.f> 0,limm 0010011000101111F111111110001010. */ +{ "not", 0x262F7F8A, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* not_s b,c 01111bbbccc10010. */ +{ "not_s", 0x00007812, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, + +/* or<.f> a,b,c 00100bbb00000101FBBBCCCCCCAAAAAA. */ +{ "or", 0x20050000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* or<.f> 0,b,c 00100bbb00000101FBBBCCCCCC111110. */ +{ "or", 0x2005003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* or<.f><.cc> b,b,c 00100bbb11000101FBBBCCCCCC0QQQQQ. */ +{ "or", 0x20C50000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* or<.f> a,b,u6 00100bbb01000101FBBBuuuuuuAAAAAA. */ +{ "or", 0x20450000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* or<.f> 0,b,u6 00100bbb01000101FBBBuuuuuu111110. */ +{ "or", 0x2045003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* or<.f><.cc> b,b,u6 00100bbb11000101FBBBuuuuuu1QQQQQ. */ +{ "or", 0x20C50020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* or<.f> b,b,s12 00100bbb10000101FBBBssssssSSSSSS. */ +{ "or", 0x20850000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* or<.f> a,limm,c 0010011000000101F111CCCCCCAAAAAA. */ +{ "or", 0x26057000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* or<.f> a,b,limm 00100bbb00000101FBBB111110AAAAAA. */ +{ "or", 0x20050F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* or<.f> 0,limm,c 0010011000000101F111CCCCCC111110. */ +{ "or", 0x2605703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* or<.f> 0,b,limm 00100bbb00000101FBBB111110111110. */ +{ "or", 0x20050FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* or<.f><.cc> b,b,limm 00100bbb11000101FBBB1111100QQQQQ. */ +{ "or", 0x20C50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* or<.f><.cc> 0,limm,c 0010011011000101F111CCCCCC0QQQQQ. */ +{ "or", 0x26C57000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* or<.f> a,limm,u6 0010011001000101F111uuuuuuAAAAAA. */ +{ "or", 0x26457000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* or<.f> 0,limm,u6 0010011001000101F111uuuuuu111110. */ +{ "or", 0x2645703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* or<.f><.cc> 0,limm,u6 0010011011000101F111uuuuuu1QQQQQ. */ +{ "or", 0x26C57020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* or<.f> 0,limm,s12 0010011010000101F111ssssssSSSSSS. */ +{ "or", 0x26857000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* or<.f> a,limm,limm 0010011000000101F111111110AAAAAA. */ +{ "or", 0x26057F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* or<.f> 0,limm,limm 0010011000000101F111111110111110. */ +{ "or", 0x26057FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* or<.f><.cc> 0,limm,limm 0010011011000101F1111111100QQQQQ. */ +{ "or", 0x26C57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* or_s b,b,c 01111bbbccc00101. */ +{ "or_s", 0x00007805, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, + +/* pkqb<.f> a,b,c 00110bbb00100000FBBBCCCCCCAAAAAA. */ +{ "pkqb", 0x30200000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* pkqb<.f><.cc> b,b,c 00110bbb11100000FBBBCCCCCC0QQQQQ. */ +{ "pkqb", 0x30E00000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* pkqb<.f> a,b,u6 00110bbb01100000FBBBuuuuuuAAAAAA. */ +{ "pkqb", 0x30600000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* pkqb<.f><.cc> b,b,u6 00110bbb11100000FBBBuuuuuu1QQQQQ. */ +{ "pkqb", 0x30E00020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* pkqb<.f> b,b,s12 00110bbb10100000FBBBssssssSSSSSS. */ +{ "pkqb", 0x30A00000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* pkqb<.f> a,limm,c 0011011000100000F111CCCCCCAAAAAA. */ +{ "pkqb", 0x36207000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* pkqb<.f> a,b,limm 00110bbb00100000FBBB111110AAAAAA. */ +{ "pkqb", 0x30200F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* pkqb<.f><.cc> b,b,limm 00110bbb11100000FBBB1111100QQQQQ. */ +{ "pkqb", 0x30E00F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* pop_s b 11000bbb11000001. */ +{ "pop_s", 0x0000C0C1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, POP, NONE, { OPERAND_RB_S }, { C_AA_AB }}, + +/* pop_s OPERAND_BLINK 11000RRR11010001. */ +{ "pop_s", 0x0000C0D1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, POP, NONE, { OPERAND_BLINK_S }, { C_AA_AB }}, + +/* push_s b 11000bbb11100001. */ +{ "push_s", 0x0000C0E1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, PUSH, NONE, { OPERAND_RB_S }, { C_AA_AW }}, + +/* push_s blink 11000RRR11110001. */ +{ "push_s", 0x0000C0F1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, PUSH, NONE, { OPERAND_BLINK_S }, { C_AA_AW }}, + +/* qmach<.f> a,b,c 00101bbb00110100FBBBCCCCCCAAAAAA. */ +{ "qmach", 0x28340000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* qmach<.f> 0,b,c 00101bbb00110100FBBBCCCCCC111110. */ +{ "qmach", 0x2834003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* qmach<.f><.cc> b,b,c 00101bbb11110100FBBBCCCCCC0QQQQQ. */ +{ "qmach", 0x28F40000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* qmach<.f> a,b,u6 00101bbb01110100FBBBuuuuuuAAAAAA. */ +{ "qmach", 0x28740000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmach<.f> 0,b,u6 00101bbb01110100FBBBuuuuuu111110. */ +{ "qmach", 0x2874003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmach<.f><.cc> b,b,u6 00101bbb11110100FBBBuuuuuu1QQQQQ. */ +{ "qmach", 0x28F40020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* qmach<.f> b,b,s12 00101bbb10110100FBBBssssssSSSSSS. */ +{ "qmach", 0x28B40000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* qmach<.f> a,limm,c 0010111000110100F111CCCCCCAAAAAA. */ +{ "qmach", 0x2E347000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* qmach<.f> a,b,limm 00101bbb00110100FBBB111110AAAAAA. */ +{ "qmach", 0x28340F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* qmach<.f> 0,limm,c 0010111000110100F111CCCCCC111110. */ +{ "qmach", 0x2E34703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* qmach<.f> 0,b,limm 00101bbb00110100FBBB111110111110. */ +{ "qmach", 0x28340FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* qmach<.f><.cc> b,b,limm 00101bbb11110100FBBB1111100QQQQQ. */ +{ "qmach", 0x28F40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* qmach<.f><.cc> 0,limm,c 0010111011110100F111CCCCCC0QQQQQ. */ +{ "qmach", 0x2EF47000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* qmach<.f> a,limm,u6 0010111001110100F111uuuuuuAAAAAA. */ +{ "qmach", 0x2E747000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmach<.f> 0,limm,u6 0010111001110100F111uuuuuu111110. */ +{ "qmach", 0x2E74703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmach<.f><.cc> 0,limm,u6 0010111011110100F111uuuuuu1QQQQQ. */ +{ "qmach", 0x2EF47020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* qmach<.f> 0,limm,s12 0010111010110100F111ssssssSSSSSS. */ +{ "qmach", 0x2EB47000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* qmach<.f> a,limm,limm 0010111000110100F111111110AAAAAA. */ +{ "qmach", 0x2E347F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* qmach<.f> 0,limm,limm 0010111000110100F111111110111110. */ +{ "qmach", 0x2E347FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* qmach<.f><.cc> 0,limm,limm 0010111011110100F1111111100QQQQQ. */ +{ "qmach", 0x2EF47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* qmachf<.f> 0,b,c 00110bbb00110101FBBBCCCCCC111110 */ +{ "qmachf", 0x3035003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* qmachf<.f> a,b,c 00110bbb00110101FBBBCCCCCCAAAAAA */ +{ "qmachf", 0x30350000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* qmachf<.f><.cc> b,b,c 00110bbb11110101FBBBCCCCCC0QQQQQ */ +{ "qmachf", 0x30F50000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* qmachf<.f> 0,b,u6 00110bbb01110101FBBBuuuuuu111110 */ +{ "qmachf", 0x3075003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmachf<.f> a,b,u6 00110bbb01110101FBBBuuuuuuAAAAAA */ +{ "qmachf", 0x30750000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmachf<.f><.cc> b,b,u6 00110bbb11110101FBBBuuuuuu1QQQQQ */ +{ "qmachf", 0x30F50020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* qmachf<.f> b,b,s12 00110bbb10110101FBBBssssssSSSSSS */ +{ "qmachf", 0x30B50000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* qmachf<.f> 0,b,limm 00110bbb00110101FBBB111110111110 */ +{ "qmachf", 0x30350FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* qmachf<.f><.cc> b,b,limm 00110bbb11110101FBBB1111100QQQQQ */ +{ "qmachf", 0x30F50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* qmachf<.f> a,limm,c 0011011000110101F111CCCCCCAAAAAA */ +{ "qmachf", 0x36357000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* qmachf<.f><.cc> 0,limm,c 0011011011110101F111CCCCCC0QQQQQ */ +{ "qmachf", 0x36F57000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* qmachf<.f> 0,limm,c 0011011000110101F111CCCCCC111110 */ +{ "qmachf", 0x3635703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* qmachf<.f> a,b,limm 00110bbb00110101FBBB111110AAAAAA */ +{ "qmachf", 0x30350F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* qmachf<.f><.cc> 0,limm,u6 0011011011110101F111uuuuuu1QQQQQ */ +{ "qmachf", 0x36F57020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* qmachf<.f> a,limm,u6 0011011001110101F111uuuuuuAAAAAA */ +{ "qmachf", 0x36757000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmachf<.f> 0,limm,u6 0011011001110101F111uuuuuu111110 */ +{ "qmachf", 0x3675703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmachf<.f> 0,limm,s12 0011011010110101F111ssssssSSSSSS */ +{ "qmachf", 0x36B57000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* qmachf<.f> a,limm,limm 0011011000110101F111111110AAAAAA */ +{ "qmachf", 0x36357F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* qmachf<.f><.cc> 0,limm,limm 0011011011110101F1111111100QQQQQ */ +{ "qmachf", 0x36F57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* qmachf<.f> 0,limm,limm 0011011000110101F111111110111110 */ +{ "qmachf", 0x36357FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* qmachu<.f> a,b,c 00101bbb00110101FBBBCCCCCCAAAAAA. */ +{ "qmachu", 0x28350000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* qmachu<.f> 0,b,c 00101bbb00110101FBBBCCCCCC111110. */ +{ "qmachu", 0x2835003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* qmachu<.f><.cc> b,b,c 00101bbb11110101FBBBCCCCCC0QQQQQ. */ +{ "qmachu", 0x28F50000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* qmachu<.f> a,b,u6 00101bbb01110101FBBBuuuuuuAAAAAA. */ +{ "qmachu", 0x28750000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmachu<.f> 0,b,u6 00101bbb01110101FBBBuuuuuu111110. */ +{ "qmachu", 0x2875003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmachu<.f><.cc> b,b,u6 00101bbb11110101FBBBuuuuuu1QQQQQ. */ +{ "qmachu", 0x28F50020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* qmachu<.f> b,b,s12 00101bbb10110101FBBBssssssSSSSSS. */ +{ "qmachu", 0x28B50000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* qmachu<.f> a,limm,c 0010111000110101F111CCCCCCAAAAAA. */ +{ "qmachu", 0x2E357000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* qmachu<.f> a,b,limm 00101bbb00110101FBBB111110AAAAAA. */ +{ "qmachu", 0x28350F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* qmachu<.f> 0,limm,c 0010111000110101F111CCCCCC111110. */ +{ "qmachu", 0x2E35703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* qmachu<.f> 0,b,limm 00101bbb00110101FBBB111110111110. */ +{ "qmachu", 0x28350FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* qmachu<.f><.cc> b,b,limm 00101bbb11110101FBBB1111100QQQQQ. */ +{ "qmachu", 0x28F50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* qmachu<.f><.cc> 0,limm,c 0010111011110101F111CCCCCC0QQQQQ. */ +{ "qmachu", 0x2EF57000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* qmachu<.f> a,limm,u6 0010111001110101F111uuuuuuAAAAAA. */ +{ "qmachu", 0x2E757000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmachu<.f> 0,limm,u6 0010111001110101F111uuuuuu111110. */ +{ "qmachu", 0x2E75703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmachu<.f><.cc> 0,limm,u6 0010111011110101F111uuuuuu1QQQQQ. */ +{ "qmachu", 0x2EF57020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* qmachu<.f> 0,limm,s12 0010111010110101F111ssssssSSSSSS. */ +{ "qmachu", 0x2EB57000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* qmachu<.f> a,limm,limm 0010111000110101F111111110AAAAAA. */ +{ "qmachu", 0x2E357F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* qmachu<.f> 0,limm,limm 0010111000110101F111111110111110. */ +{ "qmachu", 0x2E357FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* qmachu<.f><.cc> 0,limm,limm 0010111011110101F1111111100QQQQQ. */ +{ "qmachu", 0x2EF57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* qmpyh<.f> a,b,c 00101bbb00110000FBBBCCCCCCAAAAAA. */ +{ "qmpyh", 0x28300000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* qmpyh<.f> 0,b,c 00101bbb00110000FBBBCCCCCC111110. */ +{ "qmpyh", 0x2830003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* qmpyh<.f><.cc> b,b,c 00101bbb11110000FBBBCCCCCC0QQQQQ. */ +{ "qmpyh", 0x28F00000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* qmpyh<.f> a,b,u6 00101bbb01110000FBBBuuuuuuAAAAAA. */ +{ "qmpyh", 0x28700000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmpyh<.f> 0,b,u6 00101bbb01110000FBBBuuuuuu111110. */ +{ "qmpyh", 0x2870003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmpyh<.f><.cc> b,b,u6 00101bbb11110000FBBBuuuuuu1QQQQQ. */ +{ "qmpyh", 0x28F00020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* qmpyh<.f> b,b,s12 00101bbb10110000FBBBssssssSSSSSS. */ +{ "qmpyh", 0x28B00000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* qmpyh<.f> a,limm,c 0010111000110000F111CCCCCCAAAAAA. */ +{ "qmpyh", 0x2E307000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* qmpyh<.f> a,b,limm 00101bbb00110000FBBB111110AAAAAA. */ +{ "qmpyh", 0x28300F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* qmpyh<.f> 0,limm,c 0010111000110000F111CCCCCC111110. */ +{ "qmpyh", 0x2E30703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* qmpyh<.f> 0,b,limm 00101bbb00110000FBBB111110111110. */ +{ "qmpyh", 0x28300FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* qmpyh<.f><.cc> b,b,limm 00101bbb11110000FBBB1111100QQQQQ. */ +{ "qmpyh", 0x28F00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* qmpyh<.f><.cc> 0,limm,c 0010111011110000F111CCCCCC0QQQQQ. */ +{ "qmpyh", 0x2EF07000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* qmpyh<.f> a,limm,u6 0010111001110000F111uuuuuuAAAAAA. */ +{ "qmpyh", 0x2E707000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmpyh<.f> 0,limm,u6 0010111001110000F111uuuuuu111110. */ +{ "qmpyh", 0x2E70703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmpyh<.f><.cc> 0,limm,u6 0010111011110000F111uuuuuu1QQQQQ. */ +{ "qmpyh", 0x2EF07020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* qmpyh<.f> 0,limm,s12 0010111010110000F111ssssssSSSSSS. */ +{ "qmpyh", 0x2EB07000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* qmpyh<.f> a,limm,limm 0010111000110000F111111110AAAAAA. */ +{ "qmpyh", 0x2E307F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* qmpyh<.f> 0,limm,limm 0010111000110000F111111110111110. */ +{ "qmpyh", 0x2E307FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* qmpyh<.f><.cc> 0,limm,limm 0010111011110000F1111111100QQQQQ. */ +{ "qmpyh", 0x2EF07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* qmpyh<.f> a,limm,limm 0010111000110000F111111110AAAAAA */ +{ "qmpyh", 0x2E307F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* qmpyhf<.f><.cc> b,b,c 00110bbb11110001FBBBCCCCCC0QQQQQ */ +{ "qmpyhf", 0x30F10000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* qmpyhf<.f> a,b,c 00110bbb00110001FBBBCCCCCCAAAAAA */ +{ "qmpyhf", 0x30310000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* qmpyhf<.f> 0,b,c 00110bbb00110001FBBBCCCCCC111110 */ +{ "qmpyhf", 0x3031003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* qmpyhf<.f><.cc> b,b,u6 00110bbb11110001FBBBuuuuuu1QQQQQ */ +{ "qmpyhf", 0x30F10020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* qmpyhf<.f> a,b,u6 00110bbb01110001FBBBuuuuuuAAAAAA */ +{ "qmpyhf", 0x30710000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmpyhf<.f> 0,b,u6 00110bbb01110001FBBBuuuuuu111110 */ +{ "qmpyhf", 0x3071003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmpyhf<.f> b,b,s12 00110bbb10110001FBBBssssssSSSSSS */ +{ "qmpyhf", 0x30B10000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* qmpyhf<.f> 0,limm,c 0011011000110001F111CCCCCC111110 */ +{ "qmpyhf", 0x3631703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* qmpyhf<.f> a,b,limm 00110bbb00110001FBBB111110AAAAAA */ +{ "qmpyhf", 0x30310F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* qmpyhf<.f> a,limm,c 0011011000110001F111CCCCCCAAAAAA */ +{ "qmpyhf", 0x36317000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* qmpyhf<.f> 0,b,limm 00110bbb00110001FBBB111110111110 */ +{ "qmpyhf", 0x30310FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* qmpyhf<.f><.cc> b,b,limm 00110bbb11110001FBBB1111100QQQQQ */ +{ "qmpyhf", 0x30F10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* qmpyhf<.f><.cc> 0,limm,c 0011011011110001F111CCCCCC0QQQQQ */ +{ "qmpyhf", 0x36F17000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* qmpyhf<.f> a,limm,u6 0011011001110001F111uuuuuuAAAAAA */ +{ "qmpyhf", 0x36717000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmpyhf<.f> 0,limm,u6 0011011001110001F111uuuuuu111110 */ +{ "qmpyhf", 0x3671703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmpyhf<.f><.cc> 0,limm,u6 0011011011110001F111uuuuuu1QQQQQ */ +{ "qmpyhf", 0x36F17020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* qmpyhf<.f> 0,limm,s12 0011011010110001F111ssssssSSSSSS */ +{ "qmpyhf", 0x36B17000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* qmpyhf<.f><.cc> 0,limm,limm 0011011011110001F1111111100QQQQQ */ +{ "qmpyhf", 0x36F17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* qmpyhf<.f> a,limm,limm 0011011000110001F111111110AAAAAA */ +{ "qmpyhf", 0x36317F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* qmpyhf<.f> 0,limm,limm 0011011000110001F111111110111110 */ +{ "qmpyhf", 0x36317FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* qmpyhu<.f> a,b,c 00101bbb00110001FBBBCCCCCCAAAAAA. */ +{ "qmpyhu", 0x28310000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* qmpyhu<.f> 0,b,c 00101bbb00110001FBBBCCCCCC111110. */ +{ "qmpyhu", 0x2831003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* qmpyhu<.f><.cc> b,b,c 00101bbb11110001FBBBCCCCCC0QQQQQ. */ +{ "qmpyhu", 0x28F10000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* qmpyhu<.f> a,b,u6 00101bbb01110001FBBBuuuuuuAAAAAA. */ +{ "qmpyhu", 0x28710000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmpyhu<.f> 0,b,u6 00101bbb01110001FBBBuuuuuu111110. */ +{ "qmpyhu", 0x2871003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmpyhu<.f><.cc> b,b,u6 00101bbb11110001FBBBuuuuuu1QQQQQ. */ +{ "qmpyhu", 0x28F10020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* qmpyhu<.f> b,b,s12 00101bbb10110001FBBBssssssSSSSSS. */ +{ "qmpyhu", 0x28B10000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* qmpyhu<.f> a,limm,c 0010111000110001F111CCCCCCAAAAAA. */ +{ "qmpyhu", 0x2E317000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* qmpyhu<.f> a,b,limm 00101bbb00110001FBBB111110AAAAAA. */ +{ "qmpyhu", 0x28310F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* qmpyhu<.f> 0,limm,c 0010111000110001F111CCCCCC111110. */ +{ "qmpyhu", 0x2E31703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* qmpyhu<.f> 0,b,limm 00101bbb00110001FBBB111110111110. */ +{ "qmpyhu", 0x28310FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* qmpyhu<.f><.cc> b,b,limm 00101bbb11110001FBBB1111100QQQQQ. */ +{ "qmpyhu", 0x28F10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* qmpyhu<.f><.cc> 0,limm,c 0010111011110001F111CCCCCC0QQQQQ. */ +{ "qmpyhu", 0x2EF17000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* qmpyhu<.f> a,limm,u6 0010111001110001F111uuuuuuAAAAAA. */ +{ "qmpyhu", 0x2E717000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmpyhu<.f> 0,limm,u6 0010111001110001F111uuuuuu111110. */ +{ "qmpyhu", 0x2E71703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* qmpyhu<.f><.cc> 0,limm,u6 0010111011110001F111uuuuuu1QQQQQ. */ +{ "qmpyhu", 0x2EF17020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* qmpyhu<.f> 0,limm,s12 0010111010110001F111ssssssSSSSSS. */ +{ "qmpyhu", 0x2EB17000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* qmpyhu<.f> a,limm,limm 0010111000110001F111111110AAAAAA. */ +{ "qmpyhu", 0x2E317F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* qmpyhu<.f> 0,limm,limm 0010111000110001F111111110111110. */ +{ "qmpyhu", 0x2E317FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* qmpyhu<.f><.cc> 0,limm,limm 0010111011110001F1111111100QQQQQ. */ +{ "qmpyhu", 0x2EF17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* rcmp b,c 00100bbb000011011BBBCCCCCCRRRRRR. */ +{ "rcmp", 0x200D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* rcmp b,c 00100bbb000011011BBBCCCCCC000000. */ +{ "rcmp", 0x200D8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* rcmp<.cc> b,c 00100bbb110011011BBBCCCCCC0QQQQQ. */ +{ "rcmp", 0x20CD8000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }}, + +/* rcmp b,u6 00100bbb010011011BBBuuuuuuRRRRRR. */ +{ "rcmp", 0x204D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* rcmp b,u6 00100bbb010011011BBBuuuuuu000000. */ +{ "rcmp", 0x204D8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* rcmp<.cc> b,u6 00100bbb110011011BBBuuuuuu1QQQQQ. */ +{ "rcmp", 0x20CD8020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, + +/* rcmp b,s12 00100bbb100011011BBBssssssSSSSSS. */ +{ "rcmp", 0x208D8000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, + +/* rcmp limm,c 00100110000011011111CCCCCCRRRRRR. */ +{ "rcmp", 0x260DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* rcmp b,limm 00100bbb000011011BBB111110RRRRRR. */ +{ "rcmp", 0x200D8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* rcmp limm,c 00100110000011011111CCCCCC000000. */ +{ "rcmp", 0x260DF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* rcmp b,limm 00100bbb000011011BBB111110000000. */ +{ "rcmp", 0x200D8F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* rcmp<.cc> limm,c 00100110110011011111CCCCCC0QQQQQ. */ +{ "rcmp", 0x26CDF000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* rcmp<.cc> b,limm 00100bbb110011011BBB1111100QQQQQ. */ +{ "rcmp", 0x20CD8F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, + +/* rcmp limm,u6 00100110010011011111uuuuuuRRRRRR. */ +{ "rcmp", 0x264DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* rcmp limm,u6 00100110010011011111uuuuuu000000. */ +{ "rcmp", 0x264DF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* rcmp<.cc> limm,u6 00100110110011011111uuuuuu1QQQQQ. */ +{ "rcmp", 0x26CDF020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* rcmp limm,s12 00100110100011011111ssssssSSSSSS. */ +{ "rcmp", 0x268DF000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* rcmp limm,limm 00100110000011011111111110RRRRRR. */ +{ "rcmp", 0x260DFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* rcmp limm,limm 00100110000011011111111110000000. */ +{ "rcmp", 0x260DFF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* rcmp<.cc> limm,limm 001001101100110111111111100QQQQQ. */ +{ "rcmp", 0x26CDFF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* rem<.f> a,b,c 00101bbb00001000FBBBCCCCCCAAAAAA. */ +{ "rem", 0x28080000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* rem<.f> 0,b,c 00101bbb00001000FBBBCCCCCC111110. */ +{ "rem", 0x2808003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* rem<.f><.cc> b,b,c 00101bbb11001000FBBBCCCCCC0QQQQQ. */ +{ "rem", 0x28C80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* rem<.f> a,b,u6 00101bbb01001000FBBBuuuuuuAAAAAA. */ +{ "rem", 0x28480000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* rem<.f> 0,b,u6 00101bbb01001000FBBBuuuuuu111110. */ +{ "rem", 0x2848003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* rem<.f><.cc> b,b,u6 00101bbb11001000FBBBuuuuuu1QQQQQ. */ +{ "rem", 0x28C80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* rem<.f> b,b,s12 00101bbb10001000FBBBssssssSSSSSS. */ +{ "rem", 0x28880000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* rem<.f> a,limm,c 0010111000001000F111CCCCCCAAAAAA. */ +{ "rem", 0x2E087000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* rem<.f> a,b,limm 00101bbb00001000FBBB111110AAAAAA. */ +{ "rem", 0x28080F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* rem<.f> 0,limm,c 0010111000001000F111CCCCCC111110. */ +{ "rem", 0x2E08703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* rem<.f> 0,b,limm 00101bbb00001000FBBB111110111110. */ +{ "rem", 0x28080FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* rem<.f><.cc> b,b,limm 00101bbb11001000FBBB1111100QQQQQ. */ +{ "rem", 0x28C80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* rem<.f><.cc> 0,limm,c 0010111011001000F111CCCCCC0QQQQQ. */ +{ "rem", 0x2EC87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* rem<.f> a,limm,u6 0010111001001000F111uuuuuuAAAAAA. */ +{ "rem", 0x2E487000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* rem<.f> 0,limm,u6 0010111001001000F111uuuuuu111110. */ +{ "rem", 0x2E48703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* rem<.f><.cc> 0,limm,u6 0010111011001000F111uuuuuu1QQQQQ. */ +{ "rem", 0x2EC87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* rem<.f> 0,limm,s12 0010111010001000F111ssssssSSSSSS. */ +{ "rem", 0x2E887000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* rem<.f> a,limm,limm 0010111000001000F111111110AAAAAA. */ +{ "rem", 0x2E087F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* rem<.f> 0,limm,limm 0010111000001000F111111110111110. */ +{ "rem", 0x2E087FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* rem<.f><.cc> 0,limm,limm 0010111011001000F1111111100QQQQQ. */ +{ "rem", 0x2EC87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* remu<.f> a,b,c 00101bbb00001001FBBBCCCCCCAAAAAA. */ +{ "remu", 0x28090000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* remu<.f> 0,b,c 00101bbb00001001FBBBCCCCCC111110. */ +{ "remu", 0x2809003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* remu<.f><.cc> b,b,c 00101bbb11001001FBBBCCCCCC0QQQQQ. */ +{ "remu", 0x28C90000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* remu<.f> a,b,u6 00101bbb01001001FBBBuuuuuuAAAAAA. */ +{ "remu", 0x28490000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* remu<.f> 0,b,u6 00101bbb01001001FBBBuuuuuu111110. */ +{ "remu", 0x2849003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* remu<.f><.cc> b,b,u6 00101bbb11001001FBBBuuuuuu1QQQQQ. */ +{ "remu", 0x28C90020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* remu<.f> b,b,s12 00101bbb10001001FBBBssssssSSSSSS. */ +{ "remu", 0x28890000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* remu<.f> a,limm,c 0010111000001001F111CCCCCCAAAAAA. */ +{ "remu", 0x2E097000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* remu<.f> a,b,limm 00101bbb00001001FBBB111110AAAAAA. */ +{ "remu", 0x28090F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* remu<.f> 0,limm,c 0010111000001001F111CCCCCC111110. */ +{ "remu", 0x2E09703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* remu<.f> 0,b,limm 00101bbb00001001FBBB111110111110. */ +{ "remu", 0x28090FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* remu<.f><.cc> b,b,limm 00101bbb11001001FBBB1111100QQQQQ. */ +{ "remu", 0x28C90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* remu<.f><.cc> 0,limm,c 0010111011001001F111CCCCCC0QQQQQ. */ +{ "remu", 0x2EC97000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* remu<.f> a,limm,u6 0010111001001001F111uuuuuuAAAAAA. */ +{ "remu", 0x2E497000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* remu<.f> 0,limm,u6 0010111001001001F111uuuuuu111110. */ +{ "remu", 0x2E49703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* remu<.f><.cc> 0,limm,u6 0010111011001001F111uuuuuu1QQQQQ. */ +{ "remu", 0x2EC97020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* remu<.f> 0,limm,s12 0010111010001001F111ssssssSSSSSS. */ +{ "remu", 0x2E897000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* remu<.f> a,limm,limm 0010111000001001F111111110AAAAAA. */ +{ "remu", 0x2E097F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* remu<.f> 0,limm,limm 0010111000001001F111111110111110. */ +{ "remu", 0x2E097FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* remu<.f><.cc> 0,limm,limm 0010111011001001F1111111100QQQQQ. */ +{ "remu", 0x2EC97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DIVREM, DIV, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* rlc<.f> b,c 00100bbb00101111FBBBCCCCCC001011. */ +{ "rlc", 0x202F000B, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* rlc<.f> 0,c 0010011000101111F111CCCCCC001011. */ +{ "rlc", 0x262F700B, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* rlc<.f> b,u6 00100bbb01101111FBBBuuuuuu001011. */ +{ "rlc", 0x206F000B, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* rlc<.f> 0,u6 0010011001101111F111uuuuuu001011. */ +{ "rlc", 0x266F700B, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* rlc<.f> b,limm 00100bbb00101111FBBB111110001011. */ +{ "rlc", 0x202F0F8B, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* rlc<.f> 0,limm 0010011000101111F111111110001011. */ +{ "rlc", 0x262F7F8B, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* rnd16<.f> b,c 00101bbb00101111FBBBCCCCCC000011. */ +{ "rnd16", 0x282F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* rnd16<.f> 0,c 0010111000101111F111CCCCCC000011. */ +{ "rnd16", 0x2E2F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* rnd16<.f> b,u6 00101bbb01101111FBBBuuuuuu000011. */ +{ "rnd16", 0x286F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* rnd16<.f> 0,u6 0010111001101111F111uuuuuu000011. */ +{ "rnd16", 0x2E6F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* rnd16<.f> b,limm 00101bbb00101111FBBB111110000011. */ +{ "rnd16", 0x282F0F83, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* rnd16<.f> 0,limm 0010111000101111F111111110000011. */ +{ "rnd16", 0x2E2F7F83, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* rndh<.f> b,c 00101bbb00101111FBBBCCCCCC000011. */ +{ "rndh", 0x282F0003, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { C_F }}, + +/* rndh<.f> 0,c 0010111000101111F111CCCCCC000011. */ +{ "rndh", 0x2E2F7003, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* rndh<.f> b,u6 00101bbb01101111FBBBuuuuuu000011. */ +{ "rndh", 0x286F0003, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { C_F }}, + +/* rndh<.f> 0,u6 0010111001101111F111uuuuuu000011. */ +{ "rndh", 0x2E6F7003, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* rndh<.f> b,limm 00101bbb00101111FBBB111110000011. */ +{ "rndh", 0x282F0F83, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { C_F }}, + +/* rndh<.f> 0,limm 0010111000101111F111111110000011. */ +{ "rndh", 0x2E2F7F83, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* rol<.f> b,c 00100bbb00101111FBBBCCCCCC001101. */ +{ "rol", 0x202F000D, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* rol<.f> 0,c 0010011000101111F111CCCCCC001101. */ +{ "rol", 0x262F700D, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* rol<.f> b,u6 00100bbb01101111FBBBuuuuuu001101. */ +{ "rol", 0x206F000D, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* rol<.f> 0,u6 0010011001101111F111uuuuuu001101. */ +{ "rol", 0x266F700D, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* rol<.f> b,limm 00100bbb00101111FBBB111110001101. */ +{ "rol", 0x202F0F8D, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* rol<.f> 0,limm 0010011000101111F111111110001101. */ +{ "rol", 0x262F7F8D, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* rol8<.f> b,c 00101bbb00101111FBBBCCCCCC010000. */ +{ "rol8", 0x282F0010, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* rol8<.f> 0,c 0010111000101111F111CCCCCC010000. */ +{ "rol8", 0x2E2F7010, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* rol8<.f> b,u6 00101bbb01101111FBBBuuuuuu010000. */ +{ "rol8", 0x286F0010, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* rol8<.f> 0,u6 0010111001101111F111uuuuuu010000. */ +{ "rol8", 0x2E6F7010, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* rol8<.f> b,limm 00101bbb00101111FBBB111110010000. */ +{ "rol8", 0x282F0F90, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* rol8<.f> 0,limm 0010111000101111F111111110010000. */ +{ "rol8", 0x2E2F7F90, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* ror<.f> b,c 00100bbb00101111FBBBCCCCCC000011. */ +{ "ror", 0x202F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* ror<.f> 0,c 0010011000101111F111CCCCCC000011. */ +{ "ror", 0x262F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* ror<.f> a,b,c 00101bbb00000011FBBBCCCCCCAAAAAA. */ +{ "ror", 0x28030000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* ror<.f> 0,b,c 00101bbb00000011FBBBCCCCCC111110. */ +{ "ror", 0x2803003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* ror<.f><.cc> b,b,c 00101bbb11000011FBBBCCCCCC0QQQQQ. */ +{ "ror", 0x28C30000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* ror<.f> b,u6 00100bbb01101111FBBBuuuuuu000011. */ +{ "ror", 0x206F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* ror<.f> 0,u6 0010011001101111F111uuuuuu000011. */ +{ "ror", 0x266F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* ror<.f> a,b,u6 00101bbb01000011FBBBuuuuuuAAAAAA. */ +{ "ror", 0x28430000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* ror<.f> 0,b,u6 00101bbb01000011FBBBuuuuuu111110. */ +{ "ror", 0x2843003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* ror<.f><.cc> b,b,u6 00101bbb11000011FBBBuuuuuu1QQQQQ. */ +{ "ror", 0x28C30020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* ror<.f> b,b,s12 00101bbb10000011FBBBssssssSSSSSS. */ +{ "ror", 0x28830000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* ror<.f> b,limm 00100bbb00101111FBBB111110000011. */ +{ "ror", 0x202F0F83, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* ror<.f> 0,limm 0010011000101111F111111110000011. */ +{ "ror", 0x262F7F83, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* ror<.f> a,limm,c 0010111000000011F111CCCCCCAAAAAA. */ +{ "ror", 0x2E037000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* ror<.f> a,b,limm 00101bbb00000011FBBB111110AAAAAA. */ +{ "ror", 0x28030F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* ror<.f> 0,limm,c 0010111000000011F111CCCCCC111110. */ +{ "ror", 0x2E03703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* ror<.f> 0,b,limm 00101bbb00000011FBBB111110111110. */ +{ "ror", 0x28030FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* ror<.f><.cc> b,b,limm 00101bbb11000011FBBB1111100QQQQQ. */ +{ "ror", 0x28C30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* ror<.f><.cc> 0,limm,c 0010111011000011F111CCCCCC0QQQQQ. */ +{ "ror", 0x2EC37000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* ror<.f> a,limm,u6 0010111001000011F111uuuuuuAAAAAA. */ +{ "ror", 0x2E437000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* ror<.f> 0,limm,u6 0010111001000011F111uuuuuu111110. */ +{ "ror", 0x2E43703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* ror<.f><.cc> 0,limm,u6 0010111011000011F111uuuuuu1QQQQQ. */ +{ "ror", 0x2EC37020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* ror<.f> 0,limm,s12 0010111010000011F111ssssssSSSSSS. */ +{ "ror", 0x2E837000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* ror<.f> a,limm,limm 0010111000000011F111111110AAAAAA. */ +{ "ror", 0x2E037F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* ror<.f> 0,limm,limm 0010111000000011F111111110111110. */ +{ "ror", 0x2E037FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* ror<.f><.cc> 0,limm,limm 0010111011000011F1111111100QQQQQ. */ +{ "ror", 0x2EC37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* ror8<.f> b,c 00101bbb00101111FBBBCCCCCC010001. */ +{ "ror8", 0x282F0011, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* ror8<.f> 0,c 0010111000101111F111CCCCCC010001. */ +{ "ror8", 0x2E2F7011, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* ror8<.f> b,u6 00101bbb01101111FBBBuuuuuu010001. */ +{ "ror8", 0x286F0011, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* ror8<.f> 0,u6 0010111001101111F111uuuuuu010001. */ +{ "ror8", 0x2E6F7011, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* ror8<.f> b,limm 00101bbb00101111FBBB111110010001. */ +{ "ror8", 0x282F0F91, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* ror8<.f> 0,limm 0010111000101111F111111110010001. */ +{ "ror8", 0x2E2F7F91, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* rrc<.f> b,c 00100bbb00101111FBBBCCCCCC000100. */ +{ "rrc", 0x202F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* rrc<.f> 0,c 0010011000101111F111CCCCCC000100. */ +{ "rrc", 0x262F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* rrc<.f> b,u6 00100bbb01101111FBBBuuuuuu000100. */ +{ "rrc", 0x206F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* rrc<.f> 0,u6 0010011001101111F111uuuuuu000100. */ +{ "rrc", 0x266F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* rrc<.f> b,limm 00100bbb00101111FBBB111110000100. */ +{ "rrc", 0x202F0F84, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* rrc<.f> 0,limm 0010011000101111F111111110000100. */ +{ "rrc", 0x262F7F84, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* rsub<.f> a,b,c 00100bbb00001110FBBBCCCCCCAAAAAA. */ +{ "rsub", 0x200E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* rsub<.f> 0,b,c 00100bbb00001110FBBBCCCCCC111110. */ +{ "rsub", 0x200E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* rsub<.f><.cc> b,b,c 00100bbb11001110FBBBCCCCCC0QQQQQ. */ +{ "rsub", 0x20CE0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* rsub<.f> a,b,u6 00100bbb01001110FBBBuuuuuuAAAAAA. */ +{ "rsub", 0x204E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* rsub<.f> 0,b,u6 00100bbb01001110FBBBuuuuuu111110. */ +{ "rsub", 0x204E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* rsub<.f><.cc> b,b,u6 00100bbb11001110FBBBuuuuuu1QQQQQ. */ +{ "rsub", 0x20CE0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* rsub<.f> b,b,s12 00100bbb10001110FBBBssssssSSSSSS. */ +{ "rsub", 0x208E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* rsub<.f> a,limm,c 0010011000001110F111CCCCCCAAAAAA. */ +{ "rsub", 0x260E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* rsub<.f> a,b,limm 00100bbb00001110FBBB111110AAAAAA. */ +{ "rsub", 0x200E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* rsub<.f> 0,limm,c 0010011000001110F111CCCCCC111110. */ +{ "rsub", 0x260E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* rsub<.f> 0,b,limm 00100bbb00001110FBBB111110111110. */ +{ "rsub", 0x200E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* rsub<.f><.cc> b,b,limm 00100bbb11001110FBBB1111100QQQQQ. */ +{ "rsub", 0x20CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* rsub<.f><.cc> 0,limm,c 0010011011001110F111CCCCCC0QQQQQ. */ +{ "rsub", 0x26CE7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* rsub<.f> a,limm,u6 0010011001001110F111uuuuuuAAAAAA. */ +{ "rsub", 0x264E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* rsub<.f> 0,limm,u6 0010011001001110F111uuuuuu111110. */ +{ "rsub", 0x264E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* rsub<.f><.cc> 0,limm,u6 0010011011001110F111uuuuuu1QQQQQ. */ +{ "rsub", 0x26CE7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* rsub<.f> 0,limm,s12 0010011010001110F111ssssssSSSSSS. */ +{ "rsub", 0x268E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* rsub<.f> a,limm,limm 0010011000001110F111111110AAAAAA. */ +{ "rsub", 0x260E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* rsub<.f> 0,limm,limm 0010011000001110F111111110111110. */ +{ "rsub", 0x260E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* rsub<.f><.cc> 0,limm,limm 0010011011001110F1111111100QQQQQ. */ +{ "rsub", 0x26CE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* rtie 00100100011011110000000000111111. */ +{ "rtie", 0x246F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }}, + +/* rtsc b,0 00110bbb01101111RBBB000000011010. */ +{ "rtsc", 0x306F001A, 0xF8FF0FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_RB, OPERAND_ZB }, { 0 }}, + +/* rtsc 0,0 0011011001101111R111000000011010. */ +{ "rtsc", 0x366F701A, 0xFFFF7FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_ZA, OPERAND_ZB }, { 0 }}, + +/* rtsc b,c 00110bbb00101111RBBBCCCCCC011010. */ +{ "rtsc", 0x302F001A, 0xF8FF003F, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* rtsc 0,c 0011011000101111R111CCCCCC011010. */ +{ "rtsc", 0x362F701A, 0xFFFF703F, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, + +/* rtsc b,u6 00110bbb01101111RBBBuuuuuu011010. */ +{ "rtsc", 0x306F001A, 0xF8FF003F, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* rtsc 0,u6 0011011001101111R111uuuuuu011010. */ +{ "rtsc", 0x366F701A, 0xFFFF703F, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, + +/* rtsc b,limm 00110bbb00101111RBBB111110011010. */ +{ "rtsc", 0x302F0F9A, 0xF8FF0FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* rtsc 0,limm 0011011000101111R111111110011010. */ +{ "rtsc", 0x362F7F9A, 0xFFFF7FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, + +/* rtsc 0011011001101111R111000000011010. */ +{ "rtsc", 0x366F701A, 0xFFFF7FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { 0 }, { 0 }}, + +/* sat16<.f> b,c 00101bbb00101111FBBBCCCCCC000010. */ +{ "sat16", 0x282F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* sat16<.f> 0,c 0010111000101111F111CCCCCC000010. */ +{ "sat16", 0x2E2F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* sat16<.f> b,u6 00101bbb01101111FBBBuuuuuu000010. */ +{ "sat16", 0x286F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* sat16<.f> 0,u6 0010111001101111F111uuuuuu000010. */ +{ "sat16", 0x2E6F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* sat16<.f> b,limm 00101bbb00101111FBBB111110000010. */ +{ "sat16", 0x282F0F82, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* sat16<.f> 0,limm 0010111000101111F111111110000010. */ +{ "sat16", 0x2E2F7F82, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* satf<.f> b,c 00101bbb00101111FBBBCCCCCC011010 */ +{ "satf", 0x282F001A, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, +/* satf<.f> 0,c 0010111000101111F111CCCCCC011010 */ +{ "satf", 0x2E2F701A, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* satf<.f> b,u6 00101bbb01101111FBBBuuuuuu011010 */ +{ "satf", 0x286F001A, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* satf<.f> 0,u6 0010111001101111F111uuuuuu011010 */ +{ "satf", 0x2E6F701A, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* satf<.f> 0,limm 0010111000101111F111111110011010 */ +{ "satf", 0x2E2F7F9A, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* satf<.f> b,limm 00101bbb00101111FBBB111110011010 */ +{ "satf", 0x282F0F9A, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* sath<.f> b,c 00101bbb00101111FBBBCCCCCC000010. */ +{ "sath", 0x282F0002, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { C_F }}, + +/* sath<.f> 0,c 0010111000101111F111CCCCCC000010. */ +{ "sath", 0x2E2F7002, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* sath<.f> b,u6 00101bbb01101111FBBBuuuuuu000010. */ +{ "sath", 0x286F0002, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { C_F }}, + +/* sath<.f> 0,u6 0010111001101111F111uuuuuu000010. */ +{ "sath", 0x2E6F7002, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* sath<.f> b,limm 00101bbb00101111FBBB111110000010. */ +{ "sath", 0x282F0F82, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { C_F }}, + +/* sath<.f> 0,limm 0010111000101111F111111110000010. */ +{ "sath", 0x2E2F7F82, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* sbc<.f> a,b,c 00100bbb00000011FBBBCCCCCCAAAAAA. */ +{ "sbc", 0x20030000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* sbc<.f> 0,b,c 00100bbb00000011FBBBCCCCCC111110. */ +{ "sbc", 0x2003003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* sbc<.f><.cc> b,b,c 00100bbb11000011FBBBCCCCCC0QQQQQ. */ +{ "sbc", 0x20C30000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* sbc<.f> a,b,u6 00100bbb01000011FBBBuuuuuuAAAAAA. */ +{ "sbc", 0x20430000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* sbc<.f> 0,b,u6 00100bbb01000011FBBBuuuuuu111110. */ +{ "sbc", 0x2043003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* sbc<.f><.cc> b,b,u6 00100bbb11000011FBBBuuuuuu1QQQQQ. */ +{ "sbc", 0x20C30020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* sbc<.f> b,b,s12 00100bbb10000011FBBBssssssSSSSSS. */ +{ "sbc", 0x20830000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* sbc<.f> a,limm,c 0010011000000011F111CCCCCCAAAAAA. */ +{ "sbc", 0x26037000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* sbc<.f> a,b,limm 00100bbb00000011FBBB111110AAAAAA. */ +{ "sbc", 0x20030F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* sbc<.f> 0,limm,c 0010011000000011F111CCCCCC111110. */ +{ "sbc", 0x2603703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* sbc<.f> 0,b,limm 00100bbb00000011FBBB111110111110. */ +{ "sbc", 0x20030FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* sbc<.f><.cc> b,b,limm 00100bbb11000011FBBB1111100QQQQQ. */ +{ "sbc", 0x20C30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* sbc<.f><.cc> 0,limm,c 0010011011000011F111CCCCCC0QQQQQ. */ +{ "sbc", 0x26C37000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* sbc<.f> a,limm,u6 0010011001000011F111uuuuuuAAAAAA. */ +{ "sbc", 0x26437000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* sbc<.f> 0,limm,u6 0010011001000011F111uuuuuu111110. */ +{ "sbc", 0x2643703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* sbc<.f><.cc> 0,limm,u6 0010011011000011F111uuuuuu1QQQQQ. */ +{ "sbc", 0x26C37020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* sbc<.f> 0,limm,s12 0010011010000011F111ssssssSSSSSS. */ +{ "sbc", 0x26837000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* sbc<.f> a,limm,limm 0010011000000011F111111110AAAAAA. */ +{ "sbc", 0x26037F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* sbc<.f> 0,limm,limm 0010011000000011F111111110111110. */ +{ "sbc", 0x26037FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* sbc<.f><.cc> 0,limm,limm 0010011011000011F1111111100QQQQQ. */ +{ "sbc", 0x26C37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* sbcs<.f><.cc> b,b,c 00101bbb11100111FBBBCCCCCC0QQQQQ */ +{ "sbcs", 0x28E70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* sbcs<.f> 0,b,c 00101bbb00100111FBBBCCCCCC111110 */ +{ "sbcs", 0x2827003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* sbcs<.f> a,b,c 00101bbb00100111FBBBCCCCCCAAAAAA */ +{ "sbcs", 0x28270000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* sbcs<.f><.cc> b,b,u6 00101bbb11100111FBBBuuuuuu1QQQQQ */ +{ "sbcs", 0x28E70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* sbcs<.f> a,b,u6 00101bbb01100111FBBBuuuuuuAAAAAA */ +{ "sbcs", 0x28670000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* sbcs<.f> 0,b,u6 00101bbb01100111FBBBuuuuuu111110 */ +{ "sbcs", 0x2867003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* sbcs<.f> b,b,s12 00101bbb10100111FBBBssssssSSSSSS */ +{ "sbcs", 0x28A70000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* sbcs<.f><.cc> 0,limm,c 0010111011100111F111CCCCCC0QQQQQ */ +{ "sbcs", 0x2EE77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* sbcs<.f> a,b,limm 00101bbb00100111FBBB111110AAAAAA */ +{ "sbcs", 0x28270F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* sbcs<.f> 0,b,limm 00101bbb00100111FBBB111110111110 */ +{ "sbcs", 0x28270FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* sbcs<.f><.cc> b,b,limm 00101bbb11100111FBBB1111100QQQQQ */ +{ "sbcs", 0x28E70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* sbcs<.f> a,limm,c 0010111000100111F111CCCCCCAAAAAA */ +{ "sbcs", 0x2E277000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* sbcs<.f> 0,limm,c 0010111001100111F111CCCCCC111110 */ +{ "sbcs", 0x2E67703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* sbcs<.f><.cc> 0,limm,u6 0010111011100111F111uuuuuu1QQQQQ */ +{ "sbcs", 0x2EE77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* sbcs<.f> 0,limm,u6 0010111001100111F111uuuuuu111110 */ +{ "sbcs", 0x2E67703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* sbcs<.f> a,limm,u6 0010111001100111F111uuuuuuAAAAAA */ +{ "sbcs", 0x2E677000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* sbcs<.f> 0,limm,s12 0010111010100111F111ssssssSSSSSS */ +{ "sbcs", 0x2EA77000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* sbcs<.f><.cc> 0,limm,limm 0010111011100111F1111111100QQQQQ */ +{ "sbcs", 0x2EE77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* sbcs<.f> a,limm,limm 0010111000100111F111111110AAAAAA */ +{ "sbcs", 0x2E277F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* sbcs<.f> 0,limm,limm 0010111000100111F111111110111110 */ +{ "sbcs", 0x2E277FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* scond<.di> b,c 00100bbb00101111DBBBCCCCCC010001. */ +{ "scond", 0x202F0011, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* scond<.di> b,u6 00100bbb01101111DBBBuuuuuu010001. */ +{ "scond", 0x206F0011, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* scond<.di> b,limm 00100bbb00101111DBBB111110010001. */ +{ "scond", 0x202F0F91, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* scond<.di> limm,c 0010011000101111D111CCCCCC010001. */ +{ "scond", 0x262F7011, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* scond<.di> limm,u6 0010011001101111D111uuuuuu010001. */ +{ "scond", 0x266F7011, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* scond<.di> limm,limm 0010011000101111D111111110010001. */ +{ "scond", 0x262F7F91, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* scondd<.di> b,c 00100bbb00101111DBBBCCCCCC010011. */ +{ "scondd", 0x202F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* scondd<.di> b,u6 00100bbb01101111DBBBuuuuuu010011. */ +{ "scondd", 0x206F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* scondd<.di> b,limm 00100bbb00101111DBBB111110010011. */ +{ "scondd", 0x202F0F93, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI16 }}, + +/* setacc a,b,c 00101bbb000011011BBBCCCCCCAAAAAA. */ +{ "setacc", 0x280D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* setacc 0,b,c 00101bbb000011011BBBCCCCCC111110. */ +{ "setacc", 0x280D803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* setacc<.cc> b,b,c 00101bbb110011011BBBCCCCCC0QQQQQ. */ +{ "setacc", 0x28CD8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* setacc a,b,u6 00101bbb010011011BBBuuuuuuAAAAAA. */ +{ "setacc", 0x284D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* setacc 0,b,u6 00101bbb010011011BBBuuuuuu111110. */ +{ "setacc", 0x284D803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* setacc<.cc> b,b,u6 00101bbb110011011BBBuuuuuu1QQQQQ. */ +{ "setacc", 0x28CD8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* setacc b,b,s12 00101bbb100011011BBBssssssSSSSSS. */ +{ "setacc", 0x288D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* setacc a,limm,c 00101110000011011111CCCCCCAAAAAA. */ +{ "setacc", 0x2E0DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* setacc a,b,limm 00101bbb000011011BBB111110AAAAAA. */ +{ "setacc", 0x280D8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* setacc 0,limm,c 00101110000011011111CCCCCC111110. */ +{ "setacc", 0x2E0DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* setacc 0,b,limm 00101bbb000011011BBB111110111110. */ +{ "setacc", 0x280D8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* setacc<.cc> b,b,limm 00101bbb110011011BBB1111100QQQQQ. */ +{ "setacc", 0x28CD8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* setacc<.cc> 0,limm,c 00101110110011011111CCCCCC0QQQQQ. */ +{ "setacc", 0x2ECDF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* setacc a,limm,u6 00101110010011011111uuuuuuAAAAAA. */ +{ "setacc", 0x2E4DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* setacc 0,limm,u6 00101110010011011111uuuuuu111110. */ +{ "setacc", 0x2E4DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* setacc<.cc> 0,limm,u6 00101110110011011111uuuuuu1QQQQQ. */ +{ "setacc", 0x2ECDF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* setacc 0,limm,s12 00101110100011011111ssssssSSSSSS. */ +{ "setacc", 0x2E8DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* setacc a,limm,limm 00101110000011011111111110AAAAAA. */ +{ "setacc", 0x2E0DFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* setacc 0,limm,limm 00101110000011011111111110111110. */ +{ "setacc", 0x2E0DFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* setacc<.cc> 0,limm,limm 001011101100110111111111100QQQQQ. */ +{ "setacc", 0x2ECDFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* seteq<.f> a,b,c 00100bbb00111000FBBBCCCCCCAAAAAA. */ +{ "seteq", 0x20380000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* seteq<.f> 0,b,c 00100bbb00111000FBBBCCCCCC111110. */ +{ "seteq", 0x2038003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* seteq<.f><.cc> b,b,c 00100bbb11111000FBBBCCCCCC0QQQQQ. */ +{ "seteq", 0x20F80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* seteq<.f> a,b,u6 00100bbb01111000FBBBuuuuuuAAAAAA. */ +{ "seteq", 0x20780000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* seteq<.f> 0,b,u6 00100bbb01111000FBBBuuuuuu111110. */ +{ "seteq", 0x2078003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* seteq<.f><.cc> b,b,u6 00100bbb11111000FBBBuuuuuu1QQQQQ. */ +{ "seteq", 0x20F80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* seteq<.f> b,b,s12 00100bbb10111000FBBBssssssSSSSSS. */ +{ "seteq", 0x20B80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* seteq<.f> a,limm,c 0010011000111000F111CCCCCCAAAAAA. */ +{ "seteq", 0x26387000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* seteq<.f> a,b,limm 00100bbb00111000FBBB111110AAAAAA. */ +{ "seteq", 0x20380F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* seteq<.f> 0,limm,c 0010011000111000F111CCCCCC111110. */ +{ "seteq", 0x2638703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* seteq<.f> 0,b,limm 00100bbb00111000FBBB111110111110. */ +{ "seteq", 0x20380FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* seteq<.f><.cc> b,b,limm 00100bbb11111000FBBB1111100QQQQQ. */ +{ "seteq", 0x20F80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* seteq<.f><.cc> 0,limm,c 0010011011111000F111CCCCCC0QQQQQ. */ +{ "seteq", 0x26F87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* seteq<.f> a,limm,u6 0010011001111000F111uuuuuuAAAAAA. */ +{ "seteq", 0x26787000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* seteq<.f> 0,limm,u6 0010011001111000F111uuuuuu111110. */ +{ "seteq", 0x2678703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* seteq<.f><.cc> 0,limm,u6 0010011011111000F111uuuuuu1QQQQQ. */ +{ "seteq", 0x26F87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* seteq<.f> 0,limm,s12 0010011010111000F111ssssssSSSSSS. */ +{ "seteq", 0x26B87000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* seteq<.f> a,limm,limm 0010011000111000F111111110AAAAAA. */ +{ "seteq", 0x26387F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* seteq<.f> 0,limm,limm 0010011000111000F111111110111110. */ +{ "seteq", 0x26387FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* seteq<.f><.cc> 0,limm,limm 0010011011111000F1111111100QQQQQ. */ +{ "seteq", 0x26F87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* setge<.f> a,b,c 00100bbb00111011FBBBCCCCCCAAAAAA. */ +{ "setge", 0x203B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* setge<.f> 0,b,c 00100bbb00111011FBBBCCCCCC111110. */ +{ "setge", 0x203B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* setge<.f><.cc> b,b,c 00100bbb11111011FBBBCCCCCC0QQQQQ. */ +{ "setge", 0x20FB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* setge<.f> a,b,u6 00100bbb01111011FBBBuuuuuuAAAAAA. */ +{ "setge", 0x207B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* setge<.f> 0,b,u6 00100bbb01111011FBBBuuuuuu111110. */ +{ "setge", 0x207B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* setge<.f><.cc> b,b,u6 00100bbb11111011FBBBuuuuuu1QQQQQ. */ +{ "setge", 0x20FB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* setge<.f> b,b,s12 00100bbb10111011FBBBssssssSSSSSS. */ +{ "setge", 0x20BB0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* setge<.f> a,limm,c 0010011000111011F111CCCCCCAAAAAA. */ +{ "setge", 0x263B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* setge<.f> a,b,limm 00100bbb00111011FBBB111110AAAAAA. */ +{ "setge", 0x203B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* setge<.f> 0,limm,c 0010011000111011F111CCCCCC111110. */ +{ "setge", 0x263B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* setge<.f> 0,b,limm 00100bbb00111011FBBB111110111110. */ +{ "setge", 0x203B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* setge<.f><.cc> b,b,limm 00100bbb11111011FBBB1111100QQQQQ. */ +{ "setge", 0x20FB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* setge<.f><.cc> 0,limm,c 0010011011111011F111CCCCCC0QQQQQ. */ +{ "setge", 0x26FB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* setge<.f> a,limm,u6 0010011001111011F111uuuuuuAAAAAA. */ +{ "setge", 0x267B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* setge<.f> 0,limm,u6 0010011001111011F111uuuuuu111110. */ +{ "setge", 0x267B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* setge<.f><.cc> 0,limm,u6 0010011011111011F111uuuuuu1QQQQQ. */ +{ "setge", 0x26FB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* setge<.f> 0,limm,s12 0010011010111011F111ssssssSSSSSS. */ +{ "setge", 0x26BB7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* setge<.f> a,limm,limm 0010011000111011F111111110AAAAAA. */ +{ "setge", 0x263B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* setge<.f> 0,limm,limm 0010011000111011F111111110111110. */ +{ "setge", 0x263B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* setge<.f><.cc> 0,limm,limm 0010011011111011F1111111100QQQQQ. */ +{ "setge", 0x26FB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* setgt<.f> a,b,c 00100bbb00111111FBBBCCCCCCAAAAAA. */ +{ "setgt", 0x203F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* setgt<.f> 0,b,c 00100bbb00111111FBBBCCCCCC111110. */ +{ "setgt", 0x203F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* setgt<.f><.cc> b,b,c 00100bbb11111111FBBBCCCCCC0QQQQQ. */ +{ "setgt", 0x20FF0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* setgt<.f> a,b,u6 00100bbb01111111FBBBuuuuuuAAAAAA. */ +{ "setgt", 0x207F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* setgt<.f> 0,b,u6 00100bbb01111111FBBBuuuuuu111110. */ +{ "setgt", 0x207F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* setgt<.f><.cc> b,b,u6 00100bbb11111111FBBBuuuuuu1QQQQQ. */ +{ "setgt", 0x20FF0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* setgt<.f> b,b,s12 00100bbb10111111FBBBssssssSSSSSS. */ +{ "setgt", 0x20BF0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* setgt<.f> a,limm,c 0010011000111111F111CCCCCCAAAAAA. */ +{ "setgt", 0x263F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* setgt<.f> a,b,limm 00100bbb00111111FBBB111110AAAAAA. */ +{ "setgt", 0x203F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* setgt<.f> 0,limm,c 0010011000111111F111CCCCCC111110. */ +{ "setgt", 0x263F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* setgt<.f> 0,b,limm 00100bbb00111111FBBB111110111110. */ +{ "setgt", 0x203F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* setgt<.f><.cc> b,b,limm 00100bbb11111111FBBB1111100QQQQQ. */ +{ "setgt", 0x20FF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* setgt<.f><.cc> 0,limm,c 0010011011111111F111CCCCCC0QQQQQ. */ +{ "setgt", 0x26FF7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* setgt<.f> a,limm,u6 0010011001111111F111uuuuuuAAAAAA. */ +{ "setgt", 0x267F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* setgt<.f> 0,limm,u6 0010011001111111F111uuuuuu111110. */ +{ "setgt", 0x267F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* setgt<.f><.cc> 0,limm,u6 0010011011111111F111uuuuuu1QQQQQ. */ +{ "setgt", 0x26FF7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* setgt<.f> 0,limm,s12 0010011010111111F111ssssssSSSSSS. */ +{ "setgt", 0x26BF7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* setgt<.f> a,limm,limm 0010011000111111F111111110AAAAAA. */ +{ "setgt", 0x263F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* setgt<.f> 0,limm,limm 0010011000111111F111111110111110. */ +{ "setgt", 0x263F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* setgt<.f><.cc> 0,limm,limm 0010011011111111F1111111100QQQQQ. */ +{ "setgt", 0x26FF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* seths<.f> a,b,c 00100bbb00111101FBBBCCCCCCAAAAAA. */ +{ "seths", 0x203D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* seths<.f> 0,b,c 00100bbb00111101FBBBCCCCCC111110. */ +{ "seths", 0x203D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* seths<.f><.cc> b,b,c 00100bbb11111101FBBBCCCCCC0QQQQQ. */ +{ "seths", 0x20FD0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* seths<.f> a,b,u6 00100bbb01111101FBBBuuuuuuAAAAAA. */ +{ "seths", 0x207D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* seths<.f> 0,b,u6 00100bbb01111101FBBBuuuuuu111110. */ +{ "seths", 0x207D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* seths<.f><.cc> b,b,u6 00100bbb11111101FBBBuuuuuu1QQQQQ. */ +{ "seths", 0x20FD0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* seths<.f> b,b,s12 00100bbb10111101FBBBssssssSSSSSS. */ +{ "seths", 0x20BD0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* seths<.f> a,limm,c 0010011000111101F111CCCCCCAAAAAA. */ +{ "seths", 0x263D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* seths<.f> a,b,limm 00100bbb00111101FBBB111110AAAAAA. */ +{ "seths", 0x203D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* seths<.f> 0,limm,c 0010011000111101F111CCCCCC111110. */ +{ "seths", 0x263D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* seths<.f> 0,b,limm 00100bbb00111101FBBB111110111110. */ +{ "seths", 0x203D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* seths<.f><.cc> b,b,limm 00100bbb11111101FBBB1111100QQQQQ. */ +{ "seths", 0x20FD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* seths<.f><.cc> 0,limm,c 0010011011111101F111CCCCCC0QQQQQ. */ +{ "seths", 0x26FD7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* seths<.f> a,limm,u6 0010011001111101F111uuuuuuAAAAAA. */ +{ "seths", 0x267D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* seths<.f> 0,limm,u6 0010011001111101F111uuuuuu111110. */ +{ "seths", 0x267D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* seths<.f><.cc> 0,limm,u6 0010011011111101F111uuuuuu1QQQQQ. */ +{ "seths", 0x26FD7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* seths<.f> 0,limm,s12 0010011010111101F111ssssssSSSSSS. */ +{ "seths", 0x26BD7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* seths<.f> a,limm,limm 0010011000111101F111111110AAAAAA. */ +{ "seths", 0x263D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* seths<.f> 0,limm,limm 0010011000111101F111111110111110. */ +{ "seths", 0x263D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* seths<.f><.cc> 0,limm,limm 0010011011111101F1111111100QQQQQ. */ +{ "seths", 0x26FD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* seti c 00100110001011110000CCCCCC111111. */ +{ "seti", 0x262F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_RC }, { 0 }}, + +/* seti u6 00100110011011110000uuuuuu111111. */ +{ "seti", 0x266F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_UIMM6_20 }, { 0 }}, + +/* seti limm 00100110001011110000111110111111. */ +{ "seti", 0x262F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { OPERAND_LIMM }, { 0 }}, + +/* seti 00100110011011110000uuuuuu111111. */ +{ "seti", 0x266F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }}, + +/* setle<.f> a,b,c 00100bbb00111110FBBBCCCCCCAAAAAA. */ +{ "setle", 0x203E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* setle<.f> 0,b,c 00100bbb00111110FBBBCCCCCC111110. */ +{ "setle", 0x203E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* setle<.f><.cc> b,b,c 00100bbb11111110FBBBCCCCCC0QQQQQ. */ +{ "setle", 0x20FE0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* setle<.f> a,b,u6 00100bbb01111110FBBBuuuuuuAAAAAA. */ +{ "setle", 0x207E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* setle<.f> 0,b,u6 00100bbb01111110FBBBuuuuuu111110. */ +{ "setle", 0x207E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* setle<.f><.cc> b,b,u6 00100bbb11111110FBBBuuuuuu1QQQQQ. */ +{ "setle", 0x20FE0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* setle<.f> b,b,s12 00100bbb10111110FBBBssssssSSSSSS. */ +{ "setle", 0x20BE0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* setle<.f> a,limm,c 0010011000111110F111CCCCCCAAAAAA. */ +{ "setle", 0x263E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* setle<.f> a,b,limm 00100bbb00111110FBBB111110AAAAAA. */ +{ "setle", 0x203E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* setle<.f> 0,limm,c 0010011000111110F111CCCCCC111110. */ +{ "setle", 0x263E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* setle<.f> 0,b,limm 00100bbb00111110FBBB111110111110. */ +{ "setle", 0x203E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* setle<.f><.cc> b,b,limm 00100bbb11111110FBBB1111100QQQQQ. */ +{ "setle", 0x20FE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* setle<.f><.cc> 0,limm,c 0010011011111110F111CCCCCC0QQQQQ. */ +{ "setle", 0x26FE7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* setle<.f> a,limm,u6 0010011001111110F111uuuuuuAAAAAA. */ +{ "setle", 0x267E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* setle<.f> 0,limm,u6 0010011001111110F111uuuuuu111110. */ +{ "setle", 0x267E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* setle<.f><.cc> 0,limm,u6 0010011011111110F111uuuuuu1QQQQQ. */ +{ "setle", 0x26FE7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* setle<.f> 0,limm,s12 0010011010111110F111ssssssSSSSSS. */ +{ "setle", 0x26BE7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* setle<.f> a,limm,limm 0010011000111110F111111110AAAAAA. */ +{ "setle", 0x263E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* setle<.f> 0,limm,limm 0010011000111110F111111110111110. */ +{ "setle", 0x263E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* setle<.f><.cc> 0,limm,limm 0010011011111110F1111111100QQQQQ. */ +{ "setle", 0x26FE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* setlo<.f> a,b,c 00100bbb00111100FBBBCCCCCCAAAAAA. */ +{ "setlo", 0x203C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* setlo<.f> 0,b,c 00100bbb00111100FBBBCCCCCC111110. */ +{ "setlo", 0x203C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* setlo<.f><.cc> b,b,c 00100bbb11111100FBBBCCCCCC0QQQQQ. */ +{ "setlo", 0x20FC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* setlo<.f> a,b,u6 00100bbb01111100FBBBuuuuuuAAAAAA. */ +{ "setlo", 0x207C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* setlo<.f> 0,b,u6 00100bbb01111100FBBBuuuuuu111110. */ +{ "setlo", 0x207C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* setlo<.f><.cc> b,b,u6 00100bbb11111100FBBBuuuuuu1QQQQQ. */ +{ "setlo", 0x20FC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* setlo<.f> b,b,s12 00100bbb10111100FBBBssssssSSSSSS. */ +{ "setlo", 0x20BC0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* setlo<.f> a,limm,c 0010011000111100F111CCCCCCAAAAAA. */ +{ "setlo", 0x263C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* setlo<.f> a,b,limm 00100bbb00111100FBBB111110AAAAAA. */ +{ "setlo", 0x203C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* setlo<.f> 0,limm,c 0010011000111100F111CCCCCC111110. */ +{ "setlo", 0x263C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* setlo<.f> 0,b,limm 00100bbb00111100FBBB111110111110. */ +{ "setlo", 0x203C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* setlo<.f><.cc> b,b,limm 00100bbb11111100FBBB1111100QQQQQ. */ +{ "setlo", 0x20FC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* setlo<.f><.cc> 0,limm,c 0010011011111100F111CCCCCC0QQQQQ. */ +{ "setlo", 0x26FC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* setlo<.f> a,limm,u6 0010011001111100F111uuuuuuAAAAAA. */ +{ "setlo", 0x267C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* setlo<.f> 0,limm,u6 0010011001111100F111uuuuuu111110. */ +{ "setlo", 0x267C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* setlo<.f><.cc> 0,limm,u6 0010011011111100F111uuuuuu1QQQQQ. */ +{ "setlo", 0x26FC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* setlo<.f> 0,limm,s12 0010011010111100F111ssssssSSSSSS. */ +{ "setlo", 0x26BC7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* setlo<.f> a,limm,limm 0010011000111100F111111110AAAAAA. */ +{ "setlo", 0x263C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* setlo<.f> 0,limm,limm 0010011000111100F111111110111110. */ +{ "setlo", 0x263C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* setlo<.f><.cc> 0,limm,limm 0010011011111100F1111111100QQQQQ. */ +{ "setlo", 0x26FC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* setlt<.f> a,b,c 00100bbb00111010FBBBCCCCCCAAAAAA. */ +{ "setlt", 0x203A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* setlt<.f> 0,b,c 00100bbb00111010FBBBCCCCCC111110. */ +{ "setlt", 0x203A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* setlt<.f><.cc> b,b,c 00100bbb11111010FBBBCCCCCC0QQQQQ. */ +{ "setlt", 0x20FA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* setlt<.f> a,b,u6 00100bbb01111010FBBBuuuuuuAAAAAA. */ +{ "setlt", 0x207A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* setlt<.f> 0,b,u6 00100bbb01111010FBBBuuuuuu111110. */ +{ "setlt", 0x207A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* setlt<.f><.cc> b,b,u6 00100bbb11111010FBBBuuuuuu1QQQQQ. */ +{ "setlt", 0x20FA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* setlt<.f> b,b,s12 00100bbb10111010FBBBssssssSSSSSS. */ +{ "setlt", 0x20BA0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* setlt<.f> a,limm,c 0010011000111010F111CCCCCCAAAAAA. */ +{ "setlt", 0x263A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* setlt<.f> a,b,limm 00100bbb00111010FBBB111110AAAAAA. */ +{ "setlt", 0x203A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* setlt<.f> 0,limm,c 0010011000111010F111CCCCCC111110. */ +{ "setlt", 0x263A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* setlt<.f> 0,b,limm 00100bbb00111010FBBB111110111110. */ +{ "setlt", 0x203A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* setlt<.f><.cc> b,b,limm 00100bbb11111010FBBB1111100QQQQQ. */ +{ "setlt", 0x20FA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* setlt<.f><.cc> 0,limm,c 0010011011111010F111CCCCCC0QQQQQ. */ +{ "setlt", 0x26FA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* setlt<.f> a,limm,u6 0010011001111010F111uuuuuuAAAAAA. */ +{ "setlt", 0x267A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* setlt<.f> 0,limm,u6 0010011001111010F111uuuuuu111110. */ +{ "setlt", 0x267A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* setlt<.f><.cc> 0,limm,u6 0010011011111010F111uuuuuu1QQQQQ. */ +{ "setlt", 0x26FA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* setlt<.f> 0,limm,s12 0010011010111010F111ssssssSSSSSS. */ +{ "setlt", 0x26BA7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* setlt<.f> a,limm,limm 0010011000111010F111111110AAAAAA. */ +{ "setlt", 0x263A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* setlt<.f> 0,limm,limm 0010011000111010F111111110111110. */ +{ "setlt", 0x263A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* setlt<.f><.cc> 0,limm,limm 0010011011111010F1111111100QQQQQ. */ +{ "setlt", 0x26FA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* setne<.f> a,b,c 00100bbb00111001FBBBCCCCCCAAAAAA. */ +{ "setne", 0x20390000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* setne<.f> 0,b,c 00100bbb00111001FBBBCCCCCC111110. */ +{ "setne", 0x2039003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* setne<.f><.cc> b,b,c 00100bbb11111001FBBBCCCCCC0QQQQQ. */ +{ "setne", 0x20F90000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* setne<.f> a,b,u6 00100bbb01111001FBBBuuuuuuAAAAAA. */ +{ "setne", 0x20790000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* setne<.f> 0,b,u6 00100bbb01111001FBBBuuuuuu111110. */ +{ "setne", 0x2079003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* setne<.f><.cc> b,b,u6 00100bbb11111001FBBBuuuuuu1QQQQQ. */ +{ "setne", 0x20F90020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* setne<.f> b,b,s12 00100bbb10111001FBBBssssssSSSSSS. */ +{ "setne", 0x20B90000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* setne<.f> a,limm,c 0010011000111001F111CCCCCCAAAAAA. */ +{ "setne", 0x26397000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* setne<.f> a,b,limm 00100bbb00111001FBBB111110AAAAAA. */ +{ "setne", 0x20390F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* setne<.f> 0,limm,c 0010011000111001F111CCCCCC111110. */ +{ "setne", 0x2639703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* setne<.f> 0,b,limm 00100bbb00111001FBBB111110111110. */ +{ "setne", 0x20390FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* setne<.f><.cc> b,b,limm 00100bbb11111001FBBB1111100QQQQQ. */ +{ "setne", 0x20F90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* setne<.f><.cc> 0,limm,c 0010011011111001F111CCCCCC0QQQQQ. */ +{ "setne", 0x26F97000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* setne<.f> a,limm,u6 0010011001111001F111uuuuuuAAAAAA. */ +{ "setne", 0x26797000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* setne<.f> 0,limm,u6 0010011001111001F111uuuuuu111110. */ +{ "setne", 0x2679703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* setne<.f><.cc> 0,limm,u6 0010011011111001F111uuuuuu1QQQQQ. */ +{ "setne", 0x26F97020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* setne<.f> 0,limm,s12 0010011010111001F111ssssssSSSSSS. */ +{ "setne", 0x26B97000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* setne<.f> a,limm,limm 0010011000111001F111111110AAAAAA. */ +{ "setne", 0x26397F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* setne<.f> 0,limm,limm 0010011000111001F111111110111110. */ +{ "setne", 0x26397FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* setne<.f><.cc> 0,limm,limm 0010011011111001F1111111100QQQQQ. */ +{ "setne", 0x26F97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* setcc<.f> a,b,c 00100bbb00iiiiiiFBBBCCCCCCAAAAAA. */ +{ "setcc", 0x20000000, 0xF8C00000, 0, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* setcc<.f> 0,b,c 00100bbb00iiiiiiFBBBCCCCCC111110. */ +{ "setcc", 0x2000003E, 0xF8C0003F, 0, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* setcc<.f><.cc> b,b,c 00100bbb11iiiiiiFBBBCCCCCC0QQQQQ. */ +{ "setcc", 0x20C00000, 0xF8C00020, 0, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* setcc<.f> a,b,u6 00100bbb01iiiiiiFBBBuuuuuuAAAAAA. */ +{ "setcc", 0x20400000, 0xF8C00000, 0, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* setcc<.f> 0,b,u6 00100bbb01iiiiiiFBBBuuuuuu111110. */ +{ "setcc", 0x2040003E, 0xF8C0003F, 0, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* setcc<.f><.cc> b,b,u6 00100bbb11iiiiiiFBBBuuuuuu1QQQQQ. */ +{ "setcc", 0x20C00020, 0xF8C00020, 0, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* setcc<.f> b,b,s12 00100bbb10iiiiiiFBBBssssssSSSSSS. */ +{ "setcc", 0x20800000, 0xF8C00000, 0, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* setcc<.f> a,limm,c 0010011000iiiiiiF111CCCCCCAAAAAA. */ +{ "setcc", 0x26007000, 0xFFC07000, 0, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* setcc<.f> a,b,limm 00100bbb00iiiiiiFBBB111110AAAAAA. */ +{ "setcc", 0x20000F80, 0xF8C00FC0, 0, LOGICAL, CD1, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* setcc<.f> 0,limm,c 0010011000iiiiiiF111CCCCCC111110. */ +{ "setcc", 0x2600703E, 0xFFC0703F, 0, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* setcc<.f> 0,b,limm 00100bbb00iiiiiiFBBB111110111110. */ +{ "setcc", 0x20000FBE, 0xF8C00FFF, 0, LOGICAL, CD1, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* setcc<.f><.cc> b,b,limm 00100bbb11iiiiiiFBBB1111100QQQQQ. */ +{ "setcc", 0x20C00F80, 0xF8C00FE0, 0, LOGICAL, CD1, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* setcc<.f><.cc> 0,limm,c 0010011011iiiiiiF111CCCCCC0QQQQQ. */ +{ "setcc", 0x26C07000, 0xFFC07020, 0, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* setcc<.f> a,limm,u6 0010011001iiiiiiF111uuuuuuAAAAAA. */ +{ "setcc", 0x26407000, 0xFFC07000, 0, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* setcc<.f> 0,limm,u6 0010011001iiiiiiF111uuuuuu111110. */ +{ "setcc", 0x2640703E, 0xFFC0703F, 0, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* setcc<.f><.cc> 0,limm,u6 0010011011iiiiiiF111uuuuuu1QQQQQ. */ +{ "setcc", 0x26C07020, 0xFFC07020, 0, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* setcc<.f> 0,limm,s12 0010011010iiiiiiF111ssssssSSSSSS. */ +{ "setcc", 0x26807000, 0xFFC07000, 0, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* setcc<.f> a,limm,limm 0010011000iiiiiiF111111110AAAAAA. */ +{ "setcc", 0x26007F80, 0xFFC07FC0, 0, LOGICAL, CD1, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* setcc<.f> 0,limm,limm 0010011000iiiiiiF111111110111110. */ +{ "setcc", 0x26007FBE, 0xFFC07FFF, 0, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* setcc<.f><.cc> 0,limm,limm 0010011011iiiiiiF1111111100QQQQQ. */ +{ "setcc", 0x26C07F80, 0xFFC07FE0, 0, LOGICAL, CD1, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* sexb<.f> b,c 00100bbb00101111FBBBCCCCCC000101. */ +{ "sexb", 0x202F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* sexb<.f> 0,c 0010011000101111F111CCCCCC000101. */ +{ "sexb", 0x262F7005, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* sexb<.f> b,u6 00100bbb01101111FBBBuuuuuu000101. */ +{ "sexb", 0x206F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* sexb<.f> 0,u6 0010011001101111F111uuuuuu000101. */ +{ "sexb", 0x266F7005, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* sexb<.f> b,limm 00100bbb00101111FBBB111110000101. */ +{ "sexb", 0x202F0F85, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* sexb<.f> 0,limm 0010011000101111F111111110000101. */ +{ "sexb", 0x262F7F85, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* sexb_s b,c 01111bbbccc01101. */ +{ "sexb_s", 0x0000780D, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, + +/* sexh<.f> b,c 00100bbb00101111FBBBCCCCCC000110. */ +{ "sexh", 0x202F0006, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* sexh<.f> 0,c 0010011000101111F111CCCCCC000110. */ +{ "sexh", 0x262F7006, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* sexh<.f> b,u6 00100bbb01101111FBBBuuuuuu000110. */ +{ "sexh", 0x206F0006, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* sexh<.f> 0,u6 0010011001101111F111uuuuuu000110. */ +{ "sexh", 0x266F7006, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* sexh<.f> b,limm 00100bbb00101111FBBB111110000110. */ +{ "sexh", 0x202F0F86, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* sexh<.f> 0,limm 0010011000101111F111111110000110. */ +{ "sexh", 0x262F7F86, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* sexh_s b,c 01111bbbccc01110. */ +{ "sexh_s", 0x0000780E, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, + +/* sexw<.f> b,c 00100bbb00101111FBBBCCCCCC000110. */ +{ "sexw", 0x202F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* sexw<.f> 0,c 0010011000101111F111CCCCCC000110. */ +{ "sexw", 0x262F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* sexw<.f> b,u6 00100bbb01101111FBBBuuuuuu000110. */ +{ "sexw", 0x206F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* sexw<.f> 0,u6 0010011001101111F111uuuuuu000110. */ +{ "sexw", 0x266F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* sexw<.f> b,limm 00100bbb00101111FBBB111110000110. */ +{ "sexw", 0x202F0F86, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* sexw<.f> 0,limm 0010011000101111F111111110000110. */ +{ "sexw", 0x262F7F86, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* sexw_s b,c 01111bbbccc01110. */ +{ "sexw_s", 0x0000780E, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, + +/* sflag c 00110000001011110000CCCCCC111111 */ +{ "sflag", 0x302F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, CONTROL, NONE, { OPERAND_RC }, { 0 }}, + +/* sflag u6 00110000011011110000uuuuuu111111 */ +{ "sflag", 0x306F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, CONTROL, NONE, { OPERAND_UIMM6_20 }, { 0 }}, + +/* sflag limm 00110000001011110000111110111111 */ +{ "sflag", 0x302F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, CONTROL, NONE, { OPERAND_LIMM }, { 0 }}, + +/* sfxtr<.f> a,b,c 00110bbb00101001FBBBCCCCCCAAAAAA. */ +{ "sfxtr", 0x30290000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* sfxtr<.f><.cc> b,b,c 00110bbb11101001FBBBCCCCCC0QQQQQ. */ +{ "sfxtr", 0x30E90000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* sfxtr<.f> a,b,u6 00110bbb01101001FBBBuuuuuuAAAAAA. */ +{ "sfxtr", 0x30690000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* sfxtr<.f><.cc> b,b,u6 00110bbb11101001FBBBuuuuuu1QQQQQ. */ +{ "sfxtr", 0x30E90020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* sfxtr<.f> b,b,s12 00110bbb10101001FBBBssssssSSSSSS. */ +{ "sfxtr", 0x30A90000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* sfxtr<.f> a,limm,c 0011011000101001F111CCCCCCAAAAAA. */ +{ "sfxtr", 0x36297000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* sfxtr<.f> a,b,limm 00110bbb00101001FBBB111110AAAAAA. */ +{ "sfxtr", 0x30290F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* sfxtr<.f><.cc> b,b,limm 00110bbb11101001FBBB1111100QQQQQ. */ +{ "sfxtr", 0x30E90F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* sjli u12 00101RRR101000001RRRuuuuuuUUUUUU. */ +{ "sjli", 0x28A08000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, SJLI, CD1, { OPERAND_UIMM12_20 }, { 0 }}, + +/* sleep c 00100001001011110000CCCCCC111111. */ +{ "sleep", 0x212F003F, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_RC }, { 0 }}, + +/* sleep u6 00100001011011110000uuuuuu111111. */ +{ "sleep", 0x216F003F, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_UIMM6_20 }, { 0 }}, + +/* sleep limm 00100001001011110000111110111111. */ +{ "sleep", 0x212F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_LIMM }, { 0 }}, + +/* sleep 00100001011011110000uuuuuu111111. */ +{ "sleep", 0x216F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }}, + +/* sqrt<.f> b,c 00101bbb00101111FBBBCCCCCC110000 */ +{ "sqrt", 0x282F0030, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* sqrt<.f> b,u6 00101bbb01101111FBBBuuuuuu110000 */ +{ "sqrt", 0x286F0030, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* sqrt<.f> 0,u6 0010111001101111F111uuuuuu110000 */ +{ "sqrt", 0x2E6F7030, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* sqrt<.f> 0,limm 0010111000101111F111111110110000 */ +{ "sqrt", 0x2E2F7FB0, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* sqrt<.f> b,limm 00101bbb00101111FBBB111110110000 */ +{ "sqrt", 0x282F0FB0, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* sqrtacc c 00101010001011110000CCCCCC111111. */ +{ "sqrtacc", 0x2A2F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RC }, { 0 }}, + +/* sqrtacc u6 00101010011011110000uuuuuu111111. */ +{ "sqrtacc", 0x2A6F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_UIMM6_20 }, { 0 }}, + +/* sqrtf<.f> 0,c 0010111000101111F111CCCCCC110001 */ +{ "sqrtf", 0x2E2F7031, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* sqrtf<.f> b,c 00101bbb00101111FBBBCCCCCC110001 */ +{ "sqrtf", 0x282F0031, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* sqrtf<.f> b,u6 00101bbb01101111FBBBuuuuuu110001 */ +{ "sqrtf", 0x286F0031, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* sqrtf<.f> 0,u6 0010111001101111F111uuuuuu110001 */ +{ "sqrtf", 0x2E6F7031, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* sqrtf<.f> b,limm 00101bbb00101111FBBB111110110001 */ +{ "sqrtf", 0x282F0FB1, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* sqrtf<.f> 0,limm 0010111000101111F111111110110001 */ +{ "sqrtf", 0x2E2F7FB1, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* sr b,c 00100bbb001010110BBBCCCCCCRRRRRR. */ +{ "sr", 0x202B0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, + +/* sr b,c 00100bbb00101011RBBBCCCCCCRRRRRR. */ +{ "sr", 0x202B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, + +/* sr b,u6 00100bbb011010110BBBuuuuuu000000. */ +{ "sr", 0x206B0000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, + +/* sr b,u6 00100bbb01101011RBBBuuuuuu000000. */ +{ "sr", 0x206B0000, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, + +/* sr b,s12 00100bbb101010110BBBssssssSSSSSS. */ +{ "sr", 0x20AB0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, + +/* sr b,s12 00100bbb10101011RBBBssssssSSSSSS. */ +{ "sr", 0x20AB0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, + +/* sr limm,c 00100110001010110111CCCCCCRRRRRR. */ +{ "sr", 0x262B7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, + +/* sr b,limm 00100bbb001010110BBB111110RRRRRR. */ +{ "sr", 0x202B0F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, + +/* sr limm,c 0010011000101011R111CCCCCCRRRRRR. */ +{ "sr", 0x262B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RC, OPERAND_BRAKETdup }, { 0 }}, + +/* sr b,limm 00100bbb00101011RBBB111110RRRRRR. */ +{ "sr", 0x202B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_RB, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { 0 }}, + +/* sr limm,u6 00100110011010110111uuuuuu000000. */ +{ "sr", 0x266B7000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, + +/* sr limm,u6 0010011001101011R111uuuuuu000000. */ +{ "sr", 0x266B7000, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_UIMM6_20, OPERAND_BRAKETdup }, { 0 }}, + +/* sr limm,s12 00100110101010110111ssssssSSSSSS. */ +{ "sr", 0x26AB7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, + +/* sr limm,s12 0010011010101011R111ssssssSSSSSS. */ +{ "sr", 0x26AB7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_SIMM12_20, OPERAND_BRAKETdup }, { 0 }}, + +/* sr limm,limm 00100110001010110111111110RRRRRR. */ +{ "sr", 0x262B7F80, 0xFFFFFFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { 0 }}, + +/* sr limm,limm 0010011000101011R111111110RRRRRR. */ +{ "sr", 0x262B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_BRAKETdup }, { 0 }}, + +/* st<.di><.aa> c,b 00011bbb000000000BBBCCCCCCDaaZZR. */ +{ "st", 0x18000000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, + +/* st<.di><.aa> c,b 00011bbb000000000BBBCCCCCCDaaZZ0. */ +{ "st", 0x18000000, 0xF8FF8001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, + +/* st<.di><.aa> w6,b 00011bbb000000000BBBwwwwwwDaaZZ1. */ +{ "st", 0x18000001, 0xF8FF8001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, + +/* st<.di><.aa> c,b,s9 00011bbbssssssssSBBBCCCCCCDaaZZR. */ +{ "st", 0x18000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, + +/* st<.di><.aa> c,b,s9 00011bbbssssssssSBBBCCCCCCDaaZZ0. */ +{ "st", 0x18000000, 0xF8000001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, + +/* st<.di><.aa> w6,b,s9 00011bbbssssssssSBBBwwwwwwDaaZZ1. */ +{ "st", 0x18000001, 0xF8000001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, + +/* st<.di> c,limm 00011110000000000111CCCCCCDRRZZR. */ +{ "st", 0x1E007000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26 }}, + +/* st<.di> c,limm 00011110000000000111CCCCCCDRRZZ0. */ +{ "st", 0x1E007000, 0xFFFFF001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RC, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26 }}, + +/* st<.di> w6,limm 00011110000000000111wwwwwwDRRZZ1. */ +{ "st", 0x1E007001, 0xFFFFF001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26 }}, + +/* st<.di><.aa> limm,b,s9 00011bbbssssssssSBBB111110DaaZZR. */ +{ "st", 0x18000F80, 0xF8000FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, + +/* st<.di><.aa> limm,b,s9 00011bbbssssssssSBBB111110DaaZZ0. */ +{ "st", 0x18000F80, 0xF8000FC1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, + +/* st<.di><.aa> w6,limm,s9 00011110ssssssssS111wwwwwwDaaZZ1. */ +{ "st", 0x1E007001, 0xFF007001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, + +/* st<.di><.aa> limm,limm,s9 00011110ssssssssS111111110DaaZZR. */ +{ "st", 0x1E007F80, 0xFF007FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, + +/* st<.di><.aa> limm,limm,s9 00011110ssssssssS111111110DaaZZ0. */ +{ "st", 0x1E007F80, 0xFF007FC1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, + +/* stb_s c,b,u5 10101bbbcccuuuuu. */ +{ "stb_s", 0x0000A800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM5_11_S, OPERAND_BRAKETdup }, { C_ZZ_B }}, + +/* stb_s b,SP,u7 11000bbb011uuuuu. */ +{ "stb_s", 0x0000C060, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { C_ZZ_B }}, + +/* std<.di><.aa> c,b 00011bbb000000000BBBCCCCCCDaa110. */ +{ "std", 0x18000006, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RCD, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }}, + +/* std<.di><.aa> w6,b 00011bbb000000000BBBwwwwwwDaa111. */ +{ "std", 0x18000007, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_RB, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }}, + +/* std<.di><.aa> c,b,s9 00011bbbssssssssSBBBCCCCCCDaa110. */ +{ "std", 0x18000006, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RCD, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }}, + +/* std<.di><.aa> w6,b,s9 00011bbbssssssssSBBBwwwwwwDaa111. */ +{ "std", 0x18000007, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }}, + +/* std<.di> c,limm 00011110000000000111CCCCCCDRR110. */ +{ "std", 0x1E007006, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RCD, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI26, C_ZZ_D }}, + +/* std<.di> w6,limm 00011110000000000111wwwwwwDRR111. */ +{ "std", 0x1E007007, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_BRAKETdup }, { C_DI26, C_ZZ_D }}, + +/* std<.di><.aa> limm,b,s9 00011bbbssssssssSBBB111110Daa110. */ +{ "std", 0x18000F86, 0xF8000FC7, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_RB, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }}, + +/* std<.di><.aa> w6,limm,s9 00011110ssssssssS111wwwwwwDaa111. */ +{ "std", 0x1E007007, 0xFF007007, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_W6, OPERAND_BRAKET, OPERAND_LIMM, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }}, + +/* std<.di><.aa> limm,limm,s9 00011110ssssssssS111111110Daa110. */ +{ "std", 0x1E007F86, 0xFF007FC7, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_LIMM, OPERAND_BRAKET, OPERAND_LIMMdup, OPERAND_SIMM9_8, OPERAND_BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }}, + +/* sth_s c,b,u6 10110bbbcccuuuuu. */ +{ "sth_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_ZZ_H }}, + +/* stm a,u6,b 00101bbb01001101RBBBRuuuuuAAAAAA. */ +{ "stm", 0x284D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RA, OPERAND_UIMM6_A16_21, OPERAND_RB }, { 0 }}, + +/* stm 0,u6,b 00101bbb01001101RBBBRuuuuu111110. */ +{ "stm", 0x284D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_ZA, OPERAND_UIMM6_A16_21, OPERAND_RB }, { 0 }}, + +/* stm a,u6,limm 0010111001001101R111RuuuuuAAAAAA. */ +{ "stm", 0x2E4D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RA, OPERAND_UIMM6_A16_21, OPERAND_LIMM }, { 0 }}, + +/* stm 0,u6,limm 0010111001001101R111Ruuuuu111110. */ +{ "stm", 0x2E4D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_ZA, OPERAND_UIMM6_A16_21, OPERAND_LIMM }, { 0 }}, + +/* stw_s c,b,u6 10110bbbcccuuuuu. */ +{ "stw_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM6_A16_11_S, OPERAND_BRAKETdup }, { C_ZZ_H }}, + +/* st_s b,SP,u7 11000bbb010uuuuu. */ +{ "st_s", 0x0000C040, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RB_S, OPERAND_BRAKET, OPERAND_SP_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { 0 }}, + +/* st_s c,b,u7 10100bbbcccuuuuu. */ +{ "st_s", 0x0000A000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { OPERAND_RC_S, OPERAND_BRAKET, OPERAND_RB_S, OPERAND_UIMM7_A32_11_S, OPERAND_BRAKETdup }, { 0 }}, + +/* st_s OPERAND_R0,GP,s11 01010SSSSSS10sss. */ +{ "st_s", 0x00005010, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, CD2, { OPERAND_R0_S, OPERAND_BRAKET, OPERAND_GP_S, OPERAND_SIMM11_A32_13_S, OPERAND_BRAKETdup }, { 0 }}, + +/* sub<.f> a,b,c 00100bbb00000010FBBBCCCCCCAAAAAA. */ +{ "sub", 0x20020000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* sub<.f> 0,b,c 00100bbb00000010FBBBCCCCCC111110. */ +{ "sub", 0x2002003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* sub<.f><.cc> b,b,c 00100bbb11000010FBBBCCCCCC0QQQQQ. */ +{ "sub", 0x20C20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */ +{ "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* sub<.f> 0,b,u6 00100bbb01000010FBBBuuuuuu111110. */ +{ "sub", 0x2042003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* sub<.f><.cc> b,b,u6 00100bbb11000010FBBBuuuuuu1QQQQQ. */ +{ "sub", 0x20C20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* sub<.f> b,b,s12 00100bbb10000010FBBBssssssSSSSSS. */ +{ "sub", 0x20820000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* sub<.f> a,limm,c 0010011000000010F111CCCCCCAAAAAA. */ +{ "sub", 0x26027000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */ +{ "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* sub<.f> 0,limm,c 0010011000000010F111CCCCCC111110. */ +{ "sub", 0x2602703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* sub<.f> 0,b,limm 00100bbb00000010FBBB111110111110. */ +{ "sub", 0x20020FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* sub<.f><.cc> b,b,limm 00100bbb11000010FBBB1111100QQQQQ. */ +{ "sub", 0x20C20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* sub<.f><.cc> 0,limm,c 0010011011000010F111CCCCCC0QQQQQ. */ +{ "sub", 0x26C27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* sub<.f> a,limm,u6 0010011001000010F111uuuuuuAAAAAA. */ +{ "sub", 0x26427000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* sub<.f> 0,limm,u6 0010011001000010F111uuuuuu111110. */ +{ "sub", 0x2642703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* sub<.f><.cc> 0,limm,u6 0010011011000010F111uuuuuu1QQQQQ. */ +{ "sub", 0x26C27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* sub<.f> 0,limm,s12 0010011010000010F111ssssssSSSSSS. */ +{ "sub", 0x26827000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* sub<.f> a,limm,limm 0010011000000010F111111110AAAAAA. */ +{ "sub", 0x26027F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* sub<.f> 0,limm,limm 0010011000000010F111111110111110. */ +{ "sub", 0x26027FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* sub<.f><.cc> 0,limm,limm 0010011011000010F1111111100QQQQQ. */ +{ "sub", 0x26C27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* sub1<.f> a,b,c 00100bbb00010111FBBBCCCCCCAAAAAA. */ +{ "sub1", 0x20170000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* sub1<.f> 0,b,c 00100bbb00010111FBBBCCCCCC111110. */ +{ "sub1", 0x2017003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* sub1<.f><.cc> b,b,c 00100bbb11010111FBBBCCCCCC0QQQQQ. */ +{ "sub1", 0x20D70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* sub1<.f> a,b,u6 00100bbb01010111FBBBuuuuuuAAAAAA. */ +{ "sub1", 0x20570000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* sub1<.f> 0,b,u6 00100bbb01010111FBBBuuuuuu111110. */ +{ "sub1", 0x2057003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* sub1<.f><.cc> b,b,u6 00100bbb11010111FBBBuuuuuu1QQQQQ. */ +{ "sub1", 0x20D70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* sub1<.f> b,b,s12 00100bbb10010111FBBBssssssSSSSSS. */ +{ "sub1", 0x20970000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* sub1<.f> a,limm,c 0010011000010111F111CCCCCCAAAAAA. */ +{ "sub1", 0x26177000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* sub1<.f> a,b,limm 00100bbb00010111FBBB111110AAAAAA. */ +{ "sub1", 0x20170F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* sub1<.f> 0,limm,c 0010011000010111F111CCCCCC111110. */ +{ "sub1", 0x2617703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* sub1<.f> 0,b,limm 00100bbb00010111FBBB111110111110. */ +{ "sub1", 0x20170FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* sub1<.f><.cc> b,b,limm 00100bbb11010111FBBB1111100QQQQQ. */ +{ "sub1", 0x20D70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* sub1<.f><.cc> 0,limm,c 0010011011010111F111CCCCCC0QQQQQ. */ +{ "sub1", 0x26D77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* sub1<.f> a,limm,u6 0010011001010111F111uuuuuuAAAAAA. */ +{ "sub1", 0x26577000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* sub1<.f> 0,limm,u6 0010011001010111F111uuuuuu111110. */ +{ "sub1", 0x2657703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* sub1<.f><.cc> 0,limm,u6 0010011011010111F111uuuuuu1QQQQQ. */ +{ "sub1", 0x26D77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* sub1<.f> 0,limm,s12 0010011010010111F111ssssssSSSSSS. */ +{ "sub1", 0x26977000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* sub1<.f> a,limm,limm 0010011000010111F111111110AAAAAA. */ +{ "sub1", 0x26177F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* sub1<.f> 0,limm,limm 0010011000010111F111111110111110. */ +{ "sub1", 0x26177FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* sub1<.f><.cc> 0,limm,limm 0010011011010111F1111111100QQQQQ. */ +{ "sub1", 0x26D77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* sub2<.f> a,b,c 00100bbb00011000FBBBCCCCCCAAAAAA. */ +{ "sub2", 0x20180000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* sub2<.f> 0,b,c 00100bbb00011000FBBBCCCCCC111110. */ +{ "sub2", 0x2018003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* sub2<.f><.cc> b,b,c 00100bbb11011000FBBBCCCCCC0QQQQQ. */ +{ "sub2", 0x20D80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* sub2<.f> a,b,u6 00100bbb01011000FBBBuuuuuuAAAAAA. */ +{ "sub2", 0x20580000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* sub2<.f> 0,b,u6 00100bbb01011000FBBBuuuuuu111110. */ +{ "sub2", 0x2058003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* sub2<.f><.cc> b,b,u6 00100bbb11011000FBBBuuuuuu1QQQQQ. */ +{ "sub2", 0x20D80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* sub2<.f> b,b,s12 00100bbb10011000FBBBssssssSSSSSS. */ +{ "sub2", 0x20980000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* sub2<.f> a,limm,c 0010011000011000F111CCCCCCAAAAAA. */ +{ "sub2", 0x26187000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* sub2<.f> a,b,limm 00100bbb00011000FBBB111110AAAAAA. */ +{ "sub2", 0x20180F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* sub2<.f> 0,limm,c 0010011000011000F111CCCCCC111110. */ +{ "sub2", 0x2618703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* sub2<.f> 0,b,limm 00100bbb00011000FBBB111110111110. */ +{ "sub2", 0x20180FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* sub2<.f><.cc> b,b,limm 00100bbb11011000FBBB1111100QQQQQ. */ +{ "sub2", 0x20D80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* sub2<.f><.cc> 0,limm,c 0010011011011000F111CCCCCC0QQQQQ. */ +{ "sub2", 0x26D87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* sub2<.f> a,limm,u6 0010011001011000F111uuuuuuAAAAAA. */ +{ "sub2", 0x26587000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* sub2<.f> 0,limm,u6 0010011001011000F111uuuuuu111110. */ +{ "sub2", 0x2658703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* sub2<.f><.cc> 0,limm,u6 0010011011011000F111uuuuuu1QQQQQ. */ +{ "sub2", 0x26D87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* sub2<.f> 0,limm,s12 0010011010011000F111ssssssSSSSSS. */ +{ "sub2", 0x26987000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* sub2<.f> a,limm,limm 0010011000011000F111111110AAAAAA. */ +{ "sub2", 0x26187F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* sub2<.f> 0,limm,limm 0010011000011000F111111110111110. */ +{ "sub2", 0x26187FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* sub2<.f><.cc> 0,limm,limm 0010011011011000F1111111100QQQQQ. */ +{ "sub2", 0x26D87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* sub3<.f> a,b,c 00100bbb00011001FBBBCCCCCCAAAAAA. */ +{ "sub3", 0x20190000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* sub3<.f> 0,b,c 00100bbb00011001FBBBCCCCCC111110. */ +{ "sub3", 0x2019003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* sub3<.f><.cc> b,b,c 00100bbb11011001FBBBCCCCCC0QQQQQ. */ +{ "sub3", 0x20D90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* sub3<.f> a,b,u6 00100bbb01011001FBBBuuuuuuAAAAAA. */ +{ "sub3", 0x20590000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* sub3<.f> 0,b,u6 00100bbb01011001FBBBuuuuuu111110. */ +{ "sub3", 0x2059003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* sub3<.f><.cc> b,b,u6 00100bbb11011001FBBBuuuuuu1QQQQQ. */ +{ "sub3", 0x20D90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* sub3<.f> b,b,s12 00100bbb10011001FBBBssssssSSSSSS. */ +{ "sub3", 0x20990000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* sub3<.f> a,limm,c 0010011000011001F111CCCCCCAAAAAA. */ +{ "sub3", 0x26197000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* sub3<.f> a,b,limm 00100bbb00011001FBBB111110AAAAAA. */ +{ "sub3", 0x20190F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* sub3<.f> 0,limm,c 0010011000011001F111CCCCCC111110. */ +{ "sub3", 0x2619703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* sub3<.f> 0,b,limm 00100bbb00011001FBBB111110111110. */ +{ "sub3", 0x20190FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* sub3<.f><.cc> b,b,limm 00100bbb11011001FBBB1111100QQQQQ. */ +{ "sub3", 0x20D90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* sub3<.f><.cc> 0,limm,c 0010011011011001F111CCCCCC0QQQQQ. */ +{ "sub3", 0x26D97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* sub3<.f> a,limm,u6 0010011001011001F111uuuuuuAAAAAA. */ +{ "sub3", 0x26597000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* sub3<.f> 0,limm,u6 0010011001011001F111uuuuuu111110. */ +{ "sub3", 0x2659703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* sub3<.f><.cc> 0,limm,u6 0010011011011001F111uuuuuu1QQQQQ. */ +{ "sub3", 0x26D97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* sub3<.f> 0,limm,s12 0010011010011001F111ssssssSSSSSS. */ +{ "sub3", 0x26997000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* sub3<.f> a,limm,limm 0010011000011001F111111110AAAAAA. */ +{ "sub3", 0x26197F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* sub3<.f> 0,limm,limm 0010011000011001F111111110111110. */ +{ "sub3", 0x26197FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* sub3<.f><.cc> 0,limm,limm 0010011011011001F1111111100QQQQQ. */ +{ "sub3", 0x26D97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* subs<.f> a,b,c 00101bbb00000111FBBBCCCCCCAAAAAA. */ +{ "subs", 0x28070000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* subs<.f> 0,b,c 00101bbb00000111FBBBCCCCCC111110. */ +{ "subs", 0x2807003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* subs<.f><.cc> b,b,c 00101bbb11000111FBBBCCCCCC0QQQQQ. */ +{ "subs", 0x28C70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* subs<.f> a,b,u6 00101bbb01000111FBBBuuuuuuAAAAAA. */ +{ "subs", 0x28470000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* subs<.f> 0,b,u6 00101bbb01000111FBBBuuuuuu111110. */ +{ "subs", 0x2847003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* subs<.f><.cc> b,b,u6 00101bbb11000111FBBBuuuuuu1QQQQQ. */ +{ "subs", 0x28C70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* subs<.f> b,b,s12 00101bbb10000111FBBBssssssSSSSSS. */ +{ "subs", 0x28870000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* subs<.f> a,limm,c 0010111000000111F111CCCCCCAAAAAA. */ +{ "subs", 0x2E077000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* subs<.f> a,b,limm 00101bbb00000111FBBB111110AAAAAA. */ +{ "subs", 0x28070F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* subs<.f> 0,limm,c 0010111000000111F111CCCCCC111110. */ +{ "subs", 0x2E07703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* subs<.f> 0,b,limm 00101bbb00000111FBBB111110111110. */ +{ "subs", 0x28070FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* subs<.f> a,limm,c 0010111000000111F111CCCCCCAAAAAA. */ +{ "subs", 0x2E077000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* subs<.f><.cc> b,b,limm 00101bbb11000111FBBB1111100QQQQQ. */ +{ "subs", 0x28C70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* subs<.f><.cc> 0,limm,c 0010111011000111F111CCCCCC0QQQQQ. */ +{ "subs", 0x2EC77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* subs<.f> a,limm,u6 0010111001000111F111uuuuuuAAAAAA. */ +{ "subs", 0x2E477000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* subs<.f> 0,limm,u6 0010111001000111F111uuuuuu111110. */ +{ "subs", 0x2E47703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* subs<.f><.cc> 0,limm,u6 0010111011000111F111uuuuuu1QQQQQ. */ +{ "subs", 0x2EC77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* subs<.f> 0,limm,s12 0010111010000111F111ssssssSSSSSS. */ +{ "subs", 0x2E877000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* subs<.f> a,limm,limm 0010111000000111F111111110AAAAAA. */ +{ "subs", 0x2E077F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* subs<.f> 0,limm,limm 0010111000000111F111111110111110. */ +{ "subs", 0x2E077FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* subs<.f><.cc> 0,limm,limm 0010111011000111F1111111100QQQQQ. */ +{ "subs", 0x2EC77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* subsdw<.f> a,b,c 00101bbb00101001FBBBCCCCCCAAAAAA. */ +{ "subsdw", 0x28290000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* subsdw<.f> 0,b,c 00101bbb00101001FBBBCCCCCC111110. */ +{ "subsdw", 0x2829003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* subsdw<.f><.cc> b,b,c 00101bbb11101001FBBBCCCCCC0QQQQQ. */ +{ "subsdw", 0x28E90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* subsdw<.f> a,b,u6 00101bbb01101001FBBBuuuuuuAAAAAA. */ +{ "subsdw", 0x28690000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* subsdw<.f> 0,b,u6 00101bbb01101001FBBBuuuuuu111110. */ +{ "subsdw", 0x2869003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* subsdw<.f><.cc> b,b,u6 00101bbb11101001FBBBuuuuuu1QQQQQ. */ +{ "subsdw", 0x28E90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* subsdw<.f> b,b,s12 00101bbb10101001FBBBssssssSSSSSS. */ +{ "subsdw", 0x28A90000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* subsdw<.f> a,limm,c 0010111000101001F111CCCCCCAAAAAA. */ +{ "subsdw", 0x2E297000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* subsdw<.f> a,b,limm 00101bbb00101001FBBB111110AAAAAA. */ +{ "subsdw", 0x28290F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* subsdw<.f> 0,limm,c 0010111000101001F111CCCCCC111110. */ +{ "subsdw", 0x2E29703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* subsdw<.f> 0,b,limm 00101bbb00101001FBBB111110111110. */ +{ "subsdw", 0x28290FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* subsdw<.f><.cc> b,b,limm 00101bbb11101001FBBB1111100QQQQQ. */ +{ "subsdw", 0x28E90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* subsdw<.f><.cc> 0,limm,c 0010111011101001F111CCCCCC0QQQQQ. */ +{ "subsdw", 0x2EE97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* subsdw<.f> a,limm,u6 0010111001101001F111uuuuuuAAAAAA. */ +{ "subsdw", 0x2E697000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* subsdw<.f> 0,limm,u6 0010111001101001F111uuuuuu111110. */ +{ "subsdw", 0x2E69703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* subsdw<.f><.cc> 0,limm,u6 0010111011101001F111uuuuuu1QQQQQ. */ +{ "subsdw", 0x2EE97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* subsdw<.f> 0,limm,s12 0010111010101001F111ssssssSSSSSS. */ +{ "subsdw", 0x2EA97000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* subsdw<.f> a,limm,limm 0010111000101001F111111110AAAAAA. */ +{ "subsdw", 0x2E297F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* subsdw<.f> 0,limm,limm 0010111000101001F111111110111110. */ +{ "subsdw", 0x2E297FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* subsdw<.f><.cc> 0,limm,limm 0010111011101001F1111111100QQQQQ. */ +{ "subsdw", 0x2EE97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* sub_s b,b,c 01111bbbccc00010. */ +{ "sub_s", 0x00007802, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, + +/* sub_s a,b,c 01001bbbccc10aaa. */ +{ "sub_s", 0x00004810, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, CD2, { OPERAND_RA_S, OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, + +/* sub_s c,b,u3 01101bbbccc01uuu. */ +{ "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RC_S, OPERAND_RB_S, OPERAND_UIMM3_13_S }, { 0 }}, + +/* sub_s b,b,u5 10111bbb011uuuuu. */ +{ "sub_s", 0x0000B860, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_UIMM5_11_S }, { 0 }}, + +/* sub_s SP,SP,u7 11000001101uuuuu. */ +{ "sub_s", 0x0000C1A0, 0x0000FFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_SP_S, OPERAND_SP_Sdup, OPERAND_UIMM7_A32_11_S }, { 0 }}, + +/* sub_s.ne b,b,b 01111bbb11000000. */ +{ "sub_s", 0x000078C0, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, SUB, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RB_Sdup }, { C_NE, C_CC_NE }}, + +/* swap<.f> b,c 00101bbb00101111FBBBCCCCCC000000. */ +{ "swap", 0x282F0000, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* swap<.f> 0,c 0010111000101111F111CCCCCC000000. */ +{ "swap", 0x2E2F7000, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* swap<.f> b,u6 00101bbb01101111FBBBuuuuuu000000. */ +{ "swap", 0x286F0000, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* swap<.f> 0,u6 0010111001101111F111uuuuuu000000. */ +{ "swap", 0x2E6F7000, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* swap<.f> b,limm 00101bbb00101111FBBB111110000000. */ +{ "swap", 0x282F0F80, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* swap<.f> 0,limm 0010111000101111F111111110000000. */ +{ "swap", 0x2E2F7F80, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* swape<.f> b,c 00101bbb00101111FBBBCCCCCC001001. */ +{ "swape", 0x282F0009, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* swape<.f> 0,c 0010111000101111F111CCCCCC001001. */ +{ "swape", 0x2E2F7009, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* swape<.f> b,u6 00101bbb01101111FBBBuuuuuu001001. */ +{ "swape", 0x286F0009, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* swape<.f> 0,u6 0010111001101111F111uuuuuu001001. */ +{ "swape", 0x2E6F7009, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* swape<.f> b,limm 00101bbb00101111FBBB111110001001. */ +{ "swape", 0x282F0F89, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* swape<.f> 0,limm 0010111000101111F111111110001001. */ +{ "swape", 0x2E2F7F89, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* swi 00100010011011110000000000111111. */ +{ "swi", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }}, + +/* swi_s 0111101011100000. */ +{ "swi_s", 0x00007AE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }}, + +/* swi_s u6 01111uuuuuu11111. */ +{ "swi_s", 0x0000781F, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_UIMM6_5_S }, { 0 }}, + +/* sync 00100011011011110000000000111111. */ +{ "sync", 0x236F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }}, + +/* trap0 00100010011011110000000000111111. */ +{ "trap0", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700, KERNEL, NONE, { 0 }, { 0 }}, + +/* trap_s u6 01111uuuuuu11110. */ +{ "trap_s", 0x0000781E, 0x0000F81F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_UIMM6_5_S }, { 0 }}, + +/* tst b,c 00100bbb000010111BBBCCCCCCRRRRRR. */ +{ "tst", 0x200B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* tst b,c 00100bbb000010111BBBCCCCCC000000. */ +{ "tst", 0x200B8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* tst<.cc> b,c 00100bbb110010111BBBCCCCCC0QQQQQ. */ +{ "tst", 0x20CB8000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RC }, { C_CC }}, + +/* tst b,u6 00100bbb010010111BBBuuuuuuRRRRRR. */ +{ "tst", 0x204B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* tst b,u6 00100bbb010010111BBBuuuuuu000000. */ +{ "tst", 0x204B8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* tst<.cc> b,u6 00100bbb110010111BBBuuuuuu1QQQQQ. */ +{ "tst", 0x20CB8020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { C_CC }}, + +/* tst b,s12 00100bbb100010111BBBssssssSSSSSS. */ +{ "tst", 0x208B8000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_SIMM12_20 }, { 0 }}, + +/* tst limm,c 00100110000010111111CCCCCCRRRRRR. */ +{ "tst", 0x260BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* tst b,limm 00100bbb000010111BBB111110RRRRRR. */ +{ "tst", 0x200B8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* tst limm,c 00100110000010111111CCCCCC000000. */ +{ "tst", 0x260BF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* tst b,limm 00100bbb000010111BBB111110000000. */ +{ "tst", 0x200B8F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* tst<.cc> b,limm 00100bbb110010111BBB1111100QQQQQ. */ +{ "tst", 0x20CB8F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_LIMM }, { C_CC }}, + +/* tst<.cc> limm,c 00100110110010111111CCCCCC0QQQQQ. */ +{ "tst", 0x26CBF000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* tst limm,u6 00100110010010111111uuuuuuRRRRRR. */ +{ "tst", 0x264BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* tst limm,u6 00100110010010111111uuuuuu000000. */ +{ "tst", 0x264BF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* tst<.cc> limm,u6 00100110110010111111uuuuuu1QQQQQ. */ +{ "tst", 0x26CBF020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* tst limm,s12 00100110100010111111ssssssSSSSSS. */ +{ "tst", 0x268BF000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* tst limm,limm 00100110000010111111111110RRRRRR. */ +{ "tst", 0x260BFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* tst limm,limm 00100110000010111111111110000000. */ +{ "tst", 0x260BFF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* tst<.cc> limm,limm 001001101100101111111111100QQQQQ. */ +{ "tst", 0x26CBFF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* tst_s b,c 01111bbbccc01011. */ +{ "tst_s", 0x0000780B, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RC_S }, { 0 }}, + +/* unimp_s 0111100111100000. */ +{ "unimp_s", 0x000079E0, 0x0000FFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }}, + +/* upkqb<.f> a,b,c 00110bbb00100001FBBBCCCCCCAAAAAA. */ +{ "upkqb", 0x30210000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* upkqb<.f><.cc> b,b,c 00110bbb11100001FBBBCCCCCC0QQQQQ. */ +{ "upkqb", 0x30E10000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* upkqb<.f> a,b,u6 00110bbb01100001FBBBuuuuuuAAAAAA. */ +{ "upkqb", 0x30610000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* upkqb<.f> b,b,s12 00110bbb10100001FBBBssssssSSSSSS. */ +{ "upkqb", 0x30A10000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* upkqb<.f> a,limm,c 0011011000100001F111CCCCCCAAAAAA. */ +{ "upkqb", 0x36217000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* upkqb<.f> a,b,limm 00110bbb00100001FBBB111110AAAAAA. */ +{ "upkqb", 0x30210F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* upkqb<.f><.cc> b,b,limm 00110bbb11100001FBBB1111100QQQQQ. */ +{ "upkqb", 0x30E10F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* vabs2h b,c 00101bbb001011110BBBCCCCCC101000. */ +{ "vabs2h", 0x282F0028, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, + +/* vabs2h 0,c 00101110001011110111CCCCCC101000. */ +{ "vabs2h", 0x2E2F7028, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, + +/* vabs2h b,u6 00101bbb011011110BBBuuuuuu101000. */ +{ "vabs2h", 0x286F0028, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, + +/* vabs2h 0,u6 00101110011011110111uuuuuu101000. */ +{ "vabs2h", 0x2E6F7028, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, + +/* vabs2h b,limm 00101bbb001011110BBB111110101000. */ +{ "vabs2h", 0x282F0FA8, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, + +/* vabs2h 0,limm 00101110001011110111111110101000. */ +{ "vabs2h", 0x2E2F7FA8, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, + +/* vabss2h b,c 00101bbb001011110BBBCCCCCC101001. */ +{ "vabss2h", 0x282F0029, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, + +/* vabss2h 0,c 00101110001011110111CCCCCC101001. */ +{ "vabss2h", 0x2E2F7029, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, + +/* vabss2h b,u6 00101bbb011011110BBBuuuuuu101001. */ +{ "vabss2h", 0x286F0029, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, + +/* vabss2h 0,u6 00101110011011110111uuuuuu101001. */ +{ "vabss2h", 0x2E6F7029, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, + +/* vabss2h b,limm 00101bbb001011110BBB111110101001. */ +{ "vabss2h", 0x282F0FA9, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, + +/* vabss2h 0,limm 00101110001011110111111110101001. */ +{ "vabss2h", 0x2E2F7FA9, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, + +/* vadd2 a,b,c 00101bbb001111000BBBCCCCCCAAAAAA. */ +{ "vadd2", 0x283C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vadd2 0,b,c 00101bbb001111000BBBCCCCCC111110. */ +{ "vadd2", 0x283C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vadd2<.cc> b,b,c 00101bbb111111000BBBCCCCCC0QQQQQ. */ +{ "vadd2", 0x28FC0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vadd2 a,b,u6 00101bbb011111000BBBuuuuuuAAAAAA. */ +{ "vadd2", 0x287C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadd2 0,b,u6 00101bbb011111000BBBuuuuuu111110. */ +{ "vadd2", 0x287C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadd2<.cc> b,b,u6 00101bbb111111000BBBuuuuuu1QQQQQ. */ +{ "vadd2", 0x28FC0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vadd2 b,b,s12 00101bbb101111000BBBssssssSSSSSS. */ +{ "vadd2", 0x28BC0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vadd2 a,limm,c 00101110001111000111CCCCCCAAAAAA. */ +{ "vadd2", 0x2E3C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vadd2 a,b,limm 00101bbb001111000BBB111110AAAAAA. */ +{ "vadd2", 0x283C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vadd2 0,limm,c 00101110001111000111CCCCCC111110. */ +{ "vadd2", 0x2E3C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vadd2 0,b,limm 00101bbb001111000BBB111110111110. */ +{ "vadd2", 0x283C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vadd2<.cc> b,b,limm 00101bbb111111000BBB1111100QQQQQ. */ +{ "vadd2", 0x28FC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vadd2<.cc> 0,limm,c 00101110111111000111CCCCCC0QQQQQ. */ +{ "vadd2", 0x2EFC7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vadd2 a,limm,u6 00101110011111000111uuuuuuAAAAAA. */ +{ "vadd2", 0x2E7C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadd2 0,limm,u6 00101110011111000111uuuuuu111110. */ +{ "vadd2", 0x2E7C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadd2<.cc> 0,limm,u6 00101110111111000111uuuuuu1QQQQQ. */ +{ "vadd2", 0x2EFC7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vadd2 0,limm,s12 00101110101111000111ssssssSSSSSS. */ +{ "vadd2", 0x2EBC7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vadd2 a,limm,limm 00101110001111000111111110AAAAAA. */ +{ "vadd2", 0x2E3C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vadd2 0,limm,limm 00101110001111000111111110111110. */ +{ "vadd2", 0x2E3C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vadd2<.cc> 0,limm,limm 001011101111110001111111100QQQQQ. */ +{ "vadd2", 0x2EFC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vadd2h a,b,c 00101bbb000101000BBBCCCCCCAAAAAA. */ +{ "vadd2h", 0x28140000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vadd2h 0,b,c 00101bbb000101000BBBCCCCCC111110. */ +{ "vadd2h", 0x2814003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vadd2h<.cc> b,b,c 00101bbb110101000BBBCCCCCC0QQQQQ. */ +{ "vadd2h", 0x28D40000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vadd2h a,b,u6 00101bbb010101000BBBuuuuuuAAAAAA. */ +{ "vadd2h", 0x28540000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadd2h 0,b,u6 00101bbb010101000BBBuuuuuu111110. */ +{ "vadd2h", 0x2854003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadd2h<.cc> b,b,u6 00101bbb110101000BBBuuuuuu1QQQQQ. */ +{ "vadd2h", 0x28D40020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vadd2h b,b,s12 00101bbb100101000BBBssssssSSSSSS. */ +{ "vadd2h", 0x28940000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vadd2h a,limm,c 00101110000101000111CCCCCCAAAAAA. */ +{ "vadd2h", 0x2E147000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vadd2h a,b,limm 00101bbb000101000BBB111110AAAAAA. */ +{ "vadd2h", 0x28140F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vadd2h 0,limm,c 00101110000101000111CCCCCC111110. */ +{ "vadd2h", 0x2E14703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vadd2h 0,b,limm 00101bbb000101000BBB111110111110. */ +{ "vadd2h", 0x28140FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vadd2h<.cc> b,b,limm 00101bbb110101000BBB1111100QQQQQ. */ +{ "vadd2h", 0x28D40F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vadd2h<.cc> 0,limm,c 00101110110101000111CCCCCC0QQQQQ. */ +{ "vadd2h", 0x2ED47000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vadd2h a,limm,u6 00101110010101000111uuuuuuAAAAAA. */ +{ "vadd2h", 0x2E547000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadd2h 0,limm,u6 00101110010101000111uuuuuu111110. */ +{ "vadd2h", 0x2E54703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadd2h<.cc> 0,limm,u6 00101110110101000111uuuuuu1QQQQQ. */ +{ "vadd2h", 0x2ED47020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vadd2h 0,limm,s12 00101110100101000111ssssssSSSSSS. */ +{ "vadd2h", 0x2E947000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vadd2h a,limm,limm 00101110000101000111111110AAAAAA. */ +{ "vadd2h", 0x2E147F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vadd2h 0,limm,limm 00101110000101000111111110111110. */ +{ "vadd2h", 0x2E147FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vadd2h<.cc> 0,limm,limm 001011101101010001111111100QQQQQ. */ +{ "vadd2h", 0x2ED47F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vadd4b a,b,c 00101bbb001001000BBBCCCCCCAAAAAA. */ +{ "vadd4b", 0x28240000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vadd4b 0,b,c 00101bbb001001000BBBCCCCCC111110. */ +{ "vadd4b", 0x2824003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vadd4b<.cc> b,b,c 00101bbb111001000BBBCCCCCC0QQQQQ. */ +{ "vadd4b", 0x28E40000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vadd4b a,b,u6 00101bbb011001000BBBuuuuuuAAAAAA. */ +{ "vadd4b", 0x28640000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadd4b 0,b,u6 00101bbb011001000BBBuuuuuu111110. */ +{ "vadd4b", 0x2864003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadd4b<.cc> b,b,u6 00101bbb111001000BBBuuuuuu1QQQQQ. */ +{ "vadd4b", 0x28E40020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vadd4b b,b,s12 00101bbb101001000BBBssssssSSSSSS. */ +{ "vadd4b", 0x28A40000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vadd4b a,limm,c 00101110001001000111CCCCCCAAAAAA. */ +{ "vadd4b", 0x2E247000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vadd4b a,b,limm 00101bbb001001000BBB111110AAAAAA. */ +{ "vadd4b", 0x28240F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vadd4b 0,limm,c 00101110011001000111CCCCCC111110. */ +{ "vadd4b", 0x2E64703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vadd4b 0,b,limm 00101bbb001001000BBB111110111110. */ +{ "vadd4b", 0x28240FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vadd4b<.cc> b,b,limm 00101bbb111001000BBB1111100QQQQQ. */ +{ "vadd4b", 0x28E40F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vadd4b<.cc> 0,limm,c 00101110111001000111CCCCCC0QQQQQ. */ +{ "vadd4b", 0x2EE47000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vadd4b a,limm,u6 00101110011001000111uuuuuuAAAAAA. */ +{ "vadd4b", 0x2E647000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadd4b 0,limm,u6 00101110011001000111uuuuuu111110. */ +{ "vadd4b", 0x2E64703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadd4b<.cc> 0,limm,u6 00101110111001000111uuuuuu1QQQQQ. */ +{ "vadd4b", 0x2EE47020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vadd4b 0,limm,s12 00101110101001000111ssssssSSSSSS. */ +{ "vadd4b", 0x2EA47000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vadd4b a,limm,limm 00101110001001000111111110AAAAAA. */ +{ "vadd4b", 0x2E247F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vadd4b 0,limm,limm 00101110001001000111111110111110. */ +{ "vadd4b", 0x2E247FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vadd4b<.cc> 0,limm,limm 001011101110010001111111100QQQQQ. */ +{ "vadd4b", 0x2EE47F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vadd4h a,b,c 00101bbb001110000BBBCCCCCCAAAAAA. */ +{ "vadd4h", 0x28380000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vadd4h 0,b,c 00101bbb001110000BBBCCCCCC111110. */ +{ "vadd4h", 0x2838003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vadd4h<.cc> b,b,c 00101bbb111110000BBBCCCCCC0QQQQQ. */ +{ "vadd4h", 0x28F80000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vadd4h a,b,u6 00101bbb011110000BBBuuuuuuAAAAAA. */ +{ "vadd4h", 0x28780000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadd4h 0,b,u6 00101bbb011110000BBBuuuuuu111110. */ +{ "vadd4h", 0x2878003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadd4h<.cc> b,b,u6 00101bbb111110000BBBuuuuuu1QQQQQ. */ +{ "vadd4h", 0x28F80020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vadd4h b,b,s12 00101bbb101110000BBBssssssSSSSSS. */ +{ "vadd4h", 0x28B80000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vadd4h a,limm,c 00101110001110000111CCCCCCAAAAAA. */ +{ "vadd4h", 0x2E387000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vadd4h a,b,limm 00101bbb001110000BBB111110AAAAAA. */ +{ "vadd4h", 0x28380F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vadd4h 0,limm,c 00101110001110000111CCCCCC111110. */ +{ "vadd4h", 0x2E38703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vadd4h 0,b,limm 00101bbb001110000BBB111110111110. */ +{ "vadd4h", 0x28380FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vadd4h<.cc> b,b,limm 00101bbb111110000BBB1111100QQQQQ. */ +{ "vadd4h", 0x28F80F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vadd4h<.cc> 0,limm,c 00101110111110000111CCCCCC0QQQQQ. */ +{ "vadd4h", 0x2EF87000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vadd4h a,limm,u6 00101110011110000111uuuuuuAAAAAA. */ +{ "vadd4h", 0x2E787000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadd4h 0,limm,u6 00101110011110000111uuuuuu111110. */ +{ "vadd4h", 0x2E78703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadd4h<.cc> 0,limm,u6 00101110111110000111uuuuuu1QQQQQ. */ +{ "vadd4h", 0x2EF87020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vadd4h 0,limm,s12 00101110101110000111ssssssSSSSSS. */ +{ "vadd4h", 0x2EB87000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vadd4h a,limm,limm 00101110001110000111111110AAAAAA. */ +{ "vadd4h", 0x2E387F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vadd4h 0,limm,limm 00101110001110000111111110111110. */ +{ "vadd4h", 0x2E387FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vadd4h<.cc> 0,limm,limm 001011101111100001111111100QQQQQ. */ +{ "vadd4h", 0x2EF87F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vadds2<.cc> b,b,c 00101bbb111111000BBBCCCCCC0QQQQQ */ +{ "vadds2", 0x28FC0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vadds2 a,b,c 00101bbb001111000BBBCCCCCCAAAAAA */ +{ "vadds2", 0x283C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vadds2 0,b,c 00101bbb001111000BBBCCCCCC111110 */ +{ "vadds2", 0x283C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vadds2<.cc> b,b,u6 00101bbb111111000BBBuuuuuu1QQQQQ */ +{ "vadds2", 0x28FC0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vadds2 a,b,u6 00101bbb011111000BBBuuuuuuAAAAAA */ +{ "vadds2", 0x287C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadds2 0,b,u6 00101bbb011111000BBBuuuuuu111110 */ +{ "vadds2", 0x287C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadds2 b,b,s12 00101bbb101111000BBBssssssSSSSSS */ +{ "vadds2", 0x28BC0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vadds2 a,b,limm 00101bbb001111000BBB111110AAAAAA */ +{ "vadds2", 0x283C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vadds2<.cc> 0,limm,c 00101110111111000111CCCCCC0QQQQQ */ +{ "vadds2", 0x2EFC7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vadds2 0,b,limm 00101bbb001111000BBB111110111110 */ +{ "vadds2", 0x283C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vadds2<.cc> b,b,limm 00101bbb111111000BBB1111100QQQQQ */ +{ "vadds2", 0x28FC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vadds2 a,limm,c 00101110001111000111CCCCCCAAAAAA */ +{ "vadds2", 0x2E3C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vadds2 0,limm,c 00101110001111000111CCCCCC111110 */ +{ "vadds2", 0x2E3C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vadds2<.cc> 0,limm,u6 00101110111111000111uuuuuu1QQQQQ */ +{ "vadds2", 0x2EFC7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vadds2 0,limm,u6 00101110011111000111uuuuuu111110 */ +{ "vadds2", 0x2E7C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadds2 a,limm,u6 00101110011111000111uuuuuuAAAAAA */ +{ "vadds2", 0x2E7C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadds2 0,limm,s12 00101110101111000111ssssssSSSSSS */ +{ "vadds2", 0x2EBC7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vadds2 0,limm,limm 00101110001111000111111110111110 */ +{ "vadds2", 0x2E3C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vadds2 a,limm,limm 00101110001111000111111110AAAAAA */ +{ "vadds2", 0x2E3C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vadds2<.cc> 0,limm,limm 001011101111110001111111100QQQQQ */ +{ "vadds2", 0x2EFC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vadds2h a,b,c 00101bbb000101001BBBCCCCCCAAAAAA. */ +{ "vadds2h", 0x28148000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vadds2h 0,b,c 00101bbb000101001BBBCCCCCC111110. */ +{ "vadds2h", 0x2814803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vadds2h<.cc> b,b,c 00101bbb110101001BBBCCCCCC0QQQQQ. */ +{ "vadds2h", 0x28D48000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vadds2h a,b,u6 00101bbb010101001BBBuuuuuuAAAAAA. */ +{ "vadds2h", 0x28548000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadds2h 0,b,u6 00101bbb010101001BBBuuuuuu111110. */ +{ "vadds2h", 0x2854803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadds2h<.cc> b,b,u6 00101bbb110101001BBBuuuuuu1QQQQQ. */ +{ "vadds2h", 0x28D48020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vadds2h b,b,s12 00101bbb100101001BBBssssssSSSSSS. */ +{ "vadds2h", 0x28948000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vadds2h a,limm,c 00101110000101001111CCCCCCAAAAAA. */ +{ "vadds2h", 0x2E14F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vadds2h a,b,limm 00101bbb000101001BBB111110AAAAAA. */ +{ "vadds2h", 0x28148F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vadds2h 0,limm,c 00101110000101001111CCCCCC111110. */ +{ "vadds2h", 0x2E14F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vadds2h 0,b,limm 00101bbb000101001BBB111110111110. */ +{ "vadds2h", 0x28148FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vadds2h<.cc> b,b,limm 00101bbb110101001BBB1111100QQQQQ. */ +{ "vadds2h", 0x28D48F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vadds2h<.cc> 0,limm,c 00101110110101001111CCCCCC0QQQQQ. */ +{ "vadds2h", 0x2ED4F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vadds2h a,limm,u6 00101110010101001111uuuuuuAAAAAA. */ +{ "vadds2h", 0x2E54F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadds2h 0,limm,u6 00101110010101001111uuuuuu111110. */ +{ "vadds2h", 0x2E54F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadds2h<.cc> 0,limm,u6 00101110110101001111uuuuuu1QQQQQ. */ +{ "vadds2h", 0x2ED4F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vadds2h 0,limm,s12 00101110100101001111ssssssSSSSSS. */ +{ "vadds2h", 0x2E94F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vadds2h a,limm,limm 00101110000101001111111110AAAAAA. */ +{ "vadds2h", 0x2E14FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vadds2h 0,limm,limm 00101110000101001111111110111110. */ +{ "vadds2h", 0x2E14FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vadds2h<.cc> 0,limm,limm 001011101101010011111111100QQQQQ. */ +{ "vadds2h", 0x2ED4FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vadds4h a,b,c 00101bbb001110000BBBCCCCCCAAAAAA */ +{ "vadds4h", 0x28380000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vadds4h 0,b,c 00101bbb001110000BBBCCCCCC111110 */ +{ "vadds4h", 0x2838003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vadds4h<.cc> b,b,c 00101bbb111110000BBBCCCCCC0QQQQQ */ +{ "vadds4h", 0x28F80000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vadds4h 0,b,u6 00101bbb011110000BBBuuuuuu111110 */ +{ "vadds4h", 0x2878003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadds4h<.cc> b,b,u6 00101bbb111110000BBBuuuuuu1QQQQQ */ +{ "vadds4h", 0x28F80020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vadds4h a,b,u6 00101bbb011110000BBBuuuuuuAAAAAA */ +{ "vadds4h", 0x28780000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadds4h b,b,s12 00101bbb101110000BBBssssssSSSSSS */ +{ "vadds4h", 0x28B80000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vadds4h<.cc> b,b,limm 00101bbb111110000BBB1111100QQQQQ */ +{ "vadds4h", 0x28F80F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vadds4h a,b,limm 00101bbb001110000BBB111110AAAAAA */ +{ "vadds4h", 0x28380F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vadds4h<.cc> 0,limm,c 00101110111110000111CCCCCC0QQQQQ */ +{ "vadds4h", 0x2EF87000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vadds4h a,limm,c 00101110001110000111CCCCCCAAAAAA */ +{ "vadds4h", 0x2E387000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vadds4h 0,b,limm 00101bbb001110000BBB111110111110 */ +{ "vadds4h", 0x28380FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vadds4h 0,limm,c 00101110001110000111CCCCCC111110 */ +{ "vadds4h", 0x2E38703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vadds4h<.cc> 0,limm,u6 00101110111110000111uuuuuu1QQQQQ */ +{ "vadds4h", 0x2EF87020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vadds4h a,limm,u6 00101110011110000111uuuuuuAAAAAA */ +{ "vadds4h", 0x2E787000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadds4h 0,limm,u6 00101110011110000111uuuuuu111110 */ +{ "vadds4h", 0x2E78703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vadds4h 0,limm,s12 00101110101110000111ssssssSSSSSS */ +{ "vadds4h", 0x2EB87000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vadds4h a,limm,limm 00101110001110000111111110AAAAAA */ +{ "vadds4h", 0x2E387F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vadds4h<.cc> 0,limm,limm 001011101111100001111111100QQQQQ */ +{ "vadds4h", 0x2EF87F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vadds4h 0,limm,limm 00101110001110000111111110111110 */ +{ "vadds4h", 0x2E387FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vaddsub a,b,c 00101bbb001111100BBBCCCCCCAAAAAA. */ +{ "vaddsub", 0x283E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vaddsub 0,b,c 00101bbb001111100BBBCCCCCC111110. */ +{ "vaddsub", 0x283E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vaddsub<.cc> b,b,c 00101bbb111111100BBBCCCCCC0QQQQQ. */ +{ "vaddsub", 0x28FE0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vaddsub a,b,u6 00101bbb011111100BBBuuuuuuAAAAAA. */ +{ "vaddsub", 0x287E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsub 0,b,u6 00101bbb011111100BBBuuuuuu111110. */ +{ "vaddsub", 0x287E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsub<.cc> b,b,u6 00101bbb111111100BBBuuuuuu1QQQQQ. */ +{ "vaddsub", 0x28FE0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vaddsub b,b,s12 00101bbb101111100BBBssssssSSSSSS. */ +{ "vaddsub", 0x28BE0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vaddsub a,limm,c 00101110001111100111CCCCCCAAAAAA. */ +{ "vaddsub", 0x2E3E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vaddsub a,b,limm 00101bbb001111100BBB111110AAAAAA. */ +{ "vaddsub", 0x283E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vaddsub 0,limm,c 00101110001111100111CCCCCC111110. */ +{ "vaddsub", 0x2E3E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vaddsub 0,b,limm 00101bbb001111100BBB111110111110. */ +{ "vaddsub", 0x283E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vaddsub<.cc> b,b,limm 00101bbb111111100BBB1111100QQQQQ. */ +{ "vaddsub", 0x28FE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vaddsub<.cc> 0,limm,c 00101110111111100111CCCCCC0QQQQQ. */ +{ "vaddsub", 0x2EFE7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vaddsub a,limm,u6 00101110011111100111uuuuuuAAAAAA. */ +{ "vaddsub", 0x2E7E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsub 0,limm,u6 00101110011111100111uuuuuu111110. */ +{ "vaddsub", 0x2E7E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsub<.cc> 0,limm,u6 00101110111111100111uuuuuu1QQQQQ. */ +{ "vaddsub", 0x2EFE7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vaddsub 0,limm,s12 00101110101111100111ssssssSSSSSS. */ +{ "vaddsub", 0x2EBE7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vaddsub a,limm,limm 00101110001111100111111110AAAAAA. */ +{ "vaddsub", 0x2E3E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vaddsub 0,limm,limm 00101110001111100111111110111110. */ +{ "vaddsub", 0x2E3E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vaddsub<.cc> 0,limm,limm 001011101111111001111111100QQQQQ. */ +{ "vaddsub", 0x2EFE7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vaddsub2h a,b,c 00101bbb000101100BBBCCCCCCAAAAAA. */ +{ "vaddsub2h", 0x28160000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vaddsub2h 0,b,c 00101bbb000101100BBBCCCCCC111110. */ +{ "vaddsub2h", 0x2816003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vaddsub2h<.cc> b,b,c 00101bbb110101100BBBCCCCCC0QQQQQ. */ +{ "vaddsub2h", 0x28D60000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vaddsub2h a,b,u6 00101bbb010101100BBBuuuuuuAAAAAA. */ +{ "vaddsub2h", 0x28560000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsub2h 0,b,u6 00101bbb010101100BBBuuuuuu111110. */ +{ "vaddsub2h", 0x2856003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsub2h<.cc> b,b,u6 00101bbb110101100BBBuuuuuu1QQQQQ. */ +{ "vaddsub2h", 0x28D60020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vaddsub2h b,b,s12 00101bbb100101100BBBssssssSSSSSS. */ +{ "vaddsub2h", 0x28960000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vaddsub2h a,limm,c 00101110000101100111CCCCCCAAAAAA. */ +{ "vaddsub2h", 0x2E167000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vaddsub2h a,b,limm 00101bbb000101100BBB111110AAAAAA. */ +{ "vaddsub2h", 0x28160F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vaddsub2h 0,limm,c 00101110000101100111CCCCCC111110. */ +{ "vaddsub2h", 0x2E16703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vaddsub2h 0,b,limm 00101bbb000101100BBB111110111110. */ +{ "vaddsub2h", 0x28160FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vaddsub2h<.cc> b,b,limm 00101bbb110101100BBB1111100QQQQQ. */ +{ "vaddsub2h", 0x28D60F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vaddsub2h<.cc> 0,limm,c 00101110110101100111CCCCCC0QQQQQ. */ +{ "vaddsub2h", 0x2ED67000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vaddsub2h a,limm,u6 00101110010101100111uuuuuuAAAAAA. */ +{ "vaddsub2h", 0x2E567000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsub2h 0,limm,u6 00101110010101100111uuuuuu111110. */ +{ "vaddsub2h", 0x2E56703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsub2h<.cc> 0,limm,u6 00101110110101100111uuuuuu1QQQQQ. */ +{ "vaddsub2h", 0x2ED67020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vaddsub2h 0,limm,s12 00101110100101100111ssssssSSSSSS. */ +{ "vaddsub2h", 0x2E967000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vaddsub2h a,limm,limm 00101110000101100111111110AAAAAA. */ +{ "vaddsub2h", 0x2E167F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vaddsub2h 0,limm,limm 00101110000101100111111110111110. */ +{ "vaddsub2h", 0x2E167FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vaddsub2h<.cc> 0,limm,limm 001011101101011001111111100QQQQQ. */ +{ "vaddsub2h", 0x2ED67F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vaddsub4h a,b,c 00101bbb001110100BBBCCCCCCAAAAAA. */ +{ "vaddsub4h", 0x283A0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vaddsub4h 0,b,c 00101bbb001110100BBBCCCCCC111110. */ +{ "vaddsub4h", 0x283A003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vaddsub4h<.cc> b,b,c 00101bbb111110100BBBCCCCCC0QQQQQ. */ +{ "vaddsub4h", 0x28FA0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vaddsub4h a,b,u6 00101bbb011110100BBBuuuuuuAAAAAA. */ +{ "vaddsub4h", 0x287A0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsub4h 0,b,u6 00101bbb011110100BBBuuuuuu111110. */ +{ "vaddsub4h", 0x287A003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsub4h<.cc> b,b,u6 00101bbb111110100BBBuuuuuu1QQQQQ. */ +{ "vaddsub4h", 0x28FA0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vaddsub4h b,b,s12 00101bbb101110100BBBssssssSSSSSS. */ +{ "vaddsub4h", 0x28BA0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vaddsub4h a,limm,c 00101110001110100111CCCCCCAAAAAA. */ +{ "vaddsub4h", 0x2E3A7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vaddsub4h a,b,limm 00101bbb001110100BBB111110AAAAAA. */ +{ "vaddsub4h", 0x283A0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vaddsub4h 0,limm,c 00101110001110100111CCCCCC111110. */ +{ "vaddsub4h", 0x2E3A703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vaddsub4h 0,b,limm 00101bbb001110100BBB111110111110. */ +{ "vaddsub4h", 0x283A0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vaddsub4h<.cc> b,b,limm 00101bbb111110100BBB1111100QQQQQ. */ +{ "vaddsub4h", 0x28FA0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vaddsub4h<.cc> 0,limm,c 00101110111110100111CCCCCC0QQQQQ. */ +{ "vaddsub4h", 0x2EFA7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vaddsub4h a,limm,u6 00101110011110100111uuuuuuAAAAAA. */ +{ "vaddsub4h", 0x2E7A7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsub4h 0,limm,u6 00101110011110100111uuuuuu111110. */ +{ "vaddsub4h", 0x2E7A703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsub4h<.cc> 0,limm,u6 00101110111110100111uuuuuu1QQQQQ. */ +{ "vaddsub4h", 0x2EFA7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vaddsub4h 0,limm,s12 00101110101110100111ssssssSSSSSS. */ +{ "vaddsub4h", 0x2EBA7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vaddsub4h a,limm,limm 00101110001110100111111110AAAAAA. */ +{ "vaddsub4h", 0x2E3A7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vaddsub4h 0,limm,limm 00101110001110100111111110111110. */ +{ "vaddsub4h", 0x2E3A7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vaddsub4h<.cc> 0,limm,limm 001011101111101001111111100QQQQQ. */ +{ "vaddsub4h", 0x2EFA7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vaddsubs a,b,c 00101bbb001111100BBBCCCCCCAAAAAA */ +{ "vaddsubs", 0x283E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vaddsubs<.cc> b,b,c 00101bbb111111100BBBCCCCCC0QQQQQ */ +{ "vaddsubs", 0x28FE0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vaddsubs 0,b,c 00101bbb001111100BBBCCCCCC111110 */ +{ "vaddsubs", 0x283E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vaddsubs a,b,u6 00101bbb011111100BBBuuuuuuAAAAAA */ +{ "vaddsubs", 0x287E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsubs 0,b,u6 00101bbb011111100BBBuuuuuu111110 */ +{ "vaddsubs", 0x287E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsubs<.cc> b,b,u6 00101bbb111111100BBBuuuuuu1QQQQQ */ +{ "vaddsubs", 0x28FE0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vaddsubs b,b,s12 00101bbb101111100BBBssssssSSSSSS */ +{ "vaddsubs", 0x28BE0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vaddsubs a,limm,c 00101110001111100111CCCCCCAAAAAA */ +{ "vaddsubs", 0x2E3E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vaddsubs a,b,limm 00101bbb001111100BBB111110AAAAAA */ +{ "vaddsubs", 0x283E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vaddsubs<.cc> 0,limm,c 00101110111111100111CCCCCC0QQQQQ */ +{ "vaddsubs", 0x2EFE7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vaddsubs 0,limm,c 00101110001111100111CCCCCC111110 */ +{ "vaddsubs", 0x2E3E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vaddsubs<.cc> b,b,limm 00101bbb111111100BBB1111100QQQQQ */ +{ "vaddsubs", 0x28FE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vaddsubs 0,b,limm 00101bbb001111100BBB111110111110 */ +{ "vaddsubs", 0x283E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vaddsubs a,limm,u6 00101110011111100111uuuuuuAAAAAA */ +{ "vaddsubs", 0x2E7E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsubs 0,limm,u6 00101110011111100111uuuuuu111110 */ +{ "vaddsubs", 0x2E7E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsubs<.cc> 0,limm,u6 00101110111111100111uuuuuu1QQQQQ */ +{ "vaddsubs", 0x2EFE7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vaddsubs 0,limm,s12 00101110101111100111ssssssSSSSSS */ +{ "vaddsubs", 0x2EBE7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vaddsubs 0,limm,limm 00101110001111100111111110111110 */ +{ "vaddsubs", 0x2E3E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vaddsubs<.cc> 0,limm,limm 001011101111111001111111100QQQQQ */ +{ "vaddsubs", 0x2EFE7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vaddsubs a,limm,limm 00101110001111100111111110AAAAAA */ +{ "vaddsubs", 0x2E3E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vaddsubs2h a,b,c 00101bbb000101101BBBCCCCCCAAAAAA. */ +{ "vaddsubs2h", 0x28168000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vaddsubs2h 0,b,c 00101bbb000101101BBBCCCCCC111110. */ +{ "vaddsubs2h", 0x2816803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vaddsubs2h<.cc> b,b,c 00101bbb110101101BBBCCCCCC0QQQQQ. */ +{ "vaddsubs2h", 0x28D68000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vaddsubs2h a,b,u6 00101bbb010101101BBBuuuuuuAAAAAA. */ +{ "vaddsubs2h", 0x28568000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsubs2h 0,b,u6 00101bbb010101101BBBuuuuuu111110. */ +{ "vaddsubs2h", 0x2856803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsubs2h<.cc> b,b,u6 00101bbb110101101BBBuuuuuu1QQQQQ. */ +{ "vaddsubs2h", 0x28D68020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vaddsubs2h b,b,s12 00101bbb100101101BBBssssssSSSSSS. */ +{ "vaddsubs2h", 0x28968000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vaddsubs2h a,limm,c 00101110000101101111CCCCCCAAAAAA. */ +{ "vaddsubs2h", 0x2E16F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vaddsubs2h a,b,limm 00101bbb000101101BBB111110AAAAAA. */ +{ "vaddsubs2h", 0x28168F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vaddsubs2h 0,limm,c 00101110000101101111CCCCCC111110. */ +{ "vaddsubs2h", 0x2E16F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vaddsubs2h 0,b,limm 00101bbb000101101BBB111110111110. */ +{ "vaddsubs2h", 0x28168FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vaddsubs2h<.cc> b,b,limm 00101bbb110101101BBB1111100QQQQQ. */ +{ "vaddsubs2h", 0x28D68F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vaddsubs2h<.cc> 0,limm,c 00101110110101101111CCCCCC0QQQQQ. */ +{ "vaddsubs2h", 0x2ED6F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vaddsubs2h a,limm,u6 00101110010101101111uuuuuuAAAAAA. */ +{ "vaddsubs2h", 0x2E56F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsubs2h 0,limm,u6 00101110010101101111uuuuuu111110. */ +{ "vaddsubs2h", 0x2E56F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsubs2h<.cc> 0,limm,u6 00101110110101101111uuuuuu1QQQQQ. */ +{ "vaddsubs2h", 0x2ED6F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vaddsubs2h 0,limm,s12 00101110100101101111ssssssSSSSSS. */ +{ "vaddsubs2h", 0x2E96F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vaddsubs2h a,limm,limm 00101110000101101111111110AAAAAA. */ +{ "vaddsubs2h", 0x2E16FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vaddsubs2h 0,limm,limm 00101110000101101111111110111110. */ +{ "vaddsubs2h", 0x2E16FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vaddsubs2h<.cc> 0,limm,limm 001011101101011011111111100QQQQQ. */ +{ "vaddsubs2h", 0x2ED6FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vaddsubs4h a,b,c 00101bbb001110100BBBCCCCCCAAAAAA */ +{ "vaddsubs4h", 0x283A0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vaddsubs4h 0,b,c 00101bbb001110100BBBCCCCCC111110 */ +{ "vaddsubs4h", 0x283A003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vaddsubs4h<.cc> b,b,c 00101bbb111110100BBBCCCCCC0QQQQQ */ +{ "vaddsubs4h", 0x28FA0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vaddsubs4h a,b,u6 00101bbb011110100BBBuuuuuuAAAAAA */ +{ "vaddsubs4h", 0x287A0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsubs4h<.cc> b,b,u6 00101bbb111110100BBBuuuuuu1QQQQQ */ +{ "vaddsubs4h", 0x28FA0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vaddsubs4h 0,b,u6 00101bbb011110100BBBuuuuuu111110 */ +{ "vaddsubs4h", 0x287A003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsubs4h b,b,s12 00101bbb101110100BBBssssssSSSSSS */ +{ "vaddsubs4h", 0x28BA0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vaddsubs4h a,limm,c 00101110001110100111CCCCCCAAAAAA */ +{ "vaddsubs4h", 0x2E3A7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vaddsubs4h<.cc> 0,limm,c 00101110111110100111CCCCCC0QQQQQ */ +{ "vaddsubs4h", 0x2EFA7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vaddsubs4h a,b,limm 00101bbb001110100BBB111110AAAAAA */ +{ "vaddsubs4h", 0x283A0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vaddsubs4h<.cc> b,b,limm 00101bbb111110100BBB1111100QQQQQ */ +{ "vaddsubs4h", 0x28FA0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vaddsubs4h 0,b,limm 00101bbb001110100BBB111110111110 */ +{ "vaddsubs4h", 0x283A0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vaddsubs4h 0,limm,c 00101110001110100111CCCCCC111110 */ +{ "vaddsubs4h", 0x2E3A703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vaddsubs4h 0,limm,u6 00101110011110100111uuuuuu111110 */ +{ "vaddsubs4h", 0x2E7A703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsubs4h a,limm,u6 00101110011110100111uuuuuuAAAAAA */ +{ "vaddsubs4h", 0x2E7A7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vaddsubs4h<.cc> 0,limm,u6 00101110111110100111uuuuuu1QQQQQ */ +{ "vaddsubs4h", 0x2EFA7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vaddsubs4h 0,limm,s12 00101110101110100111ssssssSSSSSS */ +{ "vaddsubs4h", 0x2EBA7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vaddsubs4h<.cc> 0,limm,limm 001011101111101001111111100QQQQQ */ +{ "vaddsubs4h", 0x2EFA7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vaddsubs4h 0,limm,limm 00101110001110100111111110111110 */ +{ "vaddsubs4h", 0x2E3A7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vaddsubs4h a,limm,limm 00101110001110100111111110AAAAAA */ +{ "vaddsubs4h", 0x2E3A7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* valgn2h a,b,c 00101bbb000011010BBBCCCCCCAAAAAA. */ +{ "valgn2h", 0x280D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* valgn2h 0,b,c 00101bbb000011010BBBCCCCCC111110. */ +{ "valgn2h", 0x280D003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* valgn2h<.cc> b,b,c 00101bbb110011010BBBCCCCCC0QQQQQ. */ +{ "valgn2h", 0x28CD0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* valgn2h a,b,u6 00101bbb010011010BBBuuuuuuAAAAAA. */ +{ "valgn2h", 0x284D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* valgn2h 0,b,u6 00101bbb010011010BBBuuuuuu111110. */ +{ "valgn2h", 0x284D003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* valgn2h<.cc> b,b,u6 00101bbb110011010BBBuuuuuu1QQQQQ. */ +{ "valgn2h", 0x28CD0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* valgn2h b,b,s12 00101bbb100011010BBBssssssSSSSSS. */ +{ "valgn2h", 0x288D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* valgn2h a,limm,c 00101110000011010111CCCCCCAAAAAA. */ +{ "valgn2h", 0x2E0D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* valgn2h a,b,limm 00101bbb000011010BBB111110AAAAAA. */ +{ "valgn2h", 0x280D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* valgn2h 0,limm,c 00101110000011010111CCCCCC111110. */ +{ "valgn2h", 0x2E0D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* valgn2h 0,b,limm 00101bbb000011010BBB111110111110. */ +{ "valgn2h", 0x280D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* valgn2h<.cc> b,b,limm 00101bbb110011010BBB1111100QQQQQ. */ +{ "valgn2h", 0x28CD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* valgn2h<.cc> 0,limm,c 00101110110011010111CCCCCC0QQQQQ. */ +{ "valgn2h", 0x2ECD7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* valgn2h a,limm,u6 00101110010011010111uuuuuuAAAAAA. */ +{ "valgn2h", 0x2E4D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* valgn2h 0,limm,u6 00101110010011010111uuuuuu111110. */ +{ "valgn2h", 0x2E4D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* valgn2h<.cc> 0,limm,u6 00101110110011010111uuuuuu1QQQQQ. */ +{ "valgn2h", 0x2ECD7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* valgn2h 0,limm,s12 00101110100011010111ssssssSSSSSS. */ +{ "valgn2h", 0x2E8D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* valgn2h a,limm,limm 00101110000011010111111110AAAAAA. */ +{ "valgn2h", 0x2E0D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* valgn2h 0,limm,limm 00101110000011010111111110111110. */ +{ "valgn2h", 0x2E0D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* valgn2h<.cc> 0,limm,limm 001011101100110101111111100QQQQQ. */ +{ "valgn2h", 0x2ECD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vasl2h a,b,c 00101bbb001000010BBBCCCCCCAAAAAA. */ +{ "vasl2h", 0x28210000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vasl2h 0,b,c 00101bbb001000010BBBCCCCCC111110. */ +{ "vasl2h", 0x2821003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vasl2h<.cc> b,b,c 00101bbb111000010BBBCCCCCC0QQQQQ. */ +{ "vasl2h", 0x28E10000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vasl2h a,b,u6 00101bbb011000010BBBuuuuuuAAAAAA. */ +{ "vasl2h", 0x28610000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vasl2h 0,b,u6 00101bbb011000010BBBuuuuuu111110. */ +{ "vasl2h", 0x2861003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vasl2h<.cc> b,b,u6 00101bbb111000010BBBuuuuuu1QQQQQ. */ +{ "vasl2h", 0x28E10020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vasl2h b,b,s12 00101bbb101000010BBBssssssSSSSSS. */ +{ "vasl2h", 0x28A10000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vasl2h a,limm,c 00101110001000010111CCCCCCAAAAAA. */ +{ "vasl2h", 0x2E217000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vasl2h a,b,limm 00101bbb001000010BBB111110AAAAAA. */ +{ "vasl2h", 0x28210F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vasl2h 0,limm,c 00101110011000010111CCCCCC111110. */ +{ "vasl2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vasl2h 0,b,limm 00101bbb001000010BBB111110111110. */ +{ "vasl2h", 0x28210FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vasl2h<.cc> b,b,limm 00101bbb111000010BBB1111100QQQQQ. */ +{ "vasl2h", 0x28E10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vasl2h<.cc> 0,limm,c 00101110111000010111CCCCCC0QQQQQ. */ +{ "vasl2h", 0x2EE17000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vasl2h a,limm,u6 00101110011000010111uuuuuuAAAAAA. */ +{ "vasl2h", 0x2E617000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vasl2h 0,limm,u6 00101110011000010111uuuuuu111110. */ +{ "vasl2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vasl2h<.cc> 0,limm,u6 00101110111000010111uuuuuu1QQQQQ. */ +{ "vasl2h", 0x2EE17020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vasl2h 0,limm,s12 00101110101000010111ssssssSSSSSS. */ +{ "vasl2h", 0x2EA17000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vasl2h a,limm,limm 00101110001000010111111110AAAAAA. */ +{ "vasl2h", 0x2E217F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vasl2h 0,limm,limm 00101110001000010111111110111110. */ +{ "vasl2h", 0x2E217FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vasl2h<.cc> 0,limm,limm 001011101110000101111111100QQQQQ. */ +{ "vasl2h", 0x2EE17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vasls2h a,b,c 00101bbb001000011BBBCCCCCCAAAAAA. */ +{ "vasls2h", 0x28218000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vasls2h 0,b,c 00101bbb001000010BBBCCCCCC111110. */ +{ "vasls2h", 0x2821003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vasls2h<.cc> b,b,c 00101bbb111000011BBBCCCCCC0QQQQQ. */ +{ "vasls2h", 0x28E18000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vasls2h a,b,u6 00101bbb011000011BBBuuuuuuAAAAAA. */ +{ "vasls2h", 0x28618000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vasls2h 0,b,u6 00101bbb011000010BBBuuuuuu111110. */ +{ "vasls2h", 0x2861003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vasls2h<.cc> b,b,u6 00101bbb111000011BBBuuuuuu1QQQQQ. */ +{ "vasls2h", 0x28E18020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vasls2h b,b,s12 00101bbb101000011BBBssssssSSSSSS. */ +{ "vasls2h", 0x28A18000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vasls2h a,limm,c 00101110001000010111CCCCCCAAAAAA. */ +{ "vasls2h", 0x2E217000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vasls2h a,b,limm 00101bbb001000010BBB111110AAAAAA. */ +{ "vasls2h", 0x28210F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vasls2h 0,limm,c 00101110011000010111CCCCCC111110. */ +{ "vasls2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vasls2h 0,b,limm 00101bbb001000010BBB111110111110. */ +{ "vasls2h", 0x28210FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vasls2h<.cc> b,b,limm 00101bbb111000010BBB1111100QQQQQ. */ +{ "vasls2h", 0x28E10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vasls2h<.cc> 0,limm,c 00101110111000010111CCCCCC0QQQQQ. */ +{ "vasls2h", 0x2EE17000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vasls2h a,limm,u6 00101110011000010111uuuuuuAAAAAA. */ +{ "vasls2h", 0x2E617000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vasls2h 0,limm,u6 00101110011000010111uuuuuu111110. */ +{ "vasls2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vasls2h<.cc> 0,limm,u6 00101110111000010111uuuuuu1QQQQQ. */ +{ "vasls2h", 0x2EE17020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vasls2h 0,limm,s12 00101110101000010111ssssssSSSSSS. */ +{ "vasls2h", 0x2EA17000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vasls2h a,limm,limm 00101110001000010111111110AAAAAA. */ +{ "vasls2h", 0x2E217F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vasls2h 0,limm,limm 00101110001000010111111110111110. */ +{ "vasls2h", 0x2E217FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vasls2h<.cc> 0,limm,limm 001011101110000101111111100QQQQQ. */ +{ "vasls2h", 0x2EE17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vasr2h a,b,c 00101bbb001000100BBBCCCCCCAAAAAA. */ +{ "vasr2h", 0x28220000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vasr2h 0,b,c 00101bbb001000100BBBCCCCCC111110. */ +{ "vasr2h", 0x2822003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vasr2h<.cc> b,b,c 00101bbb111000100BBBCCCCCC0QQQQQ. */ +{ "vasr2h", 0x28E20000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vasr2h a,b,u6 00101bbb011000100BBBuuuuuuAAAAAA. */ +{ "vasr2h", 0x28620000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vasr2h 0,b,u6 00101bbb011000100BBBuuuuuu111110. */ +{ "vasr2h", 0x2862003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vasr2h<.cc> b,b,u6 00101bbb111000100BBBuuuuuu1QQQQQ. */ +{ "vasr2h", 0x28E20020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vasr2h b,b,s12 00101bbb101000100BBBssssssSSSSSS. */ +{ "vasr2h", 0x28A20000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vasr2h a,limm,c 00101110001000100111CCCCCCAAAAAA. */ +{ "vasr2h", 0x2E227000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vasr2h a,b,limm 00101bbb001000100BBB111110AAAAAA. */ +{ "vasr2h", 0x28220F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vasr2h 0,limm,c 00101110011000100111CCCCCC111110. */ +{ "vasr2h", 0x2E62703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vasr2h 0,b,limm 00101bbb001000100BBB111110111110. */ +{ "vasr2h", 0x28220FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vasr2h<.cc> b,b,limm 00101bbb111000100BBB1111100QQQQQ. */ +{ "vasr2h", 0x28E20F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vasr2h<.cc> 0,limm,c 00101110111000100111CCCCCC0QQQQQ. */ +{ "vasr2h", 0x2EE27000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vasr2h a,limm,u6 00101110011000100111uuuuuuAAAAAA. */ +{ "vasr2h", 0x2E627000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vasr2h 0,limm,u6 00101110011000100111uuuuuu111110. */ +{ "vasr2h", 0x2E62703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vasr2h<.cc> 0,limm,u6 00101110111000100111uuuuuu1QQQQQ. */ +{ "vasr2h", 0x2EE27020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vasr2h 0,limm,s12 00101110101000100111ssssssSSSSSS. */ +{ "vasr2h", 0x2EA27000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vasr2h a,limm,limm 00101110001000100111111110AAAAAA. */ +{ "vasr2h", 0x2E227F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vasr2h 0,limm,limm 00101110001000100111111110111110. */ +{ "vasr2h", 0x2E227FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vasr2h<.cc> 0,limm,limm 001011101110001001111111100QQQQQ. */ +{ "vasr2h", 0x2EE27F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vasrs2h a,b,c 00101bbb001000101BBBCCCCCCAAAAAA. */ +{ "vasrs2h", 0x28228000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vasrs2h 0,b,c 00101bbb001000101BBBCCCCCC111110. */ +{ "vasrs2h", 0x2822803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vasrs2h<.cc> b,b,c 00101bbb111000101BBBCCCCCC0QQQQQ. */ +{ "vasrs2h", 0x28E28000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vasrs2h a,b,u6 00101bbb011000101BBBuuuuuuAAAAAA. */ +{ "vasrs2h", 0x28628000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vasrs2h 0,b,u6 00101bbb011000101BBBuuuuuu111110. */ +{ "vasrs2h", 0x2862803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vasrs2h<.cc> b,b,u6 00101bbb111000101BBBuuuuuu1QQQQQ. */ +{ "vasrs2h", 0x28E28020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vasrs2h b,b,s12 00101bbb101000101BBBssssssSSSSSS. */ +{ "vasrs2h", 0x28A28000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vasrs2h a,limm,c 00101110001000101111CCCCCCAAAAAA. */ +{ "vasrs2h", 0x2E22F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vasrs2h a,b,limm 00101bbb001000101BBB111110AAAAAA. */ +{ "vasrs2h", 0x28228F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vasrs2h 0,limm,c 00101110011000101111CCCCCC111110. */ +{ "vasrs2h", 0x2E62F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vasrs2h 0,b,limm 00101bbb001000101BBB111110111110. */ +{ "vasrs2h", 0x28228FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vasrs2h<.cc> b,b,limm 00101bbb111000101BBB1111100QQQQQ. */ +{ "vasrs2h", 0x28E28F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vasrs2h<.cc> 0,limm,c 00101110111000101111CCCCCC0QQQQQ. */ +{ "vasrs2h", 0x2EE2F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vasrs2h a,limm,u6 00101110011000101111uuuuuuAAAAAA. */ +{ "vasrs2h", 0x2E62F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vasrs2h 0,limm,u6 00101110011000101111uuuuuu111110. */ +{ "vasrs2h", 0x2E62F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vasrs2h<.cc> 0,limm,u6 00101110111000101111uuuuuu1QQQQQ. */ +{ "vasrs2h", 0x2EE2F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vasrs2h 0,limm,s12 00101110101000101111ssssssSSSSSS. */ +{ "vasrs2h", 0x2EA2F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vasrs2h a,limm,limm 00101110001000101111111110AAAAAA. */ +{ "vasrs2h", 0x2E22FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vasrs2h 0,limm,limm 00101110001000101111111110111110. */ +{ "vasrs2h", 0x2E22FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vasrs2h<.cc> 0,limm,limm 001011101110001011111111100QQQQQ. */ +{ "vasrs2h", 0x2EE2FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vasrsr2h a,b,c 00101bbb001000111BBBCCCCCCAAAAAA. */ +{ "vasrsr2h", 0x28238000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vasrsr2h 0,b,c 00101bbb001000111BBBCCCCCC111110. */ +{ "vasrsr2h", 0x2823803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vasrsr2h<.cc> b,b,c 00101bbb111000111BBBCCCCCC0QQQQQ. */ +{ "vasrsr2h", 0x28E38000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vasrsr2h a,b,u6 00101bbb011000111BBBuuuuuuAAAAAA. */ +{ "vasrsr2h", 0x28638000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vasrsr2h 0,b,u6 00101bbb011000111BBBuuuuuu111110. */ +{ "vasrsr2h", 0x2863803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vasrsr2h<.cc> b,b,u6 00101bbb111000111BBBuuuuuu1QQQQQ. */ +{ "vasrsr2h", 0x28E38020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vasrsr2h b,b,s12 00101bbb101000111BBBssssssSSSSSS. */ +{ "vasrsr2h", 0x28A38000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vasrsr2h a,limm,c 00101110001000111111CCCCCCAAAAAA. */ +{ "vasrsr2h", 0x2E23F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vasrsr2h a,b,limm 00101bbb001000111BBB111110AAAAAA. */ +{ "vasrsr2h", 0x28238F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vasrsr2h 0,limm,c 00101110011000111111CCCCCC111110. */ +{ "vasrsr2h", 0x2E63F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vasrsr2h 0,b,limm 00101bbb001000111BBB111110111110. */ +{ "vasrsr2h", 0x28238FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vasrsr2h<.cc> b,b,limm 00101bbb111000111BBB1111100QQQQQ. */ +{ "vasrsr2h", 0x28E38F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vasrsr2h<.cc> 0,limm,c 00101110111000111111CCCCCC0QQQQQ. */ +{ "vasrsr2h", 0x2EE3F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vasrsr2h a,limm,u6 00101110011000111111uuuuuuAAAAAA. */ +{ "vasrsr2h", 0x2E63F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vasrsr2h 0,limm,u6 00101110011000111111uuuuuu111110. */ +{ "vasrsr2h", 0x2E63F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vasrsr2h<.cc> 0,limm,u6 00101110111000111111uuuuuu1QQQQQ. */ +{ "vasrsr2h", 0x2EE3F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vasrsr2h 0,limm,s12 00101110101000111111ssssssSSSSSS. */ +{ "vasrsr2h", 0x2EA3F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vasrsr2h a,limm,limm 00101110001000111111111110AAAAAA. */ +{ "vasrsr2h", 0x2E23FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vasrsr2h 0,limm,limm 00101110001000111111111110111110. */ +{ "vasrsr2h", 0x2E23FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vasrsr2h<.cc> 0,limm,limm 001011101110001111111111100QQQQQ. */ +{ "vasrsr2h", 0x2EE3FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vbfdw<.f> b,c 00101bbb00101111FBBBCCCCCC001010. */ +{ "vbfdw", 0x282F000A, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { C_F }}, + +/* vbfdw<.f> 0,c 0010111000101111F111CCCCCC001010. */ +{ "vbfdw", 0x2E2F700A, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { C_F }}, + +/* vbfdw<.f> b,u6 00101bbb01101111FBBBuuuuuu001010. */ +{ "vbfdw", 0x286F000A, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { C_F }}, + +/* vbfdw<.f> 0,u6 0010111001101111F111uuuuuu001010. */ +{ "vbfdw", 0x2E6F700A, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { C_F }}, + +/* vbfdw<.f> b,limm 00101bbb00101111FBBB111110001010. */ +{ "vbfdw", 0x282F0F8A, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { C_F }}, + +/* vbfdw<.f> 0,limm 0010111000101111F111111110001010. */ +{ "vbfdw", 0x2E2F7F8A, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { C_F }}, + +/* vext2bhl b,c 00101bbb001011110BBBCCCCCC100100. */ +{ "vext2bhl", 0x282F0024, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, + +/* vext2bhl 0,c 00101110001011110111CCCCCC100100. */ +{ "vext2bhl", 0x2E2F7024, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, + +/* vext2bhl b,u6 00101bbb011011110BBBuuuuuu100100. */ +{ "vext2bhl", 0x286F0024, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, + +/* vext2bhl 0,u6 00101110011011110111uuuuuu100100. */ +{ "vext2bhl", 0x2E6F7024, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, + +/* vext2bhl b,limm 00101bbb001011110BBB111110100100. */ +{ "vext2bhl", 0x282F0FA4, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, + +/* vext2bhl 0,limm 00101110001011110111111110100100. */ +{ "vext2bhl", 0x2E2F7FA4, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, + +/* vext2bhlf 0,c 00101110001011110111CCCCCC100000 */ +{ "vext2bhlf", 0x2E2F7020, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, + +/* vext2bhlf b,c 00101bbb001011110BBBCCCCCC100000 */ +{ "vext2bhlf", 0x282F0020, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vext2bhlf b,u6 00101bbb011011110BBBuuuuuu100000 */ +{ "vext2bhlf", 0x286F0020, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vext2bhlf 0,u6 00101110011011110111uuuuuu100000 */ +{ "vext2bhlf", 0x2E6F7020, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, + +/* vext2bhlf b,limm 00101bbb001011110BBB111110100000 */ +{ "vext2bhlf", 0x282F0FA0, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vext2bhlf 0,limm 00101110001011110111111110100000 */ +{ "vext2bhlf", 0x2E2F7FA0, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, + +/* vext2bhm b,c 00101bbb001011110BBBCCCCCC100101. */ +{ "vext2bhm", 0x282F0025, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, + +/* vext2bhm 0,c 00101110001011110111CCCCCC100101. */ +{ "vext2bhm", 0x2E2F7025, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, + +/* vext2bhm b,u6 00101bbb011011110BBBuuuuuu100101. */ +{ "vext2bhm", 0x286F0025, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, + +/* vext2bhm 0,u6 00101110011011110111uuuuuu100101. */ +{ "vext2bhm", 0x2E6F7025, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, + +/* vext2bhm b,limm 00101bbb001011110BBB111110100101. */ +{ "vext2bhm", 0x282F0FA5, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, + +/* vext2bhm 0,limm 00101110001011110111111110100101. */ +{ "vext2bhm", 0x2E2F7FA5, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, + +/* vext2bhmf b,c 00101bbb001011110BBBCCCCCC100001 */ +{ "vext2bhmf", 0x282F0021, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vext2bhmf 0,c 00101110001011110111CCCCCC100001 */ +{ "vext2bhmf", 0x2E2F7021, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, + +/* vext2bhmf b,u6 00101bbb011011110BBBuuuuuu100001 */ +{ "vext2bhmf", 0x286F0021, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vext2bhmf 0,u6 00101110011011110111uuuuuu100001 */ +{ "vext2bhmf", 0x2E6F7021, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, + +/* vext2bhmf 0,limm 00101110001011110111111110100001 */ +{ "vext2bhmf", 0x2E2F7FA1, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, + +/* vext2bhmf b,limm 00101bbb001011110BBB111110100001 */ +{ "vext2bhmf", 0x282F0FA1, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vlsr2h a,b,c 00101bbb001000110BBBCCCCCCAAAAAA. */ +{ "vlsr2h", 0x28230000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vlsr2h 0,b,c 00101bbb001000110BBBCCCCCC111110. */ +{ "vlsr2h", 0x2823003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vlsr2h<.cc> b,b,c 00101bbb111000110BBBCCCCCC0QQQQQ. */ +{ "vlsr2h", 0x28E30000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vlsr2h a,b,u6 00101bbb011000110BBBuuuuuuAAAAAA. */ +{ "vlsr2h", 0x28630000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vlsr2h 0,b,u6 00101bbb011000110BBBuuuuuu111110. */ +{ "vlsr2h", 0x2863003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vlsr2h<.cc> b,b,u6 00101bbb111000110BBBuuuuuu1QQQQQ. */ +{ "vlsr2h", 0x28E30020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vlsr2h b,b,s12 00101bbb101000110BBBssssssSSSSSS. */ +{ "vlsr2h", 0x28A30000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vlsr2h a,limm,c 00101110001000110111CCCCCCAAAAAA. */ +{ "vlsr2h", 0x2E237000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vlsr2h a,b,limm 00101bbb001000110BBB111110AAAAAA. */ +{ "vlsr2h", 0x28230F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vlsr2h 0,limm,c 00101110011000110111CCCCCC111110. */ +{ "vlsr2h", 0x2E63703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vlsr2h 0,b,limm 00101bbb001000110BBB111110111110. */ +{ "vlsr2h", 0x28230FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vlsr2h<.cc> b,b,limm 00101bbb111000110BBB1111100QQQQQ. */ +{ "vlsr2h", 0x28E30F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vlsr2h<.cc> 0,limm,c 00101110111000110111CCCCCC0QQQQQ. */ +{ "vlsr2h", 0x2EE37000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vlsr2h a,limm,u6 00101110011000110111uuuuuuAAAAAA. */ +{ "vlsr2h", 0x2E637000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vlsr2h 0,limm,u6 00101110011000110111uuuuuu111110. */ +{ "vlsr2h", 0x2E63703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vlsr2h<.cc> 0,limm,u6 00101110111000110111uuuuuu1QQQQQ. */ +{ "vlsr2h", 0x2EE37020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vlsr2h 0,limm,s12 00101110101000110111ssssssSSSSSS. */ +{ "vlsr2h", 0x2EA37000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vlsr2h a,limm,limm 00101110001000110111111110AAAAAA. */ +{ "vlsr2h", 0x2E237F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vlsr2h 0,limm,limm 00101110001000110111111110111110. */ +{ "vlsr2h", 0x2E237FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vlsr2h<.cc> 0,limm,limm 001011101110001101111111100QQQQQ. */ +{ "vlsr2h", 0x2EE37F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vmac2h a,b,c 00101bbb000111100BBBCCCCCCAAAAAA. */ +{ "vmac2h", 0x281E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmac2h 0,b,c 00101bbb000111100BBBCCCCCC111110. */ +{ "vmac2h", 0x281E003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmac2h<.cc> b,b,c 00101bbb110111100BBBCCCCCC0QQQQQ. */ +{ "vmac2h", 0x28DE0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vmac2h a,b,u6 00101bbb010111100BBBuuuuuuAAAAAA. */ +{ "vmac2h", 0x285E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmac2h 0,b,u6 00101bbb010111100BBBuuuuuu111110. */ +{ "vmac2h", 0x285E003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmac2h<.cc> b,b,u6 00101bbb110111100BBBuuuuuu1QQQQQ. */ +{ "vmac2h", 0x28DE0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmac2h b,b,s12 00101bbb100111100BBBssssssSSSSSS. */ +{ "vmac2h", 0x289E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmac2h a,limm,c 00101110000111100111CCCCCCAAAAAA. */ +{ "vmac2h", 0x2E1E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmac2h a,b,limm 00101bbb000111100BBB111110AAAAAA. */ +{ "vmac2h", 0x281E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmac2h 0,limm,c 00101110000111100111CCCCCC111110. */ +{ "vmac2h", 0x2E1E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmac2h 0,b,limm 00101bbb000111100BBB111110111110. */ +{ "vmac2h", 0x281E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmac2h<.cc> b,b,limm 00101bbb110111100BBB1111100QQQQQ. */ +{ "vmac2h", 0x28DE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vmac2h<.cc> 0,limm,c 00101110110111100111CCCCCC0QQQQQ. */ +{ "vmac2h", 0x2EDE7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vmac2h a,limm,u6 00101110010111100111uuuuuuAAAAAA. */ +{ "vmac2h", 0x2E5E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmac2h 0,limm,u6 00101110010111100111uuuuuu111110. */ +{ "vmac2h", 0x2E5E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmac2h<.cc> 0,limm,u6 00101110110111100111uuuuuu1QQQQQ. */ +{ "vmac2h", 0x2EDE7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmac2h 0,limm,s12 00101110100111100111ssssssSSSSSS. */ +{ "vmac2h", 0x2E9E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmac2h a,limm,limm 00101110000111100111111110AAAAAA. */ +{ "vmac2h", 0x2E1E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmac2h 0,limm,limm 00101110000111100111111110111110. */ +{ "vmac2h", 0x2E1E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmac2h<.cc> 0,limm,limm 001011101101111001111111100QQQQQ. */ +{ "vmac2h", 0x2EDE7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vmac2hf a,b,c 00101bbb000111101BBBCCCCCCAAAAAA. */ +{ "vmac2hf", 0x281E8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmac2hf 0,b,c 00101bbb000111101BBBCCCCCC111110. */ +{ "vmac2hf", 0x281E803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmac2hf<.cc> b,b,c 00101bbb110111101BBBCCCCCC0QQQQQ. */ +{ "vmac2hf", 0x28DE8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vmac2hf a,b,u6 00101bbb010111101BBBuuuuuuAAAAAA. */ +{ "vmac2hf", 0x285E8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmac2hf 0,b,u6 00101bbb010111101BBBuuuuuu111110. */ +{ "vmac2hf", 0x285E803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmac2hf<.cc> b,b,u6 00101bbb110111101BBBuuuuuu1QQQQQ. */ +{ "vmac2hf", 0x28DE8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmac2hf b,b,s12 00101bbb100111101BBBssssssSSSSSS. */ +{ "vmac2hf", 0x289E8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmac2hf a,limm,c 00101110000111101111CCCCCCAAAAAA. */ +{ "vmac2hf", 0x2E1EF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmac2hf a,b,limm 00101bbb000111101BBB111110AAAAAA. */ +{ "vmac2hf", 0x281E8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmac2hf 0,limm,c 00101110000111101111CCCCCC111110. */ +{ "vmac2hf", 0x2E1EF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmac2hf 0,b,limm 00101bbb000111101BBB111110111110. */ +{ "vmac2hf", 0x281E8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmac2hf<.cc> b,b,limm 00101bbb110111101BBB1111100QQQQQ. */ +{ "vmac2hf", 0x28DE8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vmac2hf<.cc> 0,limm,c 00101110110111101111CCCCCC0QQQQQ. */ +{ "vmac2hf", 0x2EDEF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vmac2hf a,limm,u6 00101110010111101111uuuuuuAAAAAA. */ +{ "vmac2hf", 0x2E5EF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmac2hf 0,limm,u6 00101110010111101111uuuuuu111110. */ +{ "vmac2hf", 0x2E5EF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmac2hf<.cc> 0,limm,u6 00101110110111101111uuuuuu1QQQQQ. */ +{ "vmac2hf", 0x2EDEF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmac2hf 0,limm,s12 00101110100111101111ssssssSSSSSS. */ +{ "vmac2hf", 0x2E9EF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmac2hf a,limm,limm 00101110000111101111111110AAAAAA. */ +{ "vmac2hf", 0x2E1EFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmac2hf 0,limm,limm 00101110000111101111111110111110. */ +{ "vmac2hf", 0x2E1EFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmac2hf<.cc> 0,limm,limm 001011101101111011111111100QQQQQ. */ +{ "vmac2hf", 0x2EDEFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vmac2hfr a,b,c 00101bbb000111111BBBCCCCCCAAAAAA. */ +{ "vmac2hfr", 0x281F8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmac2hfr 0,b,c 00101bbb000111111BBBCCCCCC111110. */ +{ "vmac2hfr", 0x281F803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmac2hfr<.cc> b,b,c 00101bbb110111111BBBCCCCCC0QQQQQ. */ +{ "vmac2hfr", 0x28DF8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vmac2hfr a,b,u6 00101bbb010111111BBBuuuuuuAAAAAA. */ +{ "vmac2hfr", 0x285F8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmac2hfr 0,b,u6 00101bbb010111111BBBuuuuuu111110. */ +{ "vmac2hfr", 0x285F803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmac2hfr<.cc> b,b,u6 00101bbb110111111BBBuuuuuu1QQQQQ. */ +{ "vmac2hfr", 0x28DF8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmac2hfr b,b,s12 00101bbb100111111BBBssssssSSSSSS. */ +{ "vmac2hfr", 0x289F8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmac2hfr a,limm,c 00101110000111111111CCCCCCAAAAAA. */ +{ "vmac2hfr", 0x2E1FF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmac2hfr a,b,limm 00101bbb000111111BBB111110AAAAAA. */ +{ "vmac2hfr", 0x281F8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmac2hfr 0,limm,c 00101110000111111111CCCCCC111110. */ +{ "vmac2hfr", 0x2E1FF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmac2hfr 0,b,limm 00101bbb000111111BBB111110111110. */ +{ "vmac2hfr", 0x281F8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmac2hfr<.cc> b,b,limm 00101bbb110111111BBB1111100QQQQQ. */ +{ "vmac2hfr", 0x28DF8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vmac2hfr<.cc> 0,limm,c 00101110110111111111CCCCCC0QQQQQ. */ +{ "vmac2hfr", 0x2EDFF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vmac2hfr a,limm,u6 00101110010111111111uuuuuuAAAAAA. */ +{ "vmac2hfr", 0x2E5FF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmac2hfr 0,limm,u6 00101110010111111111uuuuuu111110. */ +{ "vmac2hfr", 0x2E5FF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmac2hfr<.cc> 0,limm,u6 00101110110111111111uuuuuu1QQQQQ. */ +{ "vmac2hfr", 0x2EDFF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmac2hfr 0,limm,s12 00101110100111111111ssssssSSSSSS. */ +{ "vmac2hfr", 0x2E9FF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmac2hfr a,limm,limm 00101110000111111111111110AAAAAA. */ +{ "vmac2hfr", 0x2E1FFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmac2hfr 0,limm,limm 00101110000111111111111110111110. */ +{ "vmac2hfr", 0x2E1FFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmac2hfr<.cc> 0,limm,limm 001011101101111111111111100QQQQQ. */ +{ "vmac2hfr", 0x2EDFFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vmac2hnfr a,b,c 00110bbb000100010BBBCCCCCCAAAAAA. */ +{ "vmac2hnfr", 0x30110000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmac2hnfr 0,b,c 00110bbb000100010BBBCCCCCC111110. */ +{ "vmac2hnfr", 0x3011003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmac2hnfr<.cc> b,b,c 00110bbb110100010BBBCCCCCC0QQQQQ. */ +{ "vmac2hnfr", 0x30D10000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vmac2hnfr a,b,u6 00110bbb010100010BBBuuuuuuAAAAAA. */ +{ "vmac2hnfr", 0x30510000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmac2hnfr 0,b,u6 00110bbb010100010BBBuuuuuu111110. */ +{ "vmac2hnfr", 0x3051003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmac2hnfr<.cc> b,b,u6 00110bbb110100010BBBuuuuuu1QQQQQ. */ +{ "vmac2hnfr", 0x30D10020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmac2hnfr b,b,s12 00110bbb100100010BBBssssssSSSSSS. */ +{ "vmac2hnfr", 0x30910000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmac2hnfr a,limm,c 00110110000100010111CCCCCCAAAAAA. */ +{ "vmac2hnfr", 0x36117000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmac2hnfr a,b,limm 00110bbb000100010BBB111110AAAAAA. */ +{ "vmac2hnfr", 0x30110F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmac2hnfr 0,limm,c 00110110000100010111CCCCCC111110. */ +{ "vmac2hnfr", 0x3611703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmac2hnfr 0,b,limm 00110bbb000100010BBB111110111110. */ +{ "vmac2hnfr", 0x30110FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmac2hnfr<.cc> b,b,limm 00110bbb110100010BBB1111100QQQQQ. */ +{ "vmac2hnfr", 0x30D10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vmac2hnfr<.cc> 0,limm,c 00110110110100010111CCCCCC0QQQQQ. */ +{ "vmac2hnfr", 0x36D17000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vmac2hnfr a,limm,u6 00110110010100010111uuuuuuAAAAAA. */ +{ "vmac2hnfr", 0x36517000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmac2hnfr 0,limm,u6 00110110010100010111uuuuuu111110. */ +{ "vmac2hnfr", 0x3651703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmac2hnfr<.cc> 0,limm,u6 00110110110100010111uuuuuu1QQQQQ. */ +{ "vmac2hnfr", 0x36D17020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmac2hnfr 0,limm,s12 00110110100100010111ssssssSSSSSS. */ +{ "vmac2hnfr", 0x36917000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmac2hnfr a,limm,limm 00110110000100010111111110AAAAAA. */ +{ "vmac2hnfr", 0x36117F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmac2hnfr 0,limm,limm 00110110000100010111111110111110. */ +{ "vmac2hnfr", 0x36117FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmac2hnfr<.cc> 0,limm,limm 001101101101000101111111100QQQQQ. */ +{ "vmac2hnfr", 0x36D17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vmac2hu a,b,c 00101bbb000111110BBBCCCCCCAAAAAA. */ +{ "vmac2hu", 0x281F0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmac2hu 0,b,c 00101bbb000111110BBBCCCCCC111110. */ +{ "vmac2hu", 0x281F003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmac2hu<.cc> b,b,c 00101bbb110111110BBBCCCCCC0QQQQQ. */ +{ "vmac2hu", 0x28DF0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vmac2hu a,b,u6 00101bbb010111110BBBuuuuuuAAAAAA. */ +{ "vmac2hu", 0x285F0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmac2hu 0,b,u6 00101bbb010111110BBBuuuuuu111110. */ +{ "vmac2hu", 0x285F003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmac2hu<.cc> b,b,u6 00101bbb110111110BBBuuuuuu1QQQQQ. */ +{ "vmac2hu", 0x28DF0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmac2hu b,b,s12 00101bbb100111110BBBssssssSSSSSS. */ +{ "vmac2hu", 0x289F0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmac2hu a,limm,c 00101110000111110111CCCCCCAAAAAA. */ +{ "vmac2hu", 0x2E1F7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmac2hu a,b,limm 00101bbb000111110BBB111110AAAAAA. */ +{ "vmac2hu", 0x281F0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmac2hu 0,limm,c 00101110000111110111CCCCCC111110. */ +{ "vmac2hu", 0x2E1F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmac2hu 0,b,limm 00101bbb000111110BBB111110111110. */ +{ "vmac2hu", 0x281F0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmac2hu<.cc> b,b,limm 00101bbb110111110BBB1111100QQQQQ. */ +{ "vmac2hu", 0x28DF0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vmac2hu<.cc> 0,limm,c 00101110110111110111CCCCCC0QQQQQ. */ +{ "vmac2hu", 0x2EDF7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vmac2hu a,limm,u6 00101110010111110111uuuuuuAAAAAA. */ +{ "vmac2hu", 0x2E5F7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmac2hu 0,limm,u6 00101110010111110111uuuuuu111110. */ +{ "vmac2hu", 0x2E5F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmac2hu<.cc> 0,limm,u6 00101110110111110111uuuuuu1QQQQQ. */ +{ "vmac2hu", 0x2EDF7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmac2hu 0,limm,s12 00101110100111110111ssssssSSSSSS. */ +{ "vmac2hu", 0x2E9F7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmac2hu a,limm,limm 00101110000111110111111110AAAAAA. */ +{ "vmac2hu", 0x2E1F7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmac2hu 0,limm,limm 00101110000111110111111110111110. */ +{ "vmac2hu", 0x2E1F7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmac2hu<.cc> 0,limm,limm 001011101101111101111111100QQQQQ. */ +{ "vmac2hu", 0x2EDF7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vmax2h a,b,c 00101bbb001001001BBBCCCCCCAAAAAA. */ +{ "vmax2h", 0x28248000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmax2h 0,b,c 00101bbb001001001BBBCCCCCC111110. */ +{ "vmax2h", 0x2824803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmax2h<.cc> b,b,c 00101bbb111001001BBBCCCCCC0QQQQQ. */ +{ "vmax2h", 0x28E48000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vmax2h a,b,u6 00101bbb011001001BBBuuuuuuAAAAAA. */ +{ "vmax2h", 0x28648000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmax2h 0,b,u6 00101bbb011001001BBBuuuuuu111110. */ +{ "vmax2h", 0x2864803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmax2h<.cc> b,b,u6 00101bbb111001001BBBuuuuuu1QQQQQ. */ +{ "vmax2h", 0x28E48020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmax2h b,b,s12 00101bbb101001001BBBssssssSSSSSS. */ +{ "vmax2h", 0x28A48000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmax2h a,limm,c 00101110001001001111CCCCCCAAAAAA. */ +{ "vmax2h", 0x2E24F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmax2h a,b,limm 00101bbb001001001BBB111110AAAAAA. */ +{ "vmax2h", 0x28248F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmax2h 0,limm,c 00101110011001001111CCCCCC111110. */ +{ "vmax2h", 0x2E64F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmax2h 0,b,limm 00101bbb001001001BBB111110111110. */ +{ "vmax2h", 0x28248FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmax2h<.cc> b,b,limm 00101bbb111001001BBB1111100QQQQQ. */ +{ "vmax2h", 0x28E48F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vmax2h<.cc> 0,limm,c 00101110111001001111CCCCCC0QQQQQ. */ +{ "vmax2h", 0x2EE4F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vmax2h a,limm,u6 00101110011001001111uuuuuuAAAAAA. */ +{ "vmax2h", 0x2E64F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmax2h 0,limm,u6 00101110011001001111uuuuuu111110. */ +{ "vmax2h", 0x2E64F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmax2h<.cc> 0,limm,u6 00101110111001001111uuuuuu1QQQQQ. */ +{ "vmax2h", 0x2EE4F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmax2h 0,limm,s12 00101110101001001111ssssssSSSSSS. */ +{ "vmax2h", 0x2EA4F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmax2h a,limm,limm 00101110001001001111111110AAAAAA. */ +{ "vmax2h", 0x2E24FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmax2h 0,limm,limm 00101110001001001111111110111110. */ +{ "vmax2h", 0x2E24FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmax2h<.cc> 0,limm,limm 001011101110010011111111100QQQQQ. */ +{ "vmax2h", 0x2EE4FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vmin2h a,b,c 00101bbb001001011BBBCCCCCCAAAAAA. */ +{ "vmin2h", 0x28258000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmin2h 0,b,c 00101bbb001001011BBBCCCCCC111110. */ +{ "vmin2h", 0x2825803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmin2h<.cc> b,b,c 00101bbb111001011BBBCCCCCC0QQQQQ. */ +{ "vmin2h", 0x28E58000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vmin2h a,b,u6 00101bbb011001011BBBuuuuuuAAAAAA. */ +{ "vmin2h", 0x28658000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmin2h 0,b,u6 00101bbb011001011BBBuuuuuu111110. */ +{ "vmin2h", 0x2865803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmin2h<.cc> b,b,u6 00101bbb111001011BBBuuuuuu1QQQQQ. */ +{ "vmin2h", 0x28E58020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmin2h b,b,s12 00101bbb101001011BBBssssssSSSSSS. */ +{ "vmin2h", 0x28A58000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmin2h a,limm,c 00101110001001011111CCCCCCAAAAAA. */ +{ "vmin2h", 0x2E25F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmin2h a,b,limm 00101bbb001001011BBB111110AAAAAA. */ +{ "vmin2h", 0x28258F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmin2h 0,limm,c 00101110011001011111CCCCCC111110. */ +{ "vmin2h", 0x2E65F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmin2h 0,b,limm 00101bbb001001011BBB111110111110. */ +{ "vmin2h", 0x28258FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmin2h<.cc> b,b,limm 00101bbb111001011BBB1111100QQQQQ. */ +{ "vmin2h", 0x28E58F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vmin2h<.cc> 0,limm,c 00101110111001011111CCCCCC0QQQQQ. */ +{ "vmin2h", 0x2EE5F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vmin2h a,limm,u6 00101110011001011111uuuuuuAAAAAA. */ +{ "vmin2h", 0x2E65F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmin2h 0,limm,u6 00101110011001011111uuuuuu111110. */ +{ "vmin2h", 0x2E65F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmin2h<.cc> 0,limm,u6 00101110111001011111uuuuuu1QQQQQ. */ +{ "vmin2h", 0x2EE5F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmin2h 0,limm,s12 00101110101001011111ssssssSSSSSS. */ +{ "vmin2h", 0x2EA5F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmin2h a,limm,limm 00101110001001011111111110AAAAAA. */ +{ "vmin2h", 0x2E25FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmin2h 0,limm,limm 00101110001001011111111110111110. */ +{ "vmin2h", 0x2E25FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmin2h<.cc> 0,limm,limm 001011101110010111111111100QQQQQ. */ +{ "vmin2h", 0x2EE5FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vmpy2h a,b,c 00101bbb000111000BBBCCCCCCAAAAAA. */ +{ "vmpy2h", 0x281C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmpy2h 0,b,c 00101bbb000111000BBBCCCCCC111110. */ +{ "vmpy2h", 0x281C003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmpy2h<.cc> b,b,c 00101bbb110111000BBBCCCCCC0QQQQQ. */ +{ "vmpy2h", 0x28DC0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vmpy2h a,b,c 00101bbb000111000BBBCCCCCCAAAAAA. */ +{ "vmpy2h", 0x281C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmpy2h 0,b,c 00101bbb000111000BBBCCCCCC111110. */ +{ "vmpy2h", 0x281C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmpy2h<.cc> b,b,c 00101bbb110111000BBBCCCCCC0QQQQQ. */ +{ "vmpy2h", 0x28DC0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vmpy2h a,b,u6 00101bbb010111000BBBuuuuuuAAAAAA. */ +{ "vmpy2h", 0x285C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2h 0,b,u6 00101bbb010111000BBBuuuuuu111110. */ +{ "vmpy2h", 0x285C003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2h<.cc> b,b,u6 00101bbb110111000BBBuuuuuu1QQQQQ. */ +{ "vmpy2h", 0x28DC0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmpy2h a,b,u6 00101bbb010111000BBBuuuuuuAAAAAA. */ +{ "vmpy2h", 0x285C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2h 0,b,u6 00101bbb010111000BBBuuuuuu111110. */ +{ "vmpy2h", 0x285C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2h<.cc> b,b,u6 00101bbb110111000BBBuuuuuu1QQQQQ. */ +{ "vmpy2h", 0x28DC0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmpy2h b,b,s12 00101bbb100111000BBBssssssSSSSSS. */ +{ "vmpy2h", 0x289C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmpy2h b,b,s12 00101bbb100111000BBBssssssSSSSSS. */ +{ "vmpy2h", 0x289C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmpy2h a,limm,c 00101110000111000111CCCCCCAAAAAA. */ +{ "vmpy2h", 0x2E1C7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmpy2h a,b,limm 00101bbb000111000BBB111110AAAAAA. */ +{ "vmpy2h", 0x281C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmpy2h 0,limm,c 00101110000111000111CCCCCC111110. */ +{ "vmpy2h", 0x2E1C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmpy2h 0,b,limm 00101bbb000111000BBB111110111110. */ +{ "vmpy2h", 0x281C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmpy2h<.cc> b,b,limm 00101bbb110111000BBB1111100QQQQQ. */ +{ "vmpy2h", 0x28DC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vmpy2h<.cc> 0,limm,c 00101110110111000111CCCCCC0QQQQQ. */ +{ "vmpy2h", 0x2EDC7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vmpy2h a,limm,c 00101110000111000111CCCCCCAAAAAA. */ +{ "vmpy2h", 0x2E1C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmpy2h a,b,limm 00101bbb000111000BBB111110AAAAAA. */ +{ "vmpy2h", 0x281C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmpy2h 0,limm,c 00101110000111000111CCCCCC111110. */ +{ "vmpy2h", 0x2E1C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmpy2h 0,b,limm 00101bbb000111000BBB111110111110. */ +{ "vmpy2h", 0x281C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmpy2h<.cc> b,b,limm 00101bbb110111000BBB1111100QQQQQ. */ +{ "vmpy2h", 0x28DC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vmpy2h<.cc> 0,limm,c 00101110110111000111CCCCCC0QQQQQ. */ +{ "vmpy2h", 0x2EDC7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vmpy2h a,limm,u6 00101110010111000111uuuuuuAAAAAA. */ +{ "vmpy2h", 0x2E5C7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2h 0,limm,u6 00101110010111000111uuuuuu111110. */ +{ "vmpy2h", 0x2E5C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2h<.cc> 0,limm,u6 00101110110111000111uuuuuu1QQQQQ. */ +{ "vmpy2h", 0x2EDC7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmpy2h a,limm,u6 00101110010111000111uuuuuuAAAAAA. */ +{ "vmpy2h", 0x2E5C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2h 0,limm,u6 00101110010111000111uuuuuu111110. */ +{ "vmpy2h", 0x2E5C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2h<.cc> 0,limm,u6 00101110110111000111uuuuuu1QQQQQ. */ +{ "vmpy2h", 0x2EDC7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmpy2h 0,limm,s12 00101110100111000111ssssssSSSSSS. */ +{ "vmpy2h", 0x2E9C7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmpy2h 0,limm,s12 00101110100111000111ssssssSSSSSS. */ +{ "vmpy2h", 0x2E9C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmpy2h a,limm,limm 00101110000111000111111110AAAAAA. */ +{ "vmpy2h", 0x2E1C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmpy2h 0,limm,limm 00101110000111000111111110111110. */ +{ "vmpy2h", 0x2E1C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmpy2h<.cc> 0,limm,limm 001011101101110001111111100QQQQQ. */ +{ "vmpy2h", 0x2EDC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vmpy2h a,limm,limm 00101110000111000111111110AAAAAA. */ +{ "vmpy2h", 0x2E1C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmpy2h 0,limm,limm 00101110000111000111111110111110. */ +{ "vmpy2h", 0x2E1C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmpy2h<.cc> 0,limm,limm 001011101101110001111111100QQQQQ. */ +{ "vmpy2h", 0x2EDC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vmpy2hf a,b,c 00101bbb000111001BBBCCCCCCAAAAAA. */ +{ "vmpy2hf", 0x281C8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmpy2hf 0,b,c 00101bbb000111001BBBCCCCCC111110. */ +{ "vmpy2hf", 0x281C803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmpy2hf<.cc> b,b,c 00101bbb110111001BBBCCCCCC0QQQQQ. */ +{ "vmpy2hf", 0x28DC8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vmpy2hf a,b,u6 00101bbb010111001BBBuuuuuuAAAAAA. */ +{ "vmpy2hf", 0x285C8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2hf 0,b,u6 00101bbb010111001BBBuuuuuu111110. */ +{ "vmpy2hf", 0x285C803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2hf<.cc> b,b,u6 00101bbb110111001BBBuuuuuu1QQQQQ. */ +{ "vmpy2hf", 0x28DC8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmpy2hf b,b,s12 00101bbb100111001BBBssssssSSSSSS. */ +{ "vmpy2hf", 0x289C8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmpy2hf a,limm,c 00101110000111001111CCCCCCAAAAAA. */ +{ "vmpy2hf", 0x2E1CF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmpy2hf a,b,limm 00101bbb000111001BBB111110AAAAAA. */ +{ "vmpy2hf", 0x281C8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmpy2hf 0,limm,c 00101110000111001111CCCCCC111110. */ +{ "vmpy2hf", 0x2E1CF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmpy2hf 0,b,limm 00101bbb000111001BBB111110111110. */ +{ "vmpy2hf", 0x281C8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmpy2hf<.cc> b,b,limm 00101bbb110111001BBB1111100QQQQQ. */ +{ "vmpy2hf", 0x28DC8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vmpy2hf<.cc> 0,limm,c 00101110110111001111CCCCCC0QQQQQ. */ +{ "vmpy2hf", 0x2EDCF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vmpy2hf a,limm,u6 00101110010111001111uuuuuuAAAAAA. */ +{ "vmpy2hf", 0x2E5CF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2hf 0,limm,u6 00101110010111001111uuuuuu111110. */ +{ "vmpy2hf", 0x2E5CF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2hf<.cc> 0,limm,u6 00101110110111001111uuuuuu1QQQQQ. */ +{ "vmpy2hf", 0x2EDCF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmpy2hf 0,limm,s12 00101110100111001111ssssssSSSSSS. */ +{ "vmpy2hf", 0x2E9CF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmpy2hf a,limm,limm 00101110000111001111111110AAAAAA. */ +{ "vmpy2hf", 0x2E1CFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmpy2hf 0,limm,limm 00101110000111001111111110111110. */ +{ "vmpy2hf", 0x2E1CFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmpy2hf<.cc> 0,limm,limm 001011101101110011111111100QQQQQ. */ +{ "vmpy2hf", 0x2EDCFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vmpy2hfr a,b,c 00101bbb000111011BBBCCCCCCAAAAAA. */ +{ "vmpy2hfr", 0x281D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmpy2hfr 0,b,c 00101bbb000111011BBBCCCCCC111110. */ +{ "vmpy2hfr", 0x281D803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmpy2hfr<.cc> b,b,c 00101bbb110111011BBBCCCCCC0QQQQQ. */ +{ "vmpy2hfr", 0x28DD8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vmpy2hfr a,b,u6 00101bbb010111011BBBuuuuuuAAAAAA. */ +{ "vmpy2hfr", 0x285D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2hfr 0,b,u6 00101bbb010111011BBBuuuuuu111110. */ +{ "vmpy2hfr", 0x285D803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2hfr<.cc> b,b,u6 00101bbb110111011BBBuuuuuu1QQQQQ. */ +{ "vmpy2hfr", 0x28DD8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmpy2hfr b,b,s12 00101bbb100111011BBBssssssSSSSSS. */ +{ "vmpy2hfr", 0x289D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmpy2hfr a,limm,c 00101110000111011111CCCCCCAAAAAA. */ +{ "vmpy2hfr", 0x2E1DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmpy2hfr a,b,limm 00101bbb000111011BBB111110AAAAAA. */ +{ "vmpy2hfr", 0x281D8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmpy2hfr 0,limm,c 00101110000111011111CCCCCC111110. */ +{ "vmpy2hfr", 0x2E1DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmpy2hfr 0,b,limm 00101bbb000111011BBB111110111110. */ +{ "vmpy2hfr", 0x281D8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmpy2hfr<.cc> b,b,limm 00101bbb110111011BBB1111100QQQQQ. */ +{ "vmpy2hfr", 0x28DD8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vmpy2hfr<.cc> 0,limm,c 00101110110111011111CCCCCC0QQQQQ. */ +{ "vmpy2hfr", 0x2EDDF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vmpy2hfr a,limm,u6 00101110010111011111uuuuuuAAAAAA. */ +{ "vmpy2hfr", 0x2E5DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2hfr 0,limm,u6 00101110010111011111uuuuuu111110. */ +{ "vmpy2hfr", 0x2E5DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2hfr<.cc> 0,limm,u6 00101110110111011111uuuuuu1QQQQQ. */ +{ "vmpy2hfr", 0x2EDDF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmpy2hfr 0,limm,s12 00101110100111011111ssssssSSSSSS. */ +{ "vmpy2hfr", 0x2E9DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmpy2hfr a,limm,limm 00101110000111011111111110AAAAAA. */ +{ "vmpy2hfr", 0x2E1DFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmpy2hfr 0,limm,limm 00101110000111011111111110111110. */ +{ "vmpy2hfr", 0x2E1DFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmpy2hfr<.cc> 0,limm,limm 001011101101110111111111100QQQQQ. */ +{ "vmpy2hfr", 0x2EDDFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vmpy2hu a,b,c 00101bbb000111010BBBCCCCCCAAAAAA. */ +{ "vmpy2hu", 0x281D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmpy2hu 0,b,c 00101bbb000111010BBBCCCCCC111110. */ +{ "vmpy2hu", 0x281D003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmpy2hu<.cc> b,b,c 00101bbb110111010BBBCCCCCC0QQQQQ. */ +{ "vmpy2hu", 0x28DD0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vmpy2hu a,b,c 00101bbb000111010BBBCCCCCCAAAAAA. */ +{ "vmpy2hu", 0x281D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmpy2hu 0,b,c 00101bbb000111010BBBCCCCCC111110. */ +{ "vmpy2hu", 0x281D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmpy2hu<.cc> b,b,c 00101bbb110111010BBBCCCCCC0QQQQQ. */ +{ "vmpy2hu", 0x28DD0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vmpy2hu a,b,u6 00101bbb010111010BBBuuuuuuAAAAAA. */ +{ "vmpy2hu", 0x285D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2hu 0,b,u6 00101bbb010111010BBBuuuuuu111110. */ +{ "vmpy2hu", 0x285D003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2hu<.cc> b,b,u6 00101bbb110111010BBBuuuuuu1QQQQQ. */ +{ "vmpy2hu", 0x28DD0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmpy2hu a,b,u6 00101bbb010111010BBBuuuuuuAAAAAA. */ +{ "vmpy2hu", 0x285D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2hu 0,b,u6 00101bbb010111010BBBuuuuuu111110. */ +{ "vmpy2hu", 0x285D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2hu<.cc> b,b,u6 00101bbb110111010BBBuuuuuu1QQQQQ. */ +{ "vmpy2hu", 0x28DD0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmpy2hu b,b,s12 00101bbb100111010BBBssssssSSSSSS. */ +{ "vmpy2hu", 0x289D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmpy2hu b,b,s12 00101bbb100111010BBBssssssSSSSSS. */ +{ "vmpy2hu", 0x289D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmpy2hu a,limm,c 00101110000111010111CCCCCCAAAAAA. */ +{ "vmpy2hu", 0x2E1D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmpy2hu a,b,limm 00101bbb000111010BBB111110AAAAAA. */ +{ "vmpy2hu", 0x281D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmpy2hu 0,limm,c 00101110000111010111CCCCCC111110. */ +{ "vmpy2hu", 0x2E1D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmpy2hu 0,b,limm 00101bbb000111010BBB111110111110. */ +{ "vmpy2hu", 0x281D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmpy2hu<.cc> b,b,limm 00101bbb110111010BBB1111100QQQQQ. */ +{ "vmpy2hu", 0x28DD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vmpy2hu<.cc> 0,limm,c 00101110110111010111CCCCCC0QQQQQ. */ +{ "vmpy2hu", 0x2EDD7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vmpy2hu a,limm,c 00101110000111010111CCCCCCAAAAAA. */ +{ "vmpy2hu", 0x2E1D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmpy2hu a,b,limm 00101bbb000111010BBB111110AAAAAA. */ +{ "vmpy2hu", 0x281D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmpy2hu 0,limm,c 00101110000111010111CCCCCC111110. */ +{ "vmpy2hu", 0x2E1D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmpy2hu 0,b,limm 00101bbb000111010BBB111110111110. */ +{ "vmpy2hu", 0x281D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmpy2hu<.cc> b,b,limm 00101bbb110111010BBB1111100QQQQQ. */ +{ "vmpy2hu", 0x28DD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vmpy2hu<.cc> 0,limm,c 00101110110111010111CCCCCC0QQQQQ. */ +{ "vmpy2hu", 0x2EDD7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vmpy2hu a,limm,u6 00101110010111010111uuuuuuAAAAAA. */ +{ "vmpy2hu", 0x2E5D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2hu 0,limm,u6 00101110010111010111uuuuuu111110. */ +{ "vmpy2hu", 0x2E5D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2hu<.cc> 0,limm,u6 00101110110111010111uuuuuu1QQQQQ. */ +{ "vmpy2hu", 0x2EDD7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmpy2hu a,limm,u6 00101110010111010111uuuuuuAAAAAA. */ +{ "vmpy2hu", 0x2E5D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2hu 0,limm,u6 00101110010111010111uuuuuu111110. */ +{ "vmpy2hu", 0x2E5D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2hu<.cc> 0,limm,u6 00101110110111010111uuuuuu1QQQQQ. */ +{ "vmpy2hu", 0x2EDD7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmpy2hu 0,limm,s12 00101110100111010111ssssssSSSSSS. */ +{ "vmpy2hu", 0x2E9D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmpy2hu 0,limm,s12 00101110100111010111ssssssSSSSSS. */ +{ "vmpy2hu", 0x2E9D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmpy2hu a,limm,limm 00101110000111010111111110AAAAAA. */ +{ "vmpy2hu", 0x2E1D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmpy2hu 0,limm,limm 00101110000111010111111110111110. */ +{ "vmpy2hu", 0x2E1D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmpy2hu<.cc> 0,limm,limm 001011101101110101111111100QQQQQ. */ +{ "vmpy2hu", 0x2EDD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vmpy2hu a,limm,limm 00101110000111010111111110AAAAAA. */ +{ "vmpy2hu", 0x2E1D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmpy2hu 0,limm,limm 00101110000111010111111110111110. */ +{ "vmpy2hu", 0x2E1D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmpy2hu<.cc> 0,limm,limm 001011101101110101111111100QQQQQ. */ +{ "vmpy2hu", 0x2EDD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY8E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vmpy2hwf a,b,c 00101bbb001000000BBBCCCCCCAAAAAA. */ +{ "vmpy2hwf", 0x28200000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmpy2hwf 0,b,c 00101bbb001000000BBBCCCCCC111110. */ +{ "vmpy2hwf", 0x2820003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmpy2hwf<.cc> b,b,c 00101bbb111000000BBBCCCCCC0QQQQQ. */ +{ "vmpy2hwf", 0x28E00000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vmpy2hwf a,b,u6 00101bbb011000000BBBuuuuuuAAAAAA. */ +{ "vmpy2hwf", 0x28600000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2hwf 0,b,u6 00101bbb011000000BBBuuuuuu111110. */ +{ "vmpy2hwf", 0x2860003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2hwf<.cc> b,b,u6 00101bbb111000000BBBuuuuuu1QQQQQ. */ +{ "vmpy2hwf", 0x28E00020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmpy2hwf b,b,s12 00101bbb101000000BBBssssssSSSSSS. */ +{ "vmpy2hwf", 0x28A00000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmpy2hwf a,limm,c 00101110001000000111CCCCCCAAAAAA. */ +{ "vmpy2hwf", 0x2E207000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmpy2hwf a,b,limm 00101bbb001000000BBB111110AAAAAA. */ +{ "vmpy2hwf", 0x28200F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmpy2hwf 0,limm,c 00101110011000000111CCCCCC111110. */ +{ "vmpy2hwf", 0x2E60703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmpy2hwf 0,b,limm 00101bbb001000000BBB111110111110. */ +{ "vmpy2hwf", 0x28200FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmpy2hwf<.cc> b,b,limm 00101bbb111000000BBB1111100QQQQQ. */ +{ "vmpy2hwf", 0x28E00F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vmpy2hwf<.cc> 0,limm,c 00101110111000000111CCCCCC0QQQQQ. */ +{ "vmpy2hwf", 0x2EE07000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vmpy2hwf a,limm,u6 00101110011000000111uuuuuuAAAAAA. */ +{ "vmpy2hwf", 0x2E607000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2hwf 0,limm,u6 00101110011000000111uuuuuu111110. */ +{ "vmpy2hwf", 0x2E60703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmpy2hwf<.cc> 0,limm,u6 00101110111000000111uuuuuu1QQQQQ. */ +{ "vmpy2hwf", 0x2EE07020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmpy2hwf 0,limm,s12 00101110101000000111ssssssSSSSSS. */ +{ "vmpy2hwf", 0x2EA07000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmpy2hwf a,limm,limm 00101110001000000111111110AAAAAA. */ +{ "vmpy2hwf", 0x2E207F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmpy2hwf 0,limm,limm 00101110001000000111111110111110. */ +{ "vmpy2hwf", 0x2E207FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmpy2hwf<.cc> 0,limm,limm 001011101110000001111111100QQQQQ. */ +{ "vmpy2hwf", 0x2EE07F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vmsub2hf a,b,c 00110bbb000001000BBBCCCCCCAAAAAA. */ +{ "vmsub2hf", 0x30040000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmsub2hf 0,b,c 00110bbb000001000BBBCCCCCC111110. */ +{ "vmsub2hf", 0x3004003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmsub2hf<.cc> b,b,c 00110bbb110001000BBBCCCCCC0QQQQQ. */ +{ "vmsub2hf", 0x30C40000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vmsub2hf a,b,u6 00110bbb010001000BBBuuuuuuAAAAAA. */ +{ "vmsub2hf", 0x30440000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmsub2hf 0,b,u6 00110bbb010001000BBBuuuuuu111110. */ +{ "vmsub2hf", 0x3044003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmsub2hf<.cc> b,b,u6 00110bbb110001000BBBuuuuuu1QQQQQ. */ +{ "vmsub2hf", 0x30C40020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmsub2hf b,b,s12 00110bbb100001000BBBssssssSSSSSS. */ +{ "vmsub2hf", 0x30840000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmsub2hf a,limm,c 00110110000001000111CCCCCCAAAAAA. */ +{ "vmsub2hf", 0x36047000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmsub2hf a,b,limm 00110bbb000001000BBB111110AAAAAA. */ +{ "vmsub2hf", 0x30040F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmsub2hf 0,limm,c 00110110000001000111CCCCCC111110. */ +{ "vmsub2hf", 0x3604703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmsub2hf 0,b,limm 00110bbb000001000BBB111110111110. */ +{ "vmsub2hf", 0x30040FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmsub2hf<.cc> b,b,limm 00110bbb110001000BBB1111100QQQQQ. */ +{ "vmsub2hf", 0x30C40F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vmsub2hf<.cc> 0,limm,c 00110110110001000111CCCCCC0QQQQQ. */ +{ "vmsub2hf", 0x36C47000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vmsub2hf a,limm,u6 00110110010001000111uuuuuuAAAAAA. */ +{ "vmsub2hf", 0x36447000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmsub2hf 0,limm,u6 00110110010001000111uuuuuu111110. */ +{ "vmsub2hf", 0x3644703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmsub2hf<.cc> 0,limm,u6 00110110110001000111uuuuuu1QQQQQ. */ +{ "vmsub2hf", 0x36C47020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmsub2hf 0,limm,s12 00110110100001000111ssssssSSSSSS. */ +{ "vmsub2hf", 0x36847000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmsub2hf a,limm,limm 00110110000001000111111110AAAAAA. */ +{ "vmsub2hf", 0x36047F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmsub2hf 0,limm,limm 00110110000001000111111110111110. */ +{ "vmsub2hf", 0x36047FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmsub2hf<.cc> 0,limm,limm 001101101100010001111111100QQQQQ. */ +{ "vmsub2hf", 0x36C47F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vmsub2hfr a,b,c 00110bbb000000110BBBCCCCCCAAAAAA. */ +{ "vmsub2hfr", 0x30030000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmsub2hfr 0,b,c 00110bbb000000110BBBCCCCCC111110. */ +{ "vmsub2hfr", 0x3003003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmsub2hfr<.cc> b,b,c 00110bbb110000110BBBCCCCCC0QQQQQ. */ +{ "vmsub2hfr", 0x30C30000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vmsub2hfr a,b,u6 00110bbb010000110BBBuuuuuuAAAAAA. */ +{ "vmsub2hfr", 0x30430000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmsub2hfr 0,b,u6 00110bbb010000110BBBuuuuuu111110. */ +{ "vmsub2hfr", 0x3043003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmsub2hfr<.cc> b,b,u6 00110bbb110000110BBBuuuuuu1QQQQQ. */ +{ "vmsub2hfr", 0x30C30020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmsub2hfr b,b,s12 00110bbb100000110BBBssssssSSSSSS. */ +{ "vmsub2hfr", 0x30830000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmsub2hfr a,limm,c 00110110000000110111CCCCCCAAAAAA. */ +{ "vmsub2hfr", 0x36037000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmsub2hfr a,b,limm 00110bbb000000110BBB111110AAAAAA. */ +{ "vmsub2hfr", 0x30030F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmsub2hfr 0,limm,c 00110110000000110111CCCCCC111110. */ +{ "vmsub2hfr", 0x3603703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmsub2hfr 0,b,limm 00110bbb000000110BBB111110111110. */ +{ "vmsub2hfr", 0x30030FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmsub2hfr<.cc> b,b,limm 00110bbb110000110BBB1111100QQQQQ. */ +{ "vmsub2hfr", 0x30C30F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vmsub2hfr<.cc> 0,limm,c 00110110110000110111CCCCCC0QQQQQ. */ +{ "vmsub2hfr", 0x36C37000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vmsub2hfr a,limm,u6 00110110010000110111uuuuuuAAAAAA. */ +{ "vmsub2hfr", 0x36437000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmsub2hfr 0,limm,u6 00110110010000110111uuuuuu111110. */ +{ "vmsub2hfr", 0x3643703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmsub2hfr<.cc> 0,limm,u6 00110110110000110111uuuuuu1QQQQQ. */ +{ "vmsub2hfr", 0x36C37020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmsub2hfr 0,limm,s12 00110110100000110111ssssssSSSSSS. */ +{ "vmsub2hfr", 0x36837000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmsub2hfr a,limm,limm 00110110000000110111111110AAAAAA. */ +{ "vmsub2hfr", 0x36037F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmsub2hfr 0,limm,limm 00110110000000110111111110111110. */ +{ "vmsub2hfr", 0x36037FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmsub2hfr<.cc> 0,limm,limm 001101101100001101111111100QQQQQ. */ +{ "vmsub2hfr", 0x36C37F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vmsub2hnfr a,b,c 00110bbb000100011BBBCCCCCCAAAAAA. */ +{ "vmsub2hnfr", 0x30118000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmsub2hnfr 0,b,c 00110bbb000100011BBBCCCCCC111110. */ +{ "vmsub2hnfr", 0x3011803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vmsub2hnfr<.cc> b,b,c 00110bbb110100011BBBCCCCCC0QQQQQ. */ +{ "vmsub2hnfr", 0x30D18000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vmsub2hnfr a,b,u6 00110bbb010100011BBBuuuuuuAAAAAA. */ +{ "vmsub2hnfr", 0x30518000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmsub2hnfr 0,b,u6 00110bbb010100011BBBuuuuuu111110. */ +{ "vmsub2hnfr", 0x3051803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmsub2hnfr<.cc> b,b,u6 00110bbb110100011BBBuuuuuu1QQQQQ. */ +{ "vmsub2hnfr", 0x30D18020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmsub2hnfr b,b,s12 00110bbb100100011BBBssssssSSSSSS. */ +{ "vmsub2hnfr", 0x30918000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmsub2hnfr a,limm,c 00110110000100011111CCCCCCAAAAAA. */ +{ "vmsub2hnfr", 0x3611F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmsub2hnfr a,b,limm 00110bbb000100011BBB111110AAAAAA. */ +{ "vmsub2hnfr", 0x30118F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmsub2hnfr 0,limm,c 00110110000100011111CCCCCC111110. */ +{ "vmsub2hnfr", 0x3611F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vmsub2hnfr 0,b,limm 00110bbb000100011BBB111110111110. */ +{ "vmsub2hnfr", 0x30118FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vmsub2hnfr<.cc> b,b,limm 00110bbb110100011BBB1111100QQQQQ. */ +{ "vmsub2hnfr", 0x30D18F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vmsub2hnfr<.cc> 0,limm,c 00110110110100011111CCCCCC0QQQQQ. */ +{ "vmsub2hnfr", 0x36D1F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vmsub2hnfr a,limm,u6 00110110010100011111uuuuuuAAAAAA. */ +{ "vmsub2hnfr", 0x3651F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmsub2hnfr 0,limm,u6 00110110010100011111uuuuuu111110. */ +{ "vmsub2hnfr", 0x3651F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vmsub2hnfr<.cc> 0,limm,u6 00110110110100011111uuuuuu1QQQQQ. */ +{ "vmsub2hnfr", 0x36D1F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vmsub2hnfr 0,limm,s12 00110110100100011111ssssssSSSSSS. */ +{ "vmsub2hnfr", 0x3691F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vmsub2hnfr a,limm,limm 00110110000100011111111110AAAAAA. */ +{ "vmsub2hnfr", 0x3611FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmsub2hnfr 0,limm,limm 00110110000100011111111110111110. */ +{ "vmsub2hnfr", 0x3611FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vmsub2hnfr<.cc> 0,limm,limm 001101101101000111111111100QQQQQ. */ +{ "vmsub2hnfr", 0x36D1FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vneg2h b,c 00101bbb001011110BBBCCCCCC101010. */ +{ "vneg2h", 0x282F002A, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, + +/* vneg2h 0,c 00101110001011110111CCCCCC101010. */ +{ "vneg2h", 0x2E2F702A, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, + +/* vneg2h b,u6 00101bbb011011110BBBuuuuuu101010. */ +{ "vneg2h", 0x286F002A, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, + +/* vneg2h 0,u6 00101110011011110111uuuuuu101010. */ +{ "vneg2h", 0x2E6F702A, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, + +/* vneg2h b,limm 00101bbb001011110BBB111110101010. */ +{ "vneg2h", 0x282F0FAA, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, + +/* vneg2h 0,limm 00101110001011110111111110101010. */ +{ "vneg2h", 0x2E2F7FAA, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, + +/* vnegs2h b,c 00101bbb001011110BBBCCCCCC101011. */ +{ "vnegs2h", 0x282F002B, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, + +/* vnegs2h 0,c 00101110001011110111CCCCCC101011. */ +{ "vnegs2h", 0x2E2F702B, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, + +/* vnegs2h b,u6 00101bbb011011110BBBuuuuuu101011. */ +{ "vnegs2h", 0x286F002B, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, + +/* vnegs2h 0,u6 00101110011011110111uuuuuu101011. */ +{ "vnegs2h", 0x2E6F702B, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, + +/* vnegs2h b,limm 00101bbb001011110BBB111110101011. */ +{ "vnegs2h", 0x282F0FAB, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, + +/* vnegs2h 0,limm 00101110001011110111111110101011. */ +{ "vnegs2h", 0x2E2F7FAB, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, + +/* vnorm2h b,c 00101bbb001011110BBBCCCCCC101100. */ +{ "vnorm2h", 0x282F002C, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, + +/* vnorm2h 0,c 00101110001011110111CCCCCC101100. */ +{ "vnorm2h", 0x2E2F702C, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, + +/* vnorm2h b,u6 00101bbb011011110BBBuuuuuu101100. */ +{ "vnorm2h", 0x286F002C, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, + +/* vnorm2h 0,u6 00101110011011110111uuuuuu101100. */ +{ "vnorm2h", 0x2E6F702C, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, + +/* vnorm2h b,limm 00101bbb001011110BBB111110101100. */ +{ "vnorm2h", 0x282F0FAC, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, + +/* vnorm2h 0,limm 00101110001011110111111110101100. */ +{ "vnorm2h", 0x2E2F7FAC, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, + +/* vpack2hbl b,c 00101bbb001011110BBBCCCCCC011100 */ +{ "vpack2hbl", 0x282F001C, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vpack2hbl 0,c 00101110001011110111CCCCCC011100 */ +{ "vpack2hbl", 0x2E2F701C, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, + +/* vpack2hbl 0,u6 00101110011011110111uuuuuu011100 */ +{ "vpack2hbl", 0x2E6F701C, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, + +/* vpack2hbl b,u6 00101bbb011011110BBBuuuuuu011100 */ +{ "vpack2hbl", 0x286F001C, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vpack2hbl 0,limm 00101110001011110111111110011100 */ +{ "vpack2hbl", 0x2E2F7F9C, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, + +/* vpack2hbl b,limm 00101bbb001011110BBB111110011100 */ +{ "vpack2hbl", 0x282F0F9C, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vpack2hblf b,c 00101bbb001011110BBBCCCCCC011110 */ +{ "vpack2hblf", 0x282F001E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vpack2hblf 0,c 00101110001011110111CCCCCC011110 */ +{ "vpack2hblf", 0x2E2F701E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, + +/* vpack2hblf 0,u6 00101110011011110111uuuuuu011110 */ +{ "vpack2hblf", 0x2E6F701E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, + +/* vpack2hblf b,u6 00101bbb011011110BBBuuuuuu011110 */ +{ "vpack2hblf", 0x286F001E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vpack2hblf b,limm 00101bbb001011110BBB111110011110 */ +{ "vpack2hblf", 0x282F0F9E, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vpack2hblf 0,limm 00101110001011110111111110011110 */ +{ "vpack2hblf", 0x2E2F7F9E, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, + +/* vpack2hbm b,c 00101bbb001011110BBBCCCCCC011101 */ +{ "vpack2hbm", 0x282F001D, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vpack2hbm 0,c 00101110001011110111CCCCCC011101 */ +{ "vpack2hbm", 0x2E2F701D, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, + +/* vpack2hbm b,u6 00101bbb011011110BBBuuuuuu011101 */ +{ "vpack2hbm", 0x286F001D, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vpack2hbm 0,u6 00101110011011110111uuuuuu011101 */ +{ "vpack2hbm", 0x2E6F701D, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, + +/* vpack2hbm 0,limm 00101110001011110111111110011101 */ +{ "vpack2hbm", 0x2E2F7F9D, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, + +/* vpack2hbm b,limm 00101bbb001011110BBB111110011101 */ +{ "vpack2hbm", 0x282F0F9D, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vpack2hbmf 0,c 00101110001011110111CCCCCC011111 */ +{ "vpack2hbmf", 0x2E2F701F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, + +/* vpack2hbmf b,c 00101bbb001011110BBBCCCCCC011111 */ +{ "vpack2hbmf", 0x282F001F, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vpack2hbmf b,u6 00101bbb011011110BBBuuuuuu011111 */ +{ "vpack2hbmf", 0x286F001F, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vpack2hbmf 0,u6 00101110011011110111uuuuuu011111 */ +{ "vpack2hbmf", 0x2E6F701F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, + +/* vpack2hbmf 0,limm 00101110001011110111111110011111 */ +{ "vpack2hbmf", 0x2E2F7F9F, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, + +/* vpack2hbmf b,limm 00101bbb001011110BBB111110011111 */ +{ "vpack2hbmf", 0x282F0F9F, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vpack2hl 0,b,c 00101bbb001010010BBBCCCCCC111110 */ +{ "vpack2hl", 0x2829003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vpack2hl a,b,c 00101bbb001010010BBBCCCCCCAAAAAA */ +{ "vpack2hl", 0x28290000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vpack2hl<.cc> b,b,c 00101bbb111010010BBBCCCCCC0QQQQQ */ +{ "vpack2hl", 0x28E90000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vpack2hl<.cc> b,b,u6 00101bbb111010010BBBuuuuuu1QQQQQ */ +{ "vpack2hl", 0x28E90020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vpack2hl a,b,u6 00101bbb011010010BBBuuuuuuAAAAAA */ +{ "vpack2hl", 0x28690000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vpack2hl 0,b,u6 00101bbb011010010BBBuuuuuu111110 */ +{ "vpack2hl", 0x2869003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vpack2hl b,b,s12 00101bbb101010010BBBssssssSSSSSS */ +{ "vpack2hl", 0x28A90000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vpack2hl<.cc> 0,limm,c 00101110111010010111CCCCCC0QQQQQ */ +{ "vpack2hl", 0x2EE97000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vpack2hl 0,limm,c 00101110011010010111CCCCCC111110 */ +{ "vpack2hl", 0x2E69703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vpack2hl a,b,limm 00101bbb001010010BBB111110AAAAAA */ +{ "vpack2hl", 0x28290F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vpack2hl a,limm,c 00101110001010010111CCCCCCAAAAAA */ +{ "vpack2hl", 0x2E297000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vpack2hl 0,b,limm 00101bbb001010010BBB111110111110 */ +{ "vpack2hl", 0x28290FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vpack2hl<.cc> b,b,limm 00101bbb111010010BBB1111100QQQQQ */ +{ "vpack2hl", 0x28E90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vpack2hl a,limm,u6 00101110011010010111uuuuuuAAAAAA */ +{ "vpack2hl", 0x2E697000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vpack2hl 0,limm,u6 00101110011010010111uuuuuu111110 */ +{ "vpack2hl", 0x2E69703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vpack2hl<.cc> 0,limm,u6 00101110111010010111uuuuuu1QQQQQ */ +{ "vpack2hl", 0x2EE97020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vpack2hl 0,limm,s12 00101110101010010111ssssssSSSSSS */ +{ "vpack2hl", 0x2EA97000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vpack2hl<.cc> 0,limm,limm 001011101110100101111111100QQQQQ */ +{ "vpack2hl", 0x2EE97F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vpack2hl a,limm,limm 00101110001010010111111110AAAAAA */ +{ "vpack2hl", 0x2E297F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vpack2hl 0,limm,limm 00101110001010010111111110111110 */ +{ "vpack2hl", 0x2E297FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vpack2hm a,b,c 00101bbb001010011BBBCCCCCCAAAAAA */ +{ "vpack2hm", 0x28298000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vpack2hm<.cc> b,b,c 00101bbb111010011BBBCCCCCC0QQQQQ */ +{ "vpack2hm", 0x28E98000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vpack2hm 0,b,c 00101bbb001010011BBBCCCCCC111110 */ +{ "vpack2hm", 0x2829803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vpack2hm a,b,u6 00101bbb011010011BBBuuuuuuAAAAAA */ +{ "vpack2hm", 0x28698000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vpack2hm 0,b,u6 00101bbb011010011BBBuuuuuu111110 */ +{ "vpack2hm", 0x2869803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vpack2hm<.cc> b,b,u6 00101bbb111010011BBBuuuuuu1QQQQQ */ +{ "vpack2hm", 0x28E98020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vpack2hm b,b,s12 00101bbb101010011BBBssssssSSSSSS */ +{ "vpack2hm", 0x28A98000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vpack2hm a,b,limm 00101bbb001010011BBB111110AAAAAA */ +{ "vpack2hm", 0x28298F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vpack2hm 0,b,limm 00101bbb001010011BBB111110111110 */ +{ "vpack2hm", 0x28298FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vpack2hm<.cc> 0,limm,c 00101110111010011111CCCCCC0QQQQQ */ +{ "vpack2hm", 0x2EE9F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vpack2hm<.cc> b,b,limm 00101bbb111010011BBB1111100QQQQQ */ +{ "vpack2hm", 0x28E98F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vpack2hm a,limm,c 00101110001010011111CCCCCCAAAAAA */ +{ "vpack2hm", 0x2E29F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vpack2hm 0,limm,c 00101110011010011111CCCCCC111110 */ +{ "vpack2hm", 0x2E69F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vpack2hm a,limm,u6 00101110011010011111uuuuuuAAAAAA */ +{ "vpack2hm", 0x2E69F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vpack2hm 0,limm,u6 00101110011010011111uuuuuu111110 */ +{ "vpack2hm", 0x2E69F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vpack2hm<.cc> 0,limm,u6 00101110111010011111uuuuuu1QQQQQ */ +{ "vpack2hm", 0x2EE9F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vpack2hm 0,limm,s12 00101110101010011111ssssssSSSSSS */ +{ "vpack2hm", 0x2EA9F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vpack2hm a,limm,limm 00101110001010011111111110AAAAAA */ +{ "vpack2hm", 0x2E29FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vpack2hm 0,limm,limm 00101110001010011111111110111110 */ +{ "vpack2hm", 0x2E29FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vpack2hm<.cc> 0,limm,limm 001011101110100111111111100QQQQQ */ +{ "vpack2hm", 0x2EE9FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vperm 0,b,c 00101bbb001011100BBBCCCCCC111110 */ +{ "vperm", 0x282E003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vperm a,b,c 00101bbb001011100BBBCCCCCCAAAAAA */ +{ "vperm", 0x282E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vperm<.cc> b,b,c 00101bbb111011100BBBCCCCCC0QQQQQ */ +{ "vperm", 0x28EE0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vperm 0,b,u6 00101bbb011011100BBBuuuuuu111110 */ +{ "vperm", 0x286E003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vperm<.cc> b,b,u6 00101bbb111011100BBBuuuuuu1QQQQQ */ +{ "vperm", 0x28EE0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vperm a,b,u6 00101bbb011011100BBBuuuuuuAAAAAA */ +{ "vperm", 0x286E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vperm b,b,s12 00101bbb101011100BBBssssssSSSSSS */ +{ "vperm", 0x28AE0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vperm a,b,limm 00101bbb001011100BBB111110AAAAAA */ +{ "vperm", 0x282E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vperm<.cc> b,b,limm 00101bbb111011100BBB1111100QQQQQ */ +{ "vperm", 0x28EE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vperm<.cc> 0,limm,c 00101110111011100111CCCCCC0QQQQQ */ +{ "vperm", 0x2EEE7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vperm a,limm,c 00101110001011100111CCCCCCAAAAAA */ +{ "vperm", 0x2E2E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vperm 0,b,limm 00101bbb001011100BBB111110111110 */ +{ "vperm", 0x282E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vperm 0,limm,c 00101110011011100111CCCCCC111110 */ +{ "vperm", 0x2E6E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vperm<.cc> 0,limm,u6 00101110111011100111uuuuuu1QQQQQ */ +{ "vperm", 0x2EEE7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vperm 0,limm,u6 00101110011011100111uuuuuu111110 */ +{ "vperm", 0x2E6E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vperm a,limm,u6 00101110011011100111uuuuuuAAAAAA */ +{ "vperm", 0x2E6E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vperm 0,limm,s12 00101110101011100111ssssssSSSSSS */ +{ "vperm", 0x2EAE7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vperm a,limm,limm 00101110001011100111111110AAAAAA */ +{ "vperm", 0x2E2E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vperm 0,limm,limm 00101110001011100111111110111110 */ +{ "vperm", 0x2E2E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vperm<.cc> 0,limm,limm 001011101110111001111111100QQQQQ */ +{ "vperm", 0x2EEE7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vrep2hl b,c 00101bbb001011110BBBCCCCCC100010. */ +{ "vrep2hl", 0x282F0022, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, + +/* vrep2hl 0,c 00101110001011110111CCCCCC100010. */ +{ "vrep2hl", 0x2E2F7022, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, + +/* vrep2hl b,u6 00101bbb011011110BBBuuuuuu100010. */ +{ "vrep2hl", 0x286F0022, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, + +/* vrep2hl 0,u6 00101110011011110111uuuuuu100010. */ +{ "vrep2hl", 0x2E6F7022, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, + +/* vrep2hl b,limm 00101bbb001011110BBB111110100010. */ +{ "vrep2hl", 0x282F0FA2, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, + +/* vrep2hl 0,limm 00101110001011110111111110100010. */ +{ "vrep2hl", 0x2E2F7FA2, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, + +/* vrep2hm b,c 00101bbb001011110BBBCCCCCC100011. */ +{ "vrep2hm", 0x282F0023, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, + +/* vrep2hm 0,c 00101110001011110111CCCCCC100011. */ +{ "vrep2hm", 0x2E2F7023, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, + +/* vrep2hm b,u6 00101bbb011011110BBBuuuuuu100011. */ +{ "vrep2hm", 0x286F0023, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, + +/* vrep2hm 0,u6 00101110011011110111uuuuuu100011. */ +{ "vrep2hm", 0x2E6F7023, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, + +/* vrep2hm b,limm 00101bbb001011110BBB111110100011. */ +{ "vrep2hm", 0x282F0FA3, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, + +/* vrep2hm 0,limm 00101110001011110111111110100011. */ +{ "vrep2hm", 0x2E2F7FA3, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, + +/* vsext2bhl b,c 00101bbb001011110BBBCCCCCC100110. */ +{ "vsext2bhl", 0x282F0026, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, + +/* vsext2bhl 0,c 00101110001011110111CCCCCC100110. */ +{ "vsext2bhl", 0x2E2F7026, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, + +/* vsext2bhl b,u6 00101bbb011011110BBBuuuuuu100110. */ +{ "vsext2bhl", 0x286F0026, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsext2bhl 0,u6 00101110011011110111uuuuuu100110. */ +{ "vsext2bhl", 0x2E6F7026, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsext2bhl b,limm 00101bbb001011110BBB111110100110. */ +{ "vsext2bhl", 0x282F0FA6, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, + +/* vsext2bhl 0,limm 00101110001011110111111110100110. */ +{ "vsext2bhl", 0x2E2F7FA6, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, + +/* vsext2bhm b,c 00101bbb001011110BBBCCCCCC100111. */ +{ "vsext2bhm", 0x282F0027, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RC }, { 0 }}, + +/* vsext2bhm 0,c 00101110001011110111CCCCCC100111. */ +{ "vsext2bhm", 0x2E2F7027, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RC }, { 0 }}, + +/* vsext2bhm b,u6 00101bbb011011110BBBuuuuuu100111. */ +{ "vsext2bhm", 0x286F0027, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsext2bhm 0,u6 00101110011011110111uuuuuu100111. */ +{ "vsext2bhm", 0x2E6F7027, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsext2bhm b,limm 00101bbb001011110BBB111110100111. */ +{ "vsext2bhm", 0x282F0FA7, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_LIMM }, { 0 }}, + +/* vsext2bhm 0,limm 00101110001011110111111110100111. */ +{ "vsext2bhm", 0x2E2F7FA7, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM }, { 0 }}, + +/* vsub2 a,b,c 00101bbb001111010BBBCCCCCCAAAAAA. */ +{ "vsub2", 0x283D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsub2 0,b,c 00101bbb001111010BBBCCCCCC111110. */ +{ "vsub2", 0x283D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsub2<.cc> b,b,c 00101bbb111111010BBBCCCCCC0QQQQQ. */ +{ "vsub2", 0x28FD0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vsub2 a,b,u6 00101bbb011111010BBBuuuuuuAAAAAA. */ +{ "vsub2", 0x287D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsub2 0,b,u6 00101bbb011111010BBBuuuuuu111110. */ +{ "vsub2", 0x287D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsub2<.cc> b,b,u6 00101bbb111111010BBBuuuuuu1QQQQQ. */ +{ "vsub2", 0x28FD0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsub2 b,b,s12 00101bbb101111010BBBssssssSSSSSS. */ +{ "vsub2", 0x28BD0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsub2 a,limm,c 00101110001111010111CCCCCCAAAAAA. */ +{ "vsub2", 0x2E3D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsub2 a,b,limm 00101bbb001111010BBB111110AAAAAA. */ +{ "vsub2", 0x283D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsub2 0,limm,c 00101110001111010111CCCCCC111110. */ +{ "vsub2", 0x2E3D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsub2 0,b,limm 00101bbb001111010BBB111110111110. */ +{ "vsub2", 0x283D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsub2<.cc> b,b,limm 00101bbb111111010BBB1111100QQQQQ. */ +{ "vsub2", 0x28FD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vsub2<.cc> 0,limm,c 00101110111111010111CCCCCC0QQQQQ. */ +{ "vsub2", 0x2EFD7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vsub2 a,limm,u6 00101110011111010111uuuuuuAAAAAA. */ +{ "vsub2", 0x2E7D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsub2 0,limm,u6 00101110011111010111uuuuuu111110. */ +{ "vsub2", 0x2E7D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsub2<.cc> 0,limm,u6 00101110111111010111uuuuuu1QQQQQ. */ +{ "vsub2", 0x2EFD7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsub2 0,limm,s12 00101110101111010111ssssssSSSSSS. */ +{ "vsub2", 0x2EBD7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsub2 a,limm,limm 00101110001111010111111110AAAAAA. */ +{ "vsub2", 0x2E3D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsub2 0,limm,limm 00101110001111010111111110111110. */ +{ "vsub2", 0x2E3D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsub2<.cc> 0,limm,limm 001011101111110101111111100QQQQQ. */ +{ "vsub2", 0x2EFD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vsub2h a,b,c 00101bbb000101010BBBCCCCCCAAAAAA. */ +{ "vsub2h", 0x28150000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsub2h 0,b,c 00101bbb000101010BBBCCCCCC111110. */ +{ "vsub2h", 0x2815003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsub2h<.cc> b,b,c 00101bbb110101010BBBCCCCCC0QQQQQ. */ +{ "vsub2h", 0x28D50000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vsub2h a,b,u6 00101bbb010101010BBBuuuuuuAAAAAA. */ +{ "vsub2h", 0x28550000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsub2h 0,b,u6 00101bbb010101010BBBuuuuuu111110. */ +{ "vsub2h", 0x2855003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsub2h<.cc> b,b,u6 00101bbb110101010BBBuuuuuu1QQQQQ. */ +{ "vsub2h", 0x28D50020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsub2h b,b,s12 00101bbb100101010BBBssssssSSSSSS. */ +{ "vsub2h", 0x28950000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsub2h a,limm,c 00101110000101010111CCCCCCAAAAAA. */ +{ "vsub2h", 0x2E157000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsub2h a,b,limm 00101bbb000101010BBB111110AAAAAA. */ +{ "vsub2h", 0x28150F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsub2h 0,limm,c 00101110000101010111CCCCCC111110. */ +{ "vsub2h", 0x2E15703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsub2h 0,b,limm 00101bbb000101010BBB111110111110. */ +{ "vsub2h", 0x28150FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsub2h<.cc> b,b,limm 00101bbb110101010BBB1111100QQQQQ. */ +{ "vsub2h", 0x28D50F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vsub2h<.cc> 0,limm,c 00101110110101010111CCCCCC0QQQQQ. */ +{ "vsub2h", 0x2ED57000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vsub2h a,limm,u6 00101110010101010111uuuuuuAAAAAA. */ +{ "vsub2h", 0x2E557000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsub2h 0,limm,u6 00101110010101010111uuuuuu111110. */ +{ "vsub2h", 0x2E55703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsub2h<.cc> 0,limm,u6 00101110110101010111uuuuuu1QQQQQ. */ +{ "vsub2h", 0x2ED57020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsub2h 0,limm,s12 00101110100101010111ssssssSSSSSS. */ +{ "vsub2h", 0x2E957000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsub2h a,limm,limm 00101110000101010111111110AAAAAA. */ +{ "vsub2h", 0x2E157F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsub2h 0,limm,limm 00101110000101010111111110111110. */ +{ "vsub2h", 0x2E157FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsub2h<.cc> 0,limm,limm 001011101101010101111111100QQQQQ. */ +{ "vsub2h", 0x2ED57F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vsub4b a,b,c 00101bbb001001010BBBCCCCCCAAAAAA. */ +{ "vsub4b", 0x28250000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsub4b 0,b,c 00101bbb001001010BBBCCCCCC111110. */ +{ "vsub4b", 0x2825003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsub4b<.cc> b,b,c 00101bbb111001010BBBCCCCCC0QQQQQ. */ +{ "vsub4b", 0x28E50000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vsub4b a,b,u6 00101bbb011001010BBBuuuuuuAAAAAA. */ +{ "vsub4b", 0x28650000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsub4b 0,b,u6 00101bbb011001010BBBuuuuuu111110. */ +{ "vsub4b", 0x2865003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsub4b<.cc> b,b,u6 00101bbb111001010BBBuuuuuu1QQQQQ. */ +{ "vsub4b", 0x28E50020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsub4b b,b,s12 00101bbb101001010BBBssssssSSSSSS. */ +{ "vsub4b", 0x28A50000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsub4b a,limm,c 00101110001001010111CCCCCCAAAAAA. */ +{ "vsub4b", 0x2E257000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsub4b a,b,limm 00101bbb001001010BBB111110AAAAAA. */ +{ "vsub4b", 0x28250F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsub4b 0,limm,c 00101110011001010111CCCCCC111110. */ +{ "vsub4b", 0x2E65703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsub4b 0,b,limm 00101bbb001001010BBB111110111110. */ +{ "vsub4b", 0x28250FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsub4b<.cc> b,b,limm 00101bbb111001010BBB1111100QQQQQ. */ +{ "vsub4b", 0x28E50F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vsub4b<.cc> 0,limm,c 00101110111001010111CCCCCC0QQQQQ. */ +{ "vsub4b", 0x2EE57000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vsub4b a,limm,u6 00101110011001010111uuuuuuAAAAAA. */ +{ "vsub4b", 0x2E657000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsub4b 0,limm,u6 00101110011001010111uuuuuu111110. */ +{ "vsub4b", 0x2E65703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsub4b<.cc> 0,limm,u6 00101110111001010111uuuuuu1QQQQQ. */ +{ "vsub4b", 0x2EE57020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsub4b 0,limm,s12 00101110101001010111ssssssSSSSSS. */ +{ "vsub4b", 0x2EA57000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsub4b a,limm,limm 00101110001001010111111110AAAAAA. */ +{ "vsub4b", 0x2E257F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsub4b 0,limm,limm 00101110001001010111111110111110. */ +{ "vsub4b", 0x2E257FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsub4b<.cc> 0,limm,limm 001011101110010101111111100QQQQQ. */ +{ "vsub4b", 0x2EE57F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vsub4h a,b,c 00101bbb001110010BBBCCCCCCAAAAAA. */ +{ "vsub4h", 0x28390000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsub4h 0,b,c 00101bbb001110010BBBCCCCCC111110. */ +{ "vsub4h", 0x2839003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsub4h<.cc> b,b,c 00101bbb111110010BBBCCCCCC0QQQQQ. */ +{ "vsub4h", 0x28F90000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vsub4h a,b,u6 00101bbb011110010BBBuuuuuuAAAAAA. */ +{ "vsub4h", 0x28790000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsub4h 0,b,u6 00101bbb011110010BBBuuuuuu111110. */ +{ "vsub4h", 0x2879003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsub4h<.cc> b,b,u6 00101bbb111110010BBBuuuuuu1QQQQQ. */ +{ "vsub4h", 0x28F90020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsub4h b,b,s12 00101bbb101110010BBBssssssSSSSSS. */ +{ "vsub4h", 0x28B90000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsub4h a,limm,c 00101110001110010111CCCCCCAAAAAA. */ +{ "vsub4h", 0x2E397000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsub4h a,b,limm 00101bbb001110010BBB111110AAAAAA. */ +{ "vsub4h", 0x28390F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsub4h 0,limm,c 00101110001110010111CCCCCC111110. */ +{ "vsub4h", 0x2E39703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsub4h 0,b,limm 00101bbb001110010BBB111110111110. */ +{ "vsub4h", 0x28390FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsub4h<.cc> b,b,limm 00101bbb111110010BBB1111100QQQQQ. */ +{ "vsub4h", 0x28F90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vsub4h<.cc> 0,limm,c 00101110111110010111CCCCCC0QQQQQ. */ +{ "vsub4h", 0x2EF97000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vsub4h a,limm,u6 00101110011110010111uuuuuuAAAAAA. */ +{ "vsub4h", 0x2E797000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsub4h 0,limm,u6 00101110011110010111uuuuuu111110. */ +{ "vsub4h", 0x2E79703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsub4h<.cc> 0,limm,u6 00101110111110010111uuuuuu1QQQQQ. */ +{ "vsub4h", 0x2EF97020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsub4h 0,limm,s12 00101110101110010111ssssssSSSSSS. */ +{ "vsub4h", 0x2EB97000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsub4h a,limm,limm 00101110001110010111111110AAAAAA. */ +{ "vsub4h", 0x2E397F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsub4h 0,limm,limm 00101110001110010111111110111110. */ +{ "vsub4h", 0x2E397FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsub4h<.cc> 0,limm,limm 001011101111100101111111100QQQQQ. */ +{ "vsub4h", 0x2EF97F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vsubadd a,b,c 00101bbb001111110BBBCCCCCCAAAAAA. */ +{ "vsubadd", 0x283F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsubadd 0,b,c 00101bbb001111110BBBCCCCCC111110. */ +{ "vsubadd", 0x283F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsubadd<.cc> b,b,c 00101bbb111111110BBBCCCCCC0QQQQQ. */ +{ "vsubadd", 0x28FF0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vsubadd a,b,u6 00101bbb011111110BBBuuuuuuAAAAAA. */ +{ "vsubadd", 0x287F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadd 0,b,u6 00101bbb011111110BBBuuuuuu111110. */ +{ "vsubadd", 0x287F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadd<.cc> b,b,u6 00101bbb111111110BBBuuuuuu1QQQQQ. */ +{ "vsubadd", 0x28FF0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsubadd b,b,s12 00101bbb101111110BBBssssssSSSSSS. */ +{ "vsubadd", 0x28BF0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsubadd a,limm,c 00101110001111110111CCCCCCAAAAAA. */ +{ "vsubadd", 0x2E3F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsubadd a,b,limm 00101bbb001111110BBB111110AAAAAA. */ +{ "vsubadd", 0x283F0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsubadd 0,limm,c 00101110001111110111CCCCCC111110. */ +{ "vsubadd", 0x2E3F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsubadd 0,b,limm 00101bbb001111110BBB111110111110. */ +{ "vsubadd", 0x283F0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsubadd<.cc> b,b,limm 00101bbb111111110BBB1111100QQQQQ. */ +{ "vsubadd", 0x28FF0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vsubadd<.cc> 0,limm,c 00101110111111110111CCCCCC0QQQQQ. */ +{ "vsubadd", 0x2EFF7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vsubadd a,limm,u6 00101110011111110111uuuuuuAAAAAA. */ +{ "vsubadd", 0x2E7F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadd 0,limm,u6 00101110011111110111uuuuuu111110. */ +{ "vsubadd", 0x2E7F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadd<.cc> 0,limm,u6 00101110111111110111uuuuuu1QQQQQ. */ +{ "vsubadd", 0x2EFF7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsubadd 0,limm,s12 00101110101111110111ssssssSSSSSS. */ +{ "vsubadd", 0x2EBF7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsubadd a,limm,limm 00101110001111110111111110AAAAAA. */ +{ "vsubadd", 0x2E3F7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsubadd 0,limm,limm 00101110001111110111111110111110. */ +{ "vsubadd", 0x2E3F7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsubadd<.cc> 0,limm,limm 001011101111111101111111100QQQQQ. */ +{ "vsubadd", 0x2EFF7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vsubadd2h a,b,c 00101bbb000101110BBBCCCCCCAAAAAA. */ +{ "vsubadd2h", 0x28170000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsubadd2h 0,b,c 00101bbb000101110BBBCCCCCC111110. */ +{ "vsubadd2h", 0x2817003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsubadd2h<.cc> b,b,c 00101bbb110101110BBBCCCCCC0QQQQQ. */ +{ "vsubadd2h", 0x28D70000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vsubadd2h a,b,u6 00101bbb010101110BBBuuuuuuAAAAAA. */ +{ "vsubadd2h", 0x28570000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadd2h 0,b,u6 00101bbb010101110BBBuuuuuu111110. */ +{ "vsubadd2h", 0x2857003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadd2h<.cc> b,b,u6 00101bbb110101110BBBuuuuuu1QQQQQ. */ +{ "vsubadd2h", 0x28D70020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsubadd2h b,b,s12 00101bbb100101110BBBssssssSSSSSS. */ +{ "vsubadd2h", 0x28970000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsubadd2h a,limm,c 00101110000101110111CCCCCCAAAAAA. */ +{ "vsubadd2h", 0x2E177000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsubadd2h a,b,limm 00101bbb000101110BBB111110AAAAAA. */ +{ "vsubadd2h", 0x28170F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsubadd2h 0,limm,c 00101110000101110111CCCCCC111110. */ +{ "vsubadd2h", 0x2E17703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsubadd2h 0,b,limm 00101bbb000101110BBB111110111110. */ +{ "vsubadd2h", 0x28170FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsubadd2h<.cc> b,b,limm 00101bbb110101110BBB1111100QQQQQ. */ +{ "vsubadd2h", 0x28D70F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vsubadd2h<.cc> 0,limm,c 00101110110101110111CCCCCC0QQQQQ. */ +{ "vsubadd2h", 0x2ED77000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vsubadd2h a,limm,u6 00101110010101110111uuuuuuAAAAAA. */ +{ "vsubadd2h", 0x2E577000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadd2h 0,limm,u6 00101110010101110111uuuuuu111110. */ +{ "vsubadd2h", 0x2E57703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadd2h<.cc> 0,limm,u6 00101110110101110111uuuuuu1QQQQQ. */ +{ "vsubadd2h", 0x2ED77020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsubadd2h 0,limm,s12 00101110100101110111ssssssSSSSSS. */ +{ "vsubadd2h", 0x2E977000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsubadd2h a,limm,limm 00101110000101110111111110AAAAAA. */ +{ "vsubadd2h", 0x2E177F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsubadd2h 0,limm,limm 00101110000101110111111110111110. */ +{ "vsubadd2h", 0x2E177FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsubadd2h<.cc> 0,limm,limm 001011101101011101111111100QQQQQ. */ +{ "vsubadd2h", 0x2ED77F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MPY, MPY7E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vsubadd4h a,b,c 00101bbb001110110BBBCCCCCCAAAAAA. */ +{ "vsubadd4h", 0x283B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsubadd4h 0,b,c 00101bbb001110110BBBCCCCCC111110. */ +{ "vsubadd4h", 0x283B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsubadd4h<.cc> b,b,c 00101bbb111110110BBBCCCCCC0QQQQQ. */ +{ "vsubadd4h", 0x28FB0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vsubadd4h a,b,u6 00101bbb011110110BBBuuuuuuAAAAAA. */ +{ "vsubadd4h", 0x287B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadd4h 0,b,u6 00101bbb011110110BBBuuuuuu111110. */ +{ "vsubadd4h", 0x287B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadd4h<.cc> b,b,u6 00101bbb111110110BBBuuuuuu1QQQQQ. */ +{ "vsubadd4h", 0x28FB0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsubadd4h b,b,s12 00101bbb101110110BBBssssssSSSSSS. */ +{ "vsubadd4h", 0x28BB0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsubadd4h a,limm,c 00101110001110110111CCCCCCAAAAAA. */ +{ "vsubadd4h", 0x2E3B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsubadd4h a,b,limm 00101bbb001110110BBB111110AAAAAA. */ +{ "vsubadd4h", 0x283B0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsubadd4h 0,limm,c 00101110001110110111CCCCCC111110. */ +{ "vsubadd4h", 0x2E3B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsubadd4h 0,b,limm 00101bbb001110110BBB111110111110. */ +{ "vsubadd4h", 0x283B0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsubadd4h<.cc> b,b,limm 00101bbb111110110BBB1111100QQQQQ. */ +{ "vsubadd4h", 0x28FB0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vsubadd4h<.cc> 0,limm,c 00101110111110110111CCCCCC0QQQQQ. */ +{ "vsubadd4h", 0x2EFB7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vsubadd4h a,limm,u6 00101110011110110111uuuuuuAAAAAA. */ +{ "vsubadd4h", 0x2E7B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadd4h 0,limm,u6 00101110011110110111uuuuuu111110. */ +{ "vsubadd4h", 0x2E7B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadd4h<.cc> 0,limm,u6 00101110111110110111uuuuuu1QQQQQ. */ +{ "vsubadd4h", 0x2EFB7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsubadd4h 0,limm,s12 00101110101110110111ssssssSSSSSS. */ +{ "vsubadd4h", 0x2EBB7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsubadd4h a,limm,limm 00101110001110110111111110AAAAAA. */ +{ "vsubadd4h", 0x2E3B7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsubadd4h 0,limm,limm 00101110001110110111111110111110. */ +{ "vsubadd4h", 0x2E3B7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsubadd4h<.cc> 0,limm,limm 001011101111101101111111100QQQQQ. */ +{ "vsubadd4h", 0x2EFB7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vsubadds a,b,c 00101bbb001111110BBBCCCCCCAAAAAA */ +{ "vsubadds", 0x283F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsubadds<.cc> b,b,c 00101bbb111111110BBBCCCCCC0QQQQQ */ +{ "vsubadds", 0x28FF0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vsubadds 0,b,c 00101bbb001111110BBBCCCCCC111110 */ +{ "vsubadds", 0x283F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsubadds 0,b,u6 00101bbb011111110BBBuuuuuu111110 */ +{ "vsubadds", 0x287F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadds a,b,u6 00101bbb011111110BBBuuuuuuAAAAAA */ +{ "vsubadds", 0x287F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadds<.cc> b,b,u6 00101bbb111111110BBBuuuuuu1QQQQQ */ +{ "vsubadds", 0x28FF0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsubadds b,b,s12 00101bbb101111110BBBssssssSSSSSS */ +{ "vsubadds", 0x28BF0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsubadds 0,b,limm 00101bbb001111110BBB111110111110 */ +{ "vsubadds", 0x283F0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsubadds 0,limm,c 00101110001111110111CCCCCC111110 */ +{ "vsubadds", 0x2E3F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsubadds<.cc> 0,limm,c 00101110111111110111CCCCCC0QQQQQ */ +{ "vsubadds", 0x2EFF7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vsubadds a,limm,c 00101110001111110111CCCCCCAAAAAA */ +{ "vsubadds", 0x2E3F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsubadds<.cc> b,b,limm 00101bbb111111110BBB1111100QQQQQ */ +{ "vsubadds", 0x28FF0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vsubadds a,b,limm 00101bbb001111110BBB111110AAAAAA */ +{ "vsubadds", 0x283F0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsubadds 0,limm,u6 00101110011111110111uuuuuu111110 */ +{ "vsubadds", 0x2E7F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadds<.cc> 0,limm,u6 00101110111111110111uuuuuu1QQQQQ */ +{ "vsubadds", 0x2EFF7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsubadds a,limm,u6 00101110011111110111uuuuuuAAAAAA */ +{ "vsubadds", 0x2E7F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadds 0,limm,s12 00101110101111110111ssssssSSSSSS */ +{ "vsubadds", 0x2EBF7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsubadds a,limm,limm 00101110001111110111111110AAAAAA */ +{ "vsubadds", 0x2E3F7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsubadds 0,limm,limm 00101110001111110111111110111110 */ +{ "vsubadds", 0x2E3F7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsubadds<.cc> 0,limm,limm 001011101111111101111111100QQQQQ */ +{ "vsubadds", 0x2EFF7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vsubadds2h a,b,c 00101bbb000101111BBBCCCCCCAAAAAA. */ +{ "vsubadds2h", 0x28178000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsubadds2h 0,b,c 00101bbb000101111BBBCCCCCC111110. */ +{ "vsubadds2h", 0x2817803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsubadds2h<.cc> b,b,c 00101bbb110101111BBBCCCCCC0QQQQQ. */ +{ "vsubadds2h", 0x28D78000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vsubadds2h a,b,u6 00101bbb010101111BBBuuuuuuAAAAAA. */ +{ "vsubadds2h", 0x28578000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadds2h 0,b,u6 00101bbb010101111BBBuuuuuu111110. */ +{ "vsubadds2h", 0x2857803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadds2h<.cc> b,b,u6 00101bbb110101111BBBuuuuuu1QQQQQ. */ +{ "vsubadds2h", 0x28D78020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsubadds2h b,b,s12 00101bbb100101111BBBssssssSSSSSS. */ +{ "vsubadds2h", 0x28978000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsubadds2h a,limm,c 00101110000101111111CCCCCCAAAAAA. */ +{ "vsubadds2h", 0x2E17F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsubadds2h a,b,limm 00101bbb000101111BBB111110AAAAAA. */ +{ "vsubadds2h", 0x28178F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsubadds2h 0,limm,c 00101110000101111111CCCCCC111110. */ +{ "vsubadds2h", 0x2E17F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsubadds2h 0,b,limm 00101bbb000101111BBB111110111110. */ +{ "vsubadds2h", 0x28178FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsubadds2h<.cc> b,b,limm 00101bbb110101111BBB1111100QQQQQ. */ +{ "vsubadds2h", 0x28D78F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vsubadds2h<.cc> 0,limm,c 00101110110101111111CCCCCC0QQQQQ. */ +{ "vsubadds2h", 0x2ED7F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vsubadds2h a,limm,u6 00101110010101111111uuuuuuAAAAAA. */ +{ "vsubadds2h", 0x2E57F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadds2h 0,limm,u6 00101110010101111111uuuuuu111110. */ +{ "vsubadds2h", 0x2E57F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadds2h<.cc> 0,limm,u6 00101110110101111111uuuuuu1QQQQQ. */ +{ "vsubadds2h", 0x2ED7F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsubadds2h 0,limm,s12 00101110100101111111ssssssSSSSSS. */ +{ "vsubadds2h", 0x2E97F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsubadds2h a,limm,limm 00101110000101111111111110AAAAAA. */ +{ "vsubadds2h", 0x2E17FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsubadds2h 0,limm,limm 00101110000101111111111110111110. */ +{ "vsubadds2h", 0x2E17FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsubadds2h<.cc> 0,limm,limm 001011101101011111111111100QQQQQ. */ +{ "vsubadds2h", 0x2ED7FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vsubadds4h 0,b,c 00101bbb001110110BBBCCCCCC111110 */ +{ "vsubadds4h", 0x283B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsubadds4h<.cc> b,b,c 00101bbb111110110BBBCCCCCC0QQQQQ */ +{ "vsubadds4h", 0x28FB0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vsubadds4h a,b,c 00101bbb001110110BBBCCCCCCAAAAAA */ +{ "vsubadds4h", 0x283B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsubadds4h 0,b,u6 00101bbb011110110BBBuuuuuu111110 */ +{ "vsubadds4h", 0x287B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadds4h<.cc> b,b,u6 00101bbb111110110BBBuuuuuu1QQQQQ */ +{ "vsubadds4h", 0x28FB0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsubadds4h a,b,u6 00101bbb011110110BBBuuuuuuAAAAAA */ +{ "vsubadds4h", 0x287B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadds4h b,b,s12 00101bbb101110110BBBssssssSSSSSS */ +{ "vsubadds4h", 0x28BB0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsubadds4h a,limm,c 00101110001110110111CCCCCCAAAAAA */ +{ "vsubadds4h", 0x2E3B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsubadds4h 0,b,limm 00101bbb001110110BBB111110111110 */ +{ "vsubadds4h", 0x283B0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsubadds4h<.cc> 0,limm,c 00101110111110110111CCCCCC0QQQQQ */ +{ "vsubadds4h", 0x2EFB7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vsubadds4h<.cc> b,b,limm 00101bbb111110110BBB1111100QQQQQ */ +{ "vsubadds4h", 0x28FB0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vsubadds4h a,b,limm 00101bbb001110110BBB111110AAAAAA */ +{ "vsubadds4h", 0x283B0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsubadds4h 0,limm,c 00101110001110110111CCCCCC111110 */ +{ "vsubadds4h", 0x2E3B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsubadds4h a,limm,u6 00101110011110110111uuuuuuAAAAAA */ +{ "vsubadds4h", 0x2E7B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadds4h 0,limm,u6 00101110011110110111uuuuuu111110 */ +{ "vsubadds4h", 0x2E7B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubadds4h<.cc> 0,limm,u6 00101110111110110111uuuuuu1QQQQQ */ +{ "vsubadds4h", 0x2EFB7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsubadds4h 0,limm,s12 00101110101110110111ssssssSSSSSS */ +{ "vsubadds4h", 0x2EBB7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsubadds4h a,limm,limm 00101110001110110111111110AAAAAA */ +{ "vsubadds4h", 0x2E3B7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsubadds4h<.cc> 0,limm,limm 001011101111101101111111100QQQQQ */ +{ "vsubadds4h", 0x2EFB7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vsubadds4h 0,limm,limm 00101110001110110111111110111110 */ +{ "vsubadds4h", 0x2E3B7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsubs2 a,b,c 00101bbb001111010BBBCCCCCCAAAAAA */ +{ "vsubs2", 0x283D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsubs2<.cc> b,b,c 00101bbb111111010BBBCCCCCC0QQQQQ */ +{ "vsubs2", 0x28FD0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vsubs2 0,b,c 00101bbb001111010BBBCCCCCC111110 */ +{ "vsubs2", 0x283D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsubs2<.cc> b,b,u6 00101bbb111111010BBBuuuuuu1QQQQQ */ +{ "vsubs2", 0x28FD0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsubs2 0,b,u6 00101bbb011111010BBBuuuuuu111110 */ +{ "vsubs2", 0x287D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubs2 a,b,u6 00101bbb011111010BBBuuuuuuAAAAAA */ +{ "vsubs2", 0x287D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubs2 b,b,s12 00101bbb101111010BBBssssssSSSSSS */ +{ "vsubs2", 0x28BD0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsubs2 0,limm,c 00101110001111010111CCCCCC111110 */ +{ "vsubs2", 0x2E3D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsubs2 0,b,limm 00101bbb001111010BBB111110111110 */ +{ "vsubs2", 0x283D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsubs2 a,b,limm 00101bbb001111010BBB111110AAAAAA */ +{ "vsubs2", 0x283D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsubs2<.cc> 0,limm,c 00101110111111010111CCCCCC0QQQQQ */ +{ "vsubs2", 0x2EFD7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vsubs2<.cc> b,b,limm 00101bbb111111010BBB1111100QQQQQ */ +{ "vsubs2", 0x28FD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vsubs2 a,limm,c 00101110001111010111CCCCCCAAAAAA */ +{ "vsubs2", 0x2E3D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsubs2 0,limm,u6 00101110011111010111uuuuuu111110 */ +{ "vsubs2", 0x2E7D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubs2<.cc> 0,limm,u6 00101110111111010111uuuuuu1QQQQQ */ +{ "vsubs2", 0x2EFD7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsubs2 a,limm,u6 00101110011111010111uuuuuuAAAAAA */ +{ "vsubs2", 0x2E7D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubs2 0,limm,s12 00101110101111010111ssssssSSSSSS */ +{ "vsubs2", 0x2EBD7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsubs2 0,limm,limm 00101110001111010111111110111110 */ +{ "vsubs2", 0x2E3D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsubs2<.cc> 0,limm,limm 001011101111110101111111100QQQQQ */ +{ "vsubs2", 0x2EFD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vsubs2 a,limm,limm 00101110001111010111111110AAAAAA */ +{ "vsubs2", 0x2E3D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsubs2h a,b,c 00101bbb000101011BBBCCCCCCAAAAAA. */ +{ "vsubs2h", 0x28158000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsubs2h 0,b,c 00101bbb000101011BBBCCCCCC111110. */ +{ "vsubs2h", 0x2815803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsubs2h<.cc> b,b,c 00101bbb110101011BBBCCCCCC0QQQQQ. */ +{ "vsubs2h", 0x28D58000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vsubs2h a,b,u6 00101bbb010101011BBBuuuuuuAAAAAA. */ +{ "vsubs2h", 0x28558000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubs2h 0,b,u6 00101bbb010101011BBBuuuuuu111110. */ +{ "vsubs2h", 0x2855803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubs2h<.cc> b,b,u6 00101bbb110101011BBBuuuuuu1QQQQQ. */ +{ "vsubs2h", 0x28D58020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsubs2h b,b,s12 00101bbb100101011BBBssssssSSSSSS. */ +{ "vsubs2h", 0x28958000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsubs2h a,limm,c 00101110000101011111CCCCCCAAAAAA. */ +{ "vsubs2h", 0x2E15F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsubs2h a,b,limm 00101bbb000101011BBB111110AAAAAA. */ +{ "vsubs2h", 0x28158F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsubs2h 0,limm,c 00101110000101011111CCCCCC111110. */ +{ "vsubs2h", 0x2E15F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsubs2h 0,b,limm 00101bbb000101011BBB111110111110. */ +{ "vsubs2h", 0x28158FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsubs2h<.cc> b,b,limm 00101bbb110101011BBB1111100QQQQQ. */ +{ "vsubs2h", 0x28D58F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RB_CHK, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vsubs2h<.cc> 0,limm,c 00101110110101011111CCCCCC0QQQQQ. */ +{ "vsubs2h", 0x2ED5F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vsubs2h a,limm,u6 00101110010101011111uuuuuuAAAAAA. */ +{ "vsubs2h", 0x2E55F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubs2h 0,limm,u6 00101110010101011111uuuuuu111110. */ +{ "vsubs2h", 0x2E55F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubs2h<.cc> 0,limm,u6 00101110110101011111uuuuuu1QQQQQ. */ +{ "vsubs2h", 0x2ED5F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsubs2h 0,limm,s12 00101110100101011111ssssssSSSSSS. */ +{ "vsubs2h", 0x2E95F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsubs2h a,limm,limm 00101110000101011111111110AAAAAA. */ +{ "vsubs2h", 0x2E15FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_RA_CHK, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsubs2h 0,limm,limm 00101110000101011111111110111110. */ +{ "vsubs2h", 0x2E15FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsubs2h<.cc> 0,limm,limm 001011101101010111111111100QQQQQ. */ +{ "vsubs2h", 0x2ED5FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vsubs4h a,b,c 00101bbb001110010BBBCCCCCCAAAAAA */ +{ "vsubs4h", 0x28390000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsubs4h<.cc> b,b,c 00101bbb111110010BBBCCCCCC0QQQQQ */ +{ "vsubs4h", 0x28F90000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_CC }}, + +/* vsubs4h 0,b,c 00101bbb001110010BBBCCCCCC111110 */ +{ "vsubs4h", 0x2839003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { 0 }}, + +/* vsubs4h 0,b,u6 00101bbb011110010BBBuuuuuu111110 */ +{ "vsubs4h", 0x2879003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubs4h<.cc> b,b,u6 00101bbb111110010BBBuuuuuu1QQQQQ */ +{ "vsubs4h", 0x28F90020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsubs4h a,b,u6 00101bbb011110010BBBuuuuuuAAAAAA */ +{ "vsubs4h", 0x28790000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubs4h b,b,s12 00101bbb101110010BBBssssssSSSSSS */ +{ "vsubs4h", 0x28B90000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsubs4h<.cc> 0,limm,c 00101110111110010111CCCCCC0QQQQQ */ +{ "vsubs4h", 0x2EF97000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_CC }}, + +/* vsubs4h a,b,limm 00101bbb001110010BBB111110AAAAAA */ +{ "vsubs4h", 0x28390F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsubs4h 0,limm,c 00101110001110010111CCCCCC111110 */ +{ "vsubs4h", 0x2E39703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsubs4h<.cc> b,b,limm 00101bbb111110010BBB1111100QQQQQ */ +{ "vsubs4h", 0x28F90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_CC }}, + +/* vsubs4h 0,b,limm 00101bbb001110010BBB111110111110 */ +{ "vsubs4h", 0x28390FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { 0 }}, + +/* vsubs4h a,limm,c 00101110001110010111CCCCCCAAAAAA */ +{ "vsubs4h", 0x2E397000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { 0 }}, + +/* vsubs4h<.cc> 0,limm,u6 00101110111110010111uuuuuu1QQQQQ */ +{ "vsubs4h", 0x2EF97020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_CC }}, + +/* vsubs4h a,limm,u6 00101110011110010111uuuuuuAAAAAA */ +{ "vsubs4h", 0x2E797000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubs4h 0,limm,u6 00101110011110010111uuuuuu111110 */ +{ "vsubs4h", 0x2E79703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { 0 }}, + +/* vsubs4h 0,limm,s12 00101110101110010111ssssssSSSSSS */ +{ "vsubs4h", 0x2EB97000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { 0 }}, + +/* vsubs4h a,limm,limm 00101110001110010111111110AAAAAA */ +{ "vsubs4h", 0x2E397F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* vsubs4h<.cc> 0,limm,limm 001011101111100101111111100QQQQQ */ +{ "vsubs4h", 0x2EF97F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_CC }}, + +/* vsubs4h 0,limm,limm 00101110001110010111111110111110 */ +{ "vsubs4h", 0x2E397FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { 0 }}, + +/* wevt c 00100000001011110001CCCCCC111111. */ +{ "wevt", 0x202F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_RC }, { 0 }}, + +/* wevt u6 00100000011011110001uuuuuu111111. */ +{ "wevt", 0x206F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_UIMM6_20 }, { 0 }}, + +/* wlfc c 00100001001011110001CCCCCC111111. */ +{ "wlfc", 0x212F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_RC }, { 0 }}, + +/* wlfc u6 00100001011011110001uuuuuu111111. */ +{ "wlfc", 0x216F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { OPERAND_UIMM6_20 }, { 0 }}, + +/* xbfu<.f> a,b,c 00100bbb00101101FBBBCCCCCCAAAAAA. */ +{ "xbfu", 0x202D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* xbfu<.f> 0,b,c 00100bbb00101101FBBBCCCCCC111110. */ +{ "xbfu", 0x202D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* xbfu<.f><.cc> b,b,c 00100bbb11101101FBBBCCCCCC0QQQQQ. */ +{ "xbfu", 0x20ED0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* xbfu<.f> a,b,u6 00100bbb01101101FBBBuuuuuuAAAAAA. */ +{ "xbfu", 0x206D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* xbfu<.f> 0,b,u6 00100bbb01101101FBBBuuuuuu111110. */ +{ "xbfu", 0x206D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* xbfu<.f><.cc> b,b,u6 00100bbb11101101FBBBuuuuuu1QQQQQ. */ +{ "xbfu", 0x20ED0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* xbfu<.f> b,b,s12 00100bbb10101101FBBBssssssSSSSSS. */ +{ "xbfu", 0x20AD0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* xbfu<.f> a,limm,c 0010011000101101F111CCCCCCAAAAAA. */ +{ "xbfu", 0x262D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* xbfu<.f> a,b,limm 00100bbb00101101FBBB111110AAAAAA. */ +{ "xbfu", 0x202D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* xbfu<.f> 0,limm,c 0010011000101101F111CCCCCC111110. */ +{ "xbfu", 0x262D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* xbfu<.f> 0,b,limm 00100bbb00101101FBBB111110111110. */ +{ "xbfu", 0x202D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* xbfu<.f><.cc> b,b,limm 00100bbb11101101FBBB1111100QQQQQ. */ +{ "xbfu", 0x20ED0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* xbfu<.f><.cc> 0,limm,c 0010011011101101F111CCCCCC0QQQQQ. */ +{ "xbfu", 0x26ED7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* xbfu<.f> a,limm,u6 0010011001101101F111uuuuuuAAAAAA. */ +{ "xbfu", 0x266D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* xbfu<.f> 0,limm,u6 0010011001101101F111uuuuuu111110. */ +{ "xbfu", 0x266D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* xbfu<.f><.cc> 0,limm,u6 0010011011101101F111uuuuuu1QQQQQ. */ +{ "xbfu", 0x26ED7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* xbfu<.f> 0,limm,s12 0010011010101101F111ssssssSSSSSS. */ +{ "xbfu", 0x26AD7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* xbfu<.f> a,limm,limm 0010011000101101F111111110AAAAAA. */ +{ "xbfu", 0x262D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* xbfu<.f> 0,limm,limm 0010011000101101F111111110111110. */ +{ "xbfu", 0x262D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* xbfu<.f><.cc> 0,limm,limm 0010011011101101F1111111100QQQQQ. */ +{ "xbfu", 0x26ED7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* xor<.f> a,b,c 00100bbb00000111FBBBCCCCCCAAAAAA. */ +{ "xor", 0x20070000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* xor<.f> 0,b,c 00100bbb00000111FBBBCCCCCC111110. */ +{ "xor", 0x2007003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* xor<.f><.cc> b,b,c 00100bbb11000111FBBBCCCCCC0QQQQQ. */ +{ "xor", 0x20C70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* xor<.f> a,b,u6 00100bbb01000111FBBBuuuuuuAAAAAA. */ +{ "xor", 0x20470000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* xor<.f> 0,b,u6 00100bbb01000111FBBBuuuuuu111110. */ +{ "xor", 0x2047003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* xor<.f><.cc> b,b,u6 00100bbb11000111FBBBuuuuuu1QQQQQ. */ +{ "xor", 0x20C70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* xor<.f> b,b,s12 00100bbb10000111FBBBssssssSSSSSS. */ +{ "xor", 0x20870000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* xor<.f> a,limm,c 0010011000000111F111CCCCCCAAAAAA. */ +{ "xor", 0x26077000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* xor<.f> a,b,limm 00100bbb00000111FBBB111110AAAAAA. */ +{ "xor", 0x20070F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* xor<.f> 0,limm,c 0010011000000111F111CCCCCC111110. */ +{ "xor", 0x2607703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* xor<.f> 0,b,limm 00100bbb00000111FBBB111110111110. */ +{ "xor", 0x20070FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* xor<.f><.cc> 0,limm,c 0010011011000111F111CCCCCC0QQQQQ. */ +{ "xor", 0x26C77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_RC }, { C_F, C_CC }}, + +/* xor<.f><.cc> b,b,limm 00100bbb11000111FBBB1111100QQQQQ. */ +{ "xor", 0x20C70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, + +/* xor<.f> a,limm,u6 0010011001000111F111uuuuuuAAAAAA. */ +{ "xor", 0x26477000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* xor<.f> 0,limm,u6 0010011001000111F111uuuuuu111110. */ +{ "xor", 0x2647703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F }}, + +/* xor<.f><.cc> 0,limm,u6 0010011011000111F111uuuuuu1QQQQQ. */ +{ "xor", 0x26C77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* xor<.f> 0,limm,s12 0010011010000111F111ssssssSSSSSS. */ +{ "xor", 0x26877000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_SIMM12_20 }, { C_F }}, + +/* xor<.f> a,limm,limm 0010011000000111F111111110AAAAAA. */ +{ "xor", 0x26077F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* xor<.f> 0,limm,limm 0010011000000111F111111110111110. */ +{ "xor", 0x26077FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F }}, + +/* xor<.f><.cc> 0,limm,limm 0010011011000111F1111111100QQQQQ. */ +{ "xor", 0x26C77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_ZA, OPERAND_LIMM, OPERAND_LIMMdup }, { C_F, C_CC }}, + +/* xor_s b,b,c 01111bbbccc00111. */ +{ "xor_s", 0x00007807, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { OPERAND_RB_S, OPERAND_RB_Sdup, OPERAND_RC_S }, { 0 }}, + +/* xpkqb<.f> a,b,c 00110bbb00100010FBBBCCCCCCAAAAAA. */ +{ "xpkqb", 0x30220000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_RC }, { C_F }}, + +/* xpkqb<.f><.cc> b,b,c 00110bbb11100010FBBBCCCCCC0QQQQQ. */ +{ "xpkqb", 0x30E20000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_RC }, { C_F, C_CC }}, + +/* xpkqb<.f> a,b,u6 00110bbb01100010FBBBuuuuuuAAAAAA. */ +{ "xpkqb", 0x30620000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_UIMM6_20 }, { C_F }}, + +/* xpkqb<.f><.cc> b,b,u6 00110bbb11100010FBBBuuuuuu1QQQQQ. */ +{ "xpkqb", 0x30E20020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_UIMM6_20 }, { C_F, C_CC }}, + +/* xpkqb<.f> b,b,s12 00110bbb10100010FBBBssssssSSSSSS. */ + +{ "xpkqb", 0x30A20000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_SIMM12_20 }, { C_F }}, + +/* xpkqb<.f> a,limm,c 0011011000100010F111CCCCCCAAAAAA. */ +{ "xpkqb", 0x36227000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_LIMM, OPERAND_RC }, { C_F }}, + +/* xpkqb<.f> a,b,limm 00110bbb00100010FBBB111110AAAAAA. */ +{ "xpkqb", 0x30220F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RA, OPERAND_RB, OPERAND_LIMM }, { C_F }}, + +/* xpkqb<.f><.cc> b,b,limm 00110bbb11100010FBBB1111100QQQQQ. */ +{ "xpkqb", 0x30E20F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { OPERAND_RB, OPERAND_RBdup, OPERAND_LIMM }, { C_F, C_CC }}, From patchwork Wed Nov 11 16:17:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cupertino Miranda X-Patchwork-Id: 1398388 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2001:8b0:10b:1231::1; helo=merlin.infradead.org; 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[2.80.104.46]) by smtp.gmail.com with ESMTPSA id s188sm3115178wmf.45.2020.11.11.08.18.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2020 08:18:09 -0800 (PST) From: cupertinomiranda@gmail.com To: qemu-devel@nongnu.org Subject: [PATCH 04/15] arc: TCG and decoder glue code and helpers Date: Wed, 11 Nov 2020 16:17:47 +0000 Message-Id: <20201111161758.9636-5-cupertinomiranda@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201111161758.9636-1-cupertinomiranda@gmail.com> References: <20201111161758.9636-1-cupertinomiranda@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201111_111812_286970_BC02D3A4 X-CRM114-Status: GOOD ( 25.01 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:42e listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [cupertinomiranda[at]gmail.com] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Claudiu Zissulescu , Cupertino Miranda , Shahab Vahedi , Shahab Vahedi , Cupertino Miranda , linux-snps-arc@lists.infradead.org, Claudiu Zissulescu Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Cupertino Miranda Signed-off-by: Cupertino Miranda --- target/arc/extra_mapping.def | 40 ++ target/arc/helper.c | 293 +++++++++++++ target/arc/helper.h | 46 ++ target/arc/op_helper.c | 749 +++++++++++++++++++++++++++++++++ target/arc/semfunc_mapping.def | 329 +++++++++++++++ 5 files changed, 1457 insertions(+) create mode 100644 target/arc/extra_mapping.def create mode 100644 target/arc/helper.c create mode 100644 target/arc/helper.h create mode 100644 target/arc/op_helper.c create mode 100644 target/arc/semfunc_mapping.def diff --git a/target/arc/extra_mapping.def b/target/arc/extra_mapping.def new file mode 100644 index 0000000000..1387d7d483 --- /dev/null +++ b/target/arc/extra_mapping.def @@ -0,0 +1,40 @@ +/* + * QEMU ARC EXTRA MAPPING + * + * Copyright (c) 2020 Synopsys Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +SEMANTIC_FUNCTION(SWI, 1) +SEMANTIC_FUNCTION(SWI, 1) +SEMANTIC_FUNCTION(UNIMP, 0) +SEMANTIC_FUNCTION(RTIE, 0) +SEMANTIC_FUNCTION(SLEEP, 1) + +MAPPING(swi, SWI, 0) +CONSTANT(SWI, swi_s, 0, 0) +MAPPING(swi_s, SWI, 1, 0) +MAPPING(trap_s, TRAP, 1, 0) +MAPPING(rtie, RTIE, 0) +MAPPING(sleep, SLEEP, 1, 0) +MAPPING(vadd2, VADD, 3, 0, 1, 2) +MAPPING(vadd2h, VADD, 3, 0, 1, 2) +MAPPING(vadd4h, VADD, 3, 0, 1, 2) +MAPPING(vsub2, VSUB, 3, 0, 1, 2) +MAPPING(vsub2h, VSUB, 3, 0, 1, 2) +MAPPING(vsub4h, VSUB, 3, 0, 1, 2) +MAPPING(mpyd, MPYD, 3, 0, 1, 2) +MAPPING(mpydu, MPYD, 3, 0, 1, 2) diff --git a/target/arc/helper.c b/target/arc/helper.c new file mode 100644 index 0000000000..aca7152ef8 --- /dev/null +++ b/target/arc/helper.c @@ -0,0 +1,293 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synppsys Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#include "qemu/osdep.h" + +#include "cpu.h" +#include "hw/irq.h" +#include "include/hw/sysbus.h" +#include "include/sysemu/sysemu.h" +#include "qemu/qemu-print.h" +#include "exec/exec-all.h" +#include "exec/cpu_ldst.h" +#include "qemu/host-utils.h" +#include "exec/helper-proto.h" +#include "irq.h" + +#if defined(CONFIG_USER_ONLY) + +void arc_cpu_do_interrupt(CPUState *cs) +{ + ARCCPU *cpu = ARC_CPU(cs); + CPUARCState *env = &cpu->env; + + cs->exception_index = -1; + CPU_ILINK(env) = env->pc; +} + +#else /* !CONFIG_USER_ONLY */ + +void arc_cpu_do_interrupt(CPUState *cs) +{ + ARCCPU *cpu = ARC_CPU(cs); + CPUARCState *env = &cpu->env; + uint32_t offset = 0; + uint32_t vectno; + const char *name; + + /* + * NOTE: Special LP_END exception. Immediatelly return code execution to + * lp_start. + * Now also used for delayslot MissI cases. + * This special exception should not execute any of the exception + * handling code. Instead it returns immediately after setting PC to the + * address passed as exception parameter. + */ + if (cs->exception_index == EXCP_LPEND_REACHED + || cs->exception_index == EXCP_FAKE) { + env->pc = env->param; + CPU_PCL(env) = env->pc & 0xfffffffe; + return; + } + + /* If we take an exception within an exception => fatal Machine Check. */ + if (env->stat.AEf == 1) { + cs->exception_index = EXCP_MACHINE_CHECK; + env->causecode = 0; + env->param = 0; + env->mmu.enabled = false; /* no more MMU */ + env->mpu.enabled = false; /* no more MPU */ + } + vectno = cs->exception_index & 0x0F; + offset = vectno << 2; + + /* Generic computation for exceptions. */ + switch (cs->exception_index) { + case EXCP_RESET: + name = "Reset"; + break; + case EXCP_MEMORY_ERROR: + name = "Memory Error"; + break; + case EXCP_INST_ERROR: + name = "Instruction Error"; + break; + case EXCP_MACHINE_CHECK: + name = "Machine Check"; + break; + case EXCP_TLB_MISS_I: + name = "TLB Miss Instruction"; + break; + case EXCP_TLB_MISS_D: + name = "TLB Miss Data"; + break; + case EXCP_PROTV: + name = "Protection Violation"; + break; + case EXCP_PRIVILEGEV: + name = "Privilege Violation"; + break; + case EXCP_SWI: + name = "SWI"; + break; + case EXCP_TRAP: + name = "Trap"; + break; + case EXCP_EXTENSION: + name = "Extension"; + break; + case EXCP_DIVZERO: + name = "DIV by Zero"; + break; + case EXCP_DCERROR: + name = "DCError"; + break; + case EXCP_MISALIGNED: + name = "Misaligned"; + break; + case EXCP_IRQ: + default: + cpu_abort(cs, "unhandled exception/irq type=%d\n", + cs->exception_index); + break; + } + + qemu_log_mask(CPU_LOG_INT, "[EXCP] exception %d (%s) at pc=0x%08x\n", + cs->exception_index, name, env->pc); + + /* + * 3. exception status register is loaded with the contents + * of STATUS32. + */ + env->stat_er = env->stat; + + /* 4. exception return branch target address register. */ + env->erbta = env->bta; + + /* + * 5. eception cause register is loaded with a code to indicate + * the cause of the exception. + */ + env->ecr = (vectno & 0xFF) << 16; + env->ecr |= (env->causecode & 0xFF) << 8; + env->ecr |= (env->param & 0xFF); + + /* 6. Set the EFA if available. */ + if (cpu->cfg.has_mmu || cpu->cfg.has_mpu) { + switch (cs->exception_index) { + case EXCP_DCERROR: + case EXCP_DIVZERO: + case EXCP_EXTENSION: + case EXCP_TRAP: + case EXCP_SWI: + case EXCP_PRIVILEGEV: + case EXCP_MACHINE_CHECK: + case EXCP_INST_ERROR: + case EXCP_RESET: + /* TODO: this should move to the place raising the exception */ + env->efa = env->pc; + break; + default: + break; + } + } + + /* 7. CPU is switched to kernel mode. */ + env->stat.Uf = 0; + + if (env->stat_er.Uf) { + switchSP(env); + } + + /* 8. Interrupts are disabled. */ + env->stat.IEf = 0; + + /* 9. The active exception flag is set. */ + env->stat.AEf = 1; + + /* 10-14. Other flags sets. */ + env->stat.Zf = env->stat_er.Uf; + env->stat.Lf = 1; + env->stat.DEf = 0; + env->stat.ESf = 0; + env->stat.DZf = 0; + env->stat.SCf = 0; + + /* 15. The PC is set with the appropriate exception vector. */ + env->pc = cpu_ldl_code(env, env->intvec + offset); + CPU_PCL(env) = env->pc & 0xfffffffe; + + qemu_log_mask(CPU_LOG_INT, "[EXCP] isr=0x%x vec=0x%x ecr=0x%08x\n", + env->pc, offset, env->ecr); + + /* Make sure that exception code decodes corectly */ + env->stat.is_delay_slot_instruction = 0; + + cs->exception_index = -1; +} + +#endif + + +static gint arc_cpu_list_compare(gconstpointer a, gconstpointer b) +{ + ObjectClass *class_a = (ObjectClass *)a; + ObjectClass *class_b = (ObjectClass *)b; + const char *name_a; + const char *name_b; + + name_a = object_class_get_name(class_a); + name_b = object_class_get_name(class_b); + if (strcmp(name_a, "any-" TYPE_ARC_CPU) == 0) { + return 1; + } else if (strcmp(name_b, "any-" TYPE_ARC_CPU) == 0) { + return -1; + } else { + return strcmp(name_a, name_b); + } +} + +static void arc_cpu_list_entry(gpointer data, gpointer user_data) +{ + ObjectClass *oc = data; + const char *typename; + char *name; + + typename = object_class_get_name(oc); + name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARC_CPU)); + qemu_printf(" %s\n", name); + g_free(name); +} + +void arc_cpu_list(void) +{ + GSList *list; + + list = object_class_get_list(TYPE_ARC_CPU, false); + list = g_slist_sort(list, arc_cpu_list_compare); + qemu_printf("Available CPUs:\n"); + g_slist_foreach(list, arc_cpu_list_entry, NULL); + g_slist_free(list); +} + +int arc_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf, + int len, bool is_write) +{ + return cpu_memory_rw_debug(cs, addr, buf, len, is_write); +} + +hwaddr arc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +{ + ARCCPU *cpu = ARC_CPU(cs); + CPUARCState *env = &cpu->env; + + return arc_mmu_translate(env, addr, MMU_MEM_IRRELEVANT_TYPE, + NULL); +} + +void helper_debug(CPUARCState *env) +{ + CPUState *cs = env_cpu(env); + + cs->exception_index = EXCP_DEBUG; + cpu_loop_exit(cs); +} + +/* + * raises a simple exception with causecode and parameter set to 0. + * it also considers "pc" as the exception return address. this is + * not true for a software trap. + * it is very important that "env->host_pc" holds the recent value, + * else the cpu_restore_state() will not be helpful and we end up + * with incorrect registers in env. + */ +void QEMU_NORETURN arc_raise_exception(CPUARCState *env, int32_t excp_idx) +{ + CPUState *cs = env_cpu(env); + cpu_restore_state(cs, env->host_pc, true); + cs->exception_index = excp_idx; + env->causecode = env->param = 0x0; + env->eret = env->pc; + env->erbta = env->bta; + cpu_loop_exit(cs); +} + + +/* vim: set ts=4 sw=4 et: */ diff --git a/target/arc/helper.h b/target/arc/helper.h new file mode 100644 index 0000000000..2a7e61a182 --- /dev/null +++ b/target/arc/helper.h @@ -0,0 +1,46 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synopsys Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * href="http://www.gnu.org/licenses/lgpl-2.1.html + */ + +DEF_HELPER_1(debug, void, env) +DEF_HELPER_2(norm, i32, env, i32) +DEF_HELPER_2(normh, i32, env, i32) +DEF_HELPER_2(ffs, i32, env, i32) +DEF_HELPER_2(fls, i32, env, i32) +DEF_HELPER_2(lr, tl, env, i32) +DEF_HELPER_3(sr, void, env, i32, i32) +DEF_HELPER_2(halt, noreturn, env, i32) +DEF_HELPER_1(rtie, void, env) +DEF_HELPER_1(flush, void, env) +DEF_HELPER_4(raise_exception, noreturn, env, i32, i32, i32) +DEF_HELPER_2(zol_verify, void, env, i32) +DEF_HELPER_2(fake_exception, void, env, i32) +DEF_HELPER_2(set_status32, void, env, i32) +DEF_HELPER_1(get_status32, i32, env) +DEF_HELPER_3(carry_add_flag, i32, i32, i32, i32) +DEF_HELPER_3(overflow_add_flag, i32, i32, i32, i32) +DEF_HELPER_3(overflow_sub_flag, i32, i32, i32, i32) + +DEF_HELPER_2(enter, void, env, i32) +DEF_HELPER_2(leave, void, env, i32) + +DEF_HELPER_3(mpymu, i32, env, i32, i32) +DEF_HELPER_3(mpym, i32, env, i32, i32) + +DEF_HELPER_3(repl_mask, i32, i32, i32, i32) diff --git a/target/arc/op_helper.c b/target/arc/op_helper.c new file mode 100644 index 0000000000..f24fd8c942 --- /dev/null +++ b/target/arc/op_helper.c @@ -0,0 +1,749 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synopsys Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "cpu.h" +#include "sysemu/runstate.h" +#include "exec/helper-proto.h" +#include "exec/cpu_ldst.h" +#include "exec/ioport.h" +#include "translate-all.h" +#include "target/arc/regs.h" +#include "mmu.h" +#include "hw/arc/cpudevs.h" +#include "qemu/main-loop.h" +#include "irq.h" +#include "sysemu/sysemu.h" + + +static target_ulong get_status32(CPUARCState *env) +{ + target_ulong value = pack_status32(&env->stat); + + /* TODO: Implement debug mode */ + if (env->stat.Uf == 1) { + value &= 0x00000f00; + } + + if (env->stopped) { + value |= BIT(0); + } + + return value; +} + +static void set_status32(CPUARCState *env, target_ulong value) +{ + /* TODO: Implement debug mode. */ + bool debug_mode = false; + if (env->stat.Uf == 1) { + value &= 0x00000f00; + } else if (!debug_mode) { + value &= 0xffff6f3f; + } + + if (((env->stat.Uf >> 7) & 0x1) != ((value >> 7) & 0x1)) { + tlb_flush(env_cpu(env)); + } + + unpack_status32(&env->stat, value); + + /* Implement HALT functionality. */ + if (value & 0x01) { + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + } +} + +static void do_exception_no_delayslot(CPUARCState *env, uint32_t index, + uint32_t causecode, uint32_t param) +{ + CPUState *cs = env_cpu(env); + cpu_restore_state(cs, GETPC(), true); + env->eret = env->pc; + env->erbta = env->bta; + + helper_raise_exception(env, index, causecode, param); +} + +target_ulong helper_norm(CPUARCState *env, uint32_t src1) +{ + int i; + int32_t tmp = (int32_t) src1; + if (tmp == 0 || tmp == -1) { + return 0; + } + for (i = 0; i <= 31; i++) { + if ((tmp >> i) == 0) { + break; + } + if ((tmp >> i) == -1) { + break; + } + } + return i; +} + +target_ulong helper_normh(CPUARCState *env, uint32_t src1) +{ + int i; + for (i = 0; i <= 15; i++) { + if (src1 >> i == 0) { + break; + } + if (src1 >> i == -1) { + break; + } + } + return i; +} + +target_ulong helper_ffs(CPUARCState *env, uint32_t src) +{ + int i; + if (src == 0) { + return 31; + } + for (i = 0; i <= 31; i++) { + if (((src >> i) & 1) != 0) { + break; + } + } + return i; +} + +target_ulong helper_fls(CPUARCState *env, uint32_t src) +{ + int i; + if (src == 0) { + return 0; + } + + for (i = 31; i >= 0; i--) { + if (((src >> i) & 1) != 0) { + break; + } + } + return i; +} + +static void report_aux_reg_error(uint32_t aux) +{ + if (((aux >= ARC_BCR1_START) && (aux <= ARC_BCR1_END)) || + ((aux >= ARC_BCR2_START) && (aux <= ARC_BCR2_END))) { + qemu_log_mask(LOG_UNIMP, "Undefined BCR 0x%03x\n", aux); + } + + error_report("Undefined AUX register 0x%03x, aborting", aux); + exit(EXIT_FAILURE); +} + +void helper_sr(CPUARCState *env, uint32_t val, uint32_t aux) +{ + struct arc_aux_reg_detail *aux_reg_detail = + arc_aux_reg_struct_for_address(aux, ARC_OPCODE_ARCv2HS); + + if (aux_reg_detail == NULL) { + report_aux_reg_error(aux); + } + + /* saving return address in case an exception must be raised later */ + env->host_pc = GETPC(); + + switch (aux_reg_detail->id) { + case AUX_ID_lp_start: + env->lps = val; + break; + + case AUX_ID_lp_end: + env->lpe = val; + break; + + case AUX_ID_status32: + set_status32(env, val); + break; + + case AUX_ID_eret: + env->eret = val; + break; + + case AUX_ID_erbta: + env->erbta = val; + break; + + case AUX_ID_bta: + env->bta = val; + break; + + case AUX_ID_erstatus: + unpack_status32(&env->stat_er, val); + break; + + case AUX_ID_ecr: + env->ecr = val; + break; + + case AUX_ID_efa: + env->efa = val; + break; + + default: + if (aux_reg_detail->aux_reg->set_func != NULL) { + aux_reg_detail->aux_reg->set_func(aux_reg_detail, val, + (void *) env); + } else { + /* setting a register that does not provide one is not allowed */ + arc_raise_exception(env, EXCP_INST_ERROR); + /* TODO: are lr and sr possible delayslot instructions ? */ + /* TODO: what is this? can it be removed? */ + do_exception_no_delayslot(env, EXCP_INST_ERROR, 0, 0); + } + break; + } + cpu_outl(aux, val); +} + +static target_ulong get_debug(CPUARCState *env) +{ + target_ulong res = 0x00000000; + + res |= (env->debug.LD) ? BIT(31) : 0; + res |= (env->debug.SH) ? BIT(30) : 0; + res |= (env->debug.BH) ? BIT(29) : 0; + res |= (env->debug.UB) ? BIT(28) : 0; + res |= (env->debug.ZZ) ? BIT(27) : 0; + res |= (env->debug.RA) ? BIT(22) : 0; + res |= (env->debug.IS) ? BIT(11) : 0; + res |= (env->debug.FH) ? BIT(1) : 0; + res |= (env->debug.SS) ? BIT(0) : 0; + + return res; +} + +static target_ulong get_identity(CPUARCState *env) +{ + target_ulong chipid = 0xffff, arcnum = 0, arcver, res; + + switch (env->family) { + case ARC_OPCODE_ARC700: + arcver = 0x34; + break; + + case ARC_OPCODE_ARCv2EM: + arcver = 0x44; + break; + + case ARC_OPCODE_ARCv2HS: + arcver = 0x54; + break; + + default: + arcver = 0; + + } + + /* TODO: in SMP, arcnum depends on the cpu instance. */ + res = ((chipid & 0xFFFF) << 16) | ((arcnum & 0xFF) << 8) | (arcver & 0xFF); + return res; +} + +target_ulong helper_lr(CPUARCState *env, uint32_t aux) +{ + target_ulong result = 0; + + struct arc_aux_reg_detail *aux_reg_detail = + arc_aux_reg_struct_for_address(aux, ARC_OPCODE_ARCv2HS); + + if (aux_reg_detail == NULL) { + report_aux_reg_error(aux); + } + + /* saving return address in case an exception must be raised later */ + env->host_pc = GETPC(); + + switch (aux_reg_detail->id) { + case AUX_ID_aux_volatile: + result = 0xc0000000; + break; + + case AUX_ID_lp_start: + result = env->lps; + break; + + case AUX_ID_lp_end: + result = env->lpe; + break; + + case AUX_ID_identity: + result = get_identity(env); + break; + + case AUX_ID_exec_ctrl: + result = 0; + break; + + case AUX_ID_debug: + result = get_debug(env); + break; + + case AUX_ID_pc: + result = env->pc & 0xfffffffe; + break; + + case AUX_ID_status32: + result = get_status32(env); + break; + + case AUX_ID_mpy_build: + result = env->mpy_build; + break; + + case AUX_ID_isa_config: + result = env->isa_config; + break; + + case AUX_ID_eret: + result = env->eret; + break; + + case AUX_ID_erbta: + result = env->erbta; + break; + + case AUX_ID_erstatus: + if (is_user_mode(env)) { + arc_raise_exception(env, EXCP_PRIVILEGEV); + } + result = pack_status32(&env->stat_er); + break; + + case AUX_ID_ecr: + result = env->ecr; + break; + + case AUX_ID_efa: + result = env->efa; + break; + + case AUX_ID_bta: + result = env->bta; + break; + + case AUX_ID_bta_l1: + result = env->bta_l1; + break; + + case AUX_ID_bta_l2: + result = env->bta_l2; + break; + + default: + if (aux_reg_detail->aux_reg->get_func != NULL) { + result = aux_reg_detail->aux_reg->get_func(aux_reg_detail, + (void *) env); + } else { + /* TODO: is lr and sr possible delayslot instructions ? */ + assert(0); + arc_raise_exception(env, EXCP_INST_ERROR); + do_exception_no_delayslot(env, EXCP_INST_ERROR, 0, 0); + } + break; + } + + return result; +} + +void QEMU_NORETURN helper_halt(CPUARCState *env, uint32_t npc) +{ + CPUState *cs = env_cpu(env); + if (env->stat.Uf) { + cs->exception_index = EXCP_PRIVILEGEV; + env->causecode = 0; + env->param = 0; + /* Restore PC such that we point at the faulty instruction. */ + env->eret = env->pc; + } else { + env->pc = npc; + cs->halted = 1; + cs->exception_index = EXCP_HLT; + } + cpu_loop_exit(cs); +} + +void helper_rtie(CPUARCState *env) +{ + CPUState *cs = env_cpu(env); + if (env->stat.Uf) { + cs->exception_index = EXCP_PRIVILEGEV; + env->causecode = 0; + env->param = 0; + /* Restore PC such that we point at the faulty instruction. */ + env->eret = env->pc; + cpu_loop_exit(cs); + return; + } + + if (env->stat.AEf || (env->aux_irq_act & 0xFFFF) == 0) { + assert(env->stat.Uf == 0); + + CPU_PCL(env) = env->eret; + env->pc = env->eret; + + env->stat = env->stat_er; + env->bta = env->erbta; + + /* If returning to userland, restore SP. */ + if (env->stat.Uf) { + switchSP(env); + } + + qemu_log_mask(CPU_LOG_INT, "[EXCP] RTIE @0x%08x ECR:0x%08x\n", + env->r[63], env->ecr); + } else { + arc_rtie_interrupts(env); + qemu_log_mask(CPU_LOG_INT, "[IRQ] RTIE @0x%08x STATUS32:0x%08x\n", + env->r[63], pack_status32(&env->stat)); + } + + helper_zol_verify(env, env->pc); +} + +void helper_flush(CPUARCState *env) +{ + tb_flush((CPUState *)env_archcpu(env)); +} + +/* + * This should only be called from translate, via gen_raise_exception. + * We expect that ENV->PC has already been updated. + */ + +void QEMU_NORETURN helper_raise_exception(CPUARCState *env, + uint32_t index, + uint32_t causecode, + uint32_t param) +{ + CPUState *cs = env_cpu(env); + /* Cannot restore state here. */ + /* cpu_restore_state(cs, GETPC(), true); */ + cs->exception_index = index; + env->causecode = causecode; + env->param = param; + cpu_loop_exit(cs); +} + +void helper_zol_verify(CPUARCState *env, uint32_t npc) +{ + if (npc == env->lpe) { + if (env->r[60] > 1) { + env->r[60] -= 1; + helper_raise_exception(env, (uint32_t) EXCP_LPEND_REACHED, 0, + env->lps); + } else { + env->r[60] = 0; + } + } +} +void helper_fake_exception(CPUARCState *env, uint32_t pc) +{ + helper_raise_exception(env, (uint32_t) EXCP_FAKE, 0, pc); +} + +uint32_t helper_get_status32(CPUARCState *env) +{ + return get_status32(env); +} + +void helper_set_status32(CPUARCState *env, uint32_t value) +{ + set_status32(env, value); +} + +uint32_t helper_carry_add_flag(uint32_t dest, uint32_t b, uint32_t c) +{ + uint32_t t1, t2, t3; + + t1 = b & c; + t2 = b & (~dest); + t3 = c & (~dest); + t1 = t1 | t2 | t3; + return (t1 >> 31) & 1; +} + +uint32_t helper_overflow_add_flag(uint32_t dest, uint32_t b, uint32_t c) +{ + dest >>= 31; + b >>= 31; + c >>= 31; + if ((dest == 0 && b == 1 && c == 1) + || (dest == 1 && b == 0 && c == 0)) { + return 1; + } else { + return 0; + } +} + +uint32_t helper_overflow_sub_flag(uint32_t dest, uint32_t b, uint32_t c) +{ + dest >>= 31; + b >>= 31; + c >>= 31; + if ((dest == 1 && b == 0 && c == 1) + || (dest == 0 && b == 1 && c == 0)) { + return 1; + } else { + return 0; + } +} + +uint32_t helper_repl_mask(uint32_t dest, uint32_t src, uint32_t mask) +{ + uint32_t ret = dest & (~mask); + ret |= (src & mask); + + return ret; +} + +uint32_t helper_mpymu(CPUARCState *env, uint32_t b, uint32_t c) +{ + uint64_t _b = (uint64_t) b; + uint64_t _c = (uint64_t) c; + + return (uint32_t) ((_b * _c) >> 32); +} + +uint32_t helper_mpym(CPUARCState *env, uint32_t b, uint32_t c) +{ + int64_t _b = (int64_t) ((int32_t) b); + int64_t _c = (int64_t) ((int32_t) c); + + /* + * fprintf(stderr, "B = 0x%llx, C = 0x%llx, result = 0x%llx\n", + * _b, _c, _b * _c); + */ + return (_b * _c) >> 32; +} + + +/* + * throw "illegal instruction" exception if more than available + * registers are asked to be saved/restore. + */ +static void check_enter_leave_nr_regs(CPUARCState *env, + uint8_t regs, + uintptr_t host_pc) +{ + const uint8_t rgf_num_regs = env_archcpu(env)->cfg.rgf_num_regs; + if ((rgf_num_regs == 32 && regs > 14) || + (rgf_num_regs == 16 && regs > 3)) { + CPUState *cs = env_cpu(env); + cpu_restore_state(cs, host_pc, true); + cs->exception_index = EXCP_INST_ERROR; + env->causecode = 0x00; + env->param = 0x00; + env->eret = env->pc; + env->erbta = env->bta; + cpu_loop_exit(cs); + } +} + +/* + * throw "illegal instruction sequence" exception if we are in a + * delay/execution slot. + */ +static void check_delay_or_execution_slot(CPUARCState *env, + uintptr_t host_pc) +{ + if (env->stat.DEf || env->stat.ESf) { + CPUState *cs = env_cpu(env); + cpu_restore_state(cs, host_pc, true); + cs->exception_index = EXCP_INST_ERROR; + env->causecode = 0x01; + env->param = 0x00; + env->eret = env->pc; + env->erbta = env->bta; + cpu_loop_exit(cs); + } +} + +/* + * Throw "misaligned" exception if 'addr' is not 32-bit aligned. + * This check is done irrelevant of status32.AD bit. + */ +static void check_addr_is_word_aligned(CPUARCState *env, + target_ulong addr, + uintptr_t host_pc) +{ + if (addr & 0x3) { + CPUState *cs = env_cpu(env); + cpu_restore_state(cs, host_pc, true); + cs->exception_index = EXCP_MISALIGNED; + env->causecode = 0x00; + env->param = 0x00; + env->efa = addr; + env->eret = env->pc; + env->erbta = env->bta; + cpu_loop_exit(cs); + } +} + +/* + * helper for enter_s instruction. + * after we are done, stack layout would be: + * ,- top -. + * | blink | + * | r13 | + * | r14 | + * | ... | + * | r26 | + * | fp | + * `-------' + */ +void helper_enter(CPUARCState *env, uint32_t u6) +{ + /* nothing to do? then bye-bye! */ + if (!u6) { + return; + } + + uint8_t regs = u6 & 0x0f; /* u[3:0] determines registers to save */ + bool save_fp = u6 & 0x10; /* u[4] indicates if fp must be saved */ + bool save_blink = u6 & 0x20; /* u[5] indicates saving of blink */ + uint8_t stack_size = 4 * (regs + save_fp + save_blink); + + /* number of regs to be saved must be sane */ + check_enter_leave_nr_regs(env, regs, GETPC()); + + /* this cannot be executed in a delay/execution slot */ + check_delay_or_execution_slot(env, GETPC()); + + /* stack must be a multiple of 4 (32 bit aligned) */ + check_addr_is_word_aligned(env, CPU_SP(env) - stack_size, GETPC()); + + uint32_t tmp_sp = CPU_SP(env); + + if (save_fp) { + tmp_sp -= 4; + cpu_stl_data(env, tmp_sp, CPU_FP(env)); + } + + for (uint8_t gpr = regs; gpr >= 1; --gpr) { + tmp_sp -= 4; + cpu_stl_data(env, tmp_sp, env->r[13 + gpr - 1]); + } + + if (save_blink) { + tmp_sp -= 4; + cpu_stl_data(env, tmp_sp, CPU_BLINK(env)); + } + + CPU_SP(env) = tmp_sp; + + /* now that sp has been allocated, shall we write it to fp? */ + if (save_fp) { + CPU_FP(env) = CPU_SP(env); + } +} + +/* + * helper for leave_s instruction. + * a stack layout of below is assumed: + * ,- top -. + * | blink | + * | r13 | + * | r14 | + * | ... | + * | r26 | + * | fp | + * `-------' + */ +void helper_leave(CPUARCState *env, uint32_t u7) +{ + /* nothing to do? then bye-bye! */ + if (!u7) { + return; + } + + uint8_t regs = u7 & 0x0f; /* u[3:0] determines registers to save */ + bool restore_fp = u7 & 0x10; /* u[4] indicates if fp must be saved */ + bool restore_blink = u7 & 0x20; /* u[5] indicates saving of blink */ + bool jump_to_blink = u7 & 0x40; /* u[6] should we jump to blink? */ + + /* number of regs to be restored must be sane */ + check_enter_leave_nr_regs(env, regs, GETPC()); + + /* this cannot be executed in a delay/execution slot */ + check_delay_or_execution_slot(env, GETPC()); + + /* + * stack must be a multiple of 4 (32 bit aligned). we must take into + * account if sp is going to use fp's value or not. + */ + const target_ulong addr = restore_fp ? CPU_FP(env) : CPU_SP(env); + check_addr_is_word_aligned(env, addr, GETPC()); + + /* + * if fp is in the picture, then first we have to use the current + * fp as the stack pointer for restoring. + */ + if (restore_fp) { + CPU_SP(env) = CPU_FP(env); + } + + uint32_t tmp_sp = CPU_SP(env); + + if (restore_blink) { + CPU_BLINK(env) = cpu_ldl_data(env, tmp_sp); + tmp_sp += 4; + } + + for (uint8_t gpr = 0; gpr < regs; ++gpr) { + env->r[13 + gpr] = cpu_ldl_data(env, tmp_sp); + tmp_sp += 4; + } + + if (restore_fp) { + CPU_FP(env) = cpu_ldl_data(env, tmp_sp); + tmp_sp += 4; + } + + CPU_SP(env) = tmp_sp; + + /* now that we are done, should we jump to blink? */ + if (jump_to_blink) { + CPU_PCL(env) = CPU_BLINK(env); + env->pc = CPU_BLINK(env); + } +} + +/* + * uint32_t lf_variable = 0; + * uint32_t helper_get_lf(void) + * { + * return lf_variable; + * } + * void helper_set_lf(uint32_t v) + * { + * lf_variable = v; + * } + */ + +/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ +/* vim: set ts=4 sw=4 et: */ diff --git a/target/arc/semfunc_mapping.def b/target/arc/semfunc_mapping.def new file mode 100644 index 0000000000..b47edb42e5 --- /dev/null +++ b/target/arc/semfunc_mapping.def @@ -0,0 +1,329 @@ +/* + * QEMU ARC SEMANTIC MAPPING. + * + * Copyright (c) 2020 Synopsys, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +SEMANTIC_FUNCTION(FLAG, 1) +SEMANTIC_FUNCTION(KFLAG, 1) +SEMANTIC_FUNCTION(ADD, 3) +SEMANTIC_FUNCTION(ADD1, 3) +SEMANTIC_FUNCTION(ADD2, 3) +SEMANTIC_FUNCTION(ADD3, 3) +SEMANTIC_FUNCTION(ADC, 3) +SEMANTIC_FUNCTION(SBC, 3) +SEMANTIC_FUNCTION(NEG, 2) +SEMANTIC_FUNCTION(SUB, 3) +SEMANTIC_FUNCTION(SUB1, 3) +SEMANTIC_FUNCTION(SUB2, 3) +SEMANTIC_FUNCTION(SUB3, 3) +SEMANTIC_FUNCTION(MAX, 3) +SEMANTIC_FUNCTION(MIN, 3) +SEMANTIC_FUNCTION(CMP, 2) +SEMANTIC_FUNCTION(AND, 3) +SEMANTIC_FUNCTION(OR, 3) +SEMANTIC_FUNCTION(XOR, 3) +SEMANTIC_FUNCTION(MOV, 2) +SEMANTIC_FUNCTION(ASL, 3) +SEMANTIC_FUNCTION(ASR, 3) +SEMANTIC_FUNCTION(ASR8, 2) +SEMANTIC_FUNCTION(ASR16, 2) +SEMANTIC_FUNCTION(LSL16, 2) +SEMANTIC_FUNCTION(LSL8, 2) +SEMANTIC_FUNCTION(LSR, 3) +SEMANTIC_FUNCTION(LSR16, 2) +SEMANTIC_FUNCTION(LSR8, 2) +SEMANTIC_FUNCTION(BIC, 3) +SEMANTIC_FUNCTION(BCLR, 3) +SEMANTIC_FUNCTION(BMSK, 3) +SEMANTIC_FUNCTION(BMSKN, 3) +SEMANTIC_FUNCTION(BSET, 3) +SEMANTIC_FUNCTION(BXOR, 3) +SEMANTIC_FUNCTION(ROL, 2) +SEMANTIC_FUNCTION(ROL8, 2) +SEMANTIC_FUNCTION(ROR, 3) +SEMANTIC_FUNCTION(ROR8, 2) +SEMANTIC_FUNCTION(RLC, 2) +SEMANTIC_FUNCTION(RRC, 2) +SEMANTIC_FUNCTION(SEXB, 2) +SEMANTIC_FUNCTION(SEXH, 2) +SEMANTIC_FUNCTION(EXTB, 2) +SEMANTIC_FUNCTION(EXTH, 2) +SEMANTIC_FUNCTION(BTST, 2) +SEMANTIC_FUNCTION(TST, 2) +SEMANTIC_FUNCTION(XBFU, 3) +SEMANTIC_FUNCTION(AEX, 2) +SEMANTIC_FUNCTION(LR, 2) +SEMANTIC_FUNCTION(SR, 2) +SEMANTIC_FUNCTION(SYNC, 0) +SEMANTIC_FUNCTION(CLRI, 1) +SEMANTIC_FUNCTION(SETI, 1) +SEMANTIC_FUNCTION(NOP, 0) +SEMANTIC_FUNCTION(PREALLOC, 0) +SEMANTIC_FUNCTION(PREFETCH, 2) +SEMANTIC_FUNCTION(MPY, 3) +SEMANTIC_FUNCTION(MPYMU, 3) +SEMANTIC_FUNCTION(MPYM, 3) +SEMANTIC_FUNCTION(MPYU, 3) +SEMANTIC_FUNCTION(MPYUW, 3) +SEMANTIC_FUNCTION(MPYW, 3) +SEMANTIC_FUNCTION(DIV, 3) +SEMANTIC_FUNCTION(DIVU, 3) +SEMANTIC_FUNCTION(REM, 3) +SEMANTIC_FUNCTION(REMU, 3) +SEMANTIC_FUNCTION(MAC, 3) +SEMANTIC_FUNCTION(MACU, 3) +SEMANTIC_FUNCTION(MACD, 3) +SEMANTIC_FUNCTION(MACDU, 3) +SEMANTIC_FUNCTION(ABS, 2) +SEMANTIC_FUNCTION(SWAP, 2) +SEMANTIC_FUNCTION(SWAPE, 2) +SEMANTIC_FUNCTION(NOT, 2) +SEMANTIC_FUNCTION(BI, 1) +SEMANTIC_FUNCTION(BIH, 1) +SEMANTIC_FUNCTION(B, 1) +SEMANTIC_FUNCTION(B_S, 1) +SEMANTIC_FUNCTION(BBIT0, 3) +SEMANTIC_FUNCTION(BBIT1, 3) +SEMANTIC_FUNCTION(BL, 1) +SEMANTIC_FUNCTION(J, 1) +SEMANTIC_FUNCTION(JL, 1) +SEMANTIC_FUNCTION(SETEQ, 3) +SEMANTIC_FUNCTION(BREQ, 3) +SEMANTIC_FUNCTION(SETNE, 3) +SEMANTIC_FUNCTION(BRNE, 3) +SEMANTIC_FUNCTION(SETLT, 3) +SEMANTIC_FUNCTION(BRLT, 3) +SEMANTIC_FUNCTION(SETGE, 3) +SEMANTIC_FUNCTION(BRGE, 3) +SEMANTIC_FUNCTION(SETLE, 3) +SEMANTIC_FUNCTION(SETGT, 3) +SEMANTIC_FUNCTION(BRLO, 3) +SEMANTIC_FUNCTION(SETLO, 3) +SEMANTIC_FUNCTION(BRHS, 3) +SEMANTIC_FUNCTION(SETHS, 3) +SEMANTIC_FUNCTION(EX, 2) +SEMANTIC_FUNCTION(LLOCK, 2) +SEMANTIC_FUNCTION(LLOCKD, 2) +SEMANTIC_FUNCTION(SCOND, 2) +SEMANTIC_FUNCTION(SCONDD, 2) +SEMANTIC_FUNCTION(DMB, 1) +SEMANTIC_FUNCTION(LD, 3) +SEMANTIC_FUNCTION(LDD, 3) +SEMANTIC_FUNCTION(ST, 3) +SEMANTIC_FUNCTION(STD, 3) +SEMANTIC_FUNCTION(ENTER_S, 1) +SEMANTIC_FUNCTION(LEAVE_S, 1) +SEMANTIC_FUNCTION(POP, 1) +SEMANTIC_FUNCTION(PUSH, 1) +SEMANTIC_FUNCTION(LP, 1) +SEMANTIC_FUNCTION(NORM, 2) +SEMANTIC_FUNCTION(NORMH, 2) +SEMANTIC_FUNCTION(FLS, 2) +SEMANTIC_FUNCTION(FFS, 2) + + +MAPPING(flag, FLAG, 1, 0) +MAPPING(kflag, KFLAG, 1, 0) +MAPPING(add, ADD, 3, 1, 2, 0) +MAPPING(add_s, ADD, 3, 1, 2, 0) +MAPPING(add1, ADD1, 3, 1, 2, 0) +MAPPING(add1_s, ADD1, 3, 1, 2, 0) +MAPPING(add2, ADD2, 3, 1, 2, 0) +MAPPING(add2_s, ADD2, 3, 1, 2, 0) +MAPPING(add3, ADD3, 3, 1, 2, 0) +MAPPING(add3_s, ADD3, 3, 1, 2, 0) +MAPPING(adc, ADC, 3, 1, 2, 0) +MAPPING(sbc, SBC, 3, 1, 2, 0) +MAPPING(neg, NEG, 2, 1, 0) +MAPPING(neg_s, NEG, 2, 1, 0) +MAPPING(sub, SUB, 3, 1, 2, 0) +MAPPING(sub_s, SUB, 3, 1, 2, 0) +MAPPING(rsub, SUB, 3, 2, 1, 0) +MAPPING(sub1, SUB1, 3, 1, 2, 0) +MAPPING(sub2, SUB2, 3, 1, 2, 0) +MAPPING(sub3, SUB3, 3, 1, 2, 0) +MAPPING(max, MAX, 3, 1, 2, 0) +MAPPING(min, MIN, 3, 1, 2, 0) +MAPPING(cmp, CMP, 2, 0, 1) +MAPPING(cmp_s, CMP, 2, 0, 1) +MAPPING(rcmp, CMP, 2, 1, 0) +MAPPING(and, AND, 3, 1, 2, 0) +MAPPING(and_s, AND, 3, 1, 2, 0) +MAPPING(or, OR, 3, 1, 2, 0) +MAPPING(or_s, OR, 3, 1, 2, 0) +MAPPING(xor, XOR, 3, 1, 2, 0) +MAPPING(xor_s, XOR, 3, 1, 2, 0) +MAPPING(mov, MOV, 2, 1, 0) +MAPPING(mov_s, MOV, 2, 1, 0) +CONSTANT(ASL, asl, 2, 268435457) /* For variable @c */ +MAPPING(asl, ASL, 3, 1, 2, 0) +CONSTANT(ASL, asl_s, 2, 268435457) /* For variable @c */ +MAPPING(asl_s, ASL, 3, 1, 2, 0) +CONSTANT(ASR, asr, 2, 1) /* For variable @c */ +MAPPING(asr, ASR, 3, 1, 2, 0) +CONSTANT(ASR, asr_s, 2, 1) /* For variable @c */ +MAPPING(asr_s, ASR, 3, 1, 2, 0) +MAPPING(asr8, ASR8, 2, 1, 0) +MAPPING(asr16, ASR16, 2, 1, 0) +MAPPING(lsl16, LSL16, 2, 1, 0) +MAPPING(lsl8, LSL8, 2, 1, 0) +CONSTANT(LSR, lsr, 2, 1) /* For variable @c */ +MAPPING(lsr, LSR, 3, 1, 2, 0) +CONSTANT(LSR, lsr_s, 2, 1) /* For variable @c */ +MAPPING(lsr_s, LSR, 3, 1, 2, 0) +MAPPING(lsr16, LSR16, 2, 1, 0) +MAPPING(lsr8, LSR8, 2, 1, 0) +MAPPING(bic, BIC, 3, 1, 2, 0) +MAPPING(bic_s, BIC, 3, 1, 2, 0) +MAPPING(bclr, BCLR, 3, 2, 1, 0) +MAPPING(bclr_s, BCLR, 3, 2, 1, 0) +MAPPING(bmsk, BMSK, 3, 2, 1, 0) +MAPPING(bmsk_s, BMSK, 3, 2, 1, 0) +MAPPING(bmskn, BMSKN, 3, 2, 1, 0) +MAPPING(bset, BSET, 3, 2, 1, 0) +MAPPING(bset_s, BSET, 3, 2, 1, 0) +MAPPING(bxor, BXOR, 3, 2, 1, 0) +MAPPING(rol, ROL, 2, 1, 0) +MAPPING(rol8, ROL8, 2, 1, 0) +CONSTANT(ROR, ror, 2, 1) /* For variable @n */ +MAPPING(ror, ROR, 3, 1, 2, 0) +MAPPING(ror8, ROR8, 2, 1, 0) +MAPPING(rlc, RLC, 2, 1, 0) +MAPPING(rrc, RRC, 2, 1, 0) +MAPPING(sexb, SEXB, 2, 0, 1) +MAPPING(sexb_s, SEXB, 2, 0, 1) +MAPPING(sexh, SEXH, 2, 0, 1) +MAPPING(sexh_s, SEXH, 2, 0, 1) +MAPPING(extb, EXTB, 2, 0, 1) +MAPPING(extb_s, EXTB, 2, 0, 1) +MAPPING(exth, EXTH, 2, 0, 1) +MAPPING(exth_s, EXTH, 2, 0, 1) +MAPPING(btst, BTST, 2, 1, 0) +MAPPING(btst_s, BTST, 2, 1, 0) +MAPPING(tst, TST, 2, 0, 1) +MAPPING(tst_s, TST, 2, 0, 1) +MAPPING(xbfu, XBFU, 3, 2, 1, 0) +MAPPING(aex, AEX, 2, 1, 0) +MAPPING(lr, LR, 2, 0, 1) +MAPPING(sr, SR, 2, 1, 0) +MAPPING(sync, SYNC, 0) +MAPPING(clri, CLRI, 1, 0) +MAPPING(seti, SETI, 1, 0) +MAPPING(nop, NOP, 0) +MAPPING(nop_s, NOP, 0) +MAPPING(prealloc, PREALLOC, 0) +CONSTANT(PREFETCH, prefetch, 1, 0) /* For variable @src2 */ +MAPPING(prefetch, PREFETCH, 2, 0, 1) +CONSTANT(PREFETCH, prefetchw, 1, 0) /* For variable @src2 */ +MAPPING(prefetchw, PREFETCH, 2, 0, 1) +MAPPING(mpy, MPY, 3, 1, 2, 0) +MAPPING(mpy_s, MPY, 3, 1, 2, 0) +MAPPING(mpymu, MPYMU, 3, 0, 1, 2) +MAPPING(mpym, MPYM, 3, 0, 1, 2) +MAPPING(mpyu, MPYU, 3, 1, 2, 0) +MAPPING(mpyuw, MPYUW, 3, 0, 1, 2) +MAPPING(mpyuw_s, MPYUW, 3, 0, 1, 2) +MAPPING(mpyw, MPYW, 3, 0, 1, 2) +MAPPING(mpyw_s, MPYW, 3, 0, 1, 2) +MAPPING(div, DIV, 3, 2, 1, 0) +MAPPING(divu, DIVU, 3, 2, 0, 1) +MAPPING(rem, REM, 3, 2, 1, 0) +MAPPING(remu, REMU, 3, 2, 0, 1) +MAPPING(mac, MAC, 3, 1, 2, 0) +MAPPING(macu, MACU, 3, 1, 2, 0) +MAPPING(macd, MACD, 3, 1, 2, 0) +MAPPING(macdu, MACDU, 3, 1, 2, 0) +MAPPING(abs, ABS, 2, 1, 0) +MAPPING(abs_s, ABS, 2, 1, 0) +MAPPING(swap, SWAP, 2, 1, 0) +MAPPING(swape, SWAPE, 2, 1, 0) +MAPPING(not, NOT, 2, 0, 1) +MAPPING(not_s, NOT, 2, 0, 1) +MAPPING(bi, BI, 1, 0) +MAPPING(bih, BIH, 1, 0) +MAPPING(b, B, 1, 0) +MAPPING(beq_s, B_S, 1, 0) +MAPPING(bne_s, B_S, 1, 0) +MAPPING(bgt_s, B_S, 1, 0) +MAPPING(bge_s, B_S, 1, 0) +MAPPING(blt_s, B_S, 1, 0) +MAPPING(ble_s, B_S, 1, 0) +MAPPING(bhi_s, B_S, 1, 0) +MAPPING(bhs_s, B_S, 1, 0) +MAPPING(blo_s, B_S, 1, 0) +MAPPING(bls_s, B_S, 1, 0) +MAPPING(b_s, B_S, 1, 0) +MAPPING(bbit0, BBIT0, 3, 0, 1, 2) +MAPPING(bbit1, BBIT1, 3, 0, 1, 2) +MAPPING(bl, BL, 1, 0) +MAPPING(bl_s, BL, 1, 0) +MAPPING(j, J, 1, 0) +MAPPING(j_s, J, 1, 0) +MAPPING(jeq_s, J, 1, 0) +MAPPING(jne_s, J, 1, 0) +MAPPING(jl, JL, 1, 0) +MAPPING(jl_s, JL, 1, 0) +MAPPING(seteq, SETEQ, 3, 1, 2, 0) +MAPPING(breq, BREQ, 3, 0, 1, 2) +MAPPING(breq_s, BREQ, 3, 0, 1, 2) +MAPPING(setne, SETNE, 3, 1, 2, 0) +MAPPING(brne, BRNE, 3, 0, 1, 2) +MAPPING(brne_s, BRNE, 3, 0, 1, 2) +MAPPING(setlt, SETLT, 3, 1, 2, 0) +MAPPING(brlt, BRLT, 3, 0, 1, 2) +MAPPING(setge, SETGE, 3, 1, 2, 0) +MAPPING(brge, BRGE, 3, 0, 1, 2) +MAPPING(setle, SETLE, 3, 1, 2, 0) +MAPPING(setgt, SETGT, 3, 1, 2, 0) +MAPPING(brlo, BRLO, 3, 0, 1, 2) +MAPPING(setlo, SETLO, 3, 1, 2, 0) +MAPPING(brhs, BRHS, 3, 0, 1, 2) +MAPPING(seths, SETHS, 3, 1, 2, 0) +MAPPING(ex, EX, 2, 0, 1) +MAPPING(llock, LLOCK, 2, 0, 1) +MAPPING(llockd, LLOCKD, 2, 0, 1) +MAPPING(scond, SCOND, 2, 1, 0) +MAPPING(scondd, SCONDD, 2, 1, 0) +MAPPING(dmb, DMB, 1, 0) +CONSTANT(LD, ld, 2, 0) /* For variable @src2 */ +MAPPING(ld, LD, 3, 1, 2, 0) +MAPPING(ld_s, LD, 3, 1, 2, 0) +MAPPING(ldb_s, LD, 3, 1, 2, 0) +MAPPING(ldh_s, LD, 3, 1, 2, 0) +MAPPING(ldw_s, LD, 3, 1, 2, 0) +CONSTANT(LD, ldi, 2, 0) /* For variable @src2 */ +MAPPING(ldi, LD, 3, 1, 2, 0) +CONSTANT(LD, ldi_s, 2, 0) /* For variable @src2 */ +MAPPING(ldi_s, LD, 3, 1, 2, 0) +CONSTANT(LDD, ldd, 2, 0) /* For variable @src2 */ +MAPPING(ldd, LDD, 3, 1, 2, 0) +CONSTANT(ST, st, 2, 0) /* For variable @src2 */ +MAPPING(st, ST, 3, 1, 2, 0) +MAPPING(st_s, ST, 3, 1, 2, 0) +MAPPING(stb_s, ST, 3, 1, 2, 0) +MAPPING(sth_s, ST, 3, 1, 2, 0) +MAPPING(stw_s, ST, 3, 1, 2, 0) +CONSTANT(STD, std, 2, 0) /* For variable @src2 */ +MAPPING(std, STD, 3, 1, 2, 0) +MAPPING(enter_s, ENTER_S, 1, 0) +MAPPING(leave_s, LEAVE_S, 1, 0) +MAPPING(pop_s, POP, 1, 0) +MAPPING(push_s, PUSH, 1, 0) +MAPPING(lp, LP, 1, 0) +MAPPING(norm, NORM, 2, 1, 0) +MAPPING(normh, NORMH, 2, 1, 0) +MAPPING(fls, FLS, 2, 1, 0) +MAPPING(ffs, FFS, 2, 1, 0) From patchwork Wed Nov 11 16:17:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cupertino Miranda X-Patchwork-Id: 1398389 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2001:8b0:10b:1231::1; helo=merlin.infradead.org; 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[2.80.104.46]) by smtp.gmail.com with ESMTPSA id s188sm3115178wmf.45.2020.11.11.08.18.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2020 08:18:10 -0800 (PST) From: cupertinomiranda@gmail.com To: qemu-devel@nongnu.org Subject: [PATCH 05/15] arc: TCG instruction generator and hand-definitions Date: Wed, 11 Nov 2020 16:17:48 +0000 Message-Id: <20201111161758.9636-6-cupertinomiranda@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201111161758.9636-1-cupertinomiranda@gmail.com> References: <20201111161758.9636-1-cupertinomiranda@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201111_111814_237258_D8B9A2C1 X-CRM114-Status: GOOD ( 25.88 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:335 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [cupertinomiranda[at]gmail.com] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Claudiu Zissulescu , Cupertino Miranda , Shahab Vahedi , Shahab Vahedi , Cupertino Miranda , linux-snps-arc@lists.infradead.org, Claudiu Zissulescu Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Cupertino Miranda Add the most generic parts of TCG constructions. It contains the basic infrastructure for fundamental ARC features, such as ZOL (zero overhead loops) and delay-slots. Also includes hand crafted TCG for more intricate instructions, such as vector instructions. Signed-off-by: Shahab Vahedi --- target/arc/translate.c | 1345 ++++++++++++++++++++++++++++++++++++++++ target/arc/translate.h | 201 ++++++ 2 files changed, 1546 insertions(+) create mode 100644 target/arc/translate.c create mode 100644 target/arc/translate.h diff --git a/target/arc/translate.c b/target/arc/translate.c new file mode 100644 index 0000000000..9034d05821 --- /dev/null +++ b/target/arc/translate.c @@ -0,0 +1,1345 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synppsys Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#include "qemu/osdep.h" +#include "translate.h" +#include "qemu/qemu-print.h" +#include "tcg/tcg-op-gvec.h" +#include "target/arc/semfunc.h" +#include "target/arc/arc-common.h" + +/* Globals */ +TCGv cpu_gp; /* Global Pointer */ +TCGv cpu_fp; /* Frame Pointer */ +TCGv cpu_sp; /* Stack Pointer */ +TCGv cpu_ilink1; /* Level 1 interrupt link register */ +TCGv cpu_ilink2; /* Level 2 interrupt link register */ +TCGv cpu_blink; /* Branch link register */ +TCGv cpu_acclo; /* 64-bit accumulator register: low */ +TCGv cpu_acchi; /* 64-bit accumulator register: high */ +TCGv cpu_limm; /* Long immediate data indicator */ +TCGv cpu_pcl; /* Program Counter [31:2], read-only. */ + +TCGv cpu_S1f; +TCGv cpu_S2f; +TCGv cpu_CSf; + +TCGv cpu_Lf; +TCGv cpu_Zf; +TCGv cpu_Nf; +TCGv cpu_Cf; +TCGv cpu_Vf; +TCGv cpu_Uf; + +TCGv cpu_DEf; +TCGv cpu_ESf; +TCGv cpu_AEf; +TCGv cpu_Hf; +TCGv cpu_IEf; +TCGv cpu_Ef; + +TCGv cpu_is_delay_slot_instruction; + +TCGv cpu_l1_Lf; +TCGv cpu_l1_Zf; +TCGv cpu_l1_Nf; +TCGv cpu_l1_Cf; +TCGv cpu_l1_Vf; +TCGv cpu_l1_Uf; + +TCGv cpu_l1_DEf; +TCGv cpu_l1_AEf; +TCGv cpu_l1_Hf; + +TCGv cpu_l2_Lf; +TCGv cpu_l2_Zf; +TCGv cpu_l2_Nf; +TCGv cpu_l2_Cf; +TCGv cpu_l2_Vf; +TCGv cpu_l2_Uf; + +TCGv cpu_l2_DEf; +TCGv cpu_l2_AEf; +TCGv cpu_l2_Hf; + +TCGv cpu_er_Lf; +TCGv cpu_er_Zf; +TCGv cpu_er_Nf; +TCGv cpu_er_Cf; +TCGv cpu_er_Vf; +TCGv cpu_er_Uf; + +TCGv cpu_er_DEf; +TCGv cpu_er_AEf; +TCGv cpu_er_Hf; + +TCGv cpu_eret; +TCGv cpu_erbta; +TCGv cpu_ecr; +TCGv cpu_efa; + +TCGv cpu_bta; +TCGv cpu_bta_l1; +TCGv cpu_bta_l2; + +TCGv cpu_pc; +TCGv cpu_lpc; +/* replaced by AUX_REG array */ +TCGv cpu_lps; +TCGv cpu_lpe; + +TCGv cpu_r[64]; + +TCGv cpu_intvec; + +TCGv cpu_debug_LD; +TCGv cpu_debug_SH; +TCGv cpu_debug_BH; +TCGv cpu_debug_UB; +TCGv cpu_debug_ZZ; +TCGv cpu_debug_RA; +TCGv cpu_debug_IS; +TCGv cpu_debug_FH; +TCGv cpu_debug_SS; + +TCGv cpu_lock_lf_var; + +/* NOTE: Pseudo register required for comparison with lp_end */ +TCGv cpu_npc; + +/* Macros */ + +#include "exec/gen-icount.h" +#define REG(x) (cpu_r[x]) + +/* macro used to fix middle-endianess. */ +#define ARRANGE_ENDIAN(endianess, buf) \ + ((endianess) ? arc_getm32(buf) : bswap32(buf)) + +/* + * The macro to add boiler plate code for conditional execution. + * It will add tcg_gen codes only if there is a condition to + * be checked (ctx->insn.cc != 0). This macro assumes that there + * is a "ctx" variable of type "DisasCtxt *" in context. Remember + * to pair it with CC_EPILOGUE macro. + */ +#define CC_PROLOGUE \ + TCGv cc = tcg_temp_local_new(); \ + TCGLabel *done = gen_new_label(); \ + do { \ + if (ctx->insn.cc) { \ + arc_gen_verifyCCFlag(ctx, cc); \ + tcg_gen_brcondi_tl(TCG_COND_NE, cc, 1, done); \ + } \ + } while (0) + +/* + * The finishing counter part of CC_PROLUGE. This is supposed + * to be put at the end of the function using it. + */ +#define CC_EPILOGUE \ + if (ctx->insn.cc) { \ + gen_set_label(done); \ + } \ + tcg_temp_free(cc) + +static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) +{ + if (unlikely(dc->base.singlestep_enabled)) { + return false; + } +#ifndef CONFIG_USER_ONLY + return (dc->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); +#else + return true; +#endif +} + +void gen_goto_tb(DisasContext *ctx, int n, TCGv dest) +{ + tcg_gen_mov_tl(cpu_pc, dest); + tcg_gen_andi_tl(cpu_pcl, dest, 0xfffffffc); + if (ctx->base.singlestep_enabled) { + gen_helper_debug(cpu_env); + } + tcg_gen_exit_tb(NULL, 0); +} + +static void gen_gotoi_tb(DisasContext *ctx, int n, target_ulong dest) +{ + if (use_goto_tb(ctx, dest)) { + tcg_gen_goto_tb(n); + tcg_gen_movi_tl(cpu_pc, dest); + tcg_gen_movi_tl(cpu_pcl, dest & 0xfffffffc); + tcg_gen_exit_tb(ctx->base.tb, n); + } else { + tcg_gen_movi_tl(cpu_pc, dest); + tcg_gen_movi_tl(cpu_pcl, dest & 0xfffffffc); + if (ctx->base.singlestep_enabled) { + gen_helper_debug(cpu_env); + } + tcg_gen_exit_tb(NULL, 0); + } +} + +void arc_translate_init(void) +{ + int i; + static int init_not_done = 1; + + if (init_not_done == 0) { + return; + } +#define ARC_REG_OFFS(x) offsetof(CPUARCState, x) + +#define NEW_ARC_REG(x) \ + tcg_global_mem_new_i32(cpu_env, offsetof(CPUARCState, x), #x) + + cpu_S1f = NEW_ARC_REG(macmod.S1); + cpu_S2f = NEW_ARC_REG(macmod.S2); + cpu_CSf = NEW_ARC_REG(macmod.CS); + + cpu_Zf = NEW_ARC_REG(stat.Zf); + cpu_Lf = NEW_ARC_REG(stat.Lf); + cpu_Nf = NEW_ARC_REG(stat.Nf); + cpu_Cf = NEW_ARC_REG(stat.Cf); + cpu_Vf = NEW_ARC_REG(stat.Vf); + cpu_Uf = NEW_ARC_REG(stat.Uf); + cpu_DEf = NEW_ARC_REG(stat.DEf); + cpu_ESf = NEW_ARC_REG(stat.ESf); + cpu_AEf = NEW_ARC_REG(stat.AEf); + cpu_Hf = NEW_ARC_REG(stat.Hf); + cpu_IEf = NEW_ARC_REG(stat.IEf); + cpu_Ef = NEW_ARC_REG(stat.Ef); + + cpu_is_delay_slot_instruction = NEW_ARC_REG(stat.is_delay_slot_instruction); + + cpu_l1_Zf = NEW_ARC_REG(stat_l1.Zf); + cpu_l1_Lf = NEW_ARC_REG(stat_l1.Lf); + cpu_l1_Nf = NEW_ARC_REG(stat_l1.Nf); + cpu_l1_Cf = NEW_ARC_REG(stat_l1.Cf); + cpu_l1_Vf = NEW_ARC_REG(stat_l1.Vf); + cpu_l1_Uf = NEW_ARC_REG(stat_l1.Uf); + cpu_l1_DEf = NEW_ARC_REG(stat_l1.DEf); + cpu_l1_AEf = NEW_ARC_REG(stat_l1.AEf); + cpu_l1_Hf = NEW_ARC_REG(stat_l1.Hf); + + cpu_er_Zf = NEW_ARC_REG(stat_er.Zf); + cpu_er_Lf = NEW_ARC_REG(stat_er.Lf); + cpu_er_Nf = NEW_ARC_REG(stat_er.Nf); + cpu_er_Cf = NEW_ARC_REG(stat_er.Cf); + cpu_er_Vf = NEW_ARC_REG(stat_er.Vf); + cpu_er_Uf = NEW_ARC_REG(stat_er.Uf); + cpu_er_DEf = NEW_ARC_REG(stat_er.DEf); + cpu_er_AEf = NEW_ARC_REG(stat_er.AEf); + cpu_er_Hf = NEW_ARC_REG(stat_er.Hf); + + cpu_eret = NEW_ARC_REG(eret); + cpu_erbta = NEW_ARC_REG(erbta); + cpu_ecr = NEW_ARC_REG(ecr); + cpu_efa = NEW_ARC_REG(efa); + cpu_bta = NEW_ARC_REG(bta); + cpu_lps = NEW_ARC_REG(lps); + cpu_lpe = NEW_ARC_REG(lpe); + cpu_pc = NEW_ARC_REG(pc); + cpu_npc = NEW_ARC_REG(npc); + + cpu_bta_l1 = NEW_ARC_REG(bta_l1); + cpu_bta_l2 = NEW_ARC_REG(bta_l2); + + cpu_intvec = NEW_ARC_REG(intvec); + + for (i = 0; i < 64; i++) { + char name[16]; + + sprintf(name, "r[%d]", i); + + cpu_r[i] = tcg_global_mem_new_i32(cpu_env, + ARC_REG_OFFS(r[i]), + strdup(name)); + } + + cpu_gp = cpu_r[26]; + cpu_fp = cpu_r[27]; + cpu_sp = cpu_r[28]; + cpu_ilink1 = cpu_r[29]; + cpu_ilink2 = cpu_r[30]; + cpu_blink = cpu_r[31]; + cpu_acclo = cpu_r[58]; + cpu_acchi = cpu_r[59]; + cpu_lpc = cpu_r[60]; + cpu_limm = cpu_r[62]; + cpu_pcl = cpu_r[63]; + + cpu_debug_LD = NEW_ARC_REG(debug.LD); + cpu_debug_SH = NEW_ARC_REG(debug.SH); + cpu_debug_BH = NEW_ARC_REG(debug.BH); + cpu_debug_UB = NEW_ARC_REG(debug.UB); + cpu_debug_ZZ = NEW_ARC_REG(debug.ZZ); + cpu_debug_RA = NEW_ARC_REG(debug.RA); + cpu_debug_IS = NEW_ARC_REG(debug.IS); + cpu_debug_FH = NEW_ARC_REG(debug.FH); + cpu_debug_SS = NEW_ARC_REG(debug.SS); + + cpu_lock_lf_var = NEW_ARC_REG(lock_lf_var); + + init_not_done = 0; +} + +static void arc_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cs) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + dc->base.is_jmp = DISAS_NEXT; + dc->mem_idx = dc->base.tb->flags & 1; +} +static void arc_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) +{ + /* place holder for now */ +} + +static void arc_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + + tcg_gen_insn_start(dc->base.pc_next); + dc->cpc = dc->base.pc_next; + + if (dc->base.num_insns == dc->base.max_insns && + (dc->base.tb->cflags & CF_LAST_IO)) { + gen_io_start(); + } +} + +static bool arc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + const CPUBreakpoint *bp) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + tcg_gen_movi_tl(cpu_pc, dc->cpc); + dc->base.is_jmp = DISAS_NORETURN; + gen_helper_debug(cpu_env); + dc->base.pc_next += 2; + return true; +} + +static int arc_gen_INVALID(const DisasContext *ctx) +{ + fprintf(stderr, "invalid inst @:%08x\n", ctx->cpc); + return DISAS_NEXT; +} + +extern bool enabled_interrupts; + +/* Arrange to middle endian, used by LITTLE ENDIAN systems. */ +static uint32_t arc_getm32(uint32_t data) +{ + uint32_t value = 0; + + value = (data & 0x0000ffff) << 16; + value |= (data & 0xffff0000) >> 16; + return value; +} + +/* + * Giving a CTX, decode it into an valid OPCODE_P if it + * exists. Returns TRUE if successfully. + */ +static bool read_and_decode_context(DisasContext *ctx, + const struct arc_opcode **opcode_p) +{ + uint16_t buffer[2]; + uint8_t length; + uint64_t insn; + + /* Read the first 16 bits, figure it out what kind of instruction it is. */ + buffer[0] = cpu_lduw_code(ctx->env, ctx->cpc); + length = arc_insn_length(buffer[0], ctx->env->family); + + switch (length) { + case 2: + /* 16-bit instructions. */ + insn = (uint64_t) buffer[0]; + break; + case 4: + /* 32-bit instructions. */ + buffer[1] = cpu_lduw_code(ctx->env, ctx->cpc + 2); + uint32_t buf = (buffer[0] << 16) | buffer[1]; + insn = buf; + break; + default: + g_assert_not_reached(); + } + + /* + * Now, we have read the entire opcode, decode it and place the + * relevant info into opcode and ctx->insn. + */ + *opcode_p = arc_find_format(&ctx->insn, insn, length, ctx->env->family); + + if (*opcode_p == NULL) { + return false; + } + + /* + * If the instruction requires long immediate, read the extra 4 + * bytes and initialize the relevant fields. + */ + if (ctx->insn.limm_p) { + ctx->insn.limm = ARRANGE_ENDIAN(true, + cpu_ldl_code(ctx->env, + ctx->cpc + length)); + length += 4; + } else { + ctx->insn.limm = 0; + } + + /* Update context. */ + ctx->insn.len = length; + ctx->npc = ctx->cpc + length; + ctx->pcl = ctx->cpc & 0xfffffffc; + + return true; +} + +/* Check if OPR is a register _and_ an even numbered one. */ +static inline bool is_odd_numbered_register(const operand_t opr) +{ + return (opr.type & ARC_OPERAND_IR) && (opr.value & 1); +} + +/* + * Going through every operand, if any of those is a register + * it is verified to be an even numbered register. Else, an + * exception is put in the generated code and FALSE is returned. + */ +static bool verify_all_regs_are_even(const DisasCtxt *ctx) +{ + for (int nop = 0; nop < ctx->insn.n_ops; ++nop) { + if (is_odd_numbered_register(ctx->insn.operands[nop])) { + arc_gen_excp(ctx, EXCP_INST_ERROR, 0, 0); + return false; + } + } + return true; +} + +/* + * Verifies if the destination operand (operand 0) is a register + * then it is an even numbered one. Else, an exception is put in + * the generated code and FALSE is returned. + */ +static bool verify_dest_reg_is_even(const DisasCtxt *ctx) +{ + if (is_odd_numbered_register(ctx->insn.operands[0])) { + arc_gen_excp(ctx, EXCP_INST_ERROR, 0, 0); + return false; + } + return true; +} + +enum arc_opcode_map { + MAP_NONE = -1, +#define SEMANTIC_FUNCTION(...) +#define CONSTANT(...) +#define MAPPING(MNEMONIC, NAME, NOPS, ...) MAP_##MNEMONIC##_##NAME, +#include "target/arc/semfunc_mapping.def" +#include "target/arc/extra_mapping.def" +#undef MAPPING +#undef CONSTANT +#undef SEMANTIC_FUNCTION + /* Add some include to generated files */ + MAP_LAST +}; + +const char number_of_ops_semfunc[MAP_LAST + 1] = { +#define SEMANTIC_FUNCTION(...) +#define CONSTANT(...) +#define MAPPING(MNEMONIC, NAME, NOPS, ...) NOPS, +#include "target/arc/semfunc_mapping.def" +#include "target/arc/extra_mapping.def" +#undef MAPPING +#undef CONSTANT +#undef SEMANTIC_FUNCTION + 2 +}; + +static enum arc_opcode_map arc_map_opcode(const struct arc_opcode *opcode) +{ +#define SEMANTIC_FUNCTION(...) +#define CONSTANT(...) +#define MAPPING(MNEMONIC, NAME, ...) \ + if (strcmp(opcode->name, #MNEMONIC) == 0) \ + return MAP_##MNEMONIC##_##NAME; +#include "target/arc/semfunc_mapping.def" +#include "target/arc/extra_mapping.def" +#undef MAPPING +#undef CONSTANT +#undef SEMANTIC_FUNCTION + + return MAP_NONE; +} + +/* Code support for constant values coming from semantic function mapping. */ +struct constant_operands { + uint8_t operand_number; + uint32_t default_value; + struct constant_operands *next; +}; + +struct constant_operands *map_constant_operands[MAP_LAST]; + +static void add_constant_operand(enum arc_opcode_map mapping, + uint8_t operand_number, + uint32_t value) +{ + struct constant_operands **t = &(map_constant_operands[mapping]); + while (*t != NULL) { + t = &((*t)->next); + } + *t = (struct constant_operands *) malloc(sizeof(struct constant_operands)); + + (*t)->operand_number = operand_number; + (*t)->default_value = value; + (*t)->next = NULL; +} + +static struct constant_operands * +constant_entry_for(enum arc_opcode_map mapping, + uint8_t operand_number) +{ + struct constant_operands *t = map_constant_operands[mapping]; + while (t != NULL) { + if (t->operand_number == operand_number) { + return t; + } + t = t->next; + } + return NULL; +} + +static void init_constants(void) +{ +#define SEMANTIC_FUNCTION(...) +#define MAPPING(...) +#define CONSTANT(NAME, MNEMONIC, OP_NUM, VALUE) \ + add_constant_operand(MAP_##MNEMONIC##_##NAME, OP_NUM, VALUE); +#include "target/arc/semfunc_mapping.def" +#include "target/arc/extra_mapping.def" +#undef MAPPING +#undef CONSTANT +#undef SEMANTIC_FUNCTION +} + +static void arc_debug_opcode(const struct arc_opcode *opcode, + DisasContext *ctx, + const char *msg) +{ + qemu_log_mask(LOG_UNIMP, + "%s for %s at pc=0x%08x\n", + msg, opcode->name, ctx->cpc); +} + +static TCGv arc_decode_operand(const struct arc_opcode *opcode, + DisasContext *ctx, + unsigned char nop, + enum arc_opcode_map mapping) +{ + TCGv ret; + + if (nop >= ctx->insn.n_ops) { + struct constant_operands *co = constant_entry_for(mapping, nop); + assert(co != NULL); + ret = tcg_const_local_i32(co->default_value); + return ret; + } else { + operand_t operand = ctx->insn.operands[nop]; + + if (operand.type & ARC_OPERAND_IR) { + ret = cpu_r[operand.value]; + if (operand.value == 63) { + tcg_gen_movi_tl(cpu_pcl, ctx->pcl); + } + } else { + int32_t limm = operand.value; + if (operand.type & ARC_OPERAND_LIMM) { + limm = ctx->insn.limm; + tcg_gen_movi_tl(cpu_limm, limm); + ret = cpu_r[62]; + } else { + ret = tcg_const_local_i32(limm); + } + } + } + + return ret; +} + +/* See translate.h. */ +void arc_gen_excp(const DisasCtxt *ctx, + uint32_t index, + uint32_t causecode, + uint32_t param) +{ + TCGv_i32 tcg_index = tcg_const_i32(index); + TCGv_i32 tcg_cause = tcg_const_i32(causecode); + TCGv_i32 tcg_param = tcg_const_i32(param); + + tcg_gen_movi_tl(cpu_pc, ctx->cpc); + tcg_gen_movi_tl(cpu_eret, ctx->cpc); + tcg_gen_movi_tl(cpu_erbta, ctx->npc); + + gen_helper_raise_exception(cpu_env, tcg_index, tcg_cause, tcg_param); + + tcg_temp_free_i32(tcg_index); + tcg_temp_free_i32(tcg_cause); + tcg_temp_free_i32(tcg_param); +} + +/* Generate trap. */ +static void gen_trap(DisasContext *ctx, uint32_t param) +{ + TCGv_i32 tmp0 = tcg_const_i32(EXCP_TRAP); + TCGv_i32 tmp1 = tcg_const_i32(0); + TCGv_i32 tmp2 = tcg_const_i32(param); + + tcg_gen_movi_tl(cpu_pc, ctx->cpc); + tcg_gen_movi_tl(cpu_eret, ctx->npc); + tcg_gen_mov_tl(cpu_erbta, cpu_bta); + + gen_helper_raise_exception(cpu_env, tmp0, tmp1, tmp2); + + tcg_temp_free_i32(tmp0); + tcg_temp_free_i32(tmp1); + tcg_temp_free_i32(tmp2); +} + +/* Generate sleep insn. */ +static void gen_sleep(DisasContext *ctx, TCGv opa) +{ + uint32_t param = 0; + + if (ctx->insn.operands[0].type & ARC_OPERAND_IR) { + TCGv tmp3 = tcg_temp_local_new_i32(); + TCGLabel *done_L = gen_new_label(); + + tcg_gen_andi_tl(tmp3, opa, 0x10); + tcg_gen_brcondi_tl(TCG_COND_NE, tmp3, 0x10, done_L); + tcg_gen_andi_tl(cpu_Ef, opa, 0x0f); + tcg_gen_movi_tl(cpu_IEf, 1); + gen_set_label(done_L); + + tcg_temp_free_i32(tmp3); + } else { + param = ctx->insn.operands[0].value; + if (param & 0x10) { + tcg_gen_movi_tl(cpu_IEf, 1); + tcg_gen_movi_tl(cpu_Ef, param & 0x0f); + } + } + /* FIXME: setup debug registers as well. */ + + TCGv npc = tcg_temp_local_new_i32(); + tcg_gen_movi_tl(npc, ctx->npc); + gen_helper_halt(cpu_env, npc); + tcg_temp_free_i32(npc); + qemu_log_mask(CPU_LOG_TB_IN_ASM, + "CPU in sleep mode, waiting for an IRQ.\n"); +} + +/* Return from exception. */ +static void gen_rtie(DisasContext *ctx) +{ + tcg_gen_movi_tl(cpu_pc, ctx->cpc); + gen_helper_rtie(cpu_env); + tcg_gen_mov_tl(cpu_pc, cpu_pcl); + gen_goto_tb(ctx, 1, cpu_pc); +} + +/* accumulator = b32 * c32 (signed multiplication). */ +void +arc_gen_mpyd(const DisasCtxt *ctx, TCGv_i32 dest, + TCGv_i32 b32, TCGv_i32 c32) +{ + CC_PROLOGUE; + tcg_gen_muls2_i32(cpu_acclo, cpu_acchi, b32, c32); + if (ctx->insn.operands[0].type & ARC_OPERAND_IR) { + tcg_gen_mov_tl(arc_gen_next_reg(ctx, dest), cpu_acchi); + tcg_gen_mov_tl(dest, cpu_acclo); + } + if (ctx->insn.f) { + setNFlag(cpu_acchi); + tcg_gen_movi_tl(cpu_Vf, 0); + } + CC_EPILOGUE; +} + +/* accumulator = b32 * c32 (unsigned multiplication). */ +void +arc_gen_mpydu(const DisasCtxt *ctx, TCGv_i32 dest, + TCGv_i32 b32, TCGv_i32 c32) +{ + CC_PROLOGUE; + tcg_gen_mulu2_i32(cpu_acclo, cpu_acchi, b32, c32); + if (ctx->insn.operands[0].type & ARC_OPERAND_IR) { + tcg_gen_mov_tl(arc_gen_next_reg(ctx, dest), cpu_acchi); + tcg_gen_mov_tl(dest, cpu_acclo); + } + if (ctx->insn.f) { + tcg_gen_movi_tl(cpu_Vf, 0); + } + CC_EPILOGUE; +} + +/* + * Populates a 64-bit vector with register pair: + * vec64=(REGn+1,REGn)=(REGn+1_hi,REGn+1_lo,REGn_hi,REGn_lo) + * REG must be refering to an even numbered register. + * Do not forget to free the returned TCGv_i64 when done! + */ +static TCGv_i64 pair_reg_to_i64(const DisasCtxt *ctx, TCGv_i32 reg) +{ + TCGv_i64 vec64 = tcg_temp_new_i64(); + tcg_gen_concat_i32_i64(vec64, reg, arc_gen_next_reg(ctx, reg)); + return vec64; +} + +/* + * Populates a 32-bit vector with repeating SHIMM: + * vec32=(0000000000u6,0000000000u6) + * vec32=(sssss12,sssss12) + * It's crucial that the s12 part of an encoding is in signed + * integer form while passed along in SHIMM, e.g: + * s12 = -125 (0xf803) --> 0xfffff803 + * Do not forget to free the returned TCGv_i32 when done! + */ +static TCGv_i32 dup_shimm_to_i32(int16_t shimm) +{ + TCGv_i32 vec32 = tcg_temp_new_i32(); + int32_t val = shimm; + val = ((val << 16) & 0xffff0000) | (val & 0xffff); + tcg_gen_movi_i32(vec32, val); + return vec32; +} + +/* + * Populates a 64-bit vector with repeating LIMM: + * vec64=(limm,limm)=(limm_hi,limm_lo,limm_hi,limm_lo) + * Do not forget to free the returned TCGv_i64 when done! + */ +static TCGv_i64 dup_limm_to_i64(int32_t limm) +{ + TCGv_i64 vec64 = tcg_temp_new_i64(); + int64_t val = limm; + val = (val << 32) | (val & 0xffffffff); + tcg_gen_movi_i64(vec64, val); + return vec64; +} + +/* + * Populates a 64-bit vector with four SHIMM (u6 or s12): + * vec64=(0000000000u6,0000000000u6,0000000000u6,0000000000u6) + * vec64=(sssss12,sssss12,sssss12,sssss12) + * It's crucial that the s12 part of an encoding is in signed + * integer form while passed along in SHIMM, e.g: + * s12 = -125 (0xf803) --> 0xfffff803 + * Do not forget to free the returned TCGv_i64 when done! + */ +static TCGv_i64 quad_shimm_to_i64(int16_t shimm) +{ + TCGv_i64 vec64 = tcg_temp_new_i64(); + int64_t val = shimm; + val = (val << 48) | ((val << 32) & 0x0000ffff00000000) | + ((val << 16) & 0x00000000ffff0000) | (val & 0xffff); + tcg_gen_movi_i64(vec64, val); + return vec64; +} + +/* + * gen_vec_op2 emits instructions to perform the desired operation, + * defined by OP, on the inputs (B32 and C32) and returns the + * result in DEST. + * + * vector size: 64-bit + * vector elements: 2 + * element size: 32-bit + * + * (A1, A0) = (B1, B0) op (C1, C0) + */ +static void gen_vec_op2(const DisasCtxt *ctx, + void (*OP)(TCGv_i64, TCGv_i64, TCGv_i64), + TCGv_i32 dest, + TCGv_i32 b32, + TCGv_i32 c32) +{ + TCGv_i64 d64, b64, c64; + + /* If no real register for result, then this a nop. Bail out! */ + if (!(ctx->insn.operands[0].type & ARC_OPERAND_IR)) { + return; + } + + /* Extend B32 to B64 based on its type: {reg, limm}. */ + if (ctx->insn.operands[1].type & ARC_OPERAND_IR) { + b64 = pair_reg_to_i64(ctx, b32); + } else if (ctx->insn.operands[1].type & ARC_OPERAND_LIMM) { + b64 = dup_limm_to_i64(ctx->insn.limm); + } else { + g_assert_not_reached(); + } + /* Extend C32 to C64 based on its type: {reg, limm, shimm}. */ + if (ctx->insn.operands[2].type & ARC_OPERAND_IR) { + c64 = pair_reg_to_i64(ctx, c32); + } else if (ctx->insn.operands[2].type & ARC_OPERAND_LIMM) { + c64 = dup_limm_to_i64(ctx->insn.limm); + } else if (ctx->insn.operands[2].type & ARC_OPERAND_SHIMM) { + /* At this point SHIMM is extended like LIMM. */ + c64 = dup_limm_to_i64(ctx->insn.operands[2].value); + } else { + g_assert_not_reached(); + } + d64 = tcg_temp_new_i64(); + + (*OP)(d64, b64, c64); + tcg_gen_extrl_i64_i32(dest, d64); + tcg_gen_extrh_i64_i32(arc_gen_next_reg(ctx, dest), d64); + + tcg_temp_free_i64(d64); + tcg_temp_free_i64(c64); + tcg_temp_free_i64(b64); + return; +} + +/* + * gen_vec_op2h emits instructions to perform the desired operation, + * defined by OP, on the inputs (B32 and C32) and returns the + * result in DEST. + * + * vector size: 32-bit + * vector elements: 2 + * element size: 16-bit + * + * (a1, a0) = (b1, b0) op (c1, c0) + */ +static void gen_vec_op2h(const DisasCtxt *ctx, + void (*OP)(TCGv, TCGv, TCGv), + TCGv_i32 dest, + TCGv_i32 b32, + TCGv_i32 c32) +{ + TCGv_i32 t0, t1; + + /* If no real register for result, then this a nop. Bail out! */ + if (!(ctx->insn.operands[0].type & ARC_OPERAND_IR)) { + return; + } + + t0 = tcg_temp_new(); + tcg_gen_mov_i32(t0, b32); + /* + * If the last operand is a u6/s12, say 63, there is no "HI" in it. + * Instead, it must be duplicated to form a pair; e.g.: (63, 63). + */ + if (ctx->insn.operands[2].type & ARC_OPERAND_SHIMM) { + t1 = dup_shimm_to_i32(ctx->insn.operands[2].value); + } else { + t1 = tcg_temp_new(); + tcg_gen_mov_i32(t1, c32); + } + + (*OP)(dest, t0, t1); + + tcg_temp_free(t1); + tcg_temp_free(t0); +} + + +/* + * gen_vec_op4h emits instructions to perform the desired operation, + * defined by OP, on the inputs (B32 and C32) and returns the + * result in DEST. + * + * vector size: 64-bit + * vector elements: 4 + * element size: 16-bit + * + * (a3, a2, a1, a0) = (b3, b2, b1, b0) op (c3, c2, c1, c0) + */ +static void gen_vec_op4h(const DisasCtxt *ctx, + void (*op)(TCGv_i64, TCGv_i64, TCGv_i64), + TCGv_i32 dest, + TCGv_i32 b32, + TCGv_i32 c32) +{ + TCGv_i64 d64, b64, c64; + + /* If no real register for result, then this a nop. Bail out! */ + if (!(ctx->insn.operands[0].type & ARC_OPERAND_IR)) { + return; + } + + /* Extend B32 to B64 based on its type: {reg, limm}. */ + if (ctx->insn.operands[1].type & ARC_OPERAND_IR) { + b64 = pair_reg_to_i64(ctx, b32); + } else if (ctx->insn.operands[1].type & ARC_OPERAND_LIMM) { + b64 = dup_limm_to_i64(ctx->insn.limm); + } else { + g_assert_not_reached(); + } + /* Extend C32 to C64 based on its type: {reg, limm, shimm}. */ + if (ctx->insn.operands[2].type & ARC_OPERAND_IR) { + c64 = pair_reg_to_i64(ctx, c32); + } else if (ctx->insn.operands[2].type & ARC_OPERAND_LIMM) { + c64 = dup_limm_to_i64(ctx->insn.limm); + } else if (ctx->insn.operands[2].type & ARC_OPERAND_SHIMM) { + c64 = quad_shimm_to_i64(ctx->insn.operands[2].value); + } else { + g_assert_not_reached(); + } + d64 = tcg_temp_new_i64(); + + (*op)(d64, b64, c64); + tcg_gen_extrl_i64_i32(dest, d64); + tcg_gen_extrh_i64_i32(arc_gen_next_reg(ctx, dest), d64); + + tcg_temp_free_i64(d64); + tcg_temp_free_i64(c64); + tcg_temp_free_i64(b64); + return; +} + +/* + * To use a 32-bit adder to sum two 16-bit numbers: + * 1) Mask out the 16th bit in both operands to cause no carry. + * 2) Add the numbers. + * 3) Put back the 16th bit sum: T0[15] ^ T1[15] ^ CARRY[14] + * (ignoring the possible carry generated) + * T0 and T1 values will change. Use temporary ones. + */ +static void gen_add16(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_xor_i32(tmp, t0, t1); + tcg_gen_andi_i32(tmp, tmp, 0x8000); + tcg_gen_andi_i32(t0, t0, ~0x8000); + tcg_gen_andi_i32(t1, t1, ~0x8000); + tcg_gen_add_i32(t0, t0, t1); + tcg_gen_xor_i32(dest, t0, tmp); + tcg_temp_free_i32(tmp); +} + +/* + * To use a 32-bit subtracter to subtract two 16-bit numbers: + * 0) Record how T0[15]-T1[15] would result without other bits. + * 1) Make the 16th bit for the first operand 1 and the second + * operand 0. This combination of (1 - 0) will absorb any + * possible borrow that may come from the 15th bit. + * 2) Subtract the numbers. + * 3) Correct the 16th bit result (1 - 0 - B): + * If the 16th bit is 1 --> no borrow was asked. + * If the 16th bit is 0 --> a borrow was asked. + * and if a borrow was asked, the result of step 0 must be + * inverted (0 -> 1 and 1 -> 0). If not, the result of step + * 0 can be used readily: + * STEP2[15] | T0[15]-T1[15] | DEST[15] + * ----------+---------------+--------- + * 0 | 0 | 1 + * 0 | 1 | 0 + * 1 | 0 | 0 + * 1 | 1 | 1 + * This is a truth table for XNOR(a,b): + * NOT(XOR(a,b))=XOR(XOR(a,b),1) + * This approach might seem pedantic, but it generates one less + * instruction than the obvious mask-and-sub approach and requires + * two less TCG variables. + * T0 and T1 values will change. Use temporary ones. + */ +static void gen_sub16(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_xor_i32(tmp, t0, t1); /* step 0 */ + tcg_gen_andi_i32(tmp, tmp, 0x8000); /* step 0 */ + tcg_gen_ori_i32(t0, t0, 0x8000); /* step 1 */ + tcg_gen_andi_i32(t1, t1, ~0x8000); /* step 1 */ + tcg_gen_sub_i32(t0, t0, t1); /* step 2 */ + tcg_gen_xor_i32(dest, t0, tmp); /* step 3 */ + tcg_gen_xori_i32(dest, dest, 0x8000); /* step 3 */ + tcg_temp_free_i32(tmp); +} + +void +arc_gen_vadd2(const DisasCtxt *ctx, TCGv dest, TCGv_i32 b, TCGv_i32 c) +{ + CC_PROLOGUE; + gen_vec_op2(ctx, tcg_gen_vec_add32_i64, dest, b, c); + CC_EPILOGUE; +} + +void +arc_gen_vadd2h(const DisasCtxt *ctx, TCGv dest, TCGv_i32 b, TCGv_i32 c) +{ + CC_PROLOGUE; + gen_vec_op2h(ctx, gen_add16, dest, b, c); + CC_EPILOGUE; +} + +void +arc_gen_vadd4h(const DisasCtxt *ctx, TCGv dest, TCGv_i32 b, TCGv_i32 c) +{ + CC_PROLOGUE; + gen_vec_op4h(ctx, tcg_gen_vec_add16_i64, dest, b, c); + CC_EPILOGUE; +} + +void +arc_gen_vsub2(const DisasCtxt *ctx, TCGv dest, TCGv_i32 b, TCGv_i32 c) +{ + CC_PROLOGUE; + gen_vec_op2(ctx, tcg_gen_vec_sub32_i64, dest, b, c); + CC_EPILOGUE; +} + +void +arc_gen_vsub2h(const DisasCtxt *ctx, TCGv dest, TCGv_i32 b, TCGv_i32 c) +{ + CC_PROLOGUE; + gen_vec_op2h(ctx, gen_sub16, dest, b, c); + CC_EPILOGUE; +} + +void +arc_gen_vsub4h(const DisasCtxt *ctx, TCGv dest, TCGv_i32 b, TCGv_i32 c) +{ + CC_PROLOGUE; + gen_vec_op4h(ctx, tcg_gen_vec_sub16_i64, dest, b, c); + CC_EPILOGUE; +} + + +/* Given a CTX, generate the relevant TCG code for the given opcode. */ +static int arc_decode(DisasContext *ctx, const struct arc_opcode *opcode) +{ + int ret = DISAS_NEXT; + enum arc_opcode_map mapping; + static bool initialized = false; + + if (initialized == false) { + init_constants(); + initialized = true; + } + + /* Do the mapping. */ + mapping = arc_map_opcode(opcode); + if (mapping != MAP_NONE) { + TCGv ops[10]; + int i; + for (i = 0; i < number_of_ops_semfunc[mapping]; i++) { + ops[i] = arc_decode_operand(opcode, ctx, i, mapping); + } + + /* + * Store some elements statically to implement less dynamic + * features of instructions. Started by the need to keep a + * static reference to LP_START and LP_END. + */ + +#define SEMANTIC_FUNCTION_CALL_0(NAME, A) \ + arc_gen_##NAME(ctx); +#define SEMANTIC_FUNCTION_CALL_1(NAME, A) \ + arc_gen_##NAME(ctx, ops[A]); +#define SEMANTIC_FUNCTION_CALL_2(NAME, A, B) \ + arc_gen_##NAME(ctx, ops[A], ops[B]); +#define SEMANTIC_FUNCTION_CALL_3(NAME, A, B, C) \ + arc_gen_##NAME(ctx, ops[A], ops[B], ops[C]); +#define SEMANTIC_FUNCTION_CALL_4(NAME, A, B, C, D) \ + arc_gen_##NAME(ctx, ops[A], ops[B], ops[C], ops[D]); + +#define SEMANTIC_FUNCTION(...) +#define CONSTANT(...) +#define MAPPING(MNEMONIC, NAME, NOPS, ...) \ + case MAP_##MNEMONIC##_##NAME: \ + ret = SEMANTIC_FUNCTION_CALL_##NOPS(NAME, __VA_ARGS__); \ + break; + switch (mapping) { +#include "target/arc/semfunc_mapping.def" + + case MAP_swi_SWI: + case MAP_swi_s_SWI: + arc_gen_excp(ctx, EXCP_SWI, 0, ctx->insn.operands[0].value); + ret = DISAS_NEXT; + break; + + case MAP_trap_s_TRAP: + gen_trap(ctx, ctx->insn.operands[0].value); + ret = DISAS_NORETURN; + break; + + case MAP_rtie_RTIE: + gen_rtie(ctx); + ret = DISAS_NORETURN; + break; + + case MAP_sleep_SLEEP: + gen_sleep(ctx, ops[0]); + ret = DISAS_NEXT; + break; + + case MAP_vadd2_VADD: + if (verify_all_regs_are_even(ctx)) { + arc_gen_vadd2(ctx, ops[0], ops[1], ops[2]); + } + ret = DISAS_NEXT; + break; + case MAP_vadd2h_VADD: + arc_gen_vadd2h(ctx, ops[0], ops[1], ops[2]); + ret = DISAS_NEXT; + break; + case MAP_vadd4h_VADD: + if (verify_all_regs_are_even(ctx)) { + arc_gen_vadd4h(ctx, ops[0], ops[1], ops[2]); + } + ret = DISAS_NEXT; + break; + + case MAP_vsub2_VSUB: + if (verify_all_regs_are_even(ctx)) { + arc_gen_vsub2(ctx, ops[0], ops[1], ops[2]); + } + ret = DISAS_NEXT; + break; + case MAP_vsub2h_VSUB: + arc_gen_vsub2h(ctx, ops[0], ops[1], ops[2]); + ret = DISAS_NEXT; + break; + case MAP_vsub4h_VSUB: + if (verify_all_regs_are_even(ctx)) { + arc_gen_vsub4h(ctx, ops[0], ops[1], ops[2]); + } + ret = DISAS_NEXT; + break; + + case MAP_mpyd_MPYD: + if (verify_dest_reg_is_even(ctx)) { + arc_gen_mpyd(ctx, ops[0], ops[1], ops[2]); + } + ret = DISAS_NEXT; + break; + case MAP_mpydu_MPYD: + if (verify_dest_reg_is_even(ctx)) { + arc_gen_mpydu(ctx, ops[0], ops[1], ops[2]); + } + ret = DISAS_NEXT; + break; + + default: + arc_debug_opcode(opcode, ctx, "No handle for map opcode"); + g_assert(!"Semantic not handled: Use -d unimp to list it."); + } +#undef MAPPING +#undef CONSTANT +#undef SEMANTIC_FUNCTION +#undef SEMANTIC_FUNCTION_CALL_0 +#undef SEMANTIC_FUNCTION_CALL_1 +#undef SEMANTIC_FUNCTION_CALL_2 +#undef SEMANTIC_FUNCTION_CALL_3 + + for (i = 0; i < number_of_ops_semfunc[mapping]; i++) { + operand_t operand = ctx->insn.operands[i]; + if (!(operand.type & ARC_OPERAND_LIMM) && + !(operand.type & ARC_OPERAND_IR)) { + tcg_temp_free_i32(ops[i]); + } + } + + } else { + arc_debug_opcode(opcode, ctx, "No mapping for opcode"); + g_assert(!"Semantic not found: Use -d unimp to list it."); + } + + return ret; +} + +void decode_opc(CPUARCState *env, DisasContext *ctx) +{ + ctx->env = env; + + enabled_interrupts = false; + + const struct arc_opcode *opcode = NULL; + if (!read_and_decode_context(ctx, &opcode)) { + ctx->base.is_jmp = arc_gen_INVALID(ctx); + return; + } + + ctx->base.is_jmp = arc_decode(ctx, opcode); + + TCGv npc = tcg_const_local_i32(ctx->npc); + gen_helper_zol_verify(cpu_env, npc); + tcg_temp_free(npc); + + enabled_interrupts = true; +} + +static void arc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + bool in_a_delayslot_instruction = false; + DisasContext *dc = container_of(dcbase, DisasContext, base); + CPUARCState *env = cpu->env_ptr; + + /* TODO (issue #62): these must be removed */ + dc->zero = tcg_const_local_i32(0); + dc->one = tcg_const_local_i32(1); + + if (env->stat.is_delay_slot_instruction == 1) { + in_a_delayslot_instruction = true; + } + + dc->cpc = dc->base.pc_next; + decode_opc(env, dc); + + dc->base.pc_next = dc->npc; + tcg_gen_movi_tl(cpu_npc, dc->npc); + + if (in_a_delayslot_instruction == true) { + dc->base.is_jmp = DISAS_NORETURN; + + /* Post execution delayslot logic. */ + TCGLabel *DEf_not_set_label1 = gen_new_label(); + tcg_gen_brcondi_i32(TCG_COND_NE, cpu_DEf, 1, DEf_not_set_label1); + tcg_gen_movi_tl(cpu_DEf, 0); + gen_goto_tb(dc, 1, cpu_bta); + gen_set_label(DEf_not_set_label1); + env->stat.is_delay_slot_instruction = 0; + } + + if (dc->base.is_jmp == DISAS_NORETURN) { + gen_gotoi_tb(dc, 0, dc->npc); + } else if (dc->base.is_jmp == DISAS_NEXT) { + target_ulong page_start; + + page_start = dc->base.pc_first & TARGET_PAGE_MASK; + if (dc->base.pc_next - page_start >= TARGET_PAGE_SIZE) { + dc->base.is_jmp = DISAS_TOO_MANY; + } + } + + /* TODO (issue #62): these must be removed. */ + tcg_temp_free_i32(dc->zero); + tcg_temp_free_i32(dc->one); + + /* verify if there is any TCG temporaries leakge */ + translator_loop_temp_check(dcbase); +} + +static void arc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + switch (dc->base.is_jmp) { + case DISAS_TOO_MANY: + case DISAS_UPDATE: + gen_gotoi_tb(dc, 0, dc->base.pc_next); + break; + case DISAS_BRANCH_IN_DELAYSLOT: + case DISAS_NORETURN: + break; + default: + g_assert_not_reached(); + } + + if (dc->base.num_insns == dc->base.max_insns && + (dc->base.tb->cflags & CF_LAST_IO)) { + gen_io_end(); + } +} + +static void arc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size); +} + + +static const TranslatorOps arc_translator_ops = { + .init_disas_context = arc_tr_init_disas_context, + .tb_start = arc_tr_tb_start, + .insn_start = arc_tr_insn_start, + .breakpoint_check = arc_tr_breakpoint_check, + .translate_insn = arc_tr_translate_insn, + .tb_stop = arc_tr_tb_stop, + .disas_log = arc_tr_disas_log, +}; + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cpu, + TranslationBlock *tb, + int max_insns) +{ + DisasContext dc; + const TranslatorOps *ops = &arc_translator_ops; + translator_loop(ops, &dc.base, cpu, tb, max_insns); +} + +void restore_state_to_opc(CPUARCState *env, + TranslationBlock *tb, + target_ulong *data) +{ + env->pc = data[0]; +} + +void arc_cpu_dump_state(CPUState *cs, FILE *f, int flags) +{ + ARCCPU *cpu = ARC_CPU(cs); + CPUARCState *env = &cpu->env; + int i; + + qemu_fprintf(f, "STATUS: [ %c %c %c %c %c %c %s %s %s %s %s %s %c]\n", + env->stat.Lf ? 'L' : '-', + env->stat.Zf ? 'Z' : '-', + env->stat.Nf ? 'N' : '-', + env->stat.Cf ? 'C' : '-', + env->stat.Vf ? 'V' : '-', + env->stat.Uf ? 'U' : '-', + env->stat.DEf ? "DE" : "--", + env->stat.AEf ? "AE" : "--", + env->stat.Ef ? "E" : "--", + env->stat.DZf ? "DZ" : "--", + env->stat.SCf ? "SC" : "--", + env->stat.IEf ? "IE" : "--", + env->stat.Hf ? 'H' : '-' + ); + + qemu_fprintf(f, "\n"); + for (i = 0; i < ARRAY_SIZE(env->r); i++) { + qemu_fprintf(f, "R[%02d]: %02x ", i, env->r[i]); + + if ((i % 8) == 7) { + qemu_fprintf(f, "\n"); + } + } +} + + +/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ +/* vim: set ts=4 sw=4 et: */ diff --git a/target/arc/translate.h b/target/arc/translate.h new file mode 100644 index 0000000000..18c9deb972 --- /dev/null +++ b/target/arc/translate.h @@ -0,0 +1,201 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synppsys Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#ifndef ARC_TRANSLATE_H_ +#define ARC_TRANSLATE_H_ + + +#include "arc-common.h" + +#include "tcg/tcg.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "disas/disas.h" +#include "tcg/tcg-op.h" +#include "exec/cpu_ldst.h" + +#include "exec/helper-proto.h" +#include "exec/helper-gen.h" +#include "exec/log.h" + +#include "exec/translator.h" + +/* signaling the end of translation block */ +#define DISAS_UPDATE DISAS_TARGET_0 +#define DISAS_BRANCH_IN_DELAYSLOT DISAS_TARGET_1 + +typedef struct DisasContext { + DisasContextBase base; + + uint32_t cpc; /* current pc */ + uint32_t npc; /* next pc */ + uint32_t dpc; /* next next pc */ + uint32_t pcl; + uint32_t lpe; + uint32_t lps; + + unsigned ds; /* we are within ds*/ + + /* TODO (issue #62): these must be removed */ + TCGv zero; /* 0x00000000 */ + TCGv one; /* 0x00000001 */ + + insn_t insn; + + CPUARCState *env; + + uint16_t buffer[2]; + uint8_t mem_idx; + +} DisasContext; + + +extern TCGv cpu_gp; +extern TCGv cpu_fp; +extern TCGv cpu_sp; +extern TCGv cpu_ilink1; +extern TCGv cpu_ilink2; +extern TCGv cpu_blink; +extern TCGv cpu_acclo; +extern TCGv cpu_acchi; +extern TCGv cpu_pcl; +extern TCGv cpu_limm; + +extern TCGv cpu_S1f; +extern TCGv cpu_S2f; +extern TCGv cpu_CSf; + +extern TCGv cpu_Lf; +extern TCGv cpu_Zf; +extern TCGv cpu_Nf; +extern TCGv cpu_Cf; +extern TCGv cpu_Vf; +extern TCGv cpu_Uf; + +extern TCGv cpu_DEf; +extern TCGv cpu_ESf; +extern TCGv cpu_AEf; +extern TCGv cpu_IEf; +extern TCGv cpu_Hf; +extern TCGv cpu_Ef; + +extern TCGv cpu_is_delay_slot_instruction; + +extern TCGv cpu_l1_Lf; +extern TCGv cpu_l1_Zf; +extern TCGv cpu_l1_Nf; +extern TCGv cpu_l1_Cf; +extern TCGv cpu_l1_Vf; +extern TCGv cpu_l1_Uf; + +extern TCGv cpu_l1_DEf; +extern TCGv cpu_l1_AEf; +extern TCGv cpu_l1_Hf; + +extern TCGv cpu_l2_Lf; +extern TCGv cpu_l2_Zf; +extern TCGv cpu_l2_Nf; +extern TCGv cpu_l2_Cf; +extern TCGv cpu_l2_Vf; +extern TCGv cpu_l2_Uf; + +extern TCGv cpu_l2_DEf; +extern TCGv cpu_l2_AEf; +extern TCGv cpu_l2_Hf; + +extern TCGv cpu_er_Lf; +extern TCGv cpu_er_Zf; +extern TCGv cpu_er_Nf; +extern TCGv cpu_er_Cf; +extern TCGv cpu_er_Vf; +extern TCGv cpu_er_Uf; + +extern TCGv cpu_er_DEf; +extern TCGv cpu_er_AEf; +extern TCGv cpu_er_Hf; + +extern TCGv cpu_eret; +extern TCGv cpu_erbta; +extern TCGv cpu_ecr; +extern TCGv cpu_efa; + +extern TCGv cpu_pc; +extern TCGv cpu_lpc; +extern TCGv cpu_lps; +extern TCGv cpu_lpe; + +extern TCGv cpu_npc; + +extern TCGv cpu_bta; +extern TCGv cpu_bta_l1; +extern TCGv cpu_bta_l2; + +extern TCGv cpu_r[64]; + +extern TCGv cpu_intvec; + +extern TCGv cpu_debug_LD; +extern TCGv cpu_debug_SH; +extern TCGv cpu_debug_BH; +extern TCGv cpu_debug_UB; +extern TCGv cpu_debug_ZZ; +extern TCGv cpu_debug_RA; +extern TCGv cpu_debug_IS; +extern TCGv cpu_debug_FH; +extern TCGv cpu_debug_SS; + +extern TCGv cpu_lock_lf_var; + +extern TCGv cpu_exception_delay_slot_address; + +/* TODO: Remove DisasCtxt. */ +typedef struct DisasContext DisasCtxt; + +void gen_goto_tb(DisasContext *ctx, int n, TCGv dest); + +void decode_opc(CPUARCState *env, DisasContext *ctx); + +/* + * Helper function to glue "rasing an exception" in the generated TCGs. + * + * ctx: Disassembling context + * index: ECR's index field + * causecode: ECR's cause code filed + * param: ECR's parameter field + */ +void arc_gen_excp(const DisasCtxt *ctx, uint32_t index, + uint32_t causecode, uint32_t param); + +void arc_gen_vadd2(const DisasCtxt *ctx, TCGv dest, TCGv_i32 b, TCGv_i32 c); +void arc_gen_vadd2h(const DisasCtxt *ctx, TCGv dest, TCGv_i32 b, TCGv_i32 c); +void arc_gen_vadd4h(const DisasCtxt *ctx, TCGv dest, TCGv_i32 b, TCGv_i32 c); + +void arc_gen_vsub2(const DisasCtxt *ctx, TCGv dest, TCGv_i32 b, TCGv_i32 c); +void arc_gen_vsub2h(const DisasCtxt *ctx, TCGv dest, TCGv_i32 b, TCGv_i32 c); +void arc_gen_vsub4h(const DisasCtxt *ctx, TCGv dest, TCGv_i32 b, TCGv_i32 c); + +void arc_gen_mpyd(const DisasCtxt *ctx, TCGv dest, TCGv_i32 b, TCGv_i32 c); +void arc_gen_mpydu(const DisasCtxt *ctx, TCGv dest, TCGv_i32 b, TCGv_i32 c); + +#endif + + +/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ +/* vim: set ts=4 sw=4 et: */ From patchwork Wed Nov 11 16:17:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cupertino Miranda X-Patchwork-Id: 1398390 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2001:8b0:10b:1231::1; helo=merlin.infradead.org; envelope-from=linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=merlin.20170209 header.b=w8PLs12P; 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[2.80.104.46]) by smtp.gmail.com with ESMTPSA id s188sm3115178wmf.45.2020.11.11.08.18.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2020 08:18:12 -0800 (PST) From: cupertinomiranda@gmail.com To: qemu-devel@nongnu.org Subject: [PATCH 06/15] arc: TCG instruction definitions Date: Wed, 11 Nov 2020 16:17:49 +0000 Message-Id: <20201111161758.9636-7-cupertinomiranda@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201111161758.9636-1-cupertinomiranda@gmail.com> References: <20201111161758.9636-1-cupertinomiranda@gmail.com> MIME-Version: 1.0 X-Spam-Note: CRM114 run bypassed due to message size (271909 bytes) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:332 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [cupertinomiranda[at]gmail.com] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Claudiu Zissulescu , Cupertino Miranda , Shahab Vahedi , Shahab Vahedi , Cupertino Miranda , linux-snps-arc@lists.infradead.org, Claudiu Zissulescu Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Cupertino Miranda TCG definitions as defined by our domain-specific-language (DSL) ISA infrastructure. Signed-off-by: Cupertino Miranda --- target/arc/semfunc-helper.c | 493 ++ target/arc/semfunc-helper.h | 280 ++ target/arc/semfunc.c | 8473 +++++++++++++++++++++++++++++++++++ target/arc/semfunc.h | 62 + 4 files changed, 9308 insertions(+) create mode 100644 target/arc/semfunc-helper.c create mode 100644 target/arc/semfunc-helper.h create mode 100644 target/arc/semfunc.c create mode 100644 target/arc/semfunc.h diff --git a/target/arc/semfunc-helper.c b/target/arc/semfunc-helper.c new file mode 100644 index 0000000000..b84c2252f4 --- /dev/null +++ b/target/arc/semfunc-helper.c @@ -0,0 +1,493 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synppsys Inc. + * Contributed by Cupertino Miranda + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#include "qemu/osdep.h" +#include "translate.h" +#include "qemu/bitops.h" +#include "tcg/tcg.h" +#include "semfunc-helper.h" +#include "translate.h" + +void arc_gen_verifyCCFlag(const DisasCtxt *ctx, TCGv ret) +{ + TCGv c1 = tcg_temp_new_i32(); + + TCGv nZ = tcg_temp_new_i32(); + TCGv nN = tcg_temp_new_i32(); + TCGv nV = tcg_temp_new_i32(); + TCGv nC = tcg_temp_new_i32(); + + switch (ctx->insn.cc) { + /* AL, RA */ + case 0x00: + tcg_gen_movi_i32(ret, 1); + break; + /* EQ, Z */ + case 0x01: + tcg_gen_mov_i32(ret, cpu_Zf); + break; + /* NE, NZ */ + case 0x02: + tcg_gen_xori_tl(ret, cpu_Zf, 1); + break; + /* PL, P */ + case 0x03: + tcg_gen_xori_tl(ret, cpu_Nf, 1); + break; + /* MI, N: */ + case 0x04: + tcg_gen_mov_i32(ret, cpu_Nf); + break; + /* CS, C, LO */ + case 0x05: + tcg_gen_mov_i32(ret, cpu_Cf); + break; + /* CC, NC, HS */ + case 0x06: + tcg_gen_xori_tl(ret, cpu_Cf, 1); + break; + /* VS, V */ + case 0x07: + tcg_gen_mov_i32(ret, cpu_Vf); + break; + /* VC, NV */ + case 0x08: + tcg_gen_xori_tl(ret, cpu_Vf, 1); + break; + /* GT */ + case 0x09: + /* (N & V & !Z) | (!N & !V & !Z) */ + tcg_gen_xori_tl(nZ, cpu_Zf, 1); + tcg_gen_xori_tl(nN, cpu_Nf, 1); + tcg_gen_xori_tl(nV, cpu_Vf, 1); + + tcg_gen_mov_tl(c1, cpu_Nf); + tcg_gen_and_tl(c1, c1, cpu_Vf); + tcg_gen_and_tl(c1, c1, nZ); + + tcg_gen_mov_tl(ret, nN); + tcg_gen_and_tl(ret, ret, nV); + tcg_gen_and_tl(ret, ret, nZ); + + tcg_gen_or_tl(ret, c1, ret); + break; + /* GE */ + case 0x0A: + /* (N & V) | (!N & !V) */ + tcg_gen_xori_tl(nN, cpu_Nf, 1); + tcg_gen_xori_tl(nV, cpu_Vf, 1); + + tcg_gen_and_tl(c1, cpu_Nf, cpu_Vf); + + tcg_gen_and_tl(ret, nN, nV); + + tcg_gen_or_tl(ret, c1, ret); + break; + /* LT */ + case 0x0B: + /* (N & !V) | (!N & V) */ + tcg_gen_xori_tl(nN, cpu_Nf, 1); + tcg_gen_xori_tl(nV, cpu_Vf, 1); + + tcg_gen_and_tl(c1, cpu_Nf, nV); + + tcg_gen_and_tl(ret, nN, cpu_Vf); + + tcg_gen_or_tl(ret, ret, c1); + break; + /* LE */ + case 0x0C: + /* Z | (N & !V) | (!N & V) */ + tcg_gen_xori_tl(nN, cpu_Nf, 1); + tcg_gen_xori_tl(nV, cpu_Vf, 1); + + tcg_gen_and_tl(c1, cpu_Nf, nV); + + tcg_gen_and_tl(ret, nN, cpu_Vf); + + tcg_gen_or_tl(ret, ret, c1); + + tcg_gen_or_tl(ret, ret, cpu_Zf); + break; + /* HI */ + case 0x0D: + /* !C & !Z */ + tcg_gen_xori_tl(nC, cpu_Cf, 1); + tcg_gen_xori_tl(nZ, cpu_Zf, 1); + + tcg_gen_and_tl(ret, nC, nZ); + break; + /* LS */ + case 0x0E: + /* C & Z */ + tcg_gen_or_tl(ret, cpu_Cf, cpu_Zf); + break; + /* PNZ */ + case 0x0F: + /* !N & !Z */ + tcg_gen_xori_tl(nN, cpu_Nf, 1); + tcg_gen_xori_tl(nZ, cpu_Zf, 1); + + tcg_gen_and_tl(ret, nN, nZ); + break; + } + + tcg_temp_free_i32(c1); + tcg_temp_free_i32(nZ); + tcg_temp_free_i32(nN); + tcg_temp_free_i32(nV); + tcg_temp_free_i32(nC); +} + +#define MEMIDX (ctx->mem_idx) + +void arc_gen_set_memory(DisasCtxt *ctx, TCGv vaddr, int size, + TCGv src, bool sign_extend) +{ + switch (size) { + case 0x00: + tcg_gen_qemu_st_tl(src, vaddr, MEMIDX, MO_UL); + break; + + case 0x01: + if (sign_extend) { + tcg_gen_qemu_st_tl(src, vaddr, MEMIDX, MO_SB); + } else { + tcg_gen_qemu_st_tl(src, vaddr, MEMIDX, MO_UB); + } + break; + + case 0x02: + if (sign_extend) { + tcg_gen_qemu_st_tl(src, vaddr, MEMIDX, MO_SW); + } else { + tcg_gen_qemu_st_tl(src, vaddr, MEMIDX, MO_UW); + } + break; + + case 0x03: + assert(!"reserved"); + break; + } +} + +void arc_gen_get_memory(DisasCtxt *ctx, TCGv dest, TCGv vaddr, + int size, bool sign_extend) +{ + switch (size) { + case 0x00: + tcg_gen_qemu_ld_tl(dest, vaddr, MEMIDX, MO_UL); + break; + + case 0x01: + if (sign_extend) { + tcg_gen_qemu_ld_tl(dest, vaddr, MEMIDX, MO_SB); + } else { + tcg_gen_qemu_ld_tl(dest, vaddr, MEMIDX, MO_UB); + } + break; + + case 0x02: + if (sign_extend) { + tcg_gen_qemu_ld_tl(dest, vaddr, MEMIDX, MO_SW); + } else { + tcg_gen_qemu_ld_tl(dest, vaddr, MEMIDX, MO_UW); + } + break; + + case 0x03: + assert(!"reserved"); + break; + } +} + + +void arc_gen_no_further_loads_pending(DisasCtxt *ctx, TCGv ret) +{ + tcg_gen_movi_tl(ret, 1); +} + +void arc_gen_set_debug(DisasCtxt *ctx, bool value) +{ + /* TODO: Could not find a reson to set this. */ +} + +extern bool enabled_interrupts; +void +arc_gen_execute_delayslot(DisasCtxt *ctx, TCGv bta, TCGv take_branch) +{ + static int in_delay_slot = false; + + assert(ctx->insn.limm_p == 0 && !in_delay_slot); + + if (ctx->insn.limm_p == 0 && !in_delay_slot) { + in_delay_slot = true; + uint32_t cpc = ctx->cpc; + uint32_t pcl = ctx->pcl; + insn_t insn = ctx->insn; + + ctx->cpc = ctx->npc; + ctx->pcl = ctx->cpc & 0xfffffffc; + + ++ctx->ds; + + TCGLabel *do_not_set_bta_and_de = gen_new_label(); + tcg_gen_brcondi_i32(TCG_COND_NE, take_branch, 1, do_not_set_bta_and_de); + /* + * In case an exception should be raised during the execution + * of delay slot, bta value is used to set erbta. + */ + tcg_gen_mov_tl(cpu_bta, bta); + /* We are in a delay slot */ + tcg_gen_mov_tl(cpu_DEf, take_branch); + gen_set_label(do_not_set_bta_and_de); + + tcg_gen_movi_tl(cpu_is_delay_slot_instruction, 1); + + /* Set the pc to the next pc */ + tcg_gen_movi_tl(cpu_pc, ctx->npc); + /* Necessary for the likely call to restore_state_to_opc() */ + tcg_gen_insn_start(ctx->npc); + + DisasJumpType type = ctx->base.is_jmp; + enabled_interrupts = false; + + /* + * In case we might be in a situation where the delayslot is in a + * different MMU page. Make a fake exception to interrupt + * delayslot execution in the context of the branch. + * The delayslot will then be re-executed in isolation after the + * branch code has set bta and DEf status flag. + */ + if ((cpc & PAGE_MASK) < 0x80000000 && + (cpc & PAGE_MASK) != (ctx->cpc & PAGE_MASK)) { + in_delay_slot = false; + TCGv dpc = tcg_const_local_i32(ctx->npc); + tcg_gen_mov_tl(cpu_pc, dpc); + gen_helper_fake_exception(cpu_env, dpc); + tcg_temp_free_i32(dpc); + return; + } + + decode_opc(ctx->env, ctx); + enabled_interrupts = true; + ctx->base.is_jmp = type; + + tcg_gen_movi_tl(cpu_DEf, 0); + tcg_gen_movi_tl(cpu_is_delay_slot_instruction, 0); + + /* Restore the pc back */ + tcg_gen_movi_tl(cpu_pc, cpc); + /* Again, restore_state_to_opc() must use recent value */ + tcg_gen_insn_start(cpc); + + assert(ctx->base.is_jmp == DISAS_NEXT); + + --ctx->ds; + + /* Restore old values. */ + ctx->cpc = cpc; + ctx->pcl = pcl; + ctx->insn = insn; + in_delay_slot = false; + } + return; +} + + +/* dest = src1 - src2. Compute C, N, V and Z flags */ +void arc_gen_sub_Cf(TCGv ret, TCGv dest, TCGv src1, TCGv src2) +{ + TCGv t1 = tcg_temp_new_i32(); + TCGv t2 = tcg_temp_new_i32(); + TCGv t3 = tcg_temp_new_i32(); + + tcg_gen_not_tl(t1, src1); /* t1 = ~src1 */ + tcg_gen_and_tl(t2, t1, src2); /* t2 = ~src1 & src2 */ + tcg_gen_or_tl(t3, t1, src2); /* t3 = (~src1 | src2) & dest */ + tcg_gen_and_tl(t3, t3, dest); + /* t2 = ~src1 & src2 | ~src1 & dest | dest & src2 */ + tcg_gen_or_tl(t2, t2, t3); + tcg_gen_shri_tl(ret, t2, 31); /* Cf = t2(31) */ + + tcg_temp_free_i32(t3); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t1); +} + + +void arc_gen_get_bit(TCGv ret, TCGv a, TCGv pos) +{ + tcg_gen_rotr_i32(ret, a, pos); + tcg_gen_andi_tl(ret, ret, 1); +} + +/* accumulator += b32 * c32 */ +void arc_gen_mac(TCGv phi, TCGv_i32 b32, TCGv_i32 c32) +{ + TCGv_i32 plo = tcg_temp_new_i32(); + tcg_gen_muls2_i32(plo, phi, b32, c32); + + /* Adding the product to the accumulator */ + tcg_gen_add2_i32(cpu_acclo, cpu_acchi, cpu_acclo, cpu_acchi, plo, phi); + tcg_temp_free(plo); +} + +/* Unsigned version of mac */ +void arc_gen_macu(TCGv phi, TCGv_i32 b32, TCGv_i32 c32) +{ + TCGv_i32 plo = tcg_temp_new_i32(); + tcg_gen_mulu2_i32(plo, phi, b32, c32); + + /* Adding the product to the accumulator */ + tcg_gen_add2_i32(cpu_acclo, cpu_acchi, cpu_acclo, cpu_acchi, plo, phi); + tcg_temp_free(plo); +} + +/* TODO: A better name would be tcg_gen_shil_i32() */ +void tcg_gen_shlfi_i32(TCGv a, int b, TCGv c) +{ + TCGv tmp = tcg_temp_new_i32(); + tcg_gen_movi_i32(tmp, b); + tcg_gen_shl_i32(a, tmp, c); + tcg_temp_free(tmp); +} + +/* TODO: A gen_helper() would be better for this purpose */ +void arc_gen_extract_bits(TCGv ret, TCGv a, TCGv start, TCGv end) +{ + TCGv tmp1 = tcg_temp_new_i32(); + + tcg_gen_shr_i32(ret, a, end); + + tcg_gen_sub_i32(tmp1, start, end); + tcg_gen_addi_i32(tmp1, tmp1, 1); + tcg_gen_shlfi_i32(tmp1, 1, tmp1); + tcg_gen_subi_i32(tmp1, tmp1, 1); + + tcg_gen_and_i32(ret, ret, tmp1); + + tcg_temp_free(tmp1); +} + + +void arc_gen_get_register(TCGv ret, enum arc_registers reg) +{ + switch (reg) { + case R_SP: + tcg_gen_mov_i32(ret, cpu_sp); + break; + case R_STATUS32: + gen_helper_get_status32(ret, cpu_env); + break; + case R_ACCLO: + tcg_gen_mov_i32(ret, cpu_acclo); + break; + case R_ACCHI: + tcg_gen_mov_i32(ret, cpu_acchi); + break; + default: + g_assert_not_reached(); + } +} + + +void arc_gen_set_register(enum arc_registers reg, TCGv value) +{ + switch (reg) { + case R_SP: + tcg_gen_mov_i32(cpu_sp, value); + break; + case R_STATUS32: + gen_helper_set_status32(cpu_env, value); + break; + case R_ACCLO: + tcg_gen_mov_i32(cpu_acclo, value); + break; + case R_ACCHI: + tcg_gen_mov_i32(cpu_acchi, value); + break; + default: + g_assert_not_reached(); + } +} + + +/* TODO: Get this from props ... */ +void arc_has_interrupts(DisasCtxt *ctx, TCGv ret) +{ + tcg_gen_movi_i32(ret, 1); +} + +/* + *************************************** + * Statically inferred return function * + *************************************** + */ + +TCGv arc_gen_next_reg(const DisasCtxt *ctx, TCGv reg) +{ + int i; + for (i = 0; i < 64; i += 2) { + if (reg == cpu_r[i]) { + return cpu_r[i + 1]; + } + } + /* Check if REG is an odd register. */ + for (i = 1; i < 64; i += 2) { + /* If so, that is unsanctioned. */ + if (reg == cpu_r[i]) { + arc_gen_excp(ctx, EXCP_INST_ERROR, 0, 0); + return NULL; + } + } + /* REG was not a register after all. */ + g_assert_not_reached(); + + /* We never get here, but to accommodate -Werror ... */ + return NULL; +} + +bool arc_target_has_option(enum target_options option) +{ + /* TODO: Fill with meaningful cases. */ + switch (option) { + case LL64_OPTION: + return true; + break; + default: + break; + } + return false; +} + + +bool arc_is_instruction_operand_a_register(const DisasCtxt *ctx, int nop) +{ + assert(nop < ctx->insn.n_ops); + operand_t operand = ctx->insn.operands[nop]; + + return (operand.type & ARC_OPERAND_IR) != 0; +} + + +/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ +/* vim: set ts=4 sw=4 et: */ diff --git a/target/arc/semfunc-helper.h b/target/arc/semfunc-helper.h new file mode 100644 index 0000000000..3ac6b47dac --- /dev/null +++ b/target/arc/semfunc-helper.h @@ -0,0 +1,280 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synppsys Inc. + * Contributed by Cupertino Miranda + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#ifndef TRANSLATE_INST_H_ +#define TRANSLATE_INST_H_ + +#include "translate.h" +#include "qemu/bitops.h" +#include "tcg/tcg.h" +#include "target/arc/regs.h" + +typedef enum ARC_COND { + ARC_COND_AL = 0x00, + ARC_COND_RA = 0x00, + ARC_COND_EQ = 0x01, + ARC_COND_Z = 0x01, + ARC_COND_NE = 0x02, + ARC_COND_NZ = 0x02, + ARC_COND_PL = 0x03, + ARC_COND_P = 0x03, + ARC_COND_MI = 0x04, + ARC_COND_N = 0x04, + ARC_COND_CS = 0x05, + ARC_COND_C = 0x05, + ARC_COND_LO = 0x05, + ARC_COND_CC = 0x06, + ARC_COND_NC = 0x06, + ARC_COND_HS = 0x06, + ARC_COND_VS = 0x07, + ARC_COND_V = 0x07, + ARC_COND_VC = 0x08, + ARC_COND_NV = 0x08, + ARC_COND_GT = 0x09, + ARC_COND_GE = 0x0a, + ARC_COND_LT = 0x0b, + ARC_COND_LE = 0x0c, + ARC_COND_HI = 0x0d, + ARC_COND_LS = 0x0e, + ARC_COND_PNZ = 0x0f, +} ARC_COND; + +#define ARC_HELPER(NAME, RET, ...) \ + gen_helper_##NAME(RET, cpu_env, __VA_ARGS__) + +enum arc_registers { + R_SP = 0, + R_STATUS32, + R_ACCLO, + R_ACCHI +}; + +enum target_options { + INVALID_TARGET_OPTIONS = -1, + DIV_REM_OPTION, + STACK_CHECKING, + LL64_OPTION +}; + +/* TODO: Change this to allow something else then ARC HS. */ +#define LP_START \ + (arc_aux_reg_address_for(AUX_ID_lp_start, ARC_OPCODE_ARCv2HS)) +#define LP_END \ + (arc_aux_reg_address_for(AUX_ID_lp_end, ARC_OPCODE_ARCv2HS)) + +#define ReplMask(DEST, SRC, MASK) \ + gen_helper_repl_mask(DEST, DEST, SRC, MASK) + +void arc_gen_verifyCCFlag(const DisasCtxt *ctx, TCGv ret); +#define getCCFlag(R) arc_gen_verifyCCFlag(ctx, R) + +#define getFFlag(R) ((int) ctx->insn.f) + +void to_implement(DisasCtxt *ctx); +void to_implement_wo_abort(DisasCtxt *ctx); + +#define killDelaySlot() +void arc_gen_set_memory( + DisasCtxt *ctx, TCGv addr, int size, TCGv src, bool sign_extend); +#define setMemory(ADDRESS, SIZE, VALUE) \ + arc_gen_set_memory(ctx, ADDRESS, SIZE, VALUE, getFlagX()) +void arc_gen_get_memory( + DisasCtxt *ctx, TCGv ret, TCGv addr, int size, bool sign_extend); +#define getMemory(R, ADDRESS, SIZE) \ + arc_gen_get_memory(ctx, R, ADDRESS, SIZE, getFlagX()) + +#define getFlagX() (ctx->insn.x) +#define getZZFlag() (ctx->insn.zz) +#define getAAFlag() (ctx->insn.aa) + +#define SignExtend(VALUE, SIZE) VALUE +void arc_gen_no_further_loads_pending(DisasCtxt *ctx, TCGv ret); +#define NoFurtherLoadsPending(R) arc_gen_no_further_loads_pending(ctx, R) +void arc_gen_set_debug(DisasCtxt *ctx, bool value); +#define setDebugLD(A) arc_gen_set_debug(ctx, A) +void arc_gen_execute_delayslot(DisasCtxt *ctx, TCGv bta, TCGv take_branch); +#define executeDelaySlot(bta, take_branch) \ + arc_gen_execute_delayslot(ctx, bta, take_branch) + +#define shouldExecuteDelaySlot() (ctx->insn.d != 0) + +#define setNFlag(ELEM) tcg_gen_shri_tl(cpu_Nf, ELEM, 31) +#define getNFlag(R) cpu_Nf + +#define setCFlag(ELEM) tcg_gen_mov_tl(cpu_Cf, ELEM) +#define getCFlag(R) tcg_gen_mov_tl(R, cpu_Cf) + +#define setVFlag(ELEM) tcg_gen_mov_tl(cpu_Vf, ELEM) + +#define setZFlag(ELEM) \ + tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_Zf, ELEM, 0); + +#define nextInsnAddressAfterDelaySlot(R) \ + { \ + uint16_t delayslot_buffer[2]; \ + uint8_t delayslot_length; \ + ctx->env->pc = ctx->cpc; \ + ctx->env->stat.is_delay_slot_instruction = 1; \ + delayslot_buffer[0] = cpu_lduw_code(ctx->env, ctx->npc); \ + delayslot_length = arc_insn_length(delayslot_buffer[0], ctx->env->family); \ + tcg_gen_movi_tl(R, ctx->npc + delayslot_length); \ + } + +#define nextInsnAddress(R) tcg_gen_movi_tl(R, ctx->npc) +#define getPCL(R) tcg_gen_movi_tl(R, ctx->pcl) + +#define setPC(NEW_PC) \ + do { \ + gen_goto_tb(ctx, 1, NEW_PC); \ + ret = ret == DISAS_NEXT ? DISAS_NORETURN : ret; \ + } while (0) + +#define setBLINK(BLINK_ADDR) \ + tcg_gen_mov_i32(cpu_blink, BLINK_ADDR); + +#define Carry(R, A) tcg_gen_shri_tl(R, A, 31); + +#define CarryADD(R, A, B, C) gen_helper_carry_add_flag(R, A, B, C) +#define OverflowADD(R, A, B, C) gen_helper_overflow_add_flag(R, A, B, C) + +void arc_gen_sub_Cf(TCGv ret, TCGv dest, TCGv src1, TCGv src2); +#define CarrySUB(R, A, B, C) arc_gen_sub_Cf(R, A, B, C) +#define OverflowSUB(R, A, B, C) gen_helper_overflow_sub_flag(R, A, B, C) + +#define unsignedLT(R, B, C) tcg_gen_setcond_i32(TCG_COND_LTU, R, B, C) +#define unsignedGE(R, B, C) tcg_gen_setcond_i32(TCG_COND_GEU, R, B, C) +#define logicalShiftRight(R, B, C) tcg_gen_shr_i32(R, B, C) +#define logicalShiftLeft(R, B, C) tcg_gen_shl_i32(R, B, C) +#define arithmeticShiftRight(R, B, C) tcg_gen_sar_i32(R, B, C) +#define rotateLeft(R, B, C) tcg_gen_rotl_i32(R, B, C) +#define rotateRight(R, B, C) tcg_gen_rotr_i32(R, B, C) + +void arc_gen_get_bit(TCGv ret, TCGv a, TCGv pos); +#define getBit(R, A, POS) arc_gen_get_bit(R, A, POS) + +#define getRegIndex(R, ID) tcg_gen_movi_tl(R, (int) ID) + +#define readAuxReg(R, A) gen_helper_lr(R, cpu_env, A) +/* + * Here, by returning DISAS_UPDATE we are making SR the end + * of a Translation Block (TB). This is necessary because + * sometimes writing to control registers updates how a TB is + * handled, like enabling MMU/MPU. If SR is not marked as the + * end, the next instructions are fetched and generated and + * the updated outcome (page/region permissions) is not taken + * into account. + */ +#define writeAuxReg(NAME, B) \ + do { \ + gen_helper_sr(cpu_env, B, NAME); \ + ret = DISAS_UPDATE; \ + } while (0) + +/* + * At the end of a SYNC instruction, it is guaranteed that + * handling the current interrupt is finished and the raising + * pulse signal (if any), is cleared. By marking SYNC as the + * end of a TB we gave a chance to interrupt threads to execute. + */ +#define syncReturnDisasUpdate() (ret = DISAS_UPDATE) + +/* + * An enter_s may change code like below: + * ---- + * r13 .. r26 <== shell opcodes + * sp <= pc+56 + * enter_s + * --- + * It's not that we are promoting these type of instructions. + * nevertheless we must be able to emulate them. Hence, once + * again: ret = DISAS_UPDATE + */ +#define helperEnter(U6) \ + do { \ + gen_helper_enter(cpu_env, U6); \ + ret = DISAS_UPDATE; \ + } while (0) + +/* A leave_s may jump to blink, hence the DISAS_UPDATE */ +#define helperLeave(U7) \ + do { \ + tcg_gen_movi_tl(cpu_pc, ctx->cpc); \ + gen_helper_leave(cpu_env, U7); \ + TCGv jump_to_blink = tcg_temp_local_new_i32(); \ + TCGLabel *done = gen_new_label(); \ + tcg_gen_shri_i32(jump_to_blink, U7, 6); \ + tcg_gen_brcondi_i32(TCG_COND_EQ, jump_to_blink, 0, done); \ + gen_goto_tb(ctx, 1, cpu_pc); \ + ret = DISAS_NORETURN; \ + gen_set_label(done); \ + tcg_temp_free(jump_to_blink); \ + } while (0) + +void arc_gen_mac(TCGv phi, TCGv_i32 b, TCGv_i32 c); +#define MAC(R, B, C) arc_gen_mac(R, B, C) +void arc_gen_macu(TCGv phi, TCGv_i32 b, TCGv_i32 c); +#define MACU(R, B, C) arc_gen_macu(R, B, C) + +void arc_gen_extract_bits(TCGv ret, TCGv a, TCGv start, TCGv end); +#define extractBits(R, ELEM, START, END) \ + arc_gen_extract_bits(R, ELEM, START, END) +void arc_gen_get_register(TCGv ret, enum arc_registers reg); +#define getRegister(R, REG) arc_gen_get_register(R, REG) +void arc_gen_set_register(enum arc_registers reg, TCGv value); +#define setRegister(REG, VALUE) arc_gen_set_register(REG, VALUE) + +#define divSigned(R, SRC1, SRC2) tcg_gen_div_i32(R, SRC1, SRC2) +#define divUnsigned(R, SRC1, SRC2) tcg_gen_divu_i32(R, SRC1, SRC2) +#define divRemainingSigned(R, SRC1, SRC2) tcg_gen_rem_i32(R, SRC1, SRC2) +#define divRemainingUnsigned(R, SRC1, SRC2) tcg_gen_remu_i32(R, SRC1, SRC2) + +/* TODO: To implement */ +#define Halt() + +void arc_has_interrupts(DisasCtxt *ctx, TCGv ret); +#define hasInterrupts(R) arc_has_interrupts(ctx, R) +#define doNothing() + +#define setLF(VALUE) tcg_gen_mov_tl(cpu_lock_lf_var, VALUE) +#define getLF(R) tcg_gen_mov_tl(R, cpu_lock_lf_var) + +/* Statically inferred return function */ + +TCGv arc_gen_next_reg(const DisasCtxt *ctx, TCGv reg); +#define nextReg(A) arc_gen_next_reg(ctx, A) + +/* TODO (issue #62): This must be removed. */ +#define Zero() (ctx->zero) + +bool arc_target_has_option(enum target_options option); +#define targetHasOption(OPTION) arc_target_has_option(OPTION) + +bool arc_is_instruction_operand_a_register(const DisasCtxt *ctx, int nop); +#define instructionHasRegisterOperandIn(NOP) \ + arc_is_instruction_operand_a_register(ctx, NOP) + +void tcg_gen_shlfi_i32(TCGv a, int b, TCGv c); + +#endif /* TRANSLATE_INST_H_ */ + + +/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ +/* vim: set ts=4 sw=4 et: */ diff --git a/target/arc/semfunc.c b/target/arc/semfunc.c new file mode 100644 index 0000000000..dc81563cc4 --- /dev/null +++ b/target/arc/semfunc.c @@ -0,0 +1,8473 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synppsys Inc. + * Contributed by Cupertino Miranda + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#include "qemu/osdep.h" +#include "translate.h" +#include "target/arc/semfunc.h" + +/* + * FLAG + * Variables: @src + * Functions: getCCFlag, getRegister, getBit, hasInterrupts, Halt, ReplMask, + * targetHasOption, setRegister + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * status32 = getRegister (R_STATUS32); + * if(((getBit (@src, 0) == 1) && (getBit (status32, 7) == 0))) + * { + * if((hasInterrupts () > 0)) + * { + * status32 = (status32 | 1); + * Halt (); + * }; + * } + * else + * { + * ReplMask (status32, @src, 3840); + * if(((getBit (status32, 7) == 0) && (hasInterrupts () > 0))) + * { + * ReplMask (status32, @src, 30); + * if(targetHasOption (DIV_REM_OPTION)) + * { + * ReplMask (status32, @src, 8192); + * }; + * if(targetHasOption (STACK_CHECKING)) + * { + * ReplMask (status32, @src, 16384); + * }; + * if(targetHasOption (LL64_OPTION)) + * { + * ReplMask (status32, @src, 524288); + * }; + * ReplMask (status32, @src, 1048576); + * }; + * }; + * setRegister (R_STATUS32, status32); + * }; + * } + */ + +int +arc_gen_FLAG(DisasCtxt *ctx, TCGv src) +{ + int ret = DISAS_NEXT; + TCGv temp_13 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_14 = tcg_temp_local_new_i32(); + TCGv status32 = tcg_temp_local_new_i32(); + TCGv temp_16 = tcg_temp_local_new_i32(); + TCGv temp_15 = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_18 = tcg_temp_local_new_i32(); + TCGv temp_17 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_19 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_20 = tcg_temp_local_new_i32(); + TCGv temp_22 = tcg_temp_local_new_i32(); + TCGv temp_21 = tcg_temp_local_new_i32(); + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv temp_23 = tcg_temp_local_new_i32(); + TCGv temp_10 = tcg_temp_local_new_i32(); + TCGv temp_11 = tcg_temp_local_new_i32(); + TCGv temp_12 = tcg_temp_local_new_i32(); + TCGv temp_24 = tcg_temp_local_new_i32(); + TCGv temp_25 = tcg_temp_local_new_i32(); + TCGv temp_26 = tcg_temp_local_new_i32(); + TCGv temp_27 = tcg_temp_local_new_i32(); + TCGv temp_28 = tcg_temp_local_new_i32(); + getCCFlag(temp_13); + tcg_gen_mov_i32(cc_flag, temp_13); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + getRegister(temp_14, R_STATUS32); + tcg_gen_mov_i32(status32, temp_14); + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_movi_i32(temp_16, 0); + getBit(temp_15, src, temp_16); + tcg_gen_setcondi_i32(TCG_COND_EQ, temp_3, temp_15, 1); + tcg_gen_movi_i32(temp_18, 7); + getBit(temp_17, status32, temp_18); + tcg_gen_setcondi_i32(TCG_COND_EQ, temp_4, temp_17, 0); + tcg_gen_and_i32(temp_5, temp_3, temp_4); + tcg_gen_xori_i32(temp_6, temp_5, 1); + tcg_gen_andi_i32(temp_6, temp_6, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_6, arc_true, else_2); + TCGLabel *done_3 = gen_new_label(); + hasInterrupts(temp_19); + tcg_gen_setcondi_i32(TCG_COND_GT, temp_7, temp_19, 0); + tcg_gen_xori_i32(temp_8, temp_7, 1); + tcg_gen_andi_i32(temp_8, temp_8, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_8, arc_true, done_3); + tcg_gen_ori_i32(status32, status32, 1); + Halt(); + gen_set_label(done_3); + tcg_gen_br(done_2); + gen_set_label(else_2); + tcg_gen_movi_i32(temp_20, 3840); + ReplMask(status32, src, temp_20); + TCGLabel *done_4 = gen_new_label(); + tcg_gen_movi_i32(temp_22, 7); + getBit(temp_21, status32, temp_22); + tcg_gen_setcondi_i32(TCG_COND_EQ, temp_9, temp_21, 0); + hasInterrupts(temp_23); + tcg_gen_setcondi_i32(TCG_COND_GT, temp_10, temp_23, 0); + tcg_gen_and_i32(temp_11, temp_9, temp_10); + tcg_gen_xori_i32(temp_12, temp_11, 1); + tcg_gen_andi_i32(temp_12, temp_12, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_12, arc_true, done_4); + tcg_gen_movi_i32(temp_24, 30); + ReplMask(status32, src, temp_24); + if (targetHasOption (DIV_REM_OPTION)) { + tcg_gen_movi_i32(temp_25, 8192); + ReplMask(status32, src, temp_25); + } + if (targetHasOption (STACK_CHECKING)) { + tcg_gen_movi_i32(temp_26, 16384); + ReplMask(status32, src, temp_26); + } + if (targetHasOption (LL64_OPTION)) { + tcg_gen_movi_i32(temp_27, 524288); + ReplMask(status32, src, temp_27); + } + tcg_gen_movi_i32(temp_28, 1048576); + ReplMask(status32, src, temp_28); + gen_set_label(done_4); + gen_set_label(done_2); + setRegister(R_STATUS32, status32); + gen_set_label(done_1); + tcg_temp_free(temp_13); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_14); + tcg_temp_free(status32); + tcg_temp_free(temp_16); + tcg_temp_free(temp_15); + tcg_temp_free(temp_3); + tcg_temp_free(temp_18); + tcg_temp_free(temp_17); + tcg_temp_free(temp_4); + tcg_temp_free(temp_5); + tcg_temp_free(temp_6); + tcg_temp_free(temp_19); + tcg_temp_free(temp_7); + tcg_temp_free(temp_8); + tcg_temp_free(temp_20); + tcg_temp_free(temp_22); + tcg_temp_free(temp_21); + tcg_temp_free(temp_9); + tcg_temp_free(temp_23); + tcg_temp_free(temp_10); + tcg_temp_free(temp_11); + tcg_temp_free(temp_12); + tcg_temp_free(temp_24); + tcg_temp_free(temp_25); + tcg_temp_free(temp_26); + tcg_temp_free(temp_27); + tcg_temp_free(temp_28); + + return ret; +} + + +/* + * KFLAG + * Variables: @src + * Functions: getCCFlag, getRegister, getBit, hasInterrupts, Halt, ReplMask, + * targetHasOption, setRegister + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * status32 = getRegister (R_STATUS32); + * if(((getBit (@src, 0) == 1) && (getBit (status32, 7) == 0))) + * { + * if((hasInterrupts () > 0)) + * { + * status32 = (status32 | 1); + * Halt (); + * }; + * } + * else + * { + * ReplMask (status32, @src, 3840); + * if(((getBit (status32, 7) == 0) && (hasInterrupts () > 0))) + * { + * ReplMask (status32, @src, 62); + * if(targetHasOption (DIV_REM_OPTION)) + * { + * ReplMask (status32, @src, 8192); + * }; + * if(targetHasOption (STACK_CHECKING)) + * { + * ReplMask (status32, @src, 16384); + * }; + * ReplMask (status32, @src, 65536); + * if(targetHasOption (LL64_OPTION)) + * { + * ReplMask (status32, @src, 524288); + * }; + * ReplMask (status32, @src, 1048576); + * ReplMask (status32, @src, 2147483648); + * }; + * }; + * setRegister (R_STATUS32, status32); + * }; + * } + */ + +int +arc_gen_KFLAG(DisasCtxt *ctx, TCGv src) +{ + int ret = DISAS_NEXT; + TCGv temp_13 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_14 = tcg_temp_local_new_i32(); + TCGv status32 = tcg_temp_local_new_i32(); + TCGv temp_16 = tcg_temp_local_new_i32(); + TCGv temp_15 = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_18 = tcg_temp_local_new_i32(); + TCGv temp_17 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_19 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_20 = tcg_temp_local_new_i32(); + TCGv temp_22 = tcg_temp_local_new_i32(); + TCGv temp_21 = tcg_temp_local_new_i32(); + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv temp_23 = tcg_temp_local_new_i32(); + TCGv temp_10 = tcg_temp_local_new_i32(); + TCGv temp_11 = tcg_temp_local_new_i32(); + TCGv temp_12 = tcg_temp_local_new_i32(); + TCGv temp_24 = tcg_temp_local_new_i32(); + TCGv temp_25 = tcg_temp_local_new_i32(); + TCGv temp_26 = tcg_temp_local_new_i32(); + TCGv temp_27 = tcg_temp_local_new_i32(); + TCGv temp_28 = tcg_temp_local_new_i32(); + TCGv temp_29 = tcg_temp_local_new_i32(); + TCGv temp_30 = tcg_temp_local_new_i32(); + getCCFlag(temp_13); + tcg_gen_mov_i32(cc_flag, temp_13); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + getRegister(temp_14, R_STATUS32); + tcg_gen_mov_i32(status32, temp_14); + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_movi_i32(temp_16, 0); + getBit(temp_15, src, temp_16); + tcg_gen_setcondi_i32(TCG_COND_EQ, temp_3, temp_15, 1); + tcg_gen_movi_i32(temp_18, 7); + getBit(temp_17, status32, temp_18); + tcg_gen_setcondi_i32(TCG_COND_EQ, temp_4, temp_17, 0); + tcg_gen_and_i32(temp_5, temp_3, temp_4); + tcg_gen_xori_i32(temp_6, temp_5, 1); + tcg_gen_andi_i32(temp_6, temp_6, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_6, arc_true, else_2); + TCGLabel *done_3 = gen_new_label(); + hasInterrupts(temp_19); + tcg_gen_setcondi_i32(TCG_COND_GT, temp_7, temp_19, 0); + tcg_gen_xori_i32(temp_8, temp_7, 1); + tcg_gen_andi_i32(temp_8, temp_8, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_8, arc_true, done_3); + tcg_gen_ori_i32(status32, status32, 1); + Halt(); + gen_set_label(done_3); + tcg_gen_br(done_2); + gen_set_label(else_2); + tcg_gen_movi_i32(temp_20, 3840); + ReplMask(status32, src, temp_20); + TCGLabel *done_4 = gen_new_label(); + tcg_gen_movi_i32(temp_22, 7); + getBit(temp_21, status32, temp_22); + tcg_gen_setcondi_i32(TCG_COND_EQ, temp_9, temp_21, 0); + hasInterrupts(temp_23); + tcg_gen_setcondi_i32(TCG_COND_GT, temp_10, temp_23, 0); + tcg_gen_and_i32(temp_11, temp_9, temp_10); + tcg_gen_xori_i32(temp_12, temp_11, 1); + tcg_gen_andi_i32(temp_12, temp_12, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_12, arc_true, done_4); + tcg_gen_movi_i32(temp_24, 62); + ReplMask(status32, src, temp_24); + if (targetHasOption (DIV_REM_OPTION)) { + tcg_gen_movi_i32(temp_25, 8192); + ReplMask(status32, src, temp_25); + } + if (targetHasOption (STACK_CHECKING)) { + tcg_gen_movi_i32(temp_26, 16384); + ReplMask(status32, src, temp_26); + } + tcg_gen_movi_i32(temp_27, 65536); + ReplMask(status32, src, temp_27); + if (targetHasOption (LL64_OPTION)) { + tcg_gen_movi_i32(temp_28, 524288); + ReplMask(status32, src, temp_28); + } + tcg_gen_movi_i32(temp_29, 1048576); + ReplMask(status32, src, temp_29); + tcg_gen_movi_i32(temp_30, 2147483648); + ReplMask(status32, src, temp_30); + gen_set_label(done_4); + gen_set_label(done_2); + setRegister(R_STATUS32, status32); + gen_set_label(done_1); + tcg_temp_free(temp_13); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_14); + tcg_temp_free(status32); + tcg_temp_free(temp_16); + tcg_temp_free(temp_15); + tcg_temp_free(temp_3); + tcg_temp_free(temp_18); + tcg_temp_free(temp_17); + tcg_temp_free(temp_4); + tcg_temp_free(temp_5); + tcg_temp_free(temp_6); + tcg_temp_free(temp_19); + tcg_temp_free(temp_7); + tcg_temp_free(temp_8); + tcg_temp_free(temp_20); + tcg_temp_free(temp_22); + tcg_temp_free(temp_21); + tcg_temp_free(temp_9); + tcg_temp_free(temp_23); + tcg_temp_free(temp_10); + tcg_temp_free(temp_11); + tcg_temp_free(temp_12); + tcg_temp_free(temp_24); + tcg_temp_free(temp_25); + tcg_temp_free(temp_26); + tcg_temp_free(temp_27); + tcg_temp_free(temp_28); + tcg_temp_free(temp_29); + tcg_temp_free(temp_30); + + return ret; +} + + +/* + * ADD + * Variables: @b, @c, @a + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarryADD, + * setVFlag, OverflowADD + * --- code --- + * { + * cc_flag = getCCFlag (); + * lb = @b; + * lc = @c; + * if((cc_flag == true)) + * { + * lb = @b; + * lc = @c; + * @a = (@b + @c); + * if((getFFlag () == true)) + * { + * setZFlag (@a); + * setNFlag (@a); + * setCFlag (CarryADD (@a, lb, lc)); + * setVFlag (OverflowADD (@a, lb, lc)); + * }; + * }; + * } + */ + +int +arc_gen_ADD(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv lb = tcg_temp_local_new_i32(); + TCGv lc = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + tcg_gen_mov_i32(lb, b); + tcg_gen_mov_i32(lc, c); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lb, b); + tcg_gen_mov_i32(lc, c); + tcg_gen_add_i32(a, b, c); + if ((getFFlag () == true)) { + setZFlag(a); + setNFlag(a); + CarryADD(temp_5, a, lb, lc); + tcg_gen_mov_i32(temp_4, temp_5); + setCFlag(temp_4); + OverflowADD(temp_7, a, lb, lc); + tcg_gen_mov_i32(temp_6, temp_7); + setVFlag(temp_6); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(lb); + tcg_temp_free(lc); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + tcg_temp_free(temp_7); + tcg_temp_free(temp_6); + + return ret; +} + + +/* + * ADD1 + * Variables: @b, @c, @a + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarryADD, + * setVFlag, OverflowADD + * --- code --- + * { + * cc_flag = getCCFlag (); + * lb = @b; + * lc = @c; + * if((cc_flag == true)) + * { + * lb = @b; + * lc = @c; + * @a = (@b + (@c << 1)); + * if((getFFlag () == true)) + * { + * setZFlag (@a); + * setNFlag (@a); + * setCFlag (CarryADD (@a, lb, lc)); + * setVFlag (OverflowADD (@a, lb, lc)); + * }; + * }; + * } + */ + +int +arc_gen_ADD1(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv lb = tcg_temp_local_new_i32(); + TCGv lc = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + tcg_gen_mov_i32(lb, b); + tcg_gen_mov_i32(lc, c); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lb, b); + tcg_gen_mov_i32(lc, c); + tcg_gen_shli_i32(temp_4, c, 1); + tcg_gen_add_i32(a, b, temp_4); + if ((getFFlag () == true)) { + setZFlag(a); + setNFlag(a); + CarryADD(temp_6, a, lb, lc); + tcg_gen_mov_i32(temp_5, temp_6); + setCFlag(temp_5); + OverflowADD(temp_8, a, lb, lc); + tcg_gen_mov_i32(temp_7, temp_8); + setVFlag(temp_7); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(lb); + tcg_temp_free(lc); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_4); + tcg_temp_free(temp_6); + tcg_temp_free(temp_5); + tcg_temp_free(temp_8); + tcg_temp_free(temp_7); + + return ret; +} + + +/* + * ADD2 + * Variables: @b, @c, @a + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarryADD, + * setVFlag, OverflowADD + * --- code --- + * { + * cc_flag = getCCFlag (); + * lb = @b; + * lc = @c; + * if((cc_flag == true)) + * { + * lb = @b; + * lc = @c; + * @a = (@b + (@c << 2)); + * if((getFFlag () == true)) + * { + * setZFlag (@a); + * setNFlag (@a); + * setCFlag (CarryADD (@a, lb, lc)); + * setVFlag (OverflowADD (@a, lb, lc)); + * }; + * }; + * } + */ + +int +arc_gen_ADD2(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv lb = tcg_temp_local_new_i32(); + TCGv lc = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + tcg_gen_mov_i32(lb, b); + tcg_gen_mov_i32(lc, c); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lb, b); + tcg_gen_mov_i32(lc, c); + tcg_gen_shli_i32(temp_4, c, 2); + tcg_gen_add_i32(a, b, temp_4); + if ((getFFlag () == true)) { + setZFlag(a); + setNFlag(a); + CarryADD(temp_6, a, lb, lc); + tcg_gen_mov_i32(temp_5, temp_6); + setCFlag(temp_5); + OverflowADD(temp_8, a, lb, lc); + tcg_gen_mov_i32(temp_7, temp_8); + setVFlag(temp_7); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(lb); + tcg_temp_free(lc); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_4); + tcg_temp_free(temp_6); + tcg_temp_free(temp_5); + tcg_temp_free(temp_8); + tcg_temp_free(temp_7); + + return ret; +} + + +/* + * ADD3 + * Variables: @b, @c, @a + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarryADD, + * setVFlag, OverflowADD + * --- code --- + * { + * cc_flag = getCCFlag (); + * lb = @b; + * lc = @c; + * if((cc_flag == true)) + * { + * lb = @b; + * lc = @c; + * @a = (@b + (@c << 3)); + * if((getFFlag () == true)) + * { + * setZFlag (@a); + * setNFlag (@a); + * setCFlag (CarryADD (@a, lb, lc)); + * setVFlag (OverflowADD (@a, lb, lc)); + * }; + * }; + * } + */ + +int +arc_gen_ADD3(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv lb = tcg_temp_local_new_i32(); + TCGv lc = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + tcg_gen_mov_i32(lb, b); + tcg_gen_mov_i32(lc, c); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lb, b); + tcg_gen_mov_i32(lc, c); + tcg_gen_shli_i32(temp_4, c, 3); + tcg_gen_add_i32(a, b, temp_4); + if ((getFFlag () == true)) { + setZFlag(a); + setNFlag(a); + CarryADD(temp_6, a, lb, lc); + tcg_gen_mov_i32(temp_5, temp_6); + setCFlag(temp_5); + OverflowADD(temp_8, a, lb, lc); + tcg_gen_mov_i32(temp_7, temp_8); + setVFlag(temp_7); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(lb); + tcg_temp_free(lc); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_4); + tcg_temp_free(temp_6); + tcg_temp_free(temp_5); + tcg_temp_free(temp_8); + tcg_temp_free(temp_7); + + return ret; +} + + +/* + * ADC + * Variables: @b, @c, @a + * Functions: getCCFlag, getCFlag, getFFlag, setZFlag, setNFlag, setCFlag, + * CarryADD, setVFlag, OverflowADD + * --- code --- + * { + * cc_flag = getCCFlag (); + * lb = @b; + * lc = @c; + * if((cc_flag == true)) + * { + * lb = @b; + * lc = @c; + * @a = ((@b + @c) + getCFlag ()); + * if((getFFlag () == true)) + * { + * setZFlag (@a); + * setNFlag (@a); + * setCFlag (CarryADD (@a, lb, lc)); + * setVFlag (OverflowADD (@a, lb, lc)); + * }; + * }; + * } + */ + +int +arc_gen_ADC(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv lb = tcg_temp_local_new_i32(); + TCGv lc = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_10 = tcg_temp_local_new_i32(); + TCGv temp_9 = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + tcg_gen_mov_i32(lb, b); + tcg_gen_mov_i32(lc, c); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lb, b); + tcg_gen_mov_i32(lc, c); + tcg_gen_add_i32(temp_4, b, c); + getCFlag(temp_6); + tcg_gen_mov_i32(temp_5, temp_6); + tcg_gen_add_i32(a, temp_4, temp_5); + if ((getFFlag () == true)) { + setZFlag(a); + setNFlag(a); + CarryADD(temp_8, a, lb, lc); + tcg_gen_mov_i32(temp_7, temp_8); + setCFlag(temp_7); + OverflowADD(temp_10, a, lb, lc); + tcg_gen_mov_i32(temp_9, temp_10); + setVFlag(temp_9); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(lb); + tcg_temp_free(lc); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_4); + tcg_temp_free(temp_6); + tcg_temp_free(temp_5); + tcg_temp_free(temp_8); + tcg_temp_free(temp_7); + tcg_temp_free(temp_10); + tcg_temp_free(temp_9); + + return ret; +} + + +/* + * SBC + * Variables: @b, @c, @a + * Functions: getCCFlag, getCFlag, getFFlag, setZFlag, setNFlag, setCFlag, + * CarryADD, setVFlag, OverflowADD + * --- code --- + * { + * cc_flag = getCCFlag (); + * lb = @b; + * lc = @c; + * if((cc_flag == true)) + * { + * lb = @b; + * lc = @c; + * @a = ((@b - @c) - getCFlag ()); + * if((getFFlag () == true)) + * { + * setZFlag (@a); + * setNFlag (@a); + * setCFlag (CarryADD (@a, lb, lc)); + * setVFlag (OverflowADD (@a, lb, lc)); + * }; + * }; + * } + */ + +int +arc_gen_SBC(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv lb = tcg_temp_local_new_i32(); + TCGv lc = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_10 = tcg_temp_local_new_i32(); + TCGv temp_9 = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + tcg_gen_mov_i32(lb, b); + tcg_gen_mov_i32(lc, c); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lb, b); + tcg_gen_mov_i32(lc, c); + tcg_gen_sub_i32(temp_4, b, c); + getCFlag(temp_6); + tcg_gen_mov_i32(temp_5, temp_6); + tcg_gen_sub_i32(a, temp_4, temp_5); + if ((getFFlag () == true)) { + setZFlag(a); + setNFlag(a); + CarryADD(temp_8, a, lb, lc); + tcg_gen_mov_i32(temp_7, temp_8); + setCFlag(temp_7); + OverflowADD(temp_10, a, lb, lc); + tcg_gen_mov_i32(temp_9, temp_10); + setVFlag(temp_9); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(lb); + tcg_temp_free(lc); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_4); + tcg_temp_free(temp_6); + tcg_temp_free(temp_5); + tcg_temp_free(temp_8); + tcg_temp_free(temp_7); + tcg_temp_free(temp_10); + tcg_temp_free(temp_9); + + return ret; +} + + +/* + * NEG + * Variables: @b, @a + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarrySUB, + * setVFlag, OverflowSUB + * --- code --- + * { + * cc_flag = getCCFlag (); + * lb = @b; + * if((cc_flag == true)) + * { + * lb = @b; + * @a = (0 - @b); + * if((getFFlag () == true)) + * { + * setZFlag (@a); + * setNFlag (@a); + * setCFlag (CarrySUB (@a, 0, lb)); + * setVFlag (OverflowSUB (@a, 0, lb)); + * }; + * }; + * } + */ + +int +arc_gen_NEG(DisasCtxt *ctx, TCGv b, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv lb = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + tcg_gen_mov_i32(lb, b); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lb, b); + tcg_gen_subfi_i32(a, 0, b); + if ((getFFlag () == true)) { + setZFlag(a); + setNFlag(a); + tcg_gen_movi_i32(temp_6, 0); + CarrySUB(temp_5, a, temp_6, lb); + tcg_gen_mov_i32(temp_4, temp_5); + setCFlag(temp_4); + tcg_gen_movi_i32(temp_9, 0); + OverflowSUB(temp_8, a, temp_9, lb); + tcg_gen_mov_i32(temp_7, temp_8); + setVFlag(temp_7); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(lb); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_6); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + tcg_temp_free(temp_9); + tcg_temp_free(temp_8); + tcg_temp_free(temp_7); + + return ret; +} + + +/* + * SUB + * Variables: @b, @c, @a + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarrySUB, + * setVFlag, OverflowSUB + * --- code --- + * { + * cc_flag = getCCFlag (); + * lb = @b; + * if((cc_flag == true)) + * { + * lb = @b; + * lc = @c; + * @a = (@b - @c); + * if((getFFlag () == true)) + * { + * setZFlag (@a); + * setNFlag (@a); + * setCFlag (CarrySUB (@a, lb, lc)); + * setVFlag (OverflowSUB (@a, lb, lc)); + * }; + * }; + * } + */ + +int +arc_gen_SUB(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv lb = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv lc = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + tcg_gen_mov_i32(lb, b); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lb, b); + tcg_gen_mov_i32(lc, c); + tcg_gen_sub_i32(a, b, c); + if ((getFFlag () == true)) { + setZFlag(a); + setNFlag(a); + CarrySUB(temp_5, a, lb, lc); + tcg_gen_mov_i32(temp_4, temp_5); + setCFlag(temp_4); + OverflowSUB(temp_7, a, lb, lc); + tcg_gen_mov_i32(temp_6, temp_7); + setVFlag(temp_6); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(lb); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(lc); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + tcg_temp_free(temp_7); + tcg_temp_free(temp_6); + + return ret; +} + + +/* + * SUB1 + * Variables: @b, @c, @a + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarrySUB, + * setVFlag, OverflowSUB + * --- code --- + * { + * cc_flag = getCCFlag (); + * lb = @b; + * if((cc_flag == true)) + * { + * lb = @b; + * lc = (@c << 1); + * @a = (@b - lc); + * if((getFFlag () == true)) + * { + * setZFlag (@a); + * setNFlag (@a); + * setCFlag (CarrySUB (@a, lb, lc)); + * setVFlag (OverflowSUB (@a, lb, lc)); + * }; + * }; + * } + */ + +int +arc_gen_SUB1(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv lb = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv lc = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + tcg_gen_mov_i32(lb, b); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lb, b); + tcg_gen_shli_i32(lc, c, 1); + tcg_gen_sub_i32(a, b, lc); + if ((getFFlag () == true)) { + setZFlag(a); + setNFlag(a); + CarrySUB(temp_5, a, lb, lc); + tcg_gen_mov_i32(temp_4, temp_5); + setCFlag(temp_4); + OverflowSUB(temp_7, a, lb, lc); + tcg_gen_mov_i32(temp_6, temp_7); + setVFlag(temp_6); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(lb); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(lc); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + tcg_temp_free(temp_7); + tcg_temp_free(temp_6); + + return ret; +} + + +/* + * SUB2 + * Variables: @b, @c, @a + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarrySUB, + * setVFlag, OverflowSUB + * --- code --- + * { + * cc_flag = getCCFlag (); + * lb = @b; + * if((cc_flag == true)) + * { + * lb = @b; + * lc = (@c << 2); + * @a = (@b - lc); + * if((getFFlag () == true)) + * { + * setZFlag (@a); + * setNFlag (@a); + * setCFlag (CarrySUB (@a, lb, lc)); + * setVFlag (OverflowSUB (@a, lb, lc)); + * }; + * }; + * } + */ + +int +arc_gen_SUB2(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv lb = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv lc = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + tcg_gen_mov_i32(lb, b); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lb, b); + tcg_gen_shli_i32(lc, c, 2); + tcg_gen_sub_i32(a, b, lc); + if ((getFFlag () == true)) { + setZFlag(a); + setNFlag(a); + CarrySUB(temp_5, a, lb, lc); + tcg_gen_mov_i32(temp_4, temp_5); + setCFlag(temp_4); + OverflowSUB(temp_7, a, lb, lc); + tcg_gen_mov_i32(temp_6, temp_7); + setVFlag(temp_6); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(lb); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(lc); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + tcg_temp_free(temp_7); + tcg_temp_free(temp_6); + + return ret; +} + + +/* + * SUB3 + * Variables: @b, @c, @a + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarrySUB, + * setVFlag, OverflowSUB + * --- code --- + * { + * cc_flag = getCCFlag (); + * lb = @b; + * if((cc_flag == true)) + * { + * lb = @b; + * lc = (@c << 3); + * @a = (@b - lc); + * if((getFFlag () == true)) + * { + * setZFlag (@a); + * setNFlag (@a); + * setCFlag (CarrySUB (@a, lb, lc)); + * setVFlag (OverflowSUB (@a, lb, lc)); + * }; + * }; + * } + */ + +int +arc_gen_SUB3(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv lb = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv lc = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + tcg_gen_mov_i32(lb, b); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lb, b); + tcg_gen_shli_i32(lc, c, 3); + tcg_gen_sub_i32(a, b, lc); + if ((getFFlag () == true)) { + setZFlag(a); + setNFlag(a); + CarrySUB(temp_5, a, lb, lc); + tcg_gen_mov_i32(temp_4, temp_5); + setCFlag(temp_4); + OverflowSUB(temp_7, a, lb, lc); + tcg_gen_mov_i32(temp_6, temp_7); + setVFlag(temp_6); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(lb); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(lc); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + tcg_temp_free(temp_7); + tcg_temp_free(temp_6); + + return ret; +} + + +/* + * MAX + * Variables: @b, @c, @a + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarrySUB, + * setVFlag, OverflowSUB + * --- code --- + * { + * cc_flag = getCCFlag (); + * lb = @b; + * if((cc_flag == true)) + * { + * lb = @b; + * lc = @c; + * alu = (lb - lc); + * if((lc >= lb)) + * { + * @a = lc; + * } + * else + * { + * @a = lb; + * }; + * if((getFFlag () == true)) + * { + * setZFlag (alu); + * setNFlag (alu); + * setCFlag (CarrySUB (@a, lb, lc)); + * setVFlag (OverflowSUB (@a, lb, lc)); + * }; + * }; + * } + */ + +int +arc_gen_MAX(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv lb = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv lc = tcg_temp_local_new_i32(); + TCGv alu = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + getCCFlag(temp_5); + tcg_gen_mov_i32(cc_flag, temp_5); + tcg_gen_mov_i32(lb, b); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lb, b); + tcg_gen_mov_i32(lc, c); + tcg_gen_sub_i32(alu, lb, lc); + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_GE, temp_3, lc, lb); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, else_2); + tcg_gen_mov_i32(a, lc); + tcg_gen_br(done_2); + gen_set_label(else_2); + tcg_gen_mov_i32(a, lb); + gen_set_label(done_2); + if ((getFFlag () == true)) { + setZFlag(alu); + setNFlag(alu); + CarrySUB(temp_7, a, lb, lc); + tcg_gen_mov_i32(temp_6, temp_7); + setCFlag(temp_6); + OverflowSUB(temp_9, a, lb, lc); + tcg_gen_mov_i32(temp_8, temp_9); + setVFlag(temp_8); + } + gen_set_label(done_1); + tcg_temp_free(temp_5); + tcg_temp_free(cc_flag); + tcg_temp_free(lb); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(lc); + tcg_temp_free(alu); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_7); + tcg_temp_free(temp_6); + tcg_temp_free(temp_9); + tcg_temp_free(temp_8); + + return ret; +} + + +/* + * MIN + * Variables: @b, @c, @a + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarrySUB, + * setVFlag, OverflowSUB + * --- code --- + * { + * cc_flag = getCCFlag (); + * lb = @b; + * if((cc_flag == true)) + * { + * lb = @b; + * lc = @c; + * alu = (lb - lc); + * if((lc <= lb)) + * { + * @a = lc; + * } + * else + * { + * @a = lb; + * }; + * if((getFFlag () == true)) + * { + * setZFlag (alu); + * setNFlag (alu); + * setCFlag (CarrySUB (@a, lb, lc)); + * setVFlag (OverflowSUB (@a, lb, lc)); + * }; + * }; + * } + */ + +int +arc_gen_MIN(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv lb = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv lc = tcg_temp_local_new_i32(); + TCGv alu = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + getCCFlag(temp_5); + tcg_gen_mov_i32(cc_flag, temp_5); + tcg_gen_mov_i32(lb, b); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lb, b); + tcg_gen_mov_i32(lc, c); + tcg_gen_sub_i32(alu, lb, lc); + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_LE, temp_3, lc, lb); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, else_2); + tcg_gen_mov_i32(a, lc); + tcg_gen_br(done_2); + gen_set_label(else_2); + tcg_gen_mov_i32(a, lb); + gen_set_label(done_2); + if ((getFFlag () == true)) { + setZFlag(alu); + setNFlag(alu); + CarrySUB(temp_7, a, lb, lc); + tcg_gen_mov_i32(temp_6, temp_7); + setCFlag(temp_6); + OverflowSUB(temp_9, a, lb, lc); + tcg_gen_mov_i32(temp_8, temp_9); + setVFlag(temp_8); + } + gen_set_label(done_1); + tcg_temp_free(temp_5); + tcg_temp_free(cc_flag); + tcg_temp_free(lb); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(lc); + tcg_temp_free(alu); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_7); + tcg_temp_free(temp_6); + tcg_temp_free(temp_9); + tcg_temp_free(temp_8); + + return ret; +} + + +/* + * CMP + * Variables: @b, @c + * Functions: getCCFlag, setZFlag, setNFlag, setCFlag, CarrySUB, setVFlag, + * OverflowSUB + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * alu = (@b - @c); + * setZFlag (alu); + * setNFlag (alu); + * setCFlag (CarrySUB (alu, @b, @c)); + * setVFlag (OverflowSUB (alu, @b, @c)); + * }; + * } + */ + +int +arc_gen_CMP(DisasCtxt *ctx, TCGv b, TCGv c) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv alu = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_sub_i32(alu, b, c); + setZFlag(alu); + setNFlag(alu); + CarrySUB(temp_5, alu, b, c); + tcg_gen_mov_i32(temp_4, temp_5); + setCFlag(temp_4); + OverflowSUB(temp_7, alu, b, c); + tcg_gen_mov_i32(temp_6, temp_7); + setVFlag(temp_6); + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(alu); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + tcg_temp_free(temp_7); + tcg_temp_free(temp_6); + + return ret; +} + + +/* + * AND + * Variables: @b, @c, @a + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * la = (@b & @c); + * @a = la; + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (la); + * setNFlag (la); + * }; + * }; + * } + */ + +int +arc_gen_AND(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv la = tcg_temp_local_new_i32(); + int f_flag; + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_and_i32(la, b, c); + tcg_gen_mov_i32(a, la); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(la); + setNFlag(la); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(la); + + return ret; +} + + +/* + * OR + * Variables: @b, @c, @a + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * la = (@b | @c); + * @a = la; + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (la); + * setNFlag (la); + * }; + * }; + * } + */ + +int +arc_gen_OR(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv la = tcg_temp_local_new_i32(); + int f_flag; + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_or_i32(la, b, c); + tcg_gen_mov_i32(a, la); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(la); + setNFlag(la); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(la); + + return ret; +} + + +/* + * XOR + * Variables: @b, @c, @a + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * la = (@b ^ @c); + * @a = la; + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (la); + * setNFlag (la); + * }; + * }; + * } + */ + +int +arc_gen_XOR(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv la = tcg_temp_local_new_i32(); + int f_flag; + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_xor_i32(la, b, c); + tcg_gen_mov_i32(a, la); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(la); + setNFlag(la); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(la); + + return ret; +} + + +/* + * MOV + * Variables: @b, @a + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * la = @b; + * @a = la; + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (la); + * setNFlag (la); + * }; + * }; + * } + */ + +int +arc_gen_MOV(DisasCtxt *ctx, TCGv b, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv la = tcg_temp_local_new_i32(); + int f_flag; + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(la, b); + tcg_gen_mov_i32(a, la); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(la); + setNFlag(la); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(la); + + return ret; +} + + +/* + * ASL + * Variables: @b, @c, @a + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, getBit, + * setVFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * lb = @b; + * lc = (@c & 31); + * la = (lb << lc); + * @a = la; + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (la); + * setNFlag (la); + * if((lc == 0)) + * { + * setCFlag (0); + * } + * else + * { + * setCFlag (getBit (lb, (32 - lc))); + * }; + * if((@c == 268435457)) + * { + * t1 = getBit (la, 31); + * t2 = getBit (lb, 31); + * if((t1 == t2)) + * { + * setVFlag (0); + * } + * else + * { + * setVFlag (1); + * }; + * }; + * }; + * }; + * } + */ + +int +arc_gen_ASL(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv lb = tcg_temp_local_new_i32(); + TCGv lc = tcg_temp_local_new_i32(); + TCGv la = tcg_temp_local_new_i32(); + int f_flag; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_10 = tcg_temp_local_new_i32(); + TCGv temp_13 = tcg_temp_local_new_i32(); + TCGv temp_12 = tcg_temp_local_new_i32(); + TCGv temp_11 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_15 = tcg_temp_local_new_i32(); + TCGv temp_14 = tcg_temp_local_new_i32(); + TCGv t1 = tcg_temp_local_new_i32(); + TCGv temp_17 = tcg_temp_local_new_i32(); + TCGv temp_16 = tcg_temp_local_new_i32(); + TCGv t2 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_18 = tcg_temp_local_new_i32(); + TCGv temp_19 = tcg_temp_local_new_i32(); + getCCFlag(temp_9); + tcg_gen_mov_i32(cc_flag, temp_9); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lb, b); + tcg_gen_andi_i32(lc, c, 31); + tcg_gen_shl_i32(la, lb, lc); + tcg_gen_mov_i32(a, la); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(la); + setNFlag(la); + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcondi_i32(TCG_COND_EQ, temp_3, lc, 0); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, else_2); + tcg_gen_movi_i32(temp_10, 0); + setCFlag(temp_10); + tcg_gen_br(done_2); + gen_set_label(else_2); + tcg_gen_subfi_i32(temp_13, 32, lc); + getBit(temp_12, lb, temp_13); + tcg_gen_mov_i32(temp_11, temp_12); + setCFlag(temp_11); + gen_set_label(done_2); + TCGLabel *done_3 = gen_new_label(); + tcg_gen_setcondi_i32(TCG_COND_EQ, temp_5, c, 268435457); + tcg_gen_xori_i32(temp_6, temp_5, 1); + tcg_gen_andi_i32(temp_6, temp_6, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_6, arc_true, done_3); + tcg_gen_movi_i32(temp_15, 31); + getBit(temp_14, la, temp_15); + tcg_gen_mov_i32(t1, temp_14); + tcg_gen_movi_i32(temp_17, 31); + getBit(temp_16, lb, temp_17); + tcg_gen_mov_i32(t2, temp_16); + TCGLabel *else_4 = gen_new_label(); + TCGLabel *done_4 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_7, t1, t2); + tcg_gen_xori_i32(temp_8, temp_7, 1); + tcg_gen_andi_i32(temp_8, temp_8, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_8, arc_true, else_4); + tcg_gen_movi_i32(temp_18, 0); + setVFlag(temp_18); + tcg_gen_br(done_4); + gen_set_label(else_4); + tcg_gen_movi_i32(temp_19, 1); + setVFlag(temp_19); + gen_set_label(done_4); + gen_set_label(done_3); + } + gen_set_label(done_1); + tcg_temp_free(temp_9); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(lb); + tcg_temp_free(lc); + tcg_temp_free(la); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_10); + tcg_temp_free(temp_13); + tcg_temp_free(temp_12); + tcg_temp_free(temp_11); + tcg_temp_free(temp_5); + tcg_temp_free(temp_6); + tcg_temp_free(temp_15); + tcg_temp_free(temp_14); + tcg_temp_free(t1); + tcg_temp_free(temp_17); + tcg_temp_free(temp_16); + tcg_temp_free(t2); + tcg_temp_free(temp_7); + tcg_temp_free(temp_8); + tcg_temp_free(temp_18); + tcg_temp_free(temp_19); + + return ret; +} + + +/* + * ASR + * Variables: @b, @c, @a + * Functions: getCCFlag, arithmeticShiftRight, getFFlag, setZFlag, setNFlag, + * setCFlag, getBit + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * lb = @b; + * lc = (@c & 31); + * la = arithmeticShiftRight (lb, lc); + * @a = la; + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (la); + * setNFlag (la); + * if((lc == 0)) + * { + * setCFlag (0); + * } + * else + * { + * setCFlag (getBit (lb, (lc - 1))); + * }; + * }; + * }; + * } + */ + +int +arc_gen_ASR(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv lb = tcg_temp_local_new_i32(); + TCGv lc = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv la = tcg_temp_local_new_i32(); + int f_flag; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_10 = tcg_temp_local_new_i32(); + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + getCCFlag(temp_5); + tcg_gen_mov_i32(cc_flag, temp_5); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lb, b); + tcg_gen_andi_i32(lc, c, 31); + arithmeticShiftRight(temp_6, lb, lc); + tcg_gen_mov_i32(la, temp_6); + tcg_gen_mov_i32(a, la); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(la); + setNFlag(la); + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcondi_i32(TCG_COND_EQ, temp_3, lc, 0); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, else_2); + tcg_gen_movi_i32(temp_7, 0); + setCFlag(temp_7); + tcg_gen_br(done_2); + gen_set_label(else_2); + tcg_gen_subi_i32(temp_10, lc, 1); + getBit(temp_9, lb, temp_10); + tcg_gen_mov_i32(temp_8, temp_9); + setCFlag(temp_8); + gen_set_label(done_2); + } + gen_set_label(done_1); + tcg_temp_free(temp_5); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(lb); + tcg_temp_free(lc); + tcg_temp_free(temp_6); + tcg_temp_free(la); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_7); + tcg_temp_free(temp_10); + tcg_temp_free(temp_9); + tcg_temp_free(temp_8); + + return ret; +} + + +/* + * ASR8 + * Variables: @b, @a + * Functions: getCCFlag, arithmeticShiftRight, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * lb = @b; + * la = arithmeticShiftRight (lb, 8); + * @a = la; + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (la); + * setNFlag (la); + * }; + * }; + * } + */ + +int +arc_gen_ASR8(DisasCtxt *ctx, TCGv b, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv lb = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv la = tcg_temp_local_new_i32(); + int f_flag; + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lb, b); + tcg_gen_movi_i32(temp_5, 8); + arithmeticShiftRight(temp_4, lb, temp_5); + tcg_gen_mov_i32(la, temp_4); + tcg_gen_mov_i32(a, la); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(la); + setNFlag(la); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(lb); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + tcg_temp_free(la); + + return ret; +} + + +/* + * ASR16 + * Variables: @b, @a + * Functions: getCCFlag, arithmeticShiftRight, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * lb = @b; + * la = arithmeticShiftRight (lb, 16); + * @a = la; + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (la); + * setNFlag (la); + * }; + * }; + * } + */ + +int +arc_gen_ASR16(DisasCtxt *ctx, TCGv b, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv lb = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv la = tcg_temp_local_new_i32(); + int f_flag; + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lb, b); + tcg_gen_movi_i32(temp_5, 16); + arithmeticShiftRight(temp_4, lb, temp_5); + tcg_gen_mov_i32(la, temp_4); + tcg_gen_mov_i32(a, la); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(la); + setNFlag(la); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(lb); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + tcg_temp_free(la); + + return ret; +} + + +/* + * LSL16 + * Variables: @b, @a + * Functions: getCCFlag, logicalShiftLeft, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * la = logicalShiftLeft (@b, 16); + * @a = la; + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (la); + * setNFlag (la); + * }; + * }; + * } + */ + +int +arc_gen_LSL16(DisasCtxt *ctx, TCGv b, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv la = tcg_temp_local_new_i32(); + int f_flag; + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_movi_i32(temp_5, 16); + logicalShiftLeft(temp_4, b, temp_5); + tcg_gen_mov_i32(la, temp_4); + tcg_gen_mov_i32(a, la); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(la); + setNFlag(la); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + tcg_temp_free(la); + + return ret; +} + + +/* + * LSL8 + * Variables: @b, @a + * Functions: getCCFlag, logicalShiftLeft, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * la = logicalShiftLeft (@b, 8); + * @a = la; + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (la); + * setNFlag (la); + * }; + * }; + * } + */ + +int +arc_gen_LSL8(DisasCtxt *ctx, TCGv b, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv la = tcg_temp_local_new_i32(); + int f_flag; + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_movi_i32(temp_5, 8); + logicalShiftLeft(temp_4, b, temp_5); + tcg_gen_mov_i32(la, temp_4); + tcg_gen_mov_i32(a, la); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(la); + setNFlag(la); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + tcg_temp_free(la); + + return ret; +} + + +/* + * LSR + * Variables: @b, @c, @a + * Functions: getCCFlag, logicalShiftRight, getFFlag, setZFlag, setNFlag, + * setCFlag, getBit + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * lb = @b; + * lc = (@c & 31); + * la = logicalShiftRight (lb, lc); + * @a = la; + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (la); + * setNFlag (la); + * if((lc == 0)) + * { + * setCFlag (0); + * } + * else + * { + * setCFlag (getBit (lb, (lc - 1))); + * }; + * }; + * }; + * } + */ + +int +arc_gen_LSR(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv lb = tcg_temp_local_new_i32(); + TCGv lc = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv la = tcg_temp_local_new_i32(); + int f_flag; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_10 = tcg_temp_local_new_i32(); + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + getCCFlag(temp_5); + tcg_gen_mov_i32(cc_flag, temp_5); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lb, b); + tcg_gen_andi_i32(lc, c, 31); + logicalShiftRight(temp_6, lb, lc); + tcg_gen_mov_i32(la, temp_6); + tcg_gen_mov_i32(a, la); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(la); + setNFlag(la); + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcondi_i32(TCG_COND_EQ, temp_3, lc, 0); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, else_2); + tcg_gen_movi_i32(temp_7, 0); + setCFlag(temp_7); + tcg_gen_br(done_2); + gen_set_label(else_2); + tcg_gen_subi_i32(temp_10, lc, 1); + getBit(temp_9, lb, temp_10); + tcg_gen_mov_i32(temp_8, temp_9); + setCFlag(temp_8); + gen_set_label(done_2); + } + gen_set_label(done_1); + tcg_temp_free(temp_5); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(lb); + tcg_temp_free(lc); + tcg_temp_free(temp_6); + tcg_temp_free(la); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_7); + tcg_temp_free(temp_10); + tcg_temp_free(temp_9); + tcg_temp_free(temp_8); + + return ret; +} + + +/* + * LSR16 + * Variables: @b, @a + * Functions: getCCFlag, logicalShiftRight, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * la = logicalShiftRight (@b, 16); + * @a = la; + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (la); + * setNFlag (la); + * }; + * }; + * } + */ + +int +arc_gen_LSR16(DisasCtxt *ctx, TCGv b, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv la = tcg_temp_local_new_i32(); + int f_flag; + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_movi_i32(temp_5, 16); + logicalShiftRight(temp_4, b, temp_5); + tcg_gen_mov_i32(la, temp_4); + tcg_gen_mov_i32(a, la); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(la); + setNFlag(la); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + tcg_temp_free(la); + + return ret; +} + + +/* + * LSR8 + * Variables: @b, @a + * Functions: getCCFlag, logicalShiftRight, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * la = logicalShiftRight (@b, 8); + * @a = la; + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (la); + * setNFlag (la); + * }; + * }; + * } + */ + +int +arc_gen_LSR8(DisasCtxt *ctx, TCGv b, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv la = tcg_temp_local_new_i32(); + int f_flag; + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_movi_i32(temp_5, 8); + logicalShiftRight(temp_4, b, temp_5); + tcg_gen_mov_i32(la, temp_4); + tcg_gen_mov_i32(a, la); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(la); + setNFlag(la); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + tcg_temp_free(la); + + return ret; +} + + +/* + * BIC + * Variables: @b, @c, @a + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * la = (@b & ~@c); + * @a = la; + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (la); + * setNFlag (la); + * }; + * }; + * } + */ + +int +arc_gen_BIC(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv la = tcg_temp_local_new_i32(); + int f_flag; + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_not_i32(temp_4, c); + tcg_gen_and_i32(la, b, temp_4); + tcg_gen_mov_i32(a, la); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(la); + setNFlag(la); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_4); + tcg_temp_free(la); + + return ret; +} + + +/* + * BCLR + * Variables: @c, @b, @a + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * tmp = (1 << (@c & 31)); + * la = (@b & ~tmp); + * @a = la; + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (la); + * setNFlag (la); + * }; + * }; + * } + */ + +int +arc_gen_BCLR(DisasCtxt *ctx, TCGv c, TCGv b, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv tmp = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv la = tcg_temp_local_new_i32(); + int f_flag; + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_andi_i32(temp_4, c, 31); + tcg_gen_shlfi_i32(tmp, 1, temp_4); + tcg_gen_not_i32(temp_5, tmp); + tcg_gen_and_i32(la, b, temp_5); + tcg_gen_mov_i32(a, la); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(la); + setNFlag(la); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_4); + tcg_temp_free(tmp); + tcg_temp_free(temp_5); + tcg_temp_free(la); + + return ret; +} + + +/* + * BMSK + * Variables: @c, @b, @a + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * tmp1 = ((@c & 31) + 1); + * if((tmp1 == 32)) + * { + * tmp2 = 4294967295; + * } + * else + * { + * tmp2 = ((1 << tmp1) - 1); + * }; + * la = (@b & tmp2); + * @a = la; + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (la); + * setNFlag (la); + * }; + * }; + * } + */ + +int +arc_gen_BMSK(DisasCtxt *ctx, TCGv c, TCGv b, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv tmp1 = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv tmp2 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv la = tcg_temp_local_new_i32(); + int f_flag; + getCCFlag(temp_5); + tcg_gen_mov_i32(cc_flag, temp_5); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_andi_i32(temp_6, c, 31); + tcg_gen_addi_i32(tmp1, temp_6, 1); + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcondi_i32(TCG_COND_EQ, temp_3, tmp1, 32); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, else_2); + tcg_gen_movi_i32(tmp2, 4294967295); + tcg_gen_br(done_2); + gen_set_label(else_2); + tcg_gen_shlfi_i32(temp_7, 1, tmp1); + tcg_gen_subi_i32(tmp2, temp_7, 1); + gen_set_label(done_2); + tcg_gen_and_i32(la, b, tmp2); + tcg_gen_mov_i32(a, la); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(la); + setNFlag(la); + } + gen_set_label(done_1); + tcg_temp_free(temp_5); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_6); + tcg_temp_free(tmp1); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(tmp2); + tcg_temp_free(temp_7); + tcg_temp_free(la); + + return ret; +} + + +/* + * BMSKN + * Variables: @c, @b, @a + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * tmp1 = ((@c & 31) + 1); + * if((tmp1 == 32)) + * { + * tmp2 = 4294967295; + * } + * else + * { + * tmp2 = ((1 << tmp1) - 1); + * }; + * la = (@b & ~tmp2); + * @a = la; + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (la); + * setNFlag (la); + * }; + * }; + * } + */ + +int +arc_gen_BMSKN(DisasCtxt *ctx, TCGv c, TCGv b, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv tmp1 = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv tmp2 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv la = tcg_temp_local_new_i32(); + int f_flag; + getCCFlag(temp_5); + tcg_gen_mov_i32(cc_flag, temp_5); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_andi_i32(temp_6, c, 31); + tcg_gen_addi_i32(tmp1, temp_6, 1); + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcondi_i32(TCG_COND_EQ, temp_3, tmp1, 32); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, else_2); + tcg_gen_movi_i32(tmp2, 4294967295); + tcg_gen_br(done_2); + gen_set_label(else_2); + tcg_gen_shlfi_i32(temp_7, 1, tmp1); + tcg_gen_subi_i32(tmp2, temp_7, 1); + gen_set_label(done_2); + tcg_gen_not_i32(temp_8, tmp2); + tcg_gen_and_i32(la, b, temp_8); + tcg_gen_mov_i32(a, la); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(la); + setNFlag(la); + } + gen_set_label(done_1); + tcg_temp_free(temp_5); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_6); + tcg_temp_free(tmp1); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(tmp2); + tcg_temp_free(temp_7); + tcg_temp_free(temp_8); + tcg_temp_free(la); + + return ret; +} + + +/* + * BSET + * Variables: @c, @b, @a + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * tmp = (1 << (@c & 31)); + * la = (@b | tmp); + * @a = la; + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (la); + * setNFlag (la); + * }; + * }; + * } + */ + +int +arc_gen_BSET(DisasCtxt *ctx, TCGv c, TCGv b, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv tmp = tcg_temp_local_new_i32(); + TCGv la = tcg_temp_local_new_i32(); + int f_flag; + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_andi_i32(temp_4, c, 31); + tcg_gen_shlfi_i32(tmp, 1, temp_4); + tcg_gen_or_i32(la, b, tmp); + tcg_gen_mov_i32(a, la); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(la); + setNFlag(la); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_4); + tcg_temp_free(tmp); + tcg_temp_free(la); + + return ret; +} + + +/* + * BXOR + * Variables: @c, @b, @a + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * tmp = (1 << @c); + * la = (@b ^ tmp); + * @a = la; + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (la); + * setNFlag (la); + * }; + * }; + * } + */ + +int +arc_gen_BXOR(DisasCtxt *ctx, TCGv c, TCGv b, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv tmp = tcg_temp_local_new_i32(); + TCGv la = tcg_temp_local_new_i32(); + int f_flag; + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_shlfi_i32(tmp, 1, c); + tcg_gen_xor_i32(la, b, tmp); + tcg_gen_mov_i32(a, la); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(la); + setNFlag(la); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(tmp); + tcg_temp_free(la); + + return ret; +} + + +/* + * ROL + * Variables: @src, @dest + * Functions: getCCFlag, rotateLeft, getFFlag, setZFlag, setNFlag, setCFlag, + * extractBits + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * lsrc = @src; + * @dest = rotateLeft (lsrc, 1); + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (@dest); + * setNFlag (@dest); + * setCFlag (extractBits (lsrc, 31, 31)); + * }; + * }; + * } + */ + +int +arc_gen_ROL(DisasCtxt *ctx, TCGv src, TCGv dest) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv lsrc = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + int f_flag; + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lsrc, src); + tcg_gen_movi_i32(temp_5, 1); + rotateLeft(temp_4, lsrc, temp_5); + tcg_gen_mov_i32(dest, temp_4); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(dest); + setNFlag(dest); + tcg_gen_movi_i32(temp_9, 31); + tcg_gen_movi_i32(temp_8, 31); + extractBits(temp_7, lsrc, temp_8, temp_9); + tcg_gen_mov_i32(temp_6, temp_7); + setCFlag(temp_6); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(lsrc); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + tcg_temp_free(temp_9); + tcg_temp_free(temp_8); + tcg_temp_free(temp_7); + tcg_temp_free(temp_6); + + return ret; +} + + +/* + * ROL8 + * Variables: @src, @dest + * Functions: getCCFlag, rotateLeft, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * lsrc = @src; + * @dest = rotateLeft (lsrc, 8); + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (@dest); + * setNFlag (@dest); + * }; + * }; + * } + */ + +int +arc_gen_ROL8(DisasCtxt *ctx, TCGv src, TCGv dest) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv lsrc = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + int f_flag; + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lsrc, src); + tcg_gen_movi_i32(temp_5, 8); + rotateLeft(temp_4, lsrc, temp_5); + tcg_gen_mov_i32(dest, temp_4); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(dest); + setNFlag(dest); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(lsrc); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + + return ret; +} + + +/* + * ROR + * Variables: @src, @n, @dest + * Functions: getCCFlag, rotateRight, getFFlag, setZFlag, setNFlag, + * setCFlag, extractBits + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * lsrc = @src; + * ln = (@n & 31); + * @dest = rotateRight (lsrc, ln); + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (@dest); + * setNFlag (@dest); + * setCFlag (extractBits (lsrc, (ln - 1), (ln - 1))); + * }; + * }; + * } + */ + +int +arc_gen_ROR(DisasCtxt *ctx, TCGv src, TCGv n, TCGv dest) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv lsrc = tcg_temp_local_new_i32(); + TCGv ln = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + int f_flag; + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lsrc, src); + tcg_gen_andi_i32(ln, n, 31); + rotateRight(temp_4, lsrc, ln); + tcg_gen_mov_i32(dest, temp_4); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(dest); + setNFlag(dest); + tcg_gen_subi_i32(temp_8, ln, 1); + tcg_gen_subi_i32(temp_7, ln, 1); + extractBits(temp_6, lsrc, temp_7, temp_8); + tcg_gen_mov_i32(temp_5, temp_6); + setCFlag(temp_5); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(lsrc); + tcg_temp_free(ln); + tcg_temp_free(temp_4); + tcg_temp_free(temp_8); + tcg_temp_free(temp_7); + tcg_temp_free(temp_6); + tcg_temp_free(temp_5); + + return ret; +} + + +/* + * ROR8 + * Variables: @src, @dest + * Functions: getCCFlag, rotateRight, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * lsrc = @src; + * @dest = rotateRight (lsrc, 8); + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (@dest); + * setNFlag (@dest); + * }; + * }; + * } + */ + +int +arc_gen_ROR8(DisasCtxt *ctx, TCGv src, TCGv dest) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv lsrc = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + int f_flag; + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lsrc, src); + tcg_gen_movi_i32(temp_5, 8); + rotateRight(temp_4, lsrc, temp_5); + tcg_gen_mov_i32(dest, temp_4); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(dest); + setNFlag(dest); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(lsrc); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + + return ret; +} + + +/* + * RLC + * Variables: @src, @dest + * Functions: getCCFlag, getCFlag, getFFlag, setZFlag, setNFlag, setCFlag, + * extractBits + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * lsrc = @src; + * @dest = (lsrc << 1); + * @dest = (@dest | getCFlag ()); + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (@dest); + * setNFlag (@dest); + * setCFlag (extractBits (lsrc, 31, 31)); + * }; + * }; + * } + */ + +int +arc_gen_RLC(DisasCtxt *ctx, TCGv src, TCGv dest) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv lsrc = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + int f_flag; + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lsrc, src); + tcg_gen_shli_i32(dest, lsrc, 1); + getCFlag(temp_5); + tcg_gen_mov_i32(temp_4, temp_5); + tcg_gen_or_i32(dest, dest, temp_4); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(dest); + setNFlag(dest); + tcg_gen_movi_i32(temp_9, 31); + tcg_gen_movi_i32(temp_8, 31); + extractBits(temp_7, lsrc, temp_8, temp_9); + tcg_gen_mov_i32(temp_6, temp_7); + setCFlag(temp_6); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(lsrc); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + tcg_temp_free(temp_9); + tcg_temp_free(temp_8); + tcg_temp_free(temp_7); + tcg_temp_free(temp_6); + + return ret; +} + + +/* + * RRC + * Variables: @src, @dest + * Functions: getCCFlag, getCFlag, getFFlag, setZFlag, setNFlag, setCFlag, + * extractBits + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * lsrc = @src; + * @dest = (lsrc >> 1); + * @dest = (@dest | (getCFlag () << 31)); + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (@dest); + * setNFlag (@dest); + * setCFlag (extractBits (lsrc, 0, 0)); + * }; + * }; + * } + */ + +int +arc_gen_RRC(DisasCtxt *ctx, TCGv src, TCGv dest) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv lsrc = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + int f_flag; + TCGv temp_10 = tcg_temp_local_new_i32(); + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(lsrc, src); + tcg_gen_shri_i32(dest, lsrc, 1); + getCFlag(temp_6); + tcg_gen_mov_i32(temp_5, temp_6); + tcg_gen_shli_i32(temp_4, temp_5, 31); + tcg_gen_or_i32(dest, dest, temp_4); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(dest); + setNFlag(dest); + tcg_gen_movi_i32(temp_10, 0); + tcg_gen_movi_i32(temp_9, 0); + extractBits(temp_8, lsrc, temp_9, temp_10); + tcg_gen_mov_i32(temp_7, temp_8); + setCFlag(temp_7); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(lsrc); + tcg_temp_free(temp_6); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + tcg_temp_free(temp_10); + tcg_temp_free(temp_9); + tcg_temp_free(temp_8); + tcg_temp_free(temp_7); + + return ret; +} + + +/* + * SEXB + * Variables: @dest, @src + * Functions: getCCFlag, arithmeticShiftRight, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * @dest = arithmeticShiftRight ((@src << 24), 24); + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (@dest); + * setNFlag (@dest); + * }; + * }; + * } + */ + +int +arc_gen_SEXB(DisasCtxt *ctx, TCGv dest, TCGv src) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + int f_flag; + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_movi_i32(temp_6, 24); + tcg_gen_shli_i32(temp_5, src, 24); + arithmeticShiftRight(temp_4, temp_5, temp_6); + tcg_gen_mov_i32(dest, temp_4); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(dest); + setNFlag(dest); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_6); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + + return ret; +} + + +/* + * SEXH + * Variables: @dest, @src + * Functions: getCCFlag, arithmeticShiftRight, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * @dest = arithmeticShiftRight ((@src << 16), 16); + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (@dest); + * setNFlag (@dest); + * }; + * }; + * } + */ + +int +arc_gen_SEXH(DisasCtxt *ctx, TCGv dest, TCGv src) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + int f_flag; + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_movi_i32(temp_6, 16); + tcg_gen_shli_i32(temp_5, src, 16); + arithmeticShiftRight(temp_4, temp_5, temp_6); + tcg_gen_mov_i32(dest, temp_4); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(dest); + setNFlag(dest); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_6); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + + return ret; +} + + +/* + * EXTB + * Variables: @dest, @src + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * @dest = (@src & 255); + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (@dest); + * setNFlag (@dest); + * }; + * }; + * } + */ + +int +arc_gen_EXTB(DisasCtxt *ctx, TCGv dest, TCGv src) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + int f_flag; + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_andi_i32(dest, src, 255); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(dest); + setNFlag(dest); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + + return ret; +} + + +/* + * EXTH + * Variables: @dest, @src + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * @dest = (@src & 65535); + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (@dest); + * setNFlag (@dest); + * }; + * }; + * } + */ + +int +arc_gen_EXTH(DisasCtxt *ctx, TCGv dest, TCGv src) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + int f_flag; + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_andi_i32(dest, src, 65535); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(dest); + setNFlag(dest); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + + return ret; +} + + +/* + * BTST + * Variables: @c, @b + * Functions: getCCFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * tmp = (1 << (@c & 31)); + * alu = (@b & tmp); + * setZFlag (alu); + * setNFlag (alu); + * }; + * } + */ + +int +arc_gen_BTST(DisasCtxt *ctx, TCGv c, TCGv b) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv tmp = tcg_temp_local_new_i32(); + TCGv alu = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_andi_i32(temp_4, c, 31); + tcg_gen_shlfi_i32(tmp, 1, temp_4); + tcg_gen_and_i32(alu, b, tmp); + setZFlag(alu); + setNFlag(alu); + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_4); + tcg_temp_free(tmp); + tcg_temp_free(alu); + + return ret; +} + + +/* + * TST + * Variables: @b, @c + * Functions: getCCFlag, setZFlag, setNFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * alu = (@b & @c); + * setZFlag (alu); + * setNFlag (alu); + * }; + * } + */ + +int +arc_gen_TST(DisasCtxt *ctx, TCGv b, TCGv c) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv alu = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_and_i32(alu, b, c); + setZFlag(alu); + setNFlag(alu); + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(alu); + + return ret; +} + + +/* + * XBFU + * Variables: @src2, @src1, @dest + * Functions: getCCFlag, extractBits, getFFlag, setZFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * N = extractBits (@src2, 4, 0); + * M = (extractBits (@src2, 9, 5) + 1); + * tmp1 = (@src1 >> N); + * tmp2 = ((1 << M) - 1); + * @dest = (tmp1 & tmp2); + * if((getFFlag () == true)) + * { + * setZFlag (@dest); + * }; + * }; + * } + */ + +int +arc_gen_XBFU(DisasCtxt *ctx, TCGv src2, TCGv src1, TCGv dest) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv N = tcg_temp_local_new_i32(); + TCGv temp_10 = tcg_temp_local_new_i32(); + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv M = tcg_temp_local_new_i32(); + TCGv tmp1 = tcg_temp_local_new_i32(); + TCGv temp_11 = tcg_temp_local_new_i32(); + TCGv tmp2 = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_movi_i32(temp_6, 0); + tcg_gen_movi_i32(temp_5, 4); + extractBits(temp_4, src2, temp_5, temp_6); + tcg_gen_mov_i32(N, temp_4); + tcg_gen_movi_i32(temp_10, 5); + tcg_gen_movi_i32(temp_9, 9); + extractBits(temp_8, src2, temp_9, temp_10); + tcg_gen_mov_i32(temp_7, temp_8); + tcg_gen_addi_i32(M, temp_7, 1); + tcg_gen_shr_i32(tmp1, src1, N); + tcg_gen_shlfi_i32(temp_11, 1, M); + tcg_gen_subi_i32(tmp2, temp_11, 1); + tcg_gen_and_i32(dest, tmp1, tmp2); + if ((getFFlag () == true)) { + setZFlag(dest); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_6); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + tcg_temp_free(N); + tcg_temp_free(temp_10); + tcg_temp_free(temp_9); + tcg_temp_free(temp_8); + tcg_temp_free(temp_7); + tcg_temp_free(M); + tcg_temp_free(tmp1); + tcg_temp_free(temp_11); + tcg_temp_free(tmp2); + + return ret; +} + + +/* + * AEX + * Variables: @src2, @b + * Functions: getCCFlag, readAuxReg, writeAuxReg + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * tmp = readAuxReg (@src2); + * writeAuxReg (@src2, @b); + * @b = tmp; + * }; + * } + */ + +int +arc_gen_AEX(DisasCtxt *ctx, TCGv src2, TCGv b) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv tmp = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + readAuxReg(temp_4, src2); + tcg_gen_mov_i32(tmp, temp_4); + writeAuxReg(src2, b); + tcg_gen_mov_i32(b, tmp); + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_4); + tcg_temp_free(tmp); + + return ret; +} + + +/* + * LR + * Variables: @dest, @src + * Functions: readAuxReg + * --- code --- + * { + * @dest = readAuxReg (@src); + * } + */ + +int +arc_gen_LR(DisasCtxt *ctx, TCGv dest, TCGv src) +{ + int ret = DISAS_NEXT; + TCGv temp_1 = tcg_temp_local_new_i32(); + readAuxReg(temp_1, src); + tcg_gen_mov_i32(dest, temp_1); + tcg_temp_free(temp_1); + + return ret; +} + + +/* + * SR + * Variables: @src2, @src1 + * Functions: writeAuxReg + * --- code --- + * { + * writeAuxReg (@src2, @src1); + * } + */ + +int +arc_gen_SR(DisasCtxt *ctx, TCGv src2, TCGv src1) +{ + int ret = DISAS_NEXT; + + writeAuxReg(src2, src1); + return ret; +} + + +/* + * SYNC + * Variables: + * Functions: syncReturnDisasUpdate + * --- code --- + * { + * syncReturnDisasUpdate (); + * } + */ + +int +arc_gen_SYNC(DisasCtxt *ctx) +{ + int ret = DISAS_NEXT; + + syncReturnDisasUpdate(); + return ret; +} + + +/* + * CLRI + * Variables: @c + * Functions: getRegister, setRegister + * --- code --- + * { + * status32 = getRegister (R_STATUS32); + * ie = (status32 & 2147483648); + * ie = (ie >> 27); + * e = ((status32 & 30) >> 1); + * a = 32; + * @c = ((ie | e) | a); + * mask = 2147483648; + * mask = ~mask; + * status32 = (status32 & mask); + * setRegister (R_STATUS32, status32); + * } + */ + +int +arc_gen_CLRI(DisasCtxt *ctx, TCGv c) +{ + int ret = DISAS_NEXT; + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv status32 = tcg_temp_local_new_i32(); + TCGv ie = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv e = tcg_temp_local_new_i32(); + TCGv a = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv mask = tcg_temp_local_new_i32(); + getRegister(temp_1, R_STATUS32); + tcg_gen_mov_i32(status32, temp_1); + tcg_gen_andi_i32(ie, status32, 2147483648); + tcg_gen_shri_i32(ie, ie, 27); + tcg_gen_andi_i32(temp_2, status32, 30); + tcg_gen_shri_i32(e, temp_2, 1); + tcg_gen_movi_i32(a, 32); + tcg_gen_or_i32(temp_3, ie, e); + tcg_gen_or_i32(c, temp_3, a); + tcg_gen_movi_i32(mask, 2147483648); + tcg_gen_not_i32(mask, mask); + tcg_gen_and_i32(status32, status32, mask); + setRegister(R_STATUS32, status32); + tcg_temp_free(temp_1); + tcg_temp_free(status32); + tcg_temp_free(ie); + tcg_temp_free(temp_2); + tcg_temp_free(e); + tcg_temp_free(a); + tcg_temp_free(temp_3); + tcg_temp_free(mask); + + return ret; +} + + +/* + * SETI + * Variables: @c + * Functions: getRegister, setRegister + * --- code --- + * { + * status32 = getRegister (R_STATUS32); + * e_mask = 30; + * e_mask = ~e_mask; + * e_value = ((@c & 15) << 1); + * temp1 = (@c & 32); + * if((temp1 != 0)) + * { + * status32 = ((status32 & e_mask) | e_value); + * ie_mask = 2147483648; + * ie_mask = ~ie_mask; + * ie_value = ((@c & 16) << 27); + * status32 = ((status32 & ie_mask) | ie_value); + * } + * else + * { + * status32 = (status32 | 2147483648); + * temp2 = (@c & 16); + * if((temp2 != 0)) + * { + * status32 = ((status32 & e_mask) | e_value); + * }; + * }; + * setRegister (R_STATUS32, status32); + * } + */ + +int +arc_gen_SETI(DisasCtxt *ctx, TCGv c) +{ + int ret = DISAS_NEXT; + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv status32 = tcg_temp_local_new_i32(); + TCGv e_mask = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv e_value = tcg_temp_local_new_i32(); + TCGv temp1 = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv ie_mask = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv ie_value = tcg_temp_local_new_i32(); + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv temp2 = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_10 = tcg_temp_local_new_i32(); + getRegister(temp_5, R_STATUS32); + tcg_gen_mov_i32(status32, temp_5); + tcg_gen_movi_i32(e_mask, 30); + tcg_gen_not_i32(e_mask, e_mask); + tcg_gen_andi_i32(temp_6, c, 15); + tcg_gen_shli_i32(e_value, temp_6, 1); + tcg_gen_andi_i32(temp1, c, 32); + TCGLabel *else_1 = gen_new_label(); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcondi_i32(TCG_COND_NE, temp_1, temp1, 0); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, else_1); + tcg_gen_and_i32(temp_7, status32, e_mask); + tcg_gen_or_i32(status32, temp_7, e_value); + tcg_gen_movi_i32(ie_mask, 2147483648); + tcg_gen_not_i32(ie_mask, ie_mask); + tcg_gen_andi_i32(temp_8, c, 16); + tcg_gen_shli_i32(ie_value, temp_8, 27); + tcg_gen_and_i32(temp_9, status32, ie_mask); + tcg_gen_or_i32(status32, temp_9, ie_value); + tcg_gen_br(done_1); + gen_set_label(else_1); + tcg_gen_ori_i32(status32, status32, 2147483648); + tcg_gen_andi_i32(temp2, c, 16); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcondi_i32(TCG_COND_NE, temp_3, temp2, 0); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, done_2); + tcg_gen_and_i32(temp_10, status32, e_mask); + tcg_gen_or_i32(status32, temp_10, e_value); + gen_set_label(done_2); + gen_set_label(done_1); + setRegister(R_STATUS32, status32); + tcg_temp_free(temp_5); + tcg_temp_free(status32); + tcg_temp_free(e_mask); + tcg_temp_free(temp_6); + tcg_temp_free(e_value); + tcg_temp_free(temp1); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_7); + tcg_temp_free(ie_mask); + tcg_temp_free(temp_8); + tcg_temp_free(ie_value); + tcg_temp_free(temp_9); + tcg_temp_free(temp2); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_10); + + return ret; +} + + +/* + * NOP + * Variables: + * Functions: doNothing + * --- code --- + * { + * doNothing (); + * } + */ + +int +arc_gen_NOP(DisasCtxt *ctx) +{ + int ret = DISAS_NEXT; + + return ret; +} + + +/* + * PREALLOC + * Variables: + * Functions: doNothing + * --- code --- + * { + * doNothing (); + * } + */ + +int +arc_gen_PREALLOC(DisasCtxt *ctx) +{ + int ret = DISAS_NEXT; + + return ret; +} + + +/* + * PREFETCH + * Variables: @src1, @src2 + * Functions: getAAFlag, doNothing + * --- code --- + * { + * AA = getAAFlag (); + * if(((AA == 1) || (AA == 2))) + * { + * @src1 = (@src1 + @src2); + * } + * else + * { + * doNothing (); + * }; + * } + */ + +int +arc_gen_PREFETCH(DisasCtxt *ctx, TCGv src1, TCGv src2) +{ + int ret = DISAS_NEXT; + int AA; + AA = getAAFlag (); + if (((AA == 1) || (AA == 2))) { + tcg_gen_add_i32(src1, src1, src2); + } else { + doNothing(); + } + + + return ret; +} + + +/* + * MPY + * Variables: @b, @c, @a + * Functions: getCCFlag, getFFlag, HELPER, setZFlag, setNFlag, setVFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * _b = @b; + * _c = @c; + * @a = ((_b * _c) & 4294967295); + * if((getFFlag () == true)) + * { + * high_part = HELPER (mpym, _b, _c); + * tmp1 = (high_part & 2147483648); + * tmp2 = (@a & 2147483648); + * setZFlag (@a); + * setNFlag (high_part); + * setVFlag ((tmp1 != tmp2)); + * }; + * }; + * } + */ + +int +arc_gen_MPY(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv _b = tcg_temp_local_new_i32(); + TCGv _c = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv high_part = tcg_temp_local_new_i32(); + TCGv tmp1 = tcg_temp_local_new_i32(); + TCGv tmp2 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(_b, b); + tcg_gen_mov_i32(_c, c); + tcg_gen_mul_i32(temp_4, _b, _c); + tcg_gen_andi_i32(a, temp_4, 4294967295); + if ((getFFlag () == true)) { + ARC_HELPER(mpym, high_part, _b, _c); + tcg_gen_andi_i32(tmp1, high_part, 2147483648); + tcg_gen_andi_i32(tmp2, a, 2147483648); + setZFlag(a); + setNFlag(high_part); + tcg_gen_setcond_i32(TCG_COND_NE, temp_5, tmp1, tmp2); + setVFlag(temp_5); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(_b); + tcg_temp_free(_c); + tcg_temp_free(temp_4); + tcg_temp_free(high_part); + tcg_temp_free(tmp1); + tcg_temp_free(tmp2); + tcg_temp_free(temp_5); + + return ret; +} + + +/* + * MPYMU + * Variables: @a, @b, @c + * Functions: getCCFlag, HELPER, getFFlag, setZFlag, setNFlag, setVFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * @a = HELPER (mpymu, @b, @c); + * if((getFFlag () == true)) + * { + * setZFlag (@a); + * setNFlag (0); + * setVFlag (0); + * }; + * }; + * } + */ + +int +arc_gen_MPYMU(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + ARC_HELPER(mpymu, a, b, c); + if ((getFFlag () == true)) { + setZFlag(a); + tcg_gen_movi_i32(temp_4, 0); + setNFlag(temp_4); + tcg_gen_movi_i32(temp_5, 0); + setVFlag(temp_5); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_4); + tcg_temp_free(temp_5); + + return ret; +} + + +/* + * MPYM + * Variables: @a, @b, @c + * Functions: getCCFlag, HELPER, getFFlag, setZFlag, setNFlag, setVFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * @a = HELPER (mpym, @b, @c); + * if((getFFlag () == true)) + * { + * setZFlag (@a); + * setNFlag (@a); + * setVFlag (0); + * }; + * }; + * } + */ + +int +arc_gen_MPYM(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + ARC_HELPER(mpym, a, b, c); + if ((getFFlag () == true)) { + setZFlag(a); + setNFlag(a); + tcg_gen_movi_i32(temp_4, 0); + setVFlag(temp_4); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_4); + + return ret; +} + + +/* + * MPYU + * Variables: @b, @c, @a + * Functions: getCCFlag, getFFlag, HELPER, setZFlag, setNFlag, setVFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * _b = @b; + * _c = @c; + * @a = ((_b * _c) & 4294967295); + * if((getFFlag () == true)) + * { + * high_part = HELPER (mpym, _b, _c); + * setZFlag (@a); + * setNFlag (0); + * setVFlag ((high_part > 0)); + * }; + * }; + * } + */ + +int +arc_gen_MPYU(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv _b = tcg_temp_local_new_i32(); + TCGv _c = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv high_part = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(_b, b); + tcg_gen_mov_i32(_c, c); + tcg_gen_mul_i32(temp_4, _b, _c); + tcg_gen_andi_i32(a, temp_4, 4294967295); + if ((getFFlag () == true)) { + ARC_HELPER(mpym, high_part, _b, _c); + setZFlag(a); + tcg_gen_movi_i32(temp_5, 0); + setNFlag(temp_5); + tcg_gen_setcondi_i32(TCG_COND_GT, temp_6, high_part, 0); + setVFlag(temp_6); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(_b); + tcg_temp_free(_c); + tcg_temp_free(temp_4); + tcg_temp_free(high_part); + tcg_temp_free(temp_5); + tcg_temp_free(temp_6); + + return ret; +} + + +/* + * MPYUW + * Variables: @a, @b, @c + * Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setVFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * @a = ((@b & 65535) * (@c & 65535)); + * if((getFFlag () == true)) + * { + * setZFlag (@a); + * setNFlag (0); + * setVFlag (0); + * }; + * }; + * } + */ + +int +arc_gen_MPYUW(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_andi_i32(temp_5, c, 65535); + tcg_gen_andi_i32(temp_4, b, 65535); + tcg_gen_mul_i32(a, temp_4, temp_5); + if ((getFFlag () == true)) { + setZFlag(a); + tcg_gen_movi_i32(temp_6, 0); + setNFlag(temp_6); + tcg_gen_movi_i32(temp_7, 0); + setVFlag(temp_7); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + tcg_temp_free(temp_6); + tcg_temp_free(temp_7); + + return ret; +} + + +/* + * MPYW + * Variables: @a, @b, @c + * Functions: getCCFlag, arithmeticShiftRight, getFFlag, setZFlag, setNFlag, + * setVFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * @a = (arithmeticShiftRight ((@b << 16), 16) + * * arithmeticShiftRight ((@c << 16), 16)); + * if((getFFlag () == true)) + * { + * setZFlag (@a); + * setNFlag (@a); + * setVFlag (0); + * }; + * }; + * } + */ + +int +arc_gen_MPYW(DisasCtxt *ctx, TCGv a, TCGv b, TCGv c) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_11 = tcg_temp_local_new_i32(); + TCGv temp_10 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_12 = tcg_temp_local_new_i32(); + getCCFlag(temp_3); + tcg_gen_mov_i32(cc_flag, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_movi_i32(temp_11, 16); + tcg_gen_shli_i32(temp_10, c, 16); + tcg_gen_movi_i32(temp_7, 16); + tcg_gen_shli_i32(temp_6, b, 16); + arithmeticShiftRight(temp_5, temp_6, temp_7); + tcg_gen_mov_i32(temp_4, temp_5); + arithmeticShiftRight(temp_9, temp_10, temp_11); + tcg_gen_mov_i32(temp_8, temp_9); + tcg_gen_mul_i32(a, temp_4, temp_8); + if ((getFFlag () == true)) { + setZFlag(a); + setNFlag(a); + tcg_gen_movi_i32(temp_12, 0); + setVFlag(temp_12); + } + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_11); + tcg_temp_free(temp_10); + tcg_temp_free(temp_7); + tcg_temp_free(temp_6); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + tcg_temp_free(temp_9); + tcg_temp_free(temp_8); + tcg_temp_free(temp_12); + + return ret; +} + + +/* + * DIV + * Variables: @src2, @src1, @dest + * Functions: getCCFlag, divSigned, getFFlag, setZFlag, setNFlag, setVFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * if(((@src2 != 0) && ((@src1 != 2147483648) || (@src2 != 4294967295)))) + * { + * @dest = divSigned (@src1, @src2); + * if((getFFlag () == true)) + * { + * setZFlag (@dest); + * setNFlag (@dest); + * setVFlag (0); + * }; + * } + * else + * { + * }; + * }; + * } + */ + +int +arc_gen_DIV(DisasCtxt *ctx, TCGv src2, TCGv src1, TCGv dest) +{ + int ret = DISAS_NEXT; + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_10 = tcg_temp_local_new_i32(); + TCGv temp_11 = tcg_temp_local_new_i32(); + getCCFlag(temp_9); + tcg_gen_mov_i32(cc_flag, temp_9); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcondi_i32(TCG_COND_NE, temp_3, src2, 0); + tcg_gen_setcondi_i32(TCG_COND_NE, temp_4, src1, 2147483648); + tcg_gen_setcondi_i32(TCG_COND_NE, temp_5, src2, 4294967295); + tcg_gen_or_i32(temp_6, temp_4, temp_5); + tcg_gen_and_i32(temp_7, temp_3, temp_6); + tcg_gen_xori_i32(temp_8, temp_7, 1); + tcg_gen_andi_i32(temp_8, temp_8, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_8, arc_true, else_2); + divSigned(temp_10, src1, src2); + tcg_gen_mov_i32(dest, temp_10); + if ((getFFlag () == true)) { + setZFlag(dest); + setNFlag(dest); + tcg_gen_movi_i32(temp_11, 0); + setVFlag(temp_11); + } + tcg_gen_br(done_2); + gen_set_label(else_2); + gen_set_label(done_2); + gen_set_label(done_1); + tcg_temp_free(temp_9); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_5); + tcg_temp_free(temp_6); + tcg_temp_free(temp_7); + tcg_temp_free(temp_8); + tcg_temp_free(temp_10); + tcg_temp_free(temp_11); + + return ret; +} + + +/* + * DIVU + * Variables: @src2, @dest, @src1 + * Functions: getCCFlag, divUnsigned, getFFlag, setZFlag, setNFlag, + * setVFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * if((@src2 != 0)) + * { + * @dest = divUnsigned (@src1, @src2); + * if((getFFlag () == true)) + * { + * setZFlag (@dest); + * setNFlag (0); + * setVFlag (0); + * }; + * } + * else + * { + * }; + * }; + * } + */ + +int +arc_gen_DIVU(DisasCtxt *ctx, TCGv src2, TCGv dest, TCGv src1) +{ + int ret = DISAS_NEXT; + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + getCCFlag(temp_5); + tcg_gen_mov_i32(cc_flag, temp_5); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcondi_i32(TCG_COND_NE, temp_3, src2, 0); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, else_2); + divUnsigned(temp_6, src1, src2); + tcg_gen_mov_i32(dest, temp_6); + if ((getFFlag () == true)) { + setZFlag(dest); + tcg_gen_movi_i32(temp_7, 0); + setNFlag(temp_7); + tcg_gen_movi_i32(temp_8, 0); + setVFlag(temp_8); + } + tcg_gen_br(done_2); + gen_set_label(else_2); + gen_set_label(done_2); + gen_set_label(done_1); + tcg_temp_free(temp_5); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_6); + tcg_temp_free(temp_7); + tcg_temp_free(temp_8); + + return ret; +} + + +/* + * REM + * Variables: @src2, @src1, @dest + * Functions: getCCFlag, divRemainingSigned, getFFlag, setZFlag, setNFlag, + * setVFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * if(((@src2 != 0) && ((@src1 != 2147483648) || (@src2 != 4294967295)))) + * { + * @dest = divRemainingSigned (@src1, @src2); + * if((getFFlag () == true)) + * { + * setZFlag (@dest); + * setNFlag (@dest); + * setVFlag (0); + * }; + * } + * else + * { + * }; + * }; + * } + */ + +int +arc_gen_REM(DisasCtxt *ctx, TCGv src2, TCGv src1, TCGv dest) +{ + int ret = DISAS_NEXT; + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_10 = tcg_temp_local_new_i32(); + TCGv temp_11 = tcg_temp_local_new_i32(); + getCCFlag(temp_9); + tcg_gen_mov_i32(cc_flag, temp_9); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcondi_i32(TCG_COND_NE, temp_3, src2, 0); + tcg_gen_setcondi_i32(TCG_COND_NE, temp_4, src1, 2147483648); + tcg_gen_setcondi_i32(TCG_COND_NE, temp_5, src2, 4294967295); + tcg_gen_or_i32(temp_6, temp_4, temp_5); + tcg_gen_and_i32(temp_7, temp_3, temp_6); + tcg_gen_xori_i32(temp_8, temp_7, 1); + tcg_gen_andi_i32(temp_8, temp_8, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_8, arc_true, else_2); + divRemainingSigned(temp_10, src1, src2); + tcg_gen_mov_i32(dest, temp_10); + if ((getFFlag () == true)) { + setZFlag(dest); + setNFlag(dest); + tcg_gen_movi_i32(temp_11, 0); + setVFlag(temp_11); + } + tcg_gen_br(done_2); + gen_set_label(else_2); + gen_set_label(done_2); + gen_set_label(done_1); + tcg_temp_free(temp_9); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_5); + tcg_temp_free(temp_6); + tcg_temp_free(temp_7); + tcg_temp_free(temp_8); + tcg_temp_free(temp_10); + tcg_temp_free(temp_11); + + return ret; +} + + +/* + * REMU + * Variables: @src2, @dest, @src1 + * Functions: getCCFlag, divRemainingUnsigned, getFFlag, setZFlag, setNFlag, + * setVFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * if((@src2 != 0)) + * { + * @dest = divRemainingUnsigned (@src1, @src2); + * if((getFFlag () == true)) + * { + * setZFlag (@dest); + * setNFlag (0); + * setVFlag (0); + * }; + * } + * else + * { + * }; + * }; + * } + */ + +int +arc_gen_REMU(DisasCtxt *ctx, TCGv src2, TCGv dest, TCGv src1) +{ + int ret = DISAS_NEXT; + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + getCCFlag(temp_5); + tcg_gen_mov_i32(cc_flag, temp_5); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcondi_i32(TCG_COND_NE, temp_3, src2, 0); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, else_2); + divRemainingUnsigned(temp_6, src1, src2); + tcg_gen_mov_i32(dest, temp_6); + if ((getFFlag () == true)) { + setZFlag(dest); + tcg_gen_movi_i32(temp_7, 0); + setNFlag(temp_7); + tcg_gen_movi_i32(temp_8, 0); + setVFlag(temp_8); + } + tcg_gen_br(done_2); + gen_set_label(else_2); + gen_set_label(done_2); + gen_set_label(done_1); + tcg_temp_free(temp_5); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_6); + tcg_temp_free(temp_7); + tcg_temp_free(temp_8); + + return ret; +} + + +/* + * MAC + * Variables: @b, @c, @a + * Functions: getCCFlag, getRegister, MAC, getFFlag, setNFlag, OverflowADD, + * setVFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * old_acchi = getRegister (R_ACCHI); + * high_mul = MAC (@b, @c); + * @a = getRegister (R_ACCLO); + * if((getFFlag () == true)) + * { + * new_acchi = getRegister (R_ACCHI); + * setNFlag (new_acchi); + * if((OverflowADD (new_acchi, old_acchi, high_mul) == true)) + * { + * setVFlag (1); + * }; + * }; + * }; + * } + */ + +int +arc_gen_MAC(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv old_acchi = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv high_mul = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv new_acchi = tcg_temp_local_new_i32(); + TCGv temp_10 = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_11 = tcg_temp_local_new_i32(); + getCCFlag(temp_5); + tcg_gen_mov_i32(cc_flag, temp_5); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + getRegister(temp_6, R_ACCHI); + tcg_gen_mov_i32(old_acchi, temp_6); + MAC(temp_7, b, c); + tcg_gen_mov_i32(high_mul, temp_7); + getRegister(temp_8, R_ACCLO); + tcg_gen_mov_i32(a, temp_8); + if ((getFFlag () == true)) { + getRegister(temp_9, R_ACCHI); + tcg_gen_mov_i32(new_acchi, temp_9); + setNFlag(new_acchi); + TCGLabel *done_2 = gen_new_label(); + OverflowADD(temp_10, new_acchi, old_acchi, high_mul); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_3, temp_10, arc_true); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, done_2); + tcg_gen_movi_i32(temp_11, 1); + setVFlag(temp_11); + gen_set_label(done_2); + } + gen_set_label(done_1); + tcg_temp_free(temp_5); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_6); + tcg_temp_free(old_acchi); + tcg_temp_free(temp_7); + tcg_temp_free(high_mul); + tcg_temp_free(temp_8); + tcg_temp_free(temp_9); + tcg_temp_free(new_acchi); + tcg_temp_free(temp_10); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_11); + + return ret; +} + + +/* + * MACU + * Variables: @b, @c, @a + * Functions: getCCFlag, getRegister, MACU, getFFlag, CarryADD, setVFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * old_acchi = getRegister (R_ACCHI); + * high_mul = MACU (@b, @c); + * @a = getRegister (R_ACCLO); + * if((getFFlag () == true)) + * { + * new_acchi = getRegister (R_ACCHI); + * if((CarryADD (new_acchi, old_acchi, high_mul) == true)) + * { + * setVFlag (1); + * }; + * }; + * }; + * } + */ + +int +arc_gen_MACU(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv old_acchi = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv high_mul = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv new_acchi = tcg_temp_local_new_i32(); + TCGv temp_10 = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_11 = tcg_temp_local_new_i32(); + getCCFlag(temp_5); + tcg_gen_mov_i32(cc_flag, temp_5); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + getRegister(temp_6, R_ACCHI); + tcg_gen_mov_i32(old_acchi, temp_6); + MACU(temp_7, b, c); + tcg_gen_mov_i32(high_mul, temp_7); + getRegister(temp_8, R_ACCLO); + tcg_gen_mov_i32(a, temp_8); + if ((getFFlag () == true)) { + getRegister(temp_9, R_ACCHI); + tcg_gen_mov_i32(new_acchi, temp_9); + TCGLabel *done_2 = gen_new_label(); + CarryADD(temp_10, new_acchi, old_acchi, high_mul); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_3, temp_10, arc_true); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, done_2); + tcg_gen_movi_i32(temp_11, 1); + setVFlag(temp_11); + gen_set_label(done_2); + } + gen_set_label(done_1); + tcg_temp_free(temp_5); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_6); + tcg_temp_free(old_acchi); + tcg_temp_free(temp_7); + tcg_temp_free(high_mul); + tcg_temp_free(temp_8); + tcg_temp_free(temp_9); + tcg_temp_free(new_acchi); + tcg_temp_free(temp_10); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_11); + + return ret; +} + + +/* + * MACD + * Variables: @b, @c, @a + * Functions: getCCFlag, getRegister, MAC, nextReg, getFFlag, setNFlag, + * OverflowADD, setVFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * old_acchi = getRegister (R_ACCHI); + * high_mul = MAC (@b, @c); + * @a = getRegister (R_ACCLO); + * pair = nextReg (a); + * pair = getRegister (R_ACCHI); + * if((getFFlag () == true)) + * { + * new_acchi = getRegister (R_ACCHI); + * setNFlag (new_acchi); + * if((OverflowADD (new_acchi, old_acchi, high_mul) == true)) + * { + * setVFlag (1); + * }; + * }; + * }; + * } + */ + +int +arc_gen_MACD(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv old_acchi = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv high_mul = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv pair = NULL; + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv temp_10 = tcg_temp_local_new_i32(); + TCGv new_acchi = tcg_temp_local_new_i32(); + TCGv temp_11 = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_12 = tcg_temp_local_new_i32(); + getCCFlag(temp_5); + tcg_gen_mov_i32(cc_flag, temp_5); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + getRegister(temp_6, R_ACCHI); + tcg_gen_mov_i32(old_acchi, temp_6); + MAC(temp_7, b, c); + tcg_gen_mov_i32(high_mul, temp_7); + getRegister(temp_8, R_ACCLO); + tcg_gen_mov_i32(a, temp_8); + pair = nextReg (a); + getRegister(temp_9, R_ACCHI); + tcg_gen_mov_i32(pair, temp_9); + if ((getFFlag () == true)) { + getRegister(temp_10, R_ACCHI); + tcg_gen_mov_i32(new_acchi, temp_10); + setNFlag(new_acchi); + TCGLabel *done_2 = gen_new_label(); + OverflowADD(temp_11, new_acchi, old_acchi, high_mul); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_3, temp_11, arc_true); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, done_2); + tcg_gen_movi_i32(temp_12, 1); + setVFlag(temp_12); + gen_set_label(done_2); + } + gen_set_label(done_1); + tcg_temp_free(temp_5); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_6); + tcg_temp_free(old_acchi); + tcg_temp_free(temp_7); + tcg_temp_free(high_mul); + tcg_temp_free(temp_8); + tcg_temp_free(temp_9); + tcg_temp_free(temp_10); + tcg_temp_free(new_acchi); + tcg_temp_free(temp_11); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_12); + + return ret; +} + + +/* + * MACDU + * Variables: @b, @c, @a + * Functions: getCCFlag, getRegister, MACU, nextReg, getFFlag, CarryADD, + * setVFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * old_acchi = getRegister (R_ACCHI); + * high_mul = MACU (@b, @c); + * @a = getRegister (R_ACCLO); + * pair = nextReg (a); + * pair = getRegister (R_ACCHI); + * if((getFFlag () == true)) + * { + * new_acchi = getRegister (R_ACCHI); + * if((CarryADD (new_acchi, old_acchi, high_mul) == true)) + * { + * setVFlag (1); + * }; + * }; + * }; + * } + */ + +int +arc_gen_MACDU(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv old_acchi = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv high_mul = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv pair = NULL; + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv temp_10 = tcg_temp_local_new_i32(); + TCGv new_acchi = tcg_temp_local_new_i32(); + TCGv temp_11 = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_12 = tcg_temp_local_new_i32(); + getCCFlag(temp_5); + tcg_gen_mov_i32(cc_flag, temp_5); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + getRegister(temp_6, R_ACCHI); + tcg_gen_mov_i32(old_acchi, temp_6); + MACU(temp_7, b, c); + tcg_gen_mov_i32(high_mul, temp_7); + getRegister(temp_8, R_ACCLO); + tcg_gen_mov_i32(a, temp_8); + pair = nextReg (a); + getRegister(temp_9, R_ACCHI); + tcg_gen_mov_i32(pair, temp_9); + if ((getFFlag () == true)) { + getRegister(temp_10, R_ACCHI); + tcg_gen_mov_i32(new_acchi, temp_10); + TCGLabel *done_2 = gen_new_label(); + CarryADD(temp_11, new_acchi, old_acchi, high_mul); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_3, temp_11, arc_true); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, done_2); + tcg_gen_movi_i32(temp_12, 1); + setVFlag(temp_12); + gen_set_label(done_2); + } + gen_set_label(done_1); + tcg_temp_free(temp_5); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_6); + tcg_temp_free(old_acchi); + tcg_temp_free(temp_7); + tcg_temp_free(high_mul); + tcg_temp_free(temp_8); + tcg_temp_free(temp_9); + tcg_temp_free(temp_10); + tcg_temp_free(new_acchi); + tcg_temp_free(temp_11); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_12); + + return ret; +} + + +/* + * ABS + * Variables: @src, @dest + * Functions: Carry, getFFlag, setZFlag, setNFlag, setCFlag, Zero, setVFlag, + * getNFlag + * --- code --- + * { + * lsrc = @src; + * alu = (0 - lsrc); + * if((Carry (lsrc) == 1)) + * { + * @dest = alu; + * } + * else + * { + * @dest = lsrc; + * }; + * if((getFFlag () == true)) + * { + * setZFlag (@dest); + * setNFlag (@dest); + * setCFlag (Zero ()); + * setVFlag (getNFlag ()); + * }; + * } + */ + +int +arc_gen_ABS(DisasCtxt *ctx, TCGv src, TCGv dest) +{ + int ret = DISAS_NEXT; + TCGv lsrc = tcg_temp_local_new_i32(); + TCGv alu = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + tcg_gen_mov_i32(lsrc, src); + tcg_gen_subfi_i32(alu, 0, lsrc); + TCGLabel *else_1 = gen_new_label(); + TCGLabel *done_1 = gen_new_label(); + Carry(temp_3, lsrc); + tcg_gen_setcondi_i32(TCG_COND_EQ, temp_1, temp_3, 1); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, else_1); + tcg_gen_mov_i32(dest, alu); + tcg_gen_br(done_1); + gen_set_label(else_1); + tcg_gen_mov_i32(dest, lsrc); + gen_set_label(done_1); + if ((getFFlag () == true)) { + setZFlag(dest); + setNFlag(dest); + tcg_gen_mov_i32(temp_4, Zero()); + setCFlag(temp_4); + tcg_gen_mov_i32(temp_5, getNFlag()); + setVFlag(temp_5); + } + tcg_temp_free(lsrc); + tcg_temp_free(alu); + tcg_temp_free(temp_3); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_4); + tcg_temp_free(temp_5); + + return ret; +} + + +/* + * SWAP + * Variables: @src, @dest + * Functions: getFFlag, setZFlag, setNFlag + * --- code --- + * { + * tmp1 = (@src << 16); + * tmp2 = ((@src >> 16) & 65535); + * @dest = (tmp1 | tmp2); + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (@dest); + * setNFlag (@dest); + * }; + * } + */ + +int +arc_gen_SWAP(DisasCtxt *ctx, TCGv src, TCGv dest) +{ + int ret = DISAS_NEXT; + TCGv tmp1 = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv tmp2 = tcg_temp_local_new_i32(); + int f_flag; + tcg_gen_shli_i32(tmp1, src, 16); + tcg_gen_shri_i32(temp_1, src, 16); + tcg_gen_andi_i32(tmp2, temp_1, 65535); + tcg_gen_or_i32(dest, tmp1, tmp2); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(dest); + setNFlag(dest); + } + tcg_temp_free(tmp1); + tcg_temp_free(temp_1); + tcg_temp_free(tmp2); + + return ret; +} + + +/* + * SWAPE + * Variables: @src, @dest + * Functions: getFFlag, setZFlag, setNFlag + * --- code --- + * { + * tmp1 = ((@src << 24) & 4278190080); + * tmp2 = ((@src << 8) & 16711680); + * tmp3 = ((@src >> 8) & 65280); + * tmp4 = ((@src >> 24) & 255); + * @dest = (((tmp1 | tmp2) | tmp3) | tmp4); + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (@dest); + * setNFlag (@dest); + * }; + * } + */ + +int +arc_gen_SWAPE(DisasCtxt *ctx, TCGv src, TCGv dest) +{ + int ret = DISAS_NEXT; + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv tmp1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv tmp2 = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv tmp3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv tmp4 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + int f_flag; + tcg_gen_shli_i32(temp_1, src, 24); + tcg_gen_andi_i32(tmp1, temp_1, 4278190080); + tcg_gen_shli_i32(temp_2, src, 8); + tcg_gen_andi_i32(tmp2, temp_2, 16711680); + tcg_gen_shri_i32(temp_3, src, 8); + tcg_gen_andi_i32(tmp3, temp_3, 65280); + tcg_gen_shri_i32(temp_4, src, 24); + tcg_gen_andi_i32(tmp4, temp_4, 255); + tcg_gen_or_i32(temp_6, tmp1, tmp2); + tcg_gen_or_i32(temp_5, temp_6, tmp3); + tcg_gen_or_i32(dest, temp_5, tmp4); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(dest); + setNFlag(dest); + } + tcg_temp_free(temp_1); + tcg_temp_free(tmp1); + tcg_temp_free(temp_2); + tcg_temp_free(tmp2); + tcg_temp_free(temp_3); + tcg_temp_free(tmp3); + tcg_temp_free(temp_4); + tcg_temp_free(tmp4); + tcg_temp_free(temp_6); + tcg_temp_free(temp_5); + + return ret; +} + + +/* + * NOT + * Variables: @dest, @src + * Functions: getFFlag, setZFlag, setNFlag + * --- code --- + * { + * @dest = ~@src; + * f_flag = getFFlag (); + * if((f_flag == true)) + * { + * setZFlag (@dest); + * setNFlag (@dest); + * }; + * } + */ + +int +arc_gen_NOT(DisasCtxt *ctx, TCGv dest, TCGv src) +{ + int ret = DISAS_NEXT; + int f_flag; + tcg_gen_not_i32(dest, src); + f_flag = getFFlag (); + if ((f_flag == true)) { + setZFlag(dest); + setNFlag(dest); + } + + return ret; +} + + +/* + * BI + * Variables: @c + * Functions: setPC, getPCL + * --- code --- + * { + * setPC ((nextInsnAddress () + (@c << 2))); + * } + */ + +int +arc_gen_BI(DisasCtxt *ctx, TCGv c) +{ + int ret = DISAS_NEXT; + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + tcg_gen_shli_i32(temp_4, c, 2); + nextInsnAddress(temp_3); + tcg_gen_mov_i32(temp_2, temp_3); + tcg_gen_add_i32(temp_1, temp_2, temp_4); + setPC(temp_1); + tcg_temp_free(temp_4); + tcg_temp_free(temp_3); + tcg_temp_free(temp_2); + tcg_temp_free(temp_1); + + return ret; +} + + +/* + * BIH + * Variables: @c + * Functions: setPC, getPCL + * --- code --- + * { + * setPC ((nextInsnAddress () + (@c << 1))); + * } + */ + +int +arc_gen_BIH(DisasCtxt *ctx, TCGv c) +{ + int ret = DISAS_NEXT; + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + tcg_gen_shli_i32(temp_4, c, 1); + nextInsnAddress(temp_3); + tcg_gen_mov_i32(temp_2, temp_3); + tcg_gen_add_i32(temp_1, temp_2, temp_4); + setPC(temp_1); + tcg_temp_free(temp_4); + tcg_temp_free(temp_3); + tcg_temp_free(temp_2); + tcg_temp_free(temp_1); + + return ret; +} + + +/* + * B + * Variables: @rd + * Functions: getCCFlag, getPCL, shouldExecuteDelaySlot, executeDelaySlot, + * setPC + * --- code --- + * { + * take_branch = false; + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * take_branch = true; + * }; + * bta = (getPCL () + @rd); + * if((shouldExecuteDelaySlot () == true)) + * { + * executeDelaySlot (bta, take_branch); + * }; + * if((cc_flag == true)) + * { + * setPC (bta); + * }; + * } + */ + +int +arc_gen_B(DisasCtxt *ctx, TCGv rd) +{ + int ret = DISAS_NEXT; + TCGv take_branch = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv bta = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + tcg_gen_mov_i32(take_branch, arc_false); + getCCFlag(temp_5); + tcg_gen_mov_i32(cc_flag, temp_5); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(take_branch, arc_true); + gen_set_label(done_1); + getPCL(temp_7); + tcg_gen_mov_i32(temp_6, temp_7); + tcg_gen_add_i32(bta, temp_6, rd); + if ((shouldExecuteDelaySlot () == true)) { + executeDelaySlot(bta, take_branch); + } + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_3, cc_flag, arc_true); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, done_2); + setPC(bta); + gen_set_label(done_2); + tcg_temp_free(take_branch); + tcg_temp_free(temp_5); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_7); + tcg_temp_free(temp_6); + tcg_temp_free(bta); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + + return ret; +} + + +/* + * B_S + * Variables: @rd + * Functions: getCCFlag, killDelaySlot, setPC, getPCL + * --- code --- + * { + * take_branch = false; + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * }; + * if((cc_flag == true)) + * { + * killDelaySlot (); + * setPC ((getPCL () + @rd)); + * }; + * } + */ + +int +arc_gen_B_S(DisasCtxt *ctx, TCGv rd) +{ + int ret = DISAS_NEXT; + TCGv take_branch = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + tcg_gen_mov_i32(take_branch, arc_false); + getCCFlag(temp_5); + tcg_gen_mov_i32(cc_flag, temp_5); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + gen_set_label(done_1); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_3, cc_flag, arc_true); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, done_2); + killDelaySlot(); + getPCL(temp_8); + tcg_gen_mov_i32(temp_7, temp_8); + tcg_gen_add_i32(temp_6, temp_7, rd); + setPC(temp_6); + gen_set_label(done_2); + tcg_temp_free(take_branch); + tcg_temp_free(temp_5); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_8); + tcg_temp_free(temp_7); + tcg_temp_free(temp_6); + + return ret; +} + + +/* + * BBIT0 + * Variables: @b, @c, @rd + * Functions: getCCFlag, getPCL, shouldExecuteDelaySlot, executeDelaySlot, + * setPC + * --- code --- + * { + * take_branch = false; + * cc_flag = getCCFlag (); + * p_b = @b; + * p_c = (@c & 31); + * tmp = (1 << p_c); + * if((cc_flag == true)) + * { + * if(((p_b && tmp) == 0)) + * { + * take_branch = true; + * }; + * }; + * bta = (getPCL () + @rd); + * if((shouldExecuteDelaySlot () == true)) + * { + * executeDelaySlot (bta, take_branch); + * }; + * if((cc_flag == true)) + * { + * if(((p_b && tmp) == 0)) + * { + * setPC (bta); + * }; + * }; + * } + */ + +int +arc_gen_BBIT0(DisasCtxt *ctx, TCGv b, TCGv c, TCGv rd) +{ + int ret = DISAS_NEXT; + TCGv take_branch = tcg_temp_local_new_i32(); + TCGv temp_11 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv p_b = tcg_temp_local_new_i32(); + TCGv p_c = tcg_temp_local_new_i32(); + TCGv tmp = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_13 = tcg_temp_local_new_i32(); + TCGv temp_12 = tcg_temp_local_new_i32(); + TCGv bta = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv temp_10 = tcg_temp_local_new_i32(); + tcg_gen_mov_i32(take_branch, arc_false); + getCCFlag(temp_11); + tcg_gen_mov_i32(cc_flag, temp_11); + tcg_gen_mov_i32(p_b, b); + tcg_gen_andi_i32(p_c, c, 31); + tcg_gen_shlfi_i32(tmp, 1, p_c); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_and_i32(temp_3, p_b, tmp); + tcg_gen_setcondi_i32(TCG_COND_EQ, temp_4, temp_3, 0); + tcg_gen_xori_i32(temp_5, temp_4, 1); + tcg_gen_andi_i32(temp_5, temp_5, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_5, arc_true, done_2); + tcg_gen_mov_i32(take_branch, arc_true); + gen_set_label(done_2); + gen_set_label(done_1); + getPCL(temp_13); + tcg_gen_mov_i32(temp_12, temp_13); + tcg_gen_add_i32(bta, temp_12, rd); + if ((shouldExecuteDelaySlot () == true)) { + executeDelaySlot(bta, take_branch); + } + TCGLabel *done_3 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_6, cc_flag, arc_true); + tcg_gen_xori_i32(temp_7, temp_6, 1); + tcg_gen_andi_i32(temp_7, temp_7, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_7, arc_true, done_3); + TCGLabel *done_4 = gen_new_label(); + tcg_gen_and_i32(temp_8, p_b, tmp); + tcg_gen_setcondi_i32(TCG_COND_EQ, temp_9, temp_8, 0); + tcg_gen_xori_i32(temp_10, temp_9, 1); + tcg_gen_andi_i32(temp_10, temp_10, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_10, arc_true, done_4); + setPC(bta); + gen_set_label(done_4); + gen_set_label(done_3); + tcg_temp_free(take_branch); + tcg_temp_free(temp_11); + tcg_temp_free(cc_flag); + tcg_temp_free(p_b); + tcg_temp_free(p_c); + tcg_temp_free(tmp); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_5); + tcg_temp_free(temp_13); + tcg_temp_free(temp_12); + tcg_temp_free(bta); + tcg_temp_free(temp_6); + tcg_temp_free(temp_7); + tcg_temp_free(temp_8); + tcg_temp_free(temp_9); + tcg_temp_free(temp_10); + + return ret; +} + + +/* + * BBIT1 + * Variables: @b, @c, @rd + * Functions: getCCFlag, getPCL, shouldExecuteDelaySlot, executeDelaySlot, + * setPC + * --- code --- + * { + * take_branch = false; + * cc_flag = getCCFlag (); + * p_b = @b; + * p_c = (@c & 31); + * tmp = (1 << p_c); + * if((cc_flag == true)) + * { + * if(((p_b && tmp) != 0)) + * { + * take_branch = true; + * }; + * }; + * bta = (getPCL () + @rd); + * if((shouldExecuteDelaySlot () == true)) + * { + * executeDelaySlot (bta, take_branch); + * }; + * if((cc_flag == true)) + * { + * if(((p_b && tmp) != 0)) + * { + * setPC (bta); + * }; + * }; + * } + */ + +int +arc_gen_BBIT1(DisasCtxt *ctx, TCGv b, TCGv c, TCGv rd) +{ + int ret = DISAS_NEXT; + TCGv take_branch = tcg_temp_local_new_i32(); + TCGv temp_11 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv p_b = tcg_temp_local_new_i32(); + TCGv p_c = tcg_temp_local_new_i32(); + TCGv tmp = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_13 = tcg_temp_local_new_i32(); + TCGv temp_12 = tcg_temp_local_new_i32(); + TCGv bta = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv temp_10 = tcg_temp_local_new_i32(); + tcg_gen_mov_i32(take_branch, arc_false); + getCCFlag(temp_11); + tcg_gen_mov_i32(cc_flag, temp_11); + tcg_gen_mov_i32(p_b, b); + tcg_gen_andi_i32(p_c, c, 31); + tcg_gen_shlfi_i32(tmp, 1, p_c); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_and_i32(temp_3, p_b, tmp); + tcg_gen_setcondi_i32(TCG_COND_NE, temp_4, temp_3, 0); + tcg_gen_xori_i32(temp_5, temp_4, 1); + tcg_gen_andi_i32(temp_5, temp_5, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_5, arc_true, done_2); + tcg_gen_mov_i32(take_branch, arc_true); + gen_set_label(done_2); + gen_set_label(done_1); + getPCL(temp_13); + tcg_gen_mov_i32(temp_12, temp_13); + tcg_gen_add_i32(bta, temp_12, rd); + if ((shouldExecuteDelaySlot () == true)) { + executeDelaySlot(bta, take_branch); + } + TCGLabel *done_3 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_6, cc_flag, arc_true); + tcg_gen_xori_i32(temp_7, temp_6, 1); + tcg_gen_andi_i32(temp_7, temp_7, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_7, arc_true, done_3); + TCGLabel *done_4 = gen_new_label(); + tcg_gen_and_i32(temp_8, p_b, tmp); + tcg_gen_setcondi_i32(TCG_COND_NE, temp_9, temp_8, 0); + tcg_gen_xori_i32(temp_10, temp_9, 1); + tcg_gen_andi_i32(temp_10, temp_10, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_10, arc_true, done_4); + setPC(bta); + gen_set_label(done_4); + gen_set_label(done_3); + tcg_temp_free(take_branch); + tcg_temp_free(temp_11); + tcg_temp_free(cc_flag); + tcg_temp_free(p_b); + tcg_temp_free(p_c); + tcg_temp_free(tmp); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_5); + tcg_temp_free(temp_13); + tcg_temp_free(temp_12); + tcg_temp_free(bta); + tcg_temp_free(temp_6); + tcg_temp_free(temp_7); + tcg_temp_free(temp_8); + tcg_temp_free(temp_9); + tcg_temp_free(temp_10); + + return ret; +} + + +/* + * BL + * Variables: @rd + * Functions: getCCFlag, getPCL, shouldExecuteDelaySlot, setBLINK, + * nextInsnAddressAfterDelaySlot, executeDelaySlot, + * nextInsnAddress, setPC + * --- code --- + * { + * take_branch = false; + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * take_branch = true; + * }; + * bta = (getPCL () + @rd); + * if((shouldExecuteDelaySlot () == 1)) + * { + * if(take_branch) + * { + * setBLINK (nextInsnAddressAfterDelaySlot ()); + * }; + * executeDelaySlot (bta, take_branch); + * } + * else + * { + * if(take_branch) + * { + * setBLINK (nextInsnAddress ()); + * }; + * }; + * if((cc_flag == true)) + * { + * setPC (bta); + * }; + * } + */ + +int +arc_gen_BL(DisasCtxt *ctx, TCGv rd) +{ + int ret = DISAS_NEXT; + TCGv take_branch = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv bta = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_11 = tcg_temp_local_new_i32(); + TCGv temp_10 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_13 = tcg_temp_local_new_i32(); + TCGv temp_12 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + tcg_gen_mov_i32(take_branch, arc_false); + getCCFlag(temp_7); + tcg_gen_mov_i32(cc_flag, temp_7); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(take_branch, arc_true); + gen_set_label(done_1); + getPCL(temp_9); + tcg_gen_mov_i32(temp_8, temp_9); + tcg_gen_add_i32(bta, temp_8, rd); + if ((shouldExecuteDelaySlot () == 1)) { + TCGLabel *done_2 = gen_new_label(); + tcg_gen_xori_i32(temp_3, take_branch, 1); + tcg_gen_andi_i32(temp_3, temp_3, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_3, arc_true, done_2); + nextInsnAddressAfterDelaySlot(temp_11); + tcg_gen_mov_i32(temp_10, temp_11); + setBLINK(temp_10); + gen_set_label(done_2); + executeDelaySlot(bta, take_branch); + } else { + TCGLabel *done_3 = gen_new_label(); + tcg_gen_xori_i32(temp_4, take_branch, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, done_3); + nextInsnAddress(temp_13); + tcg_gen_mov_i32(temp_12, temp_13); + setBLINK(temp_12); + gen_set_label(done_3); + } + + TCGLabel *done_4 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_5, cc_flag, arc_true); + tcg_gen_xori_i32(temp_6, temp_5, 1); + tcg_gen_andi_i32(temp_6, temp_6, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_6, arc_true, done_4); + setPC(bta); + gen_set_label(done_4); + tcg_temp_free(take_branch); + tcg_temp_free(temp_7); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_9); + tcg_temp_free(temp_8); + tcg_temp_free(bta); + tcg_temp_free(temp_3); + tcg_temp_free(temp_11); + tcg_temp_free(temp_10); + tcg_temp_free(temp_4); + tcg_temp_free(temp_13); + tcg_temp_free(temp_12); + tcg_temp_free(temp_5); + tcg_temp_free(temp_6); + + return ret; +} + + +/* + * J + * Variables: @src + * Functions: getCCFlag, shouldExecuteDelaySlot, executeDelaySlot, setPC + * --- code --- + * { + * take_branch = false; + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * take_branch = true; + * }; + * bta = @src; + * if((shouldExecuteDelaySlot () == 1)) + * { + * executeDelaySlot (bta, take_branch); + * }; + * if((cc_flag == true)) + * { + * setPC (bta); + * }; + * } + */ + +int +arc_gen_J(DisasCtxt *ctx, TCGv src) +{ + int ret = DISAS_NEXT; + TCGv take_branch = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv bta = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + tcg_gen_mov_i32(take_branch, arc_false); + getCCFlag(temp_5); + tcg_gen_mov_i32(cc_flag, temp_5); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(take_branch, arc_true); + gen_set_label(done_1); + tcg_gen_mov_i32(bta, src); + if ((shouldExecuteDelaySlot () == 1)) { + executeDelaySlot(bta, take_branch); + } + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_3, cc_flag, arc_true); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, done_2); + setPC(bta); + gen_set_label(done_2); + tcg_temp_free(take_branch); + tcg_temp_free(temp_5); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(bta); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + + return ret; +} + + +/* + * JL + * Variables: @src + * Functions: getCCFlag, shouldExecuteDelaySlot, setBLINK, + * nextInsnAddressAfterDelaySlot, executeDelaySlot, + * nextInsnAddress, setPC + * --- code --- + * { + * take_branch = false; + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * take_branch = true; + * }; + * bta = @src; + * if((shouldExecuteDelaySlot () == 1)) + * { + * if(take_branch) + * { + * setBLINK (nextInsnAddressAfterDelaySlot ()); + * }; + * executeDelaySlot (bta, take_branch); + * } + * else + * { + * if(take_branch) + * { + * setBLINK (nextInsnAddress ()); + * }; + * }; + * if((cc_flag == true)) + * { + * setPC (bta); + * }; + * } + */ + +int +arc_gen_JL(DisasCtxt *ctx, TCGv src) +{ + int ret = DISAS_NEXT; + TCGv take_branch = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv bta = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_11 = tcg_temp_local_new_i32(); + TCGv temp_10 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + tcg_gen_mov_i32(take_branch, arc_false); + getCCFlag(temp_7); + tcg_gen_mov_i32(cc_flag, temp_7); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(take_branch, arc_true); + gen_set_label(done_1); + tcg_gen_mov_i32(bta, src); + if ((shouldExecuteDelaySlot () == 1)) { + TCGLabel *done_2 = gen_new_label(); + tcg_gen_xori_i32(temp_3, take_branch, 1); + tcg_gen_andi_i32(temp_3, temp_3, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_3, arc_true, done_2); + nextInsnAddressAfterDelaySlot(temp_9); + tcg_gen_mov_i32(temp_8, temp_9); + setBLINK(temp_8); + gen_set_label(done_2); + executeDelaySlot(bta, take_branch); + } else { + TCGLabel *done_3 = gen_new_label(); + tcg_gen_xori_i32(temp_4, take_branch, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, done_3); + nextInsnAddress(temp_11); + tcg_gen_mov_i32(temp_10, temp_11); + setBLINK(temp_10); + gen_set_label(done_3); + } + + TCGLabel *done_4 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_5, cc_flag, arc_true); + tcg_gen_xori_i32(temp_6, temp_5, 1); + tcg_gen_andi_i32(temp_6, temp_6, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_6, arc_true, done_4); + setPC(bta); + gen_set_label(done_4); + tcg_temp_free(take_branch); + tcg_temp_free(temp_7); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(bta); + tcg_temp_free(temp_3); + tcg_temp_free(temp_9); + tcg_temp_free(temp_8); + tcg_temp_free(temp_4); + tcg_temp_free(temp_11); + tcg_temp_free(temp_10); + tcg_temp_free(temp_5); + tcg_temp_free(temp_6); + + return ret; +} + + +/* + * SETEQ + * Variables: @b, @c, @a + * Functions: getCCFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * p_b = @b; + * p_c = @c; + * take_branch = false; + * if((p_b == p_c)) + * { + * } + * else + * { + * }; + * if((p_b == p_c)) + * { + * @a = true; + * } + * else + * { + * @a = false; + * }; + * }; + * } + */ + +int +arc_gen_SETEQ(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv p_b = tcg_temp_local_new_i32(); + TCGv p_c = tcg_temp_local_new_i32(); + TCGv take_branch = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + getCCFlag(temp_7); + tcg_gen_mov_i32(cc_flag, temp_7); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(p_b, b); + tcg_gen_mov_i32(p_c, c); + tcg_gen_mov_i32(take_branch, arc_false); + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_3, p_b, p_c); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, else_2); + tcg_gen_br(done_2); + gen_set_label(else_2); + gen_set_label(done_2); + TCGLabel *else_3 = gen_new_label(); + TCGLabel *done_3 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_5, p_b, p_c); + tcg_gen_xori_i32(temp_6, temp_5, 1); + tcg_gen_andi_i32(temp_6, temp_6, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_6, arc_true, else_3); + tcg_gen_mov_i32(a, arc_true); + tcg_gen_br(done_3); + gen_set_label(else_3); + tcg_gen_mov_i32(a, arc_false); + gen_set_label(done_3); + gen_set_label(done_1); + tcg_temp_free(temp_7); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(p_b); + tcg_temp_free(p_c); + tcg_temp_free(take_branch); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_5); + tcg_temp_free(temp_6); + + return ret; +} + + +/* + * BREQ + * Variables: @b, @c, @offset + * Functions: getPCL, shouldExecuteDelaySlot, executeDelaySlot, setPC + * --- code --- + * { + * p_b = @b; + * p_c = @c; + * take_branch = false; + * if((p_b == p_c)) + * { + * take_branch = true; + * } + * else + * { + * }; + * bta = (getPCL () + @offset); + * if((shouldExecuteDelaySlot () == 1)) + * { + * executeDelaySlot (bta, take_branch); + * }; + * if((p_b == p_c)) + * { + * setPC (bta); + * } + * else + * { + * }; + * } + */ + +int +arc_gen_BREQ(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) +{ + int ret = DISAS_NEXT; + TCGv p_b = tcg_temp_local_new_i32(); + TCGv p_c = tcg_temp_local_new_i32(); + TCGv take_branch = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv bta = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + tcg_gen_mov_i32(p_b, b); + tcg_gen_mov_i32(p_c, c); + tcg_gen_mov_i32(take_branch, arc_false); + TCGLabel *else_1 = gen_new_label(); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, p_b, p_c); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, else_1); + tcg_gen_mov_i32(take_branch, arc_true); + tcg_gen_br(done_1); + gen_set_label(else_1); + gen_set_label(done_1); + getPCL(temp_6); + tcg_gen_mov_i32(temp_5, temp_6); + tcg_gen_add_i32(bta, temp_5, offset); + if ((shouldExecuteDelaySlot () == 1)) { + executeDelaySlot(bta, take_branch); + } + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_3, p_b, p_c); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, else_2); + setPC(bta); + tcg_gen_br(done_2); + gen_set_label(else_2); + gen_set_label(done_2); + tcg_temp_free(p_b); + tcg_temp_free(p_c); + tcg_temp_free(take_branch); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_6); + tcg_temp_free(temp_5); + tcg_temp_free(bta); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + + return ret; +} + + +/* + * SETNE + * Variables: @b, @c, @a + * Functions: getCCFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * p_b = @b; + * p_c = @c; + * take_branch = false; + * if((p_b != p_c)) + * { + * } + * else + * { + * }; + * if((p_b != p_c)) + * { + * @a = true; + * } + * else + * { + * @a = false; + * }; + * }; + * } + */ + +int +arc_gen_SETNE(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv p_b = tcg_temp_local_new_i32(); + TCGv p_c = tcg_temp_local_new_i32(); + TCGv take_branch = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + getCCFlag(temp_7); + tcg_gen_mov_i32(cc_flag, temp_7); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(p_b, b); + tcg_gen_mov_i32(p_c, c); + tcg_gen_mov_i32(take_branch, arc_false); + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_NE, temp_3, p_b, p_c); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, else_2); + tcg_gen_br(done_2); + gen_set_label(else_2); + gen_set_label(done_2); + TCGLabel *else_3 = gen_new_label(); + TCGLabel *done_3 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_NE, temp_5, p_b, p_c); + tcg_gen_xori_i32(temp_6, temp_5, 1); + tcg_gen_andi_i32(temp_6, temp_6, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_6, arc_true, else_3); + tcg_gen_mov_i32(a, arc_true); + tcg_gen_br(done_3); + gen_set_label(else_3); + tcg_gen_mov_i32(a, arc_false); + gen_set_label(done_3); + gen_set_label(done_1); + tcg_temp_free(temp_7); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(p_b); + tcg_temp_free(p_c); + tcg_temp_free(take_branch); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_5); + tcg_temp_free(temp_6); + + return ret; +} + + +/* + * BRNE + * Variables: @b, @c, @offset + * Functions: getPCL, shouldExecuteDelaySlot, executeDelaySlot, setPC + * --- code --- + * { + * p_b = @b; + * p_c = @c; + * take_branch = false; + * if((p_b != p_c)) + * { + * take_branch = true; + * } + * else + * { + * }; + * bta = (getPCL () + @offset); + * if((shouldExecuteDelaySlot () == 1)) + * { + * executeDelaySlot (bta, take_branch); + * }; + * if((p_b != p_c)) + * { + * setPC (bta); + * } + * else + * { + * }; + * } + */ + +int +arc_gen_BRNE(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) +{ + int ret = DISAS_NEXT; + TCGv p_b = tcg_temp_local_new_i32(); + TCGv p_c = tcg_temp_local_new_i32(); + TCGv take_branch = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv bta = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + tcg_gen_mov_i32(p_b, b); + tcg_gen_mov_i32(p_c, c); + tcg_gen_mov_i32(take_branch, arc_false); + TCGLabel *else_1 = gen_new_label(); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_NE, temp_1, p_b, p_c); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, else_1); + tcg_gen_mov_i32(take_branch, arc_true); + tcg_gen_br(done_1); + gen_set_label(else_1); + gen_set_label(done_1); + getPCL(temp_6); + tcg_gen_mov_i32(temp_5, temp_6); + tcg_gen_add_i32(bta, temp_5, offset); + if ((shouldExecuteDelaySlot () == 1)) { + executeDelaySlot(bta, take_branch); + } + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_NE, temp_3, p_b, p_c); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, else_2); + setPC(bta); + tcg_gen_br(done_2); + gen_set_label(else_2); + gen_set_label(done_2); + tcg_temp_free(p_b); + tcg_temp_free(p_c); + tcg_temp_free(take_branch); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_6); + tcg_temp_free(temp_5); + tcg_temp_free(bta); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + + return ret; +} + + +/* + * SETLT + * Variables: @b, @c, @a + * Functions: getCCFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * p_b = @b; + * p_c = @c; + * take_branch = false; + * if((p_b < p_c)) + * { + * } + * else + * { + * }; + * if((p_b < p_c)) + * { + * @a = true; + * } + * else + * { + * @a = false; + * }; + * }; + * } + */ + +int +arc_gen_SETLT(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv p_b = tcg_temp_local_new_i32(); + TCGv p_c = tcg_temp_local_new_i32(); + TCGv take_branch = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + getCCFlag(temp_7); + tcg_gen_mov_i32(cc_flag, temp_7); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(p_b, b); + tcg_gen_mov_i32(p_c, c); + tcg_gen_mov_i32(take_branch, arc_false); + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_LT, temp_3, p_b, p_c); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, else_2); + tcg_gen_br(done_2); + gen_set_label(else_2); + gen_set_label(done_2); + TCGLabel *else_3 = gen_new_label(); + TCGLabel *done_3 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_LT, temp_5, p_b, p_c); + tcg_gen_xori_i32(temp_6, temp_5, 1); + tcg_gen_andi_i32(temp_6, temp_6, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_6, arc_true, else_3); + tcg_gen_mov_i32(a, arc_true); + tcg_gen_br(done_3); + gen_set_label(else_3); + tcg_gen_mov_i32(a, arc_false); + gen_set_label(done_3); + gen_set_label(done_1); + tcg_temp_free(temp_7); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(p_b); + tcg_temp_free(p_c); + tcg_temp_free(take_branch); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_5); + tcg_temp_free(temp_6); + + return ret; +} + + +/* + * BRLT + * Variables: @b, @c, @offset + * Functions: getPCL, shouldExecuteDelaySlot, executeDelaySlot, setPC + * --- code --- + * { + * p_b = @b; + * p_c = @c; + * take_branch = false; + * if((p_b < p_c)) + * { + * take_branch = true; + * } + * else + * { + * }; + * bta = (getPCL () + @offset); + * if((shouldExecuteDelaySlot () == 1)) + * { + * executeDelaySlot (bta, take_branch); + * }; + * if((p_b < p_c)) + * { + * setPC (bta); + * } + * else + * { + * }; + * } + */ + +int +arc_gen_BRLT(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) +{ + int ret = DISAS_NEXT; + TCGv p_b = tcg_temp_local_new_i32(); + TCGv p_c = tcg_temp_local_new_i32(); + TCGv take_branch = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv bta = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + tcg_gen_mov_i32(p_b, b); + tcg_gen_mov_i32(p_c, c); + tcg_gen_mov_i32(take_branch, arc_false); + TCGLabel *else_1 = gen_new_label(); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_LT, temp_1, p_b, p_c); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, else_1); + tcg_gen_mov_i32(take_branch, arc_true); + tcg_gen_br(done_1); + gen_set_label(else_1); + gen_set_label(done_1); + getPCL(temp_6); + tcg_gen_mov_i32(temp_5, temp_6); + tcg_gen_add_i32(bta, temp_5, offset); + if ((shouldExecuteDelaySlot () == 1)) { + executeDelaySlot(bta, take_branch); + } + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_LT, temp_3, p_b, p_c); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, else_2); + setPC(bta); + tcg_gen_br(done_2); + gen_set_label(else_2); + gen_set_label(done_2); + tcg_temp_free(p_b); + tcg_temp_free(p_c); + tcg_temp_free(take_branch); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_6); + tcg_temp_free(temp_5); + tcg_temp_free(bta); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + + return ret; +} + + +/* + * SETGE + * Variables: @b, @c, @a + * Functions: getCCFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * p_b = @b; + * p_c = @c; + * take_branch = false; + * if((p_b >= p_c)) + * { + * } + * else + * { + * }; + * if((p_b >= p_c)) + * { + * @a = true; + * } + * else + * { + * @a = false; + * }; + * }; + * } + */ + +int +arc_gen_SETGE(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv p_b = tcg_temp_local_new_i32(); + TCGv p_c = tcg_temp_local_new_i32(); + TCGv take_branch = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + getCCFlag(temp_7); + tcg_gen_mov_i32(cc_flag, temp_7); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(p_b, b); + tcg_gen_mov_i32(p_c, c); + tcg_gen_mov_i32(take_branch, arc_false); + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_GE, temp_3, p_b, p_c); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, else_2); + tcg_gen_br(done_2); + gen_set_label(else_2); + gen_set_label(done_2); + TCGLabel *else_3 = gen_new_label(); + TCGLabel *done_3 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_GE, temp_5, p_b, p_c); + tcg_gen_xori_i32(temp_6, temp_5, 1); + tcg_gen_andi_i32(temp_6, temp_6, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_6, arc_true, else_3); + tcg_gen_mov_i32(a, arc_true); + tcg_gen_br(done_3); + gen_set_label(else_3); + tcg_gen_mov_i32(a, arc_false); + gen_set_label(done_3); + gen_set_label(done_1); + tcg_temp_free(temp_7); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(p_b); + tcg_temp_free(p_c); + tcg_temp_free(take_branch); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_5); + tcg_temp_free(temp_6); + + return ret; +} + + +/* + * BRGE + * Variables: @b, @c, @offset + * Functions: getPCL, shouldExecuteDelaySlot, executeDelaySlot, setPC + * --- code --- + * { + * p_b = @b; + * p_c = @c; + * take_branch = false; + * if((p_b >= p_c)) + * { + * take_branch = true; + * } + * else + * { + * }; + * bta = (getPCL () + @offset); + * if((shouldExecuteDelaySlot () == 1)) + * { + * executeDelaySlot (bta, take_branch); + * }; + * if((p_b >= p_c)) + * { + * setPC (bta); + * } + * else + * { + * }; + * } + */ + +int +arc_gen_BRGE(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) +{ + int ret = DISAS_NEXT; + TCGv p_b = tcg_temp_local_new_i32(); + TCGv p_c = tcg_temp_local_new_i32(); + TCGv take_branch = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv bta = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + tcg_gen_mov_i32(p_b, b); + tcg_gen_mov_i32(p_c, c); + tcg_gen_mov_i32(take_branch, arc_false); + TCGLabel *else_1 = gen_new_label(); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_GE, temp_1, p_b, p_c); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, else_1); + tcg_gen_mov_i32(take_branch, arc_true); + tcg_gen_br(done_1); + gen_set_label(else_1); + gen_set_label(done_1); + getPCL(temp_6); + tcg_gen_mov_i32(temp_5, temp_6); + tcg_gen_add_i32(bta, temp_5, offset); + if ((shouldExecuteDelaySlot () == 1)) { + executeDelaySlot(bta, take_branch); + } + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_GE, temp_3, p_b, p_c); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, else_2); + setPC(bta); + tcg_gen_br(done_2); + gen_set_label(else_2); + gen_set_label(done_2); + tcg_temp_free(p_b); + tcg_temp_free(p_c); + tcg_temp_free(take_branch); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_6); + tcg_temp_free(temp_5); + tcg_temp_free(bta); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + + return ret; +} + + +/* + * SETLE + * Variables: @b, @c, @a + * Functions: getCCFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * p_b = @b; + * p_c = @c; + * take_branch = false; + * if((p_b <= p_c)) + * { + * } + * else + * { + * }; + * if((p_b <= p_c)) + * { + * @a = true; + * } + * else + * { + * @a = false; + * }; + * }; + * } + */ + +int +arc_gen_SETLE(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv p_b = tcg_temp_local_new_i32(); + TCGv p_c = tcg_temp_local_new_i32(); + TCGv take_branch = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + getCCFlag(temp_7); + tcg_gen_mov_i32(cc_flag, temp_7); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(p_b, b); + tcg_gen_mov_i32(p_c, c); + tcg_gen_mov_i32(take_branch, arc_false); + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_LE, temp_3, p_b, p_c); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, else_2); + tcg_gen_br(done_2); + gen_set_label(else_2); + gen_set_label(done_2); + TCGLabel *else_3 = gen_new_label(); + TCGLabel *done_3 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_LE, temp_5, p_b, p_c); + tcg_gen_xori_i32(temp_6, temp_5, 1); + tcg_gen_andi_i32(temp_6, temp_6, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_6, arc_true, else_3); + tcg_gen_mov_i32(a, arc_true); + tcg_gen_br(done_3); + gen_set_label(else_3); + tcg_gen_mov_i32(a, arc_false); + gen_set_label(done_3); + gen_set_label(done_1); + tcg_temp_free(temp_7); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(p_b); + tcg_temp_free(p_c); + tcg_temp_free(take_branch); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_5); + tcg_temp_free(temp_6); + + return ret; +} + + +/* + * SETGT + * Variables: @b, @c, @a + * Functions: getCCFlag + * --- code --- + * { + * cc_flag = getCCFlag (); + * if((cc_flag == true)) + * { + * p_b = @b; + * p_c = @c; + * take_branch = false; + * if((p_b > p_c)) + * { + * } + * else + * { + * }; + * if((p_b > p_c)) + * { + * @a = true; + * } + * else + * { + * @a = false; + * }; + * }; + * } + */ + +int +arc_gen_SETGT(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv cc_flag = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv p_b = tcg_temp_local_new_i32(); + TCGv p_c = tcg_temp_local_new_i32(); + TCGv take_branch = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + getCCFlag(temp_7); + tcg_gen_mov_i32(cc_flag, temp_7); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, cc_flag, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + tcg_gen_mov_i32(p_b, b); + tcg_gen_mov_i32(p_c, c); + tcg_gen_mov_i32(take_branch, arc_false); + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_GT, temp_3, p_b, p_c); + tcg_gen_xori_i32(temp_4, temp_3, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_4, arc_true, else_2); + tcg_gen_br(done_2); + gen_set_label(else_2); + gen_set_label(done_2); + TCGLabel *else_3 = gen_new_label(); + TCGLabel *done_3 = gen_new_label(); + tcg_gen_setcond_i32(TCG_COND_GT, temp_5, p_b, p_c); + tcg_gen_xori_i32(temp_6, temp_5, 1); + tcg_gen_andi_i32(temp_6, temp_6, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_6, arc_true, else_3); + tcg_gen_mov_i32(a, arc_true); + tcg_gen_br(done_3); + gen_set_label(else_3); + tcg_gen_mov_i32(a, arc_false); + gen_set_label(done_3); + gen_set_label(done_1); + tcg_temp_free(temp_7); + tcg_temp_free(cc_flag); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(p_b); + tcg_temp_free(p_c); + tcg_temp_free(take_branch); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_5); + tcg_temp_free(temp_6); + + return ret; +} + + +/* + * BRLO + * Variables: @b, @c, @offset + * Functions: unsignedLT, getPCL, shouldExecuteDelaySlot, executeDelaySlot, + * setPC + * --- code --- + * { + * p_b = @b; + * p_c = @c; + * take_branch = false; + * if(unsignedLT (p_b, p_c)) + * { + * take_branch = true; + * } + * else + * { + * }; + * bta = (getPCL () + @offset); + * if((shouldExecuteDelaySlot () == 1)) + * { + * executeDelaySlot (bta, take_branch); + * }; + * if(unsignedLT (p_b, p_c)) + * { + * setPC (bta); + * } + * else + * { + * }; + * } + */ + +int +arc_gen_BRLO(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) +{ + int ret = DISAS_NEXT; + TCGv p_b = tcg_temp_local_new_i32(); + TCGv p_c = tcg_temp_local_new_i32(); + TCGv take_branch = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv bta = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + tcg_gen_mov_i32(p_b, b); + tcg_gen_mov_i32(p_c, c); + tcg_gen_mov_i32(take_branch, arc_false); + TCGLabel *else_1 = gen_new_label(); + TCGLabel *done_1 = gen_new_label(); + unsignedLT(temp_3, p_b, p_c); + tcg_gen_xori_i32(temp_1, temp_3, 1); + tcg_gen_andi_i32(temp_1, temp_1, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_1, arc_true, else_1); + tcg_gen_mov_i32(take_branch, arc_true); + tcg_gen_br(done_1); + gen_set_label(else_1); + gen_set_label(done_1); + getPCL(temp_5); + tcg_gen_mov_i32(temp_4, temp_5); + tcg_gen_add_i32(bta, temp_4, offset); + if ((shouldExecuteDelaySlot () == 1)) { + executeDelaySlot(bta, take_branch); + } + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + unsignedLT(temp_6, p_b, p_c); + tcg_gen_xori_i32(temp_2, temp_6, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, else_2); + setPC(bta); + tcg_gen_br(done_2); + gen_set_label(else_2); + gen_set_label(done_2); + tcg_temp_free(p_b); + tcg_temp_free(p_c); + tcg_temp_free(take_branch); + tcg_temp_free(temp_3); + tcg_temp_free(temp_1); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + tcg_temp_free(bta); + tcg_temp_free(temp_6); + tcg_temp_free(temp_2); + + return ret; +} + + +/* + * SETLO + * Variables: @b, @c, @a + * Functions: unsignedLT + * --- code --- + * { + * p_b = @b; + * p_c = @c; + * take_branch = false; + * if(unsignedLT (p_b, p_c)) + * { + * } + * else + * { + * }; + * if(unsignedLT (p_b, p_c)) + * { + * @a = true; + * } + * else + * { + * @a = false; + * }; + * } + */ + +int +arc_gen_SETLO(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv p_b = tcg_temp_local_new_i32(); + TCGv p_c = tcg_temp_local_new_i32(); + TCGv take_branch = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + tcg_gen_mov_i32(p_b, b); + tcg_gen_mov_i32(p_c, c); + tcg_gen_mov_i32(take_branch, arc_false); + TCGLabel *else_1 = gen_new_label(); + TCGLabel *done_1 = gen_new_label(); + unsignedLT(temp_3, p_b, p_c); + tcg_gen_xori_i32(temp_1, temp_3, 1); + tcg_gen_andi_i32(temp_1, temp_1, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_1, arc_true, else_1); + tcg_gen_br(done_1); + gen_set_label(else_1); + gen_set_label(done_1); + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + unsignedLT(temp_4, p_b, p_c); + tcg_gen_xori_i32(temp_2, temp_4, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, else_2); + tcg_gen_mov_i32(a, arc_true); + tcg_gen_br(done_2); + gen_set_label(else_2); + tcg_gen_mov_i32(a, arc_false); + gen_set_label(done_2); + tcg_temp_free(p_b); + tcg_temp_free(p_c); + tcg_temp_free(take_branch); + tcg_temp_free(temp_3); + tcg_temp_free(temp_1); + tcg_temp_free(temp_4); + tcg_temp_free(temp_2); + + return ret; +} + + +/* + * BRHS + * Variables: @b, @c, @offset + * Functions: unsignedGE, getPCL, shouldExecuteDelaySlot, executeDelaySlot, + * setPC + * --- code --- + * { + * p_b = @b; + * p_c = @c; + * take_branch = false; + * if(unsignedGE (p_b, p_c)) + * { + * take_branch = true; + * } + * else + * { + * }; + * bta = (getPCL () + @offset); + * if((shouldExecuteDelaySlot () == 1)) + * { + * executeDelaySlot (bta, take_branch); + * }; + * if(unsignedGE (p_b, p_c)) + * { + * setPC (bta); + * } + * else + * { + * }; + * } + */ + +int +arc_gen_BRHS(DisasCtxt *ctx, TCGv b, TCGv c, TCGv offset) +{ + int ret = DISAS_NEXT; + TCGv p_b = tcg_temp_local_new_i32(); + TCGv p_c = tcg_temp_local_new_i32(); + TCGv take_branch = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv bta = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + tcg_gen_mov_i32(p_b, b); + tcg_gen_mov_i32(p_c, c); + tcg_gen_mov_i32(take_branch, arc_false); + TCGLabel *else_1 = gen_new_label(); + TCGLabel *done_1 = gen_new_label(); + unsignedGE(temp_3, p_b, p_c); + tcg_gen_xori_i32(temp_1, temp_3, 1); + tcg_gen_andi_i32(temp_1, temp_1, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_1, arc_true, else_1); + tcg_gen_mov_i32(take_branch, arc_true); + tcg_gen_br(done_1); + gen_set_label(else_1); + gen_set_label(done_1); + getPCL(temp_5); + tcg_gen_mov_i32(temp_4, temp_5); + tcg_gen_add_i32(bta, temp_4, offset); + if ((shouldExecuteDelaySlot () == 1)) { + executeDelaySlot(bta, take_branch); + } + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + unsignedGE(temp_6, p_b, p_c); + tcg_gen_xori_i32(temp_2, temp_6, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, else_2); + setPC(bta); + tcg_gen_br(done_2); + gen_set_label(else_2); + gen_set_label(done_2); + tcg_temp_free(p_b); + tcg_temp_free(p_c); + tcg_temp_free(take_branch); + tcg_temp_free(temp_3); + tcg_temp_free(temp_1); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + tcg_temp_free(bta); + tcg_temp_free(temp_6); + tcg_temp_free(temp_2); + + return ret; +} + + +/* + * SETHS + * Variables: @b, @c, @a + * Functions: unsignedGE + * --- code --- + * { + * p_b = @b; + * p_c = @c; + * take_branch = false; + * if(unsignedGE (p_b, p_c)) + * { + * } + * else + * { + * }; + * if(unsignedGE (p_b, p_c)) + * { + * @a = true; + * } + * else + * { + * @a = false; + * }; + * } + */ + +int +arc_gen_SETHS(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a) +{ + int ret = DISAS_NEXT; + TCGv p_b = tcg_temp_local_new_i32(); + TCGv p_c = tcg_temp_local_new_i32(); + TCGv take_branch = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + tcg_gen_mov_i32(p_b, b); + tcg_gen_mov_i32(p_c, c); + tcg_gen_mov_i32(take_branch, arc_false); + TCGLabel *else_1 = gen_new_label(); + TCGLabel *done_1 = gen_new_label(); + unsignedGE(temp_3, p_b, p_c); + tcg_gen_xori_i32(temp_1, temp_3, 1); + tcg_gen_andi_i32(temp_1, temp_1, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_1, arc_true, else_1); + tcg_gen_br(done_1); + gen_set_label(else_1); + gen_set_label(done_1); + TCGLabel *else_2 = gen_new_label(); + TCGLabel *done_2 = gen_new_label(); + unsignedGE(temp_4, p_b, p_c); + tcg_gen_xori_i32(temp_2, temp_4, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, else_2); + tcg_gen_mov_i32(a, arc_true); + tcg_gen_br(done_2); + gen_set_label(else_2); + tcg_gen_mov_i32(a, arc_false); + gen_set_label(done_2); + tcg_temp_free(p_b); + tcg_temp_free(p_c); + tcg_temp_free(take_branch); + tcg_temp_free(temp_3); + tcg_temp_free(temp_1); + tcg_temp_free(temp_4); + tcg_temp_free(temp_2); + + return ret; +} + + +/* + * EX + * Variables: @b, @c + * Functions: getMemory, setMemory + * --- code --- + * { + * temp = @b; + * @b = getMemory (@c, LONG); + * setMemory (@c, LONG, temp); + * } + */ + +int +arc_gen_EX(DisasCtxt *ctx, TCGv b, TCGv c) +{ + int ret = DISAS_NEXT; + TCGv temp = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + tcg_gen_mov_i32(temp, b); + getMemory(temp_1, c, LONG); + tcg_gen_mov_i32(b, temp_1); + setMemory(c, LONG, temp); + tcg_temp_free(temp); + tcg_temp_free(temp_1); + + return ret; +} + + +/* + * LLOCK + * Variables: @dest, @src + * Functions: getMemory, setLF + * --- code --- + * { + * @dest = getMemory (@src, LONG); + * setLF (1); + * } + */ + +int +arc_gen_LLOCK(DisasCtxt *ctx, TCGv dest, TCGv src) +{ + int ret = DISAS_NEXT; + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + getMemory(temp_1, src, LONG); + tcg_gen_mov_i32(dest, temp_1); + tcg_gen_movi_i32(temp_2, 1); + setLF(temp_2); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + + return ret; +} + + +/* + * LLOCKD + * Variables: @dest, @src + * Functions: getMemory, nextReg, setLF + * --- code --- + * { + * @dest = getMemory (@src, LONG); + * pair = nextReg (dest); + * pair = getMemory ((@src + 4), LONG); + * setLF (1); + * } + */ + +int +arc_gen_LLOCKD(DisasCtxt *ctx, TCGv dest, TCGv src) +{ + int ret = DISAS_NEXT; + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv pair = NULL; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + getMemory(temp_1, src, LONG); + tcg_gen_mov_i32(dest, temp_1); + pair = nextReg (dest); + tcg_gen_addi_i32(temp_3, src, 4); + getMemory(temp_2, temp_3, LONG); + tcg_gen_mov_i32(pair, temp_2); + tcg_gen_movi_i32(temp_4, 1); + setLF(temp_4); + tcg_temp_free(temp_1); + tcg_temp_free(temp_3); + tcg_temp_free(temp_2); + tcg_temp_free(temp_4); + + return ret; +} + + +/* + * SCOND + * Variables: @src, @dest + * Functions: getLF, setMemory, setZFlag, setLF + * --- code --- + * { + * lf = getLF (); + * if((lf == 1)) + * { + * setMemory (@src, LONG, @dest); + * }; + * setZFlag (!lf); + * setLF (0); + * } + */ + +int +arc_gen_SCOND(DisasCtxt *ctx, TCGv src, TCGv dest) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv lf = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + getLF(temp_3); + tcg_gen_mov_i32(lf, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcondi_i32(TCG_COND_EQ, temp_1, lf, 1); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + setMemory(src, LONG, dest); + gen_set_label(done_1); + tcg_gen_xori_i32(temp_4, lf, 1); + tcg_gen_andi_i32(temp_4, temp_4, 1); + setZFlag(temp_4); + tcg_gen_movi_i32(temp_5, 0); + setLF(temp_5); + tcg_temp_free(temp_3); + tcg_temp_free(lf); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_4); + tcg_temp_free(temp_5); + + return ret; +} + + +/* + * SCONDD + * Variables: @src, @dest + * Functions: getLF, setMemory, nextReg, setZFlag, setLF + * --- code --- + * { + * lf = getLF (); + * if((lf == 1)) + * { + * setMemory (@src, LONG, @dest); + * pair = nextReg (dest); + * setMemory ((@src + 4), LONG, pair); + * }; + * setZFlag (!lf); + * setLF (0); + * } + */ + +int +arc_gen_SCONDD(DisasCtxt *ctx, TCGv src, TCGv dest) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv lf = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv pair = NULL; + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + getLF(temp_3); + tcg_gen_mov_i32(lf, temp_3); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_setcondi_i32(TCG_COND_EQ, temp_1, lf, 1); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, done_1); + setMemory(src, LONG, dest); + pair = nextReg (dest); + tcg_gen_addi_i32(temp_4, src, 4); + setMemory(temp_4, LONG, pair); + gen_set_label(done_1); + tcg_gen_xori_i32(temp_5, lf, 1); + tcg_gen_andi_i32(temp_5, temp_5, 1); + setZFlag(temp_5); + tcg_gen_movi_i32(temp_6, 0); + setLF(temp_6); + tcg_temp_free(temp_3); + tcg_temp_free(lf); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_4); + tcg_temp_free(temp_5); + tcg_temp_free(temp_6); + + return ret; +} + + +/* + * DMB + * Variables: @a + * Functions: + * --- code --- + * { + * @a = @a; + * } + */ + +int +arc_gen_DMB(DisasCtxt *ctx, TCGv a) +{ + int ret = DISAS_NEXT; + + return ret; +} + + +/* + * LD + * Variables: @src1, @src2, @dest + * Functions: getAAFlag, getZZFlag, setDebugLD, getMemory, getFlagX, + * SignExtend, NoFurtherLoadsPending + * --- code --- + * { + * AA = getAAFlag (); + * ZZ = getZZFlag (); + * address = 0; + * if(((AA == 0) || (AA == 1))) + * { + * address = (@src1 + @src2); + * }; + * if((AA == 2)) + * { + * address = @src1; + * }; + * if(((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) + * { + * address = (@src1 + (@src2 << 2)); + * }; + * if(((AA == 3) && (ZZ == 2))) + * { + * address = (@src1 + (@src2 << 1)); + * }; + * l_src1 = @src1; + * l_src2 = @src2; + * setDebugLD (1); + * new_dest = getMemory (address, ZZ); + * if(((AA == 1) || (AA == 2))) + * { + * @src1 = (l_src1 + l_src2); + * }; + * if((getFlagX () == 1)) + * { + * new_dest = SignExtend (new_dest, ZZ); + * }; + * if(NoFurtherLoadsPending ()) + * { + * setDebugLD (0); + * }; + * @dest = new_dest; + * } + */ + +int +arc_gen_LD(DisasCtxt *ctx, TCGv src1, TCGv src2, TCGv dest) +{ + int ret = DISAS_NEXT; + int AA; + int ZZ; + TCGv address = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv l_src1 = tcg_temp_local_new_i32(); + TCGv l_src2 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv new_dest = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + AA = getAAFlag (); + ZZ = getZZFlag (); + tcg_gen_movi_i32(address, 0); + if (((AA == 0) || (AA == 1))) { + tcg_gen_add_i32(address, src1, src2); + } + if ((AA == 2)) { + tcg_gen_mov_i32(address, src1); + } + if (((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) { + tcg_gen_shli_i32(temp_2, src2, 2); + tcg_gen_add_i32(address, src1, temp_2); + } + if (((AA == 3) && (ZZ == 2))) { + tcg_gen_shli_i32(temp_3, src2, 1); + tcg_gen_add_i32(address, src1, temp_3); + } + tcg_gen_mov_i32(l_src1, src1); + tcg_gen_mov_i32(l_src2, src2); + tcg_gen_movi_i32(temp_4, 1); + setDebugLD(temp_4); + getMemory(temp_5, address, ZZ); + tcg_gen_mov_i32(new_dest, temp_5); + if (((AA == 1) || (AA == 2))) { + tcg_gen_add_i32(src1, l_src1, l_src2); + } + if ((getFlagX () == 1)) { + new_dest = SignExtend (new_dest, ZZ); + } + TCGLabel *done_1 = gen_new_label(); + NoFurtherLoadsPending(temp_6); + tcg_gen_xori_i32(temp_1, temp_6, 1); + tcg_gen_andi_i32(temp_1, temp_1, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_1, arc_true, done_1); + tcg_gen_movi_i32(temp_7, 0); + setDebugLD(temp_7); + gen_set_label(done_1); + tcg_gen_mov_i32(dest, new_dest); + tcg_temp_free(address); + tcg_temp_free(temp_2); + tcg_temp_free(temp_3); + tcg_temp_free(l_src1); + tcg_temp_free(l_src2); + tcg_temp_free(temp_4); + tcg_temp_free(temp_5); + tcg_temp_free(new_dest); + tcg_temp_free(temp_6); + tcg_temp_free(temp_1); + tcg_temp_free(temp_7); + + return ret; +} + + +/* + * LDD + * Variables: @src1, @src2, @dest + * Functions: getAAFlag, getZZFlag, setDebugLD, getMemory, nextReg, + * NoFurtherLoadsPending + * --- code --- + * { + * AA = getAAFlag (); + * ZZ = getZZFlag (); + * address = 0; + * if(((AA == 0) || (AA == 1))) + * { + * address = (@src1 + @src2); + * }; + * if((AA == 2)) + * { + * address = @src1; + * }; + * if(((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) + * { + * address = (@src1 + (@src2 << 2)); + * }; + * if(((AA == 3) && (ZZ == 2))) + * { + * address = (@src1 + (@src2 << 1)); + * }; + * l_src1 = @src1; + * l_src2 = @src2; + * setDebugLD (1); + * new_dest = getMemory (address, LONG); + * pair = nextReg (dest); + * pair = getMemory ((address + 4), LONG); + * if(((AA == 1) || (AA == 2))) + * { + * @src1 = (l_src1 + l_src2); + * }; + * if(NoFurtherLoadsPending ()) + * { + * setDebugLD (0); + * }; + * @dest = new_dest; + * } + */ + +int +arc_gen_LDD(DisasCtxt *ctx, TCGv src1, TCGv src2, TCGv dest) +{ + int ret = DISAS_NEXT; + int AA; + int ZZ; + TCGv address = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv l_src1 = tcg_temp_local_new_i32(); + TCGv l_src2 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv new_dest = tcg_temp_local_new_i32(); + TCGv pair = NULL; + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_9 = tcg_temp_local_new_i32(); + AA = getAAFlag (); + ZZ = getZZFlag (); + tcg_gen_movi_i32(address, 0); + if (((AA == 0) || (AA == 1))) { + tcg_gen_add_i32(address, src1, src2); + } + if ((AA == 2)) { + tcg_gen_mov_i32(address, src1); + } + if (((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) { + tcg_gen_shli_i32(temp_2, src2, 2); + tcg_gen_add_i32(address, src1, temp_2); + } + if (((AA == 3) && (ZZ == 2))) { + tcg_gen_shli_i32(temp_3, src2, 1); + tcg_gen_add_i32(address, src1, temp_3); + } + tcg_gen_mov_i32(l_src1, src1); + tcg_gen_mov_i32(l_src2, src2); + tcg_gen_movi_i32(temp_4, 1); + setDebugLD(temp_4); + getMemory(temp_5, address, LONG); + tcg_gen_mov_i32(new_dest, temp_5); + pair = nextReg (dest); + tcg_gen_addi_i32(temp_7, address, 4); + getMemory(temp_6, temp_7, LONG); + tcg_gen_mov_i32(pair, temp_6); + if (((AA == 1) || (AA == 2))) { + tcg_gen_add_i32(src1, l_src1, l_src2); + } + TCGLabel *done_1 = gen_new_label(); + NoFurtherLoadsPending(temp_8); + tcg_gen_xori_i32(temp_1, temp_8, 1); + tcg_gen_andi_i32(temp_1, temp_1, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_1, arc_true, done_1); + tcg_gen_movi_i32(temp_9, 0); + setDebugLD(temp_9); + gen_set_label(done_1); + tcg_gen_mov_i32(dest, new_dest); + tcg_temp_free(address); + tcg_temp_free(temp_2); + tcg_temp_free(temp_3); + tcg_temp_free(l_src1); + tcg_temp_free(l_src2); + tcg_temp_free(temp_4); + tcg_temp_free(temp_5); + tcg_temp_free(new_dest); + tcg_temp_free(temp_7); + tcg_temp_free(temp_6); + tcg_temp_free(temp_8); + tcg_temp_free(temp_1); + tcg_temp_free(temp_9); + + return ret; +} + + +/* + * ST + * Variables: @src1, @src2, @dest + * Functions: getAAFlag, getZZFlag, setMemory + * --- code --- + * { + * AA = getAAFlag (); + * ZZ = getZZFlag (); + * address = 0; + * if(((AA == 0) || (AA == 1))) + * { + * address = (@src1 + @src2); + * }; + * if((AA == 2)) + * { + * address = @src1; + * }; + * if(((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) + * { + * address = (@src1 + (@src2 << 2)); + * }; + * if(((AA == 3) && (ZZ == 2))) + * { + * address = (@src1 + (@src2 << 1)); + * }; + * setMemory (address, ZZ, @dest); + * if(((AA == 1) || (AA == 2))) + * { + * @src1 = (@src1 + @src2); + * }; + * } + */ + +int +arc_gen_ST(DisasCtxt *ctx, TCGv src1, TCGv src2, TCGv dest) +{ + int ret = DISAS_NEXT; + int AA; + int ZZ; + TCGv address = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + AA = getAAFlag (); + ZZ = getZZFlag (); + tcg_gen_movi_i32(address, 0); + if (((AA == 0) || (AA == 1))) { + tcg_gen_add_i32(address, src1, src2); + } + if ((AA == 2)) { + tcg_gen_mov_i32(address, src1); + } + if (((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) { + tcg_gen_shli_i32(temp_1, src2, 2); + tcg_gen_add_i32(address, src1, temp_1); + } + if (((AA == 3) && (ZZ == 2))) { + tcg_gen_shli_i32(temp_2, src2, 1); + tcg_gen_add_i32(address, src1, temp_2); + } + setMemory(address, ZZ, dest); + if (((AA == 1) || (AA == 2))) { + tcg_gen_add_i32(src1, src1, src2); + } + tcg_temp_free(address); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + + return ret; +} + + +/* + * STD + * Variables: @src1, @src2, @dest + * Functions: getAAFlag, getZZFlag, setMemory, + * instructionHasRegisterOperandIn, nextReg, getBit + * --- code --- + * { + * AA = getAAFlag (); + * ZZ = getZZFlag (); + * address = 0; + * if(((AA == 0) || (AA == 1))) + * { + * address = (@src1 + @src2); + * }; + * if((AA == 2)) + * { + * address = @src1; + * }; + * if(((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) + * { + * address = (@src1 + (@src2 << 2)); + * }; + * if(((AA == 3) && (ZZ == 2))) + * { + * address = (@src1 + (@src2 << 1)); + * }; + * setMemory (address, LONG, @dest); + * if(instructionHasRegisterOperandIn (0)) + * { + * pair = nextReg (dest); + * } + * else + * { + * if((getBit (@dest, 31) == 1)) + * { + * pair = 4294967295; + * } + * else + * { + * pair = 0; + * }; + * }; + * setMemory ((address + 4), LONG, pair); + * if(((AA == 1) || (AA == 2))) + * { + * @src1 = (@src1 + @src2); + * }; + * } + */ + +int +arc_gen_STD(DisasCtxt *ctx, TCGv src1, TCGv src2, TCGv dest) +{ + int ret = DISAS_NEXT; + int AA; + int ZZ; + TCGv address = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv pair = NULL; + bool pair_initialized = FALSE; + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + AA = getAAFlag (); + ZZ = getZZFlag (); + tcg_gen_movi_i32(address, 0); + if (((AA == 0) || (AA == 1))) { + tcg_gen_add_i32(address, src1, src2); + } + if ((AA == 2)) { + tcg_gen_mov_i32(address, src1); + } + if (((AA == 3) && ((ZZ == 0) || (ZZ == 3)))) { + tcg_gen_shli_i32(temp_3, src2, 2); + tcg_gen_add_i32(address, src1, temp_3); + } + if (((AA == 3) && (ZZ == 2))) { + tcg_gen_shli_i32(temp_4, src2, 1); + tcg_gen_add_i32(address, src1, temp_4); + } + setMemory(address, LONG, dest); + if (instructionHasRegisterOperandIn (0)) { + pair = nextReg (dest); + } else { + TCGLabel *else_1 = gen_new_label(); + TCGLabel *done_1 = gen_new_label(); + tcg_gen_movi_i32(temp_6, 31); + getBit(temp_5, dest, temp_6); + tcg_gen_setcondi_i32(TCG_COND_EQ, temp_1, temp_5, 1); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, else_1); + pair = tcg_temp_local_new_i32(); + pair_initialized = TRUE; + tcg_gen_movi_i32(pair, 4294967295); + tcg_gen_br(done_1); + gen_set_label(else_1); + tcg_gen_movi_i32(pair, 0); + gen_set_label(done_1); + } + + tcg_gen_addi_i32(temp_7, address, 4); + setMemory(temp_7, LONG, pair); + if (((AA == 1) || (AA == 2))) { + tcg_gen_add_i32(src1, src1, src2); + } + tcg_temp_free(address); + tcg_temp_free(temp_3); + tcg_temp_free(temp_4); + tcg_temp_free(temp_6); + tcg_temp_free(temp_5); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_7); + if (pair_initialized) { + tcg_temp_free(pair); + } + + return ret; +} + + +/* + * ENTER_S + * Variables: @u6 + * Functions: helperEnter + * --- code --- + * { + * helperEnter (@u6); + * } + */ + +int +arc_gen_ENTER_S(DisasCtxt *ctx, TCGv u6) +{ + int ret = DISAS_NEXT; + + helperEnter(u6); + return ret; +} + + +/* + * LEAVE_S + * Variables: @u7 + * Functions: helperLeave + * --- code --- + * { + * helperLeave (@u7); + * } + */ + +int +arc_gen_LEAVE_S(DisasCtxt *ctx, TCGv u7) +{ + int ret = DISAS_NEXT; + + helperLeave(u7); + return ret; +} + + +/* + * POP + * Variables: @dest + * Functions: getMemory, getRegister, setRegister + * --- code --- + * { + * new_dest = getMemory (getRegister (R_SP), LONG); + * setRegister (R_SP, (getRegister (R_SP) + 4)); + * @dest = new_dest; + * } + */ + +int +arc_gen_POP(DisasCtxt *ctx, TCGv dest) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv new_dest = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + getRegister(temp_3, R_SP); + tcg_gen_mov_i32(temp_2, temp_3); + getMemory(temp_1, temp_2, LONG); + tcg_gen_mov_i32(new_dest, temp_1); + getRegister(temp_6, R_SP); + tcg_gen_mov_i32(temp_5, temp_6); + tcg_gen_addi_i32(temp_4, temp_5, 4); + setRegister(R_SP, temp_4); + tcg_gen_mov_i32(dest, new_dest); + tcg_temp_free(temp_3); + tcg_temp_free(temp_2); + tcg_temp_free(temp_1); + tcg_temp_free(new_dest); + tcg_temp_free(temp_6); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + + return ret; +} + + +/* + * PUSH + * Variables: @src + * Functions: setMemory, getRegister, setRegister + * --- code --- + * { + * local_src = @src; + * setMemory ((getRegister (R_SP) - 4), LONG, local_src); + * setRegister (R_SP, (getRegister (R_SP) - 4)); + * } + */ + +int +arc_gen_PUSH(DisasCtxt *ctx, TCGv src) +{ + int ret = DISAS_NEXT; + TCGv local_src = tcg_temp_local_new_i32(); + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + tcg_gen_mov_i32(local_src, src); + getRegister(temp_3, R_SP); + tcg_gen_mov_i32(temp_2, temp_3); + tcg_gen_subi_i32(temp_1, temp_2, 4); + setMemory(temp_1, LONG, local_src); + getRegister(temp_6, R_SP); + tcg_gen_mov_i32(temp_5, temp_6); + tcg_gen_subi_i32(temp_4, temp_5, 4); + setRegister(R_SP, temp_4); + tcg_temp_free(local_src); + tcg_temp_free(temp_3); + tcg_temp_free(temp_2); + tcg_temp_free(temp_1); + tcg_temp_free(temp_6); + tcg_temp_free(temp_5); + tcg_temp_free(temp_4); + + return ret; +} + + +/* + * LP + * Variables: @rd + * Functions: getCCFlag, getRegIndex, writeAuxReg, nextInsnAddress, getPCL, + * setPC + * --- code --- + * { + * if((getCCFlag () == true)) + * { + * lp_start_index = getRegIndex (LP_START); + * lp_end_index = getRegIndex (LP_END); + * writeAuxReg (lp_start_index, nextInsnAddress ()); + * writeAuxReg (lp_end_index, (getPCL () + @rd)); + * } + * else + * { + * setPC ((getPCL () + @rd)); + * }; + * } + */ + +int +arc_gen_LP(DisasCtxt *ctx, TCGv rd) +{ + int ret = DISAS_NEXT; + TCGv temp_3 = tcg_temp_local_new_i32(); + TCGv temp_1 = tcg_temp_local_new_i32(); + TCGv temp_2 = tcg_temp_local_new_i32(); + TCGv temp_4 = tcg_temp_local_new_i32(); + TCGv lp_start_index = tcg_temp_local_new_i32(); + TCGv temp_5 = tcg_temp_local_new_i32(); + TCGv lp_end_index = tcg_temp_local_new_i32(); + TCGv temp_7 = tcg_temp_local_new_i32(); + TCGv temp_6 = tcg_temp_local_new_i32(); + TCGv temp_10 = tcg_temp_local_new_i32(); + TCGv temp_9 = tcg_temp_local_new_i32(); + TCGv temp_8 = tcg_temp_local_new_i32(); + TCGv temp_13 = tcg_temp_local_new_i32(); + TCGv temp_12 = tcg_temp_local_new_i32(); + TCGv temp_11 = tcg_temp_local_new_i32(); + TCGLabel *else_1 = gen_new_label(); + TCGLabel *done_1 = gen_new_label(); + getCCFlag(temp_3); + tcg_gen_setcond_i32(TCG_COND_EQ, temp_1, temp_3, arc_true); + tcg_gen_xori_i32(temp_2, temp_1, 1); + tcg_gen_andi_i32(temp_2, temp_2, 1); + tcg_gen_brcond_i32(TCG_COND_EQ, temp_2, arc_true, else_1); + getRegIndex(temp_4, LP_START); + tcg_gen_mov_i32(lp_start_index, temp_4); + getRegIndex(temp_5, LP_END); + tcg_gen_mov_i32(lp_end_index, temp_5); + nextInsnAddress(temp_7); + tcg_gen_mov_i32(temp_6, temp_7); + writeAuxReg(lp_start_index, temp_6); + getPCL(temp_10); + tcg_gen_mov_i32(temp_9, temp_10); + tcg_gen_add_i32(temp_8, temp_9, rd); + writeAuxReg(lp_end_index, temp_8); + tcg_gen_br(done_1); + gen_set_label(else_1); + getPCL(temp_13); + tcg_gen_mov_i32(temp_12, temp_13); + tcg_gen_add_i32(temp_11, temp_12, rd); + setPC(temp_11); + gen_set_label(done_1); + tcg_temp_free(temp_3); + tcg_temp_free(temp_1); + tcg_temp_free(temp_2); + tcg_temp_free(temp_4); + tcg_temp_free(lp_start_index); + tcg_temp_free(temp_5); + tcg_temp_free(lp_end_index); + tcg_temp_free(temp_7); + tcg_temp_free(temp_6); + tcg_temp_free(temp_10); + tcg_temp_free(temp_9); + tcg_temp_free(temp_8); + tcg_temp_free(temp_13); + tcg_temp_free(temp_12); + tcg_temp_free(temp_11); + + return ret; +} + + +/* + * NORM + * Variables: @src, @dest + * Functions: HELPER, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * psrc = @src; + * i = HELPER (norm, psrc); + * @dest = (31 - i); + * if((getFFlag () == true)) + * { + * setZFlag (psrc); + * setNFlag (psrc); + * }; + * } + */ + +int +arc_gen_NORM(DisasCtxt *ctx, TCGv src, TCGv dest) +{ + int ret = DISAS_NEXT; + TCGv psrc = tcg_temp_local_new_i32(); + TCGv i = tcg_temp_local_new_i32(); + tcg_gen_mov_i32(psrc, src); + ARC_HELPER(norm, i, psrc); + tcg_gen_subfi_i32(dest, 31, i); + if ((getFFlag () == true)) { + setZFlag(psrc); + setNFlag(psrc); + } + tcg_temp_free(psrc); + tcg_temp_free(i); + + return ret; +} + + +/* + * NORMH + * Variables: @src, @dest + * Functions: HELPER, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * lsrc = (@src & 65535); + * i = HELPER (normh, lsrc); + * @dest = (15 - i); + * if((getFFlag () == true)) + * { + * setZFlag (lsrc); + * setNFlag (lsrc); + * }; + * } + */ + +int +arc_gen_NORMH(DisasCtxt *ctx, TCGv src, TCGv dest) +{ + int ret = DISAS_NEXT; + TCGv lsrc = tcg_temp_local_new_i32(); + TCGv i = tcg_temp_local_new_i32(); + tcg_gen_andi_i32(lsrc, src, 65535); + ARC_HELPER(normh, i, lsrc); + tcg_gen_subfi_i32(dest, 15, i); + if ((getFFlag () == true)) { + setZFlag(lsrc); + setNFlag(lsrc); + } + tcg_temp_free(lsrc); + tcg_temp_free(i); + + return ret; +} + + +/* + * FLS + * Variables: @src, @dest + * Functions: HELPER, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * psrc = @src; + * @dest = HELPER (fls, psrc); + * if((getFFlag () == true)) + * { + * setZFlag (psrc); + * setNFlag (psrc); + * }; + * } + */ + +int +arc_gen_FLS(DisasCtxt *ctx, TCGv src, TCGv dest) +{ + int ret = DISAS_NEXT; + TCGv psrc = tcg_temp_local_new_i32(); + tcg_gen_mov_i32(psrc, src); + ARC_HELPER(fls, dest, psrc); + if ((getFFlag () == true)) { + setZFlag(psrc); + setNFlag(psrc); + } + tcg_temp_free(psrc); + + return ret; +} + + +/* + * FFS + * Variables: @src, @dest + * Functions: HELPER, getFFlag, setZFlag, setNFlag + * --- code --- + * { + * psrc = @src; + * @dest = HELPER (ffs, psrc); + * if((getFFlag () == true)) + * { + * setZFlag (psrc); + * setNFlag (psrc); + * }; + * } + */ + +int +arc_gen_FFS(DisasCtxt *ctx, TCGv src, TCGv dest) +{ + int ret = DISAS_NEXT; + TCGv psrc = tcg_temp_local_new_i32(); + tcg_gen_mov_i32(psrc, src); + ARC_HELPER(ffs, dest, psrc); + if ((getFFlag () == true)) { + setZFlag(psrc); + setNFlag(psrc); + } + tcg_temp_free(psrc); + + return ret; +} diff --git a/target/arc/semfunc.h b/target/arc/semfunc.h new file mode 100644 index 0000000000..3d29569228 --- /dev/null +++ b/target/arc/semfunc.h @@ -0,0 +1,62 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synppsys Inc. + * Contributed by Cupertino Miranda + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#ifndef __ARC_SEMFUNC_H__ +#define __ARC_SEMFUNC_H__ + +#include "translate.h" +#include "semfunc-helper.h" + +/* TODO (issue #62): these must be removed */ +#define arc_false (ctx->zero) +#define arc_true (ctx->one) + +#define LONG 0 +#define BYTE 1 +#define WORD 2 + +#define SEMANTIC_FUNCTION_PROTOTYPE_0(NAME) \ + int arc_gen_##NAME(DisasCtxt *); +#define SEMANTIC_FUNCTION_PROTOTYPE_1(NAME) \ + int arc_gen_##NAME(DisasCtxt *, TCGv); +#define SEMANTIC_FUNCTION_PROTOTYPE_2(NAME) \ + int arc_gen_##NAME(DisasCtxt *, TCGv, TCGv); +#define SEMANTIC_FUNCTION_PROTOTYPE_3(NAME) \ + int arc_gen_##NAME(DisasCtxt *, TCGv, TCGv, TCGv); +#define SEMANTIC_FUNCTION_PROTOTYPE_4(NAME) \ + int arc_gen_##NAME(DisasCtxt *, TCGv, TCGv, TCGv, TCGv); + +#define MAPPING(MNEMONIC, NAME, NOPS, ...) +#define CONSTANT(...) +#define SEMANTIC_FUNCTION(NAME, NOPS) \ + SEMANTIC_FUNCTION_PROTOTYPE_##NOPS(NAME) + +#include "target/arc/semfunc_mapping.def" + +#undef MAPPING +#undef CONSTANT +#undef SEMANTIC_FUNCTION_PROTOTYPE_0 +#undef SEMANTIC_FUNCTION_PROTOTYPE_1 +#undef SEMANTIC_FUNCTION_PROTOTYPE_2 +#undef SEMANTIC_FUNCTION_PROTOTYPE_3 +#undef SEMANTIC_FUNCTION + +#endif /* __ARC_SEMFUNC_H__ */ From patchwork Wed Nov 11 16:17:50 2020 Content-Type: text/plain; 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[2.80.104.46]) by smtp.gmail.com with ESMTPSA id s188sm3115178wmf.45.2020.11.11.08.18.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2020 08:18:13 -0800 (PST) From: cupertinomiranda@gmail.com To: qemu-devel@nongnu.org Subject: [PATCH 07/15] arc: Add BCR and AUX registers implementation Date: Wed, 11 Nov 2020 16:17:50 +0000 Message-Id: <20201111161758.9636-8-cupertinomiranda@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201111161758.9636-1-cupertinomiranda@gmail.com> References: <20201111161758.9636-1-cupertinomiranda@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201111_111816_721701_DA91A5D4 X-CRM114-Status: GOOD ( 22.99 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:442 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [cupertinomiranda[at]gmail.com] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Claudiu Zissulescu , Cupertino Miranda , Shahab Vahedi , Shahab Vahedi , Cupertino Miranda , linux-snps-arc@lists.infradead.org, Claudiu Zissulescu Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Cupertino Miranda Add the infrastructure to define build configuration (BCR) and auxiliary registers allowing independent modules (MMU, MPU, etc.) to use and extend them. Signed-off-by: Cupertino Miranda --- target/arc/cache.c | 182 +++++++++++++ target/arc/cache.h | 42 +++ target/arc/regs-detail.def | 538 +++++++++++++++++++++++++++++++++++++ target/arc/regs.c | 139 ++++++++++ target/arc/regs.def | 396 +++++++++++++++++++++++++++ target/arc/regs.h | 118 ++++++++ 6 files changed, 1415 insertions(+) create mode 100644 target/arc/cache.c create mode 100644 target/arc/cache.h create mode 100644 target/arc/regs-detail.def create mode 100644 target/arc/regs.c create mode 100644 target/arc/regs.def create mode 100644 target/arc/regs.h diff --git a/target/arc/cache.c b/target/arc/cache.c new file mode 100644 index 0000000000..b5495782a6 --- /dev/null +++ b/target/arc/cache.c @@ -0,0 +1,182 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synppsys Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#include "qemu/osdep.h" +#include "hw/hw.h" +#include "cpu.h" +#include "target/arc/regs.h" +#include "target/arc/cache.h" + +void arc_cache_aux_set(const struct arc_aux_reg_detail *aux_reg_detail, + uint32_t val, void *data) +{ + + CPUARCState *env = (CPUARCState *) data; + struct arc_cache *cache = &env->cache; + + switch (aux_reg_detail->id) { + case AUX_ID_ic_ivic: + case AUX_ID_ic_ivil: + case AUX_ID_dc_ivdc: + case AUX_ID_dc_ivdl: + case AUX_ID_dc_flsh: + case AUX_ID_dc_fldl: + case AUX_ID_dc_startr: + /* Do nothing as we don't simulate cache memories */ + break; + + case AUX_ID_ic_ctrl: + cache->ic_disabled = val & 1; + break; + + case AUX_ID_ic_ivir: + cache->ic_ivir = val & 0xffffff00; + break; + + case AUX_ID_ic_endr: + cache->ic_endr = val & 0xffffff00; + break; + + case AUX_ID_ic_ptag: + cache->ic_ptag = val; + break; + + case AUX_ID_ic_ptag_hi: + cache->ic_ptag_hi = val & 0xff; + break; + +/* + * Description of the register content in order: + * DC - Disable Cache: Enables/Disables the cache: 0 - Enabled, 1 - Disabled + * IM - Invalidate Mode: Selects the invalidate type + */ + case AUX_ID_dc_ctrl: + cache->dc_disabled = val & 1; /* DC */ + cache->dc_inv_mode = (val >> 6) & 1; /* IM */ + break; + + case AUX_ID_dc_endr: + cache->dc_endr = val & 0xffffff00; + break; + + case AUX_ID_dc_ptag_hi: + cache->dc_ptag_hi = val & 0xff; + break; + + default: + hw_error("%s@%d: Attempt to write read-only register 0x%02x!\n", + __func__, __LINE__, (unsigned int)aux_reg_detail->id); + break; + } + + return; +} + +uint32_t arc_cache_aux_get(const struct arc_aux_reg_detail *aux_reg_detail, + void *data) +{ + CPUARCState *env = (CPUARCState *) data; + struct arc_cache *cache = &env->cache; + uint32_t reg = 0; + + switch (aux_reg_detail->id) { +/* + * Description of the register content in order. + * Layout: -------- -DFFBBBB CCCCAAAA VVVVVVVV + * D - indicates that IC is disabled on reset + * FL - Feature level: 10b - line lock, invalidate, advanced debug features + * BSize - indicates the cache block size in bytes: 0011b - 64 bytes + * Cache capacity: 0111b - 64 Kbytes + * Cache Associativiy: 0010b - Four-way set associative + * Version number: 4 - ARCv2 + */ + case AUX_ID_i_cache_build: + reg = (0 << 22) | /* D */ + (2 << 20) | /* FL */ + (3 << 16) | /* BBSixe*/ + (7 << 12) | /* Cache capacity */ + (2 << 8) | /* Cache Associativiy */ + (4 << 0); /* Version Number */ + break; + + case AUX_ID_ic_ctrl: + reg = cache->ic_disabled & 1; + break; + + case AUX_ID_ic_ivir: + reg = cache->ic_ivir; + break; + + case AUX_ID_ic_endr: + reg = cache->ic_endr; + break; + + case AUX_ID_ic_ptag: + reg = cache->ic_ptag; + break; + + case AUX_ID_ic_ptag_hi: + reg = cache->ic_ptag_hi; + break; + +/* + * Description of the register content in order: + * FL - Feature level: 10b - line lock, invalidate, advanced debug features + * BSize - indicates the cache block size in bytes: 0010b - 64 bytes + * Cache capacity: 0111b - 64 Kbytes + * Cache Associativiy: 0001b - Two-way set associative + * Version number: 4 - ARCv2 with fixed number of cycles + */ + case AUX_ID_d_cache_build: + reg = (2 << 20) | /* FL */ + (2 << 16) | /* BSize */ + (7 << 12) | /* Cache capacity */ + (1 << 8) | /* Cache Associativiy */ + (4 << 0); /* Version number */ + break; + +/* + * Description of the register content in order: + * DC - Disable Cache: Enables/Disables the cache: 0 - Enabled, 1 - Disabled + * SB - Success Bit: of last cache operation: 1 - succeded (immediately) + * IM - Invalidate Mode: Selects the invalidate type + */ + case AUX_ID_dc_ctrl: + reg = (cache->dc_disabled & 1) << 0 | /* DC */ + (1 << 2) | /* SB */ + (cache->dc_inv_mode & 1) << 6; /* IM */ + break; + + case AUX_ID_dc_endr: + reg = cache->dc_endr; + break; + + case AUX_ID_dc_ptag_hi: + reg = cache->dc_ptag_hi; + break; + + default: + hw_error("%s@%d: Attempt to read write-only register 0x%02x!\n", + __func__, __LINE__, (unsigned int)aux_reg_detail->id); + break; + } + + return reg; +} diff --git a/target/arc/cache.h b/target/arc/cache.h new file mode 100644 index 0000000000..c8167a07a1 --- /dev/null +++ b/target/arc/cache.h @@ -0,0 +1,42 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2019 Synopsys, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef __ARC_CACHE_H__ +#define __ARC_CACHE_H__ + +#include "target/arc/regs.h" + +struct arc_cache { + bool ic_disabled; + bool dc_disabled; + bool dc_inv_mode; + uint32_t ic_ivir; + uint32_t ic_endr; + uint32_t ic_ptag; + uint32_t ic_ptag_hi; + uint32_t dc_endr; + uint32_t dc_ptag_hi; +}; + +void arc_cache_aux_set(const struct arc_aux_reg_detail *aux_reg_detail, + uint32_t val, void *data); + +uint32_t arc_cache_aux_get(const struct arc_aux_reg_detail *aux_reg_detail, + void *data); + +#endif /* __ARC_CACHE_H__ */ diff --git a/target/arc/regs-detail.def b/target/arc/regs-detail.def new file mode 100644 index 0000000000..86f5123d6a --- /dev/null +++ b/target/arc/regs-detail.def @@ -0,0 +1,538 @@ +/* + * QEMU ARC Auxiliary register definitions + * + * Copyright (c) 2020 Synopsys, Inc. + * Contributed by Claudiu Zissulescu (claziss@synopsys.com) + * Contributed by Cupertino Miranda (cmiranda@synopsys.com) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +/* INFO: this list must be kept ordered by address to allow + * binary search of register information based on address. + */ + +DEF(0xffff,ARC_OPCODE_ARCALL, NONE, unimp_bcr) +DEF(0x1, ARC_OPCODE_ARCV1, NONE, semaphore) +DEF(0x2, ARC_OPCODE_ARCALL, NONE, lp_start) +DEF(0x3, ARC_OPCODE_ARCALL, NONE, lp_end) +DEF(0x4, ARC_OPCODE_ARCALL, NONE, identity) +DEF(0x5, ARC_OPCODE_ARCALL, NONE, debug) +DEF(0x6, ARC_OPCODE_ARCALL, NONE, pc) +DEF(0x7, ARC_OPCODE_ARCv2HS, NONE, memseg) +DEF(0x7, ARC_OPCODE_ARCV1, NONE, adcr) +DEF(0x8, ARC_OPCODE_ARCV1, NONE, apcr) +DEF(0x8, ARC_OPCODE_ARCv2HS, NONE, exec_ctrl) +DEF(0x9, ARC_OPCODE_ARCV1, NONE, acr) +DEF(0x9, ARC_OPCODE_ARCv2EM, NONE, sec_stat) +DEF(0xa, ARC_OPCODE_ARCALL, NONE, status32) +DEF(0xb, ARC_OPCODE_ARCV2, NONE, status32_p0) +DEF(0xc, ARC_OPCODE_ARCv2EM, NONE, sec_extra) +DEF(0xd, ARC_OPCODE_ARCV2, NONE, aux_user_sp) +DEF(0xe, ARC_OPCODE_ARC700, NONE, clk_enable) +DEF(0xe, ARC_OPCODE_ARCV2, NONE, aux_irq_ctrl) +DEF(0xf, ARC_OPCODE_ARC700, NONE, bpu_flush) +DEF(0xf, ARC_OPCODE_ARCv2HS, NONE, debugi) +DEF(0x10, ARC_OPCODE_ARCV1, NONE, ivic) +DEF(0x10, ARC_OPCODE_ARCALL, NONE, ic_ivic) +DEF(0x11, ARC_OPCODE_ARCV1, NONE, che_mode) +DEF(0x11, ARC_OPCODE_ARCALL, NONE, ic_ctrl) +DEF(0x12, ARC_OPCODE_ARC600, NONE, mulhi) +DEF(0x12, ARC_OPCODE_ARCv2HS, NONE, ic_startr) +DEF(0x13, ARC_OPCODE_ARCV1, NONE, lockline) +DEF(0x13, ARC_OPCODE_ARCV2, NONE, ic_lil) +DEF(0x14, ARC_OPCODE_ARC600, NONE, dmc_code_ram) +DEF(0x15, ARC_OPCODE_ARCV1, NONE, tag_addr_mask) +DEF(0x16, ARC_OPCODE_ARCV1, NONE, tag_data_mask) +DEF(0x16, ARC_OPCODE_ARCv2HS, NONE, ic_ivir) +DEF(0x17, ARC_OPCODE_ARCV1, NONE, line_length_mask) +DEF(0x17, ARC_OPCODE_ARCv2HS, NONE, ic_endr) +DEF(0x18, ARC_OPCODE_ARC600, NONE, aux_ldst_ram) +DEF(0x18, ARC_OPCODE_NONE, NONE, aux_dccm) +DEF(0x19, ARC_OPCODE_ARCV1, NONE, unlockline) +DEF(0x19, ARC_OPCODE_ARCALL, NONE, ic_ivil) +DEF(0x1a, ARC_OPCODE_ARCALL, NONE, ic_ram_address) +DEF(0x1b, ARC_OPCODE_ARCALL, NONE, ic_tag) +DEF(0x1c, ARC_OPCODE_ARCALL, NONE, ic_wp) +DEF(0x1d, ARC_OPCODE_ARCALL, NONE, ic_data) +DEF(0x1e, ARC_OPCODE_ARCALL, NONE, ic_ptag) +DEF(0x1f, ARC_OPCODE_ARCv2EM, NONE, debugi) +DEF(0x1f, ARC_OPCODE_ARCv2HS, NONE, ic_ptag_hi) +DEF(0x20, ARC_OPCODE_ARC600, NONE, sram_seq) +DEF(0x21, ARC_OPCODE_ARCALL, NONE, count0) +DEF(0x22, ARC_OPCODE_ARCALL, NONE, control0) +DEF(0x23, ARC_OPCODE_ARCALL, NONE, limit0) +DEF(0x24, ARC_OPCODE_ARCV1, NONE, pcport) +DEF(0x25, ARC_OPCODE_ARC700, NONE, int_vector_base) +DEF(0x25, ARC_OPCODE_ARCV2, NONE, int_vector_base) +DEF(0x26, ARC_OPCODE_ARC600, NONE, aux_vbfdw_mode) +DEF(0x27, ARC_OPCODE_ARC600, NONE, aux_vbfdw_bm0) +DEF(0x28, ARC_OPCODE_ARC600, NONE, aux_vbfdw_bm1) +DEF(0x29, ARC_OPCODE_ARC600, NONE, aux_vbfdw_accu) +DEF(0x2a, ARC_OPCODE_ARC600, NONE, aux_vbfdw_ofst) +DEF(0x2b, ARC_OPCODE_ARC600, NONE, aux_vbfdw_intstat) +DEF(0x2c, ARC_OPCODE_ARC600, NONE, aux_xmac0_24) +DEF(0x2d, ARC_OPCODE_ARC600, NONE, aux_xmac1_24) +DEF(0x2e, ARC_OPCODE_ARC600, NONE, aux_xmac2_24) +DEF(0x2f, ARC_OPCODE_ARC600, NONE, aux_fbf_store_16) +DEF(0x30, ARC_OPCODE_ARCv2EM, NONE, acg_ctrl) +DEF(0x30, ARC_OPCODE_NONE, NONE, ax0) +DEF(0x31, ARC_OPCODE_NONE, NONE, ax1) +DEF(0x32, ARC_OPCODE_NONE, NONE, aux_crc_poly) +DEF(0x33, ARC_OPCODE_NONE, NONE, aux_crc_mode) +DEF(0x34, ARC_OPCODE_NONE, NONE, mx0) +DEF(0x35, ARC_OPCODE_NONE, NONE, mx1) +DEF(0x36, ARC_OPCODE_NONE, NONE, my0) +DEF(0x37, ARC_OPCODE_NONE, NONE, my1) +DEF(0x38, ARC_OPCODE_NONE, NONE, xyconfig) +DEF(0x38, ARC_OPCODE_ARCv2EM, NONE, aux_kernel_sp) +DEF(0x39, ARC_OPCODE_NONE, NONE, scratch_a) +DEF(0x39, ARC_OPCODE_ARCv2EM, NONE, aux_sec_u_sp) +/* TODO: The commented lines are repeated for specific configurations. */ +/* +DEF (0x3a, ARC_OPCODE_NONE, NONE, burstsys) +DEF (0x3a, ARC_OPCODE_NONE, NONE, tsch) +*/ +DEF(0x3a, ARC_OPCODE_ARCv2EM, NONE, aux_sec_k_sp) +DEF(0x3b, ARC_OPCODE_NONE, NONE, burstxym) +DEF(0x3c, ARC_OPCODE_NONE, NONE, burstsz) +DEF(0x3d, ARC_OPCODE_NONE, NONE, burstval) +DEF(0x3e, ARC_OPCODE_ARCv2EM, NONE, aux_sec_ctrl) +DEF(0x3f, ARC_OPCODE_ARCv2EM, NONE, erp_control) +DEF(0x40, ARC_OPCODE_ARCv2EM, NONE, rferp_status0) +DEF(0x41, ARC_OPCODE_ARCv2EM, NONE, rferp_status1) +DEF(0x40, ARC_OPCODE_ARC600, NONE, xtp_newval) +DEF(0x41, ARC_OPCODE_ARCV1, NONE, aux_macmode) +DEF(0x42, ARC_OPCODE_ARC600, NONE, lsp_newval) +DEF(0x43, ARC_OPCODE_ARCV1, NONE, aux_irq_lv12) +DEF(0x43, ARC_OPCODE_ARCV2, NONE, aux_irq_act) +DEF(0x44, ARC_OPCODE_ARCV1, NONE, aux_xmac0) +DEF(0x45, ARC_OPCODE_ARCV1, NONE, aux_xmac1) +DEF(0x46, ARC_OPCODE_ARCV1, NONE, aux_xmac2) +DEF(0x47, ARC_OPCODE_ARCALL, NONE, dc_ivdc) +DEF(0x48, ARC_OPCODE_ARCALL, NONE, dc_ctrl) +DEF(0x49, ARC_OPCODE_ARCALL, NONE, dc_ldl) +DEF(0x4a, ARC_OPCODE_ARCALL, NONE, dc_ivdl) +DEF(0x4b, ARC_OPCODE_ARCALL, NONE, dc_flsh) +DEF(0x4c, ARC_OPCODE_ARCALL, NONE, dc_fldl) +DEF(0x4d, ARC_OPCODE_ARCV2, NONE, dc_startr) +DEF(0x4e, ARC_OPCODE_ARCV2, NONE, dc_endr) +DEF(0x50, ARC_OPCODE_NONE, NONE, hexdata) +DEF(0x51, ARC_OPCODE_NONE, NONE, hexctrl) +DEF(0x52, ARC_OPCODE_NONE, NONE, led) +DEF(0x56, ARC_OPCODE_NONE, NONE, dilstat) +DEF(0x57, ARC_OPCODE_ARC600, NONE, swstat) +DEF(0x58, ARC_OPCODE_ARCALL, NONE, dc_ram_addr) +DEF(0x59, ARC_OPCODE_ARCALL, NONE, dc_tag) +DEF(0x5a, ARC_OPCODE_ARCALL, NONE, dc_wp) +DEF(0x5b, ARC_OPCODE_ARCALL, NONE, dc_data) +DEF(0x5c, ARC_OPCODE_ARCALL, NONE, dc_ptag) +DEF(0x5e, ARC_OPCODE_ARCv2HS, NONE, aux_volatile) +DEF(0x5f, ARC_OPCODE_ARCv2HS, NONE, dc_ptag_hi) +DEF(0x80, ARC_OPCODE_ARCALL, NONE, ax0) +DEF(0x81, ARC_OPCODE_ARCALL, NONE, ax1) +DEF(0x82, ARC_OPCODE_ARCALL, NONE, ax2) +DEF(0x83, ARC_OPCODE_ARCALL, NONE, ax3) +DEF(0x84, ARC_OPCODE_ARCALL, NONE, ay0) +DEF(0x85, ARC_OPCODE_ARCALL, NONE, ay1) +DEF(0x86, ARC_OPCODE_ARCALL, NONE, ay2) +DEF(0x87, ARC_OPCODE_ARCALL, NONE, ay3) +DEF(0x88, ARC_OPCODE_ARCALL, NONE, mx00) +DEF(0x89, ARC_OPCODE_ARCALL, NONE, mx01) +DEF(0x8a, ARC_OPCODE_ARCALL, NONE, mx10) +DEF(0x8b, ARC_OPCODE_ARCALL, NONE, mx11) +DEF(0x8c, ARC_OPCODE_ARCALL, NONE, mx20) +DEF(0x8d, ARC_OPCODE_ARCALL, NONE, mx21) +DEF(0x8e, ARC_OPCODE_ARCALL, NONE, mx30) +DEF(0x8f, ARC_OPCODE_ARCALL, NONE, mx31) +DEF(0x90, ARC_OPCODE_ARCALL, NONE, my00) +DEF(0x91, ARC_OPCODE_ARCALL, NONE, my01) +DEF(0x92, ARC_OPCODE_ARCALL, NONE, my10) +DEF(0x93, ARC_OPCODE_ARCALL, NONE, my11) +DEF(0x94, ARC_OPCODE_ARCALL, NONE, my20) +DEF(0x95, ARC_OPCODE_ARCALL, NONE, my21) +DEF(0x96, ARC_OPCODE_ARCALL, NONE, my30) +DEF(0x97, ARC_OPCODE_ARCALL, NONE, my31) +DEF(0x98, ARC_OPCODE_ARCALL, NONE, xyconfig) +DEF(0x99, ARC_OPCODE_ARCALL, NONE, burstsys) +DEF(0x9a, ARC_OPCODE_ARCALL, NONE, burstxym) +DEF(0x9b, ARC_OPCODE_ARCALL, NONE, burstsz) +DEF(0x9c, ARC_OPCODE_ARCALL, NONE, burstval) +DEF(0x9d, ARC_OPCODE_ARCALL, NONE, xylsbasex) +DEF(0x9e, ARC_OPCODE_ARCALL, NONE, xylsbasey) +DEF(0x9f, ARC_OPCODE_ARCALL, NONE, aux_xmaclw_h) +DEF(0xa0, ARC_OPCODE_ARCALL, NONE, aux_xmaclw_l) +DEF(0xa1, ARC_OPCODE_ARCALL, NONE, se_ctrl) +DEF(0xa2, ARC_OPCODE_ARCALL, NONE, se_stat) +DEF(0xa3, ARC_OPCODE_ARCALL, NONE, se_err) +DEF(0xa4, ARC_OPCODE_ARCALL, NONE, se_eadr) +DEF(0xa5, ARC_OPCODE_ARCALL, NONE, se_spc) +DEF(0xa6, ARC_OPCODE_ARCALL, NONE, sdm_base) +DEF(0xa7, ARC_OPCODE_ARCALL, NONE, scm_base) +DEF(0xa8, ARC_OPCODE_ARCALL, NONE, se_dbg_ctrl) +DEF(0xa9, ARC_OPCODE_ARCALL, NONE, se_dbg_data0) +DEF(0xaa, ARC_OPCODE_ARCALL, NONE, se_dbg_data1) +DEF(0xab, ARC_OPCODE_ARCALL, NONE, se_dbg_data2) +DEF(0xac, ARC_OPCODE_ARCALL, NONE, se_dbg_data3) +DEF(0xad, ARC_OPCODE_ARCALL, NONE, se_watch) +DEF(0x100, ARC_OPCODE_ARCALL, NONE, count1) +DEF(0x101, ARC_OPCODE_ARCALL, NONE, control1) +DEF(0x102, ARC_OPCODE_ARCALL, NONE, limit1) +DEF(0x103, ARC_OPCODE_ARCV2, NONE, aux_rtc_ctrl) +DEF(0x104, ARC_OPCODE_ARCV2, NONE, aux_rtc_low) +DEF(0x105, ARC_OPCODE_ARCV2, NONE, aux_rtc_high) +DEF(0x200, ARC_OPCODE_ARCV1, NONE, aux_irq_lev) +DEF(0x200, ARC_OPCODE_ARCV2, NONE, irq_priority_pending) +DEF(0x201, ARC_OPCODE_ARCALL, NONE, aux_irq_hint) +DEF(0x202, ARC_OPCODE_ARC600, NONE, aux_inter_core_interrupt) +DEF(0x206, ARC_OPCODE_ARCV2, NONE, irq_priority) +DEF(0x210, ARC_OPCODE_ARC700, NONE, aes_aux_0) +DEF(0x211, ARC_OPCODE_ARC700, NONE, aes_aux_1) +DEF(0x212, ARC_OPCODE_ARC700, NONE, aes_aux_2) +DEF(0x213, ARC_OPCODE_ARC700, NONE, aes_crypt_mode) +DEF(0x214, ARC_OPCODE_ARC700, NONE, aes_auxs) +DEF(0x215, ARC_OPCODE_ARC700, NONE, aes_auxi) +DEF(0x216, ARC_OPCODE_ARC700, NONE, aes_aux_3) +DEF(0x217, ARC_OPCODE_ARC700, NONE, aes_aux_4) +DEF(0x218, ARC_OPCODE_ARC700, NONE, arith_ctl_aux) +DEF(0x219, ARC_OPCODE_ARC700, NONE, des_aux) +DEF(0x220, ARC_OPCODE_ARCALL, NONE, ap_amv0) +DEF(0x221, ARC_OPCODE_ARCALL, NONE, ap_amm0) +DEF(0x222, ARC_OPCODE_ARCALL, NONE, ap_ac0) +DEF(0x223, ARC_OPCODE_ARCALL, NONE, ap_amv1) +DEF(0x224, ARC_OPCODE_ARCALL, NONE, ap_amm1) +DEF(0x225, ARC_OPCODE_ARCALL, NONE, ap_ac1) +DEF(0x226, ARC_OPCODE_ARCALL, NONE, ap_amv2) +DEF(0x227, ARC_OPCODE_ARCALL, NONE, ap_amm2) +DEF(0x228, ARC_OPCODE_ARCALL, NONE, ap_ac2) +DEF(0x229, ARC_OPCODE_ARCALL, NONE, ap_amv3) +DEF(0x22a, ARC_OPCODE_ARCALL, NONE, ap_amm3) +DEF(0x22b, ARC_OPCODE_ARCALL, NONE, ap_ac3) +DEF(0x22c, ARC_OPCODE_ARCALL, NONE, ap_amv4) +DEF(0x22d, ARC_OPCODE_ARCALL, NONE, ap_amm4) +DEF(0x22e, ARC_OPCODE_ARCALL, NONE, ap_ac4) +DEF(0x22f, ARC_OPCODE_ARCALL, NONE, ap_amv5) +DEF(0x230, ARC_OPCODE_ARCALL, NONE, ap_amm5) +DEF(0x231, ARC_OPCODE_ARCALL, NONE, ap_ac5) +DEF(0x232, ARC_OPCODE_ARCALL, NONE, ap_amv6) +DEF(0x233, ARC_OPCODE_ARCALL, NONE, ap_amm6) +DEF(0x234, ARC_OPCODE_ARCALL, NONE, ap_ac6) +DEF(0x235, ARC_OPCODE_ARCALL, NONE, ap_amv7) +DEF(0x236, ARC_OPCODE_ARCALL, NONE, ap_amm7) +DEF(0x237, ARC_OPCODE_ARCALL, NONE, ap_ac7) +DEF(0x268, ARC_OPCODE_ARCv2EM, NONE, nsc_table_top) +DEF(0x269, ARC_OPCODE_ARCv2EM, NONE, nsc_table_base) +DEF(0x290, ARC_OPCODE_ARCV2, NONE, jli_base) +DEF(0x291, ARC_OPCODE_ARCV2, NONE, ldi_base) +DEF(0x292, ARC_OPCODE_ARCV2, NONE, ei_base) +DEF(0x300, ARC_OPCODE_ARCFPX, DPX, fp_status) +/* +DEF (0x301, ARC_OPCODE_ARCFPX, DPX, aux_dpfp1l) +DEF (0x301, ARC_OPCODE_ARCFPX, DPX, d1l) +*/ +/* +DEF (0x302, ARC_OPCODE_ARCFPX, DPX, aux_dpfp1h) +DEF (0x302, ARC_OPCODE_ARCFPX, DPX, d1h) +*/ +DEF(0x302, ARC_OPCODE_ARCv2EM, DPA, d1l) +/* +DEF (0x303, ARC_OPCODE_ARCFPX, DPX, aux_dpfp2l) +DEF (0x303, ARC_OPCODE_ARCFPX, DPX, d2l) +*/ +DEF(0x303, ARC_OPCODE_ARCv2EM, DPA, d1h) +/* +DEF (0x304, ARC_OPCODE_ARCFPX, DPX, aux_dpfp2h) +DEF (0x304, ARC_OPCODE_ARCFPX, DPX, d2h) +*/ +DEF(0x304, ARC_OPCODE_ARCv2EM, DPA, d2l) +DEF(0x305, ARC_OPCODE_ARCFPX, DPX, dpfp_status) +DEF(0x305, ARC_OPCODE_ARCv2EM, DPA, d2h) +DEF(0x400, ARC_OPCODE_ARCALL, NONE, eret) +DEF(0x401, ARC_OPCODE_ARCALL, NONE, erbta) +DEF(0x402, ARC_OPCODE_ARCALL, NONE, erstatus) +DEF(0x403, ARC_OPCODE_ARCALL, NONE, ecr) +DEF(0x404, ARC_OPCODE_ARCALL, NONE, efa) +DEF(0x405, ARC_OPCODE_ARC700, NONE, tlbpd0) +DEF(0x406, ARC_OPCODE_ARC700, NONE, tlbpd1) +DEF(0x406, ARC_OPCODE_ARCv2EM, NONE, ersec_stat) +DEF(0x407, ARC_OPCODE_ARCv2EM, NONE, aux_sec_except) +DEF(0x407, ARC_OPCODE_ARC700, NONE, tlbindex) +DEF(0x408, ARC_OPCODE_ARC700, NONE, tlbcommand) +DEF(0x409, ARC_OPCODE_ARC700, NONE, pid) +DEF(0x409, ARC_OPCODE_ARCALL, NONE, mpuen) +DEF(0x40a, ARC_OPCODE_ARCV2, NONE, icause) +DEF(0x40b, ARC_OPCODE_ARCV2, NONE, irq_select) +DEF(0x40c, ARC_OPCODE_ARCV2, NONE, irq_enable) +DEF(0x40d, ARC_OPCODE_ARCV2, NONE, irq_trigger) +DEF(0x40f, ARC_OPCODE_ARCV2, NONE, irq_status) +DEF(0x410, ARC_OPCODE_ARCALL, NONE, xpu) +DEF(0x412, ARC_OPCODE_ARCALL, NONE, bta) +DEF(0x413, ARC_OPCODE_ARC700, NONE, bta_l1) +DEF(0x414, ARC_OPCODE_ARC700, NONE, bta_l2) +DEF(0x415, ARC_OPCODE_ARCV2, NONE, irq_pulse_cancel) +DEF(0x416, ARC_OPCODE_ARCV2, NONE, irq_pending) +DEF(0x418, ARC_OPCODE_ARC700, NONE, scratch_data0) +DEF(0x420, ARC_OPCODE_ARCALL, NONE, mpuic) +DEF(0x421, ARC_OPCODE_ARCALL, NONE, mpufa) +DEF(0x422, ARC_OPCODE_ARCALL, NONE, mpurdb0) +DEF(0x423, ARC_OPCODE_ARCALL, NONE, mpurdp0) +DEF(0x424, ARC_OPCODE_ARCALL, NONE, mpurdb1) +DEF(0x425, ARC_OPCODE_ARCALL, NONE, mpurdp1) +DEF(0x426, ARC_OPCODE_ARCALL, NONE, mpurdb2) +DEF(0x427, ARC_OPCODE_ARCALL, NONE, mpurdp2) +DEF(0x428, ARC_OPCODE_ARCALL, NONE, mpurdb3) +DEF(0x429, ARC_OPCODE_ARCALL, NONE, mpurdp3) +DEF(0x42a, ARC_OPCODE_ARCALL, NONE, mpurdb4) +DEF(0x42b, ARC_OPCODE_ARCALL, NONE, mpurdp4) +DEF(0x42c, ARC_OPCODE_ARCALL, NONE, mpurdb5) +DEF(0x42d, ARC_OPCODE_ARCALL, NONE, mpurdp5) +DEF(0x42e, ARC_OPCODE_ARCALL, NONE, mpurdb6) +DEF(0x42f, ARC_OPCODE_ARCALL, NONE, mpurdp6) +DEF(0x430, ARC_OPCODE_ARCALL, NONE, mpurdb7) +DEF(0x431, ARC_OPCODE_ARCALL, NONE, mpurdp7) +DEF(0x432, ARC_OPCODE_ARCALL, NONE, mpurdb8) +DEF(0x433, ARC_OPCODE_ARCALL, NONE, mpurdp8) +DEF(0x434, ARC_OPCODE_ARCALL, NONE, mpurdb9) +DEF(0x435, ARC_OPCODE_ARCALL, NONE, mpurdp9) +DEF(0x436, ARC_OPCODE_ARCALL, NONE, mpurdb10) +DEF(0x437, ARC_OPCODE_ARCALL, NONE, mpurdp10) +DEF(0x438, ARC_OPCODE_ARCALL, NONE, mpurdb11) +DEF(0x439, ARC_OPCODE_ARCALL, NONE, mpurdp11) +DEF(0x43a, ARC_OPCODE_ARCALL, NONE, mpurdb12) +DEF(0x43b, ARC_OPCODE_ARCALL, NONE, mpurdp12) +DEF(0x43c, ARC_OPCODE_ARCALL, NONE, mpurdb13) +DEF(0x43d, ARC_OPCODE_ARCALL, NONE, mpurdp13) +DEF(0x43e, ARC_OPCODE_ARCALL, NONE, mpurdb14) +DEF(0x43f, ARC_OPCODE_ARCALL, NONE, mpurdp14) +DEF(0x440, ARC_OPCODE_ARCALL, NONE, mpurdb15) +DEF(0x441, ARC_OPCODE_ARCALL, NONE, mpurdp15) +DEF(0x450, ARC_OPCODE_ARC600, NONE, pm_status) +DEF(0x451, ARC_OPCODE_ARC600, NONE, wake) +DEF(0x452, ARC_OPCODE_ARC600, NONE, dvfs_performance) +DEF(0x453, ARC_OPCODE_ARC600, NONE, pwr_ctrl) +DEF(0x460, ARC_OPCODE_ARCv2HS, NONE, tlbpd0) +DEF(0x461, ARC_OPCODE_ARCv2HS, NONE, tlbpd1) +DEF(0x463, ARC_OPCODE_ARCv2HS, NONE, tlbpd1_hi) +DEF(0x464, ARC_OPCODE_ARCv2HS, NONE, tlbindex) +DEF(0x465, ARC_OPCODE_ARCv2HS, NONE, tlbcommand) +DEF(0x468, ARC_OPCODE_ARCv2HS, NONE, pid) +DEF(0x46a, ARC_OPCODE_ARCv2HS, NONE, sasid0) +DEF(0x46b, ARC_OPCODE_ARCv2HS, NONE, sasid1) +DEF(0x46c, ARC_OPCODE_ARCv2HS, NONE, scratch_data0) +DEF(0x500, ARC_OPCODE_ARC700, NONE, aux_vlc_buf_idx) +DEF(0x501, ARC_OPCODE_ARC700, NONE, aux_vlc_read_buf) +DEF(0x502, ARC_OPCODE_ARC700, NONE, aux_vlc_valid_bits) +DEF(0x503, ARC_OPCODE_ARC700, NONE, aux_vlc_buf_in) +DEF(0x504, ARC_OPCODE_ARC700, NONE, aux_vlc_buf_free) +DEF(0x505, ARC_OPCODE_ARC700, NONE, aux_vlc_ibuf_status) +DEF(0x506, ARC_OPCODE_ARC700, NONE, aux_vlc_setup) +DEF(0x507, ARC_OPCODE_ARC700, NONE, aux_vlc_bits) +DEF(0x508, ARC_OPCODE_ARC700, NONE, aux_vlc_table) +DEF(0x509, ARC_OPCODE_ARC700, NONE, aux_vlc_get_symbol) +DEF(0x50a, ARC_OPCODE_ARC700, NONE, aux_vlc_read_symbol) +DEF(0x510, ARC_OPCODE_ARC700, NONE, aux_ucavlc_setup) +DEF(0x511, ARC_OPCODE_ARC700, NONE, aux_ucavlc_state) +DEF(0x512, ARC_OPCODE_ARC700, NONE, aux_cavlc_zero_left) +DEF(0x514, ARC_OPCODE_ARC700, NONE, aux_uvlc_i_state) +DEF(0x51c, ARC_OPCODE_ARC700, NONE, aux_vlc_dma_ptr) +DEF(0x51d, ARC_OPCODE_ARC700, NONE, aux_vlc_dma_end) +DEF(0x51e, ARC_OPCODE_ARC700, NONE, aux_vlc_dma_esc) +DEF(0x51f, ARC_OPCODE_ARC700, NONE, aux_vlc_dma_ctrl) +DEF(0x520, ARC_OPCODE_ARC700, NONE, aux_vlc_get_0bit) +DEF(0x521, ARC_OPCODE_ARC700, NONE, aux_vlc_get_1bit) +DEF(0x522, ARC_OPCODE_ARC700, NONE, aux_vlc_get_2bit) +DEF(0x523, ARC_OPCODE_ARC700, NONE, aux_vlc_get_3bit) +DEF(0x524, ARC_OPCODE_ARC700, NONE, aux_vlc_get_4bit) +DEF(0x525, ARC_OPCODE_ARC700, NONE, aux_vlc_get_5bit) +DEF(0x526, ARC_OPCODE_ARC700, NONE, aux_vlc_get_6bit) +DEF(0x527, ARC_OPCODE_ARC700, NONE, aux_vlc_get_7bit) +DEF(0x528, ARC_OPCODE_ARC700, NONE, aux_vlc_get_8bit) +DEF(0x529, ARC_OPCODE_ARC700, NONE, aux_vlc_get_9bit) +DEF(0x52a, ARC_OPCODE_ARC700, NONE, aux_vlc_get_10bit) +DEF(0x52b, ARC_OPCODE_ARC700, NONE, aux_vlc_get_11bit) +DEF(0x52c, ARC_OPCODE_ARC700, NONE, aux_vlc_get_12bit) +DEF(0x52d, ARC_OPCODE_ARC700, NONE, aux_vlc_get_13bit) +DEF(0x52e, ARC_OPCODE_ARC700, NONE, aux_vlc_get_14bit) +DEF(0x52f, ARC_OPCODE_ARC700, NONE, aux_vlc_get_15bit) +DEF(0x530, ARC_OPCODE_ARC700, NONE, aux_vlc_get_16bit) +DEF(0x531, ARC_OPCODE_ARC700, NONE, aux_vlc_get_17bit) +DEF(0x532, ARC_OPCODE_ARC700, NONE, aux_vlc_get_18bit) +DEF(0x533, ARC_OPCODE_ARC700, NONE, aux_vlc_get_19bit) +DEF(0x534, ARC_OPCODE_ARC700, NONE, aux_vlc_get_20bit) +DEF(0x535, ARC_OPCODE_ARC700, NONE, aux_vlc_get_21bit) +DEF(0x536, ARC_OPCODE_ARC700, NONE, aux_vlc_get_22bit) +DEF(0x537, ARC_OPCODE_ARC700, NONE, aux_vlc_get_23bit) +DEF(0x538, ARC_OPCODE_ARC700, NONE, aux_vlc_get_24bit) +DEF(0x539, ARC_OPCODE_ARC700, NONE, aux_vlc_get_25bit) +DEF(0x53a, ARC_OPCODE_ARC700, NONE, aux_vlc_get_26bit) +DEF(0x53b, ARC_OPCODE_ARC700, NONE, aux_vlc_get_27bit) +DEF(0x53c, ARC_OPCODE_ARC700, NONE, aux_vlc_get_28bit) +DEF(0x53d, ARC_OPCODE_ARC700, NONE, aux_vlc_get_29bit) +DEF(0x53e, ARC_OPCODE_ARC700, NONE, aux_vlc_get_30bit) +DEF(0x53f, ARC_OPCODE_ARC700, NONE, aux_vlc_get_31bit) +DEF(0x540, ARC_OPCODE_ARC700, NONE, aux_cabac_ctrl) +DEF(0x541, ARC_OPCODE_ARC700, NONE, aux_cabac_ctx_state) +DEF(0x542, ARC_OPCODE_ARC700, NONE, aux_cabac_cod_param) +DEF(0x543, ARC_OPCODE_ARC700, NONE, aux_cabac_misc0) +DEF(0x544, ARC_OPCODE_ARC700, NONE, aux_cabac_misc1) +DEF(0x545, ARC_OPCODE_ARC700, NONE, aux_cabac_misc2) +DEF(0x700, ARC_OPCODE_ARCALL, NONE, smart_control) +/* +DEF (0x701, ARC_OPCODE_ARC700, NONE, smart_data_0) +DEF (0x701, ARC_OPCODE_ARC600, NONE, smart_data) +DEF (0x701, ARC_OPCODE_ARC700, NONE, smart_data_2) +DEF (0x701, ARC_OPCODE_ARC700, NONE, smart_data_3) +*/ + + +/* BCR aux registers */ +DEF(0x60, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x61, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x62, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x63, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x64, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x65, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x66, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x67, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x68, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x69, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x6a, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x6b, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x6c, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x6d, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x6e, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x6f, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x70, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x71, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x72, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x73, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x74, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x75, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x76, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x77, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x78, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x79, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x7a, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x7c, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x7d, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x7e, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0x7f, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xc0, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xc1, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xc2, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xc3, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xc4, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xc5, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xc6, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xc7, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xc8, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xc9, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xca, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xcb, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xcc, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xcd, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xce, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xcf, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xd0, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xd1, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xd2, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xd3, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xd4, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xd5, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xd6, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xd7, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xd8, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xd9, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xda, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xdb, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xdc, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xdd, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xde, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xdf, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xe0, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xe1, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xe2, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xe3, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xe4, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xe5, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xe6, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xe7, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xe8, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xe9, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xea, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xeb, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xec, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xed, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xee, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xef, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xf0, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xf1, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xf2, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xf3, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xf4, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xf5, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xf6, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xf7, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xf8, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xf9, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xfa, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xfb, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xfc, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xfd, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xfe, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) +DEF(0xff, ARC_OPCODE_DEFAULT, NONE, unimp_bcr) + +/* Actual BCR implementations */ + +DEF(0x6d, ARC_OPCODE_ARCv2HS, NONE, mpu_build) +DEF(0x6f, ARC_OPCODE_ARCv2HS, NONE, mmu_build) +DEF(0x75, ARC_OPCODE_ARCALL, NONE, timer_build) +DEF(0xf3, ARC_OPCODE_ARCV2, NONE, irq_build) +DEF(0x72, ARC_OPCODE_ARCV2, NONE, d_cache_build) +DEF(0x77, ARC_OPCODE_ARCV2, NONE, i_cache_build) +DEF(0x7b, ARC_OPCODE_ARCV2, NONE, mpy_build) + +/* OLD BCR definitions */ +/* +DEF (0x61, ARC_OPCODE_ARCALL, NONE, dccm_base_build) +DEF (0x63, ARC_OPCODE_ARCALL, NONE, bta_link_build) +DEF (0x64, ARC_OPCODE_ARCALL, NONE, vbfdw_build) +DEF (0x65, ARC_OPCODE_ARCALL, NONE, ea_build) +DEF (0x66, ARC_OPCODE_ARCALL, NONE, dataspace) +DEF (0x67, ARC_OPCODE_ARCALL, NONE, memsubsys) +DEF (0x68, ARC_OPCODE_ARCALL, NONE, vecbase_ac_build) +DEF (0x69, ARC_OPCODE_ARCALL, NONE, p_base_addr) +DEF (0x6a, ARC_OPCODE_ARCALL, NONE, data_uncached_build) +DEF (0x6b, ARC_OPCODE_ARCALL, NONE, fp_build) +DEF (0x6c, ARC_OPCODE_ARCALL, NONE, dpfp_build) +DEF (0x6d, ARC_OPCODE_ARCALL, NONE, mpu_build) +DEF (0x6e, ARC_OPCODE_ARCALL, NONE, rf_build) +DEF (0x6f, ARC_OPCODE_ARCALL, NONE, mmu_build) +DEF (0x70, ARC_OPCODE_ARCv2EM, NONE, sec_vecbase_build) +DEF (0x71, ARC_OPCODE_ARCALL, NONE, vecbase_build) +DEF (0x73, ARC_OPCODE_ARCALL, NONE, madi_build) + +DEF (0xc1, ARC_OPCODE_ARC600, NONE, arc600_build_config) +DEF (0xc2, ARC_OPCODE_ARCALL, NONE, isa_config) +DEF (0xf4, ARC_OPCODE_ARCALL, NONE, hwp_build) +DEF (0xf5, ARC_OPCODE_ARCALL, NONE, pct_build) +DEF (0xf6, ARC_OPCODE_ARCALL, NONE, cc_build) +DEF (0xf7, ARC_OPCODE_ARCALL, NONE, pm_bcr) +DEF (0xf8, ARC_OPCODE_ARCALL, NONE, scq_switch_build) +DEF (0xf9, ARC_OPCODE_ARCALL, NONE, vraptor_build) +DEF (0xfa, ARC_OPCODE_ARCALL, NONE, dma_config) +DEF (0xfb, ARC_OPCODE_ARCALL, NONE, simd_config) +DEF (0xfc, ARC_OPCODE_ARCALL, NONE, vlc_build) +DEF (0xfd, ARC_OPCODE_ARCALL, NONE, simd_dma_build) +DEF (0xfe, ARC_OPCODE_ARCALL, NONE, ifetch_queue_build) +*/ diff --git a/target/arc/regs.c b/target/arc/regs.c new file mode 100644 index 0000000000..3db4d01b07 --- /dev/null +++ b/target/arc/regs.c @@ -0,0 +1,139 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synppsys Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "target/arc/regs.h" +#include "target/arc/mmu.h" +#include "target/arc/mpu.h" +#include "target/arc/irq.h" +#include "target/arc/timer.h" +#include "target/arc/cache.h" + +struct arc_aux_reg_detail arc_aux_regs_detail[ARC_AUX_REGS_DETAIL_LAST] = { +#define DEF(NUM, CPU, SUB, NAME) \ + { \ + NUM, \ + CPU, \ + SUB, \ + AUX_ID_##NAME, \ + #NAME, \ + sizeof(#NAME) - 1, \ + NULL, \ + NULL, \ + }, +#include "target/arc/regs-detail.def" +#undef DEF +}; + +struct arc_aux_reg arc_aux_regs[ARC_AUX_REGS_LAST] = { +#define AUX_REG(NAME, GET_FUNC, SET_FUNC) \ + { \ + NULL, \ + GET_FUNC, \ + SET_FUNC \ + }, +#include "target/arc/regs.def" +#undef AUX_REG +}; + +const char *arc_aux_reg_name[ARC_AUX_REGS_DETAIL_LAST] = { +#define AUX_REG(NAME, GET, SET) #NAME, +#include "target/arc/regs.def" +#undef AUX_REG + "last_invalid_aux_reg" +}; + + +void arc_aux_regs_init(void) +{ + int i; + + for (i = 0; i < ARC_AUX_REGS_DETAIL_LAST; i++) { + enum arc_aux_reg_enum id = arc_aux_regs_detail[i].id; + struct arc_aux_reg_detail *next = arc_aux_regs[id].first; + arc_aux_regs_detail[i].next = next; + arc_aux_regs_detail[i].aux_reg = &(arc_aux_regs[id]); + arc_aux_regs[id].first = &(arc_aux_regs_detail[i]); + } +} + +int +arc_aux_reg_address_for(enum arc_aux_reg_enum aux_reg_def, + int isa_mask) +{ + /* TODO: This must validate for CPU. */ + struct arc_aux_reg_detail *detail = arc_aux_regs[aux_reg_def].first; + while (detail != NULL) { + if ((detail->cpu & isa_mask) != 0) { + return detail->address; + } + detail = detail->next; + } + assert(0); + + /* We never get here but to accommodate -Werror ... */ + return 0; +} + +struct arc_aux_reg_detail * +arc_aux_reg_struct_for_address(int address, int isa_mask) +{ + int i; + bool has_default = false; + struct arc_aux_reg_detail *default_ret = NULL; + + /* TODO: Make this a binary search or something faster. */ + for (i = 0; i < ARC_AUX_REGS_DETAIL_LAST; i++) { + if (arc_aux_regs_detail[i].address == address) { + if (arc_aux_regs_detail[i].cpu == ARC_OPCODE_DEFAULT) { + has_default = true; + default_ret = &(arc_aux_regs_detail[i]); + } else if ((arc_aux_regs_detail[i].cpu & isa_mask) != 0) { + return &(arc_aux_regs_detail[i]); + } + } + } + + if (has_default == true) { + return default_ret; + } + + return NULL; +} + +uint32_t +arc_regs_bcr_default_impl(const struct arc_aux_reg_detail *aux_reg, + void *data) +{ + return 0; +} + +/* TODO: Implement any non implemented auxs regs. */ +void TO_IMPLEMENT_SET(const struct arc_aux_reg_detail *aux_reg, uint32_t val, + void *data) +{ + return; +} +uint32_t TO_IMPLEMENT_GET(const struct arc_aux_reg_detail *aux_reg, void *data) +{ + return 0; +} diff --git a/target/arc/regs.def b/target/arc/regs.def new file mode 100644 index 0000000000..d9cb865916 --- /dev/null +++ b/target/arc/regs.def @@ -0,0 +1,396 @@ +/* + * QEMU ARC Auxiliary register definitions + * + * Copyright (c) 2020 Synppsys Inc. + * Contributed by Claudiu Zissulescu (claziss@synopsys.com) + * Contributed by Cupertino Miranda (cmiranda@synopsys.com) + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +AUX_REG (unimp_bcr, arc_regs_bcr_default_impl, NULL) +AUX_REG (acg_ctrl, NULL, NULL) +AUX_REG (acr, NULL, NULL) +AUX_REG (adcr, NULL, NULL) +AUX_REG (aes_aux_0, NULL, NULL) +AUX_REG (aes_aux_1, NULL, NULL) +AUX_REG (aes_aux_2, NULL, NULL) +AUX_REG (aes_aux_3, NULL, NULL) +AUX_REG (aes_aux_4, NULL, NULL) +AUX_REG (aes_auxi, NULL, NULL) +AUX_REG (aes_auxs, NULL, NULL) +AUX_REG (aes_crypt_mode, NULL, NULL) +AUX_REG (ap_ac0, NULL, NULL) +AUX_REG (ap_ac1, NULL, NULL) +AUX_REG (ap_ac2, NULL, NULL) +AUX_REG (ap_ac3, NULL, NULL) +AUX_REG (ap_ac4, NULL, NULL) +AUX_REG (ap_ac5, NULL, NULL) +AUX_REG (ap_ac6, NULL, NULL) +AUX_REG (ap_ac7, NULL, NULL) +AUX_REG (ap_amm0, NULL, NULL) +AUX_REG (ap_amm1, NULL, NULL) +AUX_REG (ap_amm2, NULL, NULL) +AUX_REG (ap_amm3, NULL, NULL) +AUX_REG (ap_amm4, NULL, NULL) +AUX_REG (ap_amm5, NULL, NULL) +AUX_REG (ap_amm6, NULL, NULL) +AUX_REG (ap_amm7, NULL, NULL) +AUX_REG (ap_amv0, NULL, NULL) +AUX_REG (ap_amv1, NULL, NULL) +AUX_REG (ap_amv2, NULL, NULL) +AUX_REG (ap_amv3, NULL, NULL) +AUX_REG (ap_amv4, NULL, NULL) +AUX_REG (ap_amv5, NULL, NULL) +AUX_REG (ap_amv6, NULL, NULL) +AUX_REG (ap_amv7, NULL, NULL) +AUX_REG (apcr, NULL, NULL) +AUX_REG (arc600_build_config, NULL, NULL) +AUX_REG (arith_ctl_aux, NULL, NULL) +AUX_REG (aux_cabac_cod_param, NULL, NULL) +AUX_REG (aux_cabac_ctrl, NULL, NULL) +AUX_REG (aux_cabac_ctx_state, NULL, NULL) +AUX_REG (aux_cabac_misc0, NULL, NULL) +AUX_REG (aux_cabac_misc1, NULL, NULL) +AUX_REG (aux_cabac_misc2, NULL, NULL) +AUX_REG (aux_cavlc_zero_left, NULL, NULL) +AUX_REG (aux_crc_mode, NULL, NULL) +AUX_REG (aux_crc_poly, NULL, NULL) +AUX_REG (aux_dccm, NULL, NULL) +AUX_REG (aux_dpfp1h, NULL, NULL) +AUX_REG (aux_dpfp1l, NULL, NULL) +AUX_REG (aux_dpfp2h, NULL, NULL) +AUX_REG (aux_dpfp2l, NULL, NULL) +AUX_REG (aux_fbf_store_16, NULL, NULL) +AUX_REG (aux_inter_core_interrupt, NULL, NULL) +AUX_REG (irq_priority, aux_irq_get, aux_irq_set) +AUX_REG (aux_irq_act, aux_irq_get, aux_irq_set) +AUX_REG (aux_irq_hint, aux_irq_get, aux_irq_set) +AUX_REG (aux_irq_lev, NULL, NULL) +AUX_REG (aux_irq_lv12, NULL, NULL) +AUX_REG (irq_pending, aux_irq_get, NULL) +AUX_REG (irq_pulse_cancel, NULL, aux_irq_set) +AUX_REG (aux_irq_ctrl, aux_irq_get, aux_irq_set) +AUX_REG (aux_kernel_sp, NULL, NULL) +AUX_REG (aux_ldst_ram, NULL, NULL) +AUX_REG (aux_macmode, NULL, NULL) +AUX_REG (aux_sec_ctrl, NULL, NULL) +AUX_REG (aux_sec_except, NULL, NULL) +AUX_REG (aux_sec_k_sp, NULL, NULL) +AUX_REG (aux_sec_u_sp, NULL, NULL) +AUX_REG (aux_ucavlc_setup, NULL, NULL) +AUX_REG (aux_ucavlc_state, NULL, NULL) +AUX_REG (aux_user_sp, aux_irq_get, aux_irq_set) +AUX_REG (aux_uvlc_i_state, NULL, NULL) +AUX_REG (aux_vbfdw_accu, NULL, NULL) +AUX_REG (aux_vbfdw_bm0, NULL, NULL) +AUX_REG (aux_vbfdw_bm1, NULL, NULL) +AUX_REG (aux_vbfdw_intstat, NULL, NULL) +AUX_REG (aux_vbfdw_mode, NULL, NULL) +AUX_REG (aux_vbfdw_ofst, NULL, NULL) +AUX_REG (aux_volatile, NULL, NULL) +AUX_REG (aux_vlc_bits, NULL, NULL) +AUX_REG (aux_vlc_buf_free, NULL, NULL) +AUX_REG (aux_vlc_buf_idx, NULL, NULL) +AUX_REG (aux_vlc_buf_in, NULL, NULL) +AUX_REG (aux_vlc_dma_ctrl, NULL, NULL) +AUX_REG (aux_vlc_dma_end, NULL, NULL) +AUX_REG (aux_vlc_dma_esc, NULL, NULL) +AUX_REG (aux_vlc_dma_ptr, NULL, NULL) +AUX_REG (aux_vlc_get_0bit, NULL, NULL) +AUX_REG (aux_vlc_get_10bit, NULL, NULL) +AUX_REG (aux_vlc_get_11bit, NULL, NULL) +AUX_REG (aux_vlc_get_12bit, NULL, NULL) +AUX_REG (aux_vlc_get_13bit, NULL, NULL) +AUX_REG (aux_vlc_get_14bit, NULL, NULL) +AUX_REG (aux_vlc_get_15bit, NULL, NULL) +AUX_REG (aux_vlc_get_16bit, NULL, NULL) +AUX_REG (aux_vlc_get_17bit, NULL, NULL) +AUX_REG (aux_vlc_get_18bit, NULL, NULL) +AUX_REG (aux_vlc_get_19bit, NULL, NULL) +AUX_REG (aux_vlc_get_1bit, NULL, NULL) +AUX_REG (aux_vlc_get_20bit, NULL, NULL) +AUX_REG (aux_vlc_get_21bit, NULL, NULL) +AUX_REG (aux_vlc_get_22bit, NULL, NULL) +AUX_REG (aux_vlc_get_23bit, NULL, NULL) +AUX_REG (aux_vlc_get_24bit, NULL, NULL) +AUX_REG (aux_vlc_get_25bit, NULL, NULL) +AUX_REG (aux_vlc_get_26bit, NULL, NULL) +AUX_REG (aux_vlc_get_27bit, NULL, NULL) +AUX_REG (aux_vlc_get_28bit, NULL, NULL) +AUX_REG (aux_vlc_get_29bit, NULL, NULL) +AUX_REG (aux_vlc_get_2bit, NULL, NULL) +AUX_REG (aux_vlc_get_30bit, NULL, NULL) +AUX_REG (aux_vlc_get_31bit, NULL, NULL) +AUX_REG (aux_vlc_get_3bit, NULL, NULL) +AUX_REG (aux_vlc_get_4bit, NULL, NULL) +AUX_REG (aux_vlc_get_5bit, NULL, NULL) +AUX_REG (aux_vlc_get_6bit, NULL, NULL) +AUX_REG (aux_vlc_get_7bit, NULL, NULL) +AUX_REG (aux_vlc_get_8bit, NULL, NULL) +AUX_REG (aux_vlc_get_9bit, NULL, NULL) +AUX_REG (aux_vlc_get_symbol, NULL, NULL) +AUX_REG (aux_vlc_ibuf_status, NULL, NULL) +AUX_REG (aux_vlc_read_buf, NULL, NULL) +AUX_REG (aux_vlc_read_symbol, NULL, NULL) +AUX_REG (aux_vlc_setup, NULL, NULL) +AUX_REG (aux_vlc_table, NULL, NULL) +AUX_REG (aux_vlc_valid_bits, NULL, NULL) +AUX_REG (aux_xmac0_24, NULL, NULL) +AUX_REG (aux_xmac0, NULL, NULL) +AUX_REG (aux_xmac1_24, NULL, NULL) +AUX_REG (aux_xmac1, NULL, NULL) +AUX_REG (aux_xmac2_24, NULL, NULL) +AUX_REG (aux_xmac2, NULL, NULL) +AUX_REG (aux_xmaclw_h, NULL, NULL) +AUX_REG (aux_xmaclw_l, NULL, NULL) +AUX_REG (ax0, NULL, NULL) +AUX_REG (ax1, NULL, NULL) +AUX_REG (ax2, NULL, NULL) +AUX_REG (ax3, NULL, NULL) +AUX_REG (ay0, NULL, NULL) +AUX_REG (ay1, NULL, NULL) +AUX_REG (ay2, NULL, NULL) +AUX_REG (ay3, NULL, NULL) +AUX_REG (bpu_flush, NULL, NULL) +AUX_REG (bta_l1, NULL, NULL) +AUX_REG (bta_l2, NULL, NULL) +AUX_REG (bta_link_build, NULL, NULL) +AUX_REG (bta, NULL, NULL) +AUX_REG (burstsys, NULL, NULL) +AUX_REG (burstsz, NULL, NULL) +AUX_REG (burstval, NULL, NULL) +AUX_REG (burstxym, NULL, NULL) +AUX_REG (cc_build, NULL, NULL) +AUX_REG (che_mode, NULL, NULL) +AUX_REG (clk_enable, NULL, NULL) +AUX_REG (control0, aux_timer_get, aux_timer_set) +AUX_REG (control1, aux_timer_get, aux_timer_set) +AUX_REG (count0, aux_timer_get, aux_timer_set) +AUX_REG (count1, aux_timer_get, aux_timer_set) +AUX_REG (d1h, NULL, NULL) +AUX_REG (d1l, NULL, NULL) +AUX_REG (d2h, NULL, NULL) +AUX_REG (d2l, NULL, NULL) +AUX_REG (dataspace, NULL, NULL) +AUX_REG (data_uncached_build, NULL, NULL) +AUX_REG (dccm_base_build, NULL, NULL) +AUX_REG (d_cache_build, arc_cache_aux_get, NULL) +AUX_REG (dc_ctrl, arc_cache_aux_get, arc_cache_aux_set) +AUX_REG (dc_data, NULL, NULL) +AUX_REG (dc_fldl, NULL, arc_cache_aux_set) +AUX_REG (dc_flsh, NULL, arc_cache_aux_set) +AUX_REG (dc_ivdc, NULL, arc_cache_aux_set) +AUX_REG (dc_ivdl, NULL, arc_cache_aux_set) +AUX_REG (dc_ldl, NULL, NULL) +AUX_REG (dc_startr, NULL, arc_cache_aux_set) +AUX_REG (dc_endr, arc_cache_aux_get, arc_cache_aux_set) +AUX_REG (dc_ptag, NULL, NULL) +AUX_REG (dc_ptag_hi, arc_cache_aux_get, arc_cache_aux_set) +AUX_REG (dc_ram_addr, NULL, NULL) +AUX_REG (dc_tag, NULL, NULL) +AUX_REG (dc_wp, NULL, NULL) +AUX_REG (debugi, NULL, NULL) +AUX_REG (debug, NULL, NULL) +AUX_REG (des_aux, NULL, NULL) +AUX_REG (dilstat, NULL, NULL) +AUX_REG (dma_config, NULL, NULL) +AUX_REG (dmc_code_ram, NULL, NULL) +AUX_REG (dpfp_build, NULL, NULL) +AUX_REG (dpfp_status, NULL, NULL) +AUX_REG (dvfs_performance, NULL, NULL) +AUX_REG (ea_build, NULL, NULL) +AUX_REG (ecr, NULL, NULL) +AUX_REG (efa, NULL, NULL) +AUX_REG (ei_base, NULL, NULL) +AUX_REG (erbta, NULL, NULL) +AUX_REG (eret, NULL, NULL) +AUX_REG (erp_control, NULL, NULL) +AUX_REG (ersec_stat, NULL, NULL) +AUX_REG (erstatus, NULL, NULL) +AUX_REG (exec_ctrl, NULL, NULL) +AUX_REG (fp_build, NULL, NULL) +AUX_REG (fp_status, NULL, NULL) +AUX_REG (hexctrl, NULL, NULL) +AUX_REG (hexdata, NULL, NULL) +AUX_REG (hwp_build, NULL, NULL) +AUX_REG (icause, aux_irq_get, NULL) +AUX_REG (irq_select, aux_irq_get, aux_irq_set) +AUX_REG (irq_enable, aux_irq_get, aux_irq_set) +AUX_REG (irq_trigger, aux_irq_get, aux_irq_set) +AUX_REG (irq_status, aux_irq_get, NULL) +AUX_REG (i_cache_build, arc_cache_aux_get, NULL) +AUX_REG (ic_ctrl, arc_cache_aux_get, arc_cache_aux_set) +AUX_REG (ic_data, NULL, NULL) +AUX_REG (ic_startr, NULL, arc_cache_aux_set) +AUX_REG (ic_endr, arc_cache_aux_get, arc_cache_aux_set) +AUX_REG (ic_ivic, NULL, arc_cache_aux_set) +AUX_REG (ic_ivil, NULL, arc_cache_aux_set) +AUX_REG (ic_ivir, arc_cache_aux_get, arc_cache_aux_set) +AUX_REG (ic_lil, NULL, NULL) +AUX_REG (ic_ptag, arc_cache_aux_get, arc_cache_aux_set) +AUX_REG (ic_ptag_hi, arc_cache_aux_get, arc_cache_aux_set) +AUX_REG (ic_ram_address, NULL, NULL) +AUX_REG (ic_tag, NULL, NULL) +AUX_REG (ic_wp, NULL, NULL) +AUX_REG (identity, NULL, NULL) +AUX_REG (ifetch_queue_build, NULL, NULL) +AUX_REG (int_vector_base, aux_irq_get, aux_irq_set) +AUX_REG (irq_build, aux_irq_get, NULL) +AUX_REG (irq_priority_pending, NULL, NULL) +AUX_REG (isa_config, NULL, NULL) +AUX_REG (ivic, NULL, NULL) +AUX_REG (jli_base, TO_IMPLEMENT_GET, TO_IMPLEMENT_SET) +AUX_REG (ldi_base, NULL, NULL) +AUX_REG (led, NULL, NULL) +AUX_REG (limit0, aux_timer_get, aux_timer_set) +AUX_REG (limit1, aux_timer_get, aux_timer_set) +AUX_REG (line_length_mask, NULL, NULL) +AUX_REG (lockline, NULL, NULL) +AUX_REG (lp_end, NULL, NULL) +AUX_REG (lp_start, NULL, NULL) +AUX_REG (lsp_newval, NULL, NULL) +AUX_REG (madi_build, NULL, NULL) +AUX_REG (memseg, NULL, NULL) +AUX_REG (memsubsys, NULL, NULL) +AUX_REG (mmu_build, arc_mmu_aux_get, NULL) +AUX_REG (mpu_build, arc_mpu_aux_get, NULL) +AUX_REG (mpuen, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpufa, NULL, NULL) +AUX_REG (mpuic, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdb0, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdb1, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdb2, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdb3, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdb4, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdb5, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdb6, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdb7, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdb8, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdb9, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdb10, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdb11, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdb12, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdb13, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdb14, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdb15, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdp0, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdp1, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdp2, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdp3, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdp4, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdp5, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdp6, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdp7, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdp8, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdp9, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdp10, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdp11, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdp12, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdp13, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdp14, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpurdp15, arc_mpu_aux_get, arc_mpu_aux_set) +AUX_REG (mpy_build, NULL, NULL) +AUX_REG (mulhi, NULL, NULL) +AUX_REG (mx00, NULL, NULL) +AUX_REG (mx01, NULL, NULL) +AUX_REG (mx0, NULL, NULL) +AUX_REG (mx10, NULL, NULL) +AUX_REG (mx11, NULL, NULL) +AUX_REG (mx1, NULL, NULL) +AUX_REG (mx20, NULL, NULL) +AUX_REG (mx21, NULL, NULL) +AUX_REG (mx30, NULL, NULL) +AUX_REG (mx31, NULL, NULL) +AUX_REG (my00, NULL, NULL) +AUX_REG (my01, NULL, NULL) +AUX_REG (my0, NULL, NULL) +AUX_REG (my10, NULL, NULL) +AUX_REG (my11, NULL, NULL) +AUX_REG (my1, NULL, NULL) +AUX_REG (my20, NULL, NULL) +AUX_REG (my21, NULL, NULL) +AUX_REG (my30, NULL, NULL) +AUX_REG (my31, NULL, NULL) +AUX_REG (nsc_table_base, NULL, NULL) +AUX_REG (nsc_table_top, NULL, NULL) +AUX_REG (p_base_addr, NULL, NULL) +AUX_REG (pc, NULL, NULL) +AUX_REG (pcport, NULL, NULL) +AUX_REG (pct_build, NULL, NULL) +AUX_REG (pid, arc_mmu_aux_get, arc_mmu_aux_set) +AUX_REG (sasid0, arc_mmu_aux_get, arc_mmu_aux_set) +AUX_REG (sasid1, arc_mmu_aux_get, arc_mmu_aux_set) +AUX_REG (pm_bcr, NULL, NULL) +AUX_REG (pm_status, NULL, NULL) +AUX_REG (pwr_ctrl, NULL, NULL) +AUX_REG (rf_build, NULL, NULL) +AUX_REG (rferp_status0, NULL, NULL) +AUX_REG (rferp_status1, NULL, NULL) +AUX_REG (scm_base, NULL, NULL) +AUX_REG (scq_switch_build, NULL, NULL) +AUX_REG (scratch_a, NULL, NULL) +AUX_REG (scratch_data0, arc_mmu_aux_get, arc_mmu_aux_set) +AUX_REG (sdm_base, NULL, NULL) +AUX_REG (sec_extra, NULL, NULL) +AUX_REG (sec_stat, NULL, NULL) +AUX_REG (se_ctrl, NULL, NULL) +AUX_REG (sec_vecbase_build, NULL, NULL) +AUX_REG (se_dbg_ctrl, NULL, NULL) +AUX_REG (se_dbg_data0, NULL, NULL) +AUX_REG (se_dbg_data1, NULL, NULL) +AUX_REG (se_dbg_data2, NULL, NULL) +AUX_REG (se_dbg_data3, NULL, NULL) +AUX_REG (se_eadr, NULL, NULL) +AUX_REG (se_err, NULL, NULL) +AUX_REG (semaphore, NULL, NULL) +AUX_REG (se_spc, NULL, NULL) +AUX_REG (se_stat, NULL, NULL) +AUX_REG (se_watch, NULL, NULL) +AUX_REG (simd_config, NULL, NULL) +AUX_REG (simd_dma_build, NULL, NULL) +AUX_REG (smart_control, NULL, NULL) +AUX_REG (smart_data_0, NULL, NULL) +AUX_REG (smart_data_2, NULL, NULL) +AUX_REG (smart_data_3, NULL, NULL) +AUX_REG (smart_data, NULL, NULL) +AUX_REG (sram_seq, NULL, NULL) +AUX_REG (status32, NULL, NULL) +AUX_REG (status32_p0, NULL, NULL) +AUX_REG (swstat, NULL, NULL) +AUX_REG (tag_addr_mask, NULL, NULL) +AUX_REG (tag_data_mask, NULL, NULL) +AUX_REG (timer_build, aux_timer_get, NULL) +AUX_REG (tlbcommand, arc_mmu_aux_get, arc_mmu_aux_set_tlbcmd) +AUX_REG (tlbindex, arc_mmu_aux_get, arc_mmu_aux_set) +AUX_REG (tlbpd0, arc_mmu_aux_get, arc_mmu_aux_set) +AUX_REG (tlbpd1_hi, arc_mmu_aux_get, arc_mmu_aux_set) +AUX_REG (tlbpd1, arc_mmu_aux_get, arc_mmu_aux_set) +AUX_REG (tsch, NULL, NULL) +AUX_REG (unlockline, NULL, NULL) +AUX_REG (vbfdw_build, NULL, NULL) +AUX_REG (vecbase_ac_build, aux_irq_get, NULL) +AUX_REG (vecbase_build, NULL, NULL) +AUX_REG (vlc_build, NULL, NULL) +AUX_REG (vraptor_build, NULL, NULL) +AUX_REG (wake, NULL, NULL) +AUX_REG (xpu, NULL, NULL) +AUX_REG (xtp_newval, NULL, NULL) +AUX_REG (xyconfig, NULL, NULL) +AUX_REG (xylsbasex, NULL, NULL) +AUX_REG (xylsbasey, NULL, NULL) +AUX_REG (aux_rtc_ctrl, aux_timer_get, aux_timer_set) +AUX_REG (aux_rtc_low, aux_timer_get, aux_timer_set) +AUX_REG (aux_rtc_high, aux_timer_get, aux_timer_set) diff --git a/target/arc/regs.h b/target/arc/regs.h new file mode 100644 index 0000000000..aad8bda443 --- /dev/null +++ b/target/arc/regs.h @@ -0,0 +1,118 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synppsys Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#ifndef ARC_REGS_H +#define ARC_REGS_H + +#include "target/arc/decoder.h" + +/* + * BCRs (Build configuration registers) are very special AUX regs + * as they are always readable even if corresponding HW module is absent. + * Thus we may always safely read them and learn what HW we have. + * All other AUX regs outside of 2 BCR areas are only readable if their + * HW is really implemented, otherwise "Instruction error" exception + * is raised by the CPU. + */ + +/* First BCR region. */ +#define ARC_BCR1_START 0x60 +#define ARC_BCR1_END 0x7f +/* Second BCR region. */ +#define ARC_BCR2_START 0xc0 +#define ARC_BCR2_END 0xff + +enum arc_aux_reg_enum { + ARC_AUX_REGS_INVALID = -1, +#define AUX_REG(NAME, GET, SET) AUX_ID_##NAME, +#include "target/arc/regs.def" +#undef AUX_REG + ARC_AUX_REGS_LAST +}; + +enum arc_aux_reg_detail_enum { + ARC_AUX_REGS_DETAIL_INVALID = -1, +#define DEF(NUM, CPU, SUB, NAME) CPU##_##NUM, +#include "target/arc/regs-detail.def" +#undef DEF + ARC_AUX_REGS_DETAIL_LAST +}; + +struct arc_aux_regs_data; +struct arc_aux_reg_detail { + /* Register address. */ + int address; + + /* + * One bit flags for the opcode. These are primarily used to + * indicate specific processors and environments support the + * instructions. + */ + enum arc_cpu_family cpu; + + /* AUX register subclass. */ + insn_subclass_t subclass; + + /* Enum for aux-reg. */ + enum arc_aux_reg_enum id; + + /* Register name. */ + const char *name; + + /* Size of the string. */ + size_t length; + + /* pointer to the first element in the list. */ + struct arc_aux_reg_detail *next; + + /* pointer to the first element in the list. */ + struct arc_aux_reg *aux_reg; +}; + +typedef void (* aux_reg_set_func)(const struct arc_aux_reg_detail *aux_reg, + uint32_t val, void *data); +typedef uint32_t (* aux_reg_get_func)(const struct arc_aux_reg_detail *aux_reg, + void *data); + +struct arc_aux_reg { + /* pointer to the first element in the list. */ + struct arc_aux_reg_detail *first; + + /* get and set function for lr and sr helpers */ + aux_reg_get_func get_func; + aux_reg_set_func set_func; +}; + +extern struct arc_aux_reg_detail arc_aux_regs_detail[ARC_AUX_REGS_DETAIL_LAST]; +extern struct arc_aux_reg arc_aux_regs[ARC_AUX_REGS_LAST]; +extern const char *arc_aux_reg_name[ARC_AUX_REGS_DETAIL_LAST]; + +void arc_aux_regs_init(void); +int arc_aux_reg_address_for(enum arc_aux_reg_enum, int); +struct arc_aux_reg_detail *arc_aux_reg_struct_for_address(int, int); + +uint32_t arc_regs_bcr_default_impl(const struct arc_aux_reg_detail *aux_reg, + void *data); + +void TO_IMPLEMENT_SET(const struct arc_aux_reg_detail *aux_reg, uint32_t val, + void *data); +uint32_t TO_IMPLEMENT_GET(const struct arc_aux_reg_detail *aux_reg, void *data); + +#endif /* ARC_REGS_H */ From patchwork Wed Nov 11 16:17:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cupertino Miranda X-Patchwork-Id: 1398392 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2001:8b0:10b:1231::1; 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[2.80.104.46]) by smtp.gmail.com with ESMTPSA id s188sm3115178wmf.45.2020.11.11.08.18.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2020 08:18:15 -0800 (PST) From: cupertinomiranda@gmail.com To: qemu-devel@nongnu.org Subject: [PATCH 08/15] arc: Add IRQ and timer subsystem support Date: Wed, 11 Nov 2020 16:17:51 +0000 Message-Id: <20201111161758.9636-9-cupertinomiranda@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201111161758.9636-1-cupertinomiranda@gmail.com> References: <20201111161758.9636-1-cupertinomiranda@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201111_111818_457896_4A9CD639 X-CRM114-Status: GOOD ( 23.54 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:336 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [cupertinomiranda[at]gmail.com] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Claudiu Zissulescu , Cupertino Miranda , Shahab Vahedi , Shahab Vahedi , Cupertino Miranda , linux-snps-arc@lists.infradead.org, Claudiu Zissulescu Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Claudiu Zissulescu Signed-off-by: Claudiu Zissulescu --- target/arc/irq.c | 658 +++++++++++++++++++++++++++++++++++++++++++++ target/arc/irq.h | 37 +++ target/arc/timer.c | 454 +++++++++++++++++++++++++++++++ target/arc/timer.h | 30 +++ 4 files changed, 1179 insertions(+) create mode 100644 target/arc/irq.c create mode 100644 target/arc/irq.h create mode 100644 target/arc/timer.c create mode 100644 target/arc/timer.h diff --git a/target/arc/irq.c b/target/arc/irq.c new file mode 100644 index 0000000000..2134fbad16 --- /dev/null +++ b/target/arc/irq.c @@ -0,0 +1,658 @@ +/* + * QEMU ARC CPU - IRQ subsystem + * + * Copyright (c) 2020 Synopsys Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "hw/irq.h" +#include "cpu.h" +#include "qemu/main-loop.h" +#include "irq.h" +#include "exec/cpu_ldst.h" +#include "translate.h" +#include "qemu/host-utils.h" + +/* Static functions and variables. */ + +static uint32_t save_reg_pair_32[] = { + 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 +}; + +static uint32_t save_reg_pair_16[] = { + 0, 2, 10, 12, 14, 26, 28, 30 +}; + +bool enabled_interrupts = false; + +/* Given a struct STATUS_R, pack it to 32 bit. */ +uint32_t pack_status32(status_t *status_r) +{ + uint32_t res = 0x00000000; + + res |= (status_r->IEf & 0x1) << 31; + res |= (status_r->USf & 0x1) << 20; + res |= (status_r->ADf & 0x1) << 19; + res |= (status_r->RBf & 0x7) << 16; + res |= (status_r->ESf & 0x1) << 15; + res |= (status_r->SCf & 0x1) << 14; + res |= (status_r->DZf & 0x1) << 13; + res |= (status_r->Lf & 0x1) << 12; + res |= (status_r->Zf & 0x1) << 11; + res |= (status_r->Nf & 0x1) << 10; + res |= (status_r->Cf & 0x1) << 9; + res |= (status_r->Vf & 0x1) << 8; + res |= (status_r->Uf & 0x1) << 7; + res |= (status_r->DEf & 0x1) << 6; + res |= (status_r->AEf & 0x1) << 5; + res |= (status_r->Ef & 0xf) << 1; + + return res; +} + +/* Reverse of the above function. */ +void unpack_status32(status_t *status_r, uint32_t value) +{ + status_r->IEf = ((value >> 31) & 0x1); + status_r->USf = ((value >> 20) & 0x1); + status_r->ADf = ((value >> 19) & 0x1); + status_r->RBf = ((value >> 16) & 0x7); + status_r->ESf = ((value >> 15) & 0x1); + status_r->SCf = ((value >> 14) & 0x1); + status_r->DZf = ((value >> 13) & 0x1); + status_r->Lf = ((value >> 12) & 0x1); + status_r->Zf = ((value >> 11) & 0x1); + status_r->Nf = ((value >> 10) & 0x1); + status_r->Cf = ((value >> 9) & 0x1); + status_r->Vf = ((value >> 8) & 0x1); + status_r->Uf = ((value >> 7) & 0x1); + status_r->DEf = ((value >> 6) & 0x1); + status_r->AEf = ((value >> 5) & 0x1); + status_r->Ef = ((value >> 1) & 0xf); +} + +/* Return from fast interrupts. */ + +static void arc_rtie_firq(CPUARCState *env) +{ + assert(env->stat.AEf == 0); + + qemu_log_mask(CPU_LOG_INT, "[IRQ] exit firq: U=%d, AUX_IRQ_ACT.U=%d\n", + env->stat.Uf, env->aux_irq_act >> 31); + + /* Clear currently active interrupt. */ + env->aux_irq_act &= 0xfffffffe; + + /* Check if we need to restore userland SP. */ + if (((env->aux_irq_act & 0xFFFF) == 0) && (env->aux_irq_act & 0x80000000)) { + switchSP(env); + } + + env->stat = env->stat_l1; /* FIXME use status32_p0 reg. */ + env->aux_irq_act &= ~(env->stat.Uf << 31); /* Keep U-bit in sync. */ + + /* FIXME! fix current reg bank if RB bit is changed. */ + + CPU_PCL(env) = CPU_ILINK(env); + env->pc = CPU_ILINK(env); +} + +/* Implements a pop operation from the CPU stack. */ +static uint32_t irq_pop(CPUARCState *env, const char *str) +{ + uint32_t rval; + rval = cpu_ldl_data(env, CPU_SP(env)); + + qemu_log_mask(CPU_LOG_INT, "[IRQ] Pop [SP:0x%08x] => 0x%08x (%s)\n", + CPU_SP(env), rval, str ? str : "unk"); + CPU_SP(env) += 4; + return rval; +} + +/* Return from regular interrupts. */ + +static void arc_rtie_irq(CPUARCState *env) +{ + uint32_t tmp; + ARCCPU *cpu = env_archcpu(env); + + assert((env->aux_irq_act & 0xFFFF) != 0); + assert(env->stat.AEf == 0); + + /* Clear currently active interrupt. */ + tmp = ctz32(env->aux_irq_act & 0xffff); + + qemu_log_mask(CPU_LOG_INT, + "[IRQ] exit irq:%d IRQ_ACT:0x%08x PRIO:%d\n", + env->icause[tmp], env->aux_irq_act, tmp); + + /* + * FIXME! I assume the current active interrupt is the one which is + * the highest in the aux_irq_act register. + */ + env->aux_irq_act &= ~(1 << tmp); + + qemu_log_mask(CPU_LOG_INT, + "[IRQ] exit irq:%d U:%d AE:%d IE:%d E:%d IRQ_ACT:0x%08x\n", + env->icause[tmp], env->stat.Uf, env->stat.AEf, env->stat.IEf, + env->stat.Ef, env->aux_irq_act); + + if (((env->aux_irq_act & 0xffff) == 0) && + (env->aux_irq_act & 0x80000000) && (env->aux_irq_ctrl & (1 << 11))) { + switchSP(env); + } + + /* Pop requested number of registers. */ + /* FIXME! select rf16 when needed. */ + uint32_t *save_reg_pair = save_reg_pair_32; + char regname[6]; + uint32_t i; + for (i = 0; i < (env->aux_irq_ctrl & 0x1F); ++i) { + sprintf(regname, "r%d", save_reg_pair[i]); + env->r[save_reg_pair[i]] = irq_pop(env, (const char *) regname); + sprintf(regname, "r%d", save_reg_pair[i] + 1); + env->r[save_reg_pair[i] + 1] = irq_pop(env, (const char *) regname); + } + + /* Pop BLINK */ + if (env->aux_irq_ctrl & (1 << 9) && ((env->aux_irq_ctrl & 0x1F) != 16)) { + CPU_BLINK(env) = irq_pop(env, "blink"); + } + + /* Pop lp_end, lp_start, lp_count if aux_irq_ctrl.l bit is set. */ + if (env->aux_irq_ctrl & (1 << 10)) { + env->lpe = irq_pop(env, "LP_END"); + env->lps = irq_pop(env, "LP_START"); + CPU_LP(env) = irq_pop(env, "lp"); + } + + /* + * Pop EI_BASE, JLI_BASE, LDI_BASE if LP bit is set and Code + * Density feature is enabled. FIXME! + */ + if (cpu->cfg.code_density && (env->aux_irq_ctrl & (1 << 13))) { + /* FIXME! env->aux_ei_base = irq_pop(env); */ + /* FIXME! env->aux_ldi_base = irq_pop(env); */ + /* FIXME! env->aux_jli_base = irq_pop(env); */ + irq_pop(env, "dummy EI_BASE"); + irq_pop(env, "dummy LDI_BASE"); + irq_pop(env, "dummy JLI_BASE"); + } + + CPU_ILINK(env) = irq_pop(env, "PC"); /* CPU PC*/ + uint32_t tmp_stat = irq_pop(env, "STATUS32"); /* status. */ + unpack_status32(&env->stat, tmp_stat); + + /* Late switch to Kernel SP if previously in User thread. */ + if (((env->aux_irq_act & 0xffff) == 0) + && env->stat.Uf && !(env->aux_irq_ctrl & (1 << 11))) { + switchSP(env); + } + + env->aux_irq_act &= ~(env->stat.Uf << 31); /* Keep U-bit in sync. */ + CPU_PCL(env) = CPU_ILINK(env); + env->pc = CPU_ILINK(env); +} + +/* Helper, implements entering in a fast irq. */ +static void arc_enter_firq(ARCCPU *cpu, uint32_t vector) +{ + CPUARCState *env = &cpu->env; + + assert(env->stat.DEf == 0); + assert(env->stat.is_delay_slot_instruction == 0); + + /* Reset RTC state machine -> AUX_RTC_CTRL &= 0x3fffffff */ + qemu_log_mask(CPU_LOG_INT, + "[IRQ] enter firq:%d U:%d AE:%d IE:%d E:%d\n", + vector, env->stat.Uf, env->stat.AEf, env->stat.IEf, + env->stat.Ef); + + /* Switch SP with AUX_SP. */ + if (env->stat.Uf) { + switchSP(env); + } + + /* Clobber ILINK with address of interrupting instruction. */ + CPU_ILINK(env) = env->pc & 0xfffffffe; + env->stat_l1 = env->stat; + + /* Set stat {Z = U; U = 0; L = 1; ES = 0; DZ = 0; DE = 0;} */ + env->stat.Lf = 1; + env->stat.Zf = env->stat.Uf; /* Old User/Kernel bit. */ + env->stat.Uf = 0; + env->stat.ESf = 0; + env->stat.DZf = 0; + env->stat.DEf = 0; + env->stat.is_delay_slot_instruction = 0; + + /* Set .RB to 1 if additional register banks are specified. */ + if (cpu->cfg.rgf_num_banks > 0) { + env->stat.RBf = 1; + /* FIXME! Switch to first register bank. */ + } +} + +/* Implements a push operation to the CPU stack. */ +static void irq_push(CPUARCState *env, uint32_t regval, const char *str) +{ + CPU_SP(env) -= 4; + qemu_log_mask(CPU_LOG_INT, "[IRQ] Push [SP:0x%08x] <= 0x%08x (%s)\n", + CPU_SP(env), regval, str ? str : "unk"); + uint32_t uf = env->stat.Uf; + env->stat.Uf = 0; + cpu_stl_data(env, CPU_SP(env), regval); + env->stat.Uf = uf; +} + +/* Helper, implements the steps required to enter a simple interrupt. */ +static void arc_enter_irq(ARCCPU *cpu, uint32_t vector) +{ + CPUARCState *env = &cpu->env; + + assert(env->stat.DEf == 0); + assert(env->stat.is_delay_slot_instruction == 0); + + /* Reset RTC state machine -> AUX_RTC_CTRL &= 0x3fffffff */ + qemu_log_mask(CPU_LOG_INT, "[IRQ] enter irq:%d U:%d AE:%d IE:%d E:%d\n", + vector, env->stat.Uf, env->stat.AEf, env->stat.IEf, + env->stat.Ef); + + /* Early switch to kernel sp if previously in user thread */ + if (env->stat.Uf && !(env->aux_irq_ctrl & (1 << 11))) { + switchSP(env); + } + + /* Clobber ILINK with address of interrupting instruction. */ + CPU_ILINK(env) = env->pc & 0xfffffffe; + + /* Start pushing regs and stat. */ + irq_push(env, pack_status32(&env->stat), "STATUS32"); + irq_push(env, env->pc, "PC"); + + /* + * Push EI_BASE, JLI_BASE, LDI_BASE if LP bit is set and Code + * Density feature is enabled. + */ + if (cpu->cfg.code_density && (env->aux_irq_ctrl & (1 << 13))) { + /* FIXME! irq_push(env, env->aux_jli_base, "JLI_BASE"); */ + /* FIXME! irq_push(env, env->aux_ldi_base, "LDI_BASE""); */ + /* FIXME! irq_push(env, env->aux_ei_base, "EI_BASE"); */ + irq_push(env, 0xdeadbeef, "dummy JLI_BASE"); + irq_push(env, 0xdeadbeef, "dummy LDI_BASE"); + irq_push(env, 0xdeadbeef, "dummy EI_BASE"); + } + + /* Push LP_COUNT, LP_START, LP_END registers if required. */ + if (env->aux_irq_ctrl & (1 << 10)) { + irq_push(env, CPU_LP(env), "lp"); + irq_push(env, env->lps, "LP_START"); + irq_push(env, env->lpe, "LP_END"); + } + + /* Push BLINK register if required */ + if (env->aux_irq_ctrl & (1 << 9) && ((env->aux_irq_ctrl & 0x1F) != 16)) { + irq_push(env, CPU_BLINK(env), "blink"); + } + + /* Push selected AUX_IRQ_CTRL.NR of registers onto stack. */ + uint32_t *save_reg_pair = cpu->cfg.rgf_num_regs == 32 ? + save_reg_pair_32 : save_reg_pair_16; + const uint32_t regspair = (cpu->cfg.rgf_num_regs == 32 ? 16 : 8); + const uint32_t upperlimit = (env->aux_irq_ctrl & 0x1F) < regspair ? + env->aux_irq_ctrl & 0x1F : regspair; + char regname[6]; + uint32_t i; + + for (i = upperlimit; i > 0; --i) { + sprintf(regname, "r%d", save_reg_pair[i - 1] + 1); + irq_push(env, env->r[save_reg_pair[i - 1] + 1], (const char *) regname); + sprintf(regname, "r%d", save_reg_pair[i - 1]); + irq_push(env, env->r[save_reg_pair[i - 1]], (const char *) regname); + } + + /* Late switch to Kernel SP if previously in User thread. */ + if (env->stat.Uf && (env->aux_irq_ctrl & (1 << 11))) { + switchSP(env); + } + + /* Set STATUS bits */ + env->stat.Zf = env->stat.Uf; /* Old User/Kernel mode. */ + env->stat.Lf = 1; + env->stat.ESf = 0; + env->stat.DZf = 0; + env->stat.DEf = 0; + env->stat.Uf = 0; +} + +/* Function implementation for reading the IRQ related aux regs. */ +uint32_t aux_irq_get(const struct arc_aux_reg_detail *aux_reg_detail, + void *data) +{ + CPUARCState *env = (CPUARCState *) data; + uint32_t tmp; + + /* extract selected IRQ. */ + const uint32_t irq = env->irq_select; + const arc_irq_t *irq_bank = &env->irq_bank[irq]; + + switch (aux_reg_detail->id) { + case AUX_ID_irq_pending: + return irq_bank->pending | (irq > 15 ? (env->aux_irq_hint == irq) : 0); + + case AUX_ID_irq_select: + return env->irq_select; + + case AUX_ID_irq_priority: + return irq_bank->priority; + + case AUX_ID_irq_trigger: + return irq_bank->trigger; + + case AUX_ID_irq_status: + return (irq_bank->priority + | irq_bank->enable << 4 + | irq_bank->trigger << 5 + | (irq_bank->pending + | (irq > 15 ? ((env->aux_irq_hint == irq) << 31) : 0))); + + case AUX_ID_aux_irq_act: + return env->aux_irq_act; + + case AUX_ID_aux_irq_ctrl: + return env->aux_irq_ctrl; + + case AUX_ID_icause: + if ((env->aux_irq_act & 0xffff) == 0) { + return 0; + } + tmp = ctz32(env->aux_irq_act & 0xffff); + return env->icause[tmp]; + + case AUX_ID_irq_build: + return env->irq_build; + + case AUX_ID_int_vector_base: + return env->intvec; + + case AUX_ID_vecbase_ac_build: + return env->vecbase_build; + break; + + case AUX_ID_aux_user_sp: + return env->aux_user_sp; + + case AUX_ID_aux_irq_hint: + return env->aux_irq_hint; + + default: + break; + } + return 0; +} + +/* Function implementation for writing the IRQ related aux regs. */ +void aux_irq_set(const struct arc_aux_reg_detail *aux_reg_detail, + uint32_t val, void *data) +{ + CPUARCState *env = (CPUARCState *) data; + const uint32_t irq = env->irq_select; + arc_irq_t *irq_bank = &env->irq_bank[irq]; + + qemu_log_mask(CPU_LOG_INT, "[IRQ] set aux_reg: %s, with 0x%08x\n", + arc_aux_reg_name[aux_reg_detail->id], + val); + + + switch (aux_reg_detail->id) { + case AUX_ID_irq_select: + if (val <= (16 + ((env->irq_build >> 8) & 0xff))) + env->irq_select = val; + else + qemu_log_mask(LOG_UNIMP, + "[IRQ] Invalid write 0x%08x to IRQ_SELECT aux reg.\n", + val); + break; + + case AUX_ID_aux_irq_hint: + qemu_mutex_lock_iothread(); + if (val == 0) { + qemu_irq_lower(env->irq[env->aux_irq_hint]); + } else if (val >= 16) { + qemu_irq_raise(env->irq[val]); + env->aux_irq_hint = val; + } + qemu_mutex_unlock_iothread(); + break; + + case AUX_ID_irq_pulse_cancel: + irq_bank->pending = irq_bank->trigger ? (val & 0x01) : 0; + break; + + case AUX_ID_irq_trigger: + irq_bank->trigger = val & 0x01; + break; + + case AUX_ID_irq_priority: + if (val <= ((env->irq_build >> 24) & 0x0f)) { + irq_bank->priority = val & 0x0f; + } else { + qemu_log_mask(LOG_UNIMP, + "[IRQ] Invalid write 0x%08x to IRQ_PRIORITY aux reg.\n", + val); + } + break; + + case AUX_ID_aux_irq_ctrl: + env->aux_irq_ctrl = val & 0x2e1f; + break; + + case AUX_ID_irq_enable: + irq_bank->enable = val & 0x01; + break; + + case AUX_ID_aux_irq_act: + env->aux_irq_act = val & 0x8000ffff; + break; + + case AUX_ID_int_vector_base: + env->intvec = val; + break; + + case AUX_ID_aux_user_sp: + env->aux_user_sp = val; + break; + + default: + break; + } +} + +/* Check if we can interrupt the cpu. */ + +bool arc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + ARCCPU *cpu = ARC_CPU(cs); + CPUARCState *env = &cpu->env; + bool found = false; + uint32_t vectno = 0; + uint32_t offset, priority; + + /* Check if we should execute this interrupt. */ + if (env->stat.Hf + /* The interrupts are enabled. */ + || (env->stat.IEf == 0) + /* We are not in an exception. */ + || env->stat.AEf + /* Disable interrupts to happen after MissI exceptions. */ + || enabled_interrupts == false + /* In a delay slot of branch */ + || env->stat.is_delay_slot_instruction + || env->stat.DEf + || (!(interrupt_request & CPU_INTERRUPT_HARD))) { + return false; + } + + /* Check if any interrupts are pending. */ + if (!env->irq_priority_pending + /* Or we are serving at the same priority level. */ + || (ctz32(env->irq_priority_pending) >= ctz32(env->aux_irq_act))) { + return false; + } + + /* Find the first IRQ to serve. */ + priority = 0; + do { + for (vectno = 0; + vectno < cpu->cfg.number_of_interrupts; vectno++) { + if (env->irq_bank[16 + vectno].priority == priority + && env->irq_bank[16 + vectno].enable + && env->irq_bank[16 + vectno].pending) { + found = true; + break; + } + } + } while (!found && ((++priority) <= env->stat.Ef)); + + /* No valid interrupt has been found. */ + if (!found) { + return false; + } + + qemu_log_mask(CPU_LOG_INT, "[IRQ] interrupt at pc=0x%08x\n", env->pc); + + /* Adjust vector number. */ + vectno += 16; + + /* Set the AUX_IRQ_ACT. */ + if ((env->aux_irq_act & 0xffff) == 0) { + env->aux_irq_act |= env->stat.Uf << 31; + } + env->aux_irq_act |= 1 << priority; + + /* Set ICAUSE register. */ + env->icause[priority] = vectno; + + /* Do FIRQ if possible. */ + if (cpu->cfg.firq_option && priority == 0) { + arc_enter_firq(cpu, vectno); + } else { + arc_enter_irq(cpu, vectno); + } + + /* XX. The PC is set with the appropriate exception vector. */ + offset = vectno << 2; + env->pc = cpu_ldl_code(env, env->intvec + offset); + CPU_PCL(env) = env->pc & 0xfffffffe; + + qemu_log_mask(CPU_LOG_INT, "[IRQ] isr=0x%08x vec=0x%08x, priority=0x%04x\n", + env->pc, offset, priority); + + return true; +} + +/* To be called in the RTIE helper. */ + +bool arc_rtie_interrupts(CPUARCState *env) +{ + ARCCPU *cpu = env_archcpu(env); + + if (env->stat.AEf || ((env->aux_irq_act & 0xffff) == 0)) { + return false; + } + + /* FIXME! Reset RTC state. */ + + if ((env->aux_irq_act & 0xffff) == 1 && cpu->cfg.firq_option) { + arc_rtie_firq(env); + } else { + arc_rtie_irq(env); + } + return true; +} + +/* Switch between AUX USER SP and CPU's SP. */ +void switchSP(CPUARCState *env) +{ + uint32_t tmp; + qemu_log_mask(CPU_LOG_INT, + "[%s] swap: r28 = 0x%08x AUX_USER_SP = 0x%08x\n", + (env->aux_irq_act & 0xFFFF) ? "IRQ" : "EXCP", + CPU_SP(env), env->aux_user_sp); + + tmp = env->aux_user_sp; + env->aux_user_sp = CPU_SP(env); + CPU_SP(env) = tmp; + /* + * TODO: maybe we need to flush the tcg buffer to switch into + * kernel mode. + */ +} + +/* Reset the IRQ subsytem. */ +void arc_resetIRQ(ARCCPU *cpu) +{ + CPUARCState *env = &cpu->env; + uint32_t i; + + if (!cpu->cfg.has_interrupts) { + return; + } + + for (i = 0; i < (cpu->cfg.number_of_interrupts & 0xff); i++) { + env->irq_bank[16 + i].enable = 1; + } + + if (cpu->cfg.has_timer_0) { + /* FIXME! add build default timer0 priority. */ + env->irq_bank[16].priority = 0; + } + + if (cpu->cfg.has_timer_1) { + /* FIXME! add build default timer1 priority. */ + env->irq_bank[17].priority = 0; + } + + qemu_log_mask(CPU_LOG_RESET, "[IRQ] Reset the IRQ subsystem."); +} + +/* Initializing the IRQ subsystem. */ +void arc_initializeIRQ(ARCCPU *cpu) +{ + CPUARCState *env = &cpu->env; + uint32_t i; + + if (cpu->cfg.has_interrupts) { + /* FIXME! add N (NMI) bit. */ + env->irq_build = 0x01 | ((cpu->cfg.number_of_interrupts & 0xff) << 8) | + ((cpu->cfg.external_interrupts & 0xff) << 16) | + ((cpu->cfg.number_of_levels & 0x0f) << 24) | + (cpu->cfg.firq_option ? (1 << 28) : 0); + + for (i = 0; i < (cpu->cfg.number_of_interrupts & 0xff); i++) { + env->irq_bank[16 + i].enable = 1; + } + + env->vecbase_build = (cpu->cfg.intvbase_preset & (~0x3ffff)) + | (0x04 << 2); + env->intvec = cpu->cfg.intvbase_preset & (~0x3ffff); + } else { + env->irq_build = 0; + } +} diff --git a/target/arc/irq.h b/target/arc/irq.h new file mode 100644 index 0000000000..fac6f554d1 --- /dev/null +++ b/target/arc/irq.h @@ -0,0 +1,37 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synopsys Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#ifndef __IRQ_H__ +#define __IRQ_H__ + +#include "target/arc/regs.h" +#include "cpu.h" + +uint32_t aux_irq_get(const struct arc_aux_reg_detail *, void *); +void aux_irq_set(const struct arc_aux_reg_detail *, uint32_t, void *); +bool arc_cpu_exec_interrupt(CPUState *, int); +bool arc_rtie_interrupts(CPUARCState *); +void switchSP(CPUARCState *); +void arc_initializeIRQ(ARCCPU *); +void arc_resetIRQ(ARCCPU *); +uint32_t pack_status32(status_t *); +void unpack_status32(status_t *, uint32_t); + +#endif diff --git a/target/arc/timer.c b/target/arc/timer.c new file mode 100644 index 0000000000..3035f330e8 --- /dev/null +++ b/target/arc/timer.c @@ -0,0 +1,454 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synppsys Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#include "qemu/osdep.h" +#include "qemu/timer.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "hw/irq.h" +#include "hw/arc/cpudevs.h" +#include "timer.h" +#include "qemu/main-loop.h" + +#define TIMER_PERIOD(hz) (1000000000LL / (hz)) +#define TIMEOUT_LIMIT 1000000 + +#define T_PERIOD (TIMER_PERIOD(env->freq_hz)) +#define T_COUNT(T) \ + ((uint32_t) ((qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - \ + env->timer[T].last_clk) / T_PERIOD)) + +/* Update the next timeout time as difference between Count and Limit */ +static void cpu_arc_timer_update(CPUARCState *env, uint32_t timer) +{ + uint32_t delta; + uint32_t t_count = T_COUNT(timer); + uint64_t now = + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / T_PERIOD) * T_PERIOD; + uint32_t period = T_PERIOD; + + delta = env->timer[timer].T_Limit - t_count - 1; + + /* + * Artificially limit timeout rate to something achievable under + * QEMU. Otherwise, QEMU spends all its time generating timer + * interrupts, and there is no forward progress. About ten + * microseconds is the fastest that really works on the current + * generation of host machines. + */ + if ((delta * period) < TIMEOUT_LIMIT) { + delta = TIMEOUT_LIMIT / period; + } + + timer_mod(env->cpu_timer[timer], now + ((uint64_t)delta * period)); + + qemu_log_mask(LOG_UNIMP, + "[TMR%d] Timer update in 0x%08x - 0x%08x = 0x%08x "\ + "(ctrl:0x%08x @ %d Hz)\n", + timer, env->timer[timer].T_Limit, + t_count, delta, env->timer[timer].T_Cntrl, env->freq_hz); +} + +/* Expire the timer function. Rise an interrupt if required. */ + +static void cpu_arc_timer_expire(CPUARCState *env, uint32_t timer) +{ + assert(timer == 1 || timer == 0); + qemu_log_mask(LOG_UNIMP, "[TMR%d] Timer expired\n", timer); + + uint32_t overflow = env->timer[timer].T_Cntrl & TMR_IP; + /* Set the IP bit. */ + + bool unlocked = !qemu_mutex_iothread_locked(); + if (unlocked) { + qemu_mutex_lock_iothread(); + } + env->timer[timer].T_Cntrl |= TMR_IP; + env->timer[timer].last_clk = + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / T_PERIOD) * T_PERIOD; + if (unlocked) { + qemu_mutex_unlock_iothread(); + } + + /* Raise an interrupt if enabled. */ + if ((env->timer[timer].T_Cntrl & TMR_IE) && !overflow) { + qemu_log_mask(CPU_LOG_INT, "[TMR%d] Rising IRQ\n", timer); + qemu_irq_raise(env->irq[TIMER0_IRQ + (timer & 0x01)]); + } +} + +/* + * This callback should occur when the counter is exactly equal to the + * limit value. Offset the count by one to avoid immediately + * retriggering the callback before any virtual time has passed. + */ + +static void arc_timer0_cb(void *opaque) +{ + CPUARCState *env = (CPUARCState *) opaque; + + if (!(env->timer_build & TB_T0)) { + return; + } + + cpu_arc_timer_expire(env, 0); + cpu_arc_timer_update(env, 0); +} + +/* Like the above function but for TIMER1. */ +static void arc_timer1_cb(void *opaque) +{ + CPUARCState *env = (CPUARCState *) opaque; + + if (!(env->timer_build & TB_T1)) { + return; + } + + cpu_arc_timer_expire(env, 1); + cpu_arc_timer_update(env, 1); +} + +/* RTC counter update. */ +static void cpu_rtc_count_update(CPUARCState *env) +{ + uint64_t now; + uint64_t llreg; + + assert((env->timer_build & TB_RTC) && env->cpu_rtc); + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + + if (!(env->aux_rtc_ctrl & 0x01)) { + return; + } + + llreg = ((now - env->last_clk_rtc) / TIMER_PERIOD(env->freq_hz)); + llreg += env->aux_rtc_low + ((uint64_t)env->aux_rtc_high << 32); + env->aux_rtc_high = llreg >> 32; + env->aux_rtc_low = (uint32_t) llreg; + + env->last_clk_rtc = now; + qemu_log_mask(LOG_UNIMP, "[RTC] RTC count-regs update\n"); +} + +/* Update the next timeout time as difference between Count and Limit */ +static void cpu_rtc_update(CPUARCState *env) +{ + uint64_t wait = 0; + uint64_t now, next, period; + + assert(env->cpu_rtc); + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + + if (!(env->aux_rtc_ctrl & 0x01)) { + return; + } + + period = TIMER_PERIOD(env->freq_hz); + wait = UINT64_MAX - ((((uint64_t) env->aux_rtc_high) << 32) + + env->aux_rtc_low); + wait -= (now - env->last_clk_rtc) / period; + + /* Limit timeout rate. */ + if ((wait * period) < TIMEOUT_LIMIT) { + period = TIMEOUT_LIMIT / wait; + } + + next = now + (uint64_t) wait * period; + timer_mod(env->cpu_rtc, next); + qemu_log_mask(LOG_UNIMP, "[RTC] RTC update\n"); +} + +/* RTC call back routine. */ +static void arc_rtc_cb(void *opaque) +{ + CPUARCState *env = (CPUARCState *) opaque; + + if (!(env->timer_build & TB_RTC)) { + return; + } + + qemu_log_mask(LOG_UNIMP, "[RTC] RTC expired\n"); + + env->aux_rtc_high = 0; + env->aux_rtc_low = 0; + env->last_clk_rtc = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + cpu_rtc_update(env); +} + +/* Helper used when resetting the system. */ +static void cpu_arc_count_reset(CPUARCState *env, uint32_t timer) +{ + assert(timer == 0 || timer == 1); + env->timer[timer].T_Cntrl = 0; + env->timer[timer].T_Limit = 0x00ffffff; +} + +/* Get the counter value. */ +static uint32_t cpu_arc_count_get(CPUARCState *env, uint32_t timer) +{ + uint32_t count = T_COUNT(timer); + qemu_log_mask(LOG_UNIMP, "[TMR%d] Timer count %d.\n", timer, count); + return count; +} + +/* Set the counter value. */ +static void cpu_arc_count_set(CPUARCState *env, uint32_t timer, uint32_t val) +{ + assert(timer == 0 || timer == 1); + bool unlocked = !qemu_mutex_iothread_locked(); + if (unlocked) { + qemu_mutex_lock_iothread(); + } + env->timer[timer].last_clk = + ((qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / T_PERIOD) + val) * T_PERIOD; + if (unlocked) { + qemu_mutex_unlock_iothread(); + } + cpu_arc_timer_update(env, timer); +} + +/* Store the counter limit. */ +static void cpu_arc_store_limit(CPUARCState *env, + uint32_t timer, uint32_t value) +{ + switch (timer) { + case 0: + if (!(env->timer_build & TB_T0)) { + return; + } + break; + case 1: + if (!(env->timer_build & TB_T1)) { + return; + } + break; + default: + break; + } + env->timer[timer].T_Limit = value; + cpu_arc_timer_update(env, timer); +} + +/* Set the timer control bits. */ +static void cpu_arc_control_set(CPUARCState *env, + uint32_t timer, uint32_t value) +{ + assert(timer == 1 || timer == 0); + bool unlocked = !qemu_mutex_iothread_locked(); + if (unlocked) { + qemu_mutex_lock_iothread(); + } + if ((env->timer[timer].T_Cntrl & TMR_IP) && !(value & TMR_IP)) { + qemu_irq_lower(env->irq[TIMER0_IRQ + (timer)]); + } + env->timer[timer].T_Cntrl = value & 0x1f; + if (unlocked) { + qemu_mutex_unlock_iothread(); + } +} + +/* Get The RTC count value. */ +static uint32_t arc_rtc_count_get(CPUARCState *env, bool lower) +{ + cpu_rtc_count_update(env); + return lower ? env->aux_rtc_low : env->aux_rtc_high; +} + +/* Set the RTC control bits. */ +static void arc_rtc_ctrl_set(CPUARCState *env, uint32_t val) +{ + assert(env->stat.Uf == 0); + + if (val & 0x02) { + env->aux_rtc_low = 0; + env->aux_rtc_high = 0; + env->last_clk_rtc = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + } + if (!(val & 0x01)) { + timer_del(env->cpu_rtc); + } + + /* Restart RTC, update last clock. */ + if ((env->aux_rtc_ctrl & 0x01) == 0 && (val & 0x01)) { + env->last_clk_rtc = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + } + + env->aux_rtc_ctrl = 0xc0000000 | (val & 0x01); + cpu_rtc_update(env); +} + +/* Init procedure, called in platform. */ + +void +cpu_arc_clock_init(ARCCPU *cpu) +{ + CPUARCState *env = &cpu->env; + + if (env->timer_build & TB_T0) { + env->cpu_timer[0] = + timer_new_ns(QEMU_CLOCK_VIRTUAL, &arc_timer0_cb, env); + } + + if (env->timer_build & TB_T1) { + env->cpu_timer[1] = + timer_new_ns(QEMU_CLOCK_VIRTUAL, &arc_timer1_cb, env); + } + + if (env->timer_build & TB_RTC) { + env->cpu_rtc = + timer_new_ns(QEMU_CLOCK_VIRTUAL, &arc_rtc_cb, env); + } + + env->timer[0].last_clk = + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / T_PERIOD) * T_PERIOD; + env->timer[1].last_clk = + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / T_PERIOD) * T_PERIOD; +} + +void +arc_initializeTIMER(ARCCPU *cpu) +{ + CPUARCState *env = &cpu->env; + + /* FIXME! add default timer priorities. */ + env->timer_build = 0x04 | (cpu->cfg.has_timer_0 ? TB_T0 : 0) | + (cpu->cfg.has_timer_1 ? TB_T1 : 0) | + (cpu->cfg.rtc_option ? TB_RTC : 0); +} + +void +arc_resetTIMER(ARCCPU *cpu) +{ + CPUARCState *env = &cpu->env; + + if (env->timer_build & TB_T0) { + cpu_arc_count_reset(env, 0); + } + + if (env->timer_build & TB_T1) { + cpu_arc_count_reset(env, 1); + } +} + +/* Function implementation for reading/writing aux regs. */ +uint32_t +aux_timer_get(const struct arc_aux_reg_detail *aux_reg_detail, void *data) +{ + CPUARCState *env = (CPUARCState *) data; + + switch (aux_reg_detail->id) { + case AUX_ID_control0: + return env->timer[0].T_Cntrl; + break; + + case AUX_ID_control1: + return env->timer[1].T_Cntrl; + break; + + case AUX_ID_count0: + return cpu_arc_count_get(env, 0); + break; + + case AUX_ID_count1: + return cpu_arc_count_get(env, 1); + break; + + case AUX_ID_limit0: + return env->timer[0].T_Limit; + break; + + case AUX_ID_limit1: + return env->timer[1].T_Limit; + break; + + case AUX_ID_timer_build: + return env->timer_build; + break; + + case AUX_ID_aux_rtc_low: + return arc_rtc_count_get(env, true); + break; + + case AUX_ID_aux_rtc_high: + return arc_rtc_count_get(env, false); + break; + + case AUX_ID_aux_rtc_ctrl: + return env->aux_rtc_ctrl; + break; + + default: + break; + } + return 0; +} + +void aux_timer_set(const struct arc_aux_reg_detail *aux_reg_detail, + uint32_t val, void *data) +{ + CPUARCState *env = (CPUARCState *) data; + + qemu_log_mask(LOG_UNIMP, "[TMRx] AUX[%s] <= 0x%08x\n", + aux_reg_detail->name, val); + switch (aux_reg_detail->id) { + case AUX_ID_control0: + if (env->timer_build & TB_T0) { + cpu_arc_control_set(env, 0, val); + } + break; + + case AUX_ID_control1: + if (env->timer_build & TB_T1) { + cpu_arc_control_set(env, 1, val); + } + break; + + case AUX_ID_count0: + if (env->timer_build & TB_T0) { + cpu_arc_count_set(env, 0, val); + } + break; + + case AUX_ID_count1: + if (env->timer_build & TB_T1) { + cpu_arc_count_set(env, 1, val); + } + break; + + case AUX_ID_limit0: + cpu_arc_store_limit(env, 0, val); + break; + + case AUX_ID_limit1: + cpu_arc_store_limit(env, 1, val); + break; + + case AUX_ID_aux_rtc_ctrl: + arc_rtc_ctrl_set(env, val); + break; + + default: + break; + } +} + + +/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ +/* vim: set ts=4 sw=4 et: */ diff --git a/target/arc/timer.h b/target/arc/timer.h new file mode 100644 index 0000000000..9a7eeb892e --- /dev/null +++ b/target/arc/timer.h @@ -0,0 +1,30 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synppsys Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#ifndef __ARC_TIMER_H__ +#define __ARC_TIMER_H__ + +void arc_initializeTIMER(ARCCPU *); +void arc_resetTIMER(ARCCPU *); + +void aux_timer_set(const struct arc_aux_reg_detail *, uint32_t, void *); +uint32_t aux_timer_get(const struct arc_aux_reg_detail *, void *); + +#endif From patchwork Wed Nov 11 16:17:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cupertino Miranda X-Patchwork-Id: 1398391 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2001:8b0:10b:1231::1; helo=merlin.infradead.org; envelope-from=linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=merlin.20170209 header.b=eiEWmvcE; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=V9hJ4RhQ; dkim-atps=neutral Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:8b0:10b:1231::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CWVK444fhz9sRK for ; Thu, 12 Nov 2020 03:18:32 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=iLBrGBz6x2WXoU13NQS14Kq8A0AF/AyLChlLzN5k3Pk=; b=eiEWmvcEzJ/wQ7/XRNA/LgeZ8 IvEEKc0YBN8vKW+dLJFsxYPK8v0d3N4oqD4kzq88n3OyJidnzGh2xumHWAW8rC94Mu27aLVxmo9UU uU8qwW8bwq/n3RPggiAOjf4LZi1Jqt+vY3X694qSMpPdg2ZIcvTuDK9wW9MzczRHpUYnGim0SLQx4 fee1mrITEGPSFG54vNOOI/EssuDAYBL5mTrXrlJFmAPIFXJFEaHcF4nFFdTj9gIdOkXw6ll+zZIpX idr3YIAyd13kS38uYBlgar7f9yk2wVSt/yK3b2pYeCMuJM0EMMm/7TuiXCzydRsfMp1t7f/b/lWc7 UNM2Lk5xQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kcspJ-0003h1-66; Wed, 11 Nov 2020 16:18:29 +0000 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kcsp8-0003cq-QK for linux-snps-arc@lists.infradead.org; Wed, 11 Nov 2020 16:18:26 +0000 Received: by mail-wr1-x444.google.com with SMTP id b6so3092662wrt.4 for ; Wed, 11 Nov 2020 08:18:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0dH6iTiEiDaNoVcjOK9D9d222s0bNd7S/gGGqMEYyFE=; b=V9hJ4RhQdkFJZd0BfiZKdKHcw4a9wKTD+qt3RJdxmr8FZdBliBHCfYRUnHuMfEztf2 AVarpDwo/VjsZCgmizmWvEvdZuViNjYgoZ3JVm4T4WRvl7Vtk4ZJWBgZj2DxmL6SzJ6x 66ymR+p8qZYcSTP/X/MP2wnwMothRJcHS8fivfvXbwGG251bLgdk2bEpxNUZtfGDxD6U tKTsZ20efZDK6UzyObMlteqqWu7Mel7d4OpduSk94DLgulnbpuWFX53MIcvycSg/je2R 9wgIye1jB9cXpkIcC9gd3FSDZML5SjUEurQC0ytdmZ1fbuZ8JSnJOhSJeIMnotuAmesy gd2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0dH6iTiEiDaNoVcjOK9D9d222s0bNd7S/gGGqMEYyFE=; b=av+6ORUhCwKMUDr2RvLrPpGACZaAloxN0zoPtyZWa4qzEo6QHcQyqnHxabp2Pakul1 xTQXbp/y3C2SnSJsYA1cvhWlj2rV2ZJv80wPvKvQozq8cWAhMaPcxSAbi+AphmselX3Z 7XbVi23L/wf8DOdQ26cri2rdjaTi2Hh/F0SujqfzuRITyyfracZhZXhvunFYPj9kOol9 MjNdBHXogutVHBWBhWGFxA3O3xSuDMAMoS9IgU8ajeVByHLRv3ZAqO2STfILIzojEsOG sXbpW0mTHVRJtK7l5pBcp7R7h413XztLZ1dXgtvnz+2lJX017UdZI1JyXY7SNHpD+KHI ivrw== X-Gm-Message-State: AOAM533o5XSw706q18lbP3LGfc4jROnLQ7sFQ2FEhL2uY5Pm6fJyzRPl 7F5VweQ3fjQoeZ3uVbzxqxg= X-Google-Smtp-Source: ABdhPJwu9Aj8Sh1SZJHfOth73U6AOQtU02QtB5FI99Uup8lLi6aF41ih343QGw+9G6X6brfwtPl22w== X-Received: by 2002:adf:ead0:: with SMTP id o16mr32612013wrn.292.1605111497519; Wed, 11 Nov 2020 08:18:17 -0800 (PST) Received: from cmiranda-laptop.localdomain (bl19-104-46.dsl.telepac.pt. [2.80.104.46]) by smtp.gmail.com with ESMTPSA id s188sm3115178wmf.45.2020.11.11.08.18.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2020 08:18:17 -0800 (PST) From: cupertinomiranda@gmail.com To: qemu-devel@nongnu.org Subject: [PATCH 09/15] arc: Add memory management unit (MMU) support Date: Wed, 11 Nov 2020 16:17:52 +0000 Message-Id: <20201111161758.9636-10-cupertinomiranda@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201111161758.9636-1-cupertinomiranda@gmail.com> References: <20201111161758.9636-1-cupertinomiranda@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201111_111819_027304_55A293C0 X-CRM114-Status: GOOD ( 25.62 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:444 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [cupertinomiranda[at]gmail.com] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Claudiu Zissulescu , Cupertino Miranda , Shahab Vahedi , Shahab Vahedi , Cupertino Miranda , linux-snps-arc@lists.infradead.org, Claudiu Zissulescu Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Cupertino Miranda Add Synopsys ARC MMU version 4 support. The implementation is restricted to 8K page size support. Signed-off-by: Cupertino Miranda --- target/arc/mmu.c | 777 +++++++++++++++++++++++++++++++++++++++++++++++ target/arc/mmu.h | 166 ++++++++++ 2 files changed, 943 insertions(+) create mode 100644 target/arc/mmu.c create mode 100644 target/arc/mmu.h diff --git a/target/arc/mmu.c b/target/arc/mmu.c new file mode 100644 index 0000000000..3d50489b15 --- /dev/null +++ b/target/arc/mmu.c @@ -0,0 +1,777 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synppsys Inc. + * Contributed by Cupertino Miranda + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#include "qemu/osdep.h" +#include "mmu.h" +#include "target/arc/regs.h" +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" + + +uint32_t +arc_mmu_aux_get(const struct arc_aux_reg_detail *aux_reg_detail, void *data) +{ + CPUARCState *env = (CPUARCState *) data; + struct arc_mmu *mmu = &env->mmu; + uint32_t reg = 0; + + switch (aux_reg_detail->id) { + case AUX_ID_mmu_build: + /* + * For now hardcode the TLB geometry and canonical page sizes + * MMUv4: 2M Super Page, 8k Page, 4 way set associative, + * 1K entries (256x4), 4 uITLB, 8 uDTLB + */ + reg = 0x04e21a4a; + break; + case AUX_ID_tlbindex: + reg = mmu->tlbindex; + break; + case AUX_ID_tlbpd0: + reg = mmu->tlbpd0; + break; + case AUX_ID_tlbpd1: + reg = mmu->tlbpd1; + break; + case AUX_ID_tlbpd1_hi: + reg = mmu->tlbpd1_hi; + break; + case AUX_ID_scratch_data0: + reg = mmu->scratch_data0; + break; + case AUX_ID_tlbcommand: + reg = mmu->tlbcmd; + break; + case AUX_ID_pid: + reg = (mmu->enabled << 31) | mmu->pid_asid; + break; + case AUX_ID_sasid0: + reg = mmu->sasid0; + break; + case AUX_ID_sasid1: + reg = mmu->sasid1; + break; + default: + break; + } + + return reg; +} + +void +arc_mmu_aux_set(const struct arc_aux_reg_detail *aux_reg_detail, + uint32_t val, void *data) +{ + CPUARCState *env = (CPUARCState *) data; + CPUState *cs = env_cpu(env); + struct arc_mmu *mmu = &env->mmu; + + switch (aux_reg_detail->id) { + /* AUX_ID_tlbcommand is more involved and handled seperately */ + case AUX_ID_tlbindex: + mmu->tlbindex = val; + break; + case AUX_ID_tlbpd0: + mmu->tlbpd0 = val; + break; + case AUX_ID_tlbpd1: + mmu->tlbpd1 = val; + break; + case AUX_ID_tlbpd1_hi: + mmu->tlbpd1_hi = val; + break; + case AUX_ID_scratch_data0: + mmu->scratch_data0 = val; + break; + case AUX_ID_pid: + qemu_log_mask(CPU_LOG_MMU, + "[MMU] Writing PID_ASID with value 0x%08x at 0x%08x\n", + val, env->pc); + mmu->enabled = (val >> 31); + mmu->pid_asid = val & 0xff; + tlb_flush(cs); + break; + case AUX_ID_sasid0: + mmu->sasid0 = val; + break; + case AUX_ID_sasid1: + mmu->sasid1 = val; + break; + default: + break; + } +} + +/* vaddr can't have top bit */ +#define VPN(addr) ((addr) & (PAGE_MASK & (~0x80000000))) +#define PFN(addr) ((addr) & PAGE_MASK) + +static void +arc_mmu_debug_tlb_for_set(CPUARCState *env, int set) +{ + int j; + bool set_printed = false; + + for (j = 0; j < N_WAYS; j++) { + struct arc_tlb_e *tlb = &env->mmu.nTLB[set][j]; + + if ((tlb->pd0 & PD0_V) != 0) { + if (set_printed == false) { + printf("set %d\n", set); + set_printed = true; + } + if (set_printed == true) { + printf(" way %d\n", j); + } + printf(" tlppd0: %08x: vaddr=\t%08x %s %s%s asid=%02x\n", + (unsigned int) tlb->pd0, (unsigned int) VPN(tlb->pd0), + (char *) ((tlb->pd0 & PD0_SZ) != 0 ? "sz1" : "sz0"), + (char *) ((tlb->pd0 & PD0_V) != 0 ? "V" : ""), + (char *) ((tlb->pd0 & PD0_G) != 0 ? "g" : ""), + tlb->pd0 & PD0_ASID); + + printf(" tlppd1: %08x: paddr=\t%08x k:%s%s%s u:%s%s%s f:%s\n", + (unsigned int) tlb->pd1, (unsigned int) PFN(tlb->pd1), + (char *) ((tlb->pd1 & PD1_RK) != 0 ? "R" : "r"), + (char *) ((tlb->pd1 & PD1_WK) != 0 ? "W" : "w"), + (char *) ((tlb->pd1 & PD1_XK) != 0 ? "X" : "x"), + (char *) ((tlb->pd1 & PD1_RU) != 0 ? "R" : "r"), + (char *) ((tlb->pd1 & PD1_WU) != 0 ? "W" : "w"), + (char *) ((tlb->pd1 & PD1_XU) != 0 ? "X" : "x"), + (char *) ((tlb->pd1 & PD1_FC) != 0 ? "C" : "c")); + } + } +} + +void +arc_mmu_debug_tlb(CPUARCState *env) +{ + int i; + + for (i = 0; i < N_SETS; i++) { + arc_mmu_debug_tlb_for_set(env, i); + } +} + +void +arc_mmu_debug_tlb_for_vaddr(CPUARCState *env, uint32_t vaddr) +{ + uint32_t set = (vaddr >> PAGE_SHIFT) & (N_SETS - 1); + arc_mmu_debug_tlb_for_set(env, set); +} + + +static struct arc_tlb_e * +arc_mmu_get_tlb_at_index(uint32_t index, struct arc_mmu *mmu) +{ + uint32_t set = index / N_WAYS; + uint32_t bank = index % N_WAYS; + return &mmu->nTLB[set][bank]; +} + +static inline bool +match_sasid(struct arc_tlb_e *tlb, struct arc_mmu *mmu) +{ + /* Match to a shared library. */ + uint8_t position = tlb->pd0 & PD0_ASID_MATCH; + uint64_t pos = 1ULL << position; + uint64_t sasid = ((uint64_t) mmu->sasid1 << 32) | mmu->sasid0; + if ((pos & sasid) == 0) { + return false; + } + return true; +} + +static struct arc_tlb_e * +arc_mmu_lookup_tlb(uint32_t vaddr, uint32_t compare_mask, struct arc_mmu *mmu, + int *num_finds, uint32_t *index) +{ + struct arc_tlb_e *ret = NULL; + uint32_t set = (vaddr >> PAGE_SHIFT) & (N_SETS - 1); + struct arc_tlb_e *tlb = &mmu->nTLB[set][0]; + int w; + + if (num_finds != NULL) { + *num_finds = 0; + } + + bool general_match = true; + for (w = 0; w < N_WAYS; w++, tlb++) { + uint32_t match = vaddr & compare_mask; + uint32_t final_compare_mask = compare_mask; + + if ((tlb->pd0 & PD0_G) == 0) { + if ((tlb->pd0 & PD0_S) != 0) { + /* Match to a shared library. */ + if (match_sasid(tlb, mmu) == false) { + general_match = false; + } + } else { + /* Match to a process. */ + match |= mmu->pid_asid & PD0_PID_MATCH; + final_compare_mask |= PD0_PID_MATCH; + } + } + + if (match == (tlb->pd0 & final_compare_mask) && general_match) { + ret = tlb; + if (num_finds != NULL) { + *num_finds += 1; + } + if (index != NULL) { + *index = (set * N_WAYS) + w; + } + } + } + + if (ret == NULL) { + uint32_t way = mmu->way_sel[set]; + ret = &mmu->nTLB[set][way]; + + /* TODO: Replace by something more significant. */ + if (index != NULL) { + *index = (set * N_WAYS) + way; + } + + mmu->way_sel[set] = (mmu->way_sel[set] + 1) & (N_WAYS - 1); + } + + return ret; +} + +/* + * TLB Insert/Delete triggered by writing the cmd to TLBCommand Aux + * - Requires PD0 and PD1 be setup apriori + */ +void +arc_mmu_aux_set_tlbcmd(const struct arc_aux_reg_detail *aux_reg_detail, + uint32_t val, void *data) +{ + CPUARCState *env = (CPUARCState *) data; + CPUState *cs = env_cpu(env); + struct arc_mmu *mmu = &env->mmu; + uint32_t pd0 = mmu->tlbpd0; + uint32_t pd1 = mmu->tlbpd1; + int num_finds = 4; + uint32_t index; + struct arc_tlb_e *tlb; + + mmu->tlbcmd = val; + uint32_t matching_mask = (PD0_VPN | PD0_SZ | PD0_G | PD0_S | PD0_ASID); + + if ((pd0 & PD0_G) != 0) { + /* + * When Global do not check for asid match. + */ + matching_mask &= ~(PD0_S | PD0_ASID); + } + + /* + * NOTE: Write and WriteNI commands are the same because we do not model + * uTLBs in QEMU. + */ + if (val == TLB_CMD_WRITE || val == TLB_CMD_WRITENI) { + /* + * TODO: Include index verification. We are always clearing the index as + * we assume it is always valid. + */ + tlb = arc_mmu_get_tlb_at_index(mmu->tlbindex & TLBINDEX_INDEX, mmu); + tlb->pd0 = mmu->tlbpd0; + tlb->pd1 = mmu->tlbpd1; + } + if (val == TLB_CMD_READ) { + /* + * TODO: Include index verification. We are always clearing the index as + * we assume it is always valid. + */ + + tlb = arc_mmu_get_tlb_at_index(mmu->tlbindex & TLBINDEX_INDEX, mmu); + mmu->tlbpd0 = tlb->pd0; + mmu->tlbpd1 = tlb->pd1; + + mmu->tlbindex &= ~(TLBINDEX_E | TLBINDEX_RC); + } + if (val == TLB_CMD_DELETE || val == TLB_CMD_INSERT) { + tlb_flush_page_by_mmuidx(cs, VPN(pd0), 3); + + if ((pd0 & PD0_G) != 0) { + /* + * When Global do not check for asid match. + */ + matching_mask &= ~(PD0_S | PD0_ASID); + } + + matching_mask &= (VPN(PD0_VPN) | (~PD0_VPN)) ; + tlb = arc_mmu_lookup_tlb(pd0, + matching_mask | PD0_V, + &env->mmu, &num_finds, &index); + + if (num_finds == 0) { + mmu->tlbindex = 0x80000000; /* No entry to delete */ + } else if (num_finds == 1) { + mmu->tlbindex = index; /* Entry is deleted set index */ + tlb->pd0 &= ~PD0_V; + num_finds--; + qemu_log_mask(CPU_LOG_MMU, + "[MMU] Delete at 0x%08x, pd0 = 0x%08x, pd1 = 0x%08x\n", + env->pc, tlb->pd0, tlb->pd1); + } else { + while (num_finds > 0) { + tlb->pd0 &= ~PD0_V; + qemu_log_mask(CPU_LOG_MMU, + "[MMU] Delete at 0x%08x, pd0 = 0x%08x, pd1 = 0x%08x\n", + env->pc, tlb->pd0, tlb->pd1); + tlb = arc_mmu_lookup_tlb(pd0, + (VPN(PD0_VPN) | PD0_V + | PD0_SZ | PD0_G | PD0_S), + mmu, &num_finds, NULL); + } + } + } + + if (val == TLB_CMD_INSERT) { + if ((pd0 & PD0_V) == 0) { + mmu->tlbindex = 0x80000000; + } else { + tlb->pd0 = pd0; + tlb->pd1 = pd1; + + /* Set index for latest inserted element. */ + mmu->tlbindex |= index; + + /* TODO: More verifications needed. */ + + qemu_log_mask(CPU_LOG_MMU, + "[MMU] Insert at 0x%08x, PID = %d, VPN = 0x%08x, " + "PFN = 0x%08x, pd0 = 0x%08x, pd1 = 0x%08x\n", + env->pc, + pd0 & 0xff, + VPN(pd0), PFN(pd1), + pd0, pd1); + } + } + + /* NOTE: We do not implement IVUTLB as we do not model uTLBs. */ + assert(val == TLB_CMD_INSERT + || val == TLB_CMD_DELETE + || val == TLB_CMD_WRITE + || val == TLB_CMD_READ + || val == TLB_CMD_WRITENI + || val == TLB_CMD_IVUTLB + ); +} + +/* Function to verify if we have permission to use MMU TLB entry. */ +static bool +arc_mmu_have_permission(CPUARCState *env, + struct arc_tlb_e *tlb, + enum mmu_access_type type) +{ + bool ret = false; + bool in_kernel_mode = !env->stat.Uf; /* Read status for user mode. */ + switch (type) { + case MMU_MEM_READ: + ret = in_kernel_mode ? tlb->pd1 & PD1_RK : tlb->pd1 & PD1_RU; + break; + case MMU_MEM_WRITE: + ret = in_kernel_mode ? tlb->pd1 & PD1_WK : tlb->pd1 & PD1_WU; + break; + case MMU_MEM_FETCH: + ret = in_kernel_mode ? tlb->pd1 & PD1_XK : tlb->pd1 & PD1_XU; + break; + case MMU_MEM_ATTOMIC: + ret = in_kernel_mode ? tlb->pd1 & PD1_RK : tlb->pd1 & PD1_RU; + ret = ret & (in_kernel_mode ? tlb->pd1 & PD1_WK : tlb->pd1 & PD1_WU); + break; + case MMU_MEM_IRRELEVANT_TYPE: + ret = true; + break; + } + + return ret; +} + +#define SET_MMU_EXCEPTION(ENV, N, C, P) { \ + ENV->mmu.exception.number = N; \ + ENV->mmu.exception.causecode = C; \ + ENV->mmu.exception.parameter = P; \ +} + +/* Translation function to get physical address from virtual address. */ +uint32_t +arc_mmu_translate(struct CPUARCState *env, + uint32_t vaddr, enum mmu_access_type rwe, + uint32_t *index) +{ + struct arc_mmu *mmu = &(env->mmu); + struct arc_tlb_e *tlb = NULL; + int num_matching_tlb = 0; + + SET_MMU_EXCEPTION(env, EXCP_NO_EXCEPTION, 0, 0); + + if (rwe != MMU_MEM_IRRELEVANT_TYPE + && env->stat.Uf != 0 && vaddr >= 0x80000000) { + goto protv_exception; + } + + /* + * Check that we are not addressing an address above 0x80000000. + * Return the same address in that case. + */ + if ((vaddr >= 0x80000000) || mmu->enabled == false) { + return vaddr; + } + + if (rwe != MMU_MEM_IRRELEVANT_TYPE) { + qemu_log_mask(CPU_LOG_MMU, + "[MMU] Translate at 0x%08x, vaddr 0x%08x, pid %d, rwe = %s\n", + env->pc, vaddr, mmu->pid_asid, RWE_STRING(rwe)); + } + + uint32_t match_pd0 = (VPN(vaddr) | PD0_V); + tlb = arc_mmu_lookup_tlb(match_pd0, (VPN(PD0_VPN) | PD0_V), mmu, + &num_matching_tlb, index); + + /* + * Check for multiple matches in nTLB, and return machine check + * exception. + */ + if (num_matching_tlb > 1) { + qemu_log_mask(CPU_LOG_MMU, + "[MMU] Machine Check exception. num_matching_tlb = %d\n", + num_matching_tlb); + SET_MMU_EXCEPTION(env, EXCP_MACHINE_CHECK, 0x01, 0x00); + return 0; + } + + + bool match = true; + + if (num_matching_tlb == 0) { + match = false; + } + + /* Check if entry if related to this address */ + if (VPN(vaddr) != VPN(tlb->pd0) || (tlb->pd0 & PD0_V) == 0) { + /* Call the interrupt. */ + match = false; + } + + if (match == true) { + if ((tlb->pd0 & PD0_G) == 0) { + if ((tlb->pd0 & PD0_S) != 0) { + /* Match to a shared library. */ + if (match_sasid(tlb, mmu) == false) { + match = false; + } + } else if ((tlb->pd0 & PD0_PID_MATCH) != + (mmu->pid_asid & PD0_PID_MATCH)) { + /* Match to a process. */ + match = false; + } + } + } + + if (match == true && !arc_mmu_have_permission(env, tlb, rwe)) { + protv_exception: + qemu_log_mask(CPU_LOG_MMU, + "[MMU] ProtV exception at 0x%08x for 0x%08x. rwe = %s, " + "tlb->pd0 = %08x, tlb->pd1 = %08x\n", + env->pc, + vaddr, + RWE_STRING(rwe), + tlb->pd0, tlb->pd1); + + SET_MMU_EXCEPTION(env, EXCP_PROTV, CAUSE_CODE(rwe), 0x08); + return 0; + } + + if (match == true) { + if (rwe != MMU_MEM_IRRELEVANT_TYPE) { + qemu_log_mask(CPU_LOG_MMU, + "[MMU] Translated to 0x%08x, pd0=0x%08x, pd1=0x%08x\n", + (tlb->pd1 & PAGE_MASK) | (vaddr & (~PAGE_MASK)), + tlb->pd0, tlb->pd1); + } + return (tlb->pd1 & PAGE_MASK) | (vaddr & (~PAGE_MASK)); + } else { + if (rwe != MMU_MEM_IRRELEVANT_TYPE) { + /* To remove eventually, just fail safe to check kernel. */ + if (mmu->sasid0 != 0 || mmu->sasid1 != 0) { + assert(0); + } else { + mmu->tlbpd0 = (vaddr & (VPN(PD0_VPN))) + | PD0_V | (mmu->pid_asid & PD0_ASID); + } + if (rwe == MMU_MEM_FETCH) { + qemu_log_mask(CPU_LOG_MMU, + "[MMU] TLB_MissI exception at 0x%08x. rwe = %s, " + "vaddr = %08x, tlb->pd0 = %08x, tlb->pd1 = %08x\n", + env->pc, + RWE_STRING(rwe), + vaddr, tlb->pd0, tlb->pd1); + SET_MMU_EXCEPTION(env, EXCP_TLB_MISS_I, 0x00, 0x00); + } else { + qemu_log_mask(CPU_LOG_MMU, + "[MMU] TLB_MissD exception at 0x%08x. rwe = %s, " + "vaddr = %08x, tlb->pd0 = %08x, tlb->pd1 = %08x\n", + env->pc, + RWE_STRING(rwe), + vaddr, tlb->pd0, tlb->pd1); + SET_MMU_EXCEPTION(env, EXCP_TLB_MISS_D, CAUSE_CODE(rwe), + 0x00); + } + } else if (rwe != MMU_MEM_IRRELEVANT_TYPE) { + qemu_log_mask(CPU_LOG_MMU, + "[MMU] Failed to translate to 0x%08x\n", + vaddr); + } + return 0; + } +} + +uint32_t arc_mmu_page_address_for(uint32_t vaddr) +{ + uint32_t ret = VPN(vaddr); + if (vaddr >= 0x80000000) { + ret |= 0x80000000; + } + return ret; +} + +void arc_mmu_init(struct arc_mmu *mmu) +{ + mmu->enabled = 0; + mmu->pid_asid = 0; + mmu->sasid0 = 0; + mmu->sasid1 = 0; + + mmu->tlbpd0 = 0; + mmu->tlbpd1 = 0; + mmu->tlbpd1_hi = 0; + mmu->tlbindex = 0; + mmu->tlbcmd = 0; + mmu->scratch_data0 = 0; + + memset(mmu->nTLB, 0, sizeof(mmu->nTLB)); +} + +static int +arc_mmu_get_prot_for_index(uint32_t index, CPUARCState *env) +{ + struct arc_tlb_e *tlb; + int ret = 0; + bool in_kernel_mode = !env->stat.Uf; /* Read status for user mode. */ + + tlb = arc_mmu_get_tlb_at_index( + index, + &env->mmu); + + if ((in_kernel_mode && (tlb->pd1 & PD1_RK) != 0) + || (!in_kernel_mode && (tlb->pd1 & PD1_RU) != 0)) { + ret |= PAGE_READ; + } + + if ((in_kernel_mode && (tlb->pd1 & PD1_WK) != 0) + || (!in_kernel_mode && (tlb->pd1 & PD1_WU) != 0)) { + ret |= PAGE_WRITE; + } + + if ((in_kernel_mode && (tlb->pd1 & PD1_XK) != 0) + || (!in_kernel_mode && (tlb->pd1 & PD1_XU) != 0)) { + ret |= PAGE_EXEC; + } + + return ret; +} + +static void QEMU_NORETURN raise_mem_exception( + CPUState *cs, target_ulong addr, uintptr_t host_pc, + int32_t excp_idx, uint8_t excp_cause_code, uint8_t excp_param) +{ + CPUARCState *env = &(ARC_CPU(cs)->env); + if (excp_idx != EXCP_TLB_MISS_I) { + cpu_restore_state(cs, host_pc, true); + } + + env->efa = addr; + env->eret = env->pc; + env->erbta = env->bta; + + cs->exception_index = excp_idx; + env->causecode = excp_cause_code; + env->param = excp_param; + cpu_loop_exit(cs); +} + +/* MMU range */ +static const uint32_t MMU_VA_START = 0x00000000; /* inclusive */ +static const uint32_t MMU_VA_END = 0x80000000; /* exclusive */ + +typedef enum { + DIRECT_ACTION, + MPU_ACTION, + MMU_ACTION, + EXCEPTION_ACTION +} ACTION; + +/* + * Applying the following logic + * ,-----.-----.-----------.---------.---------------. + * | MMU | MPU | MMU range | mmu_idx | action | + * |-----+-----+-----------+---------+---------------| + * | dis | dis | x | x | phys = virt | + * |-----+-----+-----------+---------+---------------| + * | dis | ena | x | x | mpu_translate | + * |-----+-----+-----------+---------+---------------| + * | ena | dis | true | x | mmu_translate | + * |-----+-----+-----------+---------+---------------| + * | ena | dis | false | 0 | phys = virt | + * |-----+-----+-----------+---------+---------------| + * | ena | dis | false | 1 | exception | + * |-----+-----+-----------+---------+---------------| + * | ena | ena | false | x | mpu_translate | + * |-----+-----+-----------+---------+---------------| + * | ena | ena | true | x | mmu_translate | + * `-----^-----^-----------^---------^---------------' + */ +static int decide_action(const CPUARCState *env, + target_ulong addr, + int mmu_idx) +{ + static ACTION table[2][2][2][2] = { }; + static bool is_initialized = false; + const bool is_user = (mmu_idx == 1); + const bool is_mmu_range = ((addr >= MMU_VA_START) && (addr < MMU_VA_END)); + + if (!is_initialized) { + /* Both MMU and MPU disabled */ +#define T true +#define F false + + table[F][F][F][F] = DIRECT_ACTION; + table[F][F][F][T] = DIRECT_ACTION; + table[F][F][T][F] = DIRECT_ACTION; + table[F][F][T][T] = DIRECT_ACTION; + + /* Only MPU */ + table[F][T][F][F] = MPU_ACTION; + table[F][T][F][T] = MPU_ACTION; + table[F][T][T][F] = MPU_ACTION; + table[F][T][T][T] = MPU_ACTION; + + /* Only MMU; non-mmu range; kernel access */ + table[T][F][F][F] = DIRECT_ACTION; + /* Only MMU; non-mmu range; user access */ + table[T][F][F][T] = EXCEPTION_ACTION; + + /* Only MMU; mmu range; both modes access */ + table[T][F][T][F] = MMU_ACTION; + table[T][F][T][T] = MMU_ACTION; + + /* Both MMU and MPU enabled; non-mmu range */ + table[T][T][F][F] = MPU_ACTION; + table[T][T][F][T] = MPU_ACTION; + + /* Both MMU and MPU enabled; mmu range */ + table[T][T][T][F] = MMU_ACTION; + table[T][T][T][T] = MMU_ACTION; + +#undef T +#undef F + + is_initialized = true; + } + + return table[env->mmu.enabled][env->mpu.enabled][is_mmu_range][is_user]; +} + + +#ifndef CONFIG_USER_ONLY +/* Softmmu support function for MMU. */ +bool arc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + /* TODO: this rwe should go away when the TODO below is done */ + enum mmu_access_type rwe = (char) access_type; + CPUARCState *env = &((ARC_CPU(cs))->env); + int action = decide_action(env, address, mmu_idx); + + switch (action) { + case DIRECT_ACTION: + tlb_set_page(cs, address & PAGE_MASK, address & PAGE_MASK, + PAGE_READ | PAGE_WRITE | PAGE_EXEC, + mmu_idx, TARGET_PAGE_SIZE); + break; + case MPU_ACTION: + if (arc_mpu_translate(env, address, access_type, mmu_idx)) { + if (probe) { + return false; + } + MPUException *mpu_excp = &env->mpu.exception; + raise_mem_exception(cs, address, retaddr, + mpu_excp->number, mpu_excp->code, mpu_excp->param); + } + break; + case MMU_ACTION: { + /* + * TODO: these lines must go inside arc_mmu_translate and it + * should only signal a failure or success --> generate an + * exception or not + */ + uint32_t index; + target_ulong paddr = arc_mmu_translate(env, address, rwe, &index); + if ((enum exception_code_list) env->mmu.exception.number != + EXCP_NO_EXCEPTION) { + if (probe) { + return false; + } + const struct mmu_exception *mmu_excp = &env->mmu.exception; + raise_mem_exception(cs, address, retaddr, + mmu_excp->number, mmu_excp->causecode, mmu_excp->parameter); + } else { + int prot = arc_mmu_get_prot_for_index(index, env); + address = arc_mmu_page_address_for(address); + tlb_set_page(cs, address, paddr & PAGE_MASK, prot, + mmu_idx, TARGET_PAGE_SIZE); + } + break; + } + case EXCEPTION_ACTION: + if (probe) { + return false; + } + /* TODO: like TODO above, this must move inside mmu */ + qemu_log_mask(CPU_LOG_MMU, "[MMU_TLB_FILL] ProtV " + "exception at 0x%08x. rwe = %s\n", + env->pc, RWE_STRING(rwe)); + raise_mem_exception(cs, address, retaddr, + EXCP_PROTV, CAUSE_CODE(rwe), 0x08); + break; + default: + g_assert_not_reached(); + } + + return true; +} +#endif /* ifndef CONFIG_USER_ONLY */ diff --git a/target/arc/mmu.h b/target/arc/mmu.h new file mode 100644 index 0000000000..0afc9af3eb --- /dev/null +++ b/target/arc/mmu.h @@ -0,0 +1,166 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synppsys Inc. + * Contributed by Cupertino Miranda + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#ifndef ARC_MMU_H +#define ARC_MMU_H + +#include "target/arc/regs.h" + +/* PD0 flags */ +#define PD0_VPN 0x7ffff000 +#define PD0_ASID 0x000000ff +#define PD0_G 0x00000100 /* Global */ +#define PD0_V 0x00000200 /* Valid */ +#define PD0_SZ 0x00000400 /* Size: Normal or Super Page */ +#define PD0_L 0x00000800 /* Lock */ +#define PD0_S 0x80000000 /* Shared Library ASID */ +#define PD0_FLG (PD0_G | PD0_V | PD0_SZ | PD0_L) + +#define PD0_ASID_MATCH 0x0000003f +#define PD0_PID_MATCH 0x000000ff + +/* PD1 permission bits */ +#define PD1_PPN 0xfffff000 /* Cached */ +#define PD1_FC 0x00000001 /* Cached */ +#define PD1_XU 0x00000002 /* User Execute */ +#define PD1_WU 0x00000004 /* User Write */ +#define PD1_RU 0x00000008 /* User Read */ +#define PD1_XK 0x00000010 /* Kernel Execute */ +#define PD1_WK 0x00000020 /* Kernel Write */ +#define PD1_RK 0x00000040 /* Kernel Read */ +#define PD1_FLG (PD1_FC | PD1_XU | PD1_WU | PD1_RU | PD1_XK | PD1_WK | PD1_RK) + +#define TLBINDEX_INDEX 0x00001fff +#define TLBINDEX_E 0x80000000 +#define TLBINDEX_RC 0x70000000 + +#define TLB_CMD_WRITE 0x1 +#define TLB_CMD_WRITENI 0x5 +#define TLB_CMD_READ 0x2 +#define TLB_CMD_INSERT 0x7 +#define TLB_CMD_DELETE 0x8 +#define TLB_CMD_IVUTLB 0x6 + +#define N_SETS 256 +#define N_WAYS 4 +#define TLB_ENTRIES (N_SETS * N_WAYS) + +#define PAGE_SHIFT TARGET_PAGE_BITS +#define PAGE_SIZE (1 << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE - 1)) + +/* NOTE: Do not reorder, this is casted in tbl_fill function. */ +enum mmu_access_type { + MMU_MEM_READ = 0, + MMU_MEM_WRITE, + MMU_MEM_FETCH, /* Read for execution. */ + MMU_MEM_ATTOMIC, + MMU_MEM_IRRELEVANT_TYPE, +}; + +#define RWE_STRING(RWE) \ + (RWE == MMU_MEM_READ ? "MEM_READ" : \ + (RWE == MMU_MEM_WRITE ? "MEM_WRITE" : \ + (RWE == MMU_MEM_ATTOMIC ? "MEM_ATTOMIC" : \ + (RWE == MMU_MEM_FETCH ? "MEM_FETCH" : \ + (RWE == MMU_MEM_IRRELEVANT_TYPE ? "MEM_IRRELEVANT" \ + : "NOT_VALID_RWE"))))) + + +#define CAUSE_CODE(ENUM) \ + ((ENUM == MMU_MEM_FETCH) ? 0 : \ + ((ENUM == MMU_MEM_READ) ? 1 : \ + ((ENUM == MMU_MEM_WRITE) ? 2 : 3))) + + +struct arc_tlb_e { + /* + * TLB entry is {PD0,PD1} tuple, kept "unpacked" to avoid bit fiddling + * flags includes both PD0 flags and PD1 permissions. + */ + uint32_t pd0, pd1; +}; + +#define RAISE_MMU_EXCEPTION(ENV) { \ + do_exception_no_delayslot(ENV, \ + ENV->mmu.exception.number, \ + ENV->mmu.exception.causecode, \ + ENV->mmu.exception.parameter); \ +} + +struct arc_mmu { + uint32_t enabled; + struct mmu_exception { + int32_t number; + uint8_t causecode; + uint8_t parameter; + } exception; + + struct arc_tlb_e nTLB[N_SETS][N_WAYS]; + + /* insert uses vaddr to find set; way selection could be random/rr/lru */ + uint32_t way_sel[N_SETS]; + + /* + * Current Address Space ID (in whose context mmu lookups done) + * Note that it is actually present in AUX PID reg, which we don't + * explicitly maintain, but {re,de}construct as needed by LR/SR insns + * respectively. + */ + uint32_t pid_asid; + uint32_t sasid0; + uint32_t sasid1; + + uint32_t tlbpd0; + uint32_t tlbpd1; + uint32_t tlbpd1_hi; + uint32_t tlbindex; + uint32_t tlbcmd; + uint32_t scratch_data0; +}; + + +struct CPUARCState; + + +extern void +arc_mmu_aux_set_tlbcmd(const struct arc_aux_reg_detail *aux_reg_detail, + uint32_t val, void *data); +extern void +arc_mmu_aux_set(const struct arc_aux_reg_detail *aux_reg_detail, + uint32_t val, void *data) ; + +extern uint32_t +arc_mmu_aux_get(const struct arc_aux_reg_detail *aux_reg_detail, void *data); + +uint32_t +arc_mmu_translate(struct CPUARCState *env, + uint32_t vaddr, enum mmu_access_type rwe, + uint32_t *index); + +void arc_mmu_debug_tlb(struct CPUARCState *env); +void arc_mmu_debug_tlb_for_vaddr(struct CPUARCState *env, uint32_t vaddr); + +uint32_t arc_mmu_page_address_for(uint32_t vaddr); + +void arc_mmu_init(struct arc_mmu *mmu); + +#endif /* ARC_MMU_H */ From patchwork Wed Nov 11 16:17:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cupertino Miranda X-Patchwork-Id: 1398396 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[2.80.104.46]) by smtp.gmail.com with ESMTPSA id s188sm3115178wmf.45.2020.11.11.08.18.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2020 08:18:18 -0800 (PST) From: cupertinomiranda@gmail.com To: qemu-devel@nongnu.org Subject: [PATCH 10/15] arc: Add memory protection unit (MPU) support Date: Wed, 11 Nov 2020 16:17:53 +0000 Message-Id: <20201111161758.9636-11-cupertinomiranda@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201111161758.9636-1-cupertinomiranda@gmail.com> References: <20201111161758.9636-1-cupertinomiranda@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201111_111823_470033_5344C8C8 X-CRM114-Status: GOOD ( 26.92 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:42a listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [cupertinomiranda[at]gmail.com] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Claudiu Zissulescu , Cupertino Miranda , Shahab Vahedi , Shahab Vahedi , Cupertino Miranda , linux-snps-arc@lists.infradead.org, Claudiu Zissulescu Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Shahab Vahedi Add memory implementation for Synopsys MPU unit version 3. Synopsys MPU allows to create memory regions against unauthorized execution/read/writes accesses. Signed-off-by: Shahab Vahedi --- target/arc/mpu.c | 656 +++++++++++++++++++++++++++++++++++++++++++++++ target/arc/mpu.h | 142 ++++++++++ 2 files changed, 798 insertions(+) create mode 100644 target/arc/mpu.c create mode 100644 target/arc/mpu.h diff --git a/target/arc/mpu.c b/target/arc/mpu.c new file mode 100644 index 0000000000..2d04f9c43e --- /dev/null +++ b/target/arc/mpu.c @@ -0,0 +1,656 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synppsys Inc. + * Contributed by Shahab Vahedi (Synopsys) + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#include "qemu/osdep.h" +#include "mpu.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "mmu.h" + +/* + * In case of exception, this signals the effective region + * was the default one + */ +#define MPU_DEFAULT_REGION_NR 0xff + +/* Defines used by in-house functions */ +#define MPU_EN_EN_BIT 30 +#define MPU_EN_KR_BIT 8 +#define MPU_EN_KW_BIT 7 +#define MPU_EN_KE_BIT 6 +#define MPU_EN_UR_BIT 5 +#define MPU_EN_UW_BIT 4 +#define MPU_EN_UE_BIT 3 + +#define MPU_ECR_EC_CODE_BIT 16 +#define MPU_ECR_VT_BIT 8 + +#define MPU_BASE_ADDR_MASK 0xffffffe0 /* ignore least 5 bits */ +#define MPU_BASE_VALID_MASK 0x00000001 /* bit #0 */ + +/* + * Given a number of bits as width, calc the mask to + * "and" with. e.g.: 3 bits --> 8 - 1 --> 7 (111b) + */ +#define MPU_WIDTH_TO_MASK(w) ((1 << (w)) - 1) +#define MPU_PERMS_REG_LOWER_SIZE_WIDTH 2 +#define MPU_PERMS_REG_HIGHER_SIZE_WIDTH 3 +#define MPU_PERMS_REG_HIGHER_SIZE_POS 9 + +/* + * After knowing the operating mode (user/kernel), + * this struct represents the effective permissions. + */ +typedef struct MPUEffectPerm { + bool read; + bool write; + bool exec; +} MPUEffectPerm; + +/* Packer and unpackers (local to this translation unit) */ +static inline uint32_t pack_enable(const bool ena) +{ + return ena << MPU_EN_EN_BIT; +} + +static inline void unpack_enable(bool *enabled, uint32_t value) +{ + *enabled = (value >> MPU_EN_EN_BIT) & 1; +} + +static inline uint32_t pack_permissions(const MPUPermissions *perms) +{ + return perms->KR << MPU_EN_KR_BIT | + perms->KW << MPU_EN_KW_BIT | + perms->KE << MPU_EN_KE_BIT | + perms->UR << MPU_EN_UR_BIT | + perms->UW << MPU_EN_UW_BIT | + perms->UE << MPU_EN_UE_BIT; +} + +static inline void unpack_permissions(MPUPermissions *perms, uint32_t value) +{ + perms->KR = (value >> MPU_EN_KR_BIT) & 1; + perms->KW = (value >> MPU_EN_KW_BIT) & 1; + perms->KE = (value >> MPU_EN_KE_BIT) & 1; + perms->UR = (value >> MPU_EN_UR_BIT) & 1; + perms->UW = (value >> MPU_EN_UW_BIT) & 1; + perms->UE = (value >> MPU_EN_UE_BIT) & 1; +} + +static inline uint32_t pack_enable_reg(const MPUEnableReg *mpuen) +{ + return pack_enable(mpuen->enabled) | + pack_permissions(&mpuen->permission); +} + +static inline void unpack_enable_reg(MPUEnableReg *mpuen, uint32_t value) +{ + unpack_enable(&mpuen->enabled, value); + unpack_permissions(&mpuen->permission, value); +} + +static inline uint32_t pack_ecr(const MPUECR *mpuecr) +{ + return ARC_MPU_ECR_VEC_NUM << MPU_ECR_EC_CODE_BIT | + (mpuecr->violation & 3) << MPU_ECR_VT_BIT | + mpuecr->region; +} + +static inline uint32_t pack_base_reg(const MPUBaseReg *mpurdb) +{ + return mpurdb->addr | mpurdb->valid; +} + +static inline void unpack_base_reg(MPUBaseReg *mpurdb, uint32_t value) +{ + mpurdb->addr = value & MPU_BASE_ADDR_MASK; + mpurdb->valid = value & MPU_BASE_VALID_MASK; +} + + +/* + * Break the "size" field into "higher" and "lower" parts + * e.g.: a b c d e --> a b c . . . d e + * higher lower + */ +static uint32_t pack_region_size_bits(uint8_t size_bits) +{ + uint32_t lower = + size_bits & MPU_WIDTH_TO_MASK(MPU_PERMS_REG_LOWER_SIZE_WIDTH); + uint32_t higher = size_bits >> MPU_PERMS_REG_LOWER_SIZE_WIDTH; + higher &= MPU_WIDTH_TO_MASK(MPU_PERMS_REG_HIGHER_SIZE_WIDTH); + return (higher << MPU_PERMS_REG_HIGHER_SIZE_POS) | lower; +} + +/* + * Put the higher and lower parts of "size" field together + * e.g.: a b c . . . d e ---> abcde + * higher lower + */ +static void unpack_region_size_bits(uint8_t *size_bits, uint32_t value) +{ + uint8_t lower = + value & MPU_WIDTH_TO_MASK(MPU_PERMS_REG_LOWER_SIZE_WIDTH); + uint8_t higher = value >> MPU_PERMS_REG_HIGHER_SIZE_POS; + higher &= MPU_WIDTH_TO_MASK(MPU_PERMS_REG_HIGHER_SIZE_WIDTH); + *size_bits = (higher << MPU_PERMS_REG_LOWER_SIZE_WIDTH) | lower; +} + +static void set_region_mask(uint32_t *mask, uint8_t size_bits) +{ + uint32_t region_offset_mask = 0; + /* + * size_bits: 00100b (4) --> 32 bytes --> least 5 bits are 0 + * size_bits: 00101b (5) --> 64 bytes --> least 6 bits are 0 + * ... + * size_bits: 11111b (31) --> 4 gb --> least 32 bits are 0 + */ + if (size_bits >= 4 && size_bits < 31) { + region_offset_mask = (2 << size_bits) - 1; + } else if (size_bits == 31) { + region_offset_mask = 0xffffffff; + } else { + qemu_log_mask(LOG_GUEST_ERROR, "[MPU] %hu as size of a region is " + "undefined behaviour.\n", size_bits); + } + *mask = ~region_offset_mask; +} + +static inline uint32_t pack_perm_reg(const MPUPermReg *mpurdp) +{ + return pack_region_size_bits(mpurdp->size_bits) | + pack_permissions(&mpurdp->permission); +} + +static void unpack_perm_reg(MPUPermReg *mpurdp, uint32_t value) +{ + unpack_region_size_bits(&mpurdp->size_bits, value); + /* size_bits of below 4 are undefined --> Assuming min region size. */ + mpurdp->size = (mpurdp->size_bits < 4) ? 32 : (2ul << mpurdp->size_bits); + unpack_permissions(&mpurdp->permission, value); + /* The mask is a facilitator to find the corresponding region easier */ + set_region_mask(&mpurdp->mask, mpurdp->size_bits); +} + + +/* Extern function: To be called at reset() */ +void arc_mpu_init(struct ARCCPU *cpu) +{ + static const MPUPermissions INITIAL_PERMS = {0}; + ARCMPU *mpu = &cpu->env.mpu; + size_t idx = 0; + + /* Maybe the version must be determinded also based on CPU type */ + mpu->reg_bcr.version = cpu->cfg.has_mpu ? ARC_MPU_VERSION : 0; + mpu->reg_bcr.regions = cpu->cfg.has_mpu ? cpu->cfg.mpu_num_regions : 0; + switch (mpu->reg_bcr.regions) { + case 0 ... 2: + case 4: + case 8: + case 16: + break; + default: + assert(!"Invalid number of MPU regions."); + } + + /* + * We use this flag to determine if MPU is in motion or not. + * This is most of the time the same as reg_enable.enabled, + * However, in case of a double exception (Machine Check) + * this becomes false while reg_enable.enabled holds its + * value. As a result, there is no MPU anymore after a + * Machine Check is raised. + */ + mpu->enabled = false; + + mpu->reg_enable.enabled = false; + mpu->reg_enable.permission = INITIAL_PERMS; + + mpu->reg_ecr.region = 0; + mpu->reg_ecr.violation = 0; + mpu->exception.number = ARC_MPU_ECR_VEC_NUM; + mpu->exception.code = 0; + mpu->exception.param = ARC_MPU_ECR_PARAM; + + for (idx = 0; idx < ARC_MPU_MAX_NR_REGIONS; ++idx) { + mpu->reg_base[idx].valid = false; + mpu->reg_base[idx].addr = 0; + + mpu->reg_perm[idx].size_bits = 0; + mpu->reg_perm[idx].mask = 0xffffffff; + mpu->reg_perm[idx].permission = INITIAL_PERMS; + } +} + +/* Checking the sanity of situation before accessing MPU registers */ +static void validate_mpu_regs_access(CPUARCState *env) +{ + /* MPU registers are only accessible in kernel mode */ + if (is_user_mode(env)) { + arc_raise_exception(env, EXCP_PRIVILEGEV); + } + /* No MPU, no getting any */ + else if ((env_archcpu(env))->cfg.has_mpu == false) { + arc_raise_exception(env, EXCP_INST_ERROR); + } +} + +/* If 'rgn' is higher than configured region number, throw an exception */ +static inline void validate_region_number(const ARCMPU *mpu, uint8_t rgn) +{ + if (!(rgn < mpu->reg_bcr.regions)) { + arc_raise_exception(container_of(mpu, CPUARCState, mpu), /* env */ + EXCP_INST_ERROR); + } +} + +/* Extern function: Getter for MPU registers */ +uint32_t +arc_mpu_aux_get(const struct arc_aux_reg_detail *aux_reg_detail, void *data) +{ + validate_mpu_regs_access((CPUARCState *) data); + ARCMPU *mpu = &(((CPUARCState *) data)->mpu); + uint32_t reg = 0; + + switch (aux_reg_detail->id) { + case AUX_ID_mpu_build: + reg = (mpu->reg_bcr.regions << 8) | mpu->reg_bcr.version; + break; + case AUX_ID_mpuen: + reg = pack_enable_reg(&mpu->reg_enable); + break; + case AUX_ID_mpuic: + reg = pack_ecr(&mpu->reg_ecr); + break; + case AUX_ID_mpurdb0 ... AUX_ID_mpurdb15: { + const uint8_t rgn = aux_reg_detail->id - AUX_ID_mpurdb0; + validate_region_number(mpu, rgn); + reg = pack_base_reg(&mpu->reg_base[rgn]); + break; + } + case AUX_ID_mpurdp0 ... AUX_ID_mpurdp15: { + const uint8_t rgn = aux_reg_detail->id - AUX_ID_mpurdp0; + validate_region_number(mpu, rgn); + reg = pack_perm_reg(&mpu->reg_perm[rgn]); + break; + } + default: + g_assert_not_reached(); + } + return reg; +} + +/* Log the MPU sensitive information */ +static void log_mpu_data(const ARCMPU *mpu) +{ + char suffix[4] = " B"; + uint32_t size; + /* Log header */ + qemu_log_mask(CPU_LOG_MMU, + "[MPU] ,--------.-------.------------.--------.---" + "--------------------.--------------.------------.\n"); + qemu_log_mask(CPU_LOG_MMU, + "[MPU] | region | valid | address | size | " + "effective address | kernel perm. | user perm. |\n"); + qemu_log_mask(CPU_LOG_MMU, + "[MPU] |--------+-------+------------+--------+---" + "--------------------+--------------+------------|\n"); + /* Now its every regions turn */ + for (uint8_t r = 0; r < mpu->reg_bcr.regions; ++r) { + const MPUBaseReg *rb = &mpu->reg_base[r]; + const MPUPermReg *rp = &mpu->reg_perm[r]; + const MPUPermissions *p = &rp->permission; + if (rp->size >= 0x40000000) { + suffix[0] = 'G'; + size = rp->size >> 30; + } else if (rp->size >= 0x00100000) { + suffix[0] = 'M'; + size = rp->size >> 20; + } else if (rp->size >= 0x00000400) { + suffix[0] = 'K'; + size = rp->size >> 10; + } else { + suffix[0] = ' '; + size = rp->size & 0x3FF; + } + qemu_log_mask(CPU_LOG_MMU, + "[MPU] | %02u | %s | 0x%08x | %3u %s | 0x%08x-0x%08x " + "| %c%c%c | %c%c%c |\n", + r, rb->valid ? "true " : "false", rb->addr, size, suffix, + rb->addr & rp->mask, + (rb->addr & rp->mask) + ((uint32_t) rp->size), + p->KR ? 'r' : '-', p->KW ? 'w' : '-', p->KE ? 'x' : '-', + p->UR ? 'r' : '-', p->UW ? 'w' : '-', p->UE ? 'x' : '-'); + } + /* Default region */ + const MPUPermissions *defp = &mpu->reg_enable.permission; + qemu_log_mask(CPU_LOG_MMU, + "[MPU] | def. | | | | " + " | %c%c%c | %c%c%c |\n", + defp->KR ? 'r' : '-', defp->KW ? 'w' : '-', defp->KE ? 'x' : '-', + defp->UR ? 'r' : '-', defp->UW ? 'w' : '-', defp->UE ? 'x' : '-'); + /* Wrap it up */ + qemu_log_mask(CPU_LOG_MMU, + "[MPU] `--------^-------^------------^--------^---" + "--------------------^--------------^------------'\n"); +} + +/* Extern function: Setter for MPU registers */ +void +arc_mpu_aux_set(const struct arc_aux_reg_detail *aux_reg_detail, + const uint32_t value, void *data) +{ + validate_mpu_regs_access((CPUARCState *) data); + ARCMPU *mpu = &(((CPUARCState *) data)->mpu); + + switch (aux_reg_detail->id) { + case AUX_ID_mpuen: + unpack_enable_reg(&mpu->reg_enable, value); + mpu->enabled = mpu->reg_enable.enabled; + break; + case AUX_ID_mpurdb0 ... AUX_ID_mpurdb15: { + const uint8_t rgn = aux_reg_detail->id - AUX_ID_mpurdb0; + validate_region_number(mpu, rgn); + unpack_base_reg(&mpu->reg_base[rgn], value); + break; + } + case AUX_ID_mpurdp0 ... AUX_ID_mpurdp15: { + const uint8_t rgn = aux_reg_detail->id - AUX_ID_mpurdp0; + validate_region_number(mpu, rgn); + unpack_perm_reg(&mpu->reg_perm[rgn], value); + break; + } + default: + g_assert_not_reached(); + } + /* Invalidate the entries in qemu's translation buffer */ + tlb_flush(env_cpu((CPUARCState *) data)); + /* If MPU is enabled, log its data */ + if (mpu->enabled) { + log_mpu_data(mpu); + } +} + +/* + * If user mode, return the user permission only. + * If kernel mode, return the aggregation of both permissions. + */ +static void get_effective_rwe(const MPUPermissions *perm, + bool user_mode, MPUEffectPerm *effective) +{ + effective->read = user_mode ? perm->UR : perm->KR | perm->UR; + effective->write = user_mode ? perm->UW : perm->KW | perm->UW; + effective->exec = user_mode ? perm->UE : perm->KE | perm->UE; +} + +/* Translate internal QEMU's access type to an MPU violation type */ +static inline uint8_t qemu_access_to_violation(MMUAccessType access) +{ + uint8_t vt = 0; + switch (access) { + case MMU_INST_FETCH: + vt = MPU_CAUSE_FETCH; + break; + case MMU_DATA_LOAD: + vt = MPU_CAUSE_READ; + break; + case MMU_DATA_STORE: + vt = MPU_CAUSE_WRITE; + break; + /* TODO: there must be an MPU_CAUSE_RW as well, but how? */ + default: + g_assert_not_reached(); + } + return vt; +} + +/* Translate MPU's permission to QEMU's tlb permission */ +static inline uint8_t mpu_permission_to_qemu(const MPUPermissions *perm, + bool user_mode) +{ + MPUEffectPerm effective = { }; + get_effective_rwe(perm, user_mode, &effective); + return (effective.read ? PAGE_READ : 0) | + (effective.write ? PAGE_WRITE : 0) | + (effective.exec ? PAGE_EXEC : 0); +} + +/* + * Check if the 'access' is according to 'perm'ission. + * Note that a user mode permission is also implied for kernel. + */ +static bool allowed(MMUAccessType access, bool user_mode, + const MPUPermissions *perm) +{ + MPUEffectPerm effective_perm = { }; + get_effective_rwe(perm, user_mode, &effective_perm); + + switch (access) { + case MMU_INST_FETCH: + return effective_perm.exec; + case MMU_DATA_LOAD: + return effective_perm.read; + case MMU_DATA_STORE: + return effective_perm.write; + default: + g_assert_not_reached(); + } +} + +/* Used for logging purposes */ +static inline const char *log_violation_to_str(uint8_t violation) +{ + return (violation == MPU_CAUSE_FETCH) ? "fetch" : + (violation == MPU_CAUSE_READ) ? "read" : + (violation == MPU_CAUSE_WRITE) ? "write" : + (violation == MPU_CAUSE_RW) ? "read-write" : + "unknown"; +} + +/* Sets the exception data */ +static void set_exception(CPUARCState *env, uint32_t addr, + uint8_t region, MMUAccessType access) +{ + MPUECR *ecr = &env->mpu.reg_ecr; + ecr->violation = qemu_access_to_violation(access); + ecr->region = region; + + /* this info is used by the caller to trigger the exception */ + MPUException *excp = &env->mpu.exception; + excp->number = EXCP_PROTV; + excp->code = ecr->violation; + excp->param = ARC_MPU_ECR_PARAM; + + qemu_log_mask(CPU_LOG_MMU, + "[MPU] exception: region=%hu, addr=0x%08x, violation=%s\n", + region, addr, log_violation_to_str(ecr->violation)); +} + +/* + * Given an 'addr', finds the region it belongs to. If no match + * is found, then it signals this by returning MPU_DEFAULT_REGION_NR. + * Since regions with lower index has higher priority, the first match + * is the correct one even if there is overlap among regions. + */ +static uint8_t get_matching_region(const ARCMPU *mpu, uint32_t addr) +{ + qemu_log_mask(CPU_LOG_MMU, "[MPU] looking up: addr=0x%08x\n", addr); + for (uint8_t r = 0; r < mpu->reg_bcr.regions; ++r) { + if (!mpu->reg_base[r].valid) { + continue; + } + const uint32_t mask = mpu->reg_perm[r].mask; + /* 'addr' falls under the current region? */ + if ((mpu->reg_base[r].addr & mask) == (addr & mask)) { + qemu_log_mask(CPU_LOG_MMU, + "[MPU] region match: region=%u, base=0x%08x\n", + r, mpu->reg_base[r].addr); + return r; + } + } + /* If we are here, then no corresponding region is found */ + qemu_log_mask(CPU_LOG_MMU, "[MPU] default region will be used.\n"); + return MPU_DEFAULT_REGION_NR; +} + +/* + * Returns the corresponding permission for the given 'region'. + * If 'region' is MPU_DEFAULT_REGION_NR, then the default permission + * from MPU_EN register is returned. + */ +static const MPUPermissions *get_permission(const ARCMPU *mpu, + uint8_t region) +{ + if (region < mpu->reg_bcr.regions) { + return &mpu->reg_perm[region].permission; + } else if (region == MPU_DEFAULT_REGION_NR) { + return &mpu->reg_enable.permission; + } + g_assert_not_reached(); +} + +/* + * Have the following example in mind: + * ,------------. + * | region 5 | + * | | + * | | first page of region 5 + * | | + * |............| + * | | + * |,----------.| second page of region 5 + * || region 4 || + * |`----------'| + * `------------' + * Here region four's size is half a page size. + * + * This function checks if the page that the address belongs to, + * overlaps with another higher priority region. regions with lower + * priority don't matter because they cannot influence the permission. + * + * The logic is to check if any of the valid regions is contained in + * the page that 'addr' belongs to. + */ +static bool is_overlap_free(const ARCMPU *mpu, target_ulong addr, + uint8_t current_region) +{ + /* Nothing has higher priority than region 0 */ + if (current_region == 0) { + return true; + } else if (current_region == MPU_DEFAULT_REGION_NR) { + /* Make the "default region number" fit in this function */ + current_region = mpu->reg_bcr.regions; + } + + assert(current_region <= mpu->reg_bcr.regions); + + target_ulong page_addr = addr & PAGE_MASK; + /* + * Going through every region that has higher priority than + * the current one. + */ + for (uint8_t r = 0; r < current_region; ++r) { + if (mpu->reg_base[r].valid && + page_addr == (mpu->reg_base[r].addr & PAGE_MASK)) { + return false; + } + } + /* No overlap with a higher priority region */ + return true; +} + +/* + * Update QEMU's TLB with region's permission. + * One thing to remember is that if the region size + * is smaller than TARGET_PAGE_SIZE, QEMU will always + * consult tlb_fill() for any access to that region. + * So there is no point in fine tunning TLB entry sizes + * to reflect the real region size. On the other hand, + * if the region size is big ( > TARGET_PAGE_SIZE), we + * still go with TARGET_PAGE_SIZE, because it can be + * memory demanding for host process. + */ +static void update_tlb_page(CPUARCState *env, uint8_t region, + target_ulong addr, int mmu_idx) +{ + CPUState *cs = env_cpu(env); + /* By default, only add entry for 'addr' */ + target_ulong tlb_addr = addr; + target_ulong tlb_size = 1; + bool check_for_overlap = true; + int prot = 0; + + if (region != MPU_DEFAULT_REGION_NR) { + MPUPermReg *perm = &env->mpu.reg_perm[region]; + prot = mpu_permission_to_qemu( + &perm->permission, is_user_mode(env)); + /* + * If the region's size is big enough, we'll check for overlap. + * Later if we find no overlap, then we add the permission for + * the whole page to qemu's tlb. + */ + check_for_overlap = (perm->size >= TARGET_PAGE_SIZE); + } + /* Default region */ + else { + prot = mpu_permission_to_qemu( + &env->mpu.reg_enable.permission, is_user_mode(env)); + } + + /* + * If the region completely covers the 'page' that 'addr' + * belongs to, _and_ is not overlapping with any other region + * then add a 'page'wise entry. + */ + if (check_for_overlap && + is_overlap_free(&env->mpu, addr, region)) { + tlb_addr = addr & PAGE_MASK; + tlb_size = TARGET_PAGE_SIZE; + } + + tlb_set_page(cs, tlb_addr, tlb_addr, prot, mmu_idx, tlb_size); + qemu_log_mask(CPU_LOG_MMU, "[MPU] TLB update: addr=0x%08x, " + "prot=%c%c%c, mmu_idx=%u, page_size=%u\n", tlb_addr, + (prot & PAGE_READ) ? 'r' : '-', (prot & PAGE_WRITE) ? 'w' : '-', + (prot & PAGE_EXEC) ? 'x' : '-', mmu_idx, tlb_size); +} + +/* The MPU entry point for any memory access */ +int +arc_mpu_translate(CPUARCState *env, target_ulong addr, + MMUAccessType access, int mmu_idx) +{ + ARCMPU *mpu = &env->mpu; + + uint8_t region = get_matching_region(mpu, addr); + const MPUPermissions *perms = get_permission(mpu, region); + if (!allowed(access, is_user_mode(env), perms)) { + set_exception(env, addr, region, access); + return MPU_FAULT; + } + update_tlb_page(env, region, addr, mmu_idx); + + return MPU_SUCCESS; +} + +/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ +/* vim: set ts=4 sw=4 et: */ diff --git a/target/arc/mpu.h b/target/arc/mpu.h new file mode 100644 index 0000000000..d23d289beb --- /dev/null +++ b/target/arc/mpu.h @@ -0,0 +1,142 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synppsys Inc. + * Contributed by Shahab Vahedi (Synopsys) + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#ifndef ARC_MPU_H +#define ARC_MPU_H + +#include "target/arc/regs.h" +#include "cpu-qom.h" + +/* These values are based on ARCv2 ISA PRM for ARC HS processors */ +#define ARC_MPU_VERSION 0x03 /* MPU version supported */ +#define ARC_MPU_MAX_NR_REGIONS 16 /* Number of regions to protect */ +#define ARC_MPU_ECR_VEC_NUM 0x06 /* EV_ProtV: Protection Violation */ +#define ARC_MPU_ECR_PARAM 0x04 /* MPU (as opposed to MMU, ...) */ + +/* MPU Build Configuration Register */ +typedef struct MPUBCR { + uint8_t version; /* 0 (disabled), 0x03 */ + uint8_t regions; /* 0, 1, 2, 4, 8, 16 */ +} MPUBCR; + +typedef struct MPUPermissions { + bool KR; /* Kernel read */ + bool KW; /* Kernel write */ + bool KE; /* Kernel execute */ + bool UR; /* User read */ + bool UW; /* User write */ + bool UE; /* User execute */ +} MPUPermissions; + +/* MPU Enable Register */ +typedef struct MPUEnableReg { + bool enabled; /* Is MPU enabled? */ + MPUPermissions permission; /* Default region permissions */ +} MPUEnableReg; + +/* Determines during which type of operation a violation occurred */ +enum MPUCauseCode { + MPU_CAUSE_FETCH = 0x00, + MPU_CAUSE_READ = 0x01, + MPU_CAUSE_WRITE = 0x02, + MPU_CAUSE_RW = 0x03 +}; + +/* The exception to be set */ +typedef struct MPUException { + uint8_t number; /* Exception vector number: 0x06 -> EV_ProtV */ + uint8_t code; /* Cause code: fetch, read, write, read/write */ + uint8_t param; /* Always 0x04 to represent MPU */ +} MPUException; + +/* MPU Exception Cause Register */ +typedef struct MPUECR { + uint8_t region; + uint8_t violation; /* Fetch, read, write, read/write */ +} MPUECR; + +/* MPU Region Descriptor Base Register */ +typedef struct MPUBaseReg { + bool valid; /* Is this region valid? */ + uint32_t addr; /* Minimum size is 32 bytes --> bits[4:0] are 0 */ +} MPUBaseReg; + +/* MPU Region Descriptor Permissions Register */ +typedef struct MPUPermReg { + /* size_bits: 00100b ... 11111b */ + uint8_t size_bits; + /* + * We need normal notation of size to set qemu's tlb page size later. + * Region's size: 32 bytes, 64 bytes, ..., 4 gigabytes + */ + uint64_t size; /* 2 << size_bits */ + /* + * Region offset: 0x1f, 0x3f, ..., 0xffffffff + * Hence region mask: 0xffffffe0, 0xfffffc0, ..., 0x00000000 + */ + uint32_t mask; + MPUPermissions permission; /* region's permissions */ +} MPUPermReg; + +typedef struct ARCMPU { + bool enabled; + + MPUBCR reg_bcr; + MPUEnableReg reg_enable; + MPUECR reg_ecr; + /* Base and permission registers are paired */ + MPUBaseReg reg_base[ARC_MPU_MAX_NR_REGIONS]; + MPUPermReg reg_perm[ARC_MPU_MAX_NR_REGIONS]; + + MPUException exception; +} ARCMPU; + +enum ARCMPUVerifyRet { + MPU_SUCCESS, + MPU_FAULT +}; + +struct ARCCPU; +struct CPUARCState; + +/* Used during a reset */ +extern void arc_mpu_init(struct ARCCPU *cpu); + +/* Get auxiliary MPU registers */ +extern uint32_t +arc_mpu_aux_get(const struct arc_aux_reg_detail *aux_reg_detail, void *data); + +/* Set auxiliary MPU registers */ +extern void +arc_mpu_aux_set(const struct arc_aux_reg_detail *aux_reg_detail, + const uint32_t val, void *data); + +/* + * Verifies if 'access' to 'addr' is allowed or not. + * possible return values: + * MPU_SUCCESS - allowed; 'prot' holds permissions + * MPU_FAULT - not allowed; corresponding exception parameters are set + */ +extern int +arc_mpu_translate(struct CPUARCState *env, uint32_t addr, + MMUAccessType access, int mmu_idx); + +#endif /* ARC_MPU_H */ From patchwork Wed Nov 11 16:17:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cupertino Miranda X-Patchwork-Id: 1398394 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2001:8b0:10b:1231::1; helo=merlin.infradead.org; envelope-from=linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; 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[2.80.104.46]) by smtp.gmail.com with ESMTPSA id s188sm3115178wmf.45.2020.11.11.08.18.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2020 08:18:19 -0800 (PST) From: cupertinomiranda@gmail.com To: qemu-devel@nongnu.org Subject: [PATCH 11/15] arc: Add gdbstub and XML for debugging support Date: Wed, 11 Nov 2020 16:17:54 +0000 Message-Id: <20201111161758.9636-12-cupertinomiranda@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201111161758.9636-1-cupertinomiranda@gmail.com> References: <20201111161758.9636-1-cupertinomiranda@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201111_111821_380068_9FC17610 X-CRM114-Status: GOOD ( 11.70 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:344 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [cupertinomiranda[at]gmail.com] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Claudiu Zissulescu , Cupertino Miranda , Shahab Vahedi , Shahab Vahedi , Cupertino Miranda , linux-snps-arc@lists.infradead.org, Claudiu Zissulescu Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Shahab Vahedi Register layout for the target and the mechanisms to read and set them. Signed-off-by: Shahab Vahedi --- gdb-xml/arc-v2-aux.xml | 32 +++ gdb-xml/arc-v2-core.xml | 45 +++++ gdb-xml/arc-v2-other.xml | 235 ++++++++++++++++++++++ target/arc/gdbstub.c | 420 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 732 insertions(+) create mode 100644 gdb-xml/arc-v2-aux.xml create mode 100644 gdb-xml/arc-v2-core.xml create mode 100644 gdb-xml/arc-v2-other.xml create mode 100644 target/arc/gdbstub.c diff --git a/gdb-xml/arc-v2-aux.xml b/gdb-xml/arc-v2-aux.xml new file mode 100644 index 0000000000..e18168ad05 --- /dev/null +++ b/gdb-xml/arc-v2-aux.xml @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/arc-v2-core.xml b/gdb-xml/arc-v2-core.xml new file mode 100644 index 0000000000..c925a6994c --- /dev/null +++ b/gdb-xml/arc-v2-core.xml @@ -0,0 +1,45 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/arc-v2-other.xml b/gdb-xml/arc-v2-other.xml new file mode 100644 index 0000000000..9824f518cc --- /dev/null +++ b/gdb-xml/arc-v2-other.xml @@ -0,0 +1,235 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/target/arc/gdbstub.c b/target/arc/gdbstub.c new file mode 100644 index 0000000000..5f12935216 --- /dev/null +++ b/target/arc/gdbstub.c @@ -0,0 +1,420 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synppsys Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#include "qemu/osdep.h" +#include "exec/gdbstub.h" +#include "arc-common.h" +#include "target/arc/regs.h" +#include "internals.h" +#include "irq.h" + +/* gets the register address for a particular processor */ +#define REG_ADDR(reg, processor_type) \ + arc_aux_reg_address_for((reg), (processor_type)) + +int arc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) +{ + ARCCPU *cpu = ARC_CPU(cs); + CPUARCState *env = &cpu->env; + uint32_t regval = 0; + + switch (n) { + case 0 ... 31: + regval = env->r[n]; + break; + case GDB_REG_58: + regval = env->r[58]; + break; + case GDB_REG_59: + regval = env->r[59]; + break; + case GDB_REG_60: + regval = env->r[60]; + break; + case GDB_REG_63: + regval = env->r[63]; + break; + default: + assert(!"Unsupported register is being read."); + } + + return gdb_get_reg32(mem_buf, regval); +} + +int arc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + ARCCPU *cpu = ARC_CPU(cs); + CPUARCState *env = &cpu->env; + uint32_t regval = ldl_p(mem_buf); + + switch (n) { + case 0 ... 31: + env->r[n] = regval; + break; + case GDB_REG_58: + env->r[58] = regval; + break; + case GDB_REG_59: + env->r[59] = regval; + break; + case GDB_REG_60: + env->r[60] = regval; + break; + case GDB_REG_63: + env->r[63] = regval; + break; + default: + assert(!"Unsupported register is being written."); + } + + return 4; +} + + +static int +arc_aux_minimal_gdb_get_reg(CPUARCState *env, GByteArray *mem_buf, int regnum) +{ + /* TODO: processor type must be set according to configuration */ + static const int processor = ARC_OPCODE_ARCv2HS; + uint32_t regval = 0; + + switch (regnum) { + case GDB_AUX_MIN_REG_PC: + regval = env->pc & 0xfffffffe; + break; + case GDB_AUX_MIN_REG_LPS: + regval = helper_lr(env, REG_ADDR(AUX_ID_lp_start, processor)); + break; + case GDB_AUX_MIN_REG_LPE: + regval = helper_lr(env, REG_ADDR(AUX_ID_lp_end, processor)); + break; + case GDB_AUX_MIN_REG_STATUS: + regval = pack_status32(&env->stat); + break; + default: + assert(!"Unsupported minimal auxiliary register is being read."); + } + return gdb_get_reg32(mem_buf, regval); +} + + +static int +arc_aux_minimal_gdb_set_reg(CPUARCState *env, uint8_t *mem_buf, int regnum) +{ + /* TODO: processor type must be set according to configuration */ + static const int processor = ARC_OPCODE_ARCv2HS; + uint32_t regval = ldl_p(mem_buf); + switch (regnum) { + case GDB_AUX_MIN_REG_PC: + env->pc = regval & 0xfffffffe; + break; + case GDB_AUX_MIN_REG_LPS: + helper_sr(env, regval, REG_ADDR(AUX_ID_lp_start, processor)); + break; + case GDB_AUX_MIN_REG_LPE: + helper_sr(env, regval, REG_ADDR(AUX_ID_lp_end, processor)); + break; + case GDB_AUX_MIN_REG_STATUS: + unpack_status32(&env->stat, regval); + break; + default: + assert(!"Unsupported minimal auxiliary register is being written."); + } + return 4; +} + + +static int +arc_aux_other_gdb_get_reg(CPUARCState *env, GByteArray *mem_buf, int regnum) +{ + /* TODO: processor type must be set according to configuration */ + static const int processor = ARC_OPCODE_ARCv2HS; + uint32_t regval = 0; + switch (regnum) { + case GDB_AUX_OTHER_REG_TIMER_BUILD: + regval = helper_lr(env, REG_ADDR(AUX_ID_timer_build, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_BUILD: + regval = helper_lr(env, REG_ADDR(AUX_ID_irq_build, processor)); + break; + case GDB_AUX_OTHER_REG_MPY_BUILD: + regval = helper_lr(env, REG_ADDR(AUX_ID_mpy_build, processor)); + break; + case GDB_AUX_OTHER_REG_VECBASE_BUILD: + regval = env->vecbase_build; + break; + case GDB_AUX_OTHER_REG_ISA_CONFIG: + regval = env->isa_config; + break; + case GDB_AUX_OTHER_REG_TIMER_CNT0: + regval = helper_lr(env, REG_ADDR(AUX_ID_count0, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_CTRL0: + regval = helper_lr(env, REG_ADDR(AUX_ID_control0, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_LIM0: + regval = helper_lr(env, REG_ADDR(AUX_ID_limit0, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_CNT1: + regval = helper_lr(env, REG_ADDR(AUX_ID_count1, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_CTRL1: + regval = helper_lr(env, REG_ADDR(AUX_ID_control1, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_LIM1: + regval = helper_lr(env, REG_ADDR(AUX_ID_limit1, processor)); + break; + case GDB_AUX_OTHER_REG_PID: + regval = helper_lr(env, REG_ADDR(AUX_ID_pid, processor)); + break; + case GDB_AUX_OTHER_REG_TLBPD0: + regval = helper_lr(env, REG_ADDR(AUX_ID_tlbpd0, processor)); + break; + case GDB_AUX_OTHER_REG_TLBPD1: + regval = helper_lr(env, REG_ADDR(AUX_ID_tlbpd1, processor)); + break; + case GDB_AUX_OTHER_REG_TLB_INDEX: + regval = helper_lr(env, REG_ADDR(AUX_ID_tlbindex, processor)); + break; + case GDB_AUX_OTHER_REG_TLB_CMD: + regval = helper_lr(env, REG_ADDR(AUX_ID_tlbcommand, processor)); + break; + /* MPU */ + case GDB_AUX_OTHER_REG_MPU_BUILD: + regval = helper_lr(env, REG_ADDR(AUX_ID_mpu_build, processor)); + break; + case GDB_AUX_OTHER_REG_MPU_EN: + regval = helper_lr(env, REG_ADDR(AUX_ID_mpuen, processor)); + break; + case GDB_AUX_OTHER_REG_MPU_ECR: + regval = helper_lr(env, REG_ADDR(AUX_ID_mpuic, processor)); + break; + case GDB_AUX_OTHER_REG_MPU_BASE0 ... GDB_AUX_OTHER_REG_MPU_BASE15: { + const uint8_t index = regnum - GDB_AUX_OTHER_REG_MPU_BASE0; + regval = helper_lr(env, REG_ADDR(AUX_ID_mpurdb0 + index, processor)); + break; + } + case GDB_AUX_OTHER_REG_MPU_PERM0 ... GDB_AUX_OTHER_REG_MPU_PERM15: { + const uint8_t index = regnum - GDB_AUX_OTHER_REG_MPU_PERM0; + regval = helper_lr(env, REG_ADDR(AUX_ID_mpurdp0 + index, processor)); + break; + } + /* exceptions */ + case GDB_AUX_OTHER_REG_ERSTATUS: + regval = helper_lr(env, REG_ADDR(AUX_ID_erstatus, processor)); + break; + case GDB_AUX_OTHER_REG_ERBTA: + regval = helper_lr(env, REG_ADDR(AUX_ID_erbta, processor)); + break; + case GDB_AUX_OTHER_REG_ECR: + regval = helper_lr(env, REG_ADDR(AUX_ID_ecr, processor)); + break; + case GDB_AUX_OTHER_REG_ERET: + regval = helper_lr(env, REG_ADDR(AUX_ID_eret, processor)); + break; + case GDB_AUX_OTHER_REG_EFA: + regval = helper_lr(env, REG_ADDR(AUX_ID_efa, processor)); + break; + /* interrupt */ + case GDB_AUX_OTHER_REG_ICAUSE: + regval = helper_lr(env, REG_ADDR(AUX_ID_icause, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_CTRL: + regval = helper_lr(env, REG_ADDR(AUX_ID_aux_irq_ctrl, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_ACT: + regval = helper_lr(env, REG_ADDR(AUX_ID_aux_irq_act, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_PRIO_PEND: + regval = env->irq_priority_pending; + break; + case GDB_AUX_OTHER_REG_IRQ_HINT: + regval = helper_lr(env, REG_ADDR(AUX_ID_aux_irq_hint, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_SELECT: + regval = helper_lr(env, REG_ADDR(AUX_ID_irq_select, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_ENABLE: + regval = env->irq_bank[env->irq_select & 0xff].enable; + break; + case GDB_AUX_OTHER_REG_IRQ_TRIGGER: + regval = helper_lr(env, REG_ADDR(AUX_ID_irq_trigger, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_STATUS: + regval = helper_lr(env, REG_ADDR(AUX_ID_irq_status, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_PULSE: + regval = 0; /* write only for clearing the pulse triggered interrupt */ + break; + case GDB_AUX_OTHER_REG_IRQ_PENDING: + regval = helper_lr(env, REG_ADDR(AUX_ID_irq_pending, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_PRIO: + regval = helper_lr(env, REG_ADDR(AUX_ID_irq_priority, processor)); + break; + case GDB_AUX_OTHER_REG_BTA: + regval = helper_lr(env, REG_ADDR(AUX_ID_bta, processor)); + break; + default: + assert(!"Unsupported other auxiliary register is being read."); + } + return gdb_get_reg32(mem_buf, regval); +} + + +static int +arc_aux_other_gdb_set_reg(CPUARCState *env, uint8_t *mem_buf, int regnum) +{ + /* TODO: processor type must be set according to configuration */ + static const int processor = ARC_OPCODE_ARCv2HS; + uint32_t regval = ldl_p(mem_buf); + switch (regnum) { + case GDB_AUX_OTHER_REG_TIMER_BUILD: + case GDB_AUX_OTHER_REG_IRQ_BUILD: + case GDB_AUX_OTHER_REG_MPY_BUILD: + case GDB_AUX_OTHER_REG_VECBASE_BUILD: + case GDB_AUX_OTHER_REG_ISA_CONFIG: + case GDB_AUX_OTHER_REG_MPU_BUILD: + case GDB_AUX_OTHER_REG_MPU_ECR: + case GDB_AUX_OTHER_REG_ICAUSE: + case GDB_AUX_OTHER_REG_IRQ_PRIO_PEND: + case GDB_AUX_OTHER_REG_IRQ_STATUS: + case GDB_AUX_OTHER_REG_IRQ_PENDING: + /* builds/configs/exceptions/irqs cannot be changed */ + break; + case GDB_AUX_OTHER_REG_TIMER_CNT0: + helper_sr(env, regval, REG_ADDR(AUX_ID_count0, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_CTRL0: + helper_sr(env, regval, REG_ADDR(AUX_ID_control0, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_LIM0: + helper_sr(env, regval, REG_ADDR(AUX_ID_limit0, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_CNT1: + helper_sr(env, regval, REG_ADDR(AUX_ID_count1, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_CTRL1: + helper_sr(env, regval, REG_ADDR(AUX_ID_control1, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_LIM1: + helper_sr(env, regval, REG_ADDR(AUX_ID_limit1, processor)); + break; + case GDB_AUX_OTHER_REG_PID: + helper_sr(env, regval, REG_ADDR(AUX_ID_pid, processor)); + break; + case GDB_AUX_OTHER_REG_TLBPD0: + helper_sr(env, regval, REG_ADDR(AUX_ID_tlbpd0, processor)); + break; + case GDB_AUX_OTHER_REG_TLBPD1: + helper_sr(env, regval, REG_ADDR(AUX_ID_tlbpd1, processor)); + break; + case GDB_AUX_OTHER_REG_TLB_INDEX: + helper_sr(env, regval, REG_ADDR(AUX_ID_tlbindex, processor)); + break; + case GDB_AUX_OTHER_REG_TLB_CMD: + helper_sr(env, regval, REG_ADDR(AUX_ID_tlbcommand, processor)); + break; + /* MPU */ + case GDB_AUX_OTHER_REG_MPU_EN: + helper_sr(env, regval, REG_ADDR(AUX_ID_mpuen, processor)); + break; + case GDB_AUX_OTHER_REG_MPU_BASE0 ... GDB_AUX_OTHER_REG_MPU_BASE15: { + const uint8_t index = regnum - GDB_AUX_OTHER_REG_MPU_BASE0; + helper_sr(env, regval, REG_ADDR(AUX_ID_mpurdb0 + index, processor)); + break; + } + case GDB_AUX_OTHER_REG_MPU_PERM0 ... GDB_AUX_OTHER_REG_MPU_PERM15: { + const uint8_t index = regnum - GDB_AUX_OTHER_REG_MPU_PERM0; + helper_sr(env, regval, REG_ADDR(AUX_ID_mpurdp0 + index, processor)); + break; + } + /* exceptions */ + case GDB_AUX_OTHER_REG_ERSTATUS: + helper_sr(env, regval, REG_ADDR(AUX_ID_erstatus, processor)); + break; + case GDB_AUX_OTHER_REG_ERBTA: + helper_sr(env, regval, REG_ADDR(AUX_ID_erbta, processor)); + break; + case GDB_AUX_OTHER_REG_ECR: + helper_sr(env, regval, REG_ADDR(AUX_ID_ecr, processor)); + break; + case GDB_AUX_OTHER_REG_ERET: + helper_sr(env, regval, REG_ADDR(AUX_ID_eret, processor)); + break; + case GDB_AUX_OTHER_REG_EFA: + helper_sr(env, regval, REG_ADDR(AUX_ID_efa, processor)); + break; + /* interrupt */ + case GDB_AUX_OTHER_REG_IRQ_CTRL: + helper_sr(env, regval, REG_ADDR(AUX_ID_aux_irq_ctrl, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_ACT: + helper_sr(env, regval, REG_ADDR(AUX_ID_aux_irq_act, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_HINT: + helper_sr(env, regval, REG_ADDR(AUX_ID_aux_irq_hint, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_SELECT: + helper_sr(env, regval, REG_ADDR(AUX_ID_irq_select, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_ENABLE: + helper_sr(env, regval, REG_ADDR(AUX_ID_irq_enable, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_TRIGGER: + helper_sr(env, regval, REG_ADDR(AUX_ID_irq_trigger, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_PULSE: + helper_sr(env, regval, REG_ADDR(AUX_ID_irq_pulse_cancel, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_PRIO: + helper_sr(env, regval, REG_ADDR(AUX_ID_irq_priority, processor)); + break; + case GDB_AUX_OTHER_REG_BTA: + helper_sr(env, regval, REG_ADDR(AUX_ID_bta, processor)); + break; + default: + assert(!"Unsupported other auxiliary register is being written."); + } + return 4; +} + + +void arc_cpu_register_gdb_regs_for_features(ARCCPU *cpu) +{ + CPUState *cs = CPU(cpu); + + gdb_register_coprocessor(cs, + arc_aux_minimal_gdb_get_reg, /* getter */ + arc_aux_minimal_gdb_set_reg, /* setter */ + GDB_AUX_MIN_REG_LAST, /* number of registers */ + "arc-v2-aux.xml", /* feature file */ + 0); /* position in g packet */ + + gdb_register_coprocessor(cs, + arc_aux_other_gdb_get_reg, + arc_aux_other_gdb_set_reg, + GDB_AUX_OTHER_REG_LAST, + "arc-v2-other.xml", + 0); +} + +/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ +/* vim: set ts=4 sw=4 et: */ From patchwork Wed Nov 11 16:17:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cupertino Miranda X-Patchwork-Id: 1398398 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2001:8b0:10b:1231::1; helo=merlin.infradead.org; envelope-from=linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=merlin.20170209 header.b=Bwn4DY/Y; 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[2.80.104.46]) by smtp.gmail.com with ESMTPSA id s188sm3115178wmf.45.2020.11.11.08.18.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2020 08:18:20 -0800 (PST) From: cupertinomiranda@gmail.com To: qemu-devel@nongnu.org Subject: [PATCH 12/15] arc: Add Synopsys ARC emulation boards Date: Wed, 11 Nov 2020 16:17:55 +0000 Message-Id: <20201111161758.9636-13-cupertinomiranda@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201111161758.9636-1-cupertinomiranda@gmail.com> References: <20201111161758.9636-1-cupertinomiranda@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201111_111824_805442_7B9F8D98 X-CRM114-Status: GOOD ( 27.59 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:342 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [cupertinomiranda[at]gmail.com] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Claudiu Zissulescu , Cupertino Miranda , Shahab Vahedi , Shahab Vahedi , Cupertino Miranda , linux-snps-arc@lists.infradead.org, Claudiu Zissulescu Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Claudiu Zissulescu Add the Synopsys ARC boards, arc_sim for testing, sim-hs main emulation board using standard UART and nsim which includes a Synopsys ARC specific UART implementation. Signed-off-by: Claudiu Zissulescu --- hw/arc/Makefile.objs | 21 +++++++ hw/arc/arc_sim.c | 124 +++++++++++++++++++++++++++++++++++++++ hw/arc/boot.c | 100 +++++++++++++++++++++++++++++++ hw/arc/boot.h | 21 +++++++ hw/arc/meson.build | 13 ++++ hw/arc/pic_cpu.c | 113 +++++++++++++++++++++++++++++++++++ hw/arc/virt.c | 107 +++++++++++++++++++++++++++++++++ include/hw/arc/cpudevs.h | 30 ++++++++++ 8 files changed, 529 insertions(+) create mode 100644 hw/arc/Makefile.objs create mode 100644 hw/arc/arc_sim.c create mode 100644 hw/arc/boot.c create mode 100644 hw/arc/boot.h create mode 100644 hw/arc/meson.build create mode 100644 hw/arc/pic_cpu.c create mode 100644 hw/arc/virt.c create mode 100644 include/hw/arc/cpudevs.h diff --git a/hw/arc/Makefile.objs b/hw/arc/Makefile.objs new file mode 100644 index 0000000000..28d7766cd9 --- /dev/null +++ b/hw/arc/Makefile.objs @@ -0,0 +1,21 @@ +# +# QEMU ARC CPU +# +# Copyright (c) 2019 +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see +# http://www.gnu.org/licenses/lgpl-2.1.html +# + +obj-y = arc_sim.o arc_uart.o sample.o pic_cpu.o boot.o board-hsdk.o sim-hs.o nsim.o diff --git a/hw/arc/arc_sim.c b/hw/arc/arc_sim.c new file mode 100644 index 0000000000..64db440454 --- /dev/null +++ b/hw/arc/arc_sim.c @@ -0,0 +1,124 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synppsys Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "cpu.h" +#include "hw/hw.h" +#include "hw/boards.h" +#include "elf.h" +#include "hw/char/serial.h" +#include "net/net.h" +#include "hw/loader.h" +#include "exec/memory.h" +#include "exec/address-spaces.h" +#include "sysemu/reset.h" +#include "sysemu/runstate.h" +#include "sysemu/sysemu.h" +#include "hw/sysbus.h" +#include "hw/arc/cpudevs.h" +#include "boot.h" + + +static uint64_t arc_io_read(void *opaque, hwaddr addr, unsigned size) +{ + return 0; +} + +static void arc_io_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + switch (addr) { + case 0x08: /* board reset. */ + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + break; + default: + break; + } +} + +static const MemoryRegionOps arc_io_ops = { + .read = arc_io_read, + .write = arc_io_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static void arc_sim_init(MachineState *machine) +{ + static struct arc_boot_info boot_info; + unsigned int smp_cpus = machine->smp.cpus; + ram_addr_t ram_base = 0; + ram_addr_t ram_size = machine->ram_size; + ARCCPU *cpu = NULL; + MemoryRegion *ram, *system_io; + int n; + + boot_info.ram_start = ram_base; + boot_info.ram_size = ram_size; + boot_info.kernel_filename = machine->kernel_filename; + + for (n = 0; n < smp_cpus; n++) { + cpu = ARC_CPU(object_new(machine->cpu_type)); + if (cpu == NULL) { + fprintf(stderr, "Unable to find CPU definition!\n"); + exit(1); + } + + /* Set the initial CPU properties. */ + object_property_set_uint(OBJECT(cpu), "freq_hz", 1000000, &error_fatal); + object_property_set_bool(OBJECT(cpu), "rtc-opt", true, &error_fatal); + object_property_set_bool(OBJECT(cpu), "realized", true, &error_fatal); + + /* Initialize internal devices. */ + cpu_arc_pic_init(cpu); + cpu_arc_clock_init(cpu); + + qemu_register_reset(arc_cpu_reset, cpu); + } + + ram = g_new(MemoryRegion, 1); + memory_region_init_ram(ram, NULL, "arc.ram", ram_size, &error_fatal); + memory_region_add_subregion(get_system_memory(), ram_base, ram); + + system_io = g_new(MemoryRegion, 1); + memory_region_init_io(system_io, NULL, &arc_io_ops, NULL, "arc.io", + 1024); + memory_region_add_subregion(get_system_memory(), 0xf0000000, system_io); + + serial_mm_init(get_system_memory(), 0x90000000, 2, cpu->env.irq[20], + 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); + + arc_load_kernel(cpu, &boot_info); +} + +static void arc_sim_machine_init(MachineClass *mc) +{ + mc->desc = "ARCxx simulation"; + mc->init = arc_sim_init; + mc->max_cpus = 1; + mc->is_default = false; + mc->default_cpu_type = ARC_CPU_TYPE_NAME("archs"); +} + +DEFINE_MACHINE("arc-sim", arc_sim_machine_init) + + +/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ +/* vim: set ts=4 sw=4 et: */ diff --git a/hw/arc/boot.c b/hw/arc/boot.c new file mode 100644 index 0000000000..937a9efc50 --- /dev/null +++ b/hw/arc/boot.c @@ -0,0 +1,100 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synppsys Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#include "qemu/osdep.h" +#include "boot.h" +#include "elf.h" +#include "hw/loader.h" +#include "qemu/error-report.h" +#include "qemu/units.h" + +void arc_cpu_reset(void *opaque) +{ + ARCCPU *cpu = opaque; + CPUARCState *env = &cpu->env; + const struct arc_boot_info *info = env->boot_info; + + cpu_reset(CPU(cpu)); + + /* + * Right before start CPU gets reset wiping out everything + * but PC which we set on Elf load. + * + * And if we still want to pass something like U-Boot data + * via CPU registers we have to do it here. + */ + + if (info->kernel_cmdline && strlen(info->kernel_cmdline)) { + /* + * Load "cmdline" far enough from the kernel image. + * Round by MAX page size for ARC - 16 KiB. + */ + hwaddr cmdline_addr = info->ram_start + + QEMU_ALIGN_UP(info->ram_size / 2, 16 * KiB); + cpu_physical_memory_write(cmdline_addr, info->kernel_cmdline, + strlen(info->kernel_cmdline)); + + /* We're passing "cmdline" */ + cpu->env.r[0] = ARC_UBOOT_CMDLINE; + cpu->env.r[2] = cmdline_addr; + } +} + + +void arc_load_kernel(ARCCPU *cpu, struct arc_boot_info *info) +{ + hwaddr entry; + int elf_machine, kernel_size; + + if (!info->kernel_filename) { + error_report("missing kernel file"); + exit(EXIT_FAILURE); + } + + elf_machine = cpu->env.family > 2 ? EM_ARC_COMPACT2 : EM_ARC_COMPACT; + kernel_size = load_elf(info->kernel_filename, NULL, NULL, NULL, + &entry, NULL, NULL, NULL, ARC_ENDIANNESS_LE, + elf_machine, 1, 0); + + if (kernel_size < 0) { + int is_linux; + + kernel_size = load_uimage(info->kernel_filename, &entry, NULL, + &is_linux, NULL, NULL); + if (!is_linux) { + error_report("Wrong U-Boot image, only Linux kernel is supported"); + exit(EXIT_FAILURE); + } + } + + if (kernel_size < 0) { + error_report("No kernel image found"); + exit(EXIT_FAILURE); + } + + cpu->env.boot_info = info; + + /* Set CPU's PC to point to the entry-point */ + cpu->env.pc = entry; +} + + +/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ +/* vim: set ts=4 sw=4 et: */ diff --git a/hw/arc/boot.h b/hw/arc/boot.h new file mode 100644 index 0000000000..e46aa16fc6 --- /dev/null +++ b/hw/arc/boot.h @@ -0,0 +1,21 @@ +#ifndef ARC_BOOT_H +#define ARC_BOOT_H + +#include "hw/hw.h" +#include "cpu.h" + +struct arc_boot_info { + hwaddr ram_start; + uint64_t ram_size; + const char *kernel_filename; + const char *kernel_cmdline; +}; + +void arc_cpu_reset(void *opaque); +void arc_load_kernel(ARCCPU *cpu, struct arc_boot_info *boot_info); + +#endif /* ARC_BOOT_H */ + + +/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ +/* vim: set ts=4 sw=4 et: */ diff --git a/hw/arc/meson.build b/hw/arc/meson.build new file mode 100644 index 0000000000..6a587307a4 --- /dev/null +++ b/hw/arc/meson.build @@ -0,0 +1,13 @@ +arc_ss = ss.source_set() +arc_ss.add(files( + 'arc_sim.c', + 'arc_uart.c', + 'sample.c', + 'pic_cpu.c', + 'boot.c', + 'board-hsdk.c', + 'sim-hs.c', + 'nsim.c', +)) + +hw_arch += {'arc': arc_ss} diff --git a/hw/arc/pic_cpu.c b/hw/arc/pic_cpu.c new file mode 100644 index 0000000000..ade0b425f7 --- /dev/null +++ b/hw/arc/pic_cpu.c @@ -0,0 +1,113 @@ +/* + * ARC Programmable Interrupt Controller support. + * + * Copyright (c) 2020 Synppsys Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + + +#include "qemu/osdep.h" +#include "cpu.h" +#include "hw/hw.h" +#include "hw/irq.h" +#include "qemu/log.h" +#include "hw/arc/cpudevs.h" + +/* + * ARC pic handler + */ +static void arc_pic_cpu_handler(void *opaque, int irq, int level) +{ + ARCCPU *cpu = (ARCCPU *) opaque; + CPUState *cs = CPU(cpu); + CPUARCState *env = &cpu->env; + int i; + bool clear = false; + uint32_t irq_bit; + + /* Assert if this handler is called in a system without interrupts. */ + assert(cpu->cfg.has_interrupts); + + /* Assert if the IRQ is not within the cpu configuration bounds. */ + assert(irq >= 16 && irq < (cpu->cfg.number_of_interrupts + 15)); + + irq_bit = 1 << env->irq_bank[irq].priority; + if (level) { + /* + * An interrupt is enabled, update irq_priority_pendig and rise + * the qemu interrupt line. + */ + env->irq_bank[irq].pending = 1; + qatomic_or(&env->irq_priority_pending, irq_bit); + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + env->irq_bank[irq].pending = 0; + + /* + * First, check if we still have any pending interrupt at the + * given priority. + */ + clear = true; + for (i = 16; i < cpu->cfg.number_of_interrupts; i++) { + if (env->irq_bank[i].pending + && env->irq_bank[i].priority == env->irq_bank[irq].priority) { + clear = false; + break; + } + } + + /* If not, update (clear) irq_priority_pending. */ + if (clear) { + qatomic_and(&env->irq_priority_pending, ~irq_bit); + } + + /* + * If we don't have any pending priority, lower the qemu irq + * line. N.B. we can also check more here like IE bit, but we + * need to add a cpu_interrupt call when we enable the + * interrupts (e.g., sleep, seti). + */ + if (!env->irq_priority_pending) { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } + } + qemu_log_mask(CPU_LOG_INT, + "[IRQ] level = %d, clear = %d, irq = %d, priority = %d, " + "pending = %08x, pc = %08x\n", + level, clear, irq, env->irq_bank[irq].priority, + env->irq_priority_pending, env->pc); +} + +/* + * ARC PIC initialization helper + */ +void cpu_arc_pic_init(ARCCPU *cpu) +{ + CPUARCState *env = &cpu->env; + int i; + qemu_irq *qi; + + qi = qemu_allocate_irqs(arc_pic_cpu_handler, cpu, + 16 + cpu->cfg.number_of_interrupts); + + for (i = 0; i < cpu->cfg.number_of_interrupts; i++) { + env->irq[16 + i] = qi[16 + i]; + } +} + + +/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ +/* vim: set ts=4 sw=4 et: */ diff --git a/hw/arc/virt.c b/hw/arc/virt.c new file mode 100644 index 0000000000..426ceca44d --- /dev/null +++ b/hw/arc/virt.c @@ -0,0 +1,107 @@ +/* + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "boot.h" +#include "hw/boards.h" +#include "hw/char/serial.h" +#include "exec/address-spaces.h" +#include "sysemu/reset.h" +#include "sysemu/sysemu.h" +#include "hw/arc/cpudevs.h" +#include "hw/sysbus.h" + +#define VIRT_RAM_BASE 0x80000000 +#define VIRT_RAM_SIZE 0x80000000 +#define VIRT_IO_BASE 0xf0000000 +#define VIRT_IO_SIZE 0x10000000 +#define VIRT_UART0_OFFSET 0x0 +#define VIRT_UART0_IRQ 24 + +/* VirtIO */ +#define VIRT_VIRTIO_NUMBER 5 +#define VIRT_VIRTIO_OFFSET 0x100000 +#define VIRT_VIRTIO_BASE (VIRT_IO_BASE + VIRT_VIRTIO_OFFSET) +#define VIRT_VIRTIO_SIZE 0x2000 +#define VIRT_VIRTIO_IRQ 31 + +static void virt_init(MachineState *machine) +{ + static struct arc_boot_info boot_info; + unsigned int smp_cpus = machine->smp.cpus; + MemoryRegion *system_memory = get_system_memory(); + MemoryRegion *system_ram; + MemoryRegion *system_io; + ARCCPU *cpu = NULL; + int n; + + boot_info.ram_start = VIRT_RAM_BASE; + boot_info.ram_size = VIRT_RAM_SIZE; + boot_info.kernel_filename = machine->kernel_filename; + boot_info.kernel_cmdline = machine->kernel_cmdline; + + for (n = 0; n < smp_cpus; n++) { + cpu = ARC_CPU(cpu_create("archs-" TYPE_ARC_CPU)); + if (cpu == NULL) { + fprintf(stderr, "Unable to find CPU definition!\n"); + exit(1); + } + + /* Initialize internal devices. */ + cpu_arc_pic_init(cpu); + cpu_arc_clock_init(cpu); + + qemu_register_reset(arc_cpu_reset, cpu); + } + + /* Init system DDR */ + system_ram = g_new(MemoryRegion, 1); + memory_region_init_ram(system_ram, NULL, "arc.ram", VIRT_RAM_SIZE, + &error_fatal); + memory_region_add_subregion(system_memory, VIRT_RAM_BASE, system_ram); + + /* Init IO area */ + system_io = g_new(MemoryRegion, 1); + memory_region_init_io(system_io, NULL, NULL, NULL, "arc.io", + VIRT_IO_SIZE); + memory_region_add_subregion(system_memory, VIRT_IO_BASE, system_io); + + serial_mm_init(system_io, VIRT_UART0_OFFSET, 2, + cpu->env.irq[VIRT_UART0_IRQ], 115200, serial_hd(0), + DEVICE_NATIVE_ENDIAN); + + for (n = 0; n < VIRT_VIRTIO_NUMBER; n++) { + sysbus_create_simple("virtio-mmio", + VIRT_VIRTIO_BASE + VIRT_VIRTIO_SIZE * n, + cpu->env.irq[VIRT_VIRTIO_IRQ + n]); + } + + arc_load_kernel(cpu, &boot_info); +} + +static void virt_machine_init(MachineClass *mc) +{ + mc->desc = "ARC Virtual Machine"; + mc->init = virt_init; + mc->max_cpus = 1; + mc->is_default = true; +} + +DEFINE_MACHINE("virt", virt_machine_init) + + +/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ +/* vim: set ts=4 sw=4 et: */ diff --git a/include/hw/arc/cpudevs.h b/include/hw/arc/cpudevs.h new file mode 100644 index 0000000000..2e155b6437 --- /dev/null +++ b/include/hw/arc/cpudevs.h @@ -0,0 +1,30 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synppsys Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#ifndef HW_ARC_CPUDEVS_H +#define HW_ARC_CPUDEVS_H + +/* Timer service routines. */ +extern void cpu_arc_clock_init(ARCCPU *); + +/* PIC service routines. */ +extern void cpu_arc_pic_init(ARCCPU *); + +#endif /* !HW_ARC_CPUDEVS_H */ From patchwork Wed Nov 11 16:17:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cupertino Miranda X-Patchwork-Id: 1398395 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2001:8b0:10b:1231::1; helo=merlin.infradead.org; envelope-from=linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=merlin.20170209 header.b=0vYgZaqw; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=ZtvXhrOj; dkim-atps=neutral Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:8b0:10b:1231::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CWVKB5mlkz9s0b for ; Thu, 12 Nov 2020 03:18:38 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=T5Al++g3IYw19A6jcrI9HjggUsUBZvhCSbpkuEpL1AY=; b=0vYgZaqw85zir6Yyl7OmovDur p9ocgTy0cAZJ/bS6fhlYqSy5/3wIODnUr/E6O14gRkh3EHIF8H2P8bOf4/MrShA+TAuXCfIAQBm9W w/rx039rPosWDXiWsfFbmHYTtM4K51Dw/IG83rxN1yzkKCnzlINuzUnoT30M/xxKqt4X8pjmgJUMe A1EnsX2vjRyXEvzIrIWaFW8N/Gc13IfHRfe2j90LUR5qZxzwZ8rAjS5A1QrIud0sXnW0E1u4I2Ilk NeDfstxQAfv+L6bqEhspDBOG9X0vy48G0Cp/HQ5LwQYAkUhpWpbPxiSFlu96pbB3JLlmpbZz5c1mr KMcTNHl2Q==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kcspO-0003jB-Uq; Wed, 11 Nov 2020 16:18:35 +0000 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kcspD-0003ew-KV for linux-snps-arc@lists.infradead.org; Wed, 11 Nov 2020 16:18:30 +0000 Received: by mail-wr1-x442.google.com with SMTP id o15so3091984wru.6 for ; Wed, 11 Nov 2020 08:18:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8zo+2MC0dwCZlrl13leQZToCZo2pO8yIdQ0oeKd3peA=; b=ZtvXhrOj4OgfH7Y0rT9t+8ifkSQNRJonm8yG5cG8fNzaqFURRPA44VyK7pwINMjSBL KFfyf6/6mQR5iQKtriLhaQ8rZHqrwmTbDSpaHrEUVw8qozpIDLMswNctbnu0KjDdVUG9 s39vvmJvVsPgMCx+/pLr9xdWPOYZtmcGL4D6a+K9cNcF6POer4QDW8sciTXin4MjvrWc P51zsKADUNxDDMqDGjH26041DxmvaqPpZJTehMkIzRsJ5+apbtjpacXpVRmd4eRBMtoR nTCfTF6kXeFLnZOnxK7Y4Ddk/4dW4vZE1qKOlOmnQbuWIJEO6cUqlaIHGUY43mIUJimD NGwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8zo+2MC0dwCZlrl13leQZToCZo2pO8yIdQ0oeKd3peA=; b=Kq7VyFR9lyAJWBsH0ZgJHE6p07oup2oJ9uLGL1pcSA1dyMwl06srpP9b5+ksqR4tkm tqid13PjgefbwWOP5cLONMtHwpU/LNn7O7JHj5USMiRpLuQmLwihBG+/6NNWSPcD7t9b cPuvj+AEpIwxKvz8mMnCg9/raQo8epzdh6GcHLVAbq6xYSCXJEC9pUi2AMPpaaU9bBZM UUjX9yGDhRVMn2nfjOoW3YzpC3jYYbqPOCghU+86SYtooIhei3M1Yw8TeP4uMn1lu2NM uUKxyvV4H412Gb/bboj/r4YiBxRMuexLPiqLBxHiCoFi4+QZDkVMr95QGHAtwiZIUiEL Ve7Q== X-Gm-Message-State: AOAM532fGnFCrIsUZwh2gMmNWZdJLAWixItK3xf2LCbqZrZkeIq8VWfb y6fCSzYSy5Ax6ZKUyoeCbVRfpbRGHnznNA== X-Google-Smtp-Source: ABdhPJxQeSJo2eG10vYIX11zR2DSpF+mmJp03lsdQFgutH1a0viB1wKIttGvCjXBTbZA5akDGi1hsw== X-Received: by 2002:adf:cd02:: with SMTP id w2mr30579464wrm.3.1605111502682; Wed, 11 Nov 2020 08:18:22 -0800 (PST) Received: from cmiranda-laptop.localdomain (bl19-104-46.dsl.telepac.pt. [2.80.104.46]) by smtp.gmail.com with ESMTPSA id s188sm3115178wmf.45.2020.11.11.08.18.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2020 08:18:22 -0800 (PST) From: cupertinomiranda@gmail.com To: qemu-devel@nongnu.org Subject: [PATCH 13/15] arc: Add support for ARCv2 Date: Wed, 11 Nov 2020 16:17:56 +0000 Message-Id: <20201111161758.9636-14-cupertinomiranda@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201111161758.9636-1-cupertinomiranda@gmail.com> References: <20201111161758.9636-1-cupertinomiranda@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201111_111823_747748_E0CE062B X-CRM114-Status: GOOD ( 23.75 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:442 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [cupertinomiranda[at]gmail.com] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Claudiu Zissulescu , Cupertino Miranda , Shahab Vahedi , Shahab Vahedi , Cupertino Miranda , linux-snps-arc@lists.infradead.org, Claudiu Zissulescu Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Shahab Vahedi Add remaining bits of the Synopsys ARCv2 (EM/HS) support into QEMU, configure bits, arch_init and configuration files for softmmu (hardware emulation). Signed-off-by: Shahab Vahedi Signed-off-by: Cupertino Miranda --- configure | 2 ++ default-configs/arc-softmmu.mak | 5 +++++ default-configs/devices/arc-softmmu.mak | 7 +++++++ default-configs/targets/arc-softmmu.mak | 2 ++ disas.c | 2 ++ disas/meson.build | 1 + hw/Kconfig | 1 + hw/arc/Kconfig | 7 +++++++ hw/arc/Makefile.objs | 21 --------------------- hw/arc/meson.build | 6 +----- hw/meson.build | 1 + include/disas/dis-asm.h | 10 +++++++++- include/elf.h | 3 +++ include/exec/poison.h | 2 ++ include/sysemu/arch_init.h | 1 + meson.build | 5 +++-- softmmu/arch_init.c | 2 ++ target/meson.build | 1 + 18 files changed, 50 insertions(+), 29 deletions(-) create mode 100644 default-configs/arc-softmmu.mak create mode 100644 default-configs/devices/arc-softmmu.mak create mode 100644 default-configs/targets/arc-softmmu.mak create mode 100644 hw/arc/Kconfig delete mode 100644 hw/arc/Makefile.objs diff --git a/configure b/configure index 2c3c69f118..1c8a6c8fcf 100755 --- a/configure +++ b/configure @@ -672,6 +672,8 @@ elif check_define __arm__ ; then cpu="arm" elif check_define __aarch64__ ; then cpu="aarch64" +elif check_define __arc__ ; then + cpu="arc" else cpu=$(uname -m) fi diff --git a/default-configs/arc-softmmu.mak b/default-configs/arc-softmmu.mak new file mode 100644 index 0000000000..4300a90c93 --- /dev/null +++ b/default-configs/arc-softmmu.mak @@ -0,0 +1,5 @@ +# Default configuration for arc-softmmu + +CONFIG_VIRTIO_MMIO=y +CONFIG_SERIAL=y +CONFIG_OPENCORES_ETH=y diff --git a/default-configs/devices/arc-softmmu.mak b/default-configs/devices/arc-softmmu.mak new file mode 100644 index 0000000000..0ce4176b2d --- /dev/null +++ b/default-configs/devices/arc-softmmu.mak @@ -0,0 +1,7 @@ +# Default configuration for arc-softmmu + +CONFIG_SEMIHOSTING=n + +# Boards: +# +CONFIG_ARC_VIRT=y diff --git a/default-configs/targets/arc-softmmu.mak b/default-configs/targets/arc-softmmu.mak new file mode 100644 index 0000000000..31916cb23d --- /dev/null +++ b/default-configs/targets/arc-softmmu.mak @@ -0,0 +1,2 @@ +TARGET_ARCH=arc +TARGET_XML_FILES= gdb-xml/arc-v2-core.xml gdb-xml/arc-v2-aux.xml gdb-xml/arc-v2-other.xml diff --git a/disas.c b/disas.c index 7c18d7d2a7..0085a55fd7 100644 --- a/disas.c +++ b/disas.c @@ -208,6 +208,8 @@ static void initialize_debug_host(CPUDebug *s) s->info.cap_insn_split = 6; #elif defined(__hppa__) s->info.print_insn = print_insn_hppa; +#elif defined(__arc__) + s->info.print_insn = print_insn_arc; #endif } diff --git a/disas/meson.build b/disas/meson.build index 09a852742e..98271bafb9 100644 --- a/disas/meson.build +++ b/disas/meson.build @@ -4,6 +4,7 @@ subdir('libvixl') common_ss.add(when: 'CONFIG_ALPHA_DIS', if_true: files('alpha.c')) common_ss.add(when: 'CONFIG_ARM_A64_DIS', if_true: files('arm-a64.cc')) common_ss.add_all(when: 'CONFIG_ARM_A64_DIS', if_true: libvixl_ss) +common_ss.add(when: 'CONFIG_ARC_DIS', if_true: files('arc.c')) common_ss.add(when: 'CONFIG_ARM_DIS', if_true: files('arm.c')) common_ss.add(when: 'CONFIG_CRIS_DIS', if_true: files('cris.c')) common_ss.add(when: 'CONFIG_HPPA_DIS', if_true: files('hppa.c')) diff --git a/hw/Kconfig b/hw/Kconfig index 4de1797ffd..7c942ba1c2 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -41,6 +41,7 @@ source vfio/Kconfig source watchdog/Kconfig # arch Kconfig +source arc/Kconfig source arm/Kconfig source alpha/Kconfig source avr/Kconfig diff --git a/hw/arc/Kconfig b/hw/arc/Kconfig new file mode 100644 index 0000000000..37402397c6 --- /dev/null +++ b/hw/arc/Kconfig @@ -0,0 +1,7 @@ +config ARC_VIRT + bool + select SERIAL + select VIRTIO_MMIO + +config ARC + bool diff --git a/hw/arc/Makefile.objs b/hw/arc/Makefile.objs deleted file mode 100644 index 28d7766cd9..0000000000 --- a/hw/arc/Makefile.objs +++ /dev/null @@ -1,21 +0,0 @@ -# -# QEMU ARC CPU -# -# Copyright (c) 2019 -# -# This library is free software; you can redistribute it and/or -# modify it under the terms of the GNU Lesser General Public -# License as published by the Free Software Foundation; either -# version 2.1 of the License, or (at your option) any later version. -# -# This library is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -# Lesser General Public License for more details. -# -# You should have received a copy of the GNU Lesser General Public -# License along with this library; if not, see -# http://www.gnu.org/licenses/lgpl-2.1.html -# - -obj-y = arc_sim.o arc_uart.o sample.o pic_cpu.o boot.o board-hsdk.o sim-hs.o nsim.o diff --git a/hw/arc/meson.build b/hw/arc/meson.build index 6a587307a4..f3b517013d 100644 --- a/hw/arc/meson.build +++ b/hw/arc/meson.build @@ -1,13 +1,9 @@ arc_ss = ss.source_set() arc_ss.add(files( 'arc_sim.c', - 'arc_uart.c', - 'sample.c', 'pic_cpu.c', 'boot.c', - 'board-hsdk.c', - 'sim-hs.c', - 'nsim.c', )) +arc_ss.add(when: 'CONFIG_ARC_VIRT', if_true: files('virt.c')) hw_arch += {'arc': arc_ss} diff --git a/hw/meson.build b/hw/meson.build index 010de7219c..e2b14a9ed8 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -43,6 +43,7 @@ subdir('xen') subdir('xenpv') subdir('alpha') +subdir('arc') subdir('arm') subdir('avr') subdir('cris') diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h index 2164762b46..cb63fd7550 100644 --- a/include/disas/dis-asm.h +++ b/include/disas/dis-asm.h @@ -206,7 +206,14 @@ enum bfd_architecture bfd_arch_v850, /* NEC V850 */ #define bfd_mach_v850 0 bfd_arch_arc, /* Argonaut RISC Core */ -#define bfd_mach_arc_base 0 +#define bfd_mach_arc_a4 0 +#define bfd_mach_arc_a5 1 +#define bfd_mach_arc_arc600 2 +#define bfd_mach_arc_arc601 4 +#define bfd_mach_arc_arc700 3 +#define bfd_mach_arc_arcv2 5 +#define bfd_mach_arc_arcv2em 6 +#define bfd_mach_arc_arcv2hs 7 bfd_arch_m32r, /* Mitsubishi M32R/D */ #define bfd_mach_m32r 0 /* backwards compatibility */ bfd_arch_mn10200, /* Matsushita MN10200 */ @@ -459,6 +466,7 @@ int print_insn_xtensa (bfd_vma, disassemble_info*); int print_insn_riscv32 (bfd_vma, disassemble_info*); int print_insn_riscv64 (bfd_vma, disassemble_info*); int print_insn_rx(bfd_vma, disassemble_info *); +int print_insn_arc (bfd_vma, disassemble_info*); #ifdef CONFIG_CAPSTONE bool cap_disas_target(disassemble_info *info, uint64_t pc, size_t size); diff --git a/include/elf.h b/include/elf.h index 7a418ee559..030b15e49c 100644 --- a/include/elf.h +++ b/include/elf.h @@ -207,6 +207,9 @@ typedef struct mips_elf_abiflags_v0 { #define EM_TILEGX 191 /* TILE-Gx */ +#define EM_ARC_COMPACT 93 /* Synopsys ARCompact */ +#define EM_ARC_COMPACT2 195 /* Synopsys ARCompact V2 */ + #define EM_MOXIE 223 /* Moxie processor family */ #define EM_MOXIE_OLD 0xFEED diff --git a/include/exec/poison.h b/include/exec/poison.h index 7b9ac361dc..635ccc66a1 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -9,6 +9,7 @@ #pragma GCC poison TARGET_X86_64 #pragma GCC poison TARGET_AARCH64 #pragma GCC poison TARGET_ALPHA +#pragma GCC poison TARGET_ARC #pragma GCC poison TARGET_ARM #pragma GCC poison TARGET_CRIS #pragma GCC poison TARGET_HPPA @@ -70,6 +71,7 @@ #pragma GCC poison CONFIG_ALPHA_DIS #pragma GCC poison CONFIG_ARM_A64_DIS +#pragma GCC poison CONFIG_ARC_DIS #pragma GCC poison CONFIG_ARM_DIS #pragma GCC poison CONFIG_CRIS_DIS #pragma GCC poison CONFIG_HPPA_DIS diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h index 54f069d491..5fbedebcb0 100644 --- a/include/sysemu/arch_init.h +++ b/include/sysemu/arch_init.h @@ -26,6 +26,7 @@ enum { QEMU_ARCH_RISCV = (1 << 19), QEMU_ARCH_RX = (1 << 20), QEMU_ARCH_AVR = (1 << 21), + QEMU_ARCH_ARC = (1 << 22), QEMU_ARCH_NONE = (1 << 31), }; diff --git a/meson.build b/meson.build index 39ac5cf6d8..6e4f8a2cbb 100644 --- a/meson.build +++ b/meson.build @@ -53,8 +53,8 @@ have_block = have_system or have_tools python = import('python').find_installation() supported_oses = ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', 'sunos', 'linux'] -supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv32', 'riscv64', 'x86', 'x86_64', - 'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64'] +supported_cpus = ['ppc', 'ppc64', 's390x', 'sparc64', 'riscv32', 'riscv64', 'x86', 'x86_64', + 'arc', 'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64'] cpu = host_machine.cpu_family() targetos = host_machine.system() @@ -827,6 +827,7 @@ config_target_mak = {} disassemblers = { 'alpha' : ['CONFIG_ALPHA_DIS'], + 'arc' : ['CONFIG_ARC_DIS'], 'arm' : ['CONFIG_ARM_DIS'], 'avr' : ['CONFIG_AVR_DIS'], 'cris' : ['CONFIG_CRIS_DIS'], diff --git a/softmmu/arch_init.c b/softmmu/arch_init.c index 7fd5c09b2b..27faed5edd 100644 --- a/softmmu/arch_init.c +++ b/softmmu/arch_init.c @@ -92,6 +92,8 @@ int graphic_depth = 32; #define QEMU_ARCH QEMU_ARCH_XTENSA #elif defined(TARGET_AVR) #define QEMU_ARCH QEMU_ARCH_AVR +#elif defined(TARGET_ARC) +#define QEMU_ARCH QEMU_ARCH_ARC #endif const uint32_t arch_type = QEMU_ARCH; diff --git a/target/meson.build b/target/meson.build index 9f0ae93b75..f4a3a6425c 100644 --- a/target/meson.build +++ b/target/meson.build @@ -1,4 +1,5 @@ subdir('alpha') +subdir('arc') subdir('arm') subdir('avr') subdir('cris') From patchwork Wed Nov 11 16:17:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cupertino Miranda X-Patchwork-Id: 1398399 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2001:8b0:10b:1231::1; helo=merlin.infradead.org; envelope-from=linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; 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[2.80.104.46]) by smtp.gmail.com with ESMTPSA id s188sm3115178wmf.45.2020.11.11.08.18.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2020 08:18:23 -0800 (PST) From: cupertinomiranda@gmail.com To: qemu-devel@nongnu.org Subject: [PATCH 14/15] tests/tcg: ARC: Add TCG instruction definition tests Date: Wed, 11 Nov 2020 16:17:57 +0000 Message-Id: <20201111161758.9636-15-cupertinomiranda@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201111161758.9636-1-cupertinomiranda@gmail.com> References: <20201111161758.9636-1-cupertinomiranda@gmail.com> MIME-Version: 1.0 X-Spam-Note: CRM114 run bypassed due to message size (286164 bytes) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:436 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [cupertinomiranda[at]gmail.com] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Claudiu Zissulescu , Cupertino Miranda , Shahab Vahedi , Shahab Vahedi , Cupertino Miranda , linux-snps-arc@lists.infradead.org, Claudiu Zissulescu Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Claudiu Zissulescu The added tests verify basic instructions execution as well as more advanced features such as zero overhead loops interrupt system, memory management unit and memory protection unit. Signed-off-by: Claudiu Zissulescu Signed-off-by: Cupertino Miranda --- tests/Makefile.include | 1 + tests/tcg/arc/Makefile | 114 ++++ tests/tcg/arc/Makefile.softmmu-target | 43 ++ tests/tcg/arc/Makefile.target | 101 ++++ tests/tcg/arc/check_add.S | 11 + tests/tcg/arc/check_addx.S | 71 +++ tests/tcg/arc/check_andx.S | 36 ++ tests/tcg/arc/check_aslx.S | 57 ++ tests/tcg/arc/check_asrx.S | 86 ++++ tests/tcg/arc/check_basic1.S | 30 ++ tests/tcg/arc/check_basic2.S | 26 + tests/tcg/arc/check_beq.S | 14 + tests/tcg/arc/check_beqx.S | 26 + tests/tcg/arc/check_bi.S | 32 ++ tests/tcg/arc/check_big_tb.S | 173 +++++++ tests/tcg/arc/check_bih.S | 29 ++ tests/tcg/arc/check_bnex.S | 26 + tests/tcg/arc/check_breqx.S | 26 + tests/tcg/arc/check_brgex.S | 26 + tests/tcg/arc/check_brhsx.S | 27 + tests/tcg/arc/check_brlox.S | 26 + tests/tcg/arc/check_brltx.S | 26 + tests/tcg/arc/check_brnex.S | 26 + tests/tcg/arc/check_bta.S | 294 +++++++++++ tests/tcg/arc/check_carry.S | 15 + tests/tcg/arc/check_enter_leave.S | 715 ++++++++++++++++++++++++++ tests/tcg/arc/check_excp.S | 17 + tests/tcg/arc/check_excp_1.c | 15 + tests/tcg/arc/check_excp_jumpdl_mmu.S | 44 ++ tests/tcg/arc/check_excp_mmu.S | 69 +++ tests/tcg/arc/check_flags.S | 23 + tests/tcg/arc/check_ldaw_mmu.S | 71 +++ tests/tcg/arc/check_ldstx.S | 37 ++ tests/tcg/arc/check_lp.S | 12 + tests/tcg/arc/check_lp02.S | 72 +++ tests/tcg/arc/check_lp03.S | 49 ++ tests/tcg/arc/check_lp04.S | 48 ++ tests/tcg/arc/check_lp05.S | 23 + tests/tcg/arc/check_lp06.S | 163 ++++++ tests/tcg/arc/check_lsrx.S | 33 ++ tests/tcg/arc/check_mac.S | 228 ++++++++ tests/tcg/arc/check_manip_10_mmu.S | 173 +++++++ tests/tcg/arc/check_manip_4_mmu.S | 158 ++++++ tests/tcg/arc/check_manip_5_mmu.S | 166 ++++++ tests/tcg/arc/check_manip_mmu.S | 565 ++++++++++++++++++++ tests/tcg/arc/check_mmu.S | 59 +++ tests/tcg/arc/check_mpu.S | 703 +++++++++++++++++++++++++ tests/tcg/arc/check_mpyd.S | 543 +++++++++++++++++++ tests/tcg/arc/check_mpyw.S | 41 ++ tests/tcg/arc/check_norm.S | 40 ++ tests/tcg/arc/check_orx.S | 34 ++ tests/tcg/arc/check_prefetch.S | 37 ++ tests/tcg/arc/check_rolx.S | 47 ++ tests/tcg/arc/check_rorx.S | 64 +++ tests/tcg/arc/check_rtc.S | 29 ++ tests/tcg/arc/check_rtie_user.S | 30 ++ tests/tcg/arc/check_stld.S | 10 + tests/tcg/arc/check_subf.S | 67 +++ tests/tcg/arc/check_subx.S | 43 ++ tests/tcg/arc/check_swi.S | 115 +++++ tests/tcg/arc/check_swirq.S | 27 + tests/tcg/arc/check_swirq1.S | 31 ++ tests/tcg/arc/check_swirq3.S | 49 ++ tests/tcg/arc/check_t01.S | 12 + tests/tcg/arc/check_t02.S | 9 + tests/tcg/arc/check_timer0.S | 36 ++ tests/tcg/arc/check_timer0_loop.S | 34 ++ tests/tcg/arc/check_timer0_loop3.S | 46 ++ tests/tcg/arc/check_timer0_retrig.S | 29 ++ tests/tcg/arc/check_timer0_sleep.S | 33 ++ tests/tcg/arc/check_timerX_freq.S | 87 ++++ tests/tcg/arc/check_vadd.S | 510 ++++++++++++++++++ tests/tcg/arc/check_vsub.S | 510 ++++++++++++++++++ tests/tcg/arc/check_xorx.S | 32 ++ tests/tcg/arc/ivt.S | 38 ++ tests/tcg/arc/macros.inc | 261 ++++++++++ tests/tcg/arc/memory.x | 12 + tests/tcg/arc/mmu.inc | 132 +++++ tests/tcg/arc/mpu.inc | 269 ++++++++++ tests/tcg/arc/tarc.ld | 15 + tests/tcg/arc/tarc_mmu.ld | 15 + tests/tcg/arc/test_macros.h | 257 +++++++++ tests/tcg/configure.sh | 3 +- 83 files changed, 8331 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/arc/Makefile create mode 100644 tests/tcg/arc/Makefile.softmmu-target create mode 100644 tests/tcg/arc/Makefile.target create mode 100644 tests/tcg/arc/check_add.S create mode 100644 tests/tcg/arc/check_addx.S create mode 100644 tests/tcg/arc/check_andx.S create mode 100644 tests/tcg/arc/check_aslx.S create mode 100644 tests/tcg/arc/check_asrx.S create mode 100644 tests/tcg/arc/check_basic1.S create mode 100644 tests/tcg/arc/check_basic2.S create mode 100644 tests/tcg/arc/check_beq.S create mode 100644 tests/tcg/arc/check_beqx.S create mode 100644 tests/tcg/arc/check_bi.S create mode 100644 tests/tcg/arc/check_big_tb.S create mode 100644 tests/tcg/arc/check_bih.S create mode 100644 tests/tcg/arc/check_bnex.S create mode 100644 tests/tcg/arc/check_breqx.S create mode 100644 tests/tcg/arc/check_brgex.S create mode 100644 tests/tcg/arc/check_brhsx.S create mode 100644 tests/tcg/arc/check_brlox.S create mode 100644 tests/tcg/arc/check_brltx.S create mode 100644 tests/tcg/arc/check_brnex.S create mode 100644 tests/tcg/arc/check_bta.S create mode 100644 tests/tcg/arc/check_carry.S create mode 100644 tests/tcg/arc/check_enter_leave.S create mode 100644 tests/tcg/arc/check_excp.S create mode 100644 tests/tcg/arc/check_excp_1.c create mode 100644 tests/tcg/arc/check_excp_jumpdl_mmu.S create mode 100644 tests/tcg/arc/check_excp_mmu.S create mode 100644 tests/tcg/arc/check_flags.S create mode 100644 tests/tcg/arc/check_ldaw_mmu.S create mode 100644 tests/tcg/arc/check_ldstx.S create mode 100644 tests/tcg/arc/check_lp.S create mode 100644 tests/tcg/arc/check_lp02.S create mode 100644 tests/tcg/arc/check_lp03.S create mode 100644 tests/tcg/arc/check_lp04.S create mode 100644 tests/tcg/arc/check_lp05.S create mode 100644 tests/tcg/arc/check_lp06.S create mode 100644 tests/tcg/arc/check_lsrx.S create mode 100644 tests/tcg/arc/check_mac.S create mode 100644 tests/tcg/arc/check_manip_10_mmu.S create mode 100644 tests/tcg/arc/check_manip_4_mmu.S create mode 100644 tests/tcg/arc/check_manip_5_mmu.S create mode 100644 tests/tcg/arc/check_manip_mmu.S create mode 100644 tests/tcg/arc/check_mmu.S create mode 100644 tests/tcg/arc/check_mpu.S create mode 100644 tests/tcg/arc/check_mpyd.S create mode 100644 tests/tcg/arc/check_mpyw.S create mode 100644 tests/tcg/arc/check_norm.S create mode 100644 tests/tcg/arc/check_orx.S create mode 100644 tests/tcg/arc/check_prefetch.S create mode 100644 tests/tcg/arc/check_rolx.S create mode 100644 tests/tcg/arc/check_rorx.S create mode 100644 tests/tcg/arc/check_rtc.S create mode 100644 tests/tcg/arc/check_rtie_user.S create mode 100644 tests/tcg/arc/check_stld.S create mode 100644 tests/tcg/arc/check_subf.S create mode 100644 tests/tcg/arc/check_subx.S create mode 100644 tests/tcg/arc/check_swi.S create mode 100644 tests/tcg/arc/check_swirq.S create mode 100644 tests/tcg/arc/check_swirq1.S create mode 100644 tests/tcg/arc/check_swirq3.S create mode 100644 tests/tcg/arc/check_t01.S create mode 100644 tests/tcg/arc/check_t02.S create mode 100644 tests/tcg/arc/check_timer0.S create mode 100644 tests/tcg/arc/check_timer0_loop.S create mode 100644 tests/tcg/arc/check_timer0_loop3.S create mode 100644 tests/tcg/arc/check_timer0_retrig.S create mode 100644 tests/tcg/arc/check_timer0_sleep.S create mode 100644 tests/tcg/arc/check_timerX_freq.S create mode 100644 tests/tcg/arc/check_vadd.S create mode 100644 tests/tcg/arc/check_vsub.S create mode 100644 tests/tcg/arc/check_xorx.S create mode 100644 tests/tcg/arc/ivt.S create mode 100644 tests/tcg/arc/macros.inc create mode 100644 tests/tcg/arc/memory.x create mode 100644 tests/tcg/arc/mmu.inc create mode 100644 tests/tcg/arc/mpu.inc create mode 100644 tests/tcg/arc/tarc.ld create mode 100644 tests/tcg/arc/tarc_mmu.ld create mode 100644 tests/tcg/arc/test_macros.h diff --git a/tests/Makefile.include b/tests/Makefile.include index 3a0524ce74..9dd0472dfa 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -54,6 +54,7 @@ $(BUILD_TCG_TARGET_RULES): build-tcg-tests-%: $(if $(CONFIG_PLUGIN),test-plugins $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) \ -f $(SRC_PATH)/tests/tcg/Makefile.qemu \ SRC_PATH=$(SRC_PATH) \ + BUILD_DIR=$(BUILD_DIR) \ V="$(V)" TARGET="$*" guest-tests, \ "BUILD", "TCG tests for $*") diff --git a/tests/tcg/arc/Makefile b/tests/tcg/arc/Makefile new file mode 100644 index 0000000000..81226d294e --- /dev/null +++ b/tests/tcg/arc/Makefile @@ -0,0 +1,114 @@ +-include ../../../config-host.mak + +CROSS = arc-elf32- +#CROSS = arc-snps-linux-uclibc- + +SIM = ../../../arc-softmmu/qemu-system-arc +SIM_FLAGS = -M arc-sim -m 3G -nographic -no-reboot -monitor none \ + -serial stdio -global cpu.mpu-numreg=8 -kernel +#SIM_FLAGS=-cpu archs +TST_PATH = $(SRC_PATH)/tests/tcg/arc + +CC = $(CROSS)gcc +LD = $(CROSS)ld +AS = $(CROSS)as +CFLAGS = -mcpu=archs -O2 --specs=qemu.specs +ASFLAGS = -mcpu=archs + +TESTCASES = check_add.tst +TESTCASES += check_lp.tst +TESTCASES += check_lp02.tst +TESTCASES += check_lp03.tst +TESTCASES += check_lp04.tst +TESTCASES += check_lp05.tst +TESTCASES += check_lp06.tst +TESTCASES += check_addx.tst +TESTCASES += check_andx.tst +TESTCASES += check_aslx.tst +TESTCASES += check_asrx.tst +TESTCASES += check_orx.tst +TESTCASES += check_rolx.tst +TESTCASES += check_rorx.tst +TESTCASES += check_subx.tst +TESTCASES += check_xorx.tst +TESTCASES += check_beqx.tst +TESTCASES += check_bnex.tst +TESTCASES += check_brhsx.tst +TESTCASES += check_brlox.tst +TESTCASES += check_breqx.tst +TESTCASES += check_brnex.tst +TESTCASES += check_brltx.tst +TESTCASES += check_brgex.tst +TESTCASES += check_ldstx.tst +TESTCASES += check_stld.tst +TESTCASES += check_lsrx.tst +TESTCASES += check_beq.tst +TESTCASES += check_carry.tst +TESTCASES += check_flags.tst +TESTCASES += check_t01.tst +TESTCASES += check_t02.tst +TESTCASES += check_basic1.tst +TESTCASES += check_basic2.tst +TESTCASES += check_norm.tst +TESTCASES += check_excp.tst +TESTCASES += check_excp_1.ctst +TESTCASES += check_mmu.tst +TESTCASES += check_excp_mmu.tst +TESTCASES += check_excp_jumpdl_mmu.tst +TESTCASES += check_timer0.tst +TESTCASES += check_timer0_loop.tst +TESTCASES += check_timer0_loop3.tst +TESTCASES += check_timer0_retrig.tst +TESTCASES += check_timer0_sleep.tst +TESTCASES += check_timerX_freq.tst +TESTCASES += check_swi.tst +TESTCASES += check_swirq.tst +TESTCASES += check_swirq1.tst +TESTCASES += check_swirq3.tst +TESTCASES += check_mpyw.tst +TESTCASES += check_subf.tst +TESTCASES += check_prefetch.tst +TESTCASES += check_mac.tst +TESTCASES += check_ldaw_mmu.tst +TESTCASES += check_manip_4_mmu.tst +TESTCASES += check_manip_5_mmu.tst +TESTCASES += check_manip_10_mmu.tst +TESTCASES += check_manip_mmu.tst +TESTCASES += check_rtie_user.tst +TESTCASES += check_rtc.tst +TESTCASES += check_mpu.tst +TESTCASES += check_big_tb.tst +TESTCASES += check_enter_leave.tst +TESTCASES += check_bta.tst +TESTCASES += check_vadd.tst +TESTCASES += check_vsub.tst +TESTCASES += check_mpyd.tst +TESTCASES += check_bi.tst +TESTCASES += check_bih.tst + +all: $(TESTCASES) +OBJECTS = ivt.o + +%.o: $(SRC_PATH)/tests/tcg/arc/%.S + echo "Running: $(CC) $(ASFLAGS) -c $< -o $@ -I$(TST_PATH)"; \ + $(CC) $(ASFLAGS) -c $< -o $@ -I$(TST_PATH) + +%_mmu.tst: %_mmu.o ${OBJECTS} $(SRC_PATH)/tests/tcg/arc/macros.inc $(SRC_PATH)/tests/tcg/arc/mmu.inc + echo "Running: $(LD) -T $(TST_PATH)/tarc_mmu.ld ${OBJECTS} $< -o $@"; \ + $(LD) -T $(TST_PATH)/tarc_mmu.ld ${OBJECTS} $< -o $@ + +%.tst: %.o ${OBJECTS} $(SRC_PATH)/tests/tcg/arc/macros.inc + echo "Running: $(LD) -T $(TST_PATH)/tarc.ld ${OBJECTS} $< -o $@"; \ + $(LD) -T $(TST_PATH)/tarc.ld ${OBJECTS} $< -o $@ + +%.ctst: $(SRC_PATH)/tests/tcg/arc/%.c + $(CC) $(CFLAGS) -Wl,-marcv2elfx -L $(SRC_PATH)/tests/tcg/arc/ $< -o $@ + +check: $(TESTCASES) + @for case in $(TESTCASES); do \ + echo $(SIM) $(SIM_FLAGS) ./$$case;\ + $(SIM) $(SIM_FLAGS) ./$$case; \ + done + +clean: + $(RM) -rf $(TESTCASES) diff --git a/tests/tcg/arc/Makefile.softmmu-target b/tests/tcg/arc/Makefile.softmmu-target new file mode 100644 index 0000000000..3a0db7ef8c --- /dev/null +++ b/tests/tcg/arc/Makefile.softmmu-target @@ -0,0 +1,43 @@ +# +# ARC softmmu tests +# + +ARC_SRC = $(SRC_PATH)/tests/tcg/arc +ARC_ALL = $(filter-out $(ARC_SRC)/ivt.S,$(wildcard $(ARC_SRC)/*.S)) +ARC_TESTS = $(patsubst $(ARC_SRC)/%.S, %, $(ARC_ALL)) + +# Filter out common blobs and broken tests +ARC_BROKEN_TESTS = check_carry check_excp_jumpdl_mmu +ARC_USABLE_TESTS = $(filter-out $(ARC_BROKEN_TESTS), $(ARC_TESTS)) + +# add to the list of tests +TESTS += $(ARC_USABLE_TESTS) +VPATH += $(ARC_SRC) + +QEMU_OPTS+=-M arc-sim -m 3G -nographic -no-reboot -serial stdio -global cpu.mpu-numreg=8 -kernel + +CROSS = arc-elf32- + +ASFLAGS = -mcpu=archs +LDFLAGS = --specs=qemu.specs -T $(ARC_SRC)/tarc.ld -nostartfiles -nostdlib +MMU_LDFLAGS = --specs=qemu.specs -T $(ARC_SRC)/tarc_mmu.ld -nostartfiles -nostdlib +CRT = ivt.o + +SIM = ../../../qemu-system-arc +SIM_FLAGS = -M arc-sim -m 3G -nographic -no-reboot -monitor none \ + -serial stdio -global cpu.mpu-numreg=8 -kernel + +$(ARC_USABLE_TESTS): $(CRT) Makefile.softmmu-target + +# special rule for common blobs +%.o: %.S + cd ${BUILD_DIR} && \ + $(CC) -I$(ARC_SRC) $($*ASFLAGS) $(ASFLAGS) $(EXTRACFLAGS) -c $< -o ./$@ + +%_mmu: %_mmu.o + cd ${BUILD_DIR} && \ + $(CC) -I$(ARC_SRC) $(ASFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(MMU_LDFLAGS) $(NOSTDFLAGS) $(CRT) + +%: %.o + cd ${BUILD_DIR} && \ + $(CC) -I$(ARC_SRC) $(ASFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) $(NOSTDFLAGS) $(CRT) diff --git a/tests/tcg/arc/Makefile.target b/tests/tcg/arc/Makefile.target new file mode 100644 index 0000000000..abbf1a7b79 --- /dev/null +++ b/tests/tcg/arc/Makefile.target @@ -0,0 +1,101 @@ +# -*- Mode: makefile -*- +# +# ARC specific tweaks + +ARC_SRC=$(SRC_PATH)/tests/tcg/arc-softmmu +VPATH+=$(ARC_SRC) + +ARC_TESTS = check_add.tst +ARC_TESTS += check_lp.tst +ARC_TESTS += check_lp02.tst +ARC_TESTS += check_lp03.tst +ARC_TESTS += check_lp04.tst +ARC_TESTS += check_lp05.tst +ARC_TESTS += check_lp06.tst +ARC_TESTS += check_addx.tst +ARC_TESTS += check_andx.tst +ARC_TESTS += check_aslx.tst +ARC_TESTS += check_asrx.tst +ARC_TESTS += check_orx.tst +ARC_TESTS += check_rolx.tst +ARC_TESTS += check_rorx.tst +ARC_TESTS += check_subx.tst +ARC_TESTS += check_xorx.tst +ARC_TESTS += check_beqx.tst +ARC_TESTS += check_bnex.tst +ARC_TESTS += check_brhsx.tst +ARC_TESTS += check_brlox.tst +ARC_TESTS += check_breqx.tst +ARC_TESTS += check_brnex.tst +ARC_TESTS += check_brltx.tst +ARC_TESTS += check_brgex.tst +ARC_TESTS += check_ldstx.tst +ARC_TESTS += check_stld.tst +ARC_TESTS += check_lsrx.tst +ARC_TESTS += check_beq.tst +ARC_TESTS += check_carry.tst +ARC_TESTS += check_flags.tst +ARC_TESTS += check_t01.tst +ARC_TESTS += check_t02.tst +ARC_TESTS += check_basic1.tst +ARC_TESTS += check_basic2.tst +ARC_TESTS += check_norm.tst +ARC_TESTS += check_excp.tst +ARC_TESTS += check_excp_1.ctst +ARC_TESTS += check_mmu.tst +ARC_TESTS += check_excp_mmu.tst +ARC_TESTS += check_excp_jumpdl_mmu.tst +ARC_TESTS += check_timer0.tst +ARC_TESTS += check_timer0_loop.tst +ARC_TESTS += check_timer0_loop3.tst +ARC_TESTS += check_timer0_retrig.tst +ARC_TESTS += check_timer0_sleep.tst +ARC_TESTS += check_timerX_freq.tst +ARC_TESTS += check_swi.tst +ARC_TESTS += check_swirq.tst +ARC_TESTS += check_swirq1.tst +ARC_TESTS += check_swirq3.tst +ARC_TESTS += check_mpyw.tst +ARC_TESTS += check_subf.tst +ARC_TESTS += check_prefetch.tst +ARC_TESTS += check_mac.tst +ARC_TESTS += check_ldaw_mmu.tst +ARC_TESTS += check_manip_4_mmu.tst +ARC_TESTS += check_manip_5_mmu.tst +ARC_TESTS += check_manip_10_mmu.tst +ARC_TESTS += check_manip_mmu.tst +ARC_TESTS += check_rtie_user.tst +ARC_TESTS += check_rtc.tst +ARC_TESTS += check_mpu.tst +ARC_TESTS += check_big_tb.tst +ARC_TESTS += check_enter_leave.tst +ARC_TESTS += check_bta.tst +ARC_TESTS += check_vadd.tst +ARC_TESTS += check_vsub.tst +ARC_TESTS += check_mpyd.tst + +TESTS+=$(ARC_TESTS) + +%.o: $(ARC_SRC)/%.S + echo "Running: $(CC) $(ASFLAGS) -c $< -o $@ -I$(TST_PATH)"; \ + $(CC) $(ASFLAGS) -c $< -o $@ -I$(TST_PATH) + +%_mmu.tst: %_mmu.o ${OBJECTS} $(ARC_SRC)/macros.inc $(ARC_SRC)/mmu.inc + echo "Running: $(LD) -T $(TST_PATH)/tarc_mmu.ld ${OBJECTS} $< -o $@"; \ + $(LD) -T $(TST_PATH)/tarc_mmu.ld ${OBJECTS} $< -o $@ + +%.tst: %.o ${OBJECTS} $(ARC_SRC)/macros.inc + echo "Running: $(LD) -T $(TST_PATH)/tarc.ld ${OBJECTS} $< -o $@"; \ + $(LD) -T $(TST_PATH)/tarc.ld ${OBJECTS} $< -o $@ + +%.ctst: $(ARC_SRC)/%.c + $(CC) $(CFLAGS) -Wl,-marcv2elfx -L $(ARC_SRC)/ $< -o $@ + +#test-cmov: EXTRA_CFLAGS=-DTEST_CMOV +#test-cmov: test-cond.c +# $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) +# +#run-test-cmov: test-cmov +# +## On Alpha Linux only supports 8k pages +#EXTRA_RUNS+=run-test-mmap-8192 diff --git a/tests/tcg/arc/check_add.S b/tests/tcg/arc/check_add.S new file mode 100644 index 0000000000..be400cf788 --- /dev/null +++ b/tests/tcg/arc/check_add.S @@ -0,0 +1,11 @@ +.include "macros.inc" + + start + + test_name ADD_1 + mov r2,0x10ff01ff + mov r3,0x10010001 + add r2,r2,r3 + check_r2 0x21000200 + + end diff --git a/tests/tcg/arc/check_addx.S b/tests/tcg/arc/check_addx.S new file mode 100644 index 0000000000..467679823f --- /dev/null +++ b/tests/tcg/arc/check_addx.S @@ -0,0 +1,71 @@ +#define ARCTEST_ARC32 + +#***************************************************************************** +# add.S +#----------------------------------------------------------------------------- +# +# Test add instruction. +# + +#include "test_macros.h" + +ARCTEST_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, add, 0x00000000, 0x00000000, 0x000 ) + TEST_IMM_OP( 3, add, 0x00000002, 0x00000001, 0x001 ) + TEST_IMM_OP( 4, add, 0x0000000a, 0x00000003, 0x007 ) + + TEST_IMM_OP( 5, add, 0xfffffffffffff800, 0x0000000000000000, 0x800 ) + TEST_IMM_OP( 6, add, 0xffffffff80000000, 0xffffffff80000000, 0x000 ) + TEST_IMM_OP( 7, add, 0xffffffff7ffff800, 0xffffffff80000000, 0x800 ) + + TEST_IMM_OP( 8, add, 0x00000000000007ff, 0x00000000, 0x7ff ) + TEST_IMM_OP( 9, add, 0x000000007fffffff, 0x7fffffff, 0x000 ) + TEST_IMM_OP( 10, add, 0x00000000800007fe, 0x7fffffff, 0x7ff ) + + TEST_IMM_OP( 11, add, 0xffffffff800007ff, 0xffffffff80000000, 0x7ff ) + TEST_IMM_OP( 12, add, 0x000000007ffff7ff, 0x000000007fffffff, 0x800 ) + + TEST_IMM_OP( 13, add, 0xffffffffffffffff, 0x0000000000000000, 0xfff ) + TEST_IMM_OP( 14, add, 0x0000000000000000, 0xffffffffffffffff, 0x001 ) + TEST_IMM_OP( 15, add, 0xfffffffffffffffe, 0xffffffffffffffff, 0xfff ) + + TEST_IMM_OP( 16, add, 0x0000000080000000, 0x7fffffff, 0x001 ) + + TEST_RR_3OP( 17, add, 0x00000000, 0x00000000, 0x00000000 ) + TEST_RR_3OP( 18, add, 0x00000002, 0x00000001, 0x00000001 ) + TEST_RR_3OP( 19, add, 0x0000000a, 0x00000003, 0x00000007 ) + + TEST_RR_3OP( 20, add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ) + TEST_RR_3OP( 21, add, 0xffffffff80000000, 0xffffffff80000000, 0x00000000 ) + TEST_RR_3OP( 22, add, 0xffffffff7fff8000, 0xffffffff80000000, 0xffffffffffff8000 ) + + TEST_RR_3OP( 23, add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ) + TEST_RR_3OP( 24, add, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ) + TEST_RR_3OP( 25, add, 0x0000000080007ffe, 0x000000007fffffff, 0x0000000000007fff ) + + TEST_RR_3OP( 26, add, 0xffffffff80007fff, 0xffffffff80000000, 0x0000000000007fff ) + TEST_RR_3OP( 27, add, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 ) + + TEST_RR_3OP( 28, add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ) + TEST_RR_3OP( 29, add, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000001 ) + TEST_RR_3OP( 30, add, 0xfffffffffffffffe, 0xffffffffffffffff, 0xffffffffffffffff ) + + TEST_RR_3OP( 31, add, 0x0000000080000000, 0x0000000000000001, 0x000000007fffffff ) + + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 32, add, 24, 13, 11 ) + + TEST_RR_SRC1_EQ_DEST( 33, add, 24, 13, 11 ) + TEST_RR_SRC2_EQ_DEST( 34, add, 25, 14, 11 ) + TEST_RR_SRC12_EQ_DEST( 35, add, 26, 13 ) + +ARCTEST_END diff --git a/tests/tcg/arc/check_andx.S b/tests/tcg/arc/check_andx.S new file mode 100644 index 0000000000..efdec10ae3 --- /dev/null +++ b/tests/tcg/arc/check_andx.S @@ -0,0 +1,36 @@ +#define ARCTEST_ARC32 + +#***************************************************************************** +# and.S +#----------------------------------------------------------------------------- +# +# Test and instruction. +# + +#include "test_macros.h" + +ARCTEST_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, and, 0xff00ff00, 0xff00ff00, 0xf0f ); + TEST_IMM_OP( 3, and, 0x000000f0, 0x0ff00ff0, 0x0f0 ); + TEST_IMM_OP( 4, and, 0x0000000f, 0x00ff00ff, 0x70f ); + TEST_IMM_OP( 5, and, 0x00000000, 0xf00ff00f, 0x0f0 ); + TEST_RR_3OP( 6, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_3OP( 7, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_3OP( 8, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_3OP( 9, and, 0xf000f000, 0xf00ff00f, 0xf0f0f0f0 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 10, and, 0x00000000, 0xff00ff00, 0x0f0 ); + TEST_RR_SRC1_EQ_DEST( 11, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 12, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC12_EQ_DEST( 13, and, 0xff00ff00, 0xff00ff00 ); + +ARCTEST_END diff --git a/tests/tcg/arc/check_aslx.S b/tests/tcg/arc/check_aslx.S new file mode 100644 index 0000000000..77eb3c65cc --- /dev/null +++ b/tests/tcg/arc/check_aslx.S @@ -0,0 +1,57 @@ +#define ARCTEST_ARC32 + +#***************************************************************************** +# check_aslx.S +#----------------------------------------------------------------------------- +# +# Test or instruction. +# +# .--------------.----------.--------------. +# | instruction | check CC | update flags | +# |--------------+----------+--------------| +# | asl | no | Z, N, C, V | +# | asl multiple | yes | Z, N, C | +# `--------------^----------^--------------' + +#include "test_macros.h" + +ARCTEST_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + TEST_RR_3OP(2, asl, 0x12345678, 0x12345678, 0); + TEST_RR_3OP(3, asl, 0x23456780, 0x12345678, 4); + TEST_RR_3OP(4, asl, 0x80000000, 0x12345671, 31); + + TEST_RR_2OP(5, asl, 0x00000002, 0x00000001); + TEST_RR_2OP(6, asl, 0x00000000, 0x80000000); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + TEST_RR_SRC1_EQ_DEST (7, asl, 0xf7780000, 0xdeedbeef, 0x00000013); + TEST_RR_2OP_SRC1_EQ_DEST(8, asl, 0x000804ca, 0x80040265); + + #------------------------------------------------------------- + # Flag tests + #------------------------------------------------------------- + TEST_2OP_CARRY ( 9, asl, 0, 0x10000000, 0x02); + TEST_2OP_CARRY (10, asl, 1, 0x80000000, 0x01); + TEST_2OP_CARRY (11, asl, 0, 0xffffffff, 0x00); + TEST_2OP_ZERO (12, asl, 1, 0x12345670, 0xbf); + TEST_2OP_NEGATIVE(13, asl, 1, 0x1F345678, 0x04); + # no overflow flag update in "asl multiple" + TEST_2OP_OVERFLOW(14, asl, 0, 0x80000000, 0x01); + + TEST_1OP_CARRY (15, asl, 0, 0x40000000); + TEST_1OP_CARRY (16, asl, 1, 0x80000000); + TEST_1OP_ZERO (17, asl, 0, 0x00001000); + TEST_1OP_ZERO (18, asl, 1, 0x80000000); + TEST_1OP_NEGATIVE(19, asl, 0, 0x20000000); + TEST_1OP_NEGATIVE(20, asl, 1, 0x40000000); + TEST_1OP_OVERFLOW(21, asl, 1, 0x80000000); + TEST_1OP_OVERFLOW(22, asl, 0, 0xffffffff); + TEST_1OP_OVERFLOW(23, asl, 1, 0x40000000); + +ARCTEST_END diff --git a/tests/tcg/arc/check_asrx.S b/tests/tcg/arc/check_asrx.S new file mode 100644 index 0000000000..6729f0c42b --- /dev/null +++ b/tests/tcg/arc/check_asrx.S @@ -0,0 +1,86 @@ +#define ARCTEST_ARC32 + +#***************************************************************************** +# check_asrx.S +#----------------------------------------------------------------------------- +# +# Test or instruction. +# +# .--------------.----------.--------------. +# | instruction | check CC | update flags | +# |--------------+----------+--------------| +# | asr | no | Z, N, C | +# | asr multiple | yes | Z, N, C | +# | asr8 | no | Z, N | +# | asr16 | no | Z, N | +# `--------------^----------^--------------' + +#include "test_macros.h" + +ARCTEST_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + TEST_RR_3OP( 2, asr , 0x12345678, 0x12345678, 0); + TEST_RR_3OP( 3, asr , 0x01234567, 0x12345678, 4); + TEST_RR_3OP( 4, asr , 0xFF234567, 0xF2345678, 4); + TEST_RR_3OP( 5, asr , 0xffffffff, 0x8fffffff, 31); + TEST_RR_3OP( 6, asr , 0x00000001, 0x7fffffff, 30); + + TEST_RR_2OP( 7, asr , 0x00000009, 0x00000012); + TEST_RR_2OP( 8, asr , 0xc0000000, 0x80000000); + TEST_RR_2OP( 9, asr , 0x20000000, 0x40000000); + + TEST_RR_2OP(10, asr8 , 0x00000100, 0x00010000); + TEST_RR_2OP(11, asr8 , 0xffff0000, 0xff000000); + TEST_RR_2OP(12, asr8 , 0xff800000, 0x80000000); + TEST_RR_2OP(13, asr8 , 0x007f0000, 0x7f000000); + TEST_RR_2OP(14, asr8 , 0x00000000, 0x000000ff); + + TEST_RR_2OP(15, asr16, 0x00000001, 0x00010000); + TEST_RR_2OP(16, asr16, 0xffffffff, 0xffff0000); + TEST_RR_2OP(17, asr16, 0xffff8000, 0x80000000); + TEST_RR_2OP(18, asr16, 0x00007fff, 0x7fff0000); + TEST_RR_2OP(19, asr16, 0x00000000, 0x0000ff00); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + TEST_RR_SRC1_EQ_DEST (20, asr , 0xfffffbdd, 0xdeedbeef, 0x00000013); + TEST_RR_2OP_SRC1_EQ_DEST(21, asr , 0xc0020132, 0x80040265); + TEST_RR_2OP_SRC1_EQ_DEST(22, asr8 , 0xff800402, 0x80040265); + TEST_RR_2OP_SRC1_EQ_DEST(23, asr16, 0xffff8004, 0x80040265); + + #------------------------------------------------------------- + # Flag tests + #------------------------------------------------------------- + TEST_2OP_CARRY (24, asr , 0, 0x00000001, 0x02); + TEST_2OP_CARRY (25, asr , 1, 0x00000001, 0x01); + TEST_2OP_ZERO (26, asr , 0, 0x00000004, 0x02); + TEST_2OP_ZERO (27, asr , 1, 0x12345678, 0xbf); + TEST_2OP_NEGATIVE(28, asr , 1, 0xFF345678, 0x04); + TEST_2OP_NEGATIVE(29, asr , 0, 0x7F345678, 0x04); + + TEST_1OP_CARRY (30, asr , 0, 0x00000002); + TEST_1OP_CARRY (31, asr , 1, 0x00000001); + TEST_1OP_ZERO (32, asr , 0, 0x00000002); + TEST_1OP_ZERO (33, asr , 1, 0x00000001); + TEST_1OP_NEGATIVE(34, asr , 1, 0x80000000); + TEST_1OP_NEGATIVE(35, asr , 0, 0x7fffffff); + + TEST_1OP_CARRY (36, asr8 , 0, 0x0000007f); + TEST_1OP_CARRY (37, asr8 , 0, 0xffffffff); + TEST_1OP_ZERO (38, asr8 , 0, 0x00000100); + TEST_1OP_ZERO (39, asr8 , 1, 0x000000ff); + TEST_1OP_NEGATIVE(40, asr8 , 1, 0x80000000); + TEST_1OP_NEGATIVE(41, asr8 , 0, 0x7fffffff); + + TEST_1OP_CARRY (42, asr16, 0, 0x00007fff); + TEST_1OP_CARRY (43, asr16, 0, 0xffffffff); + TEST_1OP_ZERO (44, asr16, 0, 0x00010000); + TEST_1OP_ZERO (45, asr16, 1, 0x0000ffff); + TEST_1OP_NEGATIVE(46, asr16, 1, 0x80000000); + TEST_1OP_NEGATIVE(47, asr16, 0, 0x7fffffff); + +ARCTEST_END diff --git a/tests/tcg/arc/check_basic1.S b/tests/tcg/arc/check_basic1.S new file mode 100644 index 0000000000..b26c548bc2 --- /dev/null +++ b/tests/tcg/arc/check_basic1.S @@ -0,0 +1,30 @@ +#define ARCTEST_ARC32 + +#***************************************************************************** +# ror.S +#----------------------------------------------------------------------------- +# +# Test or instruction. +# + +#include "test_macros.h" + +ARCTEST_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + TEST_RR_3OP( 2, ror, 0xca000804, 0x000804ca, 0xfff80008); + TEST_RR_3OP( 3, add1, 0x00000096, 0x00000002, 0x0000004a); + TEST_RR_3OP( 4, add2, 0x0000025a, 0x00000002, 0x00000096); + TEST_RR_3OP( 5, asr, 0x000007da, 0x00000fb5, 0xfff00001); + TEST_RR_3OP( 6, bic, 0x01010101, 0x29292909, 0x2a2a2a0a); + TEST_RR_3OP( 7, rsub, 0x00000011, 0x50005134, 0x50005145); + TEST_RR_3OP( 8, sub1, 0xfffff720, 0x0000046e, 0x000006a7); + TEST_RR_3OP( 9, sub3, 0xfffff9e4, 0x000008ac, 0x000001d9); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + +ARCTEST_END diff --git a/tests/tcg/arc/check_basic2.S b/tests/tcg/arc/check_basic2.S new file mode 100644 index 0000000000..31de81a2e4 --- /dev/null +++ b/tests/tcg/arc/check_basic2.S @@ -0,0 +1,26 @@ +#define ARCTEST_ARC32 + +#***************************************************************************** +# ror.S +#----------------------------------------------------------------------------- +# +# Test or instruction. +# + +#include "test_macros.h" + +ARCTEST_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + TEST_RR_3OP( 2, bmsk, 0x010101FF, 0x010101FF, 0x800289bf); + TEST_RR_3OP( 3, bmsk, 0x00000001, 0x01010101, 0x89000007); + TEST_RR_3OP( 4, min, 0xffffff00, 0xffffff00, 0x000000ff); + TEST_RR_3OP( 5, lsr, 0x658403fd, 0xcb0807fb, 0x89000001); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + +ARCTEST_END diff --git a/tests/tcg/arc/check_beq.S b/tests/tcg/arc/check_beq.S new file mode 100644 index 0000000000..841f4c6760 --- /dev/null +++ b/tests/tcg/arc/check_beq.S @@ -0,0 +1,14 @@ +.include "macros.inc" + + start + test_name BEQ_1 + mov.f r2,0 + beq 1f + check_r2 0x01 +1: + beq.d 2f + mov r2,0x01 + check_r2 0x00 +2: + check_r2 0x01 + end diff --git a/tests/tcg/arc/check_beqx.S b/tests/tcg/arc/check_beqx.S new file mode 100644 index 0000000000..2c246da2ce --- /dev/null +++ b/tests/tcg/arc/check_beqx.S @@ -0,0 +1,26 @@ +#***************************************************************************** +# beq.S +#----------------------------------------------------------------------------- +# +# Test beq instruction. +# + +#define ARCTEST_ARC32 +#include "test_macros.h" + +ARCTEST_BEGIN + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR2_OP_TAKEN( 2, beq, 0, 0 ); + TEST_BR2_OP_TAKEN( 3, beq, 1, 1 ); + TEST_BR2_OP_TAKEN( 4, beq, -1, -1 ); + + TEST_BR2_OP_NOTTAKEN( 5, beq, 0, 1 ); + TEST_BR2_OP_NOTTAKEN( 6, beq, 1, 0 ); + TEST_BR2_OP_NOTTAKEN( 7, beq, -1, 1 ); + TEST_BR2_OP_NOTTAKEN( 8, beq, 1, -1 ); +ARCTEST_END diff --git a/tests/tcg/arc/check_bi.S b/tests/tcg/arc/check_bi.S new file mode 100644 index 0000000000..f71748a346 --- /dev/null +++ b/tests/tcg/arc/check_bi.S @@ -0,0 +1,32 @@ + .include "macros.inc" + + start + test_name BI + mov_s r0,0 +.Lloop: + bi [r0] + b @.L1 + b @.L2 + b @.L3 + b @.L4 + b @.Lfail + b @.Lfail + b @.Lfail +.L1: + add r0,r0,1 + print "[PASS] BI:jmp0\n" + b @.Lloop +.L2: + add r0,r0,1 + print "[PASS] BI:jmp1\n" + b @.Lloop +.L3: + add r0,r0,1 + print "[PASS] BI:jmp2\n" + b @.Lloop +.L4: + print "[PASS] BI\n" + end +.Lfail: + print "[FAIL] BI\n" + end diff --git a/tests/tcg/arc/check_big_tb.S b/tests/tcg/arc/check_big_tb.S new file mode 100644 index 0000000000..1c22b811ae --- /dev/null +++ b/tests/tcg/arc/check_big_tb.S @@ -0,0 +1,173 @@ +.equ POWER_DEVICE, 0xF0000008 ; power management device + +.text +.global main +.align 4 +main: + +add3 r6,sp,0x38 +mov_s r7,0x152f8 +ldd r4r5,[r7] +ldd r2r3,[r7,8] +std r4r5,[r6] +ldd r4r5,[r7,16] +std r2r3,[r6,8] +ldd r2r3,[r7,24] +std r4r5,[r6,16] +std r2r3,[r6,24] +add3 r6,sp,0x34 +mov_s r7,0x152d8 +ldd r4r5,[r7] +ldd r2r3,[r7,8] +std r4r5,[r6] +ldd r4r5,[r7,16] +std r2r3,[r6,8] +ldd r2r3,[r7,24] +std r4r5,[r6,16] +std r2r3,[r6,24] +add3 r6,sp,0x30 +mov_s r7,0x152b8 +ldd r4r5,[r7] +ldd r2r3,[r7,8] +std r4r5,[r6] +ldd r4r5,[r7,16] +std r2r3,[r6,8] +ldd r2r3,[r7,24] +std r4r5,[r6,16] +std r2r3,[r6,24] +add3 r6,sp,0x2c +mov_s r7,0x15298 +ldd r4r5,[r7] +ldd r2r3,[r7,8] +std r4r5,[r6] +ldd r4r5,[r7,16] +std r2r3,[r6,8] +ldd r2r3,[r7,24] +std r4r5,[r6,16] +std r2r3,[r6,24] +add3 r6,sp,0x28 +mov_s r7,0x15278 +ldd r4r5,[r7] +ldd r2r3,[r7,8] +std r4r5,[r6] +ldd r4r5,[r7,16] +std r2r3,[r6,8] +ldd r2r3,[r7,24] +std r4r5,[r6,16] +std r2r3,[r6,24] +add3 r6,sp,0x24 +mov_s r7,0x15258 +ldd r4r5,[r7] +ldd r2r3,[r7,8] +std r4r5,[r6] +ldd r4r5,[r7,16] +std r2r3,[r6,8] +ldd r2r3,[r7,24] +std r4r5,[r6,16] +std r2r3,[r6,24] +add3 r6,sp,0x20 +mov_s r7,0x15238 +ldd r4r5,[r7] +ldd r2r3,[r7,8] +std r4r5,[r6] +ldd r4r5,[r7,16] +std r2r3,[r6,8] +ldd r2r3,[r7,24] +std r4r5,[r6,16] +std r2r3,[r6,24] +add3 r6,sp,0x1c +mov_s r7,0x15218 +ldd r4r5,[r7] +ldd r2r3,[r7,8] +std r4r5,[r6] +ldd r4r5,[r7,16] +std r2r3,[r6,8] +ldd r2r3,[r7,24] +std r4r5,[r6,16] +std r2r3,[r6,24] +add3 r6,sp,0x18 +mov_s r7,0x151f8 +ldd r4r5,[r7] +ldd r2r3,[r7,8] +std r4r5,[r6] +ldd r4r5,[r7,16] +std r2r3,[r6,8] +ldd r2r3,[r7,24] +std r4r5,[r6,16] +std r2r3,[r6,24] +add3 r6,sp,0x14 +mov_s r7,0x151d8 +ldd r4r5,[r7] +ldd r2r3,[r7,8] +std r4r5,[r6] +ldd r4r5,[r7,16] +std r2r3,[r6,8] +ldd r2r3,[r7,24] +std r4r5,[r6,16] +std r2r3,[r6,24] +add3 r6,sp,0x10 +mov_s r7,0x151b8 +ldd r4r5,[r7] +ldd r2r3,[r7,8] +std r4r5,[r6] +ldd r4r5,[r7,16] +std r2r3,[r6,8] +ldd r2r3,[r7,24] +std r4r5,[r6,16] +std r2r3,[r6,24] +add3 r6,sp,0xc +mov_s r7,0x15198 +ldd r4r5,[r7] +ldd r2r3,[r7,8] +std r4r5,[r6] +ldd r4r5,[r7,16] +std r2r3,[r6,8] +ldd r2r3,[r7,24] +std r4r5,[r6,16] +std r2r3,[r6,24] +add3 r6,sp,0x8 +mov_s r7,0x15178 +ldd r4r5,[r7] +ldd r2r3,[r7,8] +std r4r5,[r6] +ldd r4r5,[r7,16] +std r2r3,[r6,8] +ldd r2r3,[r7,24] +std r4r5,[r6,16] +std r2r3,[r6,24] +add r6,sp,0x20 +mov_s r7,0x15158 +ldd r4r5,[r7] +ldd r2r3,[r7,8] +std r4r5,[r6] +ldd r4r5,[r7,16] +std r2r3,[r6,8] +ldd r2r3,[r7,24] +std r4r5,[r6,16] +std r2r3,[r6,24] +mov_s r6,sp +mov_s r7,0x15138 +ldd r4r5,[r7] +ldd r2r3,[r7,8] +std r4r5,[r6] +ldd r4r5,[r7,16] +std r2r3,[r6,8] +ldd r2r3,[r7,24] +std r4r5,[r6,16] +std r2r3,[r6,24] +ld r0,[0x15118] +ld r1,[0x1511c] +ld r2,[0x15120] +ld r3,[0x15124] +ld r4,[0x15128] +ld r5,[0x1512c] +ld r6,[0x15130] +ld r7,[0x15134] +bl @fin + +nop_s +nop_s +.align 4 + +fin: +st 1, [POWER_DEVICE] diff --git a/tests/tcg/arc/check_bih.S b/tests/tcg/arc/check_bih.S new file mode 100644 index 0000000000..c099d72b96 --- /dev/null +++ b/tests/tcg/arc/check_bih.S @@ -0,0 +1,29 @@ + .include "macros.inc" + + start + test_name BIH + mov_s r0,0 +.Lloop: + bih [r0] + b_s @.L1 + b_s @.L2 + b_s @.L3 + b_s @.L4 + b_s @.Lfail + b_s @.Lfail + b_s @.Lfail +.L1: + add r0,r0,1 + b @.Lloop +.L2: + add r0,r0,1 + b @.Lloop +.L3: + add r0,r0,1 + b @.Lloop +.L4: + print "[PASS] BIH\n" + end +.Lfail: + print "[FAIL] BIH\n" + end diff --git a/tests/tcg/arc/check_bnex.S b/tests/tcg/arc/check_bnex.S new file mode 100644 index 0000000000..4b7c0cfed9 --- /dev/null +++ b/tests/tcg/arc/check_bnex.S @@ -0,0 +1,26 @@ +#***************************************************************************** +# bne.S +#----------------------------------------------------------------------------- +# +# Test bne instruction. +# + +#define ARCTEST_ARC32 +#include "test_macros.h" + +ARCTEST_BEGIN + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR2_OP_TAKEN( 2, bne, 0, 1 ); + TEST_BR2_OP_TAKEN( 3, bne, 1, 0 ); + TEST_BR2_OP_TAKEN( 4, bne, -1, 1 ); + TEST_BR2_OP_TAKEN( 5, bne, 1, -1 ); + + TEST_BR2_OP_NOTTAKEN( 6, bne, 0, 0 ); + TEST_BR2_OP_NOTTAKEN( 7, bne, 1, 1 ); + TEST_BR2_OP_NOTTAKEN( 8, bne, -1, -1 ); +ARCTEST_END diff --git a/tests/tcg/arc/check_breqx.S b/tests/tcg/arc/check_breqx.S new file mode 100644 index 0000000000..a3a3dd1160 --- /dev/null +++ b/tests/tcg/arc/check_breqx.S @@ -0,0 +1,26 @@ +#***************************************************************************** +# breq.S +#----------------------------------------------------------------------------- +# +# Test breq instruction. +# + +#define ARCTEST_ARC32 +#include "test_macros.h" + +ARCTEST_BEGIN + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR_OP_TAKEN( 2, breq, 0, 0 ); + TEST_BR_OP_TAKEN( 3, breq, 1, 1 ); + TEST_BR_OP_TAKEN( 4, breq, -1, -1 ); + + TEST_BR_OP_NOTTAKEN( 5, breq, 0, 1 ); + TEST_BR_OP_NOTTAKEN( 6, breq, 1, 0 ); + TEST_BR_OP_NOTTAKEN( 7, breq, -1, 1 ); + TEST_BR_OP_NOTTAKEN( 8, breq, 1, -1 ); +ARCTEST_END diff --git a/tests/tcg/arc/check_brgex.S b/tests/tcg/arc/check_brgex.S new file mode 100644 index 0000000000..ddd6003b7c --- /dev/null +++ b/tests/tcg/arc/check_brgex.S @@ -0,0 +1,26 @@ +#***************************************************************************** +# brge.S +#----------------------------------------------------------------------------- +# +# Test brge instruction. +# + +#defirge ARCTEST_ARC32 +#include "test_macros.h" + +ARCTEST_BEGIN + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR_OP_NOTTAKEN( 2, brge, 0, 1 ); + TEST_BR_OP_TAKEN( 3, brge, 1, 0 ); + TEST_BR_OP_NOTTAKEN( 4, brge, -1, 1 ); + TEST_BR_OP_TAKEN( 5, brge, 1, -1 ); + + TEST_BR_OP_TAKEN( 6, brge, 0, 0 ); + TEST_BR_OP_TAKEN( 7, brge, 1, 1 ); + TEST_BR_OP_TAKEN( 8, brge, -1, -1 ); +ARCTEST_END diff --git a/tests/tcg/arc/check_brhsx.S b/tests/tcg/arc/check_brhsx.S new file mode 100644 index 0000000000..6a05b53f8e --- /dev/null +++ b/tests/tcg/arc/check_brhsx.S @@ -0,0 +1,27 @@ +#***************************************************************************** +# brhs.S +#----------------------------------------------------------------------------- +# +# Test brhs instruction. +# + +#define ARCTEST_ARC32 +#include "test_macros.h" + +ARCTEST_BEGIN + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR_OP_TAKEN( 2, brhs, 0, 0 ); + TEST_BR_OP_TAKEN( 3, brhs, 1, 1 ); + TEST_BR_OP_TAKEN( 4, brhs, -1, -1 ); + TEST_BR_OP_TAKEN( 5, brhs, -1, 1 ); + + TEST_BR_OP_NOTTAKEN( 6, brhs, 0, 1 ); + TEST_BR_OP_NOTTAKEN( 7, brhs, 1, -1 ); + TEST_BR_OP_NOTTAKEN( 8, brhs, 33, 0x2aaaaaab ); + TEST_BR_OP_NOTTAKEN( 9, brhs, 123, 124 ); +ARCTEST_END diff --git a/tests/tcg/arc/check_brlox.S b/tests/tcg/arc/check_brlox.S new file mode 100644 index 0000000000..53a15b27d1 --- /dev/null +++ b/tests/tcg/arc/check_brlox.S @@ -0,0 +1,26 @@ +#***************************************************************************** +# brlo.S +#----------------------------------------------------------------------------- +# +# Test brlo instruction. +# + +#define ARCTEST_ARC32 +#include "test_macros.h" + +ARCTEST_BEGIN + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR_OP_NOTTAKEN( 2, brlo, 0, 0 ); + TEST_BR_OP_NOTTAKEN( 3, brlo, 1, 1 ); + TEST_BR_OP_NOTTAKEN( 4, brlo, -1, -1 ); + TEST_BR_OP_NOTTAKEN( 5, brlo, -1, 1 ); + + TEST_BR_OP_TAKEN( 6, brlo, 0, 1 ); + TEST_BR_OP_TAKEN( 7, brlo, 1, -1 ); + TEST_BR_OP_TAKEN( 8, brlo, 33, 0x2aaaaaab ); +ARCTEST_END diff --git a/tests/tcg/arc/check_brltx.S b/tests/tcg/arc/check_brltx.S new file mode 100644 index 0000000000..475d3ddf1c --- /dev/null +++ b/tests/tcg/arc/check_brltx.S @@ -0,0 +1,26 @@ +#***************************************************************************** +# brlt.S +#----------------------------------------------------------------------------- +# +# Test brlt instruction. +# + +#defirlt ARCTEST_ARC32 +#include "test_macros.h" + +ARCTEST_BEGIN + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR_OP_TAKEN( 2, brlt, 0, 1 ); + TEST_BR_OP_NOTTAKEN( 3, brlt, 1, 0 ); + TEST_BR_OP_TAKEN( 4, brlt, -1, 1 ); + TEST_BR_OP_NOTTAKEN( 5, brlt, 1, -1 ); + + TEST_BR_OP_NOTTAKEN( 6, brlt, 0, 0 ); + TEST_BR_OP_NOTTAKEN( 7, brlt, 1, 1 ); + TEST_BR_OP_NOTTAKEN( 8, brlt, -1, -1 ); +ARCTEST_END diff --git a/tests/tcg/arc/check_brnex.S b/tests/tcg/arc/check_brnex.S new file mode 100644 index 0000000000..6f37c33930 --- /dev/null +++ b/tests/tcg/arc/check_brnex.S @@ -0,0 +1,26 @@ +#***************************************************************************** +# brne.S +#----------------------------------------------------------------------------- +# +# Test brne instruction. +# + +#defirne ARCTEST_ARC32 +#include "test_macros.h" + +ARCTEST_BEGIN + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR_OP_TAKEN( 2, brne, 0, 1 ); + TEST_BR_OP_TAKEN( 3, brne, 1, 0 ); + TEST_BR_OP_TAKEN( 4, brne, -1, 1 ); + TEST_BR_OP_TAKEN( 5, brne, 1, -1 ); + + TEST_BR_OP_NOTTAKEN( 6, brne, 0, 0 ); + TEST_BR_OP_NOTTAKEN( 7, brne, 1, 1 ); + TEST_BR_OP_NOTTAKEN( 8, brne, -1, -1 ); +ARCTEST_END diff --git a/tests/tcg/arc/check_bta.S b/tests/tcg/arc/check_bta.S new file mode 100644 index 0000000000..abef1a33fc --- /dev/null +++ b/tests/tcg/arc/check_bta.S @@ -0,0 +1,294 @@ +; check_bta.S +; Tests for setting Branch Target Address register. +; The BTA register is updated if and only if the +; branch is going to be taken (cc = true) AND there +; is a delay slot: +; ,-----------.-----------. +; | not taken | taken | +; ,---------------|-----------+-----------| +; | no delay slot | - | - | +; |---------------|-----------+-----------| +; | delay slot | - | UPDATE | +; `---------------^-----------^-----------' +; In other words, BTA is updated only when STATUS32.DE is set. +; +; TODO: Add test cases for Bcc, JL, JLcc, BBITn +; TODO: the following test cases fail in QEMU: 3, 9 +; the condition of the tests are (not taken, delay slot) +; and yet QEMU insists on updating the BTA. + + .include "macros.inc" + +;;;;;;;;;;;;;;;;;;;;;;;;;;; Test checking routines ;;;;;;;;;;;;;;;;;;;;;;;;;; + +.data +; Test case counter +test_nr: + .word 0x0 +; Saved BTA +saved_bta: + .word 0x0 + +; Increment the test counter +.macro prep_test_case + ld r13, [test_nr] + add_s r13, r13, 1 ; Increase test case counter + st r13, [test_nr] + lr r13, [bta] + st r13, [saved_bta] ; Some tests need this to check if BTA changed. +.endm + +; Compares the current BTA with the value saved at the start of a +; test by PREP_TEST_CASE. If not the same, the test will fail. +.macro check_bta_remained_intact + ld r13, [saved_bta] + lr r12, [bta] + cmp r13, r12 + bne @fail +.endm + +; Checks the BTA against the EXPECTED_BTA. +; If they're not the same, the test will fail. +.macro check_bta expected_bta + mov r13, \expected_bta + lr r12, [bta] + cmp r13, r12 + bne @fail +.endm + +; Checks if the given REGs are equal. Fails, if not. +.macro check_equal reg, expected_reg + cmp \expected_reg, \reg + bne @fail +.endm + +; Checks if REG is one number bigger than ORIG_REG. +.macro check_one_above reg, orig_reg + mov r13, \orig_reg + add_s r13, r13, 1 + cmp r13, \reg + bne @fail +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;; Conditonal branches ;;;;;;;;;;;;;;;;;;;;;;;;; + +start + +; Test case 1 +; Conditional branch is not taken and there is no delay slot. +; BTA mustn't be updated. + prep_test_case + ld r0, [test_nr] + add r1, r0, 1 + breq r0, r1, @test_01_target + check_bta_remained_intact + b @test_01_end +test_01_target: + b @fail +test_01_end: + ; Fall through + +; Test case 2 +; Conditional branch is taken but there is no delay slot. +; BTA mustn't be updated. + prep_test_case + ld r0, [test_nr] + mov r1, r0 + breq r0, r1, @test_02_target + b @fail +test_02_target: + check_bta_remained_intact + +; Test case 3 +; Conditional branch is not taken but there is a delay slot. +; BTA mustn't be updated. + prep_test_case + ld r0, [test_nr] + add r1, r0, 1 + breq.d r0, r1, @test_03_target + add_s r0, r0, 1 + check_bta_remained_intact + check_equal r0, r1 + b @test_03_end +test_03_target: + b @fail +test_03_end: + ; Fall through + +; Test case 4 +; Conditional branch is taken AND there is a delay slot. +; BTA must be updated. + prep_test_case + ld r0, [test_nr] + mov r1, r0 + breq.d r0, r1, @test_04_target + add_s r0, r0, 1 + b @fail +test_04_target: + check_bta @test_04_target + check_one_above r0, r1 + +;;;;;;;;;;;;;;;;;;;;;;;; Unconditonal branches ;;;;;;;;;;;;;;;;;;;;;;;; + +; Test case 5 +; Branch unconditionally but there is no delay slot. +; BTA mustn't be updated. + prep_test_case + b @test_05_target + b @fail +test_05_target: + check_bta_remained_intact + +; Test case 6 +; Branch unconditionally AND there is a delay slot. +; BTA must be updated. + prep_test_case + ld r0, [test_nr] + mov r1, r0 + b.d @test_06_target + add_s r0, r0, 1 + b @fail +test_06_target: + check_bta @test_06_target + check_one_above r0, r1 + +;;;;;;;;;;;;;;;;;;;;;;;;;; Conditonal jumps ;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Test case 7 +; Conditional jump is not taken and there is no delay slot. +; BTA mustn't be updated. + prep_test_case + ld r0, [test_nr] + add r1, r0, 1 + cmp r0, r1 + jz @test_07_target + check_bta_remained_intact + b @test_07_end +test_07_target: + b @fail +test_07_end: + ; Fall through + +; Test case 8 +; Conditional jump is taken but there is no delay slot. +; BTA mustn't be updated. + prep_test_case + ld r0, [test_nr] + mov r1, r0 + cmp r0, r1 + jz @test_08_target + add_s r0, r0, 1 + + b @fail +test_08_target: + check_bta_remained_intact + +; Test case 9 +; Conditional jump is not taken but there is a delay slot. +; BTA mustn't be updated. + prep_test_case + ld r0, [test_nr] + add r1, r0, 1 + mov r2, @test_09_target + cmp r0, r1 + jz.d [r2] + add_s r0, r0, 1 + check_bta_remained_intact + check_equal r0, r1 + b @test_09_end +test_09_target: + b @fail +test_09_end: + ; Fall through + +; Test case 10 +; Conditional jump is taken AND there is a delay slot. +; BTA must be updated. + prep_test_case + ld r0, [test_nr] + mov r1, r0 + mov r2, @test_10_target + cmp r0, r1 + jz.d [r2] + add_s r0, r0, 1 + b @fail +test_10_target: + check_bta @test_10_target + check_one_above r0, r1 + +;;;;;;;;;;;;;;;;;;;;;;; Conditonal short jumps ;;;;;;;;;;;;;;;;;;;;;;; + +; Test case 11 +; Conditional short jump is not taken (there can't be a delay slot). +; BTA mustn't be updated. + prep_test_case + ld r0, [test_nr] + add r1, r0, 1 + mov blink, @test_11_target + cmp r0, r1 + jeq_s [blink] + check_bta_remained_intact + check_one_above r1, r0 + b @test_11_end +test_11_target: + b @fail +test_11_end: + ; Fall through + +; Test case 12 +; Conditional short jump is taken (there can't be a delay slot). +; BTA mustn't be updated. + prep_test_case + ld r0, [test_nr] + add r1, r0, 1 + mov blink, @test_12_target + cmp r0, r1 + jne_s [blink] + add_s r0, r0, 1 + b @fail +test_12_target: + check_bta_remained_intact + check_one_above r1, r0 + +;;;;;;;;;;;;;;;;;;;;;;;;; Unconditonal jumps ;;;;;;;;;;;;;;;;;;;;;;;;; + +; Test case 13 +; Jump unconditionally but there is no delay slot. +; BTA mustn't be updated. + prep_test_case + j @test_13_target + b @fail +test_13_target: + check_bta_remained_intact + +; Test case 14 +; Jump unconditionally AND there is a delay slot. +; BTA must be updated. + prep_test_case + ld r0, [test_nr] + mov r1, r0 + mov r2, @test_14_target + j.d [r2] + add_s r0, r0, 1 + b @fail +test_14_target: + check_bta @test_14_target + check_one_above r0, r1 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Reporting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +valhalla: + print "[PASS]" + b @1f + +; If a test fails, it jumps here. Although, for the sake of uniformity, +; the printed output does not say much about which test case failed, +; one can uncomment the print_number line below or set a breakpoint +; here to check the R0 register for the test case number. +fail: + ld r0, [test_nr] + ;print_number r0 + print "[FAIL]" +1: + print " BTA register (implicit) writing\n" + end diff --git a/tests/tcg/arc/check_carry.S b/tests/tcg/arc/check_carry.S new file mode 100644 index 0000000000..5928897911 --- /dev/null +++ b/tests/tcg/arc/check_carry.S @@ -0,0 +1,15 @@ +#define ARCTEST_ARC32 +#include "test_macros.h" + + ARCTEST_BEGIN + +test_2: + mov r0, 10 + mov r1, 12 + cmp r0,r1 ;Carry is set here + mov.lo.f 0, 0x0 + mov.hs.f 0, 0x1 + + bne @fail + + ARCTEST_END diff --git a/tests/tcg/arc/check_enter_leave.S b/tests/tcg/arc/check_enter_leave.S new file mode 100644 index 0000000000..9bb8180b29 --- /dev/null +++ b/tests/tcg/arc/check_enter_leave.S @@ -0,0 +1,715 @@ +;; These are the tests cases for verifying the functionality of +;; enter_s and leave_s. It is assumed that there are 32 general +;; purpose registers available (r0 ... r31). It is also good to +;; remark the aliases for some of the registers: +;; r27: fp +;; r28: sp +;; r31: blink + + .include "macros.inc" + +;;;;;;;;;;;;;;;;;;; / Exception Verification Helpers \ ;;;;;;;;;;;;;;;;;;;;;; +; these are the parameters that the exception routine uses as reference + .data + .align 4 +ecr_ref : .word 0x0 +eret_ref : .word 0x0 +efa_ref : .word 0x0 +erbta_ref : .word 0x0 +cont_addr : .word 0x0 +test_number: .word 0x0 + .text + .align 4 + +; macro: set_excep_params +; regs used: r11 +; +; this macro writes the provided parameters to a temporary place holder +; that later will be used by ProtV exception above to verify as reference +.macro set_excep_params ecr, eret, efa, erbta, continue, test_num + mov r11, \ecr + st r11, [ecr_ref] + mov r11, \efa + st r11, [efa_ref] + mov r11, \eret + st r11, [eret_ref] + mov r11, \erbta + st r11, [erbta_ref] + mov r11, \continue + st r11, [cont_addr] + mov r11, \test_num + st r11, [test_number] +.endm + +; exception verification routine +; regs used: r11, r12 +; +; this is a parameterized exception that will check the followings: +; ecr == ecr_ref +; efa == efa_ref +; eret == eret_ref +; if everything passes, it will jump to 'cont_addr' parameter. it will clear +; the user bit before the jump, ie if an exception is raised in user mode, +; the continuation after exception will be in kernel mode. +; the parameters must be set beforehand using 'set_except_params' macro. +; last but not least, this requires ivt.S file to be compiled and linked. + .align 4 + .global instruction_error + .global EV_Misaligned + .type instruction_error, @function + .type EV_Misaligned, @function +instruction_error: +EV_Misaligned: + ld r11, [ecr_ref] + lr r12, [ecr] + brne r12, r11, @exc_fail + ld r11, [eret_ref] + lr r12, [eret] + brne r12, r11, @exc_fail + ld r11, [efa_ref] + lr r12, [efa] + brne r12, r11, @exc_fail + ld r11, [erbta_ref] + lr r12, [erbta] + brne r12, r11, @exc_fail + ; do not pursue the branch target anymore + lr r11, [erstatus] + and r11, r11, ~0x8040 ; clear ES and DE bit + sr r11, [erstatus] + ; going back to given address + ld r11, [cont_addr] + sr r11, [eret] + rtie +exc_fail: + ld r11, [test_number] + print_number r11 + print "[FAIL] :exception is not sane:" + b @endtest +;;;;;;;;;;;;;;;;;;; \ Exception Verification Helpers / ;;;;;;;;;;;;;;;;;;;;;; + + start + mov sp , 0x1000 ; let's set sp to 0x100 for all the tests + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; u6=0 leads to doing nothing +test00: + mov r10, sp + enter_s 0 ; enter_s [] + brne sp, r10, @test00_fail + j @test01 + +test00_fail: + print "[FAIL] :test00:" + b @endtest + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; saving first 3 general purpose registers +test01: + mov r10, sp ; ,-- top ---. + mov r13, 13 ; | r13 = 13 | + mov r14, 14 ; | r14 = 14 | + mov r15, 15 ; | r15 = 15 | + enter_s [r13-r15] ; `- bottom -' + pop r3 + pop r4 + pop r5 + brne r3, 13, @test01_fail + brne r4, 14, @test01_fail + brne r5, 15, @test01_fail + brne sp, r10, @test01_fail + j @test02 + +test01_fail: + print "[FAIL] :test01:" + b @endtest + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; saving blink register +test02: + mov r10, sp + mov blink, 0x123 + enter_s [blink] + pop r1 + brne r1, 0x123, @test02_fail + brne sp, r10, @test02_fail + j @test03 + +test02_fail: + print "[FAIL] :test02:" + b @endtest + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; saving fp register +test03: + mov r10, sp + mov fp, 0x321 + + enter_s [fp] + mov r9, sp ; save current sp before poping + pop r1 + brne r1, 0x321, @test03_fail + brne fp, r9, @test03_fail + brne sp, r10, @test03_fail + j @test04 + +test03_fail: + print "[FAIL] :test03:" + b @endtest + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; saving all registers + .data + .align 4 +sp_orig: .word 0x0 + .text +test04: + st sp , [sp_orig] ; ,----- top -----. + mov blink, 0x456 ; | blink = 0x456 | + mov r13 , 13 ; | r13 = 13 | + mov r14 , 14 ; | r14 = 14 | + mov r15 , 15 ; | r15 = 15 | + mov r16 , 16 ; | r16 = 16 | + mov r17 , 17 ; | r17 = 17 | + mov r18 , 18 ; | r18 = 18 | + mov r19 , 19 ; | r19 = 19 | + mov r20 , 20 ; | r20 = 20 | + mov r21 , 21 ; | r21 = 21 | + mov r22 , 22 ; | r22 = 22 | + mov r23 , 23 ; | r23 = 23 | + mov r24 , 24 ; | r24 = 24 | + mov r25 , 25 ; | r25 = 25 | + mov r26 , 26 ; | r26 = 26 | + mov fp , 0x789 ; | fp = 0x789 | + enter_s [r13-r26, fp, blink] ; `--- bottom ----' + mov r0, sp ; save current sp before poping + pop r1 ; blink + pop r3 ; r13 + pop r4 ; r14 + pop r5 ; r15 + pop r6 ; r16 + pop r7 ; r17 + pop r8 ; r18 + pop r9 ; r19 + pop r10 ; r20 + pop r11 ; r21 + pop r12 ; r22 + pop r13 ; r23 + pop r14 ; r24 + pop r15 ; r25 + pop r16 ; r26 + pop r2 ; fp + brne fp, r0, @test04_fail ; sp value before all the pops + brne r1, 0x456, @test04_fail ; blink value during save + brne r2, 0x789, @test04_fail ; frame pointer value during save + brne r3, 13, @test04_fail ; stored r13 value + brne r4, 14, @test04_fail ; stored r14 value + brne r5, 15, @test04_fail ; stored r15 value + brne r6, 16, @test04_fail ; stored r16 value + brne r7, 17, @test04_fail ; stored r17 value + brne r8, 18, @test04_fail ; stored r18 value + brne r9, 19, @test04_fail ; stored r19 value + brne r10, 20, @test04_fail ; stored r20 value + brne r11, 21, @test04_fail ; stored r21 value + brne r12, 22, @test04_fail ; stored r22 value + brne r13, 23, @test04_fail ; stored r23 value + brne r14, 24, @test04_fail ; stored r24 value + brne r15, 25, @test04_fail ; stored r25 value + brne r16, 26, @test04_fail ; stored r26 value + ld r10, [sp_orig] ; original sp value spilled + brne sp, r10, @test04_fail ; original sp value + j @test05 + +test04_fail: + print "[FAIL] :test04:" + b @endtest + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; sp's value is not 32-bit aligned --> misaligned exception +; this happens irrelevant of status32.AD bit +test05: + .equ TEST05_SP , 0x111 ; an address which is not 32-bit aligned + .equ TEST05_STACK_SIZE, 60 ; saving r13-r26 (14x4) + fp (4) + .equ TEST05_EFA , TEST05_SP - TEST05_STACK_SIZE + lr r1, [status32] + or r1, r1, 0x80000 ; set AD bit + mov r2, @test05_excep_prep + sr r1, [erstatus] ; enable AD bit + sr r2, [eret] ; continue with the test + rtie + +test05_excep_prep: + lr r7, [erbta] ; don't care for erbta + set_excep_params ecr=MISALIGNED_DATA_ACCESS, \ + eret=@test05_enter , \ + efa=TEST05_EFA , \ + erbta=r7 , \ + continue=@test05_wrapup , \ + test_num=5 + mov r10, sp ; backup sp to restore later + mov sp, TEST05_SP ; an address which is not 32-bit aligned +test05_enter: + enter_s [r13-r26, fp] ; just being flamboyant + print "[FAIL] :test05:" ; this code must not fall through + b @endtest + +test05_wrapup: + mov sp, r10 + lr r1, [status32] + and r1, r1, ~0x80000 ; clear AD bit + mov r2, @test06 ; go to next test + sr r1, [erstatus] ; disable AD bit + sr r2, [eret] ; continue with next test + rtie + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; a delay slot instruction --> illegal instruction sequence exception +; the tricky thing in this test is that gas does not allow us to put +; an "enter_s" in a delay slot (good job there!). however, we work +; around it by writing the opcode at runtime. +test06: + set_excep_params ecr=ILLEGAL_INSTRUCTION_SEQUENCE, \ + eret=@test06_delay , \ + efa=@test06_delay , \ + erbta=@test06_fail , \ + continue=@test07 , \ + test_num=6 + mov r1, 0xc0e2 ; opcode for enter_s [r13] + sth r1, [test06_delay] + b @test06_dummy_tb ; by having 'b' here, it is end of this tb. +test06_dummy_tb: ; so this one will be decoded after mutation. + b.d @test06_fail +test06_delay: + nop_s + nop_s + +test06_fail: + print "[FAIL] :test06:" + b @endtest + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; an execution slot instruction --> illegal instruction sequence exception +; TODO (issue #73): enable this after EI_S has been implemented. +test07: +; mov r1, @test07_ei_table +; sr r1, [ei_base] +; j @test07_begin +; +; .align 4 +;test07_ei_table: +; enter_s [r13] +; +;test07_begin: +; set_excep_params ecr=ILLEGAL_INSTRUCTION_SEQUENCE, \ +; eret=@test07_ei_table , \ +; efa=@test07_ei_table , \ +; erbta=@test07_fail , \ +; continue=@test08 , \ +; test_num=7 +; ei_s 0 +; +;test07_fail: +; print "failed: test07\n" +; end + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; it is allowed to have "enter_s 0" in delay/execution slot because it is +; like a nop then and is not a multi-cycle instruction. +; TODO (issue #73): enable the ei_check part after EI_S has been done. +test08: + mov r1, 0xc0e0 ; opcode for enter_s [] + sth r1, [test08_delay] + b @test08_dummy_tb ; by having 'b' here, it is end of this tb. +test08_dummy_tb: ; so this one will be decoded after mutation. + b.d @test08_ei_check +test08_delay: + nop_s ; at runtime this is enter_s [] and is ok + nop_s + + .align 4 +test08_ei_table: + enter_s 0 + +test08_ei_check: + ; TODO (issue #73): enable after EI_S is implemented. + ;mov r1, @test08_ei_table + ;sr r1, [ei_base] + ;ei_s 0 + ; fall through to the next test + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; 32 general registers configured AND u[3:0] > 14 (r13-r26) +; OR +; 16 general registers configured AND u[3:0] > 3 (r13-r15) +; --> illegal instruction exception +; TODO (issue #52): this test case must be executed with +; -global cpu.num-regs=16. +test09: +; lr r7, [bta] ; don't care for erbta (use current bta) +; set_excep_params ecr=ILLEGAL_INSTRUCTION, \ +; eret=@test09_big_u3 , \ +; efa=@test09_big_u3 , \ +; erbta=r7 , \ +; continue=@test10 , \ +; test_num=9 +;test09_big_u3: ; enter_s encoding : 1100 00UU 111u uuu0 +; enter_s 4 +; +;test09_fail: +; print "failed: test09\n" +; end +;;;;;;;;;;;;;;;;;;;;;;;;;;;; \ Enter Tests / ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +;;;;;;;;;;;;;;;;;;;;;;;;;;;; / Leave Tests \ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; u7=0 leads to doing nothing +test10: + mov r10, sp + leave_s 0 + brne sp, r10, @test10_fail + j @test11 + +test10_fail: + print "[FAIL] :test10:" + b @endtest + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; restoring first 3 general purpose registers +test11: + mov r10, sp ; ,--- top ---. + mov r3, 113 ; | r13 = 113 | + mov r4, 114 ; | r14 = 114 | + mov r5, 115 ; | r15 = 115 | + push r5 ; `-- bottom -' + push r4 + push r3 + leave_s [r13-r15] + brne r13, 113, @test11_fail + brne r14, 114, @test11_fail + brne r15, 115, @test11_fail + brne sp , r10, @test11_fail + j @test12 + +test11_fail: + print "[FAIL] :test11:" + b @endtest + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; restoring blink register +test12: + mov r10, sp + mov r1, 0x10123 + push r1 + leave_s [blink] + brne blink, 0x10123, @test12_fail + brne sp , r10, @test12_fail + j @test13 + +test12_fail: + print "[FAIL] :test12:" + b @endtest + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; restoring fp register +test13: + mov r10, sp + mov r1, 0x11321 + push r1 + mov fp, sp ; fp is pointing current frame now + mov sp, 0x4009 ; botch sp + leave_s [fp] ; 'leave_s' must look into fp for restoring + brne fp, 0x11321, @test13_fail + brne sp, r10, @test13_fail + j @test14 + +test13_fail: + print "[FAIL] :test13" + b @endtest + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; jumping to what blink holds +test14: + mov r10, sp + mov blink, @test14_cont + leave_s [pcl] ; jump to whatever blink points to + j @test14_fail ; this should not be reached +test14_cont: + brne sp, r10, @test14_fail + j @test15 + +test14_fail: + print "[FAIL] :test14:" + b @endtest + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; restoring first 3 general purpose registers +test15: + mov r0 , sp ; ,--------- top ----------. + mov r1 , @test15_return ; | blink = @test15_return | + mov r3 , 213 ; | r3 = 213 | + mov r4 , 214 ; | r4 = 214 | + mov r5 , 215 ; | r5 = 215 | + mov r6 , 216 ; | r6 = 216 | + mov r7 , 217 ; | r7 = 217 | + mov r8 , 218 ; | r8 = 218 | + mov r9 , 219 ; | r9 = 219 | + mov r10, 220 ; | r10 = 220 | + mov r11, 221 ; | r11 = 221 | + mov r12, 222 ; | r12 = 222 | + mov r13, 223 ; | r13 = 223 | + mov r14, 224 ; | r14 = 224 | + mov r15, 225 ; | r15 = 225 | + mov r16, 226 ; | r16 = 226 | + mov r2, 0x14456 ; | fp = 0x14456 | + push r2 ; `-------- bottom --------' + push r16 + push r15 + push r14 + push r13 + push r12 + push r11 + push r10 + push r9 + push r8 + push r7 + push r6 + push r5 + push r4 + push r3 + push r1 + mov fp, sp + mov sp, 0x1337 ; both sp again + leave_s [r13-r26, fp, blink, pcl] ; restore and do everything + j @test15_fail +test15_return: + brne sp , r0, @test15_fail + brne blink, @test15_return, @test15_fail + brne r13 , 213, @test15_fail + brne r14 , 214, @test15_fail + brne r15 , 215, @test15_fail + brne r16 , 216, @test15_fail + brne r17 , 217, @test15_fail + brne r18 , 218, @test15_fail + brne r19 , 219, @test15_fail + brne r20 , 220, @test15_fail + brne r21 , 221, @test15_fail + brne r22 , 222, @test15_fail + brne r23 , 223, @test15_fail + brne r24 , 224, @test15_fail + brne r25 , 225, @test15_fail + brne r26 , 226, @test15_fail + brne fp , 0x14456, @test15_fail + j @test16 + +test15_fail: + print "[FAIL] :test15:" + b @endtest + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; sp's value is not 32-bit aligned --> misaligned exception +; this happens irrelevant of status32.AD bit +test16: + .equ TEST16_FP, 0x777 ; an address which is not 32-bit aligned + lr r1, [status32] + or r1, r1, 0x80000 ; set AD bit + mov r2, @test16_excep_prep + sr r1, [erstatus] ; enable AD bit + sr r2, [eret] ; continue with the test + rtie + +test16_excep_prep: + lr r7, [erbta] ; don't care for erbta + set_excep_params ecr=MISALIGNED_DATA_ACCESS, \ + eret=@test16_enter , \ + efa=TEST16_FP , \ + erbta=r7 , \ + continue=@test16_wrapup , \ + test_num=16 + mov r10, sp ; backup sp to restore later + mov fp, TEST16_FP ; an address which is not 32-bit aligned +test16_enter: + leave_s [r13-r26, fp] ; first fp's value is put into sp + print "[FAIL] :test16:" ; this code must not fall through + b @endtest + +test16_wrapup: + mov sp, r10 + lr r1, [status32] + and r1, r1, ~0x80000 ; clear AD bit + mov r2, @test17 ; go to next test + sr r1, [erstatus] ; disable AD bit + sr r2, [eret] ; continue with next test + rtie + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; a delay slot instruction --> illegal instruction sequence exception +; the tricky thing in this test is that gas does not allow us to put +; an "leave_s" in a delay slot (good job there!). however, we work +; around it by writing the opcode at runtime. +test17: + set_excep_params ecr=ILLEGAL_INSTRUCTION_SEQUENCE, \ + eret=@test17_delay , \ + efa=@test17_delay , \ + erbta=@test17_fail , \ + continue=@test18 , \ + test_num=17 + mov r1, 0xc0c2 ; opcode for leave_s [13] + sth r1, [test17_delay] + b @test17_dummy_tb ; by having 'b' here, it is end of this tb. +test17_dummy_tb: ; so this one will be decoded after mutation. + b.d @test17_fail +test17_delay: + nop_s + nop_s + +test17_fail: + print "[FAIL] :test17:" + b @endtest + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; an execution slot instruction --> illegal instruction sequence exception +; TODO (issue #73): enable this after EI_S has been implemented. +test18: +; mov r1, @test18_ei_table +; sr r1, [ei_base] +; j @test18_begin +; +; .align 4 +;test18_ei_table: +; leave_s [r13] +; +;test18_begin: +; set_excep_params ecr=ILLEGAL_INSTRUCTION_SEQUENCE, \ +; eret=@test18_ei_table , \ +; efa=@test18_ei_table , \ +; erbta=@test18_fail , \ +; continue=@test19 , \ +; test_num=18 +; ei_s 0 +; +;test18_fail: +; print "[FAIL] : test18\n" +; end + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; it is allowed to have "leave_s 0" in delay/execution slot because it is +; like a nop then and is not a multi-cycle instruction. +; TODO (issue #73): enable the ei_check part after EI_S has been done. +test19: + mov r1, 0xc0c0 ; opcode for leave_s [] + sth r1, [test19_delay] + b @test19_dummy_tb ; by having 'b' here, it is end of this tb. +test19_dummy_tb: ; so this one will be decoded after mutation. + b.d @test19_ei_check +test19_delay: + nop_s ; at runtime this is leave_s [] and is ok + nop_s + + .align 4 +test19_ei_table: + leave_s 0 + +test19_ei_check: + ; TODO (issue #73): enable after EI_S is implemented. + ;mov r1, @test19_ei_table + ;sr r1, [ei_base] + ;ei_s 0 + ; fall through to the next test + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; 32 general registers configured AND u[3:0] > 14 (r13-r26) +; OR +; 16 general registers configured AND u[3:0] > 3 (r13-r15) +; --> illegal instruction exception +; TODO (issue #52): this test case must be executed with +; -global cpu.num-regs=16. +test20: +; lr r7, [bta] ; don't care for erbta (use current bta) +; set_excep_params ecr=ILLEGAL_INSTRUCTION, \ +; eret=@test20_big_u3 , \ +; efa=@test20_big_u3 , \ +; erbta=r7 , \ +; continue=@test21 , \ +; test_num=20 +;test20_big_u3: ; leave_s encoding : 1100 0UUU 110u uuu0 +; leave_s 4 +; +;test20_fail: +; print "[FAIL] : test20\n" +; b @endtest +;;;;;;;;;;;;;;;;;;;;;;;;;;;; \ Leave Tests / ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +;;;;;;;;;;;;;;;;;;;;;;;;; / Enter/Leave Test \ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; testing enter_s/leave_s together full fledged. +test21: + mov r0 , sp ; original sp + mov r13, 0x80000013 + mov r14, 0x80000014 + mov r15, 0x80000015 + mov r16, 0x80000016 + mov r17, 0x80000017 + mov r18, 0x80000018 + mov r19, 0x80000019 + mov r20, 0x8000001a + mov r21, 0x8000001b + mov r22, 0x8000001c + mov r23, 0x8000001d + mov r24, 0x8000001e + mov r25, 0x8000001f + mov r26, 0x80000020 + mov r27, 0x88888888 ; fp + mov r31, @test21_verify ; blink + + enter_s [r13-r26, fp, blink] + ; botching all except for fp. it's already changed to current sp. + breq r28, 0x88888888, @test21_fail ; sanity check that fp changed + mov r1 , 0xdeadbeef + mov r13, r1 + mov r14, r1 + mov r15, r1 + mov r16, r1 + mov r17, r1 + mov r18, r1 + mov r19, r1 + mov r20, r1 + mov r21, r1 + mov r22, r1 + mov r23, r1 + mov r24, r1 + mov r25, r1 + mov r26, r1 + mov r28, r1 ; botch sp + mov r31, r1 ; botch blink + leave_s [r13-r26, fp, blink, pcl] + j @test21_fail + +test21_verify: + brne r13, 0x80000013, @test21_fail + brne r14, 0x80000014, @test21_fail + brne r15, 0x80000015, @test21_fail + brne r16, 0x80000016, @test21_fail + brne r17, 0x80000017, @test21_fail + brne r18, 0x80000018, @test21_fail + brne r19, 0x80000019, @test21_fail + brne r20, 0x8000001a, @test21_fail + brne r21, 0x8000001b, @test21_fail + brne r22, 0x8000001c, @test21_fail + brne r23, 0x8000001d, @test21_fail + brne r24, 0x8000001e, @test21_fail + brne r25, 0x8000001f, @test21_fail + brne r26, 0x80000020, @test21_fail + brne r27, 0x88888888, @test21_fail + brne r28, r0, @test21_fail + breq r31, @test21_verify, @valhalla + +test21_fail: + print "[FAIL] :test20:" + b @endtest +;;;;;;;;;;;;;;;;;;;;;;;;; \ Enter/Leave Test / ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +valhalla: + print "[PASS]" +endtest: + print " enter/leave\n" + end + + +; vim: set syntax=asm ts=2 sw=2 et: diff --git a/tests/tcg/arc/check_excp.S b/tests/tcg/arc/check_excp.S new file mode 100644 index 0000000000..18b436dec7 --- /dev/null +++ b/tests/tcg/arc/check_excp.S @@ -0,0 +1,17 @@ + .include "macros.inc" + + start + + test_name TRAP_1 + trap_s 0 + print "[PASS] TRAP_1:1\n" + trap_s 1 + print "[PASS] TRAP_1:2\n" + end + + .align 4 + .global EV_Trap + .type EV_Trap, @function +EV_SWI: +EV_Trap: + rtie diff --git a/tests/tcg/arc/check_excp_1.c b/tests/tcg/arc/check_excp_1.c new file mode 100644 index 0000000000..f06720c119 --- /dev/null +++ b/tests/tcg/arc/check_excp_1.c @@ -0,0 +1,15 @@ +#include + +void main (void) +{ + __builtin_arc_trap_s (0); + printf ("[PASS] TRAPC:1\n"); + __builtin_arc_trap_s (1); + printf ("[PASS] TRAPC:2\n"); +} + +void __attribute__ ((interrupt("ilink"))) +EV_Trap (void) +{ + printf ("[PASS] TRAPC:IRQ\n"); +} diff --git a/tests/tcg/arc/check_excp_jumpdl_mmu.S b/tests/tcg/arc/check_excp_jumpdl_mmu.S new file mode 100644 index 0000000000..a98229eba2 --- /dev/null +++ b/tests/tcg/arc/check_excp_jumpdl_mmu.S @@ -0,0 +1,44 @@ +.include "macros.inc" + +.equ PHYSICAL_ADDRESS_START, 0x80000000 +.equ MMU_ENABLE_FLAG , 0x80000000 + +start + +; use physical address range for handling exceptions (ivt) +mov r0, PHYSICAL_ADDRESS_START +sr r0, [int_vector_base] + +# enable mmu +mov r3, MMU_ENABLE_FLAG +sr r3, [pid] +xor_s r3, r3, r3 + +; write to some virtual address range in a delay slot +mov r2, 0x1000 +mov r1, @check +j_s.d [r1] # let's enjoy the code after delay slot is executed. +st r0, [r2] # oh, oh: exception! + +# this line should not be executed +add_s r3, r3, 1 + +check: +brgt r3, 0, @fail +print "[ OK]" +b @rest +fail: +print "[NOK]" + +rest: +print " Exception in a delay slot.\n" + +end + + .align 4 + .global EV_TLBMissD + .type EV_TLBMissD, @function +EV_TLBMissD: + # disable mmu + sr r3, [pid] + rtie diff --git a/tests/tcg/arc/check_excp_mmu.S b/tests/tcg/arc/check_excp_mmu.S new file mode 100644 index 0000000000..8d1cf83445 --- /dev/null +++ b/tests/tcg/arc/check_excp_mmu.S @@ -0,0 +1,69 @@ +.include "macros.inc" +.include "mmu.inc" + +; courtesy of macros.inc and mmu.inc +.extern REG_IVT_BASE +.extern PAGE_NUMBER_MSK +.extern REG_PD0_GLOBAL +.extern REG_PD0_VALID +.extern REG_PD1_KRNL_W + +; test data +; making an entry for the TLB +; +; ,------------------------------------. +; | VPN(VA), G=1, V=1 | PPN(PHY), Wk=1 | +; `------------------------------------' +; where: +; VPN(VA) is the virtual page number of logical address +; G is the global bit +; V is the validity bit +; PPN(PHY) is the physical page number +; Wk is the write permission in kernel mode + +; obviously, the offsets in both addresses must be the same +.equ VIRT_ADR , 0x13371334 ; the virtual address; word aligned +.equ PHYS_ADR , 0x73311334 ; the physical address > 0x7FFFFFFF +.equ MAGICDATA, 0x00BADB07 ; the test value to write and verify +.equ PD0_VPN , (VIRT_ADR & PAGE_NUMBER_MSK) +.equ PD1_PPN , (PHYS_ADR & PAGE_NUMBER_MSK) +.equ PD0_BITS , (PD0_VPN | REG_PD0_GLOBAL | REG_PD0_VALID) +.equ PD1_BITS , (PD1_PPN | REG_PD1_KRNL_W) +.equ INT_VECT_ADDRESS, 0x80000000 ; physical address for IVT + +start + +; use physicall address range for handling exceptions (ivt) +mov r0, INT_VECT_ADDRESS +sr r0, [REG_IVT_BASE] + +mmu_enable + +; write to the mapped virtual address +mov r0, MAGICDATA +st r0, [VIRT_ADR] + +mmu_disable + +; with mmu disabled, read from physical address and +; verify that it is the same as the value written +; to the mapped virtual address earlier +ld r1, [PHYS_ADR] +cmp r0, r1 ; r0 contains the MAGICDATA +beq @goodboy + +print "nope, still no MMU!\n" +j @adios + +goodboy: +print "Yay, you got the MMU right :)\n" + +adios: +end + + .align 4 + .global EV_TLBMissD + .type EV_TLBMissD, @function +EV_TLBMissD: + mmu_tlb_insert PD0_BITS, PD1_BITS + rtie diff --git a/tests/tcg/arc/check_flags.S b/tests/tcg/arc/check_flags.S new file mode 100644 index 0000000000..92faf18c15 --- /dev/null +++ b/tests/tcg/arc/check_flags.S @@ -0,0 +1,23 @@ +#define ARCTEST_ARC32 + +#***************************************************************************** +# flags.S +#----------------------------------------------------------------------------- +# +# Test or instruction. +# + +#include "test_macros.h" + +ARCTEST_BEGIN + + TEST_2OP_CARRY (2, sub, 0, 0x00000000, 0x0000000) ; + TEST_2OP_CARRY (3, sub, 1, 0x00000000, 0x0000001) ; + TEST_2OP_ZERO (4, sub, 0, 0x00000001, 0x0000000) ; + TEST_2OP_ZERO (5, sub, 1, 0x00000001, 0x0000001) ; + TEST_2OP_NEGATIVE (6, sub, 0, 0x00000000, 0x00000000) ; + TEST_2OP_NEGATIVE (7, sub, 1, 0x00000000, 0x00000001) ; + TEST_2OP_OVERFLOW (8, sub, 0, 0x00000000, 0x00000000) ; + TEST_2OP_OVERFLOW (9, sub, 1, 0x00000000, 0x80000000) ; + +ARCTEST_END diff --git a/tests/tcg/arc/check_ldaw_mmu.S b/tests/tcg/arc/check_ldaw_mmu.S new file mode 100644 index 0000000000..a503c607b9 --- /dev/null +++ b/tests/tcg/arc/check_ldaw_mmu.S @@ -0,0 +1,71 @@ +.include "macros.inc" +.include "mmu.inc" + +; courtesy of mmu.inc +.extern PAGE_NUMBER_MSK +.extern REG_PD0_GLOBAL +.extern REG_PD0_VALID +.extern REG_PD1_KRNL_W + +; test data +; making an entry for the TLB +; +; ,------------------------------------. +; | VPN(VA), G=1, V=1 | PPN(PHY), Wk=1 | +; `------------------------------------' +; where: +; VPN(VA) is the virtual page number of logical address +; G is the global bit +; V is the validity bit +; PPN(PHY) is the physical page number +; Wk is the write permission in kernel mode + +; obviously, the offsets in both addresses must be the same +.equ VIRT_ADR , 0x13371334 ; the virtual address; word aligned +.equ PHYS_ADR , 0x73311334 ; the physical address > 0x7FFFFFFF +.equ MAGICDATA, 0x00BADB07 ; the test value to write and verify +.equ PD0_VPN , (VIRT_ADR & PAGE_NUMBER_MSK) +.equ PD1_PPN , (PHYS_ADR & PAGE_NUMBER_MSK) +.equ PD0_BITS , (PD0_VPN | REG_PD0_GLOBAL | REG_PD0_VALID) +.equ PD1_BITS , (PD1_PPN | REG_PD1_KRNL_R) +.equ INT_VECT_ADDRESS, 0x80000000 ; physical address for IVT + +start + +; use physicall address range for handling exceptions (ivt) +mov r0, INT_VECT_ADDRESS +sr r0, [REG_IVT_BASE] + +; initialize the data in physical address +mov r0, MAGICDATA +st r0, [PHYS_ADR] + +mmu_enable + +; read from the mapped virtual address +mov r2, 0 +ld.aw r1, [r2, VIRT_ADR] + +mmu_disable + +; with mmu disabled, read from physical address and +; verify that it is the same as the value written +; to the mapped virtual address earlier +cmp r0, r1 ; r0 contains the MAGICDATA +beq @goodboy + +print "nope, still no MMU!\n" +j @adios + +goodboy: +print "Yay, you got the MMU right :)\n" + +adios: +end + +.align 4 +.global EV_TLBMissD +.type EV_TLBMissD, @function +EV_TLBMissD: +mmu_tlb_insert PD0_BITS, PD1_BITS +rtie diff --git a/tests/tcg/arc/check_ldstx.S b/tests/tcg/arc/check_ldstx.S new file mode 100644 index 0000000000..ac181d9a51 --- /dev/null +++ b/tests/tcg/arc/check_ldstx.S @@ -0,0 +1,37 @@ +#***************************************************************************** +# ldst.S +#----------------------------------------------------------------------------- +# +# This test verifies that ld, ldb, ldw work as expected. +# + +#define ARCTEST_ARC32 +#include "test_macros.h" + +ARCTEST_BEGIN + + TEST_CASE(2, r0, 0x40000000, "ld:2", ld r1,[@tdat]` ld r0,[r1,@tdat]) + TEST_CASE(3, r0, 0xbeef, "ld:3", mov r1, 16` ldw r0,[r1, @tdat]) + TEST_CASE(4, r0, 0xbe, "ld:4", mov r1, 20` ldb r0,[r1, @tdat]) + TEST_CASE(5, r0, 0xffffbeef, "ld:5", mov r1, 16` ldw.x r0,[r1, @tdat]) + TEST_CASE(6, r0, 0xffffffbe, "ld:6", mov r1, 20` ldb.x r0,[r1, @tdat]) + + TEST_CASE(7, r0, 0xbeef, "ld:7", mov r1, @tdat` ldw.as r0,[r1,8]) + TEST_CASE(8, r0, 0xcafebabe, "ld:8", mov r1, @tdat` ld.as r0,[r1, 5]) + TEST_CASE(9, r0, 0xcafebabe, "ld:9", mov r2, 5` mov r1, @tdat` ld_s.as r0,[r1, r2]) + TEST_CASE(10, r0, 0x40400000, "ld:10", ldd.as r0,[@tdat,2]) + TEST_CASE(11, r1, 0xc0800000, "ld:11", ldd.as r0,[@tdat,2]) + + +ARCTEST_END +# TEST_DATA + +tdat: +.word 0x00000004 +.word 0x40000000 +.word 0x40400000 +.word 0xc0800000 +.word 0xdeadbeef +.word 0xcafebabe +.word 0xabad1dea +.word 0x1337d00d diff --git a/tests/tcg/arc/check_lp.S b/tests/tcg/arc/check_lp.S new file mode 100644 index 0000000000..4074cfa1e5 --- /dev/null +++ b/tests/tcg/arc/check_lp.S @@ -0,0 +1,12 @@ +.include "macros.inc" + + start + mov_s r2,0x28cc + sub r3,0x28d8,r2 + mov lp_count,0x00fffff0 + lpne bla + st.ab r3,[r2,4] + mov 0,0 +bla: + print "[PASS] LP: simple\n" + end diff --git a/tests/tcg/arc/check_lp02.S b/tests/tcg/arc/check_lp02.S new file mode 100644 index 0000000000..866fa01f36 --- /dev/null +++ b/tests/tcg/arc/check_lp02.S @@ -0,0 +1,72 @@ +.include "macros.inc" + + start + mov r3,0 + mov r2, 0x2e10 + mov.f lp_count,0x10 + lpne 2f + st.ab r3,[r2,4] +2: + mov r2,0x1000 + mov_s r3,0xa + and.f lp_count,r3, 0x1f + lpnz 2f + add r2,r2,r2 +2: # end single insn loop + mov r2,0x1000 + mov_s r3,0xa + and.f lp_count,r3, 0x1f + lpnz 2f + add r2,r2,r2 +2: # end single insn loop + mov r2,0x1000 + mov_s r3,0xa + and.f lp_count,r3, 0x1f + lpnz 2f + add r2,r2,r2 +2: # end single insn loop + mov r2,0x1000 + mov_s r3,0xa + and.f lp_count,r3, 0x1f + lpnz 2f + add r2,r2,r2 +2: # end single insn loop + mov r2,0x1000 + mov_s r3,0xa + and.f lp_count,r3, 0x1f + lpnz 2f + add r2,r2,r2 +2: # end single insn loop + mov r2,0x1000 + mov_s r3,0xa + and.f lp_count,r3, 0x1f + lpnz 2f + add r2,r2,r2 +2: # end single insn loop + mov r2,0x1000 + mov_s r3,0xa + and.f lp_count,r3, 0x1f + lpnz 2f + add r2,r2,r2 +2: # end single insn loop + mov r2,0x1000 + mov_s r3,0xa + and.f lp_count,r3, 0x1f + lpnz 2f + add r2,r2,r2 +2: # end single insn loop + mov r2,0x1000 + mov_s r3,0xa + and.f lp_count,r3, 0x1f + lpnz 2f + add r2,r2,r2 +2: # end single insn loop + mov r2,0x1000 + mov_s r3,0xa + and.f lp_count,r3, 0x1f + lpnz 2f + add r2,r2,r2 +2: # end single insn loop + + print "[PASS] LP01\n" + end diff --git a/tests/tcg/arc/check_lp03.S b/tests/tcg/arc/check_lp03.S new file mode 100644 index 0000000000..76e70958f0 --- /dev/null +++ b/tests/tcg/arc/check_lp03.S @@ -0,0 +1,49 @@ + .include "macros.inc" + + start + test_name ZOLvsIRQ + ;; Program the Timer such that we get fast interrupts + sr 0x01,[control0] + sr 0x1ff,[limit0] + sr 0,[count0] + mov r0,0 + mov sp,0x1000 + ;; enable global interrupts + seti + ;; Make a short ZOL + mov lp_count,0x1ffff + lp 1f + nop +1: + clri + stb.ab 0,[sp,1] +2: + rem r2,r0,10 + add r2,r2,0x30 + stb.ab r2,[sp,1] + div.f r0,r0,10 + bne 2b +3: + ld.aw r2,[sp,-1] + breq r2,0,4f + ;; stb r2,[OUTPUT_DEVICE] + brne r2,0,3b +4: + print "[PASS] " + printl r30 + end + + ;; Timer ISR + .align 4 + .global IRQ_Timer0 + .type IRQ_Timer0, @function +IRQ_Timer0: + clri + ;; reset the pending interrupt and reneable it. + sr 0x01,[control0] + sr 0,[count0] + add r0,r0,1 + rtie + print "[FAIL] " + printl r30 + end diff --git a/tests/tcg/arc/check_lp04.S b/tests/tcg/arc/check_lp04.S new file mode 100644 index 0000000000..8a2ca6e432 --- /dev/null +++ b/tests/tcg/arc/check_lp04.S @@ -0,0 +1,48 @@ +.include "macros.inc" + + start + + ; memset params + mov r0, data ; address to write + mov r1, 0 ; data to write + mov r2, 0x13 ; size of memory to clear + + ; align the address + and r4, r0, 3 + rsub.f lp_count, r4, 4 + lpne @main_clear + stb.ab r1, [r0, 1] + sub r2, r2, 1 + +main_clear: + ; main setting to zero + and.f lp_count, r2, 0x1f + lpne @verify + stb.ab r1, [r0, 1] + +verify: + ld r1, [data, 0x12] + cmp r1, 0x66665500 + beq @good + print "[FAIL] " + j @the_end +good: + print "[PASS] " +the_end: + print "LP04\n" + end + +.align 4 +make_unaligned: + .2byte 0xffff +data: + .4byte 0x11111111 + .4byte 0x22222222 + .4byte 0x33333333 + .4byte 0x44444444 + .4byte 0x55555555 + .4byte 0x66666666 + .4byte 0x77777777 + .4byte 0x88888888 + .4byte 0x99999999 + .4byte 0xAAAAAAAA diff --git a/tests/tcg/arc/check_lp05.S b/tests/tcg/arc/check_lp05.S new file mode 100644 index 0000000000..2fc9e40b97 --- /dev/null +++ b/tests/tcg/arc/check_lp05.S @@ -0,0 +1,23 @@ + .include "macros.inc" +;;; Test what is happening when we have a trap_s at the end of a zol + start + mov r0,0 + mov lp_count, 0x1f + lp 1f + trap_s 0 +1: + breq r0,0x1f,1f + print "[FAIL]" + b 2f +1: + print "[PASS]" +2: + print " LP05\n" + end + + .align 4 + .global EV_Trap + .type EV_Trap, @function +EV_Trap: + add r0,r0,1 + rtie diff --git a/tests/tcg/arc/check_lp06.S b/tests/tcg/arc/check_lp06.S new file mode 100644 index 0000000000..60e7a66309 --- /dev/null +++ b/tests/tcg/arc/check_lp06.S @@ -0,0 +1,163 @@ +; check_lp06.S +; +; Tests for Zero overhead loop: interrupting the loop +; If the test fails, check the end of this file for how to troubleshoot. + + .include "macros.inc" + +;;;;;;;;;;;;;;;;;;;;;;;;;;; Test checking routines ;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Test case counter +.data +test_nr: + .word 0x0 + +; Increment the test counter. +.macro prep_test_case + ld r13, [test_nr] + add_s r13, r13, 1 ; increase test case counter + st r13, [test_nr] +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;; Exception related code ;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Handler of the day. + .align 4 +handler : .word 0x0 + +; An exception handler routine that merely jumps to whatever address +; it was told to by the test. See set_except_handler macro. This +; requires ivt.S file to be compiled and linked. + .align 4 + .global EV_Trap + .global EV_SWI + .type EV_Trap, @function + .type EV_SWI, @function +EV_SWI: +EV_Trap: + ld r11, [handler] + j [r11] + +; macro: set_except_handler +; regs used: r11 +; +; This macro writes the provided ADDR to a temporary place holder +; that later the exception handler routine will jump to. +.macro set_except_handler addr + mov r11, \addr + st r11, [handler] +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ZOL ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Let the tests begin + start + +; Test case 1 +; Having a 'trap_s' at the end of a loop body. The exception handler +; must return to the _next instruction_ after the trap which is the +; LOOP_END. Consequently, it should end up in the LOOP_START if the +; LP_COUNT != 1. To cut a long story short: +; next instruction(trap) = loop_start and all iterations should finish +; before getting out of the loop. + prep_test_case + set_except_handler @test_1_except_handler + mov r0, 0 + mov lp_count, 0x1f + lp @test_1_loop_end + trap_s 0 +test_1_loop_end: + cmp r0, 0x1f ; has the loop finished completely? + bne @fail + b @test_1_end ; success +test_1_except_handler: + add r0, r0, 1 + rtie +test_1_end: + ; Fall through + +; Test case 2 +; Having a 'swi' at the end of a loop body. The exception handler +; must return to the _last instruction_ of the loop body and the +; whole loop must finish completely. +; Going back to 'swi' is tricky because it keeps triggering the +; exception. So, after the first trigger, we change it to NOPs. + prep_test_case + set_except_handler @test_2_except_handler + mov r0, 0 ; exception trigger mark + mov r1, 0 ; loop counting + mov lp_count, 0x1f + lp @test_2_loop_end + add r1, r1, 1 +test_2_last_insn_loop: + swi +test_2_loop_end: + cmp r1, 0x1f ; has the loop finished completely? + bne @fail + cmp r0, 1 ; exception triggered? + bne @fail + b @test_2_end ; success +test_2_except_handler: + add r0, r0, 1 + mov r11, @test_2_last_insn_loop + mov r12, 0x78e0 ; NOP_S opcode + sth.ab r12, [r11,2] ; write two NOP_S instead of one NOP + sth r12, [r11] ; to avoid misaligned exception. + rtie +test_2_end: + ; Fall through + +; Test case 3 +; Check if _any_ fetch of instruction at address LOOP_END trigger +; going back to the loop start if the LP_COUNT is not 1. To test +; that: +; Jump out of the loop prematurely. +; Then outside the loop jump back inside the lopp. +; This should trigger going back to the loop, but do not jump out +; prematurely anymore. + prep_test_case + mov r0, 0 ; loop counter + mov r2, 0 ; indicator if we jumped to LOOP_END before + mov lp_count, 17 + lp @test_3_loop_end + cmp r2, 1 + bne @test_3_outside_loop +test_3_last_insn_loop: + add r0, r0, 1 +test_3_loop_end: + add r3, r2, r0 ; r3 = 1 + 17 +test_3_outside_loop: + add r2, r2, 1 + cmp r2, 1 + beq @test_3_last_insn_loop + cmp r0, 17 ; sanity checks begin + bne @fail + cmp r2, 2 ; once we jumped there, once fall through. + bne @fail + cmp r3, 18 + bne @fail + +; Next test cases +; Timer interrupt and a single insn ZOL. We need to check if indeed we get multiple interrupts, while in ZOL. +; Timer interrupt and CLRI/SETI body ZOL. The same as above, 2 tests with seti/clri and clri/seti instruction order. +; Last instruction of a ZOL gets a MMU TLBI miss. +; Last instruction of a ZOL gets a MMU TLBD miss (load/store). +; Last instruction of a ZOL gets a MMU TLBI fallowed by a MMU TLBD miss. + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Reporting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +valhalla: + print "[PASS]" + b @1f + +; If a test fails, it jumps here. Although, for the sake of uniformity, +; the printed output does not say much about which test case failed, +; one can uncomment the print_number line below or set a breakpoint +; here to check the R0 register for the test case number. +fail: + ld r0, [test_nr] + ;print_number r0 + print "[FAIL]" +1: + print " Zero overhead loop: interrupting the loop\n" + end diff --git a/tests/tcg/arc/check_lsrx.S b/tests/tcg/arc/check_lsrx.S new file mode 100644 index 0000000000..9f72e84eb5 --- /dev/null +++ b/tests/tcg/arc/check_lsrx.S @@ -0,0 +1,33 @@ +#define ARCTEST_ARC32 + +#***************************************************************************** +# lsr.S +#----------------------------------------------------------------------------- +# +# Test or instruction. +# + +#include "test_macros.h" + +ARCTEST_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + TEST_RR_3OP ( 2, lsr, 0x00000000, 0x00000000, 0); + TEST_RR_3OP ( 3, lsr, 0x12345678, 0x12345678, 0); + TEST_RR_3OP ( 4, lsr, 0x01234567, 0x12345678, 4); + TEST_RR_3OP ( 5, lsr, 0x0ABCDEF4, 0xABCDEF45, 4); + TEST_RR_3OP ( 6, lsr, 0x00000000, 0x7FFFFFFF, 31); + TEST_RR_3OP ( 7, lsr, 0x00000001, 0xFFFFFFFF, 31); + + #------------------------------------------------------------- + # Flag tests + #------------------------------------------------------------- + TEST_2OP_CARRY( 9, lsr, 0, 0x00000001, 0x02); + TEST_2OP_CARRY(10, lsr, 1, 0x00000001, 0x01); + TEST_2OP_ZERO( 11, lsr, 1, 0x00000001, 0x01); + TEST_2OP_NEGATIVE( 12, lsr, 1, 0x80000000, 0x00); + + +ARCTEST_END diff --git a/tests/tcg/arc/check_mac.S b/tests/tcg/arc/check_mac.S new file mode 100644 index 0000000000..7e172457ab --- /dev/null +++ b/tests/tcg/arc/check_mac.S @@ -0,0 +1,228 @@ +.include "macros.inc" + +.equ NOTSET, 47806 + +; conditionally sets the ACC data +.macro setup_acc acch, accl + .if \accl <> NOTSET + mov r58, \accl + .endif + .if \acch <> NOTSET + mov r59, \acch + .endif +.endm + +; conditionally checks if ACC holds the given value +.macro verify_acc racch, raccl, test_num + .if \raccl <> NOTSET + assert_eq r58, \raccl, \test_num + .endif + .if \racch <> NOTSET + assert_eq r59, \racch, \test_num + .endif +.endm + +; all Z, N, C, V flags are cleared and ACC will become 0 +.macro clear_flags_and_accu + ; clearing the Z N C V flags + mov r0, 1 + add.f r0, r0, r0 + ; clearing the acc + mov r58, 0 + mov r59, 0 +.endm + +; checks if Z, N, C, and V flags are set correctly +.macro verify_flags z=0, n=0, c=0, v=0, test_num + assert_flag REG_STAT_Z, \z, \test_num + assert_flag REG_STAT_N, \n, \test_num + assert_flag REG_STAT_C, \c, \test_num + assert_flag REG_STAT_V, \v, \test_num +.endm + +; macro for testing "MAC" instruction +.macro mac_test acch=NOTSET, accl=NOTSET, val1, val2, res, racch=NOTSET, raccl=NOTSET, n=0, v=0, test_num + ; initializing data + setup_acc \acch, \accl + mov r0, \val1 + mov r1, \val2 + ; operation under test + mac.f r0, r0, r1 + ; checking the results + verify_flags n=\n, v=\v, test_num=\test_num + assert_eq \res, r0, \test_num + verify_acc \racch, \raccl, \test_num +.endm + +; macro for testing "MACU" instruction +.macro macu_test acch=NOTSET, accl=NOTSET, val1, val2, res, racch=NOTSET, raccl=NOTSET, v=0, test_num + ; initializing data + setup_acc \acch, \accl + mov r0, \val1 + mov r1, \val2 + ; operation under test + macu.f r0, r0, r1 + ; checking the results + verify_flags v=\v, test_num=\test_num + assert_eq \res, r0, \test_num + verify_acc \racch, \raccl, \test_num +.endm + + +; macro for testing "MACD" instruction +.macro macd_test acch=NOTSET, accl=NOTSET, val1, val2, resh, resl, racch=NOTSET, raccl=NOTSET, n=0, v=0, test_num + ; initializing data + setup_acc \acch, \accl + mov r0, \val1 + mov r1, \val2 + ; operation under test + macd.f r0, r0, r1 + ; checking the results + verify_flags n=\n, v=\v, test_num=\test_num + assert_eq \resl, r0, \test_num + assert_eq \resh, r1, \test_num + verify_acc \racch, \raccl, \test_num +.endm + +; macro for testing "MACU" instruction +.macro macdu_test acch=NOTSET, accl=NOTSET, val1, val2, resh, resl, racch=NOTSET, raccl=NOTSET, v=0, test_num + ; initializing data + setup_acc \acch, \accl + mov r0, \val1 + mov r1, \val2 + ; operation under test + macdu.f r0, r0, r1 + ; checking the results + verify_flags v=\v, test_num=\test_num + assert_eq \resl, r0, \test_num + assert_eq \resh, r1, \test_num + verify_acc \racch, \raccl, \test_num +.endm + + +start + +;;;;;;;;;;;;;;;;;;;;;; MAC ;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; acc = 0 + 4*5 = 20 +mac_test val1=4, val2=5, res=20, test_num=1 +; acc = 20 + 5*1 = 25 +mac_test val1=1, val2=5, res=25, test_num=2 +; acc = 25 + -1*5 = 20 +mac_test val1=0xFFFFFFFF, val2=0x5, res=20, racch=0x0, raccl=20, n=0, test_num=3 +; acc = 20 + -3*9 = -7 +mac_test val1=0xFFFFFFFD, val2=0x09, res=0xFFFFFFF9, racch=0xFFFFFFFF, raccl=0xFFFFFFF9, n=1, test_num=4 +; producing a result that sets both acch and accl +mac_test acch=0, accl=0, val1=0x7FFFFFFF, val2=0x7FFFFFFF, res=1, racch=0x3FFFFFFF, raccl=0x01, n=0, v=0, test_num=5 +; acc is 0x3FFFFFFF00000001 +mac_test val1=0x80000000, val2=0x80000000, res=1, racch=0x7FFFFFFF, raccl=0x01, n=0, v=0, test_num=6 +; acc is 0x7FFFFFFF00000001; going for the kill: N and V will be set +mac_test val1=0x12344321, val2=0x56788654, res=0xE1C14CD5, racch=0x86262098, raccl=0xE1C14CD5, n=1, v=1, test_num=7 +; "mac" is not supposed to clear the overflow bit +mac_test acch=0, accl=0, val1=0, val2=0, res=0, racch=0, raccl=0, n=0, v=1, test_num=8 +clear_flags_and_accu + + +;;;;;;;;;;;;;;;;;;;;;; MACU ;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; acc = 0 + 4*5 = 20 +macu_test val1=4, val2=5, res=20, test_num=9 +; acc = 20 + 5*1 = 25 +macu_test val1=1, val2=5, res=25, test_num=10 +; acc = 25 + 21,474,836,475 = 21,474,836,500 (0x00000005,0x00000014) +macu_test val1=0xFFFFFFFF, val2=0x5, res=20, racch=5, raccl=20, test_num=11 +; acc = 21,474,836,500 + 38,654,705,637 = 60,129,542,137 (0x0000000D,0xFFFFFFF9) +macu_test val1=0xFFFFFFFD, val2=0x09, res=0xFFFFFFF9, racch=0x0D, raccl=0xFFFFFFF9, test_num=12 +; producing a result that sets both acch and accl +macu_test acch=0, accl=0, val1=0x7FFFFFFF, val2=0x7FFFFFFF, res=1, racch=0x3FFFFFFF, raccl=0x01, v=0, test_num=13 +; acc is 0x3FFFFFFF00000001 +macu_test val1=0x80000000, val2=0x80000000, res=1, racch=0x7FFFFFFF, raccl=0x01, v=0, test_num=14 +; acc is 0x7FFFFFFF00000001; line below still will not trigger an overflow for MACU +macu_test val1=0x12344321, val2=0x56788654, res=0xE1C14CD5, racch=0x86262098, raccl=0xE1C14CD5, v=0, test_num=15 +; cause an overflow +macu_test acch=0xFFFFFFFF, accl=0xFFFFFFFF, val1=1, val2=1, res=0, racch=0, raccl=0, v=1, test_num=16 +; "macu" is not supposed to clear the overflow bit +macu_test acch=0, accl=0, val1=0, val2=0, res=0, racch=0, raccl=0, v=1, test_num=17 +clear_flags_and_accu + + +;;;;;;;;;;;;;;;;;;;;; MACD ;;;;;;;;;;;;;;;;;;;;;;;;;;;; +macd_test val1=4, val2=5, resh=0, resl=20, test_num=18 +; acc is now 20 +macd_test val1=1, val2=5, resh=0, resl=25, test_num=19 +; acc = 25 + -1*5 = 20 +macd_test val1=0xFFFFFFFF, val2=0x5, resh=0, resl=20, racch=0x0, raccl=20, n=0, test_num=20 +; acc = 20 + -3*9 = -7 +macd_test val1=0xFFFFFFFD, val2=0x09, resh = 0xFFFFFFFF, resl=0xFFFFFFF9, racch=0xFFFFFFFF, raccl=0xFFFFFFF9, n=1, test_num=21 +; producing a result that sets both acch and accl +macd_test acch=0, accl=0, val1=0x7FFFFFFF, val2=0x7FFFFFFF, resh=0x3FFFFFFF, resl=0x01, racch=0x3FFFFFFF, raccl=0x01, v=0, test_num=22 +; acc is 0x3FFFFFFF00000001 +macd_test val1=0x80000000, val2=0x80000000, resh=0x7FFFFFFF, resl=0x01, racch=0x7FFFFFFF, raccl=0x01, v=0, test_num=23 +; acc is 0x7FFFFFFF00000001; going for the kill: N and V will be set +macd_test val1=0x12344321, val2=0x56788654, resh=0x86262098, resl=0xE1C14CD5, racch=0x86262098, raccl=0xE1C14CD5, n=1, v=1, test_num=24 +; "macd" is not supposed to clear the overflow bit +macd_test acch=0, accl=0, val1=0, val2=0, resh=0, resl=0, racch=0, raccl=0, n=0, v=1, test_num=25 +clear_flags_and_accu + + +;;;;;;;;;;;;;;;;;;;; MACDU ;;;;;;;;;;;;;;;;;;;;;;;;;;;; +macdu_test val1=4, val2=5, resh=0, resl=20, test_num=26 +; acc is now 20 +macdu_test val1=1, val2=5, resh=0, resl=25, test_num=27 +; acc = 25 + 21,474,836,475 = 21,474,836,500 (0x00000005,0x00000014) +macdu_test val1=0xFFFFFFFF, val2=0x5, resh=5, resl=20, racch=5, raccl=20, test_num=28 +; acc = 21,474,836,500 + 38,654,705,637 = 60,129,542,137 (0x0000000D,0xFFFFFFF9) +macdu_test val1=0xFFFFFFFD, val2=0x09, resh=0x0D, resl=0xFFFFFFF9, racch=0x0D, raccl=0xFFFFFFF9, test_num=29 +; producing a result that sets both acch and accl +macdu_test acch=0, accl=0, val1=0x7FFFFFFF, val2=0x7FFFFFFF, resh=0x3FFFFFFF, resl=0x01, racch=0x3FFFFFFF, raccl=0x01, v=0, test_num=30 +; acc is 0x3FFFFFFF00000001 +macdu_test val1=0x80000000, val2=0x80000000, resh=0x7FFFFFFF, resl=0x01, racch=0x7FFFFFFF, raccl=0x01, v=0, test_num=31 +; acc is 0x7FFFFFFF00000001; line below still will not trigger an overflow for MACU +macdu_test val1=0x12344321, val2=0x56788654, resh=0x86262098, resl=0xE1C14CD5, racch=0x86262098, raccl=0xE1C14CD5, v=0, test_num=32 +; cause an overflow +macdu_test acch=0xFFFFFFFF, accl=0xFFFFFFFF, val1=1, val2=1, resh=0, resl=0, racch=0, raccl=0, v=1, test_num=33 +; "macdu" is not supposed to clear the overflow bit +macdu_test acch=0, accl=0, val1=0, val2=0, resh=0, resl=0, racch=0, raccl=0, v=1, test_num=34 +clear_flags_and_accu + + +;;;;;;;;;;;;;;;;;;; CC anf FF ;;;;;;;;;;;;;;;;;;;;;;;;; +mov r0, 0xFFFFFFFF +mov r1, 0x11111111 +mac.f r2, r0, r1 +assert_flag REG_STAT_N, 1, test_num=35 +clear_flags_and_accu + +mov r0, 0xFFFFFFFF +mov r1, 0x11111111 +mac r2, r0, r1 +assert_flag REG_STAT_N, 0, test_num=36 +clear_flags_and_accu + +setup_acc acch=0xFFFFFFFF, accl=0xFFFFFFFF +mov r0, 0x01 +mov r1, 0x01 +; earlier, this caused an overflow; see test case 25 +macdu r2, r0, r1 +assert_flag REG_STAT_V, 0, test_num=37 +clear_flags_and_accu + +; FIXME: uncomment code below when assmbler starts supporting conditon codes +; cause an overflow and then execute based on CC +;mov r0, 42 +;mov r1, 1 +;mov r2, 0x1337 +;;macu.v r2, r1, r0 ; assembler does not support this line +;assert_eq 0x1337, r2, test_num=38 +; +;mov r0, 42 +;mov r1, 1 +;; causing the N bit to be set +;mov r4, 0xFFFFFFFF +;add.f r4, r4, r4 +;; conditional execution and update flags +;macd.N.f r2, r1, r0 ; assembler does not support this line +;assert_flag REG_STAT_N, 0, test_num=39 +;assert_eq 42, r2, test_num=39 + + +;;;;;;;;;;;;;;;;;;; Finished ;;;;;;;;;;;;;;;;;;;;;;;;;; +end diff --git a/tests/tcg/arc/check_manip_10_mmu.S b/tests/tcg/arc/check_manip_10_mmu.S new file mode 100644 index 0000000000..be426d89e9 --- /dev/null +++ b/tests/tcg/arc/check_manip_10_mmu.S @@ -0,0 +1,173 @@ +; check_manip_5_mmu.S +; +; Tests for MMU: manipulate MMU table in exception routines. +; If the test fails, check the end of this file for how to troubleshoot. +; The running code for this test needs to be in address range >= 0x8000_0000. + + .include "macros.inc" + .include "mmu.inc" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;; Bunch of constants ;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + .equ INT_VECT_ADDRESS, 0x80000000 ; physical address for IVT + .equ STATUS32_AD_BIT , 19 ; Alignment Disable bit + ; courtesy of macros.inc and mmu.inc + .extern REG_IVT_BASE + .extern PAGE_NUMBER_MSK + .extern REG_PD0_GLOBAL + .extern REG_PD0_VALID + .extern REG_PD1_KRNL_W + +;;;;;;;;;;;;;;;;;;;;;;;;; Exception related code ;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Handler of the day. + .align 4 +handler : .word 0x0 + +; An exception handler routine that merely jumps to whatever address +; it was told to by the test. See set_except_handler macro. This +; requires ivt.S file to be compiled and linked. + .align 4 + .global EV_TLBMissI + .global EV_TLBMissD + .global EV_ProtV + .type EV_TLBMissI, @function + .type EV_TLBMissD, @function + .type EV_ProtV, @function +EV_TLBMissI: +EV_TLBMissD: +EV_ProtV: + ld r11, [handler] + j [r11] + +; macro: set_except_handler +; regs used: r11 +; +; This macro writes the provided ADDR to a temporary place holder +; that later the exception handler routine will jump to. +.macro set_except_handler addr + mov r11, \addr + st r11, [handler] +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Tests ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Let the tests begin + start + ; use physicall address range for handling exceptions (ivt) + mov r0, INT_VECT_ADDRESS + sr r0, [REG_IVT_BASE] + +; Test case 5 +; Like previous test but with a "branch and link". This is even trickier. +; BL needs to decode the delay instruction to know its length. It uses +; this information to determine what value should "BLINK" register hold. +; Below is the pertinent semantic: +; +; delay_insn_addr = bl_insn_addr + bl_insn_len +; delay_insn_len = decode(delay_insn_addr) +; BLINK = bl_insn_addr + bl_insn_len + delay_insn_len +; +; If the "delay slot" instruction is on a missing page, a TLBMissI is +; raised during "decode(delay_insn_addr)". This all happens while the +; "BL" instruction is being handled (and not the delay slot): +; +; ecr = 0x40000 (TLBMissI) +; eret = bl_insn_addr --> for previous test, this is delay_insn_addr +; efa = delay_insn_addr +; blink = old value (not updated) + .equ T5_VIRT_ADDR, 0x00602000 ; virtual page address + .equ T5_PHYS_ADDR, 0xA0008000 ; physical page address + .equ T5_ADDR_OFS, 0x00001FF8 ; the offset in the page + .equ T5_PD0, ((T5_VIRT_ADDR+T5_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD0_GLOBAL | REG_PD0_VALID) + .equ T5_PD1, ((T5_PHYS_ADDR+T5_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD1_KRNL_R | REG_PD1_KRNL_E) + .equ T5_size, test_10_embedded_code_end - test_10_embedded_code_start + + mmu_prep_test_case + mmu_prep_test_case + ; Copy the embedded code into physical page + xor_s r3, r3, r3 + mov r0, @test_10_embedded_code_start + mov r1, @T5_PHYS_ADDR+T5_ADDR_OFS +test_10_copy: + ldb.ab r2, [r0, 1] + stb.ab r2, [r1, 1] + add_s r3, r3, 1 + cmp r3, T5_size + blt @test_10_copy + ; Add MMU + set_except_handler @test_10_except_handler + mmu_tlb_insert T5_PD0, T5_PD1 + mmu_enable + lr r8, [bta] ; remember the old bta value + mov r0, 0x80000000 ; will be used by the code to be executed + mov r1, T5_VIRT_ADDR+T5_ADDR_OFS ; jump to the copied code + ; Have embedded code word-aligned at a place where it will be put. + + mov r5, 0 + mov r4, 1 + sub.f 0, r5, r4 + j [r1] + +test_10_control: + sub r7, r4, r5 ; 1 + sub.f 0, r7, r6 ; + + bne @fail + add r5, r5, 1 + + sub.f 0, r5, 2 + beq @test_10_end + + sub.f 0, r5, r4 + j [r1] + + .align 4 +test_10_embedded_code_start: + mov r6, 1 + bne.d @to_jump + ld r7, [r0] + mov r6, 0 +to_jump: + j @test_10_control + nop +test_10_virt_finish: + mov r6, 1 + j @test_10_control +test_10_embedded_code_end: +; Exception routine that will add entry for the second page +test_10_except_handler: + mmu_prep_test_case_address + lr r9, [ecr] + cmp r9, 0x40000 ; TLBMissI? + bne @fail + mmu_prep_test_case_address + lr r9, [eret] + cmp r9, @T5_VIRT_ADDR+0x2000 ; Beginning of second page? + jne @fail + mmu_prep_test_case_address + lr r9, [efa] + cmp r9, @T5_VIRT_ADDR+0x2000 ; Beginning of second page? + jne @fail + mmu_tlb_insert T5_PD0+0x2000, T5_PD1+0x2000 + rtie +test_10_end: + ; Fall through + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Reporting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +valhalla: + print "[PASS]" + b @1f + +; If a test fails, it jumps here. Although, for the sake of uniformity, +; the printed output does not say much about which test case failed, +; one can uncomment the print_number line below or set a breakpoint +; here to check the R0 register for the test case number. +fail: + ld r0, [mmu_test_nr] + ;print_number r0 + print "[FAIL]" +1: + print " MMU: manipulate MMU table in exception routines\n" + end diff --git a/tests/tcg/arc/check_manip_4_mmu.S b/tests/tcg/arc/check_manip_4_mmu.S new file mode 100644 index 0000000000..599cd2a95a --- /dev/null +++ b/tests/tcg/arc/check_manip_4_mmu.S @@ -0,0 +1,158 @@ +; check_manip_4_mmu.S +; +; Tests for MMU: manipulate MMU table in exception routines. +; If the test fails, check the end of this file for how to troubleshoot. +; The running code for this test needs to be in address range >= 0x8000_0000. + + .include "macros.inc" + .include "mmu.inc" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;; Bunch of constants ;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + .equ INT_VECT_ADDRESS, 0x80000000 ; physical address for IVT + .equ STATUS32_AD_BIT , 19 ; Alignment Disable bit + ; courtesy of macros.inc and mmu.inc + .extern REG_IVT_BASE + .extern PAGE_NUMBER_MSK + .extern REG_PD0_GLOBAL + .extern REG_PD0_VALID + .extern REG_PD1_KRNL_W + +;;;;;;;;;;;;;;;;;;;;;;;;; Exception related code ;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Handler of the day. + .align 4 +handler : .word 0x0 + +; An exception handler routine that merely jumps to whatever address +; it was told to by the test. See set_except_handler macro. This +; requires ivt.S file to be compiled and linked. + .align 4 + .global EV_TLBMissI + .global EV_TLBMissD + .global EV_ProtV + .type EV_TLBMissI, @function + .type EV_TLBMissD, @function + .type EV_ProtV, @function +EV_TLBMissI: +EV_TLBMissD: +EV_ProtV: + ld r11, [handler] + j [r11] + +; macro: set_except_handler +; regs used: r11 +; +; This macro writes the provided ADDR to a temporary place holder +; that later the exception handler routine will jump to. +.macro set_except_handler addr + mov r11, \addr + st r11, [handler] +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Tests ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Let the tests begin + start + ; use physicall address range for handling exceptions (ivt) + mov r0, INT_VECT_ADDRESS + sr r0, [REG_IVT_BASE] +; Test case 4 +; Straddle a "branch" and its "delay slot" on two consecutive pages. +; The first virtual page has an entry in TLB, but the second one (which +; the delay slot is on) does not. We want to see when fetching the delay +; slot causes a TLBMissI, things will go back smoothly. +; +; first page with TLB entry +; ,-----. +; | ... | +; | nop | +; | b.d | branch instruction as the last instruction of the page +; `-----' +; ,-----. +; | dly | delay instruction on the next page +; | ... | +; | | +; `-----' +; second page without TLB entry + .equ T4_VIRT_ADDR, 0x00402000 ; virtual page address + .equ T4_PHYS_ADDR, 0x90008000 ; physical page address + .equ T4_ADDR_OFS, 0x00001FF8 ; the offset in the page + .equ T4_PD0, ((T4_VIRT_ADDR+T4_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD0_GLOBAL | REG_PD0_VALID) + .equ T4_PD1, ((T4_PHYS_ADDR+T4_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD1_KRNL_R | REG_PD1_KRNL_E) + .equ T4_size, test_4_embedded_code_end - test_4_embedded_code_start + + mmu_prep_test_case + ; Copy the embedded code into physical page + xor_s r3, r3, r3 + mov r0, @test_4_embedded_code_start + mov r1, @T4_PHYS_ADDR+T4_ADDR_OFS +test_4_copy: + ldb.ab r2, [r0, 1] + stb.ab r2, [r1, 1] + add_s r3, r3, 1 + cmp r3, T4_size + blt @test_4_copy + ; Add MMU + set_except_handler @test_4_except_handler + mmu_tlb_insert T4_PD0, T4_PD1 + mmu_enable + mov r0, 0x80000000 ; will be used by the code to be executed + mov r1, T4_VIRT_ADDR+T4_ADDR_OFS ; jump to the copied code + j [r1] + ; Have embedded code word-aligned at a place where it will be put. + .align 4 +test_4_embedded_code_start: + nop + b.d @test_4_virt_finish + ld r1, [r0] + nop + j @fail + nop +test_4_virt_finish: + j @test_4_end +test_4_embedded_code_end: +; Exception routine that will add entry for the second page +test_4_except_handler: + mmu_prep_test_case_address + lr r9, [ecr] + cmp r9, 0x40000 ; TLBMissI? + bne @fail + mmu_prep_test_case_address + lr r9, [eret] + cmp r9, @T4_VIRT_ADDR+0x2000 ; Beginning of second page? + jne @fail + mmu_prep_test_case_address + lr r9, [efa] + cmp r9, @T4_VIRT_ADDR+0x2000 ; Beginning of second page? + jne @fail + mmu_prep_test_case_address + lr r9, [bta] + cmp r9, @T4_VIRT_ADDR+T4_ADDR_OFS+T4_size-8 ; BTA correct? + jne @fail + mmu_prep_test_case_address + lr r9, [erbta] + cmp r9, @T4_VIRT_ADDR+T4_ADDR_OFS+T4_size-8 ; ERBTA correct? + jne @fail + mmu_tlb_insert T4_PD0+0x2000, T4_PD1+0x2000 + rtie +test_4_end: + ; Fall through + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Reporting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +valhalla: + print "[PASS]" + b @1f + +; If a test fails, it jumps here. Although, for the sake of uniformity, +; the printed output does not say much about which test case failed, +; one can uncomment the print_number line below or set a breakpoint +; here to check the R0 register for the test case number. +fail: + ld r0, [mmu_test_nr] + ;print_number r0 + print "[FAIL]" +1: + print " MMU: manipulate MMU table in exception routines\n" + end diff --git a/tests/tcg/arc/check_manip_5_mmu.S b/tests/tcg/arc/check_manip_5_mmu.S new file mode 100644 index 0000000000..17ea00bfe8 --- /dev/null +++ b/tests/tcg/arc/check_manip_5_mmu.S @@ -0,0 +1,166 @@ +; check_manip_5_mmu.S +; +; Tests for MMU: manipulate MMU table in exception routines. +; If the test fails, check the end of this file for how to troubleshoot. +; The running code for this test needs to be in address range >= 0x8000_0000. + + .include "macros.inc" + .include "mmu.inc" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;; Bunch of constants ;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + .equ INT_VECT_ADDRESS, 0x80000000 ; physical address for IVT + .equ STATUS32_AD_BIT , 19 ; Alignment Disable bit + ; courtesy of macros.inc and mmu.inc + .extern REG_IVT_BASE + .extern PAGE_NUMBER_MSK + .extern REG_PD0_GLOBAL + .extern REG_PD0_VALID + .extern REG_PD1_KRNL_W + +;;;;;;;;;;;;;;;;;;;;;;;;; Exception related code ;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Handler of the day. + .align 4 +handler : .word 0x0 + +; An exception handler routine that merely jumps to whatever address +; it was told to by the test. See set_except_handler macro. This +; requires ivt.S file to be compiled and linked. + .align 4 + .global EV_TLBMissI + .global EV_TLBMissD + .global EV_ProtV + .type EV_TLBMissI, @function + .type EV_TLBMissD, @function + .type EV_ProtV, @function +EV_TLBMissI: +EV_TLBMissD: +EV_ProtV: + ld r11, [handler] + j [r11] + +; macro: set_except_handler +; regs used: r11 +; +; This macro writes the provided ADDR to a temporary place holder +; that later the exception handler routine will jump to. +.macro set_except_handler addr + mov r11, \addr + st r11, [handler] +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Tests ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Let the tests begin + start + ; use physicall address range for handling exceptions (ivt) + mov r0, INT_VECT_ADDRESS + sr r0, [REG_IVT_BASE] + +; Test case 5 +; Like previous test but with a "branch and link". This is even trickier. +; BL needs to decode the delay instruction to know its length. It uses +; this information to determine what value should "BLINK" register hold. +; Below is the pertinent semantic: +; +; delay_insn_addr = bl_insn_addr + bl_insn_len +; delay_insn_len = decode(delay_insn_addr) +; BLINK = bl_insn_addr + bl_insn_len + delay_insn_len +; +; If the "delay slot" instruction is on a missing page, a TLBMissI is +; raised during "decode(delay_insn_addr)". This all happens while the +; "BL" instruction is being handled (and not the delay slot): +; +; ecr = 0x40000 (TLBMissI) +; eret = bl_insn_addr --> for previous test, this is delay_insn_addr +; efa = delay_insn_addr +; blink = old value (not updated) + .equ T5_VIRT_ADDR, 0x00602000 ; virtual page address + .equ T5_PHYS_ADDR, 0xA0008000 ; physical page address + .equ T5_ADDR_OFS, 0x00001FF8 ; the offset in the page + .equ T5_PD0, ((T5_VIRT_ADDR+T5_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD0_GLOBAL | REG_PD0_VALID) + .equ T5_PD1, ((T5_PHYS_ADDR+T5_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD1_KRNL_R | REG_PD1_KRNL_E) + .equ T5_size, test_5_embedded_code_end - test_5_embedded_code_start + + mmu_prep_test_case + mmu_prep_test_case + ; Copy the embedded code into physical page + xor_s r3, r3, r3 + mov r0, @test_5_embedded_code_start + mov r1, @T5_PHYS_ADDR+T5_ADDR_OFS +test_5_copy: + ldb.ab r2, [r0, 1] + stb.ab r2, [r1, 1] + add_s r3, r3, 1 + cmp r3, T5_size + blt @test_5_copy + ; Add MMU + set_except_handler @test_5_except_handler + mmu_tlb_insert T5_PD0, T5_PD1 + mmu_enable + lr r4, [bta] ; remember the old bta value + mov r0, 0x80000000 ; will be used by the code to be executed + mov r1, T5_VIRT_ADDR+T5_ADDR_OFS ; jump to the copied code + j [r1] + ; Have embedded code word-aligned at a place where it will be put. + .align 4 +test_5_embedded_code_start: + nop + bl.d @test_5_virt_finish + ld r1, [r0] + nop + j @fail + nop +test_5_virt_finish: + j @test_5_end +test_5_embedded_code_end: +; Exception routine that will add entry for the second page +test_5_except_handler: + mmu_prep_test_case_address + lr r9, [ecr] + print_number_hex r9 + cmp r9, 0x40000 ; TLBMissI? + bne @fail + mmu_prep_test_case_address + lr r9, [eret] + print_number_hex r9 + cmp r9, @T5_VIRT_ADDR+0x2000-4 ; Beginning of second page? + jne @fail + mmu_prep_test_case_address + lr r9, [efa] + print_number_hex r9 + cmp r9, @T5_VIRT_ADDR+0x2000 ; Beginning of second page? + jne @fail + mmu_prep_test_case_address + lr r9, [bta] + print_number_hex r9 + cmp r9, r4 ; BTA not updated? (still old?) + jne @fail + mmu_prep_test_case_address + lr r9, [erbta] + cmp r9, r4 ; ERBTA same as not updated BTA? + jne @fail + mmu_tlb_insert T5_PD0+0x2000, T5_PD1+0x2000 + rtie +test_5_end: + ; Fall through + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Reporting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +valhalla: + print "[PASS]" + b @1f + +; If a test fails, it jumps here. Although, for the sake of uniformity, +; the printed output does not say much about which test case failed, +; one can uncomment the print_number line below or set a breakpoint +; here to check the R0 register for the test case number. +fail: + ld r0, [mmu_test_nr] + ;print_number r0 + print "[FAIL]" +1: + print " MMU: manipulate MMU table in exception routines\n" + end diff --git a/tests/tcg/arc/check_manip_mmu.S b/tests/tcg/arc/check_manip_mmu.S new file mode 100644 index 0000000000..c2bab099f9 --- /dev/null +++ b/tests/tcg/arc/check_manip_mmu.S @@ -0,0 +1,565 @@ +; check_manip_mmu.S +; +; Tests for MMU: manipulate MMU table in exception routines. +; If the test fails, check the end of this file for how to troubleshoot. +; The running code for this test needs to be in address range >= 0x8000_0000. + + .include "macros.inc" + .include "mmu.inc" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;; Bunch of constants ;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + .equ INT_VECT_ADDRESS, 0x80000000 ; physical address for IVT + .equ STATUS32_AD_BIT , 19 ; Alignment Disable bit + ; courtesy of macros.inc and mmu.inc + .extern REG_IVT_BASE + .extern PAGE_NUMBER_MSK + .extern REG_PD0_GLOBAL + .extern REG_PD0_VALID + .extern REG_PD1_KRNL_W + +;;;;;;;;;;;;;;;;;;;;;;;;; Exception related code ;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Handler of the day. + .align 4 +handler : .word 0x0 + +; An exception handler routine that merely jumps to whatever address +; it was told to by the test. See set_except_handler macro. This +; requires ivt.S file to be compiled and linked. + .align 4 + .global EV_TLBMissI + .global EV_TLBMissD + .global EV_ProtV + .global instruction_error + .type EV_TLBMissI, @function + .type EV_TLBMissD, @function + .type EV_ProtV, @function + .type instruction_error, @function +EV_TLBMissI: +EV_TLBMissD: +EV_ProtV: +instruction_error: + ld r11, [handler] + j [r11] + +; macro: set_except_handler +; regs used: r11 +; +; This macro writes the provided ADDR to a temporary place +; that later the exception handler routine will jump to. +.macro set_except_handler addr + mov r11, \addr + st r11, [handler] +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Tests ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Let the tests begin + start + ; use physicall address range for handling exceptions (ivt) + mov r0, INT_VECT_ADDRESS + sr r0, [REG_IVT_BASE] + +; Test case 1: +; Reading from a virtual address that has no entry in TLB. This will +; cause a TLBMissD exception. In return, the exception routine handler +; will add the corresponding entry: +; ,-----------------.------------------.----------------------. +; | virtual address | physical address | (kernel) permissions | +; |-----------------+------------------+----------------------| +; | 0x1337_1334 | 0x7331_1334 | R-- | +; `-----------------^------------------^----------------------' +; After returning from the exception, the "ld" should go OK. +; Then there comes a write ("st") that will trigger a ProtV exception. +; This time, we allow writing as well: +; ,-----------------.------------------.----------------------. +; | virtual address | physical address | (kernel) permissions | +; |-----------------+------------------+----------------------| +; | 0x1337_1334 | 0x7331_1334 | RW- | +; `-----------------^------------------^----------------------' +; the "st" to the same address should go fine. + .equ T1_VIRT_ADDR, 0x13371334 ; the virtual address; word aligned + .equ T1_PHYS_ADDR, 0x73311334 ; the physical address (same page offset as VA) + .equ T1_DATA_1 , 0x00BADB07 ; the test value to read and verify + .equ T1_DATA_2 , 0x00B07BAD ; the test value to write and verify + .equ T1_PD0 , ((T1_VIRT_ADDR & PAGE_NUMBER_MSK) | REG_PD0_GLOBAL | REG_PD0_VALID) + .equ T1_PD1_R , ((T1_PHYS_ADDR & PAGE_NUMBER_MSK) | REG_PD1_KRNL_R) + .equ T1_PD1_RW, (T1_PD1_R | REG_PD1_KRNL_W) + mmu_prep_test_case + mov r2, 0 ; exception handler counter + mov r1, T1_DATA_1 ; plant the data ... + st r1, [T1_PHYS_ADDR] ; ... into the physical address + set_except_handler @test_1_except_handler + mmu_enable +test_1_ld: + ld r0, [T1_VIRT_ADDR] ; TLBMissD causing instruction + cmp r0, T1_DATA_1 + bne @fail + mov r0, T1_DATA_2 +test_1_st: + st r0, [T1_VIRT_ADDR] ; TLBProtV causing instruction + mmu_disable ; MMU bye-bye! + ld r1, [T1_PHYS_ADDR] ; Load the final destination of "st" + cmp r1, T1_DATA_2 ; was it written successfuly? + bne @fail + b @test_1_end +test_1_except_handler: + add_s r2, r2, 1 + cmp r2, 1 ; TLBMissD while loading? + bne @1f + lr r11, [ecr] + cmp r11, TLB_MISS_D_READ; TLBMissD during a load? + bne @fail + lr r11, [eret] + cmp r11, @test_1_ld ; instruction causing the exception + lr r11, [efa] + cmp r11, T1_VIRT_ADDR ; faulty address is correct? + jne @fail + mov r11, 0 + sr r11, [efa] ; clearing EFA + mmu_tlb_insert T1_PD0, T1_PD1_R + rtie +1: + cmp r2, 2 ; ProtV during write? + bne @fail + lr r11, [ecr] + cmp r11, 0x60208 ; ProtV from MMU during a write? + bne @fail + lr r11, [eret] + cmp r11, @test_1_st ; instruction causing the exception + lr r11, [efa] + cmp r11, T1_VIRT_ADDR ; faulty address is correct? + jne @fail + mmu_tlb_insert T1_PD0, T1_PD1_RW + rtie +test_1_end: + ; Fall through + +; Test case 2 +; Load a double word data straddled over two consecutive virtual pages: +; ,-------------------------------.,-----------------------------. +; | ... x0 x1 x2 x3 || x4 x5 x6 x7 x8 ... | +; `-------------------------------'`-----------------------------' +; virt=0x0050_2000..0x0050_4000 virt=0x0050_4000..0x050_6000 +; +; Only the first page has an entry in TLB: +; ,-----------------.------------------.----------------------. +; | virtual address | physical address | (kernel) permissions | +; |-----------------+------------------+----------------------| +; | 0x0050_2000 | 0x3000_8000 | R-- | +; `-----------------^------------------^----------------------' +; +; An "ldd" from the last 4 byte of the first page will span to +; the second page. This will lead to an exception (TLBMissD). + .equ T2_VIRT_ADDR, 0x00502000 ; virtual page address + .equ T2_PHYS_ADDR, 0x30008000 ; physical page address + .equ T2_ADDR_OFS, 0x00001FFC ; the offset in the page + .equ T2_PD0, ((T2_VIRT_ADDR+T2_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD0_GLOBAL | REG_PD0_VALID) + .equ T2_PD1, ((T2_PHYS_ADDR & PAGE_NUMBER_MSK) | REG_PD1_KRNL_R) + + mmu_prep_test_case + mov r2, 0 ; exception handler counter + set_except_handler @test_2_except_handler + mmu_tlb_insert T2_PD0, T2_PD1 + mmu_enable +test_2_ldd: + ldd r0, [T2_VIRT_ADDR+T2_ADDR_OFS] + cmp r2, 1 + bne @fail + b @test_2_end ; success! +test_2_except_handler: + add r2, r2, 1 ; increase the counter + lr r11, [ecr] + cmp r11, 0x50100 ; TLBMissD during a load? + bne @fail + lr r11, [eret] + cmp r11, @test_2_ldd + jne @fail + lr r11, [efa] + cmp r11, T2_VIRT_ADDR+T2_ADDR_OFS+4 ; beginning of next page + jne @fail + mmu_disable + rtie +test_2_end: + ; Fall through + +; Test case 3 +; Load a data word (0x12345678) straddled over two consecutive +; virtual pages: +; ,--------------------.,--------------------. +; | ... 0x78 || 0x56 0x34 0x12 ... | +; `--------------------'`--------------------' +; virt=0x0000...0x2000 virt=0x2000...0x4000 +; +; Only the first page has an entry in TLB: +; ,-----------------.------------------.----------------------. +; | virtual address | physical address | (kernel) permissions | +; |-----------------+------------------+----------------------| +; | 0x0000_0000 | 0x7000_0000 | R-- | +; `-----------------^------------------^----------------------' +; +; An "ld" (word-sized) from the last byte of the first page will +; span to the first 3 bytes of the second page. This will lead +; to an exception (TLBMissD). The exception routine will add the +; entry for the second page: +; ,-----------------.------------------.----------------------. +; | virtual address | physical address | (kernel) permissions | +; |-----------------+------------------+----------------------| +; | 0x0000_0000 | 0x7000_0000 | R-- | +; | 0x0000_2000 | 0x6000_2000 | R-- | +; `-----------------^------------------^----------------------' +; +; And in the end, we must have fetched the data (0x12345678). +; To make the test realistic, the physical page addresses are not +; consecutive as opposed to their virtual counter parts. +; The alignment check should be disabled for this test. + .equ T3_VIRT_ADDR_1, 0x00000000 ; two virtual page addresses ... + .equ T3_VIRT_ADDR_2, 0x00002000 ; ... that are consecutive. + .equ T3_PHYS_ADDR_1, 0x70000000 ; two physical page addresses ... + .equ T3_PHYS_ADDR_2, 0x60002000 ; ... that are inconsecutive. + .equ T3_ADDR_1_OFS, 0x00001FFF ; the offset in the first pages. + .equ T3_PD0_ENT1, ((T3_VIRT_ADDR_1+T3_ADDR_1_OFS & PAGE_NUMBER_MSK) | REG_PD0_GLOBAL | REG_PD0_VALID) + .equ T3_PD1_ENT1, ((T3_PHYS_ADDR_1 & PAGE_NUMBER_MSK) | REG_PD1_KRNL_R) + .equ T3_PD0_ENT2, ((T3_VIRT_ADDR_2 & PAGE_NUMBER_MSK) | REG_PD0_GLOBAL | REG_PD0_VALID) + .equ T3_PD1_ENT2, ((T3_PHYS_ADDR_2 & PAGE_NUMBER_MSK) | REG_PD1_KRNL_R) + mmu_prep_test_case + ; Plant data at the physical addresses + mov r1, 0x12345678 + stb r1, [T3_PHYS_ADDR_1+T3_ADDR_1_OFS] ; 0x78 at the end of first page + lsr8 r1, r1 + sth r1, [T3_PHYS_ADDR_2] ; 0x56 0x34 at the beginning of 2nd page + lsr16 r1, r1 + stb r1, [T3_PHYS_ADDR_2+2] ; 0x12 The 3rd byte on the 2nd page + mov r1, 0 ; exception handler counter + disable_alignment + set_except_handler @test_3_except_handler + mmu_tlb_insert T3_PD0_ENT1, T3_PD1_ENT1 + mmu_enable + ; Exception-causing instruction +test_3_ld: + ld r0, [T3_VIRT_ADDR_1+T3_ADDR_1_OFS] + mov r3, 0x12345678 + cmp r0, r3 + bne @fail + cmp r1, 1 + bne @fail + b @test_3_end ; success! +test_3_except_handler: + add r1, r1, 1 ; increase the counter + lr r11, [ecr] + cmp r11, 0x50100 ; TLBMissD during a load? + bne @fail + lr r11, [eret] + cmp r11, @test_3_ld + jne @fail + lr r11, [efa] + cmp r11, @T3_VIRT_ADDR_2 + jne @fail + mmu_tlb_insert T3_PD0_ENT2, T3_PD1_ENT2 + rtie +test_3_end: + ; Fall through + +; Test case 4 +; Straddle a "branch" and its "delay slot" on two consecutive pages. +; The first virtual page has an entry in TLB, but the second one (which +; the delay slot is on) does not. We want to see when fetching the delay +; slot causes a TLBMissI, things will go back smoothly. +; +; first page with TLB entry +; ,-----. +; | ... | +; | nop | +; | b.d | branch instruction as the last instruction of the page +; `-----' +; ,-----. +; | dly | delay instruction on the next page +; | ... | +; | | +; `-----' +; second page without TLB entry + .equ T4_VIRT_ADDR, 0x00402000 ; virtual page address + .equ T4_PHYS_ADDR, 0x90008000 ; physical page address + .equ T4_ADDR_OFS, 0x00001FF8 ; the offset in the page + .equ T4_PD0, ((T4_VIRT_ADDR+T4_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD0_GLOBAL | REG_PD0_VALID) + .equ T4_PD1, ((T4_PHYS_ADDR+T4_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD1_KRNL_R | REG_PD1_KRNL_E) + .equ T4_size, test_4_embedded_code_end - test_4_embedded_code_start + + mmu_prep_test_case + ; Copy the embedded code into physical page + xor_s r3, r3, r3 + mov r0, @test_4_embedded_code_start + mov r1, @T4_PHYS_ADDR+T4_ADDR_OFS +test_4_copy: + ldb.ab r2, [r0, 1] + stb.ab r2, [r1, 1] + add_s r3, r3, 1 + cmp r3, T4_size + blt @test_4_copy + ; Add MMU + set_except_handler @test_4_except_handler + mmu_tlb_insert T4_PD0, T4_PD1 + mmu_enable + mov r1, T4_VIRT_ADDR+T4_ADDR_OFS ; jump to the copied code + j [r1] + ; Have embedded code word-aligned at a place where it will be put. + .align 4 +test_4_embedded_code_start: + nop + b.d @test_4_virt_finish + add r1, r0, r0 + nop + j @fail + nop +test_4_virt_finish: + j @test_4_end +test_4_embedded_code_end: +; Exception routine that will add entry for the second page +test_4_except_handler: + lr r11, [ecr] + cmp r11, TLB_MISS_I + bne @fail + lr r11, [eret] + cmp r11, @T4_VIRT_ADDR+0x2000 ; Beginning of second page? + jne @fail + lr r11, [efa] + cmp r11, @T4_VIRT_ADDR+0x2000 ; Beginning of second page? + jne @fail + lr r11, [bta] + cmp r11, @T4_VIRT_ADDR+T4_ADDR_OFS+T4_size-8 ; BTA correct? + jne @fail + lr r11, [erbta] + cmp r11, @T4_VIRT_ADDR+T4_ADDR_OFS+T4_size-8 ; ERBTA correct? + jne @fail + mmu_tlb_insert T4_PD0+0x2000, T4_PD1+0x2000 + rtie +test_4_end: + ; Fall through + +; Test case 5 +; Like previous test but with a "branch and link". This is even trickier. +; BL needs to decode the delay instruction to know its length. It uses +; this information to determine what value should "BLINK" register hold. +; Below is the pertinent semantic: +; +; delay_insn_addr = bl_insn_addr + bl_insn_len +; delay_insn_len = decode(delay_insn_addr) +; BLINK = bl_insn_addr + bl_insn_len + delay_insn_len +; +; If the "delay slot" instruction is on a missing page, a TLBMissI is +; raised during "decode(delay_insn_addr)". This all happens while the +; "BL" instruction is being handled (and not the delay slot): +; +; ecr = 0x40000 (TLBMissI) +; eret = bl_insn_addr --> for previous test, this is delay_insn_addr +; efa = delay_insn_addr +; bta = old value (not updated) +; blink = old value (not updated) + .equ T5_VIRT_ADDR, 0x00602000 ; virtual page address + .equ T5_PHYS_ADDR, 0xA0008000 ; physical page address + .equ T5_ADDR_OFS, 0x00001FF8 ; the offset in the page + .equ T5_PD0, ((T5_VIRT_ADDR+T5_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD0_GLOBAL | REG_PD0_VALID) + .equ T5_PD1, ((T5_PHYS_ADDR+T5_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD1_KRNL_R | REG_PD1_KRNL_E) + .equ T5_size, test_5_embedded_code_end - test_5_embedded_code_start + + mmu_prep_test_case + ; Copy the embedded code into physical page + xor_s r3, r3, r3 + mov r0, @test_5_embedded_code_start + mov r1, @T5_PHYS_ADDR+T5_ADDR_OFS +test_5_copy: + ldb.ab r2, [r0, 1] + stb.ab r2, [r1, 1] + add_s r3, r3, 1 + cmp r3, T5_size + blt @test_5_copy + ; Add MMU + set_except_handler @test_5_except_handler + mmu_tlb_insert T5_PD0, T5_PD1 + mmu_enable + lr r4, [bta] ; remember the old bta value + mov r5, blink ; remember the old blink value + mov r1, T5_VIRT_ADDR+T5_ADDR_OFS ; jump to the copied code + j [r1] + ; Have embedded code word-aligned at a place where it will be put. + .align 4 +test_5_embedded_code_start: + nop + bl.d @test_5_virt_finish + add r1, r0, r0 + nop + j @fail + nop +test_5_virt_finish: + j @test_5_end +test_5_embedded_code_end: +; Exception routine that will add entry for the second page +test_5_except_handler: + lr r11, [ecr] + cmp r11, TLB_MISS_I + bne @fail + lr r11, [eret] + cmp r11, @T5_VIRT_ADDR+0x2000-4 ; Last instruction of the first page (bl)? + jne @fail + lr r11, [efa] + cmp r11, @T5_VIRT_ADDR+0x2000 ; Beginning of second page? + jne @fail + lr r11, [bta] + cmp r11, r4 ; BTA not updated? (still old?) + jne @fail + lr r11, [erbta] + cmp r11, r4 ; ERBTA same as not-updated-BTA? + mov r11, blink + cmp r11, r5 ; BLINK not updated? (still old?) + jne @fail + mmu_tlb_insert T5_PD0+0x2000, T5_PD1+0x2000 + rtie +test_5_end: + ; Fall through + +; Test case 6: BLINK register must be updated immediately after "BL". + mmu_prep_test_case + bl.d @test_6_branch_taken + mov r0, blink +test_6_after_delay_slot: + b @fail + .align 4 +test_6_branch_taken: + mov r1, @test_6_after_delay_slot + cmp r0, r1 + bne @fail + +; Test case 7: BTA register must be updated immediately after "BL". + mmu_prep_test_case + bl.d @test_7_branch_taken + lr r0, [bta] + b @fail + .align 4 +test_7_branch_taken: + mov r1, @test_7_branch_taken + cmp r0, r1 + bne @fail + +;; Test case 8: Exceptions other than TLBMissI for the delay slot of BL +;; In this case, such exceptions are deep in decoding pipeline and should +;; cause a normal exception like any other instructions, where ERET is +;; pointing to the delay slot and not the BL instruction, like the previous +;; tests. +; mmu_prep_test_case +; set_except_handler @test_8_except_handler +; bl.d @test_8_end +;test_8_delay_slot: +; lr r0, [blink] ; InstructionError +; b @fail +;; Exception routine that will add entry for the second page +;test_8_except_handler: +; lr r11, [ecr] +; cmp r11, ILLEGAL_INSTRUCTION +; bne @fail +; lr r11, [eret] +; cmp r11, @test_8_delay_slot +; jne @fail +; lr r11, [efa] +; cmp r11, @test_8_delay_slot +; jne @fail +; lr r11, [erbta] +; cmp r11, @test_8_end +; jne @fail +; lr r11, [bta] +; cmp r11, @test_8_end +; jne @fail +; sr r11, [eret] ; Get out of delay slot by jumping to BTA +; lr r11, [erstatus] +; bclr r11, r11, 6 ; Clear delay slot execution flag +; sr r11, [erstatus] +; rtie +; b @fail +; .align 4 +;test_8_end: +; ; Fall through + +; Test case 9 +; Like test case 5, but the CC is false here. Although, there is no need +; for the calculation of BLINK and the _early_ decode of delay slot +; instruction, still TLBMissI exception for the delay slot instruction +; happens during the execution of "BLne.D". This is how the hardware +; works. +; ecr = 0x40000 (TLBMissI) +; eret = bl_insn_addr +; efa = delay_insn_addr +; bta = old value (not updated) +; blink = old value (not updated) + .equ T9_VIRT_ADDR, 0x00606000 ; virtual page address + .equ T9_PHYS_ADDR, 0xA000A000 ; physical page address + .equ T9_ADDR_OFS, 0x00001FF4 ; the offset in the page + .equ T9_PD0, ((T9_VIRT_ADDR+T9_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD0_GLOBAL | REG_PD0_VALID) + .equ T9_PD1, ((T9_PHYS_ADDR+T9_ADDR_OFS & PAGE_NUMBER_MSK) | REG_PD1_KRNL_R | REG_PD1_KRNL_E) + .equ T9_size, test_9_embedded_code_end - test_9_embedded_code_start + + mmu_prep_test_case + ; Copy the embedded code into physical page + xor_s r3, r3, r3 + mov r0, @test_9_embedded_code_start + mov r1, @T9_PHYS_ADDR+T9_ADDR_OFS +test_9_copy: + ldb.ab r2, [r0, 1] + stb.ab r2, [r1, 1] + add_s r3, r3, 1 + cmp r3, T9_size + blt @test_9_copy + ; Add MMU + set_except_handler @test_9_except_handler + mmu_tlb_insert T9_PD0, T9_PD1 + mmu_enable + lr r4, [bta] ; remember the old bta value + mov r1, T9_VIRT_ADDR+T9_ADDR_OFS ; jump to the copied code + j [r1] + ; Have embedded code word-aligned at a place where it will be put. + .align 4 +test_9_embedded_code_start: + add.f 0, 0, 0 + blne.d @fail + add r0, r0, r0 + j @test_9_end +test_9_embedded_code_end: +; Exception routine that will add entry for the second page +test_9_except_handler: + lr r11, [ecr] + cmp r11, TLB_MISS_I + bne @fail + lr r11, [eret] + cmp r11, @T9_VIRT_ADDR+0x2000-4 ; Last instruction of the first page (blne.d)? + jne @fail + lr r11, [efa] + cmp r11, @T9_VIRT_ADDR+0x2000 ; Beginning of second page? + jne @fail + lr r11, [bta] + cmp r11, r4 ; BTA not updated? (still old?) + jne @fail + lr r11, [erbta] + cmp r11, r4 ; ERBTA same as not updated BTA? + jne @fail + mmu_tlb_insert T9_PD0+0x2000, T9_PD1+0x2000 + rtie +test_9_end: + ; Fall through + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Reporting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +valhalla: + print "[PASS]" + b @1f + +.align 4 +; If a test fails, it jumps here. Although, for the sake of uniformity, +; the printed output does not say much about which test case failed, +; one can uncomment the print_number line below or set a breakpoint +; here to check the R0 register for the test case number. +fail: + ld r0, [mmu_test_nr] + ;print_number r0 + print "[FAIL]" +1: + print " MMU: manipulate MMU table in exception routines\n" + end diff --git a/tests/tcg/arc/check_mmu.S b/tests/tcg/arc/check_mmu.S new file mode 100644 index 0000000000..69a38e30d5 --- /dev/null +++ b/tests/tcg/arc/check_mmu.S @@ -0,0 +1,59 @@ +.include "macros.inc" +.include "mmu.inc" + +; courtesy of mmu.inc +.extern PAGE_NUMBER_MSK +.extern REG_PD0_GLOBAL +.extern REG_PD0_VALID +.extern REG_PD1_KRNL_W + +; test data +; making an entry for the TLB +; +; ,------------------------------------. +; | VPN(VA), G=1, V=1 | PPN(PHY), Wk=1 | +; `------------------------------------' +; where: +; VPN(VA) is the virtual page number of logical address +; G is the global bit +; V is the validity bit +; PPN(PHY) is the physical page number +; Wk is the write permission in kernel mode + +; obviously, the offsets in both addresses must be the same +.equ VIRT_ADR , 0x13371334 ; the virtual address; word aligned +.equ PHYS_ADR , 0x73311334 ; the physical address > 0x7FFFFFFF +.equ MAGICDATA, 0x00BADB07 ; the test value to write and verify +.equ PD0_VPN , (VIRT_ADR & PAGE_NUMBER_MSK) +.equ PD1_PPN , (PHYS_ADR & PAGE_NUMBER_MSK) +.equ PD0_BITS , (PD0_VPN | REG_PD0_GLOBAL | REG_PD0_VALID) +.equ PD1_BITS , (PD1_PPN | REG_PD1_KRNL_W) + +start + +mmu_enable + +; insert into table: VA 0x13371337 (Global) --> PHY: 0x73311337 (RW kernel) +mmu_tlb_insert PD0_BITS, PD1_BITS + +; write to the mapped virtual address +mov r0, MAGICDATA +st r0, [VIRT_ADR] + +mmu_disable + +; with mmu disabled, read from physical address and +; verify that it is the same as the value written +; to the mapped virtual address earlier +ld r1, [PHYS_ADR] +cmp r0, r1 ; r0 contains the MAGICDATA +beq @goodboy + +print "nope, still no MMU!\n" +j @adios + +goodboy: +print "Yay, you got the MMU right :)\n" + +adios: +end diff --git a/tests/tcg/arc/check_mpu.S b/tests/tcg/arc/check_mpu.S new file mode 100644 index 0000000000..e840b95403 --- /dev/null +++ b/tests/tcg/arc/check_mpu.S @@ -0,0 +1,703 @@ +; check_mpu.S +; +; Tests for MPUv3: Memory protection unit v3. +; If the test fails, check the end of this file for how to troubleshoot. + + .include "macros.inc" + .include "mpu.inc" + .include "mmu.inc" + +;;;;;;;;;;;;;;;;;;;;;;;;;;; Test checking routines ;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Test case counter +.data +test_nr: + .word 0x0 + +; Increment the test counter and set (Z,N,C,V) to (0,0,0,0). +.macro prep_test_case + ld r13, [test_nr] + add_s r13, r13, 1 ; increase test case counter + st r13, [test_nr] + add.f 0, 0, 1 ; (Z, N, C, V) = (0, 0, 0, 0) +.endm + +; macro: auxreg_write_read +; input: reg - the register we are talking about +; write - value to write +; read - value expected to be read +; regs used: r11, r12 +; example: auxreg_write_read mpuen, 0xffffffff, 0x400001f8 +; +; description: +; Not always, "write" and "read" values are the same. This true about +; the registers who have reserved bits or read as zero in user mode, +; etc. +; Be careful, what is the result of you writing to to "reg". It may +; have consequences like enabling page protection or so. +.macro auxreg_write_read reg, write, read + mov r11, \write + sr r11, [\reg] + ; using a different register to reduce the chande of false equality + lr r12, [\reg] + cmp r12, \read + bne @fail +.endm + + start + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; check the MPU_BUILD +test_00: + .equ VERSION , 0x03 + .equ NR_REGIONS, 0x08 + .equ MPU_BCR_REF, (NR_REGIONS << 8) | VERSION + lr r0, [mpu_build] + cmp r0, MPU_BCR_REF + bne @fail + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; All of the registers should be accessible in kernel mode +; this test (check_mpu) is based on 8 regions. +test_01: + prep_test_case + ; mpuen : momentarily enabled with full access + ; when read, only relevant bits must be set. + auxreg_write_read mpuen , 0xffffffff, 0x400001f8 + ; disable mpu at once + mpu_disable + auxreg_write_read mpurdb0 , 0xffffffff, 0xffffffe1 + auxreg_write_read mpurdp0 , 0xffffffff, 0x00000ffb + auxreg_write_read mpurdb1 , 0xffffffff, 0xffffffe1 + auxreg_write_read mpurdp1 , 0xffffffff, 0x00000ffb + auxreg_write_read mpurdb2 , 0xffffffff, 0xffffffe1 + auxreg_write_read mpurdp2 , 0xffffffff, 0x00000ffb + auxreg_write_read mpurdb3 , 0xffffffff, 0xffffffe1 + auxreg_write_read mpurdp3 , 0xffffffff, 0x00000ffb + auxreg_write_read mpurdb4 , 0xffffffff, 0xffffffe1 + auxreg_write_read mpurdp4 , 0xffffffff, 0x00000ffb + auxreg_write_read mpurdb5 , 0xffffffff, 0xffffffe1 + auxreg_write_read mpurdp5 , 0xffffffff, 0x00000ffb + auxreg_write_read mpurdb6 , 0xffffffff, 0xffffffe1 + auxreg_write_read mpurdp6 , 0xffffffff, 0x00000ffb + auxreg_write_read mpurdb7 , 0xffffffff, 0xffffffe1 + auxreg_write_read mpurdp7 , 0xffffffff, 0x00000ffb + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; None of the registers should be accessible in user mode +test_02: + prep_test_case + mpu_reset + ; prep the exception for the end + lr r0, [mpuic] ; don't care for mpu_ecr value + mpu_set_except_params mpu_ecr = r0 , \ + ecr = PRIVILEGE_VIOLATION , \ + efa = @test_02_user_space+4, \ + eret = @test_02_user_space+4, \ + continue = @test_02_end + enter_user_mode @test_02_user_space +test_02_user_space: + add r0, r0, r0 ; some filler to make a basic block + ; accessing MPU registers in user mode is not allowed + lr r0, [mpu_build] + b @fail ; an exception must have been raised +test_02_end: + ; Fall through + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Running with -global cpu.has-mpu=false or reading a region register +; which is higher than the configured number of regions causes an +; instuction error: ecr=0x020000 +test_03: + prep_test_case + mpu_reset + ; prep the exception for 'lr'ing a region that does not exist + lr r0, [mpuic] ; don't care for mpu_ecr value + mpu_set_except_params mpu_ecr = r0 , \ + ecr = ILLEGAL_INSTRUCTION , \ + efa = @test_03_illegal_lr_rgn, \ + eret = @test_03_illegal_lr_rgn, \ + continue = @test_03_cont +test_03_illegal_lr_rgn: + lr r1, [mpurdb15] + b @fail ; exception must have been raised +test_03_cont: + ; prep the exception for 'sr'ing a region that does not exist + lr r0, [mpuic] ; don't care for mpu_ecr value + mpu_set_except_params mpu_ecr = r0 , \ + ecr = ILLEGAL_INSTRUCTION , \ + efa = @test_03_illegal_sr_rgn, \ + eret = @test_03_illegal_sr_rgn, \ + continue = @test_03_end +test_03_illegal_sr_rgn: + sr r1, [mpurdp8] + b @fail ; an exception must have been raised +test_03_end: + ; Fall through + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Verifying the KR permission for region 1. +; Checking if "read" is OK and "write" raises an exception. +test_04: + .equ MEM_ADDR04 , 0x16000 + .equ DATA04 , 0x1337 + .equ MPU_ECR_W_R1, MPU_ECR_WRITE | 1 + prep_test_case + mpu_reset + mpu_add_base mpurdb1, MEM_ADDR04 + mpu_add_region mpurdp1, REG_MPU_EN_KR, MPU_SIZE_32B + mpu_write_data DATA04, MEM_ADDR04 + mpu_enable + ; read permission check + mpu_verify_data DATA04, MEM_ADDR04 + ; write permission check + mpu_set_except_params mpu_ecr = MPU_ECR_W_R1 , \ + ecr = PROTV_WRITE_MPU , \ + efa = MEM_ADDR04 , \ + eret = @test_04_illegal_store+4, \ + continue = @test_04_end +test_04_illegal_store: + add r0, r0, r0 ; filler; so exception happens in... + st r1, [MEM_ADDR04] ; ...the middle of a translation block + b @fail ; an exception must have been raised +test_04_end: + ; Fall through + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Having 2 small regions next to each other: one with write permission +; and the other with read permission. Check if permissions are respected +; accordingly. This tests how MPU sets QEmu's internal TLB and if it is +; able to set the TLB's entry size correctly. +test_05: + .equ MEM_ADDR05, 0x16024 ; 4 bytes above the multiple of 32 + .equ DATA05 , 0xbabe + prep_test_case + mpu_reset + mpu_add_base mpurdb0, MEM_ADDR05 ; effective address would be 0x4020 + mpu_add_region mpurdp0, REG_MPU_EN_KW, MPU_SIZE_32B + mpu_add_base mpurdb1, MEM_ADDR05+32; effective address would be 0x4040 + mpu_add_region mpurdp1, REG_MPU_EN_KR, MPU_SIZE_32B + mpu_write_data DATA05, MEM_ADDR05+32 ; write to 0x4044 (region1) + ; let the fun begin + mpu_enable + mpu_verify_data DATA05, MEM_ADDR05+32 + st r7, [MEM_ADDR05] ; write bogus data (region 0) + ; now time for some exception + mpu_set_except_params mpu_ecr = MPU_ECR_W_R1 , \ + ecr = PROTV_WRITE_MPU , \ + efa = MEM_ADDR05+32 , \ + eret = @test_05_illegal_store, \ + continue = @test_05_end +test_05_illegal_store: + st r7, [MEM_ADDR05+32] ; this shouldn't be allowed + b @fail ; an exception must have been raised +test_05_end: + ; Fall through + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Update a region's permission and size to check if they are taken +; into account. +test_06: + .equ MEM_ADDR06, 0x30000 + .equ MPU_ECR_R_R3, MPU_ECR_READ | 3 + prep_test_case + mpu_reset + mpu_add_base mpurdb3, MEM_ADDR06 + mpu_add_region mpurdp3, REG_MPU_EN_KR, MPU_SIZE_64B + mpu_enable + ld r7, [MEM_ADDR06+32] ; this should be allowed + ; changing permission (deliberately mpu is not disabled) + mpu_add_region mpurdp3, REG_MPU_EN_KE, MPU_SIZE_64B ; update (KR -> KE) + ; prep for exception + mpu_set_except_params mpu_ecr = MPU_ECR_R_R3 , \ + ecr = PROTV_READ_MPU , \ + efa = MEM_ADDR06+32 , \ + eret = @test_06_illegal_read, \ + continue = @test_06_change_size +test_06_illegal_read: + ld r7, [MEM_ADDR06+32] ; this is not allowed anymore + b @fail ; an exception must have been raised +test_06_change_size: + ; changing size (deliberately mpu is not disabled) + mpu_add_region mpurdp3, REG_MPU_EN_KE, MPU_SIZE_32B ; update (64 -> 32) + mpu_enable + ld r7, [MEM_ADDR06+32] ; this is allowed again (+32 is in def. region) + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Check a permission that has only execute permission. +; The read should not be possible. +test_07: + .equ NOP_OPCODE, 0x7000264a + .equ JR1_OPCODE, 0x00402020 + .equ CODE_CAVE07, 0x40000 + .equ MPU_ECR_R_R0, MPU_ECR_READ | 0 + prep_test_case + mpu_reset + mpu_add_base mpurdb0, CODE_CAVE07 + mpu_add_region mpurdp0, REG_MPU_EN_KE, MPU_SIZE_32B + mov r0, NOP_OPCODE + mov r1, @test_07_rest + mov r2, JR1_OPCODE + st r0, [CODE_CAVE07] ; nop + st r2, [CODE_CAVE07+4] ; j [r1] + st r0, [CODE_CAVE07+8] ; nop + mpu_enable + ; let's take a leap of faith + j CODE_CAVE07 + +test_07_rest: + ; wow, if we just came back, let's raise hell + mpu_set_except_params mpu_ecr = MPU_ECR_R_R0 , \ + ecr = PROTV_READ_MPU , \ + efa = CODE_CAVE07+4 , \ + eret = @test_07_illegal_read, \ + continue = @test_07_end +test_07_illegal_read: + ld r7, [CODE_CAVE07+4] ; this shouldn't be allowed + b @fail ; an exception must have been raised +test_07_end: + ; Fall through + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; One region to rule them all +; 1) We are testing a very big region here. +; 2) Moreover we change its permission and size in the middle +test_08: + .equ MEM_ADDR08 , 0x00000000 + .equ BIG_ADDR08 , 0x7FFFFFE0 + .equ MPU_ECR_W_R7 , MPU_ECR_WRITE | 7 + .equ MPU_ECR_R_DEF, MPU_ECR_READ | 0xFF + .equ DATA08_1 , 0x34fa ; random magic + .equ DATA08_2 , 0x987afb ; random magic + prep_test_case + mpu_reset + ; planting the data + mpu_write_data DATA08_1, BIG_ADDR08 + ; a 4 gigabyte region with read and execute permissions + mpu_add_base mpurdb7, MEM_ADDR08 + mpu_add_region mpurdp7, REG_MPU_EN_KR | REG_MPU_EN_KE , MPU_SIZE_4G + ; prepping exception (must be before enable, otherwise no write access) + mpu_set_except_params mpu_ecr = MPU_ECR_W_R7 , \ + ecr = PROTV_WRITE_MPU , \ + efa = BIG_ADDR08 , \ + eret = @test_08_illegal_write , \ + continue = @test_08_change_permission, \ + ; default region with only write permission + mpu_enable REG_MPU_EN_KW + ; checking read (BIG_ADDR08) and exec (current instruction) permissions + mpu_verify_data DATA08_1, BIG_ADDR08 +test_08_illegal_write: + st r7, [BIG_ADDR08] ; no write is allowed + b @fail ; an exception must have been raised +test_08_change_permission: + ; change permission _and_ size + mpu_add_region mpurdp7, REG_MPU_EN_FULL_ACCESS , MPU_SIZE_2G + ; now there should be no problem in writing either + mpu_write_data DATA08_2, BIG_ADDR08 + mpu_verify_data DATA08_2, BIG_ADDR08 + ; prepping second exception: default region has no read access + mpu_set_except_params mpu_ecr = MPU_ECR_R_DEF , \ + ecr = PROTV_READ_MPU , \ + efa = BIG_ADDR08+0xF0 , \ + eret = @test_08_illegal_def_read, \ + continue = @test_08_end +test_08_illegal_def_read: + ld r7, [BIG_ADDR08+0xF0] ; this is default region now and not sanctioned + b @fail ; an exception must have been raised +test_08_end: + ; Fall through + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; A user cannot have kernel permissions, but a kernel inherits granted +; user permissions as well. +test_09: + .equ MEM_ADDR09_1, 0x60000 + .equ MEM_ADDR09_2, 0x62000 ; 8k after + .equ MPU_ECR_W_R6, MPU_ECR_WRITE | 6 + .equ DATA09 , 0x89091 ; another random data from beyond + prep_test_case + mpu_reset + ; a region for user to write + mpu_add_base mpurdb5, MEM_ADDR09_1 + mpu_add_region mpurdp5, REG_MPU_EN_UW, MPU_SIZE_8K + ; a region only for kernel + mpu_add_base mpurdb6, MEM_ADDR09_2 + mpu_add_region mpurdp6, REG_MPU_EN_KR | REG_MPU_EN_KW, MPU_SIZE_8K + ; prep the exception for the end + mpu_set_except_params mpu_ecr = MPU_ECR_W_R6 , \ + ecr = PROTV_WRITE_MPU , \ + efa = MEM_ADDR09_2 , \ + eret = @test_09_user_space+8 , \ + continue = @test_09_rest_kernel_mode + ; let's have at it + mpu_enable REG_MPU_EN_UE | REG_MPU_EN_KR + enter_user_mode @test_09_user_space +test_09_user_space: + st r7, [MEM_ADDR09_2-4] ; write to the end of user region + st r7, [MEM_ADDR09_2] ; uh-oh: causing trouble + b @fail ; an exception must have been raised +test_09_rest_kernel_mode: + ; a simple write and verify chore in kernel mode + mpu_write_data DATA09, MEM_ADDR09_2+64 + mpu_verify_data DATA09, MEM_ADDR09_2+64 + ; also writing to user region because of implied write access + mpu_write_data DATA09, MEM_ADDR09_1+64 + mpu_disable ; else we cannot verify (no read access) + mpu_verify_data DATA09, MEM_ADDR09_1+64 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; A region with only user read access should not be fetchable. +test_10: + .equ CODE_CAVE10 , 0x100000 + .equ DATA10 , 0x010101 + .equ MPU_ECR_E_R4, MPU_ECR_FETCH | 4 + prep_test_case + mpu_reset + mpu_add_base mpurdb4, CODE_CAVE10 + mpu_add_region mpurdp4, REG_MPU_EN_UR, MPU_SIZE_64K + ; plant the data + mpu_write_data DATA10, CODE_CAVE10 + ; prep the exception for the region being not executable + mpu_set_except_params mpu_ecr = MPU_ECR_E_R4 , \ + ecr = PROTV_FETCH_MPU, \ + efa = CODE_CAVE10 , \ + eret = CODE_CAVE10 , \ + continue = @test_10_end + mpu_enable + enter_user_mode @test_10_user_space +test_10_user_space: + mpu_verify_data DATA10, CODE_CAVE10 ; read must be OK + j @CODE_CAVE10 ; this one not + b @fail ; an exception must have been raised +test_10_end: + ; Fall through + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; KE must be enough for raising exceptions. +; The tricky thing about this test is that it is allowing the +; parameters for the exceptions to be readable. As a result, +; the test assumes that there is 32 byte region that these +; parameters fit in AND it does not overlap with the exception +; routine itself. +test_11: + .equ MEM_ADDR11, 0x900 + prep_test_case + mpu_reset + ; allowing exception parameters to be read + mpu_add_base mpurdb0, @mpu_ecr_ref + mpu_add_region mpurdp0, REG_MPU_EN_KR, MPU_SIZE_32B + ; prep for the exception + mpu_set_except_params mpu_ecr = MPU_ECR_R_DEF , \ + ecr = PROTV_READ_MPU , \ + efa = MEM_ADDR11 , \ + eret = @test_11_illegal_read, \ + continue = @test_11_end + mpu_enable REG_MPU_EN_KE + add r0, r0, r0 ; just a random guy making a difference +test_11_illegal_read: + ld r0, [MEM_ADDR11] + b @fail ; an exception must have been raised +test_11_end: + mpu_disable + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Double exception must raise Machine Check with memory management disabled. +; This test hangs in nSIM if MMU exists. Apparently, nSIM sets the halt flag +; if a MachineCheck is raised and there is MMU in the system. The presence +; of MMU is necessary for test 14. +test_12: + .equ MPU_ECR_E_DEF, MPU_ECR_FETCH | 0xFF + prep_test_case + mpu_reset + ; enable MPU with no access whatsoever + mpu_enable 0x0 +test_12_doomed: + add r0, r0, r0 + lr r0, [mpuen] + cmp r0, 0 + bne @fail + j @test_12_end + ; the machine check routine to be executed eventually + .global EV_MachineCheck + .type EV_MachineCheck, @function + .align 4 +EV_MachineCheck: + lr r0, [mpuen] + cmp r0, REG_MPU_EN_EN + bne @fail + lr r0, [mpuic] + cmp r0, MPU_ECR_E_DEF + bne @fail + lr r0, [ecr] + cmp r0, MACHINE_CHECK + bne @fail + lr r0, [eret] + cmp r0, @test_12_doomed + bne @fail + lr r1, [efa] + cmp r0, r1 + bne @fail + mpu_disable ; disable MPU in a civilized way + lr r0, [erstatus] ; undo the mess: + and r0, r0, ~32 ; clear AE bit + sr r0, [erstatus] ; and + rtie ; return +test_12_end: + ; Fall through + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Page size for the default region: best effort 8K, else 1 byte. You need +; to look into tracing to see if it is doing the right thing. +test_13: + .equ TWO_PAGES_BEFORE , 0x7C000 + .equ ONE_PAGE_BEFORE , 0x7E000 + .equ MEM_ADDR13_1 , 0x80000 + .equ SAME_PAGE_BETWEEN, 0x80050 + .equ MEM_ADDR13_2 , 0x80100 + .equ SAME_PAGE_AFTER , 0x81000 + .equ ONE_PAGE_AFTER , 0x82000 + .equ MPU_ECR_R_R1 , MPU_ECR_READ | 1 + prep_test_case + mpu_reset + mpu_add_base mpurdb3, MEM_ADDR13_1 ; \ + mpu_add_region mpurdp3, 0x0, MPU_SIZE_32B ; | two black holes + mpu_add_base mpurdb1, MEM_ADDR13_2 ; | alike regions + mpu_add_region mpurdp1, 0x0, MPU_SIZE_32B ; / + ; your exception shall be your salvation + mpu_set_except_params mpu_ecr = MPU_ECR_R_R1 , \ + ecr = PROTV_READ_MPU , \ + efa = MEM_ADDR13_2 , \ + eret = @test_13_illegal_read, \ + continue = @test_13_end + mpu_enable + ld r0, [TWO_PAGES_BEFORE+0x1000] ; must cache the page + ld r0, [TWO_PAGES_BEFORE+0x1100] ; reuse same information + ld r0, [ONE_PAGE_BEFORE +0x1FFC] ; oooh, just before the black hole + ld r0, [ONE_PAGE_BEFORE +0x0500] ; reuse from above + ld r0, [SAME_PAGE_BETWEEN ] ; too narrow to cache the page + ld r0, [SAME_PAGE_BETWEEN+0x10 ] ; permissions must be totally checked + ld r0, [SAME_PAGE_AFTER ] ; same page as the black holes + ld r0, [SAME_PAGE_AFTER+0x10 ] ; no caching must be used + ld r0, [ONE_PAGE_AFTER ] ; this area is safe and ... + ld r0, [ONE_PAGE_AFTER+0x04 ] ; ...can be cached +test_13_illegal_read: + ld r0, [MEM_ADDR13_2 ] ; oops! + b @fail ; an exception must have been raised +test_13_end: + ; Fall through + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; MMU and MPU may coexist but do not overlap. +; This test assumes an "rwe" access for exception routine checks and an "re" +; access for the page this test case is loaded in. If these two pages happen +; to be the same, e.g. previous tests are commented out, then things will +; get nasty, because the last attribute will be used for both. +test_14: + .equ MMU_KRNL_RE , REG_PD1_KRNL_E | REG_PD1_KRNL_R + .equ MMU_KRNL_RWE, REG_PD1_KRNL_E | REG_PD1_KRNL_W | REG_PD1_KRNL_R + .equ MMU_VPN_GV , REG_PD0_GLOBAL | REG_PD0_VALID + .equ MEM_ADDR14 , 0x80000100 ; an address in MPU's interest + ; creates an entry in TLB with given permissions. + ; the translation is identical (virt = physical) + .macro add_mmu_entry addr, permission + mov r2, \addr + and r2, r2, PAGE_NUMBER_MSK + or r3, r2, \permission ; r3 holds physical address and permissoins + or r2, r2, MMU_VPN_GV ; r2 is a global valid virtual address + mmu_tlb_insert r2, r3 ; add entry for MMU + .endm + prep_test_case + mpu_reset + b @test_14_after_align + ; guarantee that current page won't be the same as @mp_ecr_ref's page + .align 0x2000 +test_14_after_align: + ; add a read/write/execute permission for exception part page + ; @mpu_ecr_ref and ProtV handler must be in the same page. + add_mmu_entry @mpu_ecr_ref, MMU_KRNL_RWE + ; add a read/write/execute permission for vector table. + add_mmu_entry 0x0, MMU_KRNL_RWE + ; add a read/execute permission for current page + lr r1, [pc] + add_mmu_entry r1, MMU_KRNL_RE + ; exception for writing to the (2nd) MMU page + lr r0, [mpuic] ; don't care for mpu_ecr value + mpu_set_except_params mpu_ecr = r0 , \ + ecr = PROTV_WRITE_MMU , \ + efa = r1 , \ + eret = @test_14_illegal_write, \ + continue = @test_14_mpu + ; enable the guys + mmu_enable ; enable MMU + mpu_enable REG_MPU_EN_KW ; enable MPU with kernel write access + ; this is happening in MMU's territory +test_14_illegal_write: + st r0, [r1] ; no write for this entry in TLB + b @fail ; an exception must have been raised + +test_14_mpu: + add r0, r0, r0 ; a happy camper + st r0, [MEM_ADDR14] ; in MPU realm + ; MPU exception now + mpu_set_except_params mpu_ecr = MPU_ECR_R_DEF , \ + ecr = PROTV_READ_MPU , \ + efa = MEM_ADDR14 , \ + eret = @test_14_illegal_read, \ + continue = @test_14_end +test_14_illegal_read: + ld r0, [MEM_ADDR14] ; uh-oh... + b @fail ; an exception must have been raised +test_14_end: + mpu_disable + mmu_disable + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Two overlapping regions test. One is 2 pages long and the other is inside +; the second page of the first region: +; ,----------. +; | R2:rw- | region nr 2 with read/write permission. +; page1 | | +; | | +; .......|..........|....... +; | | +; page2 |,________.| +; ||R1:r-- || region nr 1 with read only permission. +; |`--------'| this region is inside region nr 2. +; `----------' +; setup: R2 is 16kb with rw- +; R1 is 4kb with r-- +; write to the first page --> must go ok. +; write to the first half of page 2 --> must go ok. +; write to R1 --> expect an exception. +; in the end read from R1 --> must go ok. +test_15: + .equ MEM_ADDR15_R2 , 0x150000 + .equ MEM_ADDR15_R2_P2, MEM_ADDR15_R2 + PAGE_SIZE + .equ MEM_ADDR15_R1 , MEM_ADDR15_R2_P2 + PAGE_SIZE/2 + .equ DATA15_1 , 0x3ff0293f ; random magic + .equ DATA15_2 , DATA15_1+1 + .equ DATA15_3 , DATA15_1+2 + .equ MPU_ECR_W_R1, MPU_ECR_WRITE | 1 + prep_test_case + mpu_reset + mpu_add_base mpurdb1, MEM_ADDR15_R1 + mpu_add_region mpurdp1, REG_MPU_EN_KR, MPU_SIZE_4K + mpu_add_base mpurdb2, MEM_ADDR15_R2 + mpu_add_region mpurdp2, REG_MPU_EN_KR|REG_MPU_EN_KW, MPU_SIZE_16K + ; planting some data (for later read) + mpu_write_data DATA15_1, MEM_ADDR15_R1+24 + ; let the fun begin + mpu_enable + mpu_write_data DATA15_2, MEM_ADDR15_R2+20 + mpu_verify_data DATA15_2, MEM_ADDR15_R2+20 + mpu_write_data DATA15_3, MEM_ADDR15_R2+20+PAGE_SIZE + mpu_verify_data DATA15_3, MEM_ADDR15_R2+20+PAGE_SIZE + ; now time for some exception + mpu_set_except_params mpu_ecr = MPU_ECR_W_R1 , \ + ecr = PROTV_WRITE_MPU , \ + efa = MEM_ADDR15_R1+24 , \ + eret = @test_15_illegal_store, \ + continue = @test_15_cont + st r7, [MEM_ADDR15_R2_P2+32] ; write bogus data (region 2, page 2) +test_15_illegal_store: + st r7, [MEM_ADDR15_R1+24] ; this shouldn't be allowed + b @fail ; an exception must have been raised +test_15_cont: + mpu_verify_data DATA15_1, MEM_ADDR15_R1+24 ; this is allowed + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Another overlapping regions test. In previous one, a page (nr=2) was split +; among two regions. in this test, the page is contained inside another +; region, which in return is inside yet another region: +; ,----------. +; page1 | R5:r--- | region nr 5 with read only permission. +; .......|..........|....... +; page2 | | +; .......|..........|....... +; page3 | | +; .......|..........|....... +; page4 | | +; .......|,________.|....... +; page5 ||R3:-w- || region nr 3 with write only permission. +; .......||........||....... +; page6 || || this region is inside region nr 5. +; .......|`--------'|....... +; page7 | | +; .......|..........|....... +; page8 | | +; `----------' +; setup: R3 is 16kb with -w- +; R5 is 64kb with r-- +; read from the fourth page --> must go ok. +; read from page 7 --> must go ok. +; write to page 4 --> expect an exception. +; write to page 5 --> must go ok. +; read from page 6 --> expect an exception. +test_16: + .equ MEM_ADDR16_R5 , 0x160000 + .equ MEM_ADDR16_R5_P4, MEM_ADDR16_R5 + 3*PAGE_SIZE + .equ MEM_ADDR16_R5_P7, MEM_ADDR16_R5 + 6*PAGE_SIZE + .equ MEM_ADDR16_R3 , MEM_ADDR16_R5 + 4*PAGE_SIZE + .equ MEM_ADDR16_R3_P5, MEM_ADDR16_R3 + .equ MEM_ADDR16_R3_P6, MEM_ADDR16_R5 + 5*PAGE_SIZE + .equ DATA16_1 , 0x93822093 ; random magic + .equ DATA16_2 , DATA16_1+1 + .equ DATA16_3 , DATA16_1+2 + .equ MPU_ECR_R_R3, MPU_ECR_READ | 3 + .equ MPU_ECR_W_R5, MPU_ECR_WRITE | 5 + prep_test_case + mpu_reset + mpu_add_base mpurdb3, MEM_ADDR16_R3 + mpu_add_region mpurdp3, REG_MPU_EN_KW, MPU_SIZE_16K + mpu_add_base mpurdb5, MEM_ADDR16_R5 + mpu_add_region mpurdp5, REG_MPU_EN_KR, MPU_SIZE_64K + ; planting some data (for later read) + mpu_write_data DATA16_1, MEM_ADDR16_R5_P4+24 + mpu_write_data DATA16_3, MEM_ADDR16_R5_P7+24 + ; let the fun begin + mpu_enable + mpu_verify_data DATA16_1, MEM_ADDR16_R5_P4+24 + mpu_verify_data DATA16_3, MEM_ADDR16_R5_P7+24 + ; first exception because of writing in region 5 + mpu_set_except_params mpu_ecr = MPU_ECR_W_R5 , \ + ecr = PROTV_WRITE_MPU , \ + efa = MEM_ADDR16_R5_P4+24 , \ + eret = @test_16_illegal_store, \ + continue = @test_16_cont +test_16_illegal_store: + st r7, [MEM_ADDR16_R5_P4+24] ; this shouldn't be allowed + b @fail ; an exception must have been raised +test_16_cont: + mpu_write_data DATA16_2, MEM_ADDR16_R3_P5+24 ;will be checked later + ; second exception while reading in region 3 + mpu_set_except_params mpu_ecr = MPU_ECR_R_R3 , \ + ecr = PROTV_READ_MPU , \ + efa = MEM_ADDR16_R3_P6+24 , \ + eret = @test_16_illegal_read, \ + continue = @test_16_end +test_16_illegal_read: + ld r7, [MEM_ADDR16_R3_P6+24] ; this shouldn't be allowed + b @fail ; an exception must have been raised +test_16_end: + mpu_disable + mpu_verify_data DATA16_2, MEM_ADDR16_R3_P5+24 ; check if written + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Reporting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +valhalla: + print "[PASS]" + b @1f + +; If a test fails, it jumps here. Although, for the sake of uniformity, +; the printed output does not say much about which test case failed, +; one can uncomment the print_number line below or set a breakpoint +; here to check the R0 register for the test case number. +fail: + ld r0, [test_nr] + print "[FAIL" + print ":" + print_number r0 + print "]" +1: + print " MPUv3: Memory protection unit v3.\n" + end diff --git a/tests/tcg/arc/check_mpyd.S b/tests/tcg/arc/check_mpyd.S new file mode 100644 index 0000000000..1e94431d21 --- /dev/null +++ b/tests/tcg/arc/check_mpyd.S @@ -0,0 +1,543 @@ +; check_mpyd.S +; +; Tests for mpyd: mpyd mpydu +; If the test fails, check the end of this file for how to troubleshoot. + + .include "macros.inc" + +;;;;;;;;;;;;;;;;;;;;;;;;;;; Test checking routines ;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Test case counter +.data +test_nr: + .word 0x0 + +; Increment the test counter and set (Z,N,C,V) to (0,0,0,0). +.macro prep_test_case + ld r13, [test_nr] + add_s r13, r13, 1 ; increase test case counter + st r13, [test_nr] + add.f 0, 0, 1 ; (Z, N, C, V) = (0, 0, 0, 0) +.endm + +; These flag checking macros do not directly load the +; status32 register. Instead, they rely on the value +; provided by the caller. The rationale is with all these +; "cmp"s status32 will change. One must use a recorded +; version of status32 at the right time and then try the +; macros. +.macro check_Z_is_clear status + mov r11, \status + mov r12, REG_STAT_Z + and r11, r11, r12 + cmp r11, 0 + bne @fail +.endm +.macro check_N_is_set status + mov r11, \status + mov r12, REG_STAT_N + and r11, r11, r12 + cmp r11, REG_STAT_N + bne @fail +.endm +.macro check_N_is_clear status + mov r11, \status + mov r12, REG_STAT_N + and r11, r11, r12 + cmp r11, 0 + bne @fail +.endm +.macro check_V_is_set status + mov r11, \status + mov r12, REG_STAT_V + and r11, r11, r12 + cmp r11, REG_STAT_V + bne @fail +.endm +.macro check_V_is_clear status + mov r11, \status + mov r12, REG_STAT_V + and r11, r11, r12 + cmp r11, 0 + bne @fail +.endm + +; pair(HI, LOW) == pair(REG_HI, REG_LO) == pair(R59, R58) +.macro check_64bit_result hi, low, reg_hi, reg_lo + mov r11, \hi + mov r10, \low + cmp r11, \reg_hi + bne @fail + cmp r11, r59 + bne @fail + cmp r10, \reg_lo + bne @fail + cmp r10, r58 + bne @fail +.endm + +; (Z, N, C, V) = (0, 0, 0, 1) +.macro clear_N_set_V + mov r11, 0x80000000 ; very small negative number + add.f 0, r11, r11 ; cause an overflow (with carry) + rol.f 0, 0x01 ; keep the V flag, set the rests to 0 +.endm + +; (Z, N, C, V) = (0, 1, 0, 1) +.macro set_N_set_V + add.f 0, 0x7fffffff, 1 ; negative result with an overflow +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;; Exception related code ;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; parameters that an IllegalInstruction exception may set. + .align 4 +ecr_ref : .word ILLEGAL_INSTRUCTION +addr_ref : .word 0x0 ; for both eret and efa +cont_addr: .word 0x0 + +; exception: IllegalInstruction +; regs used: r11, r12 +; +; A parameterized IllegalInstruction exception that checks the followings: +; ecr == Illegal instruction +; efa == efa_ref +; eret == eret_ref +; If everything passes, it will jump to 'cont_addr' parameter. The parameters +; must be set beforehand using 'set_except_params' macro. This requires +; ivt.S file to be compiled and linked. + .align 4 + .global instruction_error + .type instruction_error, @function +instruction_error: + ld r11, [ecr_ref] + lr r12, [ecr] + cmp r12, r11 + bne @fail + ld r11, [addr_ref] + lr r12, [eret] + cmp r12, r11 + bne @fail + lr r12, [efa] + cmp r12, r11 + bne @fail + ; Success: continuing + ld r11, [cont_addr] + sr r11, [eret] + rtie + +; macro: set_except_params +; regs used: r11 +; +; This macro writes the provided parameters to a temporary place holder +; that later will be used by exception above to verify as reference. +.macro set_except_params addr, continue + mov r11, \addr + st r11, [addr_ref] + mov r11, \continue + st r11, [cont_addr] +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; MPYD ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Let the tests begin + start + +; Test case 1 +; reg4 <- reg4, reg4 +; 1 = (-1)*(-1) + prep_test_case + mov r4, -1 + mpyd r4, r4, r4 + check_64bit_result 0x0, 0x1, r5, r4 + +; Test case 2 +; reg0 <- reg1, reg0 +; 0 = 0 * 0x22334455 + prep_test_case + mov r0, 0x22334455 ; bogus data + mov r1, 0 + set_N_set_V ; (Z,N,C,V)=(0,1,0,1) + mpyd.f r0, r1, r0 + lr r5, [status32] ; take a snapshot of statu32 as is + check_Z_is_clear r5 + check_N_is_clear r5 + check_V_is_clear r5 + check_64bit_result 0x0, 0x0, r1, r0 + +; Test case 3 +; reg2 <- reg3, limm +; 0xc0000000_80000000 = 0x7ffffffff*0x80000000 +; -4611686016279904256= 2147483647 * -2147483648 + prep_test_case + mov r3, 0x7fffffff ; biggest 32-bit positive number + clear_N_set_V ; (Z,N,C,V)=(0,0,0,1) + mpyd.f r2, r3, 0x80000000 ; smallest 32-bit negative number + lr r5, [status32] ; take a snapshot of statu32 as is + check_N_is_set r5 + check_V_is_clear r5 + check_64bit_result 0xc0000000, 0x80000000, r3, r2 + +; Test case 4 +; reg2 <- limm, reg3 +; 0xffffffff_87654321 = 0x87654321 * 1 +; This is like a sign extension + prep_test_case + mov r3, 1 + clear_N_set_V ; (Z,N,C,V)=(0,0,0,1) + mpyd.f r2, 0x87654321, r3 + lr r5, [status32] ; take a snapshot of statu32 as is + check_N_is_set r5 + check_V_is_clear r5 + check_64bit_result 0xffffffff, 0x87654321, r3, r2 + +; Test case 5 +; reg0 <- limm, limm +; 0x3fffffff_00000001 = 0x7fffffff*0x7fffffff +; 4611686014132420609 = 2147483647*2147483647 + prep_test_case + set_N_set_V ; (Z,N,C,V)=(0,1,0,1) + mpyd r0, 0x7fffffff, 0x7fffffff + lr r5, [status32] ; take a snapshot of statu32 as is + check_N_is_set r5 + check_V_is_set r5 + check_64bit_result 0x3fffffff, 0x00000001, r1, r0 + +; Test case 6 +; 0 <- limm, limm only (acch,accl) will be set. +; It is expected that V=0 and N=0 +; 4761 = 69 * 69 + prep_test_case + set_N_set_V ; (Z,N,C,V)=(0,1,0,1) + mpyd.f 0, 69, 69 + lr r5, [status32] ; take a snapshot of statu32 as is + check_N_is_clear r5 + check_V_is_clear r5 + check_64bit_result 0, 4761, r59, r58 + +; Test case 7 +; 0 <- limm, u6 only (acch,accl) will be set. +; Checking that a result of 0 does not set the Z flag. +; 0 = 0x12345678 * 0 + prep_test_case + set_N_set_V ; (Z,N,C,V)=(0,1,0,1) + mpyd.f 0, 0x12345678, 0 + lr r5, [status32] ; take a snapshot of statu32 as is + check_Z_is_clear r5 ; Z must have remained 0 + check_N_is_clear r5 + check_V_is_clear r5 + check_64bit_result 0, 0, r59, r58 + +; Test case 8 +; 0 <- reg2, limm (V is already 1) +; Nothing should change, other than (acch,accl). +; 0x2468a = 2 * 0x12345 + prep_test_case + mov r2, 2 + clear_N_set_V ; (Z,N,C,V)=(0,0,0,1) + mpyd 0, r2, 0x12345 + lr r5, [status32] ; take a snapshot of statu32 as is + check_V_is_set r5 + check_64bit_result 0, 0x2468a, r59, r58 + +; Test case 9 +; reg0 <- reg2, u6 +; -63 = -1 * 63 + prep_test_case + mov r2, -1 + mpyd r0, r2, 63 + check_64bit_result 0xffffffff, 0xffffffc1, r1, r0 + +; Test case 10 +; reg2 <- limm, u6 +; 0x2_7d27d268 = 0x12345678 * 35 + prep_test_case + mpyd r2, 0x12345678, 35 + check_64bit_result 0x00000002, 0x7d27d268, r3, r2 + +; Test case 11 +; reg4 <- reg4, s12 +; 0x0000002f_1c71c71c = 0x87654321 * 0xf9c +; 202340681500 = -2023406815 * -100 + prep_test_case + mov r4, 0x87654321 + mpyd r4, r4, -100 + check_64bit_result 0x0000002f, 0x1c71c71c, r5, r4 + +; Test case 12 +; 0 <- limm, s12 +; It is expected that V is cleared and N=1 +; -1250000 = -10000 * 125 + prep_test_case + clear_N_set_V ; (Z,N,C,V)=(0,0,0,1) + mpyd.f 0, -10000 , 125 + lr r5, [status32] ; take a snapshot of statu32 as is + check_N_is_set r5 + check_V_is_clear r5 + check_64bit_result -1, -1250000, r59, r58 + +; Test case 13 +; Testing when cc condition is met +; 0 <- limm, u6 (V is already set) +; It is expected that V is cleared and N=1 +; -126 = -2 * 63 + prep_test_case + clear_N_set_V ; (Z,N,C,V)=(0,0,0,1) + mpyd.v.f 0, -2, 63 + lr r5, [status32] ; take a snapshot of statu32 as is + check_N_is_set r5 + check_V_is_clear r5 + check_64bit_result -1, -126, r59, r58 + +; Test case 14 +; Testing when cc condition is not met +; reg0 <- reg0, reg2 (V is already set) +; It is expected that V is remanins set + prep_test_case + clear_N_set_V ; (Z,N,C,V)=(0,0,0,1) + mov r0, 0xc0de ; must remain ... + mov r1, 0x1337 ; ... (0x1337,0xc0de) + mov r2, 0xf00d ; don't care ... + mov r3, 0xbad ; as long as not (0x0,0x1) + mov r4, r58 ; record accl + mov r5, r59 ; record acch + mpyd.nv.f r0, r0, r2 + lr r2, [status32] ; take a snapshot of statu32 as is + check_V_is_set r2 + cmp r1, 0x1337 + bne @fail + cmp r0, 0xc0de + bne @fail + check_64bit_result r5, r4, r59, r58 + +; Test case 15 +; Raise an Illegal Instruction exception if an odd register as dest. + prep_test_case + set_except_params @test_15_exception, @test_15_end +test_15_exception: + mpyd r3, r2, r4 + b @fail +test_15_end: + ; Fall through + +; Test case 16 +; Raise an Illegal Instruction exception if an odd register as dest. +; The exception should be made even if the CC indicates no execution. + prep_test_case + set_except_params @test_16_exception, @test_16_end + add.f 0,0,1 ; (Z,N,C,V)=(0,0,0,0) +test_16_exception: + mpyd.z r1, r1, r4 + b @fail +test_16_end: + ; Fall through + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; MPYDU ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Test case 17 +; reg2 <- reg2, reg2 +; 1 = (-1)*(-1) +; 0xfffffffe_00000001 = 0xffffffff * 0xffffffff + prep_test_case + mov r2, -1 + mpydu r2, r2, r2 + check_64bit_result 0xfffffffe, 0x00000001, r3, r2 + +; Test case 18 +; reg2 <- reg3, reg2 +; 0 = 0 * 0x22334455 + prep_test_case + mov r2, 0x22334455 ; bogus data + mov r3, 0 + set_N_set_V ; (Z,N,C,V)=(0,1,0,1) + mpydu.f r2, r3, r2 + lr r5, [status32] ; take a snapshot of statu32 as is + check_Z_is_clear r5 + check_N_is_set r5 + check_V_is_clear r5 + check_64bit_result 0x0, 0x0, r3, r2 + +; Test case 19 +; reg2 <- reg3, limm +; 0x3fffffff_80000000 = 0x7ffffffff*0x80000000 +; 4611686016279904256 = 2147483647 * 2147483648 + prep_test_case + mov r3, 0x7fffffff ; what used to be the largest 32-bit number + clear_N_set_V ; (Z,N,C,V)=(0,0,0,1) + mpydu.f r2, r3, 0x80000000 ; just another positive number + lr r5, [status32] ; take a snapshot of statu32 as is + check_V_is_clear r5 + check_64bit_result 0x3fffffff, 0x80000000, r3, r2 + +; Test case 20 +; reg4 <- limm, reg5 +; 0x00000000_87654321 = 0x87654321 * 1 +; This is like an unsigned extension + prep_test_case + mov r5, 1 + set_N_set_V ; (Z,N,C,V)=(0,1,0,1) + mpydu.f r4, 0x87654321, r5 + lr r3, [status32] ; take a snapshot of statu32 as is + check_N_is_set r3 + check_V_is_clear r3 + check_64bit_result 0x00000000, 0x87654321, r5, r4 + +; Test case 21 +; reg0 <- limm, limm +; 0x40000000_00000000 = 0x80000000*0x80000000 +; 4611686018427387904 = 2147483648*2147483648 + prep_test_case + set_N_set_V ; (Z,N,C,V)=(0,1,0,1) + mpydu r0, 0x80000000, 0x80000000 + lr r5, [status32] ; take a snapshot of statu32 as is + check_N_is_set r5 + check_V_is_set r5 + check_64bit_result 0x40000000, 0x00000000, r1, r0 + +; Test case 22 +; 0 <- limm, limm only (acch,accl) will be set. +; It is expected that V=0 and N=0 +; 3876961 = 1969 * 1969 + prep_test_case + set_N_set_V ; (Z,N,C,V)=(0,1,0,1) + mpydu.f 0, 1969, 1969 + lr r5, [status32] ; take a snapshot of statu32 as is + check_N_is_set r5 + check_V_is_clear r5 + check_64bit_result 0, 3876961, r59, r58 + +; Test case 23 +; 0 <- limm, u6 only (acch,accl) will be set. +; Checking that a result of 0 does not set the Z flag. +; 0 = 0x12345678 * 0 + prep_test_case + set_N_set_V ; (Z,N,C,V)=(0,1,0,1) + mpydu.f 0, 0x12345678, 0 + lr r5, [status32] ; take a snapshot of statu32 as is + check_Z_is_clear r5 ; Z must have remained 0 + check_N_is_set r5 + check_V_is_clear r5 + check_64bit_result 0, 0, r59, r58 + +; Test case 24 +; 0 <- reg2, limm (V is already 1) +; Nothing should change, other than (acch,accl). +; 0x00001eac_0d5d17a4 = 0x1af54154 * 0x12345 +; 33724307412900 = 452280660 * 74565 + prep_test_case + mov r2, 0x1af54154 ; I let an ant walk on the keyboard + clear_N_set_V ; (Z,N,C,V)=(0,0,0,1) + mpydu 0, r2, 0x12345 + lr r5, [status32] ; take a snapshot of statu32 as is + check_V_is_set r5 + check_64bit_result 0x1eac, 0x0d5d17a4, r59, r58 + +; Test case 25 +; reg0 <- reg2, u6 +; 0x3e_ffffffc1 = 0xffffffff * 0x3f +; 270582939585 = 4294967295 * 63 + prep_test_case + mov r2, -1 + mpydu r0, r2, 63 + check_64bit_result 0x3e, 0xffffffc1, r1, r0 + +; Test case 26 +; reg4 <- limm, u6 +; 0x2_7d27d268 = 0x12345678 * 35 + prep_test_case + mpydu r4, 0x12345678, 35 + check_64bit_result 0x00000002, 0x7d27d268, r5, r4 + +; Test case 27 +; reg2 <- reg2, s12 +; 0x000003e3_8e36b328 = 0xfedcba09 * 0x3e8 +; 4275878409000 = 4275878409 * 1000 + prep_test_case + mov r2, 0xfedcba09 + mpydu r2, r2, 1000 + check_64bit_result 0x000003e3, 0x8e36b328, r3, r2 + +; Test case 28 +; 0 <- limm, s12 +; It is expected that V is cleared +; 1250000 = 10000 * 125 + prep_test_case + clear_N_set_V ; (Z,N,C,V)=(0,0,0,1) + mpydu.f 0, 10000 , 125 + lr r5, [status32] ; take a snapshot of statu32 as is + check_V_is_clear r5 + check_64bit_result 0, 1250000, r59, r58 + +; Test case 29 +; Testing when cc condition is met +; 0 <- limm, u6 (V is already set) +; It is expected that V is cleared and N=1 +; 1781818164 = 28282828 * 63 + prep_test_case + set_N_set_V ; (Z,N,C,V)=(0,1,0,1) + mpydu.n.f 0, 28282828, 63 + lr r5, [status32] ; take a snapshot of statu32 as is + check_N_is_set r5 + check_V_is_clear r5 + check_64bit_result 0, 1781818164, r59, r58 + +; Test case 30 +; Testing when cc condition is not met +; reg0 <- reg0, reg2 (V is already set) +; It is expected that V is remanins set + prep_test_case + set_N_set_V ; (Z,N,C,V)=(0,1,0,1) + mov r0, 0xc0de ; must remain ... + mov r1, 0x1337 ; ... (0x1337,0xc0de) + mov r2, 0xf00d ; don't care ... + mov r3, 0xbad ; as long as not (0x0,0x1) + mov r4, r58 ; record accl + mov r5, r59 ; record acch + mpyd.p.f r0, r0, r2 ; execute only if positive (N==0) + lr r2, [status32] ; take a snapshot of statu32 as is + check_V_is_set r2 + cmp r1, 0x1337 + bne @fail + cmp r0, 0xc0de + bne @fail + check_64bit_result r5, r4, r59, r58 + +; Test case 31 +; Raise an Illegal Instruction exception if an odd register as dest. + prep_test_case + set_except_params @test_31_exception, @test_31_end +test_31_exception: + mpydu r1, r4, r0 + b @fail +test_31_end: + ; Fall through + +; Test case 32 +; Raise an Illegal Instruction exception if an odd register as dest. +; The exception should be made even if the CC indicates no execution. + prep_test_case + set_except_params @test_32_exception, @test_32_end + add.f 0,0,1 ; (Z,N,C,V)=(0,0,0,0) +test_32_exception: + mpydu.v r5, r5, r4 + b @fail +test_32_end: + ; Fall through + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Reporting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +valhalla: + print "[PASS]" + b @1f + +; If a test fails, it jumps here. Although, for the sake of uniformity, +; the printed output does not say much about which test case failed, +; one can uncomment the print_number line below or set a breakpoint +; here to check the R0 register for the test case number. +fail: + ld r0, [test_nr] + print_number r0 + print "[FAIL]" +1: + print " mpyd: mpyd mpydu\n" + end diff --git a/tests/tcg/arc/check_mpyw.S b/tests/tcg/arc/check_mpyw.S new file mode 100644 index 0000000000..091ee98975 --- /dev/null +++ b/tests/tcg/arc/check_mpyw.S @@ -0,0 +1,41 @@ +.include "macros.inc" + + +.macro mul_test val1, val2, res, test_num + mov r0, \val1 + mov r1, \val2 + mpyw r2, r0, r1 + assert_eq \res, r2, \test_num +.endm + + +.macro mul_flags_test val1, val2, res, z=0, n=0, v=0, test_num + mov r0, \val1 + mov r1, \val2 + mpyw.f r2, r0, r1 + assert_eq \res, r2, \test_num + assert_flag REG_STAT_Z, \z, \test_num + assert_flag REG_STAT_N, \n, \test_num + assert_flag REG_STAT_C, 0, \test_num + assert_flag REG_STAT_V, \v, \test_num +.endm + +start + +; 21 * 2 = 42 +mul_test 21, 2, 42, test_num=1 + +; make sure only the lower 16 bits are taken into account +; 0x11220005 * 0x00120020 --> 0x0005 * 0x0020 = 160 +mul_test 0x11220005, 0x00120020, 160, test_num=2 + +; testing sign extension and the signed result +; 0xFFFFFFFF * 0x00000007 --> 0xFFFF (-1) * 0x0007 = 0xFFFFFFF9 (-7) +mul_test 0xFFFFFFFF, 0x00000007, 0xFFFFFFF9, test_num=3 + +; testing flags +mul_flags_test 1337 , 0 , res=0 , z=1, test_num=4 +mul_flags_test 0x7FFF, 0x7FFF, res=0x3FFF0001, v=0, test_num=5 +mul_flags_test 0xFFFF, 0x0C , res=0xFFFFFFF4, n=1, test_num=6 + +end diff --git a/tests/tcg/arc/check_norm.S b/tests/tcg/arc/check_norm.S new file mode 100644 index 0000000000..4e55b71589 --- /dev/null +++ b/tests/tcg/arc/check_norm.S @@ -0,0 +1,40 @@ +.include "macros.inc" + + start + + test_name NORM_1 + norm r2, 0x0 + check_r2 0x1f + + test_name NORM_2 + norm r2, 0x1 + check_r2 0x1e + + test_name NORM_3 + norm r2, 0x1fffffff + check_r2 0x02 + + test_name NORM_4 + norm r2, 0x3fffffff + check_r2 0x01 + + test_name NORM_5 + norm r2, 0x7fffffff + check_r2 0x00 + + test_name NORM_6 + norm r2, 0x80000000 + check_r2 0x00 + + test_name NORM_8 + norm r2, 0xc0000000 + check_r2 0x01 + + test_name NORM_9 + norm r2, 0xe0000000 + check_r2 0x02 + + test_name NORM_10 + norm r2, 0xffffffff + check_r2 0x1f + end diff --git a/tests/tcg/arc/check_orx.S b/tests/tcg/arc/check_orx.S new file mode 100644 index 0000000000..c7a96b4edb --- /dev/null +++ b/tests/tcg/arc/check_orx.S @@ -0,0 +1,34 @@ +#define ARCTEST_ARC32 + +#***************************************************************************** +# or.S +#----------------------------------------------------------------------------- +# +# Test or instruction. +# + +#include "test_macros.h" + +ARCTEST_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + TEST_IMM_OP( 2, or, 0xffffffffffffff0f, 0xffffffffff00ff00, 0xf0f ); + TEST_IMM_OP( 3, or, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 ); + TEST_IMM_OP( 4, or, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f ); + TEST_IMM_OP( 5, or, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); + TEST_RR_3OP( 6, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_3OP( 7, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_3OP( 8, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_3OP( 9, or, 0xf0fff0ff, 0xf00ff00f, 0xf0f0f0f0 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 10, or, 0xff00fff0, 0xff00ff00, 0x0f0 ); + TEST_RR_SRC1_EQ_DEST( 11, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 12, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_EQ_DEST( 13, or, 0xff00ff00, 0xff00ff00 ); +ARCTEST_END diff --git a/tests/tcg/arc/check_prefetch.S b/tests/tcg/arc/check_prefetch.S new file mode 100644 index 0000000000..3eb9900de0 --- /dev/null +++ b/tests/tcg/arc/check_prefetch.S @@ -0,0 +1,37 @@ +#***************************************************************************** +# prefetch +#----------------------------------------------------------------------------- +# +# This test verifies that prefetch works as expected +# + +#define ARCTEST_ARC32 +#include "test_macros.h" + +ARCTEST_BEGIN + + # testing the decoding + TEST_CASE( 2, r0, 0x00000000, "prefetch:2", prefetch [0x12]` mov r0, 0x0) + TEST_CASE( 3, r0, 0x00000000, "prefetch:3", prefetchw [0x12]` mov r0, 0x0) + TEST_CASE( 4, r0, 0x00000000, "prefetch:4", prefetchw [r1, r2]` mov r0, 0x0) + TEST_CASE( 5, r0, 0x00000000, "prefetch:5", prefetchw [0x12, 0x1]` mov r0, 0x0) + TEST_CASE( 6, r0, 0x00000000, "prefetch:6", prefetch [r1, r2]` mov r0, 0x0) + TEST_CASE( 7, r0, 0x00000000, "prefetch:7", prefetch [0x12, 0x1]` mov r0, 0x0) + + mov r13, @tdat + TEST_CASE( 8, r0, 0x00000004, "prefetch:8", prefetch [r13]` ld r0,[r13]) + TEST_CASE( 9, r0, 0x40000000, "prefetch:9", prefetch.aw [r13,4]` ld r0,[r13]) + TEST_CASE(10, r0, 0x40400000, "prefetch:10", prefetch.ab [r13,4]` ld r0,[r13]) + +ARCTEST_END +# TEST_DATA + +tdat: +.word 0x00000004 +.word 0x40000000 +.word 0x40400000 +.word 0xc0800000 +.word 0xdeadbeef +.word 0xcafebabe +.word 0xabad1dea +.word 0x1337d00d diff --git a/tests/tcg/arc/check_rolx.S b/tests/tcg/arc/check_rolx.S new file mode 100644 index 0000000000..4f2d939f69 --- /dev/null +++ b/tests/tcg/arc/check_rolx.S @@ -0,0 +1,47 @@ +#define ARCTEST_ARC32 + +#***************************************************************************** +# check_rolx.S +#----------------------------------------------------------------------------- +# +# Test or instruction. +# +# .-------------.----------.--------------. +# | instruction | check CC | update flags | +# |-------------+----------+--------------| +# | rol | no | Z, N, C | +# | rol8 | no | Z, N | +# `-------------^----------^--------------' + +#include "test_macros.h" + +ARCTEST_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + TEST_RR_2OP(2, rol , 0xbd5b7ddf, 0xdeadbeef); + TEST_RR_2OP(3, rol8, 0x00000001, 0x01000000); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + TEST_RR_2OP_SRC1_EQ_DEST(4, rol, 0x94001009, 0xca000804); + + #------------------------------------------------------------- + # Flag tests + #------------------------------------------------------------- + TEST_1OP_CARRY ( 5, rol , 0, 0x40000000); + TEST_1OP_CARRY ( 6, rol , 1, 0x80000000); + TEST_1OP_ZERO ( 8, rol , 0, 0x00001000); + TEST_1OP_ZERO ( 9, rol , 1, 0x00000000); + TEST_1OP_NEGATIVE(10, rol , 0, 0x80000000); + TEST_1OP_NEGATIVE(11, rol , 1, 0x40000000); + #rol8 does not update carry + TEST_1OP_CARRY (12, rol8, 0, 0x000000ff); + TEST_1OP_ZERO (13, rol8, 0, 0x00001000); + TEST_1OP_ZERO (14, rol8, 1, 0x00000000); + TEST_1OP_NEGATIVE(15, rol8, 0, 0x00000040); + TEST_1OP_NEGATIVE(16, rol8, 1, 0x00800000); + +ARCTEST_END diff --git a/tests/tcg/arc/check_rorx.S b/tests/tcg/arc/check_rorx.S new file mode 100644 index 0000000000..2634e4e4a5 --- /dev/null +++ b/tests/tcg/arc/check_rorx.S @@ -0,0 +1,64 @@ +#define ARCTEST_ARC32 + +#***************************************************************************** +# check_rorx.S +#----------------------------------------------------------------------------- +# +# Test or instruction. +# +# .--------------.----------.--------------. +# | instruction | check CC | update flags | +# |--------------+----------+--------------| +# | ror | no | Z, N, C | +# | ror multiple | yes | Z, N, C | +# | ror8 | no | Z, N | +# `--------------^----------^--------------' + +#include "test_macros.h" + +ARCTEST_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + TEST_RR_3OP( 2, ror , 0xdeadbeef, 0xdeadbeef, 0x00000000); + TEST_RR_3OP( 3, ror , 0x00000001, 0x00000001, 0x00000000); + TEST_RR_3OP( 4, ror , 0x80000000, 0x80000000, 0x00000000); + TEST_RR_3OP( 5, ror , 0xbd5b7ddf, 0xdeadbeef, 0x0000001f); + TEST_RR_3OP( 6, ror , 0x00000002, 0x00000001, 0x0000001f); + TEST_RR_3OP( 7, ror , 0x00000001, 0x80000000, 0x0000001f); + TEST_RR_2OP( 8, ror , 0x80000000, 0x00000001); + TEST_RR_2OP( 9, ror , 0xdeadbeef, 0xbd5b7ddf); + TEST_RR_2OP(10, ror8, 0x01000000, 0x00000001); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + TEST_RR_SRC1_EQ_DEST (11, ror, 0xca000804, 0x000804ca, 0xfff80008); + TEST_RR_2OP_SRC1_EQ_DEST(12, ror, 0x80040265, 0x000804cb); + + #------------------------------------------------------------- + # Flag tests + #------------------------------------------------------------- + TEST_2OP_CARRY (13, ror , 0, 0x00000001, 0x02); + TEST_2OP_CARRY (14, ror , 1, 0x00000001, 0x01); + TEST_2OP_ZERO (15, ror , 0, 0x00000100, 0xbf); + TEST_2OP_ZERO (16, ror , 1, 0x00000000, 0xbf); + TEST_2OP_NEGATIVE(17, ror , 0, 0x00000001, 0x02); + TEST_2OP_NEGATIVE(18, ror , 1, 0x80000000, 0x00); + TEST_2OP_CARRY (19, ror , 1, 0x000000ff, 0x08); + TEST_1OP_CARRY (20, ror , 0, 0x00000002); + TEST_1OP_CARRY (21, ror , 1, 0x00000001); + TEST_1OP_ZERO (22, ror , 0, 0x00000100); + TEST_1OP_ZERO (23, ror , 1, 0x00000000); + TEST_1OP_NEGATIVE(24, ror , 0, 0x80000000); + TEST_1OP_NEGATIVE(25, ror , 1, 0x00000001); + TEST_1OP_CARRY (26, ror , 1, 0x80000001); + #ror8 does not update carry + TEST_1OP_CARRY (27, ror8, 0, 0x000000ff); + TEST_1OP_ZERO (28, ror8, 0, 0x00001000); + TEST_1OP_ZERO (29, ror8, 1, 0x00000000); + TEST_1OP_NEGATIVE(30, ror8, 0, 0x00000040); + TEST_1OP_NEGATIVE(31, ror8, 1, 0x00000080); + +ARCTEST_END diff --git a/tests/tcg/arc/check_rtc.S b/tests/tcg/arc/check_rtc.S new file mode 100644 index 0000000000..cb8a6ead9f --- /dev/null +++ b/tests/tcg/arc/check_rtc.S @@ -0,0 +1,29 @@ + .include "macros.inc" + +;;; Simple RTC test, read RTC value if it exists, spend some time, and +;;; re-read it. Fail if the value is the same..data +test_nr: + .word 0x0 + + start + test_name RTC + lr r0,[timer_build] + and.f 0,r0,0x400 + beq @.lfail + sr 1,[0x103] + lr r2,[0x104] +.loop: + sub.f r0,r0,1 + bnz @.loop + lr r0,[0x104] + breq r0,r2,@.lfail + print "[PASS] " + b @1f + +.lfail: + ld r0, [test_nr] + ;print_number r0 + print "[FAIL] " +1: + printl r30 + end diff --git a/tests/tcg/arc/check_rtie_user.S b/tests/tcg/arc/check_rtie_user.S new file mode 100644 index 0000000000..b29618a6ac --- /dev/null +++ b/tests/tcg/arc/check_rtie_user.S @@ -0,0 +1,30 @@ + .include "macros.inc" + + start + enter_user_mode @user_mode + +user_mode: + nop + ; must cause privilege violation exception +faulty: + rtie + +good: + print "You're on a righteous path.\n" + end + + .align 4 + .global EV_PrivilegeV + .type EV_PrivilegeV, @function +EV_PrivilegeV: + lr r0, [eret] + brne r0, @faulty, @sucks + lr r0, [efa] + brne r0, @faulty, @sucks + mov r0, @good + sr r0, [eret] + rtie + +sucks: + print "Life sucks. Get over it!\n" + end diff --git a/tests/tcg/arc/check_stld.S b/tests/tcg/arc/check_stld.S new file mode 100644 index 0000000000..3817678b98 --- /dev/null +++ b/tests/tcg/arc/check_stld.S @@ -0,0 +1,10 @@ +.include "macros.inc" + + start + + test_name STLD_1 + st -32,[0x10000] + ld r2,[0x10000] + check_r2 -32 + + end diff --git a/tests/tcg/arc/check_subf.S b/tests/tcg/arc/check_subf.S new file mode 100644 index 0000000000..10b98e803b --- /dev/null +++ b/tests/tcg/arc/check_subf.S @@ -0,0 +1,67 @@ +.include "macros.inc" + +.macro validate res, actual, z, n, c, v, test_num + assert_eq \res, \actual, \test_num + assert_flag REG_STAT_Z, \z, \test_num + assert_flag REG_STAT_N, \n, \test_num + assert_flag REG_STAT_C, \c, \test_num + assert_flag REG_STAT_V, \v, \test_num +.endm + +.macro sub0_flags_test val1, val2, res, z=0, n=0, c=0, v=0, test_num=1 + mov r0, \val1 + mov r1, \val2 + sub.f r2, r0, r1 + validate \res, r2, \z, \n, \c, \v, \test_num +.endm + +.macro sub1_flags_test val1, val2, res, z=0, n=0, c=0, v=0, test_num=1 + mov r0, \val1 + mov r1, \val2 + sub1.f r2, r0, r1 + validate \res, r2, \z, \n, \c, \v, \test_num +.endm + +.macro sub2_flags_test val1, val2, res, z=0, n=0, c=0, v=0, test_num=1 + mov r0, \val1 + mov r1, \val2 + sub2.f r2, r0, r1 + validate \res, r2, \z, \n, \c, \v, \test_num +.endm + +.macro sub3_flags_test val1, val2, res, z=0, n=0, c=0, v=0, test_num=1 + mov r0, \val1 + mov r1, \val2 + sub3.f r2, r0, r1 + validate \res, r2, \z, \n, \c, \v, \test_num +.endm + + +start + +sub0_flags_test 0xA0000000, 0xB0000000, 0xF0000000, z=0, n=1, c=1, v=0, test_num=0x01 +sub1_flags_test 0xA0000000, 0x58000000, 0xF0000000, z=0, n=1, c=1, v=0, test_num=0x02 +sub2_flags_test 0xA0000000, 0x2C000000, 0xF0000000, z=0, n=1, c=1, v=0, test_num=0x03 +sub3_flags_test 0xA0000000, 0x16000000, 0xF0000000, z=0, n=1, c=1, v=0, test_num=0x04 + +sub0_flags_test 0xFFFFFF80, 0xF0000000, 0x0FFFFF80, z=0, n=0, c=0, v=0, test_num=0x05 +sub1_flags_test 0xFFFFFF80, 0x78000000, 0x0FFFFF80, z=0, n=0, c=0, v=0, test_num=0x06 +sub2_flags_test 0xFFFFFF80, 0x3C000000, 0x0FFFFF80, z=0, n=0, c=0, v=0, test_num=0x07 +sub3_flags_test 0xFFFFFF80, 0x1E000000, 0x0FFFFF80, z=0, n=0, c=0, v=0, test_num=0x08 + +sub0_flags_test 0x80000000, 0x80000000, 0x00000000, z=1, n=0, c=0, v=0, test_num=0x09 +sub1_flags_test 0x80000000, 0x40000000, 0x00000000, z=1, n=0, c=0, v=0, test_num=0x10 +sub2_flags_test 0x80000000, 0x20000000, 0x00000000, z=1, n=0, c=0, v=0, test_num=0x11 +sub3_flags_test 0x80000000, 0x10000000, 0x00000000, z=1, n=0, c=0, v=0, test_num=0x12 + +sub0_flags_test 0x80000000, 0xC0000000, 0xC0000000, z=0, n=1, c=1, v=0, test_num=0x13 +sub1_flags_test 0x80000000, 0x60000000, 0xC0000000, z=0, n=1, c=1, v=0, test_num=0x14 +sub2_flags_test 0x80000000, 0x30000000, 0xC0000000, z=0, n=1, c=1, v=0, test_num=0x15 +sub3_flags_test 0x80000000, 0x18000000, 0xC0000000, z=0, n=1, c=1, v=0, test_num=0x16 + +sub0_flags_test 0x80000000, 0x00000008, 0x7FFFFFF8, z=0, n=0, c=0, v=1, test_num=0x17 +sub1_flags_test 0x80000000, 0x00000004, 0x7FFFFFF8, z=0, n=0, c=0, v=1, test_num=0x18 +sub2_flags_test 0x80000000, 0x00000002, 0x7FFFFFF8, z=0, n=0, c=0, v=1, test_num=0x19 +sub3_flags_test 0x80000000, 0x00000001, 0x7FFFFFF8, z=0, n=0, c=0, v=1, test_num=0x20 + +end diff --git a/tests/tcg/arc/check_subx.S b/tests/tcg/arc/check_subx.S new file mode 100644 index 0000000000..7e4c4b1009 --- /dev/null +++ b/tests/tcg/arc/check_subx.S @@ -0,0 +1,43 @@ +#***************************************************************************** +# sub.S +#----------------------------------------------------------------------------- +# +# Test sub instruction. +# + +#define ARCTEST_ARC32 +#include "test_macros.h" + +ARCTEST_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_3OP( 2, sub, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 ); + TEST_RR_3OP( 3, sub, 0x0000000000000000, 0x0000000000000001, 0x0000000000000001 ); + TEST_RR_3OP( 4, sub, 0xfffffffffffffffc, 0x0000000000000003, 0x0000000000000007 ); + + TEST_RR_3OP( 5, sub, 0x0000000000008000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_3OP( 6, sub, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000000000 ); + TEST_RR_3OP( 7, sub, 0xffffffff80008000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_3OP( 8, sub, 0xffffffffffff8001, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_3OP( 9, sub, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_3OP( 10, sub, 0x000000007fff8000, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_3OP( 11, sub, 0xffffffff7fff8001, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_3OP( 12, sub, 0x0000000080007fff, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_3OP( 13, sub, 0x0000000000000001, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_3OP( 14, sub, 0xfffffffffffffffe, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_3OP( 15, sub, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 16, sub, 2, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 17, sub, 3, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 18, sub, 0, 13 ); +ARCTEST_END diff --git a/tests/tcg/arc/check_swi.S b/tests/tcg/arc/check_swi.S new file mode 100644 index 0000000000..6786807acd --- /dev/null +++ b/tests/tcg/arc/check_swi.S @@ -0,0 +1,115 @@ + .include "macros.inc" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; exception facilitators + .align 4 +ecr_ref : .word 0x0 +efa_ref : .word 0x0 +eret_ref : .word 0x0 +cont_addr : .word 0x0 +test_number: .word 0x0 + +; macro: set_excep_params +; regs used: r11 +; +; this macro writes the provided parameters to a temporary place holder +; later it will be used by SWI exception routine as a reference +.macro set_excep_params ecr, efa, eret, continue, test_num + mov r11, \ecr + st r11, [ecr_ref] + mov r11, \efa + st r11, [efa_ref] + mov r11, \eret + st r11, [eret_ref] + mov r11, \continue + st r11, [cont_addr] + mov r11, \test_num + st r11, [test_number] +.endm + +; exception: software interrupt +; regs used: r11, r12 +; +; this is a parameterized SWI exception that will check the followings: +; ecr == ecr_ref +; efa == efa_ref +; eret == eret_ref +; if everything passes, it will jump to 'cont_addr' parameter. +; the parameters must be set beforehand using 'set_except_params' macro. +; last but not least, this requires ivt.S file to be compiled and linked. + .align 4 + .global EV_SWI + .type EV_SWI, @function +EV_SWI: + ld r11, [ecr_ref] + lr r12, [ecr] + brne r12, r11, @exc_fail + ld r11, [eret_ref] + lr r12, [eret] + brne r12, r11, @exc_fail + ld r11, [efa_ref] + lr r12, [efa] + brne r12, r11, @exc_fail + ; going back to the given address + ld r11, [cont_addr] + sr r11, [eret] + rtie +exc_fail: + ld r11, [test_number] + print "[FAIL] " + print_number r11 + print ": exception is not sane!\n" + end + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; let the test code begin + start + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; check swi_s with no argument +test01: + set_excep_params ecr = SOFTWARE_INTERRUPT, \ + efa = @test01_swis_addr , \ + eret = @test01_swis_addr , \ + continue = @test02 , \ + test_num = 0x01 + +test01_swis_addr: + swi_s + + assert_eq 0, 1, 1 ; exception must have been raised + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; check swi_s with a u6 immediate +test02: + .equ INTERRUPT_NUM , 42 + .equ TEST02_EXCP_REF, SOFTWARE_INTERRUPT | INTERRUPT_NUM + set_excep_params ecr = TEST02_EXCP_REF,\ + efa = @test02_swis_addr , \ + eret = @test02_swis_addr , \ + continue = @test03 , \ + test_num = 0x02 + +test02_swis_addr: + swi_s INTERRUPT_NUM + + assert_eq 0, 1, 2 ; exception must have been raised + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; check swi +test03: + set_excep_params ecr = SOFTWARE_INTERRUPT, \ + efa = @test03_swi_addr , \ + eret = @test03_swi_addr , \ + continue = @finish , \ + test_num = 0x01 + +test03_swi_addr: + swi + + assert_eq 0, 1, 3 ; exception must have been raised + + +finish: + print "[PASS] Software Interrupt\n" + end diff --git a/tests/tcg/arc/check_swirq.S b/tests/tcg/arc/check_swirq.S new file mode 100644 index 0000000000..f3fb69d1ed --- /dev/null +++ b/tests/tcg/arc/check_swirq.S @@ -0,0 +1,27 @@ + .include "macros.inc" + + start + ;; print "Start\n" + mov sp, 0x1000 + seti + sr 18, [aux_irq_hint] + print "[PASS] SW-IRQ:End\n" + end + + /* The delay between writing to the AUX_IRQ_HINT register and + the interrupt being taken is implementation specific. Hence, + we need to save/restore any clobber register by ISR. */ + .align 4 + .global IRQ_18 + .type IRQ_18, @function +IRQ_18: + clri + push r11 + push r12 + sr 0, [aux_irq_hint] + print "[PASS] SW-IRQ:IRQ\n" + pop r12 + pop r11 + rtie + print "[FAIL] SW-IRQ\n" + end diff --git a/tests/tcg/arc/check_swirq1.S b/tests/tcg/arc/check_swirq1.S new file mode 100644 index 0000000000..ca8e301dd3 --- /dev/null +++ b/tests/tcg/arc/check_swirq1.S @@ -0,0 +1,31 @@ + .include "macros.inc" + + start + ;; print "Check normal IRQ functioning.\n" + ;; Set the stack somewhere + mov sp, 0x1000 + ;; Use IRQ18 for the test, change to a level 1, irq so we can + ;; avoid firq. + sr 18,[REG_IRQ_SELECT] + sr 1,[irq_priority] + set_interrupt_prio_level 1 + sr 16,[aux_irq_ctrl] + ;; Enable the interrupt system, and trigger the IRQ 18. + seti + sr 18, [aux_irq_hint] + print "[PASS] IRQ:End\n" + end + + /* The delay between writing to the AUX_IRQ_HINT register and + the interrupt being taken is implementation specific. Hence, + we need to save/restore any clobber register by ISR. */ + .align 4 + .global IRQ_18 + .type IRQ_18, @function +IRQ_18: + clri + sr 0, [aux_irq_hint] + print "[PASS] IRQ:IRQ\n" + rtie + print "[FAIL] IRQ\n" + end diff --git a/tests/tcg/arc/check_swirq3.S b/tests/tcg/arc/check_swirq3.S new file mode 100644 index 0000000000..2aa5bb8d82 --- /dev/null +++ b/tests/tcg/arc/check_swirq3.S @@ -0,0 +1,49 @@ + .include "macros.inc" + + start +;;; print "Check if an IRQ gets re-trigger while in ISR:" + ;; Set the stack somewhere + mov sp, 0x1000 + seti + mov r0,0 + ;; Use IRQ18 for the test. + sr 18, [AUX_IRQ_HINT] + ;; wait (sleep doesn't work as expected because all the irq + ;; are triggered BEFORE sleep is even fetch/executed. +.llocal00: + breq r0, 0, @.llocal00 + brlt r0, 2, @.failMe + print "[PASS] SW-IRQ3\n" + end +.failMe: + print "[PASS] SW-IRQ3\n" + end + + /* The delay between writing to the AUX_IRQ_HINT register and + the interrupt being taken is implementation specific. Hence, + we need to save/restore any clobber register by ISR. */ + .align 4 + .global IRQ_18 + .type IRQ_18, @function +IRQ_18: +#define AUX_IRQ_SELECT 0x40b +#define AUX_IRQ_ENABLE 0x40c + clri + add r0,r0,1 + mov r1, AUX_IRQ_SELECT + mov r2, AUX_IRQ_ENABLE + ;; clean the IRQ + sr 18, [r1] + sr 0, [r2] + sr 0, [AUX_IRQ_HINT] + brgt r0,1,@.extisr + ;; retrigger the irq + sr 18, [AUX_IRQ_HINT] + sr 18, [r1] + sr 1, [r2] + ;; print " SW-IRQ 0," + rtie +.extisr: + ;; print " SW-IRQ 1," + rtie + end diff --git a/tests/tcg/arc/check_t01.S b/tests/tcg/arc/check_t01.S new file mode 100644 index 0000000000..c6cb9d0052 --- /dev/null +++ b/tests/tcg/arc/check_t01.S @@ -0,0 +1,12 @@ + .include "macros.inc" + + start + test_name LOOP_1 + mov r2, 4 +.L1: + sub_s r2,r2,1 + tst_s r2,r2 + bne @.L1 + check_r2 0x0 + + end diff --git a/tests/tcg/arc/check_t02.S b/tests/tcg/arc/check_t02.S new file mode 100644 index 0000000000..1567bfe1d4 --- /dev/null +++ b/tests/tcg/arc/check_t02.S @@ -0,0 +1,9 @@ + .include "macros.inc" + start + test_name PREDICATE_1 + mov r2,2 + lsr.f r2,r2 + mov.nc r2,1 + mov.cs r2,-1 # Should not execute + check_r2 0x01 + end diff --git a/tests/tcg/arc/check_timer0.S b/tests/tcg/arc/check_timer0.S new file mode 100644 index 0000000000..f2afa83200 --- /dev/null +++ b/tests/tcg/arc/check_timer0.S @@ -0,0 +1,36 @@ + .include "macros.inc" + + start + test_name TIMER0 + sr 0,[count0] + print "......" + lr r2,[count0] + breq r2, 0, @.lfail + print "X" + lr r0,[count0] + breq r0,r2,@.lfail + print "Pass\n" + sr 0x01,[control0] + mov r0, 0xffff + sr r0,[limit0] + sr 0,[count0] + mov r3, 0 + seti +.loop0: + breq r3, 0, @.loop0 + print "The end\n" + end +.lfail: + print "Fail\n" + end + + .align 4 + .global IRQ_Timer0 + .type IRQ_Timer0, @function +IRQ_Timer0: + clri + sr 0x00,[control0] + print "Pass IRQ\n" + mov r3, 1 + rtie + end diff --git a/tests/tcg/arc/check_timer0_loop.S b/tests/tcg/arc/check_timer0_loop.S new file mode 100644 index 0000000000..a1910a02ae --- /dev/null +++ b/tests/tcg/arc/check_timer0_loop.S @@ -0,0 +1,34 @@ + .include "macros.inc" + + start + test_name TIMER0 + ;; enable TIMER0 interrupts + sr 0x01,[control0] + mov r0, 0x1fffff + sr r0,[limit0] + sr 0,[count0] + ;; Now wait for the counter to reach it's limit + mov r0,0 +.loop1: + lr r0,[control0] + bbit0 r0,3,@.loop1 + ;; Now enable PIC interrupts, we expect the pending interrupt + ;; to kick in. + mov r3, 0 + seti +.loop0: + breq r3, 0, @.loop0 + print "The end\n" + end + + .align 4 + .global IRQ_Timer0 + .type IRQ_Timer0, @function +IRQ_Timer0: + clri + ;; reset interrupts + sr 0x00,[control0] + print "Pass IRQ\n" + mov r3, 1 + rtie + end diff --git a/tests/tcg/arc/check_timer0_loop3.S b/tests/tcg/arc/check_timer0_loop3.S new file mode 100644 index 0000000000..c5a1013db4 --- /dev/null +++ b/tests/tcg/arc/check_timer0_loop3.S @@ -0,0 +1,46 @@ + + .include "macros.inc" + +.equ LIMIT, 0x1ff + + start + test_name TIMER0 + ;; enable TIMER0 interrupts + sr 0x01,[control0] + mov r0, LIMIT + sr r0,[limit0] + sr 0,[count0] + ;; Now wait for the counter to reach it's limit + mov r0,0 +.loop1: + lr r0,[count0] + brgt r0,LIMIT,@.loop0 + ;; Now enable PIC interrupts, we expect the pending interrupt + ;; to kick in. + mov r3, 0 + seti +.loop0: + lr r4,[count0] + breq r3, 1, @.pass + brgt r4,LIMIT,@.fail1 + j @.loop0 +.pass: + print "[PASS]" + j @.end +.fail1: + print "[FAIL]" + ;; print_number r4 +.end: + print " TIMER0: Overflow\n" + end + + .align 4 + .global IRQ_Timer0 + .type IRQ_Timer0, @function +IRQ_Timer0: + clri + ;; reset interrupts + sr 0x00,[control0] + mov r3, 1 + rtie + end diff --git a/tests/tcg/arc/check_timer0_retrig.S b/tests/tcg/arc/check_timer0_retrig.S new file mode 100644 index 0000000000..f48e09504a --- /dev/null +++ b/tests/tcg/arc/check_timer0_retrig.S @@ -0,0 +1,29 @@ + .include "macros.inc" + + start + test_name TIMER0_RETRIG + ;; enable TIMER0 interrupts + sr 0x01,[control0] + mov r0, 0x1fffff + sr r0,[limit0] + sr 0,[count0] + ;; Now wait for the counter to reach it's limit + mov r0,0 + seti +.loop0: + brlt r3, 2, @.loop0 + print "[PASS] TIMER0: Re-trigger\n" + end + + .align 4 + .global IRQ_Timer0 + .type IRQ_Timer0, @function +IRQ_Timer0: + clri + ;; reset interrupts & enable IRQ + sr 0x01,[control0] + ;; The timer needs to continue counting, and we expect a new + ;; interrupt soon. + add r3, r3, 1 + rtie + end diff --git a/tests/tcg/arc/check_timer0_sleep.S b/tests/tcg/arc/check_timer0_sleep.S new file mode 100644 index 0000000000..87b58fcc78 --- /dev/null +++ b/tests/tcg/arc/check_timer0_sleep.S @@ -0,0 +1,33 @@ + .include "macros.inc" + + start + + ; enable TIMER0 interrupts + sr 0x01,[control0] + mov r0, 0x5ffff + sr r0,[limit0] + sr 0,[count0] + mov r3, 0 + seti + + sleep + + breq r3, 1, @.passMe + print "[FAIL]" + b @.endtest +.passMe: + print "[PASS]" +.endtest: + print " TIMER0: sleep irq\n" + end + + .align 4 + .global IRQ_Timer0 + .type IRQ_Timer0, @function +IRQ_Timer0: + clri + ; reset interrupts + sr 0x00,[control0] + mov r3, 1 + rtie + end diff --git a/tests/tcg/arc/check_timerX_freq.S b/tests/tcg/arc/check_timerX_freq.S new file mode 100644 index 0000000000..606c3ca82d --- /dev/null +++ b/tests/tcg/arc/check_timerX_freq.S @@ -0,0 +1,87 @@ + .include "macros.inc" + + start + test_name TIMER0vsTIMER1 + ;; enable TIMER0 interrupts + sr 0x01,[control0] + mov r0, 0x1ffff + sr r0,[limit0] + sr 0,[count0] + + ;; enable TIMER1 interrupts + sr 0x01,[control1] + mov r0, 0x3fffe ;Twice slower + sr r0,[limit1] + sr 0,[count1] + mov r4,0 + mov r5,0 + mov sp,0x1000 + seti + mov r3, 0 +.loop: + sleep + add r3,r3,1 + brne r3,10,@.loop + clri + stb.ab 0,[sp,1] + mov r0,r4 +.L02: + rem r2,r0,10 + add r2,r2,0x30 + stb.ab r2,[sp,1] + div.f r0,r0,10 + bne @.L02 +.L03: + ld.aw r2,[sp,-1] + breq r2,0,@.L04 + ;; stb r2,[OUTPUT_DEVICE] + brne r2,0,@.L03 +.L04: + + ;; print ">>>" + stb.ab 0,[sp,1] + mov r0,r5 +.L12: + rem r2,r0,10 + add r2,r2,0x30 + stb.ab r2,[sp,1] + div.f r0,r0,10 + bne @.L12 +.L13: + ld.aw r2,[sp,-1] + breq r2,0,@.L14 + ;; stb r2,[OUTPUT_DEVICE] + brne r2,0,@.L13 +.L14: + breq r5, 0, @.failMe + brgt r4,r5, @.passMe +.failMe: + print "[FAIL] " + b 1f +.passMe: + print "[PASS] " +1: + printl r30 + end + + .align 4 + .global IRQ_Timer0 + .type IRQ_Timer0, @function +IRQ_Timer0: + clri + ;; reset interrupts + sr 0x01,[control0] + sr 0,[count0] + add r4,r4,1 + rtie + + .global IRQ_Timer1 + .type IRQ_Timer1, @function +IRQ_Timer1: + clri + ;; reset interrupts + sr 0x01,[control1] + sr 0,[count1] + add r5,r5,1 + rtie + end diff --git a/tests/tcg/arc/check_vadd.S b/tests/tcg/arc/check_vadd.S new file mode 100644 index 0000000000..39ceac3743 --- /dev/null +++ b/tests/tcg/arc/check_vadd.S @@ -0,0 +1,510 @@ +; check_vadd.S +; +; Tests for vadd: vadd2 vadd2h vadd4h +; If the test fails, check the end of this file for how to troubleshoot. + + .include "macros.inc" + +;;;;;;;;;;;;;;;;;;;;;;;;;;; Test checking routines ;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Test case counter +.data +test_nr: + .word 0x0 + +; Increment the test counter and set (Z,N,C,V) to (0,0,0,0). +.macro prep_test_case + ld r13, [test_nr] + add_s r13, r13, 1 ; increase test case counter + st r13, [test_nr] + add.f 0, 0, 1 ; (Z, N, C, V) = (0, 0, 0, 0) +.endm + +; Checks if (Z,N,C,V) == (0,0,0,0). This relies on "ADD.F 0,0,1" +; instruction in PREP_TEST_CASE macro. From a PREP_TEST_CASE macro +; in a test case, and thence to a VECTOR instruction and finally to +; this macro, none of the aforementioned flags must have been set, +; because VECTOR instructions aren't supposed to do so. +.macro check_flags_remained_zero + lr r11, [status32] + mov r12, REG_STAT_Z + or r12, r12, REG_STAT_N + or r12, r12, REG_STAT_C + or r12, r12, REG_STAT_V + and r11, r11, r12 + cmp r11, 0 + bne @fail +.endm + +; pair(HI, LOW) == pair(REG_HI, REG_LO) +; HI, LO: 32-bit +; REG_HI, REG_LO: 32-bit +.macro check_64bit_double hi, low, reg_hi, reg_lo + check_flags_remained_zero + mov r11, \hi + mov r10, \low + cmp r11, \reg_hi + bne @fail + cmp r10, \reg_lo + bne @fail +.endm + +; REG == (HI, LO) +; HI, LO: 16-bit +; REG: 32-bit +.macro check_32bit_double hi, low, reg + check_flags_remained_zero + mov r11, \hi + and r11, r11, 0xffff + lsl16 r11, r11 + mov r12, \low + and r12, r12, 0xffff + or r11, r11, r12 + cmp r11, \reg + bne @fail +.endm + +; quartet(q3, q2, q1, q0) == pair64(REG_HI, REG_LO) +; Q3, Q2, Q1, Q0: 16-bit +; REG_HI, REG_LO: 32-bit +.macro check_64bit_quadruple q3, q2, q1, q0, reg_hi, reg_lo + check_flags_remained_zero + mov r11, \q3 + and r11, r11, 0xffff + lsl16 r11, r11 + mov r12, \q2 + and r12, r12, 0xffff + or r11, r11, r12 + mov r10, \q1 + and r10, r10, 0xffff + lsl16 r10, r10 + mov r12, \q0 + and r12, r12, 0xffff + or r10, r10, r12 + cmp r11, \reg_hi + bne @fail + cmp r10, \reg_lo + bne @fail +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;; Exception related code ;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; parameters that an IllegalInstruction exception may set. + .align 4 +ecr_ref : .word ILLEGAL_INSTRUCTION +addr_ref : .word 0x0 ; for both eret and efa +cont_addr: .word 0x0 + +; exception: IllegalInstruction +; regs used: r11, r12 +; +; A parameterized IllegalInstruction exception that checks the followings: +; ecr == Illegal instruction +; efa == efa_ref +; eret == eret_ref +; If everything passes, it will jump to 'cont_addr' parameter. The parameters +; must be set beforehand using 'set_except_params' macro. This requires +; ivt.S file to be compiled and linked. + .align 4 + .global instruction_error + .type instruction_error, @function +instruction_error: + ld r11, [ecr_ref] + lr r12, [ecr] + cmp r12, r11 + bne @fail + ld r11, [addr_ref] + lr r12, [eret] + cmp r12, r11 + bne @fail + lr r12, [efa] + cmp r12, r11 + bne @fail + ; Success: continuing + ld r11, [cont_addr] + sr r11, [eret] + rtie + +; macro: set_except_params +; regs used: r11 +; +; This macro writes the provided parameters to a temporary place holder +; that later will be used by exception above to verify as reference. +.macro set_except_params addr, continue + mov r11, \addr + st r11, [addr_ref] + mov r11, \continue + st r11, [cont_addr] +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; VADD2 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Let the tests begin + start + +; Test case 1 +; reg2 <- reg2, reg2 +; (0x00000006,0x00000004)=(0x80000003,0x80000002)+(0x80000003,0x80000002) +; To boot, C and V flags must not be set. + prep_test_case + mov r2, 0x80000002 + mov r3, 0x80000003 + vadd2 r2, r2, r2 + check_64bit_double 0x00000006, 0x00000004, r3, r2 + +; Test case 2 +; reg0 <- reg2, reg0 +; (4,6)=(1,2)+(3,4) + prep_test_case + mov r3, 0x00000001 + mov r2, 0x00000002 + mov r1, 0x00000003 + mov r0, 0x00000004 + vadd2 r0, r2, r0 + check_64bit_double 4, 6, r1, r0 + +; Test case 3 +; reg0 <- limm, reg4 +; (0x00000000,0x00000000)=(0x12345678,0x12345678)+(0xedcba988,0xedcba988) +; Moreover, Z flag mustn't be set. + prep_test_case + mov r0, 0x11111111 ; bogus data + mov r1, 0x22222222 ; bogus data + mov r4, 0xedcba988 ; neg(0x12345678) + mov r5, 0xedcba988 ; neg(0x12345678) + vadd2 r0, 0x12345678, r4 + check_64bit_double 0x00, 0x00, r1, r0 + +; Test case 4 +; reg4 <- reg2, limm +; (-3,-2)=(-2,-1)+(-1,-1) +; The N flag must not be set, irrespective of having negative results. + prep_test_case + mov r2, -1 + mov r3, -2 + vadd2 r4, r2, -1 + check_64bit_double -3, -2, r5, r4 + +; Test case 5 +; reg2 <- limm, limm (both limm should be the same) +; (0x2468acf0,0x2468acf0)=(0x12345678,0x12345678)+(0x12345678,0x12345678) + prep_test_case + vadd2 r2, 0x12345678, 0x12345678 + check_64bit_double 0x2468acf0, 0x2468acf0, r3, r2 + +; Test case 6 +; reg4 <- limm, u6 +; (0x01020343,0x01020343)=(0x01020304,0x01020304)+(0x3f,0x3f) + prep_test_case + vadd2 r4, 0x01020304, 63 + check_64bit_double 0x01020343, 0x01020343, r5, r4 + +; Test case 7 +; reg2 <- reg4, 0(u6) +; (0x08070605,0x04030201)=(0x08070605,0x04030201)+(0,0) + prep_test_case + mov r5, 0x08070605 + mov r4, 0x04030201 + vadd2 r2, r4, 0 + check_64bit_double 0x08070605, 0x04030201, r3, r2 + +; Test case 8 +; reg2 <- reg2, s12 +; (3000002048,2000002048)=(3000004096,2000004096)+(-2048,-2048) + prep_test_case + mov r3, 3000004096 + mov r2, 2000004096 + vadd2 r2, r2, -2048 + check_64bit_double 3000002048, 2000002048, r3, r2 + +; Test case 9 +; 0 <- limm, s12 +; (X,X)=(0xffeeddbb,0xffeeddbb)+(-2048,-2048) + prep_test_case + vadd2 0, 0xffeeddbb, -2048 + +; Test case 10 +; Testing when cc condition is met +; (6,4)=(3,2)+(3,2) + prep_test_case + mov r2, 2 + mov r3, 3 + mov r4, 0x80000000 ; setting... + add.f 0,r4,r4 ; ...C=1 + vadd2.c r2, r2, r2 + add.f 0,0,1 ; so that CHECK_FLAGS_REMAINED_ZERO won't fail. + check_64bit_double 6, 4, r3, r2 + +; Test case 11 +; Testing when cc condition is not met +; (2,0) + prep_test_case + mov r2, 0 + mov r3, 2 + vadd2.z r2, r2, r2 ; Z=0 because of PREP_TEST_CASE + check_64bit_double 2, 0, r3, r2 + +; Test case 12 +; Raise an Illegal Instruction exception if an odd register is used. +; Even if there is no register to save the result to. + prep_test_case + set_except_params @test_12_exception, @test_12_end +test_12_exception: + vadd2 0, r3, r0 + b @fail +test_12_end: + ; Fall through + +; Test case 13 +; Raise an Illegal Instruction exception if an odd register is used. +; The exception should be made even if the CC indicates no execution. + prep_test_case ; (Z,N,C,V)=(0,0,0,0) + set_except_params @test_13_exception, @test_13_end +test_13_exception: + vadd2.z r5, r5, r0 + b @fail +test_13_end: + ; Fall through + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; VADD2H ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Test case 14 +; reg1 <- reg1, reg1 +; (0x0006,0x0004)=(0x8003,0x8002)+(0x8003,0x8002) +; Moreover, the C and V flags are not going to be set. + prep_test_case + mov r1, 0x80038002 + vadd2h r1, r1, r1 + check_32bit_double 0x0006, 0x0004, r1 + +; Test case 15 +; reg1 <- reg1, reg3 +; (4,6)=(1,2)+(3,4) + prep_test_case + mov r3, 0x00010002 + mov r1, 0x00030004 + vadd2h r1, r1, r3 + check_32bit_double 4, 6, r1 + +; Test case 16 +; reg0 <- limm, reg4 +; (0x0000,0x0000)=(0x1234,0x5678)+(0xedcc,0xa988) +; The Z flag must not be set. + prep_test_case + mov r0, 0x11112222 ; bogus data + mov r4, 0xedcca988 ; (neg(0x1234),neg(0x5678)) + vadd2h r0, 0x12345678, r4 + check_32bit_double 0x0000, 0x0000, r0 + +; Test case 17 +; reg5 <- reg3, limm +; (-3,-2)=(-2,-1)+(-1,-1) +; The N flag mustn't be set, irrespective of having negative results. + prep_test_case + mov r3, 0xfffeffff ; (-2,-1) + vadd2h r5, r3, -1 + check_32bit_double -3, -2, r5 + +; Test case 18 +; reg1 <- limm, limm (both limm should be the same) +; (0x2468,0xacf0)=(0x1234,0x5678)+(0x1234,0x5678) + prep_test_case + vadd2h r1, 0x12345678, 0x12345678 + check_32bit_double 0x2468, 0xacf0, r1 + +; Test case 19 +; reg0 <- limm, u6 +; (0x0141,0x0343)=(0x0102,0x0304)+(0x3f,0x3f) + prep_test_case + vadd2h r0, 0x01020304, 63 + check_32bit_double 0x0141, 0x0343, r0 + +; Test case 20 +; reg1 <- reg0, 0(u6) +; (0x0403,0x0201)=(0x0403,0x0201)+(0,0) + prep_test_case + mov r0, 0x04030201 + vadd2h r1, r0, 0 + check_32bit_double 0x0403, 0x0201, r1 + +; Test case 21 +; reg3 <- reg3, s12 + ; (30064,-1)=(30000,-65)+(-125,-125) + prep_test_case + mov r3, 0x7530ffbf ; (30000,-65) + vadd2h r3, r3, -125 + check_32bit_double 29875, -190, r3 + +; Test case 22 +; 0 <- limm, s12 +; (X,X)=(0xffee,0xddbb)+(-2048,-2048) + prep_test_case + vadd2h 0, 0xffeeddbb, -2048 + +; Test case 23 +; Testing when cc condition is met +; (6,4)=(3,2)+(3,2) + prep_test_case + mov r1, 0x00030002 + mov r0, 0x80000000 ; setting... + add.f 0,r0,r0 ; ...V=1 + vadd2h.v r1, r1, r1 + add.f 0,0,1 ; so that CHECK_FLAGS_REMAINED_ZERO won't fail. + check_32bit_double 6, 4, r1 + +; Test case 24 +; Testing when cc condition is not met +; (2,0) + prep_test_case + mov r4, 0x00020000 + vadd2h.n r4, r4, r4 ; N is already 0 because of PRE_TEST_CASE. + check_32bit_double 2, 0, r4 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; VADD4H ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Test case 25 +; reg2 <- reg2, reg2 +; (0x0000,0x0006,0x0000,0x0004)=(0x8000,0x8003,0x8000,0x8002)+ +; (0x8000,0x8003,0x8000,0x8002) +; Moreover, the C and V flags must not be set. + prep_test_case + mov r2, 0x80008002 + mov r3, 0x80008003 + vadd4h r2, r2, r2 + check_64bit_quadruple 0x0000, 0x0006, 0x0000, 0x0004, r3, r2 + +; Test case 26 +; reg0 <- reg2, reg0 +; (6,8,10,12)=(1,2,3,4)+(5,6,7,8) + prep_test_case + mov r3, 0x00010002 + mov r2, 0x00030004 + mov r1, 0x00050006 + mov r0, 0x00070008 + vadd4h r0, r2, r0 + check_64bit_quadruple 6, 8, 10, 12, r1, r0 + +; Test case 27 +; reg0 <- limm, reg4 +; (0x0000,0x0000,0x0000,0x0000)=(0x1234,0x5678,0x1234,0x5678)+ +; (0xedcc,0xa988,0xedcc,0xa988) +; also the Z flag mustn't be set. + prep_test_case + mov r0, 0x11111111 ; bogus data + mov r1, 0x22222222 ; bogus data + mov r4, 0xedcca988 ; (neg(0x1234),neg(0x5678)) + mov r5, 0xedcca988 ; (neg(0x1234),neg(0x5678)) + vadd4h r0, 0x12345678, r4 + check_64bit_quadruple 0x00, 0x00, 0x00, 0x00, r1, r0 + +; Test case 28 +; reg4 <- reg2, limm +; (-5,-4,-3,-2)=(-4,-3,-2,-1)+(-1,-1,-1,-1) +; The N flag must not be set, irrespective of having negative results. + prep_test_case + mov r2, 0xfffeffff ; (-2,-1) + mov r3, 0xfffcfffd ; (-4,-3) + vadd4h r4, r2, -1 + check_64bit_quadruple -5, -4, -3, -2, r5, r4 + +; Test case 29 +; reg2 <- limm, limm (both limm should be the same) +; (0x2468,0xacf0,0x2468,0xacf0)=(0x1234,0x5678,0x1234,0x5678)+ +; (0x1234,0x5678,0x1234,0x5678) + prep_test_case + vadd4h r2, 0x12345678, 0x12345678 + check_64bit_quadruple 0x2468, 0xacf0, 0x2468, 0xacf0, r3, r2 + +; Test case 30 +; reg4 <- limm, u6 +; (0x0141,0x0343,0x0141,0x0343)=(0x0102,0x0304,0x0102,0x0304)+ +; ( 0x3f, 0x3f, 0x3f, 0x3f) + prep_test_case + vadd4h r4, 0x01020304, 63 + check_64bit_quadruple 0x0141, 0x0343, 0x0141, 0x0343, r5, r4 + +; Test case 31 +; reg0 <- reg4, 0(u6) +; (0x1122,0x3344,0x5566,0x7788)=(0x1122,0x3344,0x5566,0x7788)+ +; (0x0000,0x0000,0x0000,0x0000) + prep_test_case + mov r5, 0x11223344 + mov r4, 0x55667788 + vadd4h r0, r4, 0 + check_64bit_quadruple 0x1122, 0x3344, 0x5566, 0x7788, r1, r0 + +; Test case 32 +; reg0 <- reg0, s12 +; (2048,2046,2049,2035)=(1,-1,2,-12)+(2047,2047,2047,2047) + prep_test_case + mov r1, 0x0001ffff ; (1,-1) + mov r0, 0x0002fff4 ; (2,-12) + vadd4h r0, r0, 2047 + check_64bit_quadruple 2048, 2046, 2049, 2035, r1, r0 + +; Test case 33 +; 0 <- limm, s12 +; (X,X,X,X)=(0xffee,0xddbb,0xffee,0xddbb)+(-2048,-2048,-2048,-2048) + prep_test_case + vadd4h 0, 0xffeeddbb, -2048 + +; Test case 34 +; Testing when cc condition is met +; (40,80,120,160)=(20,40,60,80)+(20,40,60,80) + prep_test_case + mov r2, 0x003c0050 ; (60,80) + mov r3, 0x00140028 ; (20,40) + mov r4, 0x80000000 ; setting... + add.f 0,r4,r4 ; ...C=1 + vadd4h.c r2, r2, r2 + add.f 0,0,1 ; so that CHECK_FLAGS_REMAINED_ZERO won't fail. + check_64bit_quadruple 40, 80, 120, 160, r3, r2 + +; Test case 35 +; Testing when cc condition is not met +; (2,0) + prep_test_case + mov r2, 0x00020000 + mov r3, 0x00020000 + vadd4h.z r2, r2, r2 ; Z is already 0 because of PREP_TEST_CASE. + check_64bit_quadruple 2, 0, 2, 0, r3, r2 + +; Test case 36 +; Raise an Illegal Instruction exception if an odd register is used. +; Even if there is no register to save the result to. + prep_test_case + set_except_params @test_36_exception, @test_36_end +test_36_exception: + vadd4h 0, r2, r3 + b @fail +test_36_end: + ; Fall through + +; Test case 37 +; Raise an Illegal Instruction exception if an odd register is used. +; The exception should be made even if the CC indicates no execution. + prep_test_case ; (Z,N,C,V)=(0,0,0,0) + set_except_params @test_37_exception, @test_37_end +test_37_exception: + vadd4h.n r1, r1, r0 + b @fail +test_37_end: + ; Fall through + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Reporting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +valhalla: + print "[PASS]" + b @1f + +; If a test fails, it jumps here. Although, for the sake of uniformity, +; the printed output does not say much about which test case failed, +; one can uncomment the print_number line below or set a breakpoint +; here to check the R0 register for the test case number. +fail: + ld r0, [test_nr] + ;print_number r0 + print "[FAIL]" +1: + print " vadd: vadd2 vadd2h vadd4h\n" + end diff --git a/tests/tcg/arc/check_vsub.S b/tests/tcg/arc/check_vsub.S new file mode 100644 index 0000000000..db25bbdf16 --- /dev/null +++ b/tests/tcg/arc/check_vsub.S @@ -0,0 +1,510 @@ +; check_vsub.S +; +; Tests for vsub: vsub2 vsub2h vsub4h +; If the test fails, check the end of this file for how to troubleshoot. + + .include "macros.inc" + +;;;;;;;;;;;;;;;;;;;;;;;;;;; Test checking routines ;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Test case counter +.data +test_nr: + .word 0x0 + +; Increment the test counter and set (Z,N,C,V) to (0,0,0,0). +.macro prep_test_case + ld r13, [test_nr] + add_s r13, r13, 1 ; increase test case counter + st r13, [test_nr] + add.f 0, 0, 1 ; (Z, N, C, V) = (0, 0, 0, 0) +.endm + +; Checks if (Z,N,C,V) == (0,0,0,0). This relies on "ADD.F 0,0,1" +; instruction in PREP_TEST_CASE macro. From a PREP_TEST_CASE macro +; in a test case, and thence to a VECTOR instruction and finally to +; this macro, none of the aforementioned flags must have been set, +; because VECTOR instructions aren't supposed to do so. +.macro check_flags_remained_zero + lr r11, [status32] + mov r12, REG_STAT_Z + or r12, r12, REG_STAT_N + or r12, r12, REG_STAT_C + or r12, r12, REG_STAT_V + and r11, r11, r12 + cmp r11, 0 + bne @fail +.endm + +; pair(HI, LOW) == pair(REG_HI, REG_LO) +; HI, LO: 32-bit +; REG_HI, REG_LO: 32-bit +.macro check_64bit_double hi, low, reg_hi, reg_lo + check_flags_remained_zero + mov r11, \hi + mov r10, \low + cmp r11, \reg_hi + bne @fail + cmp r10, \reg_lo + bne @fail +.endm + +; REG == (HI, LO) +; HI, LO: 16-bit +; REG: 32-bit +.macro check_32bit_double hi, low, reg + check_flags_remained_zero + mov r11, \hi + and r11, r11, 0xffff + lsl16 r11, r11 + mov r12, \low + and r12, r12, 0xffff + or r11, r11, r12 + cmp r11, \reg + bne @fail +.endm + +; quartet(q3, q2, q1, q0) == pair64(REG_HI, REG_LO) +; Q3, Q2, Q1, Q0: 16-bit +; REG_HI, REG_LO: 32-bit +.macro check_64bit_quadruple q3, q2, q1, q0, reg_hi, reg_lo + check_flags_remained_zero + mov r11, \q3 + and r11, r11, 0xffff + lsl16 r11, r11 + mov r12, \q2 + and r12, r12, 0xffff + or r11, r11, r12 + mov r10, \q1 + and r10, r10, 0xffff + lsl16 r10, r10 + mov r12, \q0 + and r12, r12, 0xffff + or r10, r10, r12 + cmp r11, \reg_hi + bne @fail + cmp r10, \reg_lo + bne @fail +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;; Exception related code ;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; parameters that an IllegalInstruction exception may set. + .align 4 +ecr_ref : .word ILLEGAL_INSTRUCTION +addr_ref : .word 0x0 ; for both eret and efa +cont_addr: .word 0x0 + +; exception: IllegalInstruction +; regs used: r11, r12 +; +; A parameterized IllegalInstruction exception that checks the followings: +; ecr == Illegal instruction +; efa == efa_ref +; eret == eret_ref +; If everything passes, it will jump to 'cont_addr' parameter. The parameters +; must be set beforehand using 'set_except_params' macro. This requires +; ivt.S file to be compiled and linked. + .align 4 + .global instruction_error + .type instruction_error, @function +instruction_error: + ld r11, [ecr_ref] + lr r12, [ecr] + cmp r12, r11 + bne @fail + ld r11, [addr_ref] + lr r12, [eret] + cmp r12, r11 + bne @fail + lr r12, [efa] + cmp r12, r11 + bne @fail + ; Success: continuing + ld r11, [cont_addr] + sr r11, [eret] + rtie + +; macro: set_except_params +; regs used: r11 +; +; This macro writes the provided parameters to a temporary place holder +; that later will be used by exception above to verify as reference. +.macro set_except_params addr, continue + mov r11, \addr + st r11, [addr_ref] + mov r11, \continue + st r11, [cont_addr] +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; VSUB2 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Let the tests begin + start + +; Test case 1 +; reg2 <- reg2, reg2 +; (0x00000000,0x00000000)=(0x80000000,0xffffffff)-(0x80000000,0xffffffff) +; The Z flag must remain 0. + prep_test_case + mov r2, 0xffffffff + mov r3, 0x80000000 + vsub2 r2, r2, r2 + check_64bit_double 0, 0, r3, r2 + +; Test case 2 +; reg0 <- reg2, reg0 +; (0x7fffffff,0x80000000)=(-1,0x7fffffff)-(0x80000000,-1) +; The V and N flags must remain zero. + prep_test_case + mov r3, 0xffffffff + mov r2, 0x7fffffff + mov r1, 0x80000000 + mov r0, 0xffffffff + vsub2 r0, r2, r0 + check_64bit_double 0x7fffffff, 0x80000000, r1, r0 + +; Test case 3 +; reg0 <- limm, reg4 +; (0x90abcdef,0x00000001)=(0x12345678,0x12345678)-(0x81888889,0x12345677) + prep_test_case + mov r0, 0x11111111 ; bogus data + mov r1, 0x22222222 ; bogus data + mov r4, 0x12345677 + mov r5, 0x81888889 + vsub2 r0, 0x12345678, r4 + check_64bit_double 0x90abcdef, 0x01, r1, r0 + +; Test case 4 +; reg4 <- reg2, limm +; (-999999999,-999999998)=(1,2)-(1000000000,1000000000) +; The N flag must not be set, irrespective of having negative results. + prep_test_case + mov r2, 2 + mov r3, 1 + vsub2 r4, r2, 0x3b9aca00 ; 0x3b9aca00=1000000000 + check_64bit_double -999999999, -999999998, r5, r4 + +; Test case 5 +; reg2 <- limm, limm (both limm should be the same) +; (0x00,0x00)=(0x12345678,0x12345678)-(0x12345678,0x12345678) + prep_test_case + vsub2 r2, 0x12345678, 0x12345678 + check_64bit_double 0, 0, r3, r2 + +; Test case 6 +; reg4 <- limm, u6 +; (0x010202c5,0x010202c5)=(0x01020304,0x01020304)-(0x3f,0x3f) + prep_test_case + vsub2 r4, 0x01020304, 63 + check_64bit_double 0x010202c5, 0x010202c5, r5, r4 + +; Test case 7 +; reg2 <- reg4, 0(u6) +; (0x08070605,0x04030201)=(0x08070605,0x04030201)-(0,0) + prep_test_case + mov r5, 0x08070605 + mov r4, 0x04030201 + vsub2 r2, r4, 0 + check_64bit_double 0x08070605, 0x04030201, r3, r2 + +; Test case 8 +; reg0 <- reg0, s12 +; (2048,-200000000)=(0,-2000002048)-(-2048,-2048) + prep_test_case + mov r1, 0 + mov r0, -2000002048 + vsub2 r0, r0, -2048 + check_64bit_double 2048, -2000000000, r1, r0 + +; Test case 9 +; 0 <- limm, s12 +; (X,X)=(0xffeeddbb,0xffeeddbb)-(-2048,-2048) + prep_test_case + vsub2 0, 0xffeeddbb, -2048 + +; Test case 10 +; Testing when cc condition is met +; (0,0)=(3,2)+(3,2) + prep_test_case + mov r2, 2 + mov r3, 3 + mov r4, 0x80000000 ; setting... + add.f 0,r4,r4 ; ...C=1 + vsub2.c r2, r2, r2 + add.f 0,0,1 ; so that CHECK_FLAGS_REMAINED_ZERO won't fail. + check_64bit_double 0, 0, r3, r2 + +; Test case 11 +; Testing when cc condition is not met +; (2,0) + prep_test_case + mov r2, 0 + mov r3, 2 + vsub2.z r2, r2, r2 ; Z=0 because of PREP_TEST_CASE + check_64bit_double 2, 0, r3, r2 + +; Test case 12 +; Raise an Illegal Instruction exception if an odd register is used. +; Even if there is no register to save the result to. + prep_test_case + set_except_params @test_12_exception, @test_12_end +test_12_exception: + vsub2 0, r5, r0 + b @fail +test_12_end: + ; Fall through + +; Test case 13 +; Raise an Illegal Instruction exception if an odd register is used. +; The exception should be made even if the CC indicates no execution. + prep_test_case ; (Z,N,C,V)=(0,0,0,0) + set_except_params @test_13_exception, @test_13_end +test_13_exception: + vsub2.c r1, r1, r0 + b @fail +test_13_end: + ; Fall through + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; VSUB2H ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Test case 14 +; reg1 <- reg1, reg1 +; (0x0000,0x0000)=(0x8000,0xffff)-(0x8000,0xffff) +; To boot, the Z flag must remain unsett. + prep_test_case + mov r1, 0x8000ffff + vsub2h r1, r1, r1 + check_32bit_double 0, 0, r1 + +; Test case 15 +; reg1 <- reg1, reg3 +; (0x7fff,0x8000)=(-1,0x7fff)-(0x8000,-1) +; The V and N flags must remain zero. + prep_test_case + mov r1, 0xffff7fff + mov r3, 0x8000ffff + vsub2h r1, r1, r3 + check_32bit_double 0x7fff, 0x8000, r1 + +; Test case 16 +; reg0 <- limm, reg4 +; (0x4321,0x0001)=(0x1234,0x5678)-(0xcf13,0x5677) + prep_test_case + mov r0, 0x11111111 ; bogus data + mov r4, 0xcf135677 + vsub2h r0, 0x12345678, r4 + check_32bit_double 0x4321, 0x0001, r0 + +; Test case 17 +; reg5 <- reg3, limm +; (-9999,-9998)=(1,2)-(10000,10000) +; The N flag must not be set, irrespective of having negative results. + prep_test_case + mov r3, 0x00010002 ; (1,2) + vsub2h r5, r3, 0x27102710 ; (1,2)-(10000,10000) + check_32bit_double -9999, -9998, r5 + +; Test case 18 +; reg1 <- limm, limm (both limm should be the same) +; (0x00,0x00)=(0x1234,0x5678)-(0x1234,0x5678) + prep_test_case + vsub2h r1, 0x12345678, 0x12345678 + check_32bit_double 0, 0, r1 + +; Test case 19 +; reg0 <- limm, u6 +; (0x00c3,0x02c5)=(0x0102,0x0304)-(0x3f,0x3f) + prep_test_case + vsub2h r0, 0x01020304, 63 + check_32bit_double 0x00c3, 0x02c5, r0 + +; Test case 20 +; reg1 <- reg0, 0(u6) +; (0x0403,0x0201)=(0x0403,0x0201)-(0,0) + prep_test_case + mov r0, 0x04030201 + vsub2h r1, r0, 0 + check_32bit_double 0x0403, 0x0201, r1 + +; Test case 21 +; reg5 <- reg5, s12 +; (66,-20415)=(1,-20480)-(-65,-65) + prep_test_case + mov r5, 0x0001b000 ; (1,-20480) + vsub2h r5, r5, -65 + check_32bit_double 66, -20415, r5 + +; Test case 22 +; 0 <- limm, s12 +; (X,X)=(0xffee,0xddbb)-(-2048,-2048) + prep_test_case + vsub2h 0, 0xffeeddbb, -2048 + +; Test case 23 +; Testing when cc condition is met +; (0,0)=(3,2)+(3,2) + prep_test_case + mov r1, 0x00030002 + mov r0, 0x80000000 ; setting... + add.f 0,r0,r0 ; ...V=1 + vsub2h.v r1, r1, r1 + add.f 0,0,1 ; so that CHECK_FLAGS_REMAINED_ZERO won't fail. + check_32bit_double 0, 0, r1 + +; Test case 24 +; Testing when cc condition is not met +; (2,0) + prep_test_case + mov r4, 0x00020000 + vsub2h.n r4, r4, r4 ; N=0 because of PREP_TEST_CASE + check_32bit_double 2, 0, r4 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; VSUB4H ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Test case 25 +; reg2 <- reg2, reg2 +; (0x0000,0x0000,0x0000,0x0000)=(0x8000,0x7000,0xfffe,0xffff)- +; (0x8000,0x7000,0xfffe,0xffff) +; The Z flag must remain 0. + prep_test_case + mov r2, 0xfffeffff + mov r3, 0x80007000 + vsub4h r2, r2, r2 + check_64bit_quadruple 0, 0, 0, 0, r3, r2 + +; Test case 26 +; reg0 <- reg2, reg0 +; (0x7fff,-2,977,0x8000)=(-1,10,1000,0x7fff)-(0x8000,12,23,-1) +; The V and N flags must remain zero. + prep_test_case + mov r3, 0xffff000a ; (-1 , 10) + mov r2, 0x03e87fff ; (1000 , 0x7fff) + mov r1, 0x8000000c ; (0x8000, 12) + mov r0, 0x0017ffff ; (23 , -1) + vsub4h r0, r2, r0 + check_64bit_quadruple 0x7fff, -2, 977, 0x8000, r1, r0 + +; Test case 27 +; reg0 <- limm, reg4 +; (0x4321,0x8765,0x90ab,0xcdef)=(0x1234,0x5678,0x1234,0x5678)- +; (0xcf13,0xcf13,0x8189,0x8889) + prep_test_case + mov r0, 0x11111111 ; bogus data + mov r1, 0x22222222 ; bogus data + mov r5, 0xcf13cf13 + mov r4, 0x81898889 + vsub4h r0, 0x12345678, r4 + check_64bit_quadruple 0x4321, 0x8765, 0x90ab, 0xcdef, r1, r0 + +; Test case 28 +; reg4 <- reg2, limm +; (-9999,-10,-9653,417)=(1,2,347,429)-(10000,12,10000,12) +; The N flag must not be set, irrespective of having negative results. + prep_test_case + mov r3, 0x00010002 ; (1 , 2) + mov r2, 0x015b01ad ; (347, 429) + vsub4h r4, r2, 0x2710000c ; (0x2710,000c)=(10000,12) + check_64bit_quadruple -9999, -10, -9653, 417, r5, r4 + +; Test case 29 +; reg2 <- limm, limm (both limm should be the same) +; (0x0000,0x0000,0x0000,0x0000)=(0x1234,0x5678,0x1234,0x5678)- +; (0x1234,0x5678,0x1234,0x5678) + prep_test_case + vsub4h r2, 0x12345678, 0x12345678 + check_64bit_quadruple 0, 0, 0, 0, r3, r2 + +; Test case 30 +; reg4 <- limm, u6 +; (0x00c3,0x02c5,0x00c3,0x02c5)=(0x0102,0x0304,0x0102,0x0304)- +; ( 0x3f, 0x3f, 0x3f, 0x3f) + prep_test_case + vsub4h r4, 0x01020304, 63 + check_64bit_quadruple 0x00c3,0x02c5, 0x00c3, 0x02c5, r5, r4 + +; Test case 31 +; reg0 <- reg4, 0(u6) +; (0x1122,0x3344,0x5566,0x7788)=(0x1122,0x3344,0x5566,0x7788)- +; (0x0000,0x0000,0x0000,0x0000) + prep_test_case + mov r5, 0x11223344 + mov r4, 0x55667788 + vsub4h r0, r4, 0 + check_64bit_quadruple 0x1122, 0x3344, 0x5566, 0x7788, r1, r0 + +; Test case 32 +; reg2 <- reg2, s12 +; (-4094,1,-2035,-2049)=(-2047,2048,12,-2)-(2047,2047,2047,2047) + prep_test_case + mov r3, 0xf8010800 + mov r2, 0x000cfffe ; (12, -2) + vsub4h r2, r2, 2047 + check_64bit_quadruple -4094, 1, -2035, -2049, r3, r2 + +; Test case 33 +; 0 <- limm, s12 +; (X,X,X,X)=(0xffee,0xddbb,0xffee,0xddbb)-(-2048,-2048,-2048,-2048) + prep_test_case + vsub4h 0, 0xffeeddbb, -2048 + +; Test case 34 +; Testing when cc condition is met +; (0,0,0,0)=(3,2,1,0)-(3,2,1,0) + prep_test_case + mov r3, 0x00030002 + mov r2, 0x00010000 + mov r4, 0x80000000 ; setting... + add.f 0,r4,r4 ; ...C=1 + vsub4h.c r2, r2, r2 + add.f 0,0,1 ; so that CHECK_FLAGS_REMAINED_ZERO won't fail. + check_64bit_quadruple 0, 0, 0, 0, r3, r2 + +; Test case 35 +; Testing when cc condition is not met +; (2,0,2,0) + prep_test_case + mov r3, 0x00020000 + mov r2, 0x00020000 + vsub4h.z r2, r2, r2 ; Z=0 because of PREP_TEST_CASE + check_64bit_quadruple 2, 0, 2, 0, r3, r2 + +; Test case 36 +; Raise an Illegal Instruction exception if an odd register is used. +; Even if there is no register to save the result to. + prep_test_case + set_except_params @test_36_exception, @test_36_end +test_36_exception: + vsub4h 0, r3, r0 + b @fail +test_36_end: + ; Fall through + +; Test case 37 +; Raise an Illegal Instruction exception if an odd register is used. +; The exception should be made even if the CC indicates no execution. + prep_test_case ; (Z,N,C,V)=(0,0,0,0) + set_except_params @test_37_exception, @test_37_end +test_37_exception: + vsub4h.v r5, r5, r0 + b @fail +test_37_end: + ; Fall through + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Reporting ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +valhalla: + print "[PASS]" + b @1f + +; If a test fails, it jumps here. Although, for the sake of uniformity, +; the printed output does not say much about which test case failed, +; one can uncomment the print_number line below or set a breakpoint +; here to check the R0 register for the test case number. +fail: + ld r0, [test_nr] + ;print_number r0 + print "[FAIL]" +1: + print " vsub: vsub2 vsub2h vsub4h\n" + end diff --git a/tests/tcg/arc/check_xorx.S b/tests/tcg/arc/check_xorx.S new file mode 100644 index 0000000000..b0f5963eac --- /dev/null +++ b/tests/tcg/arc/check_xorx.S @@ -0,0 +1,32 @@ +#***************************************************************************** +# xor.S +#----------------------------------------------------------------------------- +# +# Test xor instruction. +# +#define ARCTEST_ARC32 +#include "test_macros.h" + +ARCTEST_BEGIN + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, xor, 0xffffffffff00f00f, 0x0000000000ff0f00, 0xf0f ); + TEST_IMM_OP( 3, xor, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 ); + TEST_IMM_OP( 4, xor, 0x0000000000ff0ff0, 0x0000000000ff08ff, 0x70f ); + TEST_IMM_OP( 5, xor, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); + TEST_RR_3OP( 6, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_3OP( 7, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_3OP( 8, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_3OP( 9, xor, 0x00ff00ff, 0xf00ff00f, 0xf0f0f0f0 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 10, xor, 0xffffffffff00f00f, 0xffffffffff00f700, 0x70f ); + TEST_RR_SRC1_EQ_DEST( 11, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 12, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_EQ_DEST( 13, xor, 0x00000000, 0xff00ff00 ); +ARCTEST_END diff --git a/tests/tcg/arc/ivt.S b/tests/tcg/arc/ivt.S new file mode 100644 index 0000000000..39af256ed8 --- /dev/null +++ b/tests/tcg/arc/ivt.S @@ -0,0 +1,38 @@ + .include "macros.inc" + + .section .ivt, "a", @progbits +#define IVT_ENTRY(name) \ + .word name `\ + .weak name `\ + .set name, _exit_halt + +; handler's name, number, name, offset in IVT (hex/dec) + IVT_ENTRY(main) ; 0 program entry point 0x00 0 + IVT_ENTRY(memory_error) ; 1 memory_error 0x04 4 + IVT_ENTRY(instruction_error) ; 2 instruction_error 0x08 8 + IVT_ENTRY(EV_MachineCheck) ; 3 EV_MachineCheck 0x0C 12 + IVT_ENTRY(EV_TLBMissI) ; 4 EV_TLBMissI 0x10 16 + IVT_ENTRY(EV_TLBMissD) ; 5 EV_TLBMissD 0x14 20 + IVT_ENTRY(EV_ProtV) ; 6 EV_ProtV 0x18 24 + IVT_ENTRY(EV_PrivilegeV) ; 7 EV_PrivilegeV 0x1C 28 + IVT_ENTRY(EV_SWI) ; 8 EV_SWI 0x20 32 + IVT_ENTRY(EV_Trap) ; 9 EV_Trap 0x24 36 + IVT_ENTRY(EV_Extension) ; 10 EV_Extension 0x28 40 + IVT_ENTRY(EV_DivZero) ; 11 EV_DivZero 0x2C 44 + IVT_ENTRY(EV_DCError) ; 12 EV_DCError 0x30 48 + IVT_ENTRY(EV_Misaligned) ; 13 EV_Misaligned 0x34 52 + IVT_ENTRY(EV_Ex14) ; 14 unused 0x38 56 + IVT_ENTRY(EV_Ex15) ; 15 unused 0x3C 60 + IVT_ENTRY(IRQ_Timer0) ; 16 Timer 0 0x40 64 + IVT_ENTRY(IRQ_Timer1) ; 17 Timer 1 0x44 68 + IVT_ENTRY(IRQ_18) ; 18 0x48 72 + IVT_ENTRY(IRQ_19) ; 19 0x4C 76 + IVT_ENTRY(IRQ_20) ; 20 0x50 80 + + .text + .global _exit_halt + .type _exit_halt, @function + .align 4 +_exit_halt: + print "Fail\n" + end diff --git a/tests/tcg/arc/macros.inc b/tests/tcg/arc/macros.inc new file mode 100644 index 0000000000..37530ecf3e --- /dev/null +++ b/tests/tcg/arc/macros.inc @@ -0,0 +1,261 @@ +.equ MAX_TESTNAME_LEN, 32 +.macro test_name name + .data +tn_\name: + .asciz "\name\n" + .space MAX_TESTNAME_LEN - (. - tn_\name), ' ' + .align 4 + .text + mov r30, @tn_\name +.endm + +.macro check_r2 val + sub.f r0, r2, \val + bne @1000f + print "[PASS] " + b @1001f +1000: + print "[FAIL] " +1001: + printl r30 +.endm + + +.macro start + .text + .global main + .align 4 + main: +.endm + +.macro end +1001: + st 1, [POWER_DEVICE] + b @1001b +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +.equ OUTPUT_DEVICE, 0x90000000 ; output device address in QEMU +.equ POWER_DEVICE, 0xF0000008 ; power management device + +; macro: print +; input: message - the string to be printed +; regs used: r11, r12 +; example: print "hello world\n" +.macro print message + + .data + 2010: + .asciz "\message" + .align 4 + + .text + mov_s r11, @2010b ; the message to be printed + 1010: + ldb.ab r12, [r11, 1] + breq r12, 0, @1011f + stb r12, [OUTPUT_DEVICE] + j @1010b + 1011: +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; macro: printl +; input: label - pointer to the string to be printed +; regs used: r11, r12 +; example: print @l1 +.macro printl reg + + .text + mov r11, \reg ; the message to be printed + 3010: + ldb.ab r12, [r11, 1] + breq r12, 0, @3011f + stb r12, [OUTPUT_DEVICE] + j @3010b + 3011: +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; macro: print_number +; input: number +; regs used: r11, r12, r13, r14 +; example: print_number 0x123 +; print_number 11 +; +; description: +; given a number, prints it to the output as a decimal string. +.macro print_number number + .data + .align 4 +2020: ; place holder for printed number in reverse + .skip 12 + + .text + mov r11, \number + mov r13, @2020b + mov r14, @2020b +1020: + remu r12, r11, 10 + add_s r12, r12, 0x30 + stb.ab r12, [r13, 1] + divu r11, r11, 10 + brne r11, 0, @1020b + +1021: + ldb.aw r12, [r13, -1] + stb r12, [0x90000000] + brne r13, r14, @1021b +.endm + + +; macro: print_number_hex +; input: number +; regs used: r11, r12, r13, r14 +; example: print_number_hex 0x123 +; print_number_hex 11 +; +; description: +; given a number, prints it to the output with "0x" prefix and in +; hexadecimal format. +.macro print_number_hex num + .data + .align 4 +2030: ; number printed in reverse order + .skip 12 + + .text + mov r11, \num + mov r13, @2030b + mov r14, @2030b +1030: + and r12, r11, 0x0F + brgt r12, 9, @1031f + add_s r12, r12, '0' + j @1032f +1031: + add_s r12, r12, 'W' +1032: + stb.ab r12, [r13, 1] + lsr.f r11, r11, 4 + bnz @1030b + + print "0x" +10333: + ldb.aw r12, [r13, -1] + stb r12, [OUTPUT_DEVICE] + brgt r13, r14, @10333b +.endm + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; macro: assert_eq +; input: a, b - two values/registers to be compared +; test_num - optional: printed error number, default is 1. +; regs used: r11, r12 +; example: assert_eq 12, r2 +; assert_eq r1, 8 +; assert_eq r3, r4 +; assert_eq 8 , 9 (although useless for tests) +; +; description: +; compares the two inputs. if they are equal, nothing happens. +; but if not, then it is going to print "Ret:1" and exit. +.macro assert_eq a, b, test_num=1 + mov r11, \a + mov r12, \b + breq r11, r12, @1040f + print "FAIL:" + print_number \test_num + end +1040: +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Auxilary registers +.equ REG_IRQ_SELECT, 0x40B + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Exceptions +.equ ILLEGAL_INSTRUCTION , 0x00020000 +.equ ILLEGAL_INSTRUCTION_SEQUENCE, 0x00020100 +.equ MACHINE_CHECK , 0x00030000 +.equ TLB_MISS_I , 0x00040000 +.equ TLB_MISS_D_READ , 0x00050100 +.equ PRIVILEGE_VIOLATION , 0x00070000 +.equ SOFTWARE_INTERRUPT , 0x00080000 +.equ MISALIGNED_DATA_ACCESS , 0x000D0000 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; macro: set_interrupt_prio_level +; input: prio - number in range 0..7 +; regs used: r11 +; example: set_interrupt_prio_level 1 +; +; description: +; sets the bits 1 to 3 of "status" register to the given priority. +.macro set_interrupt_prio_level prio + lr r11, [status32] + asl r12, \prio + and r12, r12, 0xE + or r11, r11, r12 + sr r11, [status32] +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STATUS register and its masks +.equ REG_STAT, 0x0A ; STATUS32 register +.equ REG_IVT_BASE, 0x25 ; Interrupt vector base +.equ REG_STAT_V, 0x0100 ; mask for Over flow bit +.equ REG_STAT_C, 0x0200 ; mask for Carry bit +.equ REG_STAT_N, 0x0400 ; mask for Negative bit +.equ REG_STAT_Z, 0x0800 ; mask for Zero bit + +; macro: assert_flag +; input: reg_stat_flag - index to get the corresponding flag +; bit - verification value: 0 or 1 +; test_num - optional: printed error number, default +; is 1. valid range is: [0 ... 9] +; regs used: r11, r12 +; example: assert_flag REG_STAT_Z, 1, num=8 +; assert_flag 0x0200 , 0, num=3 +; +; description: +; extracts the corresponding bit at given index by reg_stat_flag. +; if it holds the same value as given 'bit', nothing happens, +; else it will print an error and exit. +.macro assert_flag reg_stat_flag, bit, test_num + lr r11, [REG_STAT] + and r11, r11, \reg_stat_flag + ; if bit=0 then checking if r11 == 0 + ; if bit=1 then checking if r11 == bit_mask + assert_eq r11, \bit*\reg_stat_flag, \test_num +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; macro: enter_user_mode +; input: user_space - where the user code begins +; +; regs used: r11 +; example: enter_user_mode @my_user_space_entry +; +; description: +; this piece of code sets the user flag and jumps to given address +.macro enter_user_mode user_space + lr r11, [status32] + or r11, r11, 0x80 ; set the STATUS32.U + sr r11, [erstatus] + mov r11, \user_space + sr r11, [eret] + rtie +.endm diff --git a/tests/tcg/arc/memory.x b/tests/tcg/arc/memory.x new file mode 100644 index 0000000000..53772484fc --- /dev/null +++ b/tests/tcg/arc/memory.x @@ -0,0 +1,12 @@ +MEMORY +{ + RAM : ORIGIN = 0x00000000, LENGTH = 128M +} + +REGION_ALIAS("startup", RAM) +REGION_ALIAS("text", RAM) +REGION_ALIAS("data", RAM) +REGION_ALIAS("sdata", RAM) + +PROVIDE (__stack_top = (0xFFFF & -4) ); +PROVIDE (__end_heap = (0xFFFF) ); diff --git a/tests/tcg/arc/mmu.inc b/tests/tcg/arc/mmu.inc new file mode 100644 index 0000000000..c20c6e6bdd --- /dev/null +++ b/tests/tcg/arc/mmu.inc @@ -0,0 +1,132 @@ + +; auxilary registers +.equ REG_PD0 , 0x460 ; TLBPD0 +.equ REG_PD1 , 0x461 ; TLBPD1 +.equ REG_TLB_INDX, 0x464 ; TLB index +.equ REG_TLB_CMD , 0x465 ; TLB command +.equ REG_PID , 0x468 ; Process Identity + +; exceptions (ecr values) +.equ PROTV_FETCH_MMU, 0x060008 +.equ PROTV_READ_MMU , 0x060108 +.equ PROTV_WRITE_MMU, 0x060208 +.equ PROTV_RW_MMU , 0x060308 + +; PID register bit masks +.equ REG_PID_TLB_SET, 0x80000000 ; TLB enable bit in PID +.equ REG_PID_TLB_CLR, ~REG_PID_TLB_SET ; TLB disable bit in PID + +; bit masks related to page size +.equ PAGE_INDEX_BITS, 13 ; page size is _assumed_ to be 8 KB +.equ PAGE_SIZE , 1 << PAGE_INDEX_BITS +.equ PAGE_OFFSET_MSK, PAGE_SIZE - 1 +.equ PAGE_NUMBER_MSK, ~PAGE_OFFSET_MSK + +; TLBPD0 bit masks +.equ REG_PD0_GLOBAL, 0x100 ; Global bit +.equ REG_PD0_VALID , 0x200 ; Valid bit + +; TLBPD1 bit masks +.equ REG_PD1_KRNL_E, 0x10 ; kernel execute +.equ REG_PD1_KRNL_W, 0x20 ; kernel write +.equ REG_PD1_KRNL_R, 0x40 ; kernel read + +; TLB commands +.equ TLB_CMD_WRITE , 0x01 ; write +.equ TLB_CMD_READ , 0x02 ; read +.equ TLB_CMD_GET_INDX, 0x03 ; get index +.equ TLB_CMD_PROBE , 0x04 ; probe +.equ TLB_CMD_INSERT , 0x07 ; insert +.equ TLB_CMD_DELETE , 0x08 ; delete + + +.macro extract_page_number address + (address & PAGE_NUMBER_MSK) +.endm + + +; macro: mmu_enable +; regs used: r11 +; +; enable MMU on ARC HS systems +.macro mmu_enable + lr r11, [REG_PID] + or r11, r11, REG_PID_TLB_SET + sr r11, [REG_PID] +.endm + + +; macro: mmu_disable +; regs used: r11 +; +; disable MMU on ARC HS systems +.macro mmu_disable + lr r11, [REG_PID] + and r11, r11, REG_PID_TLB_CLR + sr r11, [REG_PID] +.endm + + +; macro: mmu_tlb_insert +; regs used: r11 +; +; inserts (TLBPD0, TLBPD1) registers as a TLB entry +.macro mmu_tlb_insert PD0, PD1 + mov r11, \PD0 + sr r11, [REG_PD0] + mov r11, \PD1 + sr r11, [REG_PD1] + mov r11, TLB_CMD_INSERT + sr r11, [REG_TLB_CMD] +.endm + + +; macro: mmu_tlb_delete +; regs used: r11 +; +; removes any entry with PD0 as page description +.macro mmu_tlb_delete PD0, PD1 + mov r11, \PD0 + sr r11, [REG_PD0] + mov r11, \PD1 + sr r11, [REG_PD1] + mov r11, TLB_CMD_INSERT + sr r11, [REG_TLB_CMD] +.endm +; vim: set syntax=asm ts=2 sw=2 et: + +;;;;;;;;;;;;;;;;;;;;;;;;;;; Test checking routines ;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Test case counter +.data +mmu_test_nr: + .word 0x0 + +; Increment the test counter +.macro mmu_prep_test_case + ld r13, [mmu_test_nr] + add_s r13, r13, 1 ; increase test case counter + st r13, [mmu_test_nr] + mmu_disable + set_except_handler 0x0 + enable_alignment +.endm + +; Increment the test counter +.macro mmu_prep_test_case_address + st pcl, [mmu_test_nr] +.endm + +; Disable alignment so there will be no Misaligned exception +.macro disable_alignment + lr r11, [status32] + bset r11, r11, STATUS32_AD_BIT + flag r11 +.endm + +; Enable alignment again. +.macro enable_alignment + lr r11, [status32] + bclr r11, r11, STATUS32_AD_BIT + flag r11 +.endm diff --git a/tests/tcg/arc/mpu.inc b/tests/tcg/arc/mpu.inc new file mode 100644 index 0000000000..421cd96846 --- /dev/null +++ b/tests/tcg/arc/mpu.inc @@ -0,0 +1,269 @@ +; MPU related defines and macros + + .equ REG_MPU_EN_EN , 0x40000000 ; enable bit + .equ REG_MPU_EN_KR , 0b100000000 ; kernel read + .equ REG_MPU_EN_KW , 0b010000000 ; kernel write + .equ REG_MPU_EN_KE , 0b001000000 ; kernel execute + .equ REG_MPU_EN_UR , 0b000100000 ; user read + .equ REG_MPU_EN_UW , 0b000010000 ; user write + .equ REG_MPU_EN_UE , 0b000001000 ; user execute + .equ REG_MPU_EN_MSK, REG_MPU_EN_EN | REG_MPU_EN_KR | REG_MPU_EN_KW | REG_MPU_EN_KE | REG_MPU_EN_UR | REG_MPU_EN_UW | REG_MPU_EN_UE + + ; full access for user ===> if a user can access, kernel can too + .equ REG_MPU_EN_FULL_ACCESS, REG_MPU_EN_UR | REG_MPU_EN_UW | REG_MPU_EN_UE + + .equ MPU_SIZE_32B , 0b00100 + .equ MPU_SIZE_64B , 0b00101 + .equ MPU_SIZE_128B, 0b00110 + .equ MPU_SIZE_256B, 0b00111 + .equ MPU_SIZE_512B, 0b01000 + .equ MPU_SIZE_1K , 0b01001 + .equ MPU_SIZE_2K , 0b01010 + .equ MPU_SIZE_4K , 0b01011 + .equ MPU_SIZE_8K , 0b01100 + .equ MPU_SIZE_16K , 0b01101 + .equ MPU_SIZE_32K , 0b01110 + .equ MPU_SIZE_64K , 0b01111 + .equ MPU_SIZE_128K, 0b10000 + .equ MPU_SIZE_256K, 0b10001 + .equ MPU_SIZE_512K, 0b10010 + .equ MPU_SIZE_1M , 0b10011 + .equ MPU_SIZE_2M , 0b10100 + .equ MPU_SIZE_4M , 0b10101 + .equ MPU_SIZE_8M , 0b10110 + .equ MPU_SIZE_16M , 0b10111 + .equ MPU_SIZE_32M , 0b11000 + .equ MPU_SIZE_64M , 0b11001 + .equ MPU_SIZE_128M, 0b11010 + .equ MPU_SIZE_256M, 0b11011 + .equ MPU_SIZE_512M, 0b11100 + .equ MPU_SIZE_1G , 0b11101 + .equ MPU_SIZE_2G , 0b11110 + .equ MPU_SIZE_4G , 0b11111 + + ; least byte is used for region + .equ MPU_ECR_FETCH, 0x060000 + .equ MPU_ECR_READ, 0x060100 + .equ MPU_ECR_WRITE, 0x060200 + .equ MPU_ECR_RW, 0x060300 + + .equ PROTV_FETCH_MPU, 0x060004 + .equ PROTV_READ_MPU, 0x060104 + .equ PROTV_WRITE_MPU, 0x060204 + .equ PROTV_RW_MPU, 0x060304 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Macro: mpu_enable +; Regs used: r11 +; +; Enable MPU on ARC HS systems +; "def_access" determines the _default region_ access +.macro mpu_enable def_access=REG_MPU_EN_FULL_ACCESS + mov r11, \def_access + or r11, r11, REG_MPU_EN_EN + and r11, r11, REG_MPU_EN_MSK + sr r11, [mpuen] +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +.macro mpu_disable + mov r11, 0 + sr r11, [mpuen] +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Macro: mpu_add_base +; Regs used: r11 +; +; Adds the base address to the given MPU base register. +; "reg" is the mpu base register: mpurdb0 ... mpurdb15 +; "addr" is the base address you are interested in, e.g.: 0x4000 +.macro mpu_add_base reg, addr + mov r11, \addr + and r11, r11, 0xffffffe0 ; the last 5 bits must be 0 + or r11, r11, 1 ; set valid flag + sr r11, [\reg] +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Macro: mpu_add_region +; Regs used: r11, r12 +; +; Adds the region permission and size to the given MPU permission register. +; "reg" is the mpu permission register: mpurdp0 ... mpurdp15 +; "access" detemines the access type +; "size" is the region size: 00100b (32 bytes) ... 11111b (4 gigabytes) +.macro mpu_add_region reg, access, size=0b100 + mov r12, \size + and r11, r12, 3 ; get the lower 2 bits + asl r12, r12, 7 ; getting the upper 3 bits in position + and r12, r12, 0xe00 ; keeping only bits[11:9] in place + or r11, r11, r12 ; r11 has the size bits now + or r11, r11, \access + sr r11, [\reg] +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Macro: mpu_reset +; Regs used: r11 +; +; Resets all the regions and disables MPU +.macro mpu_reset + lr r12, [mpu_build] + and r11, r12, 0xff + breq r11, 0, @6666f ; no mpu? then skip! + mpu_disable + lsr r12, r12, 8 + brlt r12, 1, @6666f ; no region at all? then skip! + mov r11, 0 + sr r11, [mpurdb0] + sr r11, [mpurdp0] + brlt r12, 2, @6666f ; only 1 region? then skip! + sr r11, [mpurdb1] + sr r11, [mpurdp1] + brlt r12, 4, @6666f ; only 2 regions? then skip! + sr r11, [mpurdb2] + sr r11, [mpurdp2] + sr r11, [mpurdb3] + sr r11, [mpurdp3] + brlt r12, 8, @6666f ; only 4 regions? then skip! + sr r11, [mpurdb4] + sr r11, [mpurdp4] + sr r11, [mpurdb5] + sr r11, [mpurdp5] + sr r11, [mpurdb6] + sr r11, [mpurdp6] + sr r11, [mpurdb7] + sr r11, [mpurdp7] + brlt r12, 16, @6666f ; only 8 regions? then skip! + sr r11, [mpurdb8] + sr r11, [mpurdp8] + sr r11, [mpurdb9] + sr r11, [mpurdp9] + sr r11, [mpurdb10] + sr r11, [mpurdp10] + sr r11, [mpurdb11] + sr r11, [mpurdp11] + sr r11, [mpurdb12] + sr r11, [mpurdp12] + sr r11, [mpurdb13] + sr r11, [mpurdp13] + sr r11, [mpurdb14] + sr r11, [mpurdp14] + sr r11, [mpurdb15] + sr r11, [mpurdp15] +6666: +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; These are the parameters that the ProtV exception routine uses as reference +; There are tests that want to disable the R(ead) permission for the whole +; memory layout, but they do make an exception for the parameters below. To +; achieve that, they allow reading for a region of 32 bytes (minimum possible +; size for a region) that these parameters reside in. Therefore, we have to +; make sure these are the one and only things in this region by guarding them +; with ".align 32" and nothing else. + .align 32 +mpu_ecr_ref: .word 0x0 +ecr_ref : .word 0x0 +efa_ref : .word 0x0 +eret_ref : .word 0x0 +cont_addr : .word 0x0 + .align 32 + +; Exception: Protection Violation +; Regs used: r11, r12 +; +; This is a parameterized ProtV exception that will check the followings: +; mpuic == mpu_ecr_ref +; ecr == ecr_ref +; efa == efa_ref +; eret == eret_ref +; If everything passes, it will jump to 'cont_addr' parameter. It will clear +; the user bit before the jump, i.e. if an exception is raised in user mode, +; the continuation after exception will be in kernel mode. If the check +; should fail, it jumps to "fail" label which must exist in the test file. +; The parameters must be set beforehand using 'mpu_set_except_params' macro. +; Last but not least, this requires ivt.S file to be compiled and linked. + .align 4 + .global instruction_error + .global EV_PrivilegeV + .global EV_ProtV + .type instruction_error, @function + .type EV_PrivilegeV, @function + .type EV_ProtV, @function +instruction_error: +EV_PrivilegeV: +EV_ProtV: + ld r11, [mpu_ecr_ref] + lr r12, [mpuic] + cmp r12, r11 + bne @fail + ld r11, [ecr_ref] + lr r12, [ecr] + cmp r12, r11 + bne @fail + ld r11, [eret_ref] + lr r12, [eret] + cmp r12, r11 + bne @fail + ld r11, [efa_ref] + lr r12, [efa] + cmp r12, r11 + bne @fail + ; going back to the given address in kernel mode + ld r11, [cont_addr] + sr r11, [eret] + lr r11, [erstatus] + and r11, r11, ~0x80 ; clear user mode bit + sr r11, [erstatus] + rtie + +; Macro: mpu_set_except_params +; Regs used: r11 +; +; This macro writes the provided parameters to a temporary place holder +; that later will be used by ProtV exception above to verify as reference. +.macro mpu_set_except_params mpu_ecr, ecr, efa, eret, continue + mov r11, \mpu_ecr + st r11, [mpu_ecr_ref] + mov r11, \ecr + st r11, [ecr_ref] + mov r11, \efa + st r11, [efa_ref] + mov r11, \eret + st r11, [eret_ref] + mov r11, \continue + st r11, [cont_addr] +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Macro: mpu_verify_data +; Regs used: r11, r12 +; +; Reads the data at the given address and check if it holds a certain value. +; It requires the test source file to have "fail" label. +.macro mpu_verify_data ref, addr + ld r11, [\addr] + mov r12, \ref + cmp r11, r12 + bne @fail +.endm + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Macro: mpu_write_data +; Regs used: r11, r12 +.macro mpu_write_data data, addr + mov r11, \data + st r11, [\addr] +.endm + +; vim: set syntax=asm ts=2 sw=2 et: diff --git a/tests/tcg/arc/tarc.ld b/tests/tcg/arc/tarc.ld new file mode 100644 index 0000000000..8146162d12 --- /dev/null +++ b/tests/tcg/arc/tarc.ld @@ -0,0 +1,15 @@ +ENTRY(main) +SECTIONS +{ + .ivt 0x00 : + { + KEEP (*(.ivt)); + } + . = 0x100; + .text : { *(.text) } + .data : { *(.data) } + .bss : { *(.bss COMMON) } + . = ALIGN(8); + . = . + 0x1000; /* 4kB of stack memory */ + stack_top = .; +} diff --git a/tests/tcg/arc/tarc_mmu.ld b/tests/tcg/arc/tarc_mmu.ld new file mode 100644 index 0000000000..4112c0a927 --- /dev/null +++ b/tests/tcg/arc/tarc_mmu.ld @@ -0,0 +1,15 @@ +ENTRY(main) +SECTIONS +{ + .ivt 0x80000000 : + { + KEEP (*(.ivt)); + } + . = 0x80000100; + .text : { *(.text) } + .data : { *(.data) } + .bss : { *(.bss COMMON) } + . = ALIGN(8); + . = . + 0x1000; /* 4kB of stack memory */ + stack_top = .; +} diff --git a/tests/tcg/arc/test_macros.h b/tests/tcg/arc/test_macros.h new file mode 100644 index 0000000000..15325e1ffa --- /dev/null +++ b/tests/tcg/arc/test_macros.h @@ -0,0 +1,257 @@ +#ifndef __TEST_MACROS_SCALAR_H +#define __TEST_MACROS_SCALAR_H + +#ifdef ARCTEST_ARC32 +#define __arc_xlen 32 +#else +#define __arc_xlen 64 +#endif + +#define xstr(a) str(a) +#define str(a) #a + +#define MASK_XLEN(x) ((x) & ((1 << (__arc_xlen - 1) << 1) - 1)) +#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11)) + +#define TEST_CASE( testnum, testreg, correctval, name, code... ) \ + test_ ## testnum: \ + code` \ + mov r12, testnum` \ + sub.f 0,testreg, correctval` \ + bne @fail` \ + PASS_TEST(name) + +#define TEST_IMM_OP( testnum, inst, result, val1, imm ) \ + TEST_CASE( testnum, r0, result, xstr(inst) ":" xstr(testnum), \ + mov r1, MASK_XLEN(val1)` \ + inst r0, r1, SEXT_IMM(imm) \ + ) + +#define TEST_RR_3OP( testnum, inst, result, val1, val2 ) \ + TEST_CASE( testnum, r0, result, xstr(inst) ":" xstr(testnum), \ + mov r1, MASK_XLEN(val1)` \ + mov r2, MASK_XLEN(val2)` \ + inst r0, r1, r2 \ + ) + +#define TEST_RR_2OP( testnum, inst, result, val) \ + TEST_CASE( testnum, r0, result, xstr(inst) ":" xstr(testnum), \ + mov r1, MASK_XLEN(val)` \ + inst r0, r1 \ + ) + +#define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \ + TEST_CASE( testnum, r1, result, xstr(inst) ":" xstr(testnum), \ + mov r1, MASK_XLEN(val1)` \ + inst r1, r1, SEXT_IMM(imm) \ + ) + +#define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \ + TEST_CASE( testnum, r1, result, xstr(inst) ":" xstr(testnum), \ + mov r1, MASK_XLEN(val1)` \ + mov r2, MASK_XLEN(val2)` \ + inst r1, r1, r2 \ + ) + +#define TEST_RR_2OP_SRC1_EQ_DEST( testnum, inst, result, val ) \ + TEST_CASE( testnum, r1, result, xstr(inst) ":" xstr(testnum), \ + mov r1, MASK_XLEN(val)` \ + inst r1, r1 \ + ) + +#define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \ + TEST_CASE( testnum, r2, result, xstr(inst) ":" xstr(testnum), \ + mov r1, MASK_XLEN(val1)` \ + mov r2, MASK_XLEN(val2)` \ + inst r2, r1, r2 \ + ) + +#define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \ + TEST_CASE( testnum, r1, result, xstr(inst) ":" xstr(testnum), \ + mov r1, MASK_XLEN(val1)` \ + inst r1, r1, r1 \ + ) + +#define TEST_2OP_CARRY( testnum, inst, expected, val1, val2) \ + test_ ## testnum: \ + mov r12, testnum` \ + mov r1, MASK_XLEN(val1)` \ + mov r2, MASK_XLEN(val2)` \ + inst.f 0, r1, r2` \ + mov.cs r3,(~expected) & 0x01` \ + mov.cc r3, (expected) & 0x01` \ + cmp r3, 0` \ + bne @fail + +#define TEST_1OP_CARRY( testnum, inst, expected, val) \ + test_ ## testnum: \ + mov r12, testnum` \ + add.f 0, r0, r0` \ + mov r1, MASK_XLEN(val)` \ + inst.f 0, r1` \ + mov.cs r3,(~expected) & 0x01` \ + mov.cc r3, (expected) & 0x01` \ + cmp r3, 0` \ + bne @fail + +#define TEST_2OP_ZERO( testnum, inst, expected, val1, val2) \ + test_ ## testnum: \ + mov r12, testnum` \ + mov r1, MASK_XLEN(val1)` \ + mov r2, MASK_XLEN(val2)` \ + inst.f 0, r1, r2` \ + mov.eq r3, (~expected) & 0x01` \ + mov.ne r3, (expected) & 0x01` \ + cmp r3, 0` \ + bne @fail + +#define TEST_1OP_ZERO( testnum, inst, expected, val) \ + test_ ## testnum: \ + mov r12, testnum` \ + add.f 0, r0, r0` \ + mov r1, MASK_XLEN(val)` \ + inst.f 0, r1` \ + mov.eq r3, (~expected) & 0x01` \ + mov.ne r3, (expected) & 0x01` \ + cmp r3, 0` \ + bne @fail + +#define TEST_2OP_OVERFLOW( testnum, inst, expected, val1, val2) \ + test_ ## testnum: \ + mov r12, testnum` \ + mov r1, MASK_XLEN(val1)` \ + mov r2, MASK_XLEN(val2)` \ + inst.f 0, r1, r2` \ + mov.vs r3,(~expected) & 0x01` \ + mov.vc r3, (expected) & 0x01` \ + cmp r3, 0` \ + bne @fail + +#define TEST_1OP_OVERFLOW( testnum, inst, expected, val) \ + test_ ## testnum: \ + mov r12, testnum` \ + add.f 0, r0, r0` \ + mov r1, MASK_XLEN(val)` \ + inst.f 0, r1` \ + mov.vs r3,(~expected) & 0x01` \ + mov.vc r3, (expected) & 0x01` \ + cmp r3, 0` \ + bne @fail + +#define TEST_2OP_NEGATIVE( testnum, inst, expected, val1, val2) \ + test_ ## testnum: \ + mov r12, testnum` \ + mov r1, MASK_XLEN(val1)` \ + mov r2, MASK_XLEN(val2)` \ + inst.f 0, r1, r2` \ + mov.mi r3,(~expected) & 0x01` \ + mov.pl r3, (expected) & 0x01` \ + cmp r3, 0` \ + bne @fail + +#define TEST_1OP_NEGATIVE( testnum, inst, expected, val) \ + test_ ## testnum: \ + mov r12, testnum` \ + add.f 0, r0, r0` \ + mov r1, MASK_XLEN(val)` \ + inst.f 0, r1` \ + mov.mi r3,(~expected) & 0x01` \ + mov.pl r3, (expected) & 0x01` \ + cmp r3, 0` \ + bne @fail + + +#endif + +#define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \ + test_ ## testnum:` \ + mov r12, testnum` \ + mov r1, val1` \ + mov r2, val2` \ + sub.f 0,r1,r2` \ + inst 1f` \ + b @fail` \ + 1: + +#define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \ + test_ ## testnum:` \ + mov r12,testnum` \ + mov r1, val1` \ + mov r2, val2` \ + sub.f 0,r1,r2` \ + inst @fail + +#define TEST_BR_OP_TAKEN( testnum, inst, val1, val2 ) \ + test_ ## testnum:` \ + mov r12, testnum` \ + mov r1, val1` \ + mov r2, val2` \ + inst r1,r2,1f` \ + b @fail` \ + 1: + +#define TEST_BR_OP_NOTTAKEN( testnum, inst, val1, val2 ) \ + test_ ## testnum:` \ + mov r12,testnum` \ + mov r1, val1` \ + mov r2, val2` \ + inst r1,r2,@fail + +#define ARCTEST_BEGIN \ + .text` \ + .align 4 ` \ + .global main` \ + main: \ + test_1:` \ + mov r12,1` \ + mov.f 0,0` \ + bne @fail + +#define ARCTEST_END \ + .align 4 ` \ +1:`\ + st 1,[0xf0000008]`\ + b @1b`\ +fail:`\ + mov r2, '['`\ + st r2, [0x90000000]`\ + mov r2, 'F'`\ + st r2, [0x90000000]`\ + mov r2, 'a'`\ + st r2, [0x90000000]`\ + mov r2, 'i'`\ + st r2, [0x90000000]`\ + mov r2, 'l'`\ + st r2, [0x90000000]`\ + mov r2, ']'`\ + st r2, [0x90000000]`\ + mov r2, ' '`\ + st r2, [0x90000000]`\ + mov r13, r12`\ + mov r15, 0x30`\ + mov r14, r12`\ +loop_z: `\ + sub.f r13, r13, 0x0A`\ + add.pl r15, r15, 1`\ + mov.pl r14, r13 `\ + bpl @loop_z`\ + st r15, [0x90000000]`\ + add r14, r14, 0x30`\ + st r14, [0x90000000]`\ + mov r2, '\n'`\ + st r2, [0x90000000]`\ + b 1b` + +#define PASS_TEST(name)\ + .data ` \ +2010:`\ + .ascii "[PASS] ",name ,"\n\0"` \ + .align 4`\ + .text`\ + mov_s r11, @2010b`\ + 1010:`\ + ldb.ab r12, [r11, 1]`\ + breq r12, 0, @1011f`\ + stb r12, [0x90000000]`\ + j @1010b`\ + 1011:` diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index e1b70e25f2..a486ad9b32 100755 --- a/tests/tcg/configure.sh +++ b/tests/tcg/configure.sh @@ -47,6 +47,7 @@ fi : ${cross_cc_aarch64_be="$cross_cc_aarch64"} : ${cross_cc_cflags_aarch64_be="-mbig-endian"} : $(cross_cc_alpha="alpha-linux-gnu-gcc") +: ${cross_cc_arc="arc-elf32-gcc"} : ${cross_cc_arm="arm-linux-gnueabihf-gcc"} : ${cross_cc_cflags_armeb="-mbig-endian"} : ${cross_cc_hppa="hppa-linux-gnu-gcc"} @@ -94,7 +95,7 @@ for target in $target_list; do xtensa|xtensaeb) arches=xtensa ;; - alpha|cris|hppa|i386|lm32|microblaze|microblazeel|m68k|openrisc|riscv64|s390x|sh4|sparc64) + arc|alpha|cris|hppa|i386|lm32|microblaze|microblazeel|m68k|openrisc|riscv64|s390x|sh4|sparc64) arches=$target ;; *) From patchwork Wed Nov 11 16:17:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cupertino Miranda X-Patchwork-Id: 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[2.80.104.46]) by smtp.gmail.com with ESMTPSA id s188sm3115178wmf.45.2020.11.11.08.18.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2020 08:18:24 -0800 (PST) From: cupertinomiranda@gmail.com To: qemu-devel@nongnu.org Subject: [PATCH 15/15] tests/acceptance: ARC: Add linux boot testing. Date: Wed, 11 Nov 2020 16:17:58 +0000 Message-Id: <20201111161758.9636-16-cupertinomiranda@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201111161758.9636-1-cupertinomiranda@gmail.com> References: <20201111161758.9636-1-cupertinomiranda@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201111_111827_090087_9677E5BB X-CRM114-Status: UNSURE ( 9.36 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:42b listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [cupertinomiranda[at]gmail.com] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Claudiu Zissulescu , Cupertino Miranda , Shahab Vahedi , Shahab Vahedi , Cupertino Miranda , linux-snps-arc@lists.infradead.org, Claudiu Zissulescu Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Cupertino Miranda Just an acceptance test with ARC Linux booting. Signed-off-by: Cupertino Miranda --- tests/acceptance/boot_linux_console.py | 55 ++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py index 8f433a67f8..3eae551905 100644 --- a/tests/acceptance/boot_linux_console.py +++ b/tests/acceptance/boot_linux_console.py @@ -137,6 +137,26 @@ class BootLinuxConsole(LinuxKernelTest): console_pattern = 'Kernel command line: %s' % kernel_command_line self.wait_for_console_pattern(console_pattern) + def test_mips_malta(self): + """ + :avocado: tags=arch:arc + """ + deb_url = ('http://snapshot.debian.org/archive/debian/' + '20130217T032700Z/pool/main/l/linux-2.6/' + 'linux-image-2.6.32-5-4kc-malta_2.6.32-48_mips.deb') + deb_hash = 'a8cfc28ad8f45f54811fc6cf74fc43ffcfe0ba04' + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) + kernel_path = self.extract_from_deb(deb_path, + '/boot/vmlinux-archs') + + self.vm.set_console() + kernel_command_line = self.KERNEL_COMMON_COMMAND_LINE + 'console=ttyS0' + self.vm.add_args('-kernel', kernel_path, + '-append', kernel_command_line) + self.vm.launch() + console_pattern = 'Kernel command line: %s' % kernel_command_line + self.wait_for_console_pattern(console_pattern) + def test_mips64el_malta(self): """ This test requires the ar tool to extract "data.tar.gz" from @@ -973,6 +993,17 @@ class BootLinuxConsole(LinuxKernelTest): console_pattern = 'Kernel command line: %s' % kernel_command_line self.wait_for_console_pattern(console_pattern) + def do_test_arc(self, kernel_name, console=0): + tar_url = ('https://github.com/cupertinomiranda/arc-qemu-resources/archive/master.tar.gz') + file_path = self.fetch_asset(tar_url) + archive.extract(file_path, self.workdir) + + self.vm.set_console(console_index=console) + self.vm.add_args('-kernel', + self.workdir + '/' + kernel_name) + self.vm.launch() + self.wait_for_console_pattern('QEMU advent calendar') + def test_m68k_q800(self): """ :avocado: tags=arch:m68k @@ -1101,3 +1132,27 @@ class BootLinuxConsole(LinuxKernelTest): tar_hash = '49e88d9933742f0164b60839886c9739cb7a0d34' self.vm.add_args('-cpu', 'dc233c') self.do_test_advcal_2018('02', tar_hash, 'santas-sleigh-ride.elf') + + timeout = 240 + def test_arc_virt(self): + """ + :avocado: tags=arch:arc + :avocado: tags=machine:virt + """ + + tar_url = ('https://github.com/cupertinomiranda/' + 'arc-qemu-resources/archive/master.tar.gz') + file_path = self.fetch_asset(tar_url) + archive.extract(file_path, self.workdir) + + kernel_path = self.workdir + '/arc-qemu-resources-master/vmlinux_archs' + + self.vm.set_console() + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE) + self.vm.add_args('-kernel', kernel_path) + self.vm.add_args('-device', 'virtio-net-device,netdev=net0') + self.vm.add_args('-netdev', 'user,id=net0,hostfwd=tcp::5558-:21,hostfwd=tcp::5557-:23') + self.vm.launch() + + console_pattern = 'Welcome to Buildroot' + self.wait_for_console_pattern(console_pattern)