From patchwork Thu Jan 4 11:27:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akshay Adiga X-Patchwork-Id: 855560 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zC5DL5zlzz9t20 for ; Thu, 4 Jan 2018 22:29:22 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3zC5DL2RZtzDqpN for ; Thu, 4 Jan 2018 22:29:22 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=akshay.adiga@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3zC5CF2Z3RzDqpN for ; Thu, 4 Jan 2018 22:28:24 +1100 (AEDT) Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w04BOIEp124773 for ; Thu, 4 Jan 2018 06:28:22 -0500 Received: from e06smtp10.uk.ibm.com (e06smtp10.uk.ibm.com [195.75.94.106]) by mx0a-001b2d01.pphosted.com with ESMTP id 2f9kbx85aq-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 04 Jan 2018 06:28:21 -0500 Received: from localhost by e06smtp10.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 4 Jan 2018 11:28:16 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w04BSGFh46530564; Thu, 4 Jan 2018 11:28:16 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A698611C054; Thu, 4 Jan 2018 11:22:13 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9B48611C04C; Thu, 4 Jan 2018 11:22:12 +0000 (GMT) Received: from aksadiga.in.ibm.com (unknown [9.77.193.244]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 4 Jan 2018 11:22:12 +0000 (GMT) From: Akshay Adiga To: skiboot@lists.ozlabs.org Date: Thu, 4 Jan 2018 16:57:58 +0530 X-Mailer: git-send-email 2.5.5 In-Reply-To: <1515065286-8656-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> References: <1515065286-8656-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18010411-0040-0000-0000-000004009815 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18010411-0041-0000-0000-00002603DFA8 Message-Id: <1515065286-8656-2-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-01-04_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1801040157 Subject: [Skiboot] [PATCH 1/9] SLW: Delay cpuidle device-tree creation X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Create cpuidle device-tree after slw_init(), so that we can stop the deeper states from being added , when wakeup engine is not present or failed. Signed-off-by: Akshay Adiga --- core/opal.c | 1 - hw/slw.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/core/opal.c b/core/opal.c index d33d527c..8bfa6615 100644 --- a/core/opal.c +++ b/core/opal.c @@ -407,7 +407,6 @@ void add_opal_node(void) add_opal_firmware_node(); add_associativity_ref_point(); memcons_add_properties(); - add_cpu_idle_state_properties(); } static struct lock evt_lock = LOCK_UNLOCKED; diff --git a/hw/slw.c b/hw/slw.c index c2c755d1..d6d140f8 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -1689,4 +1689,5 @@ void slw_init(void) for_each_chip(chip) slw_init_chip_p9(chip); } + add_cpu_idle_state_properties(); } From patchwork Thu Jan 4 11:27:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akshay Adiga X-Patchwork-Id: 855566 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zC5Gb02qxz9sRm for ; Thu, 4 Jan 2018 22:31:19 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3zC5GZ5N50zDqxR for ; Thu, 4 Jan 2018 22:31:18 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=akshay.adiga@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3zC5Cd1b5xzDr5W for ; Thu, 4 Jan 2018 22:28:45 +1100 (AEDT) Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w04BSgSE045840 for ; Thu, 4 Jan 2018 06:28:43 -0500 Received: from e06smtp14.uk.ibm.com (e06smtp14.uk.ibm.com [195.75.94.110]) by mx0a-001b2d01.pphosted.com with ESMTP id 2f9hvvc2yu-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 04 Jan 2018 06:28:42 -0500 Received: from localhost by e06smtp14.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 4 Jan 2018 11:28:19 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w04BSIj544433636; Thu, 4 Jan 2018 11:28:19 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 462B311C05B; Thu, 4 Jan 2018 11:22:16 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2F86E11C04C; Thu, 4 Jan 2018 11:22:15 +0000 (GMT) Received: from aksadiga.in.ibm.com (unknown [9.77.193.244]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 4 Jan 2018 11:22:14 +0000 (GMT) From: Akshay Adiga To: skiboot@lists.ozlabs.org Date: Thu, 4 Jan 2018 16:57:59 +0530 X-Mailer: git-send-email 2.5.5 In-Reply-To: <1515065286-8656-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> References: <1515065286-8656-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18010411-0016-0000-0000-000005139ABF X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18010411-0017-0000-0000-0000284FE6DD Message-Id: <1515065286-8656-3-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-01-04_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1801040159 Subject: [Skiboot] [PATCH 2/9] SLW: Split init functions X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This patch seperates code which deals with wakeup_engine from one which doesn't. Init functions for power8 and power9 are split into chip_init and late_init. slw_late_init_p?() contains wakeup_engine related code. Signed-off-by: Akshay Adiga --- hw/slw.c | 75 +++++++++++++++++++++++++++++++++++++--------------------------- 1 file changed, 43 insertions(+), 32 deletions(-) diff --git a/hw/slw.c b/hw/slw.c index d6d140f8..2fdfa4e8 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -803,6 +803,36 @@ static struct cpu_idle_states power9_ndd1_cpu_idle_states[] = { | OPAL_PM_PSSCR_EC, .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK } }; +static void slw_late_init_p9(struct proc_chip *chip) +{ + struct cpu_thread *c; + int rc; + + if (!chip->homer_base) { + log_simple_error(&e_info(OPAL_RC_SLW_REG), + "SLW: HOMER base not set %x\n", + chip->id); + return; + } + prlog(PR_NOTICE, "SLW: Configuring self-restore for HRMOR\n"); + for_each_available_cpu(c) { + if (c->chip_id != chip->id) + continue; + /* + * Clear HRMOR. Need to update only for thread + * 0 of each core. Doing it anyway for all threads + */ + rc = p9_stop_save_cpureg((void *)chip->homer_base, + P9_STOP_SPR_HRMOR, 0, + c->pir); + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_REG), + "SLW: Failed to set HRMOR for CPU %x,RC=0x%x\n", + c->pir, rc); + prlog(PR_ERR, "Disabling deep stop states\n"); + } + } +} /* Add device tree properties to describe idle states */ void add_cpu_idle_state_properties(void) @@ -1265,7 +1295,6 @@ static void slw_patch_regs(struct proc_chip *chip) static void slw_init_chip_p9(struct proc_chip *chip) { struct cpu_thread *c; - int rc; prlog(PR_DEBUG, "SLW: Init chip 0x%x\n", chip->id); @@ -1273,38 +1302,11 @@ static void slw_init_chip_p9(struct proc_chip *chip) for_each_available_core_in_chip(c, chip->id) slw_set_overrides_p9(chip, c); - if (!chip->homer_base) { - log_simple_error(&e_info(OPAL_RC_SLW_REG), - "SLW: HOMER base not set %x\n", - chip->id); - return; - } - - prlog(PR_NOTICE, "SLW: Configuring self-restore for HRMOR\n"); - - /* Should this be for_each_present_cpu() ? */ - for_each_available_cpu(c) { - if (c->chip_id != chip->id) - continue; - /* - * Clear HRMOR. Need to update only for thread - * 0 of each core. Doing it anyway for all threads - */ - rc = p9_stop_save_cpureg((void *)chip->homer_base, - P9_STOP_SPR_HRMOR, 0, - c->pir); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_REG), - "SLW: Failed to set HRMOR for CPU %x,RC=0x%x\n", - c->pir, rc); - } - } } -static void slw_init_chip(struct proc_chip *chip) +static void slw_late_init_p8(struct proc_chip *chip) { int64_t rc; - struct cpu_thread *c; prlog(PR_DEBUG, "SLW: Init chip 0x%x\n", chip->id); @@ -1337,6 +1339,11 @@ static void slw_init_chip(struct proc_chip *chip) /* Patch SLW image */ slw_patch_regs(chip); +} +static void slw_init_chip_p8(struct proc_chip *chip) +{ + struct cpu_thread *c; + /* At power ON setup inits for fast-sleep */ for_each_available_core_in_chip(c, chip->id) { idle_prepare_core(chip, c); @@ -1682,12 +1689,16 @@ void slw_init(void) struct proc_chip *chip; if (proc_gen == proc_gen_p8) { - for_each_chip(chip) - slw_init_chip(chip); + for_each_chip(chip) { + slw_init_chip_p8(chip); + slw_late_init_p8(chip); + } slw_init_timer(); } else if (proc_gen == proc_gen_p9) { - for_each_chip(chip) + for_each_chip(chip) { slw_init_chip_p9(chip); + slw_late_init_p9(chip); + } } add_cpu_idle_state_properties(); } From patchwork Thu Jan 4 11:28:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akshay Adiga X-Patchwork-Id: 855567 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zC5Gw60Fnz9sQm for ; Thu, 4 Jan 2018 22:31:36 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3zC5Gw4RGmzDqpF for ; Thu, 4 Jan 2018 22:31:36 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=akshay.adiga@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3zC5Cg6pD7zF0PG for ; Thu, 4 Jan 2018 22:28:47 +1100 (AEDT) Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w04BSgO2045938 for ; Thu, 4 Jan 2018 06:28:45 -0500 Received: from e06smtp15.uk.ibm.com (e06smtp15.uk.ibm.com [195.75.94.111]) by mx0a-001b2d01.pphosted.com with ESMTP id 2f9hvvc31r-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 04 Jan 2018 06:28:44 -0500 Received: from localhost by e06smtp15.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 4 Jan 2018 11:28:21 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w04BSLEx47841332; Thu, 4 Jan 2018 11:28:21 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DCCE611C050; Thu, 4 Jan 2018 11:22:18 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EA5CD11C04A; Thu, 4 Jan 2018 11:22:17 +0000 (GMT) Received: from aksadiga.in.ibm.com (unknown [9.77.193.244]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 4 Jan 2018 11:22:17 +0000 (GMT) From: Akshay Adiga To: skiboot@lists.ozlabs.org Date: Thu, 4 Jan 2018 16:58:00 +0530 X-Mailer: git-send-email 2.5.5 In-Reply-To: <1515065286-8656-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> References: <1515065286-8656-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18010411-0020-0000-0000-000003E68293 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18010411-0021-0000-0000-0000427894CD Message-Id: <1515065286-8656-4-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-01-04_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1801040159 Subject: [Skiboot] [PATCH 3/9] SLW: Call slw_late_init_p{8, 9} only when has_wakeup_engine is set X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Patch adds the following changes : - Moves slw image sanity check to a seperate function called slw_image_check_p{8,9}() - Move has_wakeup_engine to global scope, so that it can be set by other functions - Code which uses wakeup_engine will only be called if sanity check passes. Signed-off-by: Akshay Adiga --- hw/slw.c | 51 +++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 37 insertions(+), 14 deletions(-) diff --git a/hw/slw.c b/hw/slw.c index 2fdfa4e8..02aa67ea 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -40,6 +40,8 @@ static uint32_t slw_saved_reset[MAX_RESET_PATCH_SIZE]; static bool slw_current_le = false; +bool has_wakeup_engine = true; + /* SLW timer related stuff */ static bool slw_has_timer; static uint64_t slw_timer_inc; @@ -808,12 +810,6 @@ static void slw_late_init_p9(struct proc_chip *chip) struct cpu_thread *c; int rc; - if (!chip->homer_base) { - log_simple_error(&e_info(OPAL_RC_SLW_REG), - "SLW: HOMER base not set %x\n", - chip->id); - return; - } prlog(PR_NOTICE, "SLW: Configuring self-restore for HRMOR\n"); for_each_available_cpu(c) { if (c->chip_id != chip->id) @@ -843,7 +839,6 @@ void add_cpu_idle_state_properties(void) int nr_states; bool can_sleep = true; - bool has_wakeup_engine = true; bool has_stop_inst = false; u8 i; @@ -1304,15 +1299,29 @@ static void slw_init_chip_p9(struct proc_chip *chip) } -static void slw_late_init_p8(struct proc_chip *chip) + +static bool slw_image_check_p9(struct proc_chip *chip) { - int64_t rc; - prlog(PR_DEBUG, "SLW: Init chip 0x%x\n", chip->id); + if (!chip->homer_base) { + log_simple_error(&e_info(OPAL_RC_SLW_REG), + "SLW: HOMER base not set %x\n", + chip->id); + return false; + } else + return true; + +} + +static bool slw_image_check_p8(struct proc_chip *chip) +{ + int64_t rc; + + prlog(PR_DEBUG, "SLW: slw_check chip 0x%x\n", chip->id); if (!chip->slw_base) { prerror("SLW: No image found !\n"); - return; + return false; } /* Check actual image size */ @@ -1325,7 +1334,7 @@ static void slw_late_init_p8(struct proc_chip *chip) chip->slw_base = 0; chip->slw_bar_size = 0; chip->slw_image_size = 0; - return; + return false; } prlog(PR_DEBUG, "SLW: Image size from image: 0x%llx\n", chip->slw_image_size); @@ -1334,7 +1343,16 @@ static void slw_late_init_p8(struct proc_chip *chip) log_simple_error(&e_info(OPAL_RC_SLW_INIT), "SLW: Built-in image size larger than BAR size !\n"); /* XXX Panic ? */ + return false; } + return true; + +} + +static void slw_late_init_p8(struct proc_chip *chip) +{ + + prlog(PR_DEBUG, "SLW: late Init chip 0x%x\n", chip->id); /* Patch SLW image */ slw_patch_regs(chip); @@ -1344,6 +1362,7 @@ static void slw_init_chip_p8(struct proc_chip *chip) { struct cpu_thread *c; + prlog(PR_DEBUG, "SLW: Init chip 0x%x\n", chip->id); /* At power ON setup inits for fast-sleep */ for_each_available_core_in_chip(c, chip->id) { idle_prepare_core(chip, c); @@ -1691,13 +1710,17 @@ void slw_init(void) if (proc_gen == proc_gen_p8) { for_each_chip(chip) { slw_init_chip_p8(chip); - slw_late_init_p8(chip); + has_wakeup_engine &= slw_image_check_p8(chip); + if (has_wakeup_engine) + slw_late_init_p8(chip); } slw_init_timer(); } else if (proc_gen == proc_gen_p9) { for_each_chip(chip) { slw_init_chip_p9(chip); - slw_late_init_p9(chip); + has_wakeup_engine &= slw_image_check_p9(chip); + if (has_wakeup_engine) + slw_late_init_p9(chip); } } add_cpu_idle_state_properties(); From patchwork Thu Jan 4 11:28:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akshay Adiga X-Patchwork-Id: 855561 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zC5Dl0Kllz9sQm for ; Thu, 4 Jan 2018 22:29:43 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3zC5Dk6FJszDqxN for ; Thu, 4 Jan 2018 22:29:42 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=akshay.adiga@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3zC5CR6zPZzDqxJ for ; Thu, 4 Jan 2018 22:28:35 +1100 (AEDT) Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w04BSUP4108445 for ; Thu, 4 Jan 2018 06:28:33 -0500 Received: from e06smtp14.uk.ibm.com (e06smtp14.uk.ibm.com [195.75.94.110]) by mx0a-001b2d01.pphosted.com with ESMTP id 2f9kbxr4vr-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 04 Jan 2018 06:28:33 -0500 Received: from localhost by e06smtp14.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 4 Jan 2018 11:28:24 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w04BSOdQ33882280; Thu, 4 Jan 2018 11:28:24 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 605D311C04A; Thu, 4 Jan 2018 11:22:21 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5A2DF11C054; Thu, 4 Jan 2018 11:22:20 +0000 (GMT) Received: from aksadiga.in.ibm.com (unknown [9.77.193.244]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 4 Jan 2018 11:22:20 +0000 (GMT) From: Akshay Adiga To: skiboot@lists.ozlabs.org Date: Thu, 4 Jan 2018 16:58:01 +0530 X-Mailer: git-send-email 2.5.5 In-Reply-To: <1515065286-8656-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> References: <1515065286-8656-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18010411-0016-0000-0000-000005139AC2 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18010411-0017-0000-0000-0000284FE6E0 Message-Id: <1515065286-8656-5-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-01-04_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1801040159 Subject: [Skiboot] [PATCH 4/9] SLW: Use wakeup_engine state to handle errors in wakeup engine X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Patch introduces wakeup_engine_state which replaces a bool has_wakeup_engine. wakeup_engine_state can have 3 states : - WAKEUP_ENGINE_PRESENT : When everything is good. - WAKEUP_ENGINE_NOT_PRESENT : When wakeup_engine is not correctly detected. - WAKEUP_ENGINE_FAILED : If any operation on wakeup_engine failed. Signed-off-by: Akshay Adiga --- hw/slw.c | 38 ++++++++++++++------------------------ include/skiboot.h | 8 ++++++++ 2 files changed, 22 insertions(+), 24 deletions(-) diff --git a/hw/slw.c b/hw/slw.c index 02aa67ea..119f1e28 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -40,7 +40,7 @@ static uint32_t slw_saved_reset[MAX_RESET_PATCH_SIZE]; static bool slw_current_le = false; -bool has_wakeup_engine = true; +enum wakeup_engine_states wakeup_engine_state = WAKEUP_ENGINE_NOT_PRESENT; /* SLW timer related stuff */ static bool slw_has_timer; @@ -931,20 +931,8 @@ void add_cpu_idle_state_properties(void) nr_states = ARRAY_SIZE(power7_cpu_idle_states); } - /* - * Enable deep idle states only if : - * P8 : slw image is intact - * P9 : homer_base is set - */ - if (!(proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)) { - if (proc_gen == proc_gen_p9) - has_wakeup_engine = !!(chip->homer_base); - else /* (proc_gen == proc_gen_p8) */ - has_wakeup_engine = (chip->slw_base && chip->slw_bar_size && - chip->slw_image_size); - } else { - has_wakeup_engine = false; - } + if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) + wakeup_engine_state = WAKEUP_ENGINE_NOT_PRESENT; /* * Currently we can't append strings and cells to dt properties. @@ -972,7 +960,7 @@ void add_cpu_idle_state_properties(void) if (has_stop_inst) { /* Power 9 / POWER ISA 3.0 */ supported_states_mask = OPAL_PM_STOP_INST_FAST; - if (has_wakeup_engine) + if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT) supported_states_mask |= OPAL_PM_STOP_INST_DEEP; } else { /* Power 7 and Power 8 */ @@ -980,7 +968,7 @@ void add_cpu_idle_state_properties(void) if (can_sleep) supported_states_mask |= OPAL_PM_SLEEP_ENABLED | OPAL_PM_SLEEP_ENABLED_ER1; - if (has_wakeup_engine) + if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT) supported_states_mask |= OPAL_PM_WINKLE_ENABLED; } for (i = 0; i < nr_states; i++) { @@ -1476,10 +1464,10 @@ int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val) assert(chip); if (proc_gen == proc_gen_p9) { - if (!chip->homer_base) { + if (wakeup_engine_state != WAKEUP_ENGINE_PRESENT) { log_simple_error(&e_info(OPAL_RC_SLW_REG), - "SLW: HOMER base not set %x\n", - chip->id); + "SLW: wakeup_engine in bad state=%d chip=%x\n", + wakeup_engine_state,chip->id); return OPAL_INTERNAL_ERROR; } rc = p9_stop_save_cpureg((void *)chip->homer_base, @@ -1710,16 +1698,18 @@ void slw_init(void) if (proc_gen == proc_gen_p8) { for_each_chip(chip) { slw_init_chip_p8(chip); - has_wakeup_engine &= slw_image_check_p8(chip); - if (has_wakeup_engine) + if(slw_image_check_p8(chip)) + wakeup_engine_state = WAKEUP_ENGINE_PRESENT; + if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT) slw_late_init_p8(chip); } slw_init_timer(); } else if (proc_gen == proc_gen_p9) { for_each_chip(chip) { slw_init_chip_p9(chip); - has_wakeup_engine &= slw_image_check_p9(chip); - if (has_wakeup_engine) + if(slw_image_check_p9(chip)) + wakeup_engine_state = WAKEUP_ENGINE_PRESENT; + if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT) slw_late_init_p9(chip); } } diff --git a/include/skiboot.h b/include/skiboot.h index db913258..90deff78 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -297,6 +297,14 @@ extern void prd_register_reserved_memory(void); /* Flatten device-tree */ extern void *create_dtb(const struct dt_node *root, bool exclusive); +/* Track failure in Wakup engine */ +enum wakeup_engine_states { + WAKEUP_ENGINE_NOT_PRESENT, + WAKEUP_ENGINE_PRESENT, + WAKEUP_ENGINE_FAILED +}; +extern enum wakeup_engine_states wakeup_engine_state; + /* SLW reinit function for switching core settings */ extern int64_t slw_reinit(uint64_t flags); From patchwork Thu Jan 4 11:28:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akshay Adiga X-Patchwork-Id: 855569 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zC5Hp1KThz9sQm for ; Thu, 4 Jan 2018 22:32:22 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3zC5Hn6rnMzDrW3 for ; Thu, 4 Jan 2018 22:32:21 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=akshay.adiga@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3zC5D626jqzDr0q for ; Thu, 4 Jan 2018 22:29:10 +1100 (AEDT) Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w04BT0rq126791 for ; Thu, 4 Jan 2018 06:29:07 -0500 Received: from e06smtp12.uk.ibm.com (e06smtp12.uk.ibm.com [195.75.94.108]) by mx0a-001b2d01.pphosted.com with ESMTP id 2f9ff6jfx3-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 04 Jan 2018 06:29:04 -0500 Received: from localhost by e06smtp12.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 4 Jan 2018 11:28:26 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w04BSQUr48431334; Thu, 4 Jan 2018 11:28:26 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C850311C050; Thu, 4 Jan 2018 11:22:23 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D594711C052; Thu, 4 Jan 2018 11:22:22 +0000 (GMT) Received: from aksadiga.in.ibm.com (unknown [9.77.193.244]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 4 Jan 2018 11:22:22 +0000 (GMT) From: Akshay Adiga To: skiboot@lists.ozlabs.org Date: Thu, 4 Jan 2018 16:58:02 +0530 X-Mailer: git-send-email 2.5.5 In-Reply-To: <1515065286-8656-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> References: <1515065286-8656-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18010411-0008-0000-0000-000004BD9A02 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18010411-0009-0000-0000-00001E50DF04 Message-Id: <1515065286-8656-6-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-01-04_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1801040159 Subject: [Skiboot] [PATCH 5/9] SLW: Move MAMBO simulator checks to slw_init X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Move MAMBO simulator checks to slw_init. Signed-off-by: Akshay Adiga --- hw/slw.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/hw/slw.c b/hw/slw.c index 119f1e28..a2004c60 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -292,11 +292,6 @@ static bool slw_set_overrides_p9(struct proc_chip *chip, struct cpu_thread *c) int rc; uint32_t core = pir_to_core_id(c->pir); - /* MAMBO does not require this init */ - if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) { - return true; - } - /* Clear special wakeup bits that could hold power mgt */ rc = xscom_write(chip->id, XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_HYP), @@ -931,8 +926,6 @@ void add_cpu_idle_state_properties(void) nr_states = ARRAY_SIZE(power7_cpu_idle_states); } - if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) - wakeup_engine_state = WAKEUP_ENGINE_NOT_PRESENT; /* * Currently we can't append strings and cells to dt properties. @@ -1695,6 +1688,8 @@ void slw_init(void) { struct proc_chip *chip; + if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) + wakeup_engine_state = WAKEUP_ENGINE_NOT_PRESENT; if (proc_gen == proc_gen_p8) { for_each_chip(chip) { slw_init_chip_p8(chip); From patchwork Thu Jan 4 11:28:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akshay Adiga X-Patchwork-Id: 855563 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zC5FC6vV6z9sQm for ; Thu, 4 Jan 2018 22:30:07 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3zC5FC4NCdzDqxN for ; Thu, 4 Jan 2018 22:30:07 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=akshay.adiga@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3zC5CS67FFzDqxN for ; Thu, 4 Jan 2018 22:28:36 +1100 (AEDT) Received: from pps.filterd (m0098416.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w04BSUfJ170043 for ; Thu, 4 Jan 2018 06:28:33 -0500 Received: from e06smtp12.uk.ibm.com (e06smtp12.uk.ibm.com [195.75.94.108]) by mx0b-001b2d01.pphosted.com with ESMTP id 2f9kc605aq-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 04 Jan 2018 06:28:33 -0500 Received: from localhost by e06smtp12.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 4 Jan 2018 11:28:29 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w04BSTHk45351012; Thu, 4 Jan 2018 11:28:29 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 81C1111C04A; Thu, 4 Jan 2018 11:22:26 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 531B011C052; Thu, 4 Jan 2018 11:22:25 +0000 (GMT) Received: from aksadiga.in.ibm.com (unknown [9.77.193.244]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 4 Jan 2018 11:22:25 +0000 (GMT) From: Akshay Adiga To: skiboot@lists.ozlabs.org Date: Thu, 4 Jan 2018 16:58:03 +0530 X-Mailer: git-send-email 2.5.5 In-Reply-To: <1515065286-8656-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> References: <1515065286-8656-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18010411-0008-0000-0000-000004BD9A04 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18010411-0009-0000-0000-00001E50DF06 Message-Id: <1515065286-8656-7-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-01-04_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1801040159 Subject: [Skiboot] [PATCH 6/9] SLW: Detect if deep states are enabled X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Patch adds a global variable which indicates if the deep states are enabled through stop-enabled-bits. Only applies to POWER9. Signed-off-by: Akshay Adiga --- hw/slw.c | 16 +++++++++++++++- include/skiboot.h | 1 + 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/hw/slw.c b/hw/slw.c index a2004c60..5548226b 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -41,6 +41,7 @@ static uint32_t slw_saved_reset[MAX_RESET_PATCH_SIZE]; static bool slw_current_le = false; enum wakeup_engine_states wakeup_engine_state = WAKEUP_ENGINE_NOT_PRESENT; +bool has_deep_states = false; /* SLW timer related stuff */ static bool slw_has_timer; @@ -892,8 +893,21 @@ void add_cpu_idle_state_properties(void) has_stop_inst = true; stop_levels = dt_prop_get_u32_def(power_mgt, "ibm,enabled-stop-levels", 0); - if (!stop_levels) + if (!stop_levels) { prerror("SLW: No stop levels available. Power saving is disabled!\n"); + has_deep_states = false; + } else { + /* Iterate to see if we have deep states enabled */ + for (i = 0; i < nr_states; i++) { + u32 level = 31 - (states[i].pm_ctrl_reg_val & + OPAL_PM_PSSCR_RL_MASK); + + if ((stop_levels & (1ul << level)) && + (states[i].flags & OPAL_PM_STOP_INST_DEEP)) + has_deep_states = true; + } + } + } else if (chip->type == PROC_CHIP_P8_MURANO || chip->type == PROC_CHIP_P8_VENICE || chip->type == PROC_CHIP_P8_NAPLES) { diff --git a/include/skiboot.h b/include/skiboot.h index 90deff78..859db56d 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -304,6 +304,7 @@ enum wakeup_engine_states { WAKEUP_ENGINE_FAILED }; extern enum wakeup_engine_states wakeup_engine_state; +extern bool has_deep_states; /* SLW reinit function for switching core settings */ extern int64_t slw_reinit(uint64_t flags); From patchwork Thu Jan 4 11:28:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akshay Adiga X-Patchwork-Id: 855564 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zC5Fc1L6yz9sQm for ; Thu, 4 Jan 2018 22:30:28 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3zC5Fc08zVzDrW3 for ; Thu, 4 Jan 2018 22:30:28 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=akshay.adiga@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3zC5CW4qRMzDr01 for ; Thu, 4 Jan 2018 22:28:39 +1100 (AEDT) Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w04BSa1m011546 for ; Thu, 4 Jan 2018 06:28:37 -0500 Received: from e06smtp14.uk.ibm.com (e06smtp14.uk.ibm.com [195.75.94.110]) by mx0b-001b2d01.pphosted.com with ESMTP id 2f9hcmn9k6-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 04 Jan 2018 06:28:36 -0500 Received: from localhost by e06smtp14.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 4 Jan 2018 11:28:32 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w04BSVNk44826694; Thu, 4 Jan 2018 11:28:31 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1298F11C054; Thu, 4 Jan 2018 11:22:29 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1824411C04A; Thu, 4 Jan 2018 11:22:28 +0000 (GMT) Received: from aksadiga.in.ibm.com (unknown [9.77.193.244]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 4 Jan 2018 11:22:27 +0000 (GMT) From: Akshay Adiga To: skiboot@lists.ozlabs.org Date: Thu, 4 Jan 2018 16:58:04 +0530 X-Mailer: git-send-email 2.5.5 In-Reply-To: <1515065286-8656-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> References: <1515065286-8656-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18010411-0016-0000-0000-000005139AC7 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18010411-0017-0000-0000-0000284FE6E6 Message-Id: <1515065286-8656-8-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-01-04_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1801040159 Subject: [Skiboot] [PATCH 7/9] SLW: Call p9_stop_api only if deep_states are enabled X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" All init time p9_stop_api calls have been isolated to slw_late_init. If p9_stop_api fails, then the deep states can be excluded from device tree. For p9_stop_api called after device-tree for cpuidle is created , has_deep_states will be used to check if this call is even required. Signed-off-by: Akshay Adiga --- hw/slw.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/slw.c b/hw/slw.c index 5548226b..e461030c 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -908,6 +908,10 @@ void add_cpu_idle_state_properties(void) } } + if ((wakeup_engine_state == WAKEUP_ENGINE_PRESENT) && has_deep_states) + slw_late_init_p9(chip); + if (wakeup_engine_state != WAKEUP_ENGINE_PRESENT) + has_deep_states = false; } else if (chip->type == PROC_CHIP_P8_MURANO || chip->type == PROC_CHIP_P8_VENICE || chip->type == PROC_CHIP_P8_NAPLES) { @@ -1471,6 +1475,11 @@ int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val) assert(chip); if (proc_gen == proc_gen_p9) { + if (!has_deep_states) { + prlog(PR_INFO, "SLW: Deep states not enabled\n"); + return OPAL_SUCCESS; + } + if (wakeup_engine_state != WAKEUP_ENGINE_PRESENT) { log_simple_error(&e_info(OPAL_RC_SLW_REG), "SLW: wakeup_engine in bad state=%d chip=%x\n", From patchwork Thu Jan 4 11:28:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akshay Adiga X-Patchwork-Id: 855565 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zC5G06mKdz9sQm for ; Thu, 4 Jan 2018 22:30:48 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3zC5G00rk1zDqyV for ; Thu, 4 Jan 2018 22:30:48 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=akshay.adiga@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3zC5CX41stzDr20 for ; Thu, 4 Jan 2018 22:28:40 +1100 (AEDT) Received: from pps.filterd (m0098416.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w04BSVNP170221 for ; Thu, 4 Jan 2018 06:28:38 -0500 Received: from e06smtp10.uk.ibm.com (e06smtp10.uk.ibm.com [195.75.94.106]) by mx0b-001b2d01.pphosted.com with ESMTP id 2f9kc605ge-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 04 Jan 2018 06:28:38 -0500 Received: from localhost by e06smtp10.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 4 Jan 2018 11:28:34 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w04BSYXb47907002; Thu, 4 Jan 2018 11:28:34 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BB63E11C04A; Thu, 4 Jan 2018 11:22:31 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A209E11C050; Thu, 4 Jan 2018 11:22:30 +0000 (GMT) Received: from aksadiga.in.ibm.com (unknown [9.77.193.244]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 4 Jan 2018 11:22:30 +0000 (GMT) From: Akshay Adiga To: skiboot@lists.ozlabs.org Date: Thu, 4 Jan 2018 16:58:05 +0530 X-Mailer: git-send-email 2.5.5 In-Reply-To: <1515065286-8656-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> References: <1515065286-8656-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18010411-0040-0000-0000-000004009819 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18010411-0041-0000-0000-00002603DFAD Message-Id: <1515065286-8656-9-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-01-04_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1801040159 Subject: [Skiboot] [PATCH 8/9] SCOM restore for DARN and XIVE X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" While waking up from stop11, we want NCU_DARN_BAR to have enable bit set. Without this stop_api call, the value restored is without enable bit set. We loose NCU_SPEC_BAR when the quad goes into stop11, stop_api will restore while waking up from stop11. Signed-off-by: Akshay Adiga --- hw/nx.c | 42 ++++++++++++++++++++++++++++++++++++++++++ hw/slw.c | 6 ++++-- hw/xive.c | 30 ++++++++++++++++++++++++++++++ include/skiboot.h | 4 ++++ 4 files changed, 80 insertions(+), 2 deletions(-) diff --git a/hw/nx.c b/hw/nx.c index f6e823f6..0f6ff04d 100644 --- a/hw/nx.c +++ b/hw/nx.c @@ -24,6 +24,7 @@ #include #include #include +#include static void p9_darn_init(void) { @@ -61,6 +62,47 @@ static void p9_darn_init(void) P9X_EX_NCU_DARN_BAR); xscom_write(chip->id, addr, bar | P9X_EX_NCU_DARN_BAR_EN); + + } + } +} + +void nx_p9_rng_late_init(void) +{ + struct cpu_thread *c; + uint64_t rc; + + if (proc_gen != proc_gen_p9) + return; + if (chip_quirk(QUIRK_NO_RNG)) + return; + + prlog(PR_NOTICE, "SLW: Configuring self-restore for P9X_EX_NCU_DARN_BAR\n"); + for_each_present_cpu(c) { + if(cpu_is_thread0(c)) { + struct proc_chip *chip = get_chip(c->chip_id); + uint64_t addr, bar; + + phys_map_get(chip->id, NX_RNG, 0, &bar, NULL); + addr = XSCOM_ADDR_P9_EX(pir_to_core_id(c->pir), + P9X_EX_NCU_DARN_BAR); + /* Bail out if wakeup engine has already failed */ + if ( wakeup_engine_state != WAKEUP_ENGINE_PRESENT) { + prlog(PR_ERR,"DARN BAR p9_stop_api fail detected\n"); + break; + } + rc = p9_stop_save_scom((void *)chip->homer_base, + addr, bar | P9X_EX_NCU_DARN_BAR_EN, + P9_STOP_SCOM_REPLACE, + P9_STOP_SECTION_EQ_SCOM); + if (rc) { + prlog(PR_ERR, + "p9_stop_api for DARN_BAR failed rc= %lld", + rc); + prlog(PR_ERR, "Disabling deep stop states\n"); + wakeup_engine_state = WAKEUP_ENGINE_FAILED; + break; + } } } } diff --git a/hw/slw.c b/hw/slw.c index e461030c..ee02124b 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -907,9 +907,11 @@ void add_cpu_idle_state_properties(void) has_deep_states = true; } } - - if ((wakeup_engine_state == WAKEUP_ENGINE_PRESENT) && has_deep_states) + if ((wakeup_engine_state == WAKEUP_ENGINE_PRESENT) && has_deep_states) { slw_late_init_p9(chip); + xive_late_init(); + nx_p9_rng_late_init(); + } if (wakeup_engine_state != WAKEUP_ENGINE_PRESENT) has_deep_states = false; } else if (chip->type == PROC_CHIP_P8_MURANO || diff --git a/hw/xive.c b/hw/xive.c index c0ee2ab8..b87cb985 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -24,6 +24,7 @@ #include #include #include +#include /* Use Block group mode to move chip_id into block .... */ #define USE_BLOCK_GROUP_MODE @@ -3159,6 +3160,35 @@ static void xive_configure_ex_special_bar(struct xive *x, struct cpu_thread *c) } } +void xive_late_init(void) +{ + struct cpu_thread *c; + + prlog(PR_NOTICE, "SLW: Configuring self-restore for NCU_SPEC_BAR\n"); + for_each_present_cpu(c) { + if(cpu_is_thread0(c)) { + struct proc_chip *chip = get_chip(c->chip_id); + struct xive *x = chip->xive; + uint64_t xa, val, rc; + xa = XSCOM_ADDR_P9_EX(pir_to_core_id(c->pir), + P9X_EX_NCU_SPEC_BAR); + val = (uint64_t)x->tm_base | P9X_EX_NCU_SPEC_BAR_ENABLE; + /* Bail out if wakeup engine has already failed */ + if ( wakeup_engine_state != WAKEUP_ENGINE_PRESENT) { + prlog(PR_ERR, "XIVE p9_stop_api fail detected\n"); + break; + } + rc = p9_stop_save_scom((void *)chip->homer_base, xa, val, + P9_STOP_SCOM_REPLACE, P9_STOP_SECTION_EQ_SCOM); + if (rc) { + xive_cpu_err(c, "p9_stop_api failed for NCU_SPEC_BAR rc=%lld\n", + rc); + wakeup_engine_state = WAKEUP_ENGINE_FAILED; + } + } + } + +} static void xive_provision_cpu(struct xive_cpu_state *xs, struct cpu_thread *c) { struct xive *x; diff --git a/include/skiboot.h b/include/skiboot.h index 859db56d..cc3820b2 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -305,6 +305,10 @@ enum wakeup_engine_states { }; extern enum wakeup_engine_states wakeup_engine_state; extern bool has_deep_states; +extern void nx_p9_rng_late_init(void); +extern void xive_late_init(void); + + /* SLW reinit function for switching core settings */ extern int64_t slw_reinit(uint64_t flags); From patchwork Thu Jan 4 11:28:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akshay Adiga X-Patchwork-Id: 855568 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zC5HQ6wRtz9sRm for ; Thu, 4 Jan 2018 22:32:02 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3zC5HQ3ZwjzDqZg for ; Thu, 4 Jan 2018 22:32:02 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; 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Violators will be prosecuted; Thu, 4 Jan 2018 11:28:37 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w04BSbQv44630270; Thu, 4 Jan 2018 11:28:37 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7A69A11C04A; Thu, 4 Jan 2018 11:22:34 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3511611C050; Thu, 4 Jan 2018 11:22:33 +0000 (GMT) Received: from aksadiga.in.ibm.com (unknown [9.77.193.244]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 4 Jan 2018 11:22:32 +0000 (GMT) From: Akshay Adiga To: skiboot@lists.ozlabs.org Date: Thu, 4 Jan 2018 16:58:06 +0530 X-Mailer: git-send-email 2.5.5 In-Reply-To: <1515065286-8656-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> References: <1515065286-8656-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18010411-0016-0000-0000-000005139AC9 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18010411-0017-0000-0000-0000284FE6E7 Message-Id: <1515065286-8656-10-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-01-04_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1801040159 Subject: [Skiboot] [PATCH 9/9] SLW: Add p9_stop_api calls for IMC X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Add p9_stop_api for EVENT_MASK and PDBAR scoms. These scoms are lost on wakeup from stop11. Signed-off-by: Akshay Adiga Reviewed-by: Madhavan Srinivasan --- hw/imc.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/hw/imc.c b/hw/imc.c index df29e6d4..5bc59b59 100644 --- a/hw/imc.c +++ b/hw/imc.c @@ -20,6 +20,7 @@ #include #include #include +#include /* * Nest IMC PMU names along with their bit values as represented in the @@ -633,6 +634,9 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu { struct cpu_thread *c = find_cpu_by_pir(cpu_pir); int port_id, phys_core_id; + struct proc_chip *chip = get_chip(c->chip_id); + int ret; + uint32_t scoms; switch (type) { case OPAL_IMC_COUNTERS_NEST: @@ -665,6 +669,8 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu * * HTM Scom: scom to enable counter data movement to memory. */ + + if (xscom_write(c->chip_id, XSCOM_ADDR_P9_EP(phys_core_id, pdbar_scom_index[port_id]), @@ -673,6 +679,40 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu return OPAL_HARDWARE; } + if (has_deep_states) { + if ((wakeup_engine_state == WAKEUP_ENGINE_PRESENT)) { + prlog(PR_INFO, "Configuring stopapi for IMC\n"); + scoms = XSCOM_ADDR_P9_EP(phys_core_id,pdbar_scom_index[port_id]); + ret = p9_stop_save_scom(( void *)chip->homer_base,scoms, + (u64)(CORE_IMC_PDBAR_MASK & addr), + P9_STOP_SCOM_REPLACE, + P9_STOP_SECTION_EQ_SCOM); + if ( ret ) { + prerror("IMC pdbar stopapi ret = %d, scoms = %x (core id = %x)\n", ret, scoms, phys_core_id); + if ( ret != STOP_SAVE_SCOM_ENTRY_UPDATE_FAILED ) + wakeup_engine_state = WAKEUP_ENGINE_FAILED; + else + prerror("SCOM entries are full\n"); + return OPAL_HARDWARE; + } + scoms = XSCOM_ADDR_P9_EC(phys_core_id,CORE_IMC_EVENT_MASK_ADDR); + ret = p9_stop_save_scom(( void *)chip->homer_base,scoms, + (u64)CORE_IMC_EVENT_MASK, P9_STOP_SCOM_REPLACE, + P9_STOP_SECTION_CORE_SCOM); + if ( ret ) { + prerror("IMC event_mask stopapi ret = %d, scoms = %x (core id = %x)\n", ret, scoms, phys_core_id); + if ( ret != STOP_SAVE_SCOM_ENTRY_UPDATE_FAILED ) + wakeup_engine_state = WAKEUP_ENGINE_FAILED; + else + prerror("SCOM entries are full\n"); + return OPAL_HARDWARE; + } + } else { + prerror("IMC: Wakeup engine in error state!"); + return OPAL_HARDWARE; + } + } + if (xscom_write(c->chip_id, XSCOM_ADDR_P9_EC(phys_core_id, CORE_IMC_EVENT_MASK_ADDR),