From patchwork Sat Nov 7 08:13:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396048 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=WbLmDeHM; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqmQ3rcQz9sTL for ; Sat, 7 Nov 2020 19:14:30 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727861AbgKGIO1 (ORCPT ); Sat, 7 Nov 2020 03:14:27 -0500 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:57208 "EHLO esa3.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727738AbgKGIO1 (ORCPT ); Sat, 7 Nov 2020 03:14:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1604736866; x=1636272866; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BqUviBNZqhcYKVjLlBRgbOvJ4y6AYLOsGaaxkI1tHXE=; b=WbLmDeHMpyuMAj5o6aC3ehE826nSoTpBtKiuqxJrh9QieKpt5VVYIGEM P5BxAyT0VYjpY33M4I5MIqPeLlvVeswKj5ZZU/78m+elcsvEyLNWmS/Fg YeEgYsYj7wYE7+NqI5xY0QhIp0Qwgzrkl5UJ9eDGc413EMqkcMrpKt+U9 Dl4smzilr+Oftroz10BHEE0mR/IEtO7YACeHKUyQBzQV6CPiLBHFpYly5 SSnbNa33q7Cnk70/yLwva9DVbYB7AqsmZpcnMl7jViHjG8WztzR4tpGCB ANdHtans1lhNlmwZFFfRlxjoSIgDITVVYUWQMXKNXwb+Q4xp9LbZ1hMqt A==; IronPort-SDR: n771JepbWCHDRkYyn8eHlO+UD9lV3sUgQrKoHBpkBj7/26yMD0PvmFHEJh7Fg1b3OZV5IZi+YM aLs3US7E1aU+D1JYFzLMYtkZVOt3O/P8z7PGAPQ6ZzKeuzBT+P9X2+FKFFj5YoJ8X+Gs4UchL1 Lbokr311ZW3yP/SY/KWdYRsEHqqQ6SHkBpjmeZc5gmlCSW/FA/fa5cm6n8IbJlEVKyqYZgGwCS G38Ie2i8IPv6HuQtPABDm/3OXTfjHlXFn8xnyZGWg8UhnepZ+Io5Qh0GymXFqeUy499JgMebav f1k= X-IronPort-AV: E=Sophos;i="5.77,459,1596470400"; d="scan'208";a="156564357" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 07 Nov 2020 16:14:26 +0800 IronPort-SDR: CViM24XLr0s7xjdVlrD3qV2x7d5ahqOLGtfj6NwpuToaZWpy/uS4bssZd4bEZH4Sw4QOHEW2QD TrToZ5NlkAX0ddU0K7J/VLq/MvsWO3HqJh+K91GoK4e8JtGdJyV39OtZxiCgHCsG8Z2ymEIioI No7d6V1X4d+d6ZHLx6uHdUcZ6unfMXJSyraKM3HE+i3E8W1hfph+3je7D9Ug5mBOg9CJW1z06x bQSephzJS3Y3ps7ruC1E2m3+03z05EkU6/zKAnQCbc6VN8UsXTtSlOqCMBr6ECkd8uEvZRthwz X4CIW2tNehmo14F7SN+Xdov2 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2020 23:59:17 -0800 IronPort-SDR: TmBsa7t3u9A7oOAAJ6Q9xlQB6YGNq7OndCgwgljnfYFrMAktTQLVE89+b449fpt9Mw7Xr+O3BY U9zIY390So2hnkbpscRoeheh9r+XlcJwEykzBi55qYwq0hTm5aoaNFV3b2Bc2yubJYy5jJJpZp jjMxRqB1Bc9lZQysDb6Pcr+5RH/AgWpwmT3QihEA/AcCs4BgEg5egeDogJqj32RBmxwcAmcke+ le/0xfq+Zm5V7QU1z0BA81wKCy48rumCkg4lGF2bMCmkGnS9pARlhm+ISDPatWjLyhaaTddJm4 7Y8= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:14:24 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 01/32] of: Fix property supplier parsing Date: Sat, 7 Nov 2020 17:13:49 +0900 Message-Id: <20201107081420.60325-2-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The DesignWare GPIO driver gpio-dwapb ("snps,dw-apb-gpio" or "apm,xgene-gpio-v2" compatible string) defines the property "snps,nr-gpios" for the user to specify the number of GPIOs available on a port. The "-gpios" suffix of this property name ends up being interpreted as a cell reference when properties are parsed in of_link_to_suppliers(), leading to error messages such as: OF: /soc/bus@50200000/gpio-controller@50200000/gpio-port@0: could not find phandle Fix this by manually defining a parse_gpios() function which ignores this property, skipping the search for the supplier and thus avoiding the device tree parsing error. Signed-off-by: Damien Le Moal --- drivers/of/property.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/of/property.c b/drivers/of/property.c index 408a7b5f06a9..d16111c0d6da 100644 --- a/drivers/of/property.c +++ b/drivers/of/property.c @@ -1308,7 +1308,6 @@ DEFINE_SIMPLE_PROP(pinctrl7, "pinctrl-7", NULL) DEFINE_SIMPLE_PROP(pinctrl8, "pinctrl-8", NULL) DEFINE_SUFFIX_PROP(regulators, "-supply", NULL) DEFINE_SUFFIX_PROP(gpio, "-gpio", "#gpio-cells") -DEFINE_SUFFIX_PROP(gpios, "-gpios", "#gpio-cells") static struct device_node *parse_iommu_maps(struct device_node *np, const char *prop_name, int index) @@ -1319,6 +1318,22 @@ static struct device_node *parse_iommu_maps(struct device_node *np, return of_parse_phandle(np, prop_name, (index * 4) + 1); } +static struct device_node *parse_gpios(struct device_node *np, + const char *prop_name, int index) +{ + /* + * Quirck for the DesignWare gpio-dwapb GPIO driver which defines + * the "snps,nr-gpios" property to indicate the total number of GPIOs + * available. As this conflict with "xx-gpios" reference properties, + * ignore it. + */ + if (strcmp(prop_name, "snps,nr-gpios") == 0) + return NULL; + + return parse_suffix_prop_cells(np, prop_name, index, + "-gpios", "#gpio-cells"); +} + static const struct supplier_bindings of_supplier_bindings[] = { { .parse_prop = parse_clocks, }, { .parse_prop = parse_interconnects, }, From patchwork Sat Nov 7 08:13:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396050 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=edEe2bsF; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqmR714Bz9sTD for ; Sat, 7 Nov 2020 19:14:31 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727924AbgKGIOa (ORCPT ); Sat, 7 Nov 2020 03:14:30 -0500 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:57208 "EHLO esa3.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727833AbgKGIOa (ORCPT ); Sat, 7 Nov 2020 03:14:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1604736869; x=1636272869; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fn84oUZ4BNOGbDuiZmuvLT5yqWitqbl3jm2qr9SJ9bI=; b=edEe2bsF7O2amA9pJV2t9HKaazSKyc6ecuGi9rkzU+Ra9TzEqo633C8h aiwZ2l56NqwtgRS0UYiZJr2uMQXXd+wGXp5hkgelJCVLbxZuvW7Qq+Yy3 b3+g/OjNeX7lUt2t72sdLxnOCammeBeWMAcPT161Ut+t8mmcjSR5zFBxZ N8Fx8Gs0a+3sGvs8zCqu/k+V0m6LgZGpQs5Ewivm1AzXk6Qjg/BqXhqAD tQ7/3JoK4MTA6LU1aeij1tEGbG+hJLmv39k6uqdroQpBDSihMUSxRUo3K pqKBiM85YbF+Y/3dvAj2KDY6kAV/oDE2xpvfX3a97lbagU5ohhw9HzBGW g==; IronPort-SDR: n6bxo9BMXs8tOxfB8F51PMEkY7MmWlGZYFrUCpTftKzpydzyiImc79nFe+e5lQDpqDR3SGel1w fVaIbV7cEpRfge3u+L2YlaeleZJWOZOaCMXvgzWWvLeRTmzeRTI2pF5DhWgeYbwNQ13KRCqxCd ACZ9r2g60Ju+yFvzMvAZv58g2hIqVjogw2f2UgIxsK10Fd4KVf6iEaSE1CGXAJAzjSSbgdNRuj y9t+SJSA6k6vZvNW/6SL8rBuJCP/dE4GBaQ06rJlX1aHEkBGL/XSe77mLsXBsCpag1GJnOAk18 Hms= X-IronPort-AV: E=Sophos;i="5.77,459,1596470400"; d="scan'208";a="156564358" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 07 Nov 2020 16:14:28 +0800 IronPort-SDR: ujIRzSqCMmY6Vmwv2MOOv+fBgnUaQgcAYsJbqzHzspAq2vU020ZbtPtreqerLQh2wbZBdPQO+K xzmm3OvYPQvsb1Q7VEvJSNGQ0OaCi/k4kGNAgr2p0e41g8qHEz/LSZVPqil9fCmya8aMBq2nbY J70YerqdU8B0Uxkk92CRwcA6/G0fE4CS3PTT+h5r944YcHX0kK3+4KF0Viz1/dbfR0/mqqrD9+ fyzY1kAOmxvyLF40XB+MdAFlGmjpH5i9klRDOLNkCiKaNYK65Czy8M9hPxf3+8EjY00nXKbQ7S 3VQMqe/2qqzVz9q/RgSyPgrZ Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2020 23:59:20 -0800 IronPort-SDR: Pjy+CvffHDUeaBXBpKnVSfEEU+ksIQROzGmmXPC5PVw7W7LyOuXXasEaoNM6f2hnV3YBECU9iq LnhkeIJzWOWBBFB12SV915WaNLKoDeKBQAlm7wE6ylqZDcZgeX7vg18qvU4TLQeIZea9IAf/N5 I/Z9Kje7pGer8lGFz4ym/VEXgpvR8GX9vS6cccuowARmvkDKv4pwcaXx6DsKcVZyvwULF4rSo7 tgkrLgReXXsDTAjMXLh8x2qgfjYOktPdjaRoIl6Ew59pEikbYpOPsXvP7jJ5M1w1uqP8qplYF+ tQY= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:14:27 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 02/32] spi: dw: Add support for 32-bits ctrlr0 layout Date: Sat, 7 Nov 2020 17:13:50 +0900 Message-Id: <20201107081420.60325-3-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Synopsis DesignWare DW_apb_ssi version 4 defines a 32-bit layout of the ctrlr0 register for SPI masters. The layout of ctrlr0 is: | 31 .. 23 | 22 .. 21 | 20 .. 16 | | other stuff | spi_frf | dfs_32 | | 15 .. 10 | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 | | other stuff | tmod | mode | frf | dfs | Th main difference of this layout with the 16-bits version is the data frame format field which resides in bits 16..20 instead of bits 3..0. Introduce the DW SPI capability flag DW_SPI_CAP_DFS_32 to let a platform signal that this layout is in use. Modify dw_spi_update_config() to test this capability flag to set the data frame format field at the correct register location. Suggested-by: Sean Anderson Signed-off-by: Damien Le Moal Reviewed-by: Sean Anderson --- drivers/spi/spi-dw-core.c | 8 ++++++-- drivers/spi/spi-dw.h | 9 +++++++++ 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 2e50cc0a9291..841c85247f01 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -311,8 +311,12 @@ void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, u32 speed_hz; u16 clk_div; - /* CTRLR0[ 4/3: 0] Data Frame Size */ - cr0 |= (cfg->dfs - 1); + if (!(dws->caps & DW_SPI_CAP_DFS_32)) + /* CTRLR0[ 4/3: 0] Data Frame Size */ + cr0 |= (cfg->dfs - 1); + else + /* CTRLR0[20: 16] Data Frame Size */ + cr0 |= (cfg->dfs - 1) << DWC_APB_CTRLR0_32_DFS_OFFSET; if (!(dws->caps & DW_SPI_CAP_DWC_SSI)) /* CTRLR0[ 9:8] Transfer Mode */ diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index faf40cb66498..48a11a51a407 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -9,6 +9,7 @@ #include #include #include +#include /* Register offsets */ #define DW_SPI_CTRLR0 0x00 @@ -72,6 +73,13 @@ #define DWC_SSI_CTRLR0_FRF_OFFSET 6 #define DWC_SSI_CTRLR0_DFS_OFFSET 0 +/* + * Bit fields in CTRLR0 for DWC_apb_ssi v4 32-bits ctrlr0. + * Based on DW_apb_ssi Databook v4.02a. + */ +#define DWC_APB_CTRLR0_32_DFS_OFFSET 16 +#define DWC_APB_CTRLR0_32_DFS_MASK GENMASK(20, 16) + /* * For Keem Bay, CTRLR0[31] is used to select controller mode. * 0: SSI is slave @@ -121,6 +129,7 @@ enum dw_ssi_type { #define DW_SPI_CAP_CS_OVERRIDE BIT(0) #define DW_SPI_CAP_KEEMBAY_MST BIT(1) #define DW_SPI_CAP_DWC_SSI BIT(2) +#define DW_SPI_CAP_DFS_32 BIT(3) /* Slave spi_transfer/spi_mem_op related */ struct dw_spi_cfg { From patchwork Sat Nov 7 08:13:51 2020 Content-Type: text/plain; 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07 Nov 2020 00:14:30 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 03/32] spi: dw: Fix driving MOSI low while recieving Date: Sat, 7 Nov 2020 17:13:51 +0900 Message-Id: <20201107081420.60325-4-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Fix for the Synopsis DesignWare SPI mmio driver taken from the work by Sean Anderson for the U-Boot project. Sean comments: The resting state of MOSI is high when nothing is driving it. If we drive it low while recieving, it looks like we are transmitting 0x00 instead of transmitting nothing. This can confuse slaves (like SD cards) which allow new commands to be sent over MOSI while they are returning data over MISO. The return of MOSI from 0 to 1 at the end of recieving a byte can look like a start bit and a transmission bit to an SD card. This will cause the card to become out-of-sync with the SPI device, as it thinks the device has already started transmitting two bytes of a new command. The mmc-spi driver will not detect the R1 response from the SD card, since it is sent too early, and offset by two bits. This patch fixes transfer errors when using SD cards with dw spi. Signed-off-by: Sean Anderson Signed-off-by: Damien Le Moal Reviewed-by: Sean Anderson --- drivers/spi/spi-dw-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 841c85247f01..c2ef1d8d46d5 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -137,7 +137,7 @@ static inline u32 rx_max(struct dw_spi *dws) static void dw_writer(struct dw_spi *dws) { u32 max = tx_max(dws); - u16 txw = 0; + u16 txw = 0xffff; while (max--) { if (dws->tx) { From patchwork Sat Nov 7 08:13:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396052 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=QshweGYe; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqmW5h4hz9sRR for ; Sat, 7 Nov 2020 19:14:35 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727970AbgKGIOf (ORCPT ); Sat, 7 Nov 2020 03:14:35 -0500 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:57208 "EHLO esa3.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727833AbgKGIOe (ORCPT ); Sat, 7 Nov 2020 03:14:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1604736874; x=1636272874; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aCvWQLDyaSFYntB4Womc0e0j3CRsIntIfbuSiFLr4hA=; b=QshweGYemJGcT+KkzovV5Pwo18pjWZTCW8g3u1CTCEdIBWJC7EJAcDdg DAImK8qOXPy+gVlzduQkc0P9q05LXvxzjG0oC91IP3dwDUOEfUMFo0wnv K+1WjPuBDcfsDLiRltK1GvqpTuFlqClk+5WjN3nWs+NuTMcwsiFAyMc8Z dYPIekGvygw5Rq73diPfYPDa3bJQ+XpIXgOyWRXZ1c4OpWgOeFrHudKUh uXmFqJDDaKlcm65v2/liCIjD6yEbhvClZe8iFGkfiBfZd08yEJJqo6r7G 1jH5hOzqc0YmU3jX9fwgBgTufIYiIbsmYFOC5hnM2dLWrBRH0rwDnyZeK Q==; IronPort-SDR: a5Xd+Se+25c2QTbWar5nszM6hEg8bzpP7QZXiBmHiIX8kiPd3tTKK8VILkOLnvRC6WH7Z9Ojdb /T37LvV7XUa5v2L3OD+Ubs/1cKoWX3q74tTHcmeCaGxRwFXrB2EnNPOygoTlByNO021/t2gOH5 QWuksXJOAZ+pFHjb2Rz80Flm+ZVkAOVCiKOuILn/x5aozS+OJni/exvdYmZxo5e1V6TrBbAkbo 2dkqE1fMksvzGrA8JcF3LVYdv8OMgjjHIof13xLct5pjoZPchIoBgJ5hOImAvKntDhkBaxbNfg m7A= X-IronPort-AV: E=Sophos;i="5.77,459,1596470400"; d="scan'208";a="156564364" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 07 Nov 2020 16:14:34 +0800 IronPort-SDR: KAErByTJHniAColHyFeX8orwtASriU/MKROjO/z33lDVn5RRdECdUm4qmn1NXcgK4VTu/G7TPV 1DrFiinJCWe3OhCewJxavf7T+KqkyjRvANgYo93eR8u2SRzOAo2UhU18k1URgE46BBGzbaPHYj rsqIebwLqSTBxA0UyI6xJj5Hut/Bsavxt2wCUwPACNwu+Z2VE2OXfZR8XsPbLNDes/tzizo3XR jCR1Hob+BX5D06OIxeN4AHF8nDyuCoFIt+Jn9yHO8Q0tcm9aLQywPN5i1N7fYzAy+zmZQOC/DX qcA3xjArOwwbYAhEer/54hkA Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2020 23:59:25 -0800 IronPort-SDR: xnMAOU5B9k8aXLtf1hpdfpBLHr6sZSOKvHHBazK2i2wFWcv7QRgwZDB5yRurYFkmsx6Ckwu05/ WIME6Tf0b8tFqPDMJp7/bOJ2eMa/MWFmwTtlEgPFNFta0wWOqkFLFw+s9KUG4tiHjNQjPzfJzZ /Y+aqMbroxYK3YbaE0zZbN7MU/4qG8l2hqxL0GzsGZG88bgSljIGv2IlEe2BTxWw+VOgklowg5 t4NjYuQ2n8DxVap/Y0ZPa9osrcuQ405tsfj9NtcR3I/JsJDarohMqN/7Ix0DY0jcQmIqLh7HX+ nZg= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:14:32 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 04/32] spi: dw: Introduce polling device tree property Date: Sat, 7 Nov 2020 17:13:52 +0900 Message-Id: <20201107081420.60325-5-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org With boards that have slow interrupts context switch, and a fast device connected to a spi master, e.g. an SD card through mmc-spi, using dw_spi_poll_transfer() intead of the regular interrupt based dw_spi_transfer_handler() function is more efficient and can avoid a lot of RX FIFO overflow errors while keeping the device SPI frequency reasonnably high (for speed). Introduce the "polling" device tree property to allow requesting polled processing of transfer depending on the connected device while keeping the spi master interrupts property unschanged. E.g. device trees such as: Generic soc.dtsi dts: spi0: spi@53000000 { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dw-apb-ssi"; reg = <0x53000000 0x100>; interrupts = <2>; ... } Board specific dts: ... &spi0 { polling; status = "okay"; slot@0 { compatible = "mmc-spi-slot"; reg = <0>; voltage-ranges = <3300 3300>; spi-max-frequency = <4000000>; }; } will result in using polled transfers for the SD card while other boards using spi0 for different peripherals can use interrupt based transfers without needing to change the generic base soc dts. Signed-off-by: Damien Le Moal --- drivers/spi/spi-dw-mmio.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index d0cc5bf4fa4e..3f1bc384cb45 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -20,6 +20,7 @@ #include #include #include +#include #include "spi-dw.h" @@ -246,9 +247,13 @@ static int dw_spi_mmio_probe(struct platform_device *pdev) dws->paddr = mem->start; - dws->irq = platform_get_irq(pdev, 0); - if (dws->irq < 0) - return dws->irq; /* -ENXIO */ + if (device_property_read_bool(&pdev->dev, "polling")) { + dws->irq = IRQ_NOTCONNECTED; + } else { + dws->irq = platform_get_irq(pdev, 0); + if (dws->irq < 0) + return dws->irq; /* -ENXIO */ + } dwsmmio->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(dwsmmio->clk)) From patchwork Sat Nov 7 08:13:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396053 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=ioChVHyc; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqmZ4m17z9sRR for ; Sat, 7 Nov 2020 19:14:38 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727833AbgKGIOi (ORCPT ); Sat, 7 Nov 2020 03:14:38 -0500 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:57208 "EHLO esa3.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727810AbgKGIOi (ORCPT ); Sat, 7 Nov 2020 03:14:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1604736877; x=1636272877; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6b+MfY7Lnw6uLwvcAlOQrQcVcVnJvNY26Ca7SXPyL/Q=; b=ioChVHyc7hSArtXZbt9ah29uDuB+BbTtOKe7jrQto0USnRsvOhwZlb47 r+FT8gH8x5RfsXW6PXHrv+bSyPgfC23zHRaZtBz+JGG4f4M9UPaU8Osw7 aKAmIVPpWj3dBY/yveKvkTJq/q+ImKJ/5eqzZZuI0ePvCCeKqvAFjLSXS BbUeA+VVPIzGQSg74IGGULogi7DgnayjqDG5Ji7+WRQgvKPa+Hhiw/mSW fBn1B2UfyvJPV3G9uVHaTxUYuTEpWBCIbjsNdGQ3Rr7Rrae5Z/HY/1jX8 9X+T3i1n+RT1Yzfqe5rwmF1x3KvUDqvlGN66PptxsB4YiHUf1YRMBekVg A==; IronPort-SDR: TAn5cp3r5TAU4Oto8TkIMU+ST3Z49BoyXXJzjYo4l2iN4hrSVl8wtGPS6z4C23YWBOKRTuS9tN kbocRFoNmPPGLiMEDuowHz2Q5YLiqEB81uTqsB7OLy+Y2e70c1eNvg7JUrIA9GcjkPgsHB20Vq CGu+79NkmvwNr3onpglZSGQhPhGLNTvcodtxAAwbiNgCe2cEScdIPMpmes2enD8eGr6d+ggsSm QNbeTMdtaE0UL1kzQljjQaOwziytCBkbhea1wAZRbtffKjl72lsmFFqyNvs8fQpGnJVfL47PDx S+E= X-IronPort-AV: E=Sophos;i="5.77,459,1596470400"; d="scan'208";a="156564367" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 07 Nov 2020 16:14:37 +0800 IronPort-SDR: OJ2ye+09Fu47BaM8gl+/I/TCLcSl/QL8cB5d98MKKUk7aebTyytPcVL8cBUrt073p7vw/EprZ2 pDN2c2aCWDuaxwLftiWDlUyINoDrKPJkL1JKvuXzU0aEjd1qFbHrsHa+4ccacFgjDTauxjCuDc EwtJYWlRt8Ksa5mQjdKtdZoh3XcdaU+xiI9ABi6CTY+0qLNR3zrEGUXzveXjqCI5VqwNR9t0mB PguDwiBMUxW8R+SyI/ffG5p61KsPgkY76SYUZnwpH29rS09KFUZQRYX6ZqODcz8EUyRzDoHK+Z l9dcAq+MSwH/SA5/V8dGlrVY Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2020 23:59:28 -0800 IronPort-SDR: NSr+fi+441D/Y1RoTNH84IS+7KXzRlrA3vPMRV0+N1CX0PR26ZSjF+sMYjPwDRUPIEcZkz2Rbf jOMvNeSaoWy5oTVBlfqzCSFG+qD34T8/i7rhLqC5WioI2B6JKCjiAldHzLUdDiP+K0dRgmzVR5 G7hWuCLS6zsopefhObrpOae58CT5kaAQcUMZlbU/y2+dGZTsv1TbDx3jfSG5IMmNBjkZE5nMhn hSsR1Y1ir8AlX6JL+I/oSvG69ZIVrsLipi/Dyaa0esLFacgkelsNRm8M5rORI1GwilWaJfkd0d Ex8= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:14:35 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 05/32] spi: dw: Introduce DW_SPI_CAP_POLL_NODELAY Date: Sat, 7 Nov 2020 17:13:53 +0900 Message-Id: <20201107081420.60325-6-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On slow systems, i.e. systems with a slow CPU resulting in slow context switches, calling spi_delay_exec() when executing polled transfers using dw_spi_poll_transfer() can lead to RX FIFO overflows. Allow platforms to opt out of delayed polling by introducing the DW_SPI_CAP_POLL_NODELAY DW SPI capability flag to disable the execution of spi_delay_exec() in dw_spi_poll_transfer(). Signed-off-by: Damien Le Moal --- drivers/spi/spi-dw-core.c | 12 ++++++++---- drivers/spi/spi-dw.h | 1 + 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index c2ef1d8d46d5..16a6fd569145 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -385,14 +385,18 @@ static int dw_spi_poll_transfer(struct dw_spi *dws, u16 nbits; int ret; - delay.unit = SPI_DELAY_UNIT_SCK; - nbits = dws->n_bytes * BITS_PER_BYTE; + if (!(dws->caps & DW_SPI_CAP_POLL_NODELAY)) { + delay.unit = SPI_DELAY_UNIT_SCK; + nbits = dws->n_bytes * BITS_PER_BYTE; + } do { dw_writer(dws); - delay.value = nbits * (dws->rx_len - dws->tx_len); - spi_delay_exec(&delay, transfer); + if (!(dws->caps & DW_SPI_CAP_POLL_NODELAY)) { + delay.value = nbits * (dws->rx_len - dws->tx_len); + spi_delay_exec(&delay, transfer); + } dw_reader(dws); diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 48a11a51a407..25f6372b993a 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -130,6 +130,7 @@ enum dw_ssi_type { #define DW_SPI_CAP_KEEMBAY_MST BIT(1) #define DW_SPI_CAP_DWC_SSI BIT(2) #define DW_SPI_CAP_DFS_32 BIT(3) +#define DW_SPI_CAP_POLL_NODELAY BIT(4) /* Slave spi_transfer/spi_mem_op related */ struct dw_spi_cfg { From patchwork Sat Nov 7 08:13:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396054 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=AlfKQSOB; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqmd41g6z9sRR for ; Sat, 7 Nov 2020 19:14:41 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727973AbgKGIOl (ORCPT ); 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07 Nov 2020 00:14:38 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 06/32] spi: dw: Add support for the Kendryte K210 SoC Date: Sat, 7 Nov 2020 17:13:54 +0900 Message-Id: <20201107081420.60325-7-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The DW SPI master of the Kendryte K210 RISC-V SoC uses the 32-bits ctrlr0 register format. This SoC is also quite slow and gets significant SD card performance improvements from using no-delay polled transfers. Add the dw_spi_k210_init() function tied to the "canaan,kendryte-k210-spi" compatible string to set the DW_SPI_CAP_DFS_32 and DW_SPI_CAP_POLL_NODELAY DW SPI capability fields for this SoC. Signed-off-by: Damien Le Moal --- drivers/spi/spi-dw-mmio.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 3f1bc384cb45..a00def6c5b39 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -223,6 +223,14 @@ static int dw_spi_keembay_init(struct platform_device *pdev, return 0; } +static int dw_spi_k210_init(struct platform_device *pdev, + struct dw_spi_mmio *dwsmmio) +{ + dwsmmio->dws.caps = DW_SPI_CAP_DFS_32 | DW_SPI_CAP_POLL_NODELAY; + + return 0; +} + static int dw_spi_mmio_probe(struct platform_device *pdev) { int (*init_func)(struct platform_device *pdev, @@ -340,6 +348,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = { { .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_dwc_ssi_init}, { .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init}, { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init}, + { .compatible = "canaan,kendryte-k210-spi", .data = dw_spi_k210_init}, { /* end of table */} }; MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match); From patchwork Sat Nov 7 08:13:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396055 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=qM1/olAY; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqmg6TGJz9sRR for ; Sat, 7 Nov 2020 19:14:43 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728007AbgKGIOn (ORCPT ); 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07 Nov 2020 00:14:40 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 07/32] dt-bindings: Update DW SPI device tree bindings Date: Sat, 7 Nov 2020 17:13:55 +0900 Message-Id: <20201107081420.60325-8-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Document the polling propetry which is used to force the use of polled transfers, ignoring the device interrupt property. Signed-off-by: Damien Le Moal --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index 99ed9b416e94..890a160a253f 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -120,6 +120,11 @@ properties: This value will be used if the property is not explicitly defined for a SPI slave device. See below. + polling: + default: false + description: Ignore the device interrupt and force the use of polled + transfers. + patternProperties: "^.*@[0-9a-f]+$": type: object From patchwork Sat Nov 7 08:13:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396057 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=b+uoicjH; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqmk6ygVz9sRR for ; Sat, 7 Nov 2020 19:14:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728015AbgKGIOq (ORCPT ); Sat, 7 Nov 2020 03:14:46 -0500 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:57208 "EHLO esa3.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727801AbgKGIOp (ORCPT ); Sat, 7 Nov 2020 03:14:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1604736885; x=1636272885; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=I9FRj9UJZUXbJ36h9NtK7sWhZkQHQ9GoiFFCz8CrFtg=; b=b+uoicjH29u5OVXaeo3l/tlr0xmDcIOWiZCU3aNdSPWCdYzmOmJxzgsK w+p9S1012QEhpXnivYO7q7ghPnjPbNDuIbDt+dwgBg536ja5wFH0i4UIP CBEjs7cYKO4e/Z5jf8rdofngdmiuLvO/2ZgP846fuy2kRjPanbBB3WUPt d56zAZVw/BNhaYJN4mJDYXm7fsNujc94A36D2cVHtbqnpy7QkaJqzGUbE W7NzGqvSrQB/REJCwiqAQJoqnHMuAezetFQ1XUHDRGZXnXKqyFdnQtcT3 U9I2PsZ1pXySPb8k1spTN3pWX9Sus/8YQP1KpZ6Q7Ih1+UyqcDtQlVLsH A==; IronPort-SDR: gd50EAdFdMzA3AZBJvkyIS39FIpmxVYTyBLTTK6GHwvIVnIBIPnq4xMCooUpS2eGWoKICk1Qhg yMoUE5d21Ovc0XXqu76EABj/Q+6uvqsNeDPfTaOznusLtmz/kT0v6XgTzVZQ6AE2Igibp6geMG pwpN3TbCazuuz87pclQX71PEFcgKyQ41UtzhlSJX8DDoqBWMnobryIr4kuIgcGsib5HTbG73JO 6dCxHYZiaJudvGWEqcQV97d+o0NCzqDaj57YiRzkScOaPeak2MuUioXnHAcFRLkVZhewwXjSHD 45U= X-IronPort-AV: E=Sophos;i="5.77,459,1596470400"; d="scan'208";a="156564374" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 07 Nov 2020 16:14:44 +0800 IronPort-SDR: MCX35SrBKoKEGNTKNmw3PWR7Mi/OMf/CVEw0WqyuKI/L6phDVd5afpgAxkKl0QcSIL2dRSwlX/ GXGgxgiUWtvRXFszhbRiE0zSoENRjsOw+PVeZ2ONJipPuJnIXvmY+tCuCp18qTLCUQ4/nq+yfi gUr/K31QI08cfHWQYdq7uGVtKUpDn66A7k6vxWES8TWehRNsBAjAUz8dsW2x0AkBAYVtOeJ71N O1/Yq+SHGUrDa06Ae4QzYKpA1vECHzK86a8iUPIQZ0oMhmmLHytgMOGqGH+8Mwb3+vvWTIaz1A NM7UDI6LurVXOWecSoTMDGVN Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2020 23:59:36 -0800 IronPort-SDR: bsAAbPxhXeDIy1nlJsSKE+tRuqxbWo1/7u+arvpKA2lAET/QNMdr3zvocxX2jbfsbYlXs9bvEO Fm7DCw0P2OdyDDyO2ze8poOfGV6zbZxsnf4uvzPO/I77VGMirVUC/ruEYCZ21viQipiAvKltd4 CSNJIPeYmHIXmXrY4IlkHjE2ulrcp5b1uv41XbSr3JQWSRW+Od422ooQBDAE/kIy/Bhs4TWrfo xOo9kqfar///MEnTLDERFeB6QRkOV51jFB0kQjo3ADnzaiHY9oD9YsBVThclN7rcXFYmh/0J5J MZs= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:14:43 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 08/32] riscv: Fix kernel time_init() Date: Sat, 7 Nov 2020 17:13:56 +0900 Message-Id: <20201107081420.60325-9-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org If of_clk_init() is not called in time_init(), clock providers defined in the system device tree are not initialized, resulting in failures for other devices to initialize due to missing clocks. Similarly to other architectures and to the default kernel time_init() implementation, call of_clk_init() before executing timer_probe() in time_init(). Signed-off-by: Damien Le Moal Reviewed-by: Atish Patra --- arch/riscv/kernel/time.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/kernel/time.c b/arch/riscv/kernel/time.c index 4d3a1048ad8b..8a5cf99c0776 100644 --- a/arch/riscv/kernel/time.c +++ b/arch/riscv/kernel/time.c @@ -4,6 +4,7 @@ * Copyright (C) 2017 SiFive */ +#include #include #include #include @@ -24,6 +25,8 @@ void __init time_init(void) riscv_timebase = prop; lpj_fine = riscv_timebase / HZ; + + of_clk_init(NULL); timer_probe(); } From patchwork Sat Nov 7 08:13:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396058 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=UfQByc8Z; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqmn44grz9sTL for ; Sat, 7 Nov 2020 19:14:49 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728034AbgKGIOs (ORCPT ); Sat, 7 Nov 2020 03:14:48 -0500 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:57208 "EHLO esa3.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727801AbgKGIOs (ORCPT ); Sat, 7 Nov 2020 03:14:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1604736887; x=1636272887; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bzB7t56mVd9ZzoA3Nl5yo11GGSsnbn0Toc+QuUpGUBE=; b=UfQByc8Zupo+8vcmRRqHJqTakf3V/wKT7AWMy0HXW+IjE6WVW/XITGdB +oPWA1tB19jtV6DTAf1C2b67wbbjh4E+vLV87bxKaBuA+8cWujXaSEBSW 4vWWTOdyvutepavCD5+3bS3yo13+lbi9jI5iigbbOThGdpH5b57MW4Xkc 6UNRtkoVz4/Xwvqe6RzErIiolkno3gzfY2lwWTrn6bBz0Zf3QAKqs9Kn1 3+YT01orQLXuTF6Zg4M3tSN0vzxHNnwFumaPCA4+RHZKphCHwlE4BYodc zg7HvQefRLBZFIaPMgafKo3/tp4XdOmFiAsfFNtowYQ+OifX5mOO3kahT w==; IronPort-SDR: ZSD+opTt/gbxzFX9IZ84mAJCitX6u2VwvuVJVSiWWz3tcrXv4fMO9WWZNgQecMqk7DlHdZPhiu jp+vLH4ed8Cf9FLQjq3WZvWNLIrNWN/eYX0FcM8okojngnXMdxb2PxGE9w7xymAuhGagYUQLaM eqopja16OlGP0ILUrRSvUn2ZkLJscZZpXHu0zVgn6dcUnMm054ZtZI1kJTBBf/IPry48/d2CFv kh0eWA6AShVVrqNdidrRwS7Uxfcq1x59hkl2jkvlbY2N0ixJ96P+XAs966p1dhu7pDTsBaeUSu FeE= X-IronPort-AV: E=Sophos;i="5.77,459,1596470400"; d="scan'208";a="156564376" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 07 Nov 2020 16:14:47 +0800 IronPort-SDR: JrSgH3YALJZ3onO3oco2ABbQTOh1jAf5pZkuhmq8OUXKmFuVlztkeN33YCsBV7wzmKc9gFwNrp syq3UWb7pYp9L1i64A6d6mixKJXXN32AOCO37p2n98SSyNV/6WEumKrmzS4MRsS4ZFc4pMuOeS lrb7h+Ino8LZ0AsF+eDkZm5VLCBHFmoJ0tp3GoB0aVJ0hm0ZlKyz3bFw6dyfME2RnAiLem/5wH Do2E38B5APZOhKCAwy6nT8PtomQq48/BTRxyXDttm6vD8uUA12VH/1SCkNWLw+/Wnzlhcv0mws 7pF2VFwDUf8LxSmRlrSUM4gT Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2020 23:59:38 -0800 IronPort-SDR: B0Mfujx6UxJh3cJWVh4zNTPfCD5sD9aEoBo4eyW2xNfgr34VaQ5gkGoFqmf+P7pvJpzQzfYCkt UuKEt7LhYCIlvZTWCxOgx0ATflrP+6cTrv/tlkSOAtdqHaP7ofdeAFq4fWIyY9lPVOdT4LEcHE ZD7Lyu1Vj0LqoYB5mXvedUwpL+ZgnAIa7ecZwl0rikOIwXwhQjeUnJ5IiLAarLSHNERvOuKdwI 90nGHP04/rx0PDIZHjR1Zv+LrvNLgMqgoox+UBMnA50cZf2AumzqZuYGOpETAyMAlRNLeRiSV1 +14= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:14:46 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 09/32] riscv: Fix SiFive gpio probe Date: Sat, 7 Nov 2020 17:13:57 +0900 Message-Id: <20201107081420.60325-10-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Fix the check on the number of IRQs to allow up to the maximum (32) instead of only the maximum minus one. Signed-off-by: Damien Le Moal --- drivers/gpio/gpio-sifive.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-sifive.c b/drivers/gpio/gpio-sifive.c index c54dd08f2cbf..d5eb9ca11901 100644 --- a/drivers/gpio/gpio-sifive.c +++ b/drivers/gpio/gpio-sifive.c @@ -183,7 +183,7 @@ static int sifive_gpio_probe(struct platform_device *pdev) return PTR_ERR(chip->regs); ngpio = of_irq_count(node); - if (ngpio >= SIFIVE_GPIO_MAX) { + if (ngpio > SIFIVE_GPIO_MAX) { dev_err(dev, "Too many GPIO interrupts (max=%d)\n", SIFIVE_GPIO_MAX); return -ENXIO; From patchwork Sat Nov 7 08:13:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396059 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=erbEhKUZ; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqmq6PBpz9sSs for ; Sat, 7 Nov 2020 19:14:51 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728042AbgKGIOv (ORCPT ); Sat, 7 Nov 2020 03:14:51 -0500 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:57208 "EHLO esa3.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727801AbgKGIOv (ORCPT ); Sat, 7 Nov 2020 03:14:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1604736890; x=1636272890; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ah0+1mEnJdX05Q2mVPorPQhcLW5wBEGXXNi04bnk03g=; b=erbEhKUZuhNnxcALIHqNYaH8/th/3eoH8yHrE04w8VTjO0lvhyqrQ+ZZ XJToDacwc4NumFUN/8D2I10CcfvwFowjPnPOphDns3X1M55b4k53YxsYN 8diPsts/3W9Vlrtfq8AcdaKqXN9f6v/f+0NaSqjMja4RyGF35MOK4C+Kz wu+MU3229MaU8QNYSP1/gC3lfw0V+8T75LfOXbAXQQeNwVkr316RtcyJw 5oVrKkIWJovZ51zccZoeK7ltKxhQs30PyJnNHhSW/1R4C+ei129VoThpb gGvCsRgyp2T5idpc5Tx5s1d3Ou8RXOBrU0a4dUmU1a5PnAGs6m3cXtIiH A==; IronPort-SDR: IFysDHtVX2jf16l8p13e+9+dIPAk+iItYcov09T6w4lLZ6Ju50Ewez81sOHIQPN1sNwaSYcgrK pyRkyntS/4c+7Nmtqwjvr8sI5uEkvGznAWI02NK10BOKAkS/5XutwOTFRmEzQmzAXyn9W0cfBF QtaN+HOIOsSWNe6u3HXkA0InnnusrPQ5ODcTjwc9L+joR1+VsKRCNoqtz1n8gBmIDHI7+5jJKs Q+wm1WVKaylhMqUNwnwaN+vW3GzGs6upIlal16hwgmFKHMz9FE65UtHefaWx6g01x1a4rTXzSa pF0= X-IronPort-AV: E=Sophos;i="5.77,459,1596470400"; d="scan'208";a="156564377" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 07 Nov 2020 16:14:50 +0800 IronPort-SDR: P/sH90I0KIO2A9hcbGtFc5JHamLFGVXmQipofegbBQbvTwXlu36pmbbq/ZHIYWVINlqU5Z7v2Q SAo0EL1tEIKuUmFuggLIEU7Bc3Wx7qQAlbCTJU4ykb7RAdPsboHJVOCDt+21D1UVArtRJsND7J i3M1pwf8exiLuhbxKMJdPNmVBsNBMMZVuQBDXZ/Qat/MPMAFmn5NLeNKQbLLaNoSwK4rmUWInc DPZ6uniB7IS8KQ0w3awAHu49kNkk3dVWD4xAi6sxDDypd0w1hy912oOlw5n8s79WNvIame98mW Mocm6oL9DmzmraYvFwK3DRDx Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2020 23:59:41 -0800 IronPort-SDR: tCjB9lyCTe615202gVJFGQD2Y1XtiyOayZe8caLQvPWA5qCK2cJsOQjBAV+Wsi0GvUv4r7vhmG SPV1z3bYORy+DveiSCH9wrzxwQIBzgmN08HeP9OxANTgZQmwqqO53jsrT8+P+dYIvI+SfglE1/ xD4scmp5HEwA98e3HKCYS5E9BjH3hLhT+KvW4IaAOFJ5ObdvKk1u5QHnov7/bjiKf80JCD+yrd ZEMVDU+97kwgqPUh5eDk9o54PFRbXzdnhR4cgHQ6qXMRqnQzIn6N4rxzBABsB3xqoTTDGUpLeM tOI= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:14:48 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 10/32] riscv: Fix sifive serial driver Date: Sat, 7 Nov 2020 17:13:58 +0900 Message-Id: <20201107081420.60325-11-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Setup the port uartclk in sifive_serial_probe() so that the base baud rate is correctly printed during device probe instead of always showing "0". I.e. the probe message is changed from 38000000.serial: ttySIF0 at MMIO 0x38000000 (irq = 1, base_baud = 0) is a SiFive UART v0 to the correct: 38000000.serial: ttySIF0 at MMIO 0x38000000 (irq = 1, base_baud = 115200) is a SiFive UART v0 Signed-off-by: Damien Le Moal --- drivers/tty/serial/sifive.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/tty/serial/sifive.c b/drivers/tty/serial/sifive.c index 13eadcb8aec4..214bf3086c68 100644 --- a/drivers/tty/serial/sifive.c +++ b/drivers/tty/serial/sifive.c @@ -999,6 +999,7 @@ static int sifive_serial_probe(struct platform_device *pdev) /* Set up clock divider */ ssp->clkin_rate = clk_get_rate(ssp->clk); ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE; + ssp->port.uartclk = ssp->baud_rate * 16; __ssp_update_div(ssp); platform_set_drvdata(pdev, ssp); From patchwork Sat Nov 7 08:13:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396060 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=AvNRiFUi; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqmv3Csfz9sSs for ; Sat, 7 Nov 2020 19:14:55 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728053AbgKGIOy (ORCPT ); Sat, 7 Nov 2020 03:14:54 -0500 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:57208 "EHLO esa3.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727801AbgKGIOy (ORCPT ); Sat, 7 Nov 2020 03:14:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; 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07 Nov 2020 16:14:53 +0800 IronPort-SDR: DlrFS8IZ00iaxHHXk2zhRAyNoaJnndD2Yq+UKdGOWZuQ6boj3VYnXnhQv+pNawar+QnGe+pvQ6 XD0yiK3wCFTwK4e64mXcGy+ewY2ThGnqsPCxGFpk/HCn8YkGBuBsGbwbah4O5ErTCUlBzw/7R/ aBYmSuvXNOD0zGZuim9LJOB00uEhJ9iLwwgoSqjIr964gIFAttGzdO97DP3SfM7MM+z4xnH2x9 ylpve1luyKkS0ACZYO5OvSfw/Wz53tAk4CH2+Jt2GvuK8WrIOlchwND8493tYvXLBD1P3AwL5O X1NQ44MUmh5wBcTGEJBw3drj Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2020 23:59:44 -0800 IronPort-SDR: fT23JgunU722jRduFvljIERP725lvkEaBUxXqos8amCUHUNMsIduVaQQXwkSxtHAaC+rJkBUv8 IvTev3D8aeVnB4NxdarvBXucISWuB6ZyoMelBOI2ZIojCbT8rhZKjGN7NqrhDY08NzgXuj1dZD BfR5vSeXRdYSz4gjqPEL39VpTt4d3XqZT2b6fs4l9qpgWZna7a0KhuWToPbyg9xfVGxKP4wwS6 IqL+0nQc6LEjj7EJY7/K0WPS4cmWaTD7UVxP2dOVC1SbZZb0hVOVPGcXAUU1iB90e3fxudnB3D vtg= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:14:51 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 11/32] riscv: Enable interrupts during syscalls with M-Mode Date: Sat, 7 Nov 2020 17:13:59 +0900 Message-Id: <20201107081420.60325-12-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org When running is M-Mode (no MMU config), MPIE does not get set. This results in all syscalls being executed with interrupts disabled as handle_exception never sets SR_IE as it always sees SR_PIE being cleared. Fix this by always force enabling interrupts in handle_syscall when CONFIG_RISCV_M_MODE is enabled. Signed-off-by: Damien Le Moal --- arch/riscv/kernel/entry.S | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 524d918f3601..080eb8d78589 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -155,6 +155,15 @@ skip_context_tracking: tail do_trap_unknown handle_syscall: +#ifdef CONFIG_RISCV_M_MODE + /* + * When running is M-Mode (no MMU config), MPIE does not get set. + * As a result, we need to force enable interrupts here because + * handle_exception did not do set SR_IE as it always sees SR_PIE + * being cleared. + */ + csrs CSR_STATUS, SR_IE +#endif #if defined(CONFIG_TRACE_IRQFLAGS) || defined(CONFIG_CONTEXT_TRACKING) /* Recover a0 - a7 for system calls */ REG_L a0, PT_A0(sp) From patchwork Sat Nov 7 08:14:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396061 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=O5gdys3V; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqmx2qzfz9sRR for ; Sat, 7 Nov 2020 19:14:57 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728069AbgKGIO4 (ORCPT ); Sat, 7 Nov 2020 03:14:56 -0500 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:57208 "EHLO esa3.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727801AbgKGIO4 (ORCPT ); Sat, 7 Nov 2020 03:14:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; 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07 Nov 2020 16:14:55 +0800 IronPort-SDR: eHB44qJE5SSb0XdQ3hx6AYXToNqzcYHyj2dsRy1RT3q2tmfVAq+EBJPn5dNP6yIjDYRrrPAr3l TwcWBGD7GYrgpMQafipgAuaWFn42LqQwQz/qH9fCzPxIlPj85hIU/MhnedHs8fI1Sn/9xzEdsn 7j1xdY9XMIcMjC9yr5EUtP9p4J32KuRp26SVr6sQhNsdH8if7df+apL4ZuKXi+Yv9dLzvTOyOQ NVjw1fhhIVvpS6HnJ7ToKJfvA4Xm+8g3zFV+kuvaKaY0hETQzJ0lG1DZ/a5KfeaUtZJmdQgU4j ZqYeNPs4laTlSyaqCxEZ2vTk Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2020 23:59:46 -0800 IronPort-SDR: cDAYLC/Y3uvh8Vg5Uw/U3omgYHlJ5tgAt5xkJ+ZX3vNx/zsmJdc7c8iZKsQEVC56BhIw0O2+mu CUe1wghA6cqE9JUn7x46JYF4ba2yB4PZTwKhnvYYeyQ6FsYtzu4HM7uY+6w/gVTyHCZVEj+Vtz rJl2S0ANRS5XszYtSghrto0CMCO3RnmSogqkj8XGq6wSLeIfsfQXLhfHCR8MFhp8n+i8akiwtp GFd+3ctJ2PwrEMeMCpTKE3Ov1EoV0oF4ssbXK5nOmLxCGs5RscS1lhj+8aEp1DYia90vdaLsDS g4k= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:14:54 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 12/32] riscv: Automatically select sysctl config options Date: Sat, 7 Nov 2020 17:14:00 +0900 Message-Id: <20201107081420.60325-13-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org With the device tree update for the Kendryte K210 SoC, most peripherals are now defined under one of 3 advanced power buses (apb0, apb1 and apb2) compatible with the simple-pm-bus driver. The sysctl SoC device is defined as a syscon/simple-mfd device. Enable the configuration options PM, SIMPLE_PM_BUS, SYSCON and MFD_SYSCON to enable drivers for these device tree nodes. Signed-off-by: Damien Le Moal --- arch/riscv/Kconfig.socs | 1 + drivers/soc/Kconfig | 2 +- drivers/soc/kendryte/Kconfig | 19 +++++++------------ drivers/soc/kendryte/Makefile | 2 +- 4 files changed, 10 insertions(+), 14 deletions(-) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 8a55f6156661..e724fddc44ba 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -29,6 +29,7 @@ config SOC_KENDRYTE select SERIAL_SIFIVE if TTY select SERIAL_SIFIVE_CONSOLE if TTY select SIFIVE_PLIC + select SOC_K210 help This enables support for Kendryte K210 SoC platform hardware. diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 425ab6f7e375..f511cad87a0e 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -9,6 +9,7 @@ source "drivers/soc/bcm/Kconfig" source "drivers/soc/fsl/Kconfig" source "drivers/soc/imx/Kconfig" source "drivers/soc/ixp4xx/Kconfig" +source "drivers/soc/kendryte/Kconfig" source "drivers/soc/mediatek/Kconfig" source "drivers/soc/qcom/Kconfig" source "drivers/soc/renesas/Kconfig" @@ -22,6 +23,5 @@ source "drivers/soc/ux500/Kconfig" source "drivers/soc/versatile/Kconfig" source "drivers/soc/xilinx/Kconfig" source "drivers/soc/zte/Kconfig" -source "drivers/soc/kendryte/Kconfig" endmenu diff --git a/drivers/soc/kendryte/Kconfig b/drivers/soc/kendryte/Kconfig index 49785b1b0217..11579139ede6 100644 --- a/drivers/soc/kendryte/Kconfig +++ b/drivers/soc/kendryte/Kconfig @@ -1,14 +1,9 @@ # SPDX-License-Identifier: GPL-2.0 -if SOC_KENDRYTE - -config K210_SYSCTL - bool "Kendryte K210 system controller" - default y - depends on RISCV - help - Enables controlling the K210 various clocks and to enable - general purpose use of the extra 2MB of SRAM normally - reserved for the AI engine. - -endif +config SOC_K210 + bool "Kendryte K210 SoC drivers" + depends on RISCV && SOC_KENDRYTE && OF + select PM + select SIMPLE_PM_BUS + select SYSCON + select MFD_SYSCON diff --git a/drivers/soc/kendryte/Makefile b/drivers/soc/kendryte/Makefile index 002d9ce95c0d..e67425707484 100644 --- a/drivers/soc/kendryte/Makefile +++ b/drivers/soc/kendryte/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_K210_SYSCTL) += k210-sysctl.o +obj-$(CONFIG_SOC_K210) += k210-sysctl.o From patchwork Sat Nov 7 08:14:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396062 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=lSpjTg8c; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqn054ZVz9sTD for ; Sat, 7 Nov 2020 19:15:00 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728074AbgKGIO7 (ORCPT ); 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07 Nov 2020 00:14:56 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 13/32] riscv: Fix builtin DTB handling Date: Sat, 7 Nov 2020 17:14:01 +0900 Message-Id: <20201107081420.60325-14-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org All SiPeed K210 boards have the exact same vendor, arch and implementation IDs, preventing differentiation of the device tree to use through the SOC_BUILTIN_DTB_DECLARE() macro. This result in this macro, used only for Kendryte, to be useless and to prevent changing the builtin device tree without also changing the code of the sysctl soc driver. Fix this problem by removing the SOC_BUILTIN_DTB_DECLARE() macro and associated code, falling back to a simpler, and more traditional handling of builtin DTB similar to other architectures. Signed-off-by: Damien Le Moal --- arch/riscv/Kconfig.socs | 22 ++++++++++++---- arch/riscv/boot/dts/kendryte/Makefile | 5 ++-- arch/riscv/include/asm/soc.h | 38 --------------------------- arch/riscv/kernel/soc.c | 27 ------------------- arch/riscv/mm/init.c | 6 +---- drivers/soc/kendryte/k210-sysctl.c | 12 --------- 6 files changed, 21 insertions(+), 89 deletions(-) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index e724fddc44ba..97ef393d0ed0 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -33,9 +33,10 @@ config SOC_KENDRYTE help This enables support for Kendryte K210 SoC platform hardware. -config SOC_KENDRYTE_K210_DTB - def_bool y - depends on SOC_KENDRYTE_K210_DTB_BUILTIN +config BUILTIN_DTB + def_bool n + +if SOC_KENDRYTE config SOC_KENDRYTE_K210_DTB_BUILTIN bool "Builtin device tree for the Kendryte K210" @@ -43,10 +44,21 @@ config SOC_KENDRYTE_K210_DTB_BUILTIN default y select OF select BUILTIN_DTB - select SOC_KENDRYTE_K210_DTB help - Builds a device tree for the Kendryte K210 into the Linux image. + Build a device tree for the Kendryte K210 into the Linux image. This option should be selected if no bootloader is being used. If unsure, say Y. +config SOC_KENDRYTE_K210_DTB_SOURCE + string "Source file for the Kendryte K210 builtin DTB" + depends on SOC_KENDRYTE + depends on SOC_KENDRYTE_K210_DTB_BUILTIN + default "k210" + help + Base name (without suffix, relative to arch/riscv/boot/dts/kendryte) + for the DTS file that will be used to produce the DTB linked into the + kernel. + +endif + endmenu diff --git a/arch/riscv/boot/dts/kendryte/Makefile b/arch/riscv/boot/dts/kendryte/Makefile index 1a88e616f18e..83636693166d 100644 --- a/arch/riscv/boot/dts/kendryte/Makefile +++ b/arch/riscv/boot/dts/kendryte/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_SOC_KENDRYTE_K210_DTB) += k210.dtb - +ifneq ($(CONFIG_SOC_KENDRYTE_K210_DTB_SOURCE),"") +dtb-y += $(strip $(shell echo $(CONFIG_SOC_KENDRYTE_K210_DTB_SOURCE))).dtb obj-$(CONFIG_SOC_KENDRYTE_K210_DTB_BUILTIN) += $(addsuffix .o, $(dtb-y)) +endif diff --git a/arch/riscv/include/asm/soc.h b/arch/riscv/include/asm/soc.h index 6c8363b1f327..f494066051a2 100644 --- a/arch/riscv/include/asm/soc.h +++ b/arch/riscv/include/asm/soc.h @@ -21,42 +21,4 @@ void soc_early_init(void); extern unsigned long __soc_early_init_table_start; extern unsigned long __soc_early_init_table_end; -/* - * Allows Linux to provide a device tree, which is necessary for SOCs that - * don't provide a useful one on their own. - */ -struct soc_builtin_dtb { - unsigned long vendor_id; - unsigned long arch_id; - unsigned long imp_id; - void *(*dtb_func)(void); -}; - -/* - * The argument name must specify a valid DTS file name without the dts - * extension. - */ -#define SOC_BUILTIN_DTB_DECLARE(name, vendor, arch, impl) \ - extern void *__dtb_##name##_begin; \ - \ - static __init __used \ - void *__soc_builtin_dtb_f__##name(void) \ - { \ - return (void *)&__dtb_##name##_begin; \ - } \ - \ - static const struct soc_builtin_dtb __soc_builtin_dtb__##name \ - __used __section("__soc_builtin_dtb_table") = \ - { \ - .vendor_id = vendor, \ - .arch_id = arch, \ - .imp_id = impl, \ - .dtb_func = __soc_builtin_dtb_f__##name, \ - } - -extern unsigned long __soc_builtin_dtb_table_start; -extern unsigned long __soc_builtin_dtb_table_end; - -void *soc_lookup_builtin_dtb(void); - #endif diff --git a/arch/riscv/kernel/soc.c b/arch/riscv/kernel/soc.c index c7b0a73e382e..a0516172a33c 100644 --- a/arch/riscv/kernel/soc.c +++ b/arch/riscv/kernel/soc.c @@ -26,30 +26,3 @@ void __init soc_early_init(void) } } } - -static bool soc_builtin_dtb_match(unsigned long vendor_id, - unsigned long arch_id, unsigned long imp_id, - const struct soc_builtin_dtb *entry) -{ - return entry->vendor_id == vendor_id && - entry->arch_id == arch_id && - entry->imp_id == imp_id; -} - -void * __init soc_lookup_builtin_dtb(void) -{ - unsigned long vendor_id, arch_id, imp_id; - const struct soc_builtin_dtb *s; - - __asm__ ("csrr %0, mvendorid" : "=r"(vendor_id)); - __asm__ ("csrr %0, marchid" : "=r"(arch_id)); - __asm__ ("csrr %0, mimpid" : "=r"(imp_id)); - - for (s = (void *)&__soc_builtin_dtb_table_start; - (void *)s < (void *)&__soc_builtin_dtb_table_end; s++) { - if (soc_builtin_dtb_match(vendor_id, arch_id, imp_id, s)) - return s->dtb_func(); - } - - return NULL; -} diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index ea933b789a88..d9c8d8819ed8 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -591,11 +591,7 @@ static void __init setup_vm_final(void) asmlinkage void __init setup_vm(uintptr_t dtb_pa) { #ifdef CONFIG_BUILTIN_DTB - dtb_early_va = soc_lookup_builtin_dtb(); - if (!dtb_early_va) { - /* Fallback to first available DTS */ - dtb_early_va = (void *) __dtb_start; - } + dtb_early_va = (void *) __dtb_start; #else dtb_early_va = (void *)dtb_pa; #endif diff --git a/drivers/soc/kendryte/k210-sysctl.c b/drivers/soc/kendryte/k210-sysctl.c index 707019223dd8..4608fbca20e1 100644 --- a/drivers/soc/kendryte/k210-sysctl.c +++ b/drivers/soc/kendryte/k210-sysctl.c @@ -246,15 +246,3 @@ static void __init k210_soc_early_init(const void *fdt) iounmap(regs); } SOC_EARLY_INIT_DECLARE(generic_k210, "kendryte,k210", k210_soc_early_init); - -#ifdef CONFIG_SOC_KENDRYTE_K210_DTB_BUILTIN -/* - * Generic entry for the default k210.dtb embedded DTB for boards with: - * - Vendor ID: 0x4B5 - * - Arch ID: 0xE59889E6A5A04149 (= "Canaan AI" in UTF-8 encoded Chinese) - * - Impl ID: 0x4D41495832303030 (= "MAIX2000") - * These values are reported by the SiPEED MAXDUINO, SiPEED MAIX GO and - * SiPEED Dan dock boards. - */ -SOC_BUILTIN_DTB_DECLARE(k210, 0x4B5, 0xE59889E6A5A04149, 0x4D41495832303030); -#endif From patchwork Sat Nov 7 08:14:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396063 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=NcikV2SN; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqn31Pdmz9sRR for ; Sat, 7 Nov 2020 19:15:03 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728095AbgKGIPC (ORCPT ); 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07 Nov 2020 00:14:59 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 14/32] dt-bindings: Define all Kendryte K210 clock IDs Date: Sat, 7 Nov 2020 17:14:02 +0900 Message-Id: <20201107081420.60325-15-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Define unique arbitrary IDs for all 44 clocks available on the Kendryte K210 RISC-V SoC in the header file include/dt-bindings/clock/k210-clk.h. Signed-off-by: Damien Le Moal Reviewed-by: Sean Anderson --- include/dt-bindings/clock/k210-clk.h | 61 +++++++++++++++++++++++----- 1 file changed, 50 insertions(+), 11 deletions(-) diff --git a/include/dt-bindings/clock/k210-clk.h b/include/dt-bindings/clock/k210-clk.h index 5a2fd64d1a49..8d7ab2f0737c 100644 --- a/include/dt-bindings/clock/k210-clk.h +++ b/include/dt-bindings/clock/k210-clk.h @@ -3,18 +3,57 @@ * Copyright (C) 2019-20 Sean Anderson * Copyright (c) 2020 Western Digital Corporation or its affiliates. */ -#ifndef K210_CLK_H -#define K210_CLK_H +#ifndef CLOCK_K210_CLK_H +#define CLOCK_K210_CLK_H /* - * Arbitrary identifiers for clocks. - * The structure is: in0 -> pll0 -> aclk -> cpu - * - * Since we use the hardware defaults for now, set all these to the same clock. + * Kendryte K210 SoC clock identifiers (arbitrary values). */ -#define K210_CLK_PLL0 0 -#define K210_CLK_PLL1 0 -#define K210_CLK_ACLK 0 -#define K210_CLK_CPU 0 +#define K210_CLK_IN0 0 +#define K210_CLK_PLL0 1 +#define K210_CLK_PLL1 2 +#define K210_CLK_PLL2 3 +#define K210_CLK_ACLK 4 +#define K210_CLK_CPU 5 +#define K210_CLK_CLINT 6 +#define K210_CLK_DMA 7 +#define K210_CLK_FFT 8 +#define K210_CLK_SRAM0 9 +#define K210_CLK_SRAM1 10 +#define K210_CLK_ROM 11 +#define K210_CLK_DVP 12 +#define K210_CLK_APB0 13 +#define K210_CLK_APB1 14 +#define K210_CLK_APB2 15 +#define K210_CLK_AI 16 +#define K210_CLK_I2S0 17 +#define K210_CLK_I2S1 18 +#define K210_CLK_I2S2 19 +#define K210_CLK_I2S0_M 20 +#define K210_CLK_I2S1_M 21 +#define K210_CLK_I2S2_M 22 +#define K210_CLK_WDT0 23 +#define K210_CLK_WDT1 24 +#define K210_CLK_SPI0 25 +#define K210_CLK_SPI1 26 +#define K210_CLK_SPI2 27 +#define K210_CLK_I2C0 28 +#define K210_CLK_I2C1 29 +#define K210_CLK_I2C2 30 +#define K210_CLK_SPI3 31 +#define K210_CLK_TIMER0 32 +#define K210_CLK_TIMER1 33 +#define K210_CLK_TIMER2 34 +#define K210_CLK_GPIO 35 +#define K210_CLK_UART1 36 +#define K210_CLK_UART2 37 +#define K210_CLK_UART3 38 +#define K210_CLK_FPIOA 39 +#define K210_CLK_SHA 40 +#define K210_CLK_AES 41 +#define K210_CLK_OTP 42 +#define K210_CLK_RTC 43 -#endif /* K210_CLK_H */ +#define K210_NUM_CLKS 44 + +#endif /* CLOCK_K210_CLK_H */ From patchwork Sat Nov 7 08:14:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396065 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=AbphSkPw; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqn60Hd8z9sRR for ; Sat, 7 Nov 2020 19:15:06 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728093AbgKGIPF (ORCPT ); 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d="scan'208";a="156564392" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 07 Nov 2020 16:15:03 +0800 IronPort-SDR: taG2sS+61Tfoy1/9YQZ8YdW2Q8g/1PpSM7cqVhzq6hH1/Owv1AaX5onQ1uyecI5GiLfO6OGd5R QvMSoV0rWxvEEzvwwleCpiE8IgtaXKmgkSEBzK9RvrEdFSfeNEiD8AvNh/z/udsejhsgQSysim Bv5RxCfPfhnEVwqzDIBjtF+Ktk+Kr/tq/wfmZRN8lebUisWXtXwJO6KNFOrD1A7Ag8EwAl4Hjr dZftZvsmD++0aD3It9s5Wco89SV/cFxaHYrPY1dZqvWnZE3GifitCdXcH1lQADOws88Bs/0LVw XF1YTt0qRqJ8JOoGBqLN287+ Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2020 23:59:54 -0800 IronPort-SDR: dNzPwHeL0Y0HsdiO5RbgCWw5NbkvUs09f6HACXWVf3uJo62lGJ18zW3AULbXxjvfEzay/Fqiwj Ti4+Ok/5odPXKfyMVNpuPjkqrE0h6iYvNW/XFzgzAudOb9azkDYhuoVU3gNaBud4vKouOyh8Ao DrOaW4Ehk2wpJWepXLnw/skilL/a32bxsfTF7tGMtyNhq8nCh3Qzod393PXKbPzMdCRs0lBJgv W2WN0Mnas1krFdeveG2FIWFXpUGtHlF+BOmSXXiadqXLPo9q7LUQyxDO+5rdR2G7O8VmOwiavJ lQ0= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:15:02 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 15/32] dt-bindings: Define Kendryte K210 sysctl registers Date: Sat, 7 Nov 2020 17:14:03 +0900 Message-Id: <20201107081420.60325-16-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Introduce the dt-bindings file include/dt-bindings/mfd/k210_sysctl.h to define the offset of all registers of the K210 system controller. Signed-off-by: Damien Le Moal Reviewed-by: Sean Anderson --- include/dt-bindings/mfd/k210-sysctl.h | 41 +++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/mfd/k210-sysctl.h diff --git a/include/dt-bindings/mfd/k210-sysctl.h b/include/dt-bindings/mfd/k210-sysctl.h new file mode 100644 index 000000000000..5cc386d3c9ca --- /dev/null +++ b/include/dt-bindings/mfd/k210-sysctl.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Sean Anderson + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + */ +#ifndef MFD_K210_SYSCTL_H +#define MFD_K210_SYSCTL_H + +/* + * Kendryte K210 SoC system controller registers offsets. + * Taken from Kendryte SDK (kendryte-standalone-sdk). + */ +#define K210_SYSCTL_GIT_ID 0x00 /* Git short commit id */ +#define K210_SYSCTL_UART_BAUD 0x04 /* Default UARTHS baud rate */ +#define K210_SYSCTL_PLL0 0x08 /* PLL0 controller */ +#define K210_SYSCTL_PLL1 0x0C /* PLL1 controller */ +#define K210_SYSCTL_PLL2 0x10 /* PLL2 controller */ +#define K210_SYSCTL_PLL_LOCK 0x18 /* PLL lock tester */ +#define K210_SYSCTL_ROM_ERROR 0x1C /* AXI ROM detector */ +#define K210_SYSCTL_SEL0 0x20 /* Clock select controller 0 */ +#define K210_SYSCTL_SEL1 0x24 /* Clock select controller 1 */ +#define K210_SYSCTL_EN_CENT 0x28 /* Central clock enable */ +#define K210_SYSCTL_EN_PERI 0x2C /* Peripheral clock enable */ +#define K210_SYSCTL_SOFT_RESET 0x30 /* Soft reset ctrl */ +#define K210_SYSCTL_PERI_RESET 0x34 /* Peripheral reset controller */ +#define K210_SYSCTL_THR0 0x38 /* Clock threshold controller 0 */ +#define K210_SYSCTL_THR1 0x3C /* Clock threshold controller 1 */ +#define K210_SYSCTL_THR2 0x40 /* Clock threshold controller 2 */ +#define K210_SYSCTL_THR3 0x44 /* Clock threshold controller 3 */ +#define K210_SYSCTL_THR4 0x48 /* Clock threshold controller 4 */ +#define K210_SYSCTL_THR5 0x4C /* Clock threshold controller 5 */ +#define K210_SYSCTL_THR6 0x50 /* Clock threshold controller 6 */ +#define K210_SYSCTL_MISC 0x54 /* Miscellaneous controller */ +#define K210_SYSCTL_PERI 0x58 /* Peripheral controller */ +#define K210_SYSCTL_SPI_SLEEP 0x5C /* SPI sleep controller */ +#define K210_SYSCTL_RESET_STAT 0x60 /* Reset source status */ +#define K210_SYSCTL_DMA_SEL0 0x64 /* DMA handshake selector 0 */ +#define K210_SYSCTL_DMA_SEL1 0x68 /* DMA handshake selector 1 */ +#define K210_SYSCTL_POWER_SEL 0x6C /* IO Power Mode Select controller */ + +#endif /* MFD_K210_SYSCTL_H */ From patchwork Sat Nov 7 08:14:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396067 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=PAxIbXlY; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqn80GLLz9sSs for ; Sat, 7 Nov 2020 19:15:08 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728011AbgKGIPH (ORCPT ); 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d="scan'208";a="156564395" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 07 Nov 2020 16:15:06 +0800 IronPort-SDR: gPzOiBEBFOJNhv0W66htWfym8n2x6KfFOog34+aXcMz8y0rD7zOCAR4QFqB74e8R/nf8/348va HrNBgU1UR+gAAxU/CmaMvIUmLEH3+3jlwMm3ikl+KUEuZs0HKjxCmEsuFfRtOL5vXJgJ+8qSdJ boYmXvV065I8bIqOJXWr5gLMhnaXawkzGmr1XxA3bqccH10VgiSHMkdY1jQUxHayhQAv3tN1FG sLfOU9+nwSoXMRWsf1SejZMwjFbPovLR/tVBgIQHE04KXrIwLhaseQRKHZEVy6zuuBY0uA6fwC ussB2vrb/XxkQ+ULFY+O6yJ2 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2020 23:59:57 -0800 IronPort-SDR: Cbz0CHg/oQAxtU90LrAjPsnG2WXoTIUog6fttVMDIX4Yubpz8DuemDT6Ijw8uRcJxJqmLNcego utOLxNXRhITZAG9IQQVH9IMYmXQeL+efxwZVsC5SL4dBBSmXZTk4t2IqEVgq4dU7we2Lu4VElT baV3iKLbnf1Cgcw8nPd2ipF6Jvym+brQgZLFNi2b5bfy9Yj2J3Ub1lpOziu+/J1uluziK6reuP SMks2hqoB8C5tUCunIInGW4naOcMN2dhiyBN3nGXo6cQu7pRhLa6L6oWgZ2gvRSNYkfOrn9hfr ey4= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:15:04 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 16/32] dt-bindings: Define Kendryte K210 pin functions Date: Sat, 7 Nov 2020 17:14:04 +0900 Message-Id: <20201107081420.60325-17-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Introduce the dt-bindings file include/dt-bindings/pinctrl/k210_pinctrl.h to define all possible 255 functions that can be assigned to any of the 48 programmable pins of the SoC. Macros allowing a device tree to define a pinmux mapping are also introduced. Signed-off-by: Damien Le Moal Reviewed-by: Sean Anderson --- include/dt-bindings/pinctrl/k210-pinctrl.h | 277 +++++++++++++++++++++ 1 file changed, 277 insertions(+) create mode 100644 include/dt-bindings/pinctrl/k210-pinctrl.h diff --git a/include/dt-bindings/pinctrl/k210-pinctrl.h b/include/dt-bindings/pinctrl/k210-pinctrl.h new file mode 100644 index 000000000000..0b797a4a245e --- /dev/null +++ b/include/dt-bindings/pinctrl/k210-pinctrl.h @@ -0,0 +1,277 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Sean Anderson + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + */ +#ifndef PINCTRL_K210_SYSCTL_H +#define PINCTRL_K210_SYSCTL_H + +/* + * Full list of FPIOA functions from + * kendryte-standalone-sdk/lib/drivers/include/fpioa.h + */ +#define K210_PCF_MASK GENMASK(7, 0) +#define K210_PCF_JTAG_TCLK 0 /* JTAG Test Clock */ +#define K210_PCF_JTAG_TDI 1 /* JTAG Test Data In */ +#define K210_PCF_JTAG_TMS 2 /* JTAG Test Mode Select */ +#define K210_PCF_JTAG_TDO 3 /* JTAG Test Data Out */ +#define K210_PCF_SPI0_D0 4 /* SPI0 Data 0 */ +#define K210_PCF_SPI0_D1 5 /* SPI0 Data 1 */ +#define K210_PCF_SPI0_D2 6 /* SPI0 Data 2 */ +#define K210_PCF_SPI0_D3 7 /* SPI0 Data 3 */ +#define K210_PCF_SPI0_D4 8 /* SPI0 Data 4 */ +#define K210_PCF_SPI0_D5 9 /* SPI0 Data 5 */ +#define K210_PCF_SPI0_D6 10 /* SPI0 Data 6 */ +#define K210_PCF_SPI0_D7 11 /* SPI0 Data 7 */ +#define K210_PCF_SPI0_SS0 12 /* SPI0 Chip Select 0 */ +#define K210_PCF_SPI0_SS1 13 /* SPI0 Chip Select 1 */ +#define K210_PCF_SPI0_SS2 14 /* SPI0 Chip Select 2 */ +#define K210_PCF_SPI0_SS3 15 /* SPI0 Chip Select 3 */ +#define K210_PCF_SPI0_ARB 16 /* SPI0 Arbitration */ +#define K210_PCF_SPI0_SCLK 17 /* SPI0 Serial Clock */ +#define K210_PCF_UARTHS_RX 18 /* UART High speed Receiver */ +#define K210_PCF_UARTHS_TX 19 /* UART High speed Transmitter */ +#define K210_PCF_RESV6 20 /* Reserved function */ +#define K210_PCF_RESV7 21 /* Reserved function */ +#define K210_PCF_CLK_SPI1 22 /* Clock SPI1 */ +#define K210_PCF_CLK_I2C1 23 /* Clock I2C1 */ +#define K210_PCF_GPIOHS0 24 /* GPIO High speed 0 */ +#define K210_PCF_GPIOHS1 25 /* GPIO High speed 1 */ +#define K210_PCF_GPIOHS2 26 /* GPIO High speed 2 */ +#define K210_PCF_GPIOHS3 27 /* GPIO High speed 3 */ +#define K210_PCF_GPIOHS4 28 /* GPIO High speed 4 */ +#define K210_PCF_GPIOHS5 29 /* GPIO High speed 5 */ +#define K210_PCF_GPIOHS6 30 /* GPIO High speed 6 */ +#define K210_PCF_GPIOHS7 31 /* GPIO High speed 7 */ +#define K210_PCF_GPIOHS8 32 /* GPIO High speed 8 */ +#define K210_PCF_GPIOHS9 33 /* GPIO High speed 9 */ +#define K210_PCF_GPIOHS10 34 /* GPIO High speed 10 */ +#define K210_PCF_GPIOHS11 35 /* GPIO High speed 11 */ +#define K210_PCF_GPIOHS12 36 /* GPIO High speed 12 */ +#define K210_PCF_GPIOHS13 37 /* GPIO High speed 13 */ +#define K210_PCF_GPIOHS14 38 /* GPIO High speed 14 */ +#define K210_PCF_GPIOHS15 39 /* GPIO High speed 15 */ +#define K210_PCF_GPIOHS16 40 /* GPIO High speed 16 */ +#define K210_PCF_GPIOHS17 41 /* GPIO High speed 17 */ +#define K210_PCF_GPIOHS18 42 /* GPIO High speed 18 */ +#define K210_PCF_GPIOHS19 43 /* GPIO High speed 19 */ +#define K210_PCF_GPIOHS20 44 /* GPIO High speed 20 */ +#define K210_PCF_GPIOHS21 45 /* GPIO High speed 21 */ +#define K210_PCF_GPIOHS22 46 /* GPIO High speed 22 */ +#define K210_PCF_GPIOHS23 47 /* GPIO High speed 23 */ +#define K210_PCF_GPIOHS24 48 /* GPIO High speed 24 */ +#define K210_PCF_GPIOHS25 49 /* GPIO High speed 25 */ +#define K210_PCF_GPIOHS26 50 /* GPIO High speed 26 */ +#define K210_PCF_GPIOHS27 51 /* GPIO High speed 27 */ +#define K210_PCF_GPIOHS28 52 /* GPIO High speed 28 */ +#define K210_PCF_GPIOHS29 53 /* GPIO High speed 29 */ +#define K210_PCF_GPIOHS30 54 /* GPIO High speed 30 */ +#define K210_PCF_GPIOHS31 55 /* GPIO High speed 31 */ +#define K210_PCF_GPIO0 56 /* GPIO pin 0 */ +#define K210_PCF_GPIO1 57 /* GPIO pin 1 */ +#define K210_PCF_GPIO2 58 /* GPIO pin 2 */ +#define K210_PCF_GPIO3 59 /* GPIO pin 3 */ +#define K210_PCF_GPIO4 60 /* GPIO pin 4 */ +#define K210_PCF_GPIO5 61 /* GPIO pin 5 */ +#define K210_PCF_GPIO6 62 /* GPIO pin 6 */ +#define K210_PCF_GPIO7 63 /* GPIO pin 7 */ +#define K210_PCF_UART1_RX 64 /* UART1 Receiver */ +#define K210_PCF_UART1_TX 65 /* UART1 Transmitter */ +#define K210_PCF_UART2_RX 66 /* UART2 Receiver */ +#define K210_PCF_UART2_TX 67 /* UART2 Transmitter */ +#define K210_PCF_UART3_RX 68 /* UART3 Receiver */ +#define K210_PCF_UART3_TX 69 /* UART3 Transmitter */ +#define K210_PCF_SPI1_D0 70 /* SPI1 Data 0 */ +#define K210_PCF_SPI1_D1 71 /* SPI1 Data 1 */ +#define K210_PCF_SPI1_D2 72 /* SPI1 Data 2 */ +#define K210_PCF_SPI1_D3 73 /* SPI1 Data 3 */ +#define K210_PCF_SPI1_D4 74 /* SPI1 Data 4 */ +#define K210_PCF_SPI1_D5 75 /* SPI1 Data 5 */ +#define K210_PCF_SPI1_D6 76 /* SPI1 Data 6 */ +#define K210_PCF_SPI1_D7 77 /* SPI1 Data 7 */ +#define K210_PCF_SPI1_SS0 78 /* SPI1 Chip Select 0 */ +#define K210_PCF_SPI1_SS1 79 /* SPI1 Chip Select 1 */ +#define K210_PCF_SPI1_SS2 80 /* SPI1 Chip Select 2 */ +#define K210_PCF_SPI1_SS3 81 /* SPI1 Chip Select 3 */ +#define K210_PCF_SPI1_ARB 82 /* SPI1 Arbitration */ +#define K210_PCF_SPI1_SCLK 83 /* SPI1 Serial Clock */ +#define K210_PCF_SPI2_D0 84 /* SPI2 Data 0 */ +#define K210_PCF_SPI2_SS 85 /* SPI2 Select */ +#define K210_PCF_SPI2_SCLK 86 /* SPI2 Serial Clock */ +#define K210_PCF_I2S0_MCLK 87 /* I2S0 Master Clock */ +#define K210_PCF_I2S0_SCLK 88 /* I2S0 Serial Clock(BCLK) */ +#define K210_PCF_I2S0_WS 89 /* I2S0 Word Select(LRCLK) */ +#define K210_PCF_I2S0_IN_D0 90 /* I2S0 Serial Data Input 0 */ +#define K210_PCF_I2S0_IN_D1 91 /* I2S0 Serial Data Input 1 */ +#define K210_PCF_I2S0_IN_D2 92 /* I2S0 Serial Data Input 2 */ +#define K210_PCF_I2S0_IN_D3 93 /* I2S0 Serial Data Input 3 */ +#define K210_PCF_I2S0_OUT_D0 94 /* I2S0 Serial Data Output 0 */ +#define K210_PCF_I2S0_OUT_D1 95 /* I2S0 Serial Data Output 1 */ +#define K210_PCF_I2S0_OUT_D2 96 /* I2S0 Serial Data Output 2 */ +#define K210_PCF_I2S0_OUT_D3 97 /* I2S0 Serial Data Output 3 */ +#define K210_PCF_I2S1_MCLK 98 /* I2S1 Master Clock */ +#define K210_PCF_I2S1_SCLK 99 /* I2S1 Serial Clock(BCLK) */ +#define K210_PCF_I2S1_WS 100 /* I2S1 Word Select(LRCLK) */ +#define K210_PCF_I2S1_IN_D0 101 /* I2S1 Serial Data Input 0 */ +#define K210_PCF_I2S1_IN_D1 102 /* I2S1 Serial Data Input 1 */ +#define K210_PCF_I2S1_IN_D2 103 /* I2S1 Serial Data Input 2 */ +#define K210_PCF_I2S1_IN_D3 104 /* I2S1 Serial Data Input 3 */ +#define K210_PCF_I2S1_OUT_D0 105 /* I2S1 Serial Data Output 0 */ +#define K210_PCF_I2S1_OUT_D1 106 /* I2S1 Serial Data Output 1 */ +#define K210_PCF_I2S1_OUT_D2 107 /* I2S1 Serial Data Output 2 */ +#define K210_PCF_I2S1_OUT_D3 108 /* I2S1 Serial Data Output 3 */ +#define K210_PCF_I2S2_MCLK 109 /* I2S2 Master Clock */ +#define K210_PCF_I2S2_SCLK 110 /* I2S2 Serial Clock(BCLK) */ +#define K210_PCF_I2S2_WS 111 /* I2S2 Word Select(LRCLK) */ +#define K210_PCF_I2S2_IN_D0 112 /* I2S2 Serial Data Input 0 */ +#define K210_PCF_I2S2_IN_D1 113 /* I2S2 Serial Data Input 1 */ +#define K210_PCF_I2S2_IN_D2 114 /* I2S2 Serial Data Input 2 */ +#define K210_PCF_I2S2_IN_D3 115 /* I2S2 Serial Data Input 3 */ +#define K210_PCF_I2S2_OUT_D0 116 /* I2S2 Serial Data Output 0 */ +#define K210_PCF_I2S2_OUT_D1 117 /* I2S2 Serial Data Output 1 */ +#define K210_PCF_I2S2_OUT_D2 118 /* I2S2 Serial Data Output 2 */ +#define K210_PCF_I2S2_OUT_D3 119 /* I2S2 Serial Data Output 3 */ +#define K210_PCF_RESV0 120 /* Reserved function */ +#define K210_PCF_RESV1 121 /* Reserved function */ +#define K210_PCF_RESV2 122 /* Reserved function */ +#define K210_PCF_RESV3 123 /* Reserved function */ +#define K210_PCF_RESV4 124 /* Reserved function */ +#define K210_PCF_RESV5 125 /* Reserved function */ +#define K210_PCF_I2C0_SCLK 126 /* I2C0 Serial Clock */ +#define K210_PCF_I2C0_SDA 127 /* I2C0 Serial Data */ +#define K210_PCF_I2C1_SCLK 128 /* I2C1 Serial Clock */ +#define K210_PCF_I2C1_SDA 129 /* I2C1 Serial Data */ +#define K210_PCF_I2C2_SCLK 130 /* I2C2 Serial Clock */ +#define K210_PCF_I2C2_SDA 131 /* I2C2 Serial Data */ +#define K210_PCF_DVP_XCLK 132 /* DVP System Clock */ +#define K210_PCF_DVP_RST 133 /* DVP System Reset */ +#define K210_PCF_DVP_PWDN 134 /* DVP Power Down Mode */ +#define K210_PCF_DVP_VSYNC 135 /* DVP Vertical Sync */ +#define K210_PCF_DVP_HSYNC 136 /* DVP Horizontal Sync */ +#define K210_PCF_DVP_PCLK 137 /* Pixel Clock */ +#define K210_PCF_DVP_D0 138 /* Data Bit 0 */ +#define K210_PCF_DVP_D1 139 /* Data Bit 1 */ +#define K210_PCF_DVP_D2 140 /* Data Bit 2 */ +#define K210_PCF_DVP_D3 141 /* Data Bit 3 */ +#define K210_PCF_DVP_D4 142 /* Data Bit 4 */ +#define K210_PCF_DVP_D5 143 /* Data Bit 5 */ +#define K210_PCF_DVP_D6 144 /* Data Bit 6 */ +#define K210_PCF_DVP_D7 145 /* Data Bit 7 */ +#define K210_PCF_SCCB_SCLK 146 /* Serial Camera Control Bus Clock */ +#define K210_PCF_SCCB_SDA 147 /* Serial Camera Control Bus Data */ +#define K210_PCF_UART1_CTS 148 /* UART1 Clear To Send */ +#define K210_PCF_UART1_DSR 149 /* UART1 Data Set Ready */ +#define K210_PCF_UART1_DCD 150 /* UART1 Data Carrier Detect */ +#define K210_PCF_UART1_RI 151 /* UART1 Ring Indicator */ +#define K210_PCF_UART1_SIR_IN 152 /* UART1 Serial Infrared Input */ +#define K210_PCF_UART1_DTR 153 /* UART1 Data Terminal Ready */ +#define K210_PCF_UART1_RTS 154 /* UART1 Request To Send */ +#define K210_PCF_UART1_OUT2 155 /* UART1 User-designated Output 2 */ +#define K210_PCF_UART1_OUT1 156 /* UART1 User-designated Output 1 */ +#define K210_PCF_UART1_SIR_OUT 157 /* UART1 Serial Infrared Output */ +#define K210_PCF_UART1_BAUD 158 /* UART1 Transmit Clock Output */ +#define K210_PCF_UART1_RE 159 /* UART1 Receiver Output Enable */ +#define K210_PCF_UART1_DE 160 /* UART1 Driver Output Enable */ +#define K210_PCF_UART1_RS485_EN 161 /* UART1 RS485 Enable */ +#define K210_PCF_UART2_CTS 162 /* UART2 Clear To Send */ +#define K210_PCF_UART2_DSR 163 /* UART2 Data Set Ready */ +#define K210_PCF_UART2_DCD 164 /* UART2 Data Carrier Detect */ +#define K210_PCF_UART2_RI 165 /* UART2 Ring Indicator */ +#define K210_PCF_UART2_SIR_IN 166 /* UART2 Serial Infrared Input */ +#define K210_PCF_UART2_DTR 167 /* UART2 Data Terminal Ready */ +#define K210_PCF_UART2_RTS 168 /* UART2 Request To Send */ +#define K210_PCF_UART2_OUT2 169 /* UART2 User-designated Output 2 */ +#define K210_PCF_UART2_OUT1 170 /* UART2 User-designated Output 1 */ +#define K210_PCF_UART2_SIR_OUT 171 /* UART2 Serial Infrared Output */ +#define K210_PCF_UART2_BAUD 172 /* UART2 Transmit Clock Output */ +#define K210_PCF_UART2_RE 173 /* UART2 Receiver Output Enable */ +#define K210_PCF_UART2_DE 174 /* UART2 Driver Output Enable */ +#define K210_PCF_UART2_RS485_EN 175 /* UART2 RS485 Enable */ +#define K210_PCF_UART3_CTS 176 /* UART3 Clear To Send */ +#define K210_PCF_UART3_DSR 177 /* UART3 Data Set Ready */ +#define K210_PCF_UART3_DCD 178 /* UART3 Data Carrier Detect */ +#define K210_PCF_UART3_RI 179 /* UART3 Ring Indicator */ +#define K210_PCF_UART3_SIR_IN 180 /* UART3 Serial Infrared Input */ +#define K210_PCF_UART3_DTR 181 /* UART3 Data Terminal Ready */ +#define K210_PCF_UART3_RTS 182 /* UART3 Request To Send */ +#define K210_PCF_UART3_OUT2 183 /* UART3 User-designated Output 2 */ +#define K210_PCF_UART3_OUT1 184 /* UART3 User-designated Output 1 */ +#define K210_PCF_UART3_SIR_OUT 185 /* UART3 Serial Infrared Output */ +#define K210_PCF_UART3_BAUD 186 /* UART3 Transmit Clock Output */ +#define K210_PCF_UART3_RE 187 /* UART3 Receiver Output Enable */ +#define K210_PCF_UART3_DE 188 /* UART3 Driver Output Enable */ +#define K210_PCF_UART3_RS485_EN 189 /* UART3 RS485 Enable */ +#define K210_PCF_TIMER0_TOGGLE1 190 /* TIMER0 Toggle Output 1 */ +#define K210_PCF_TIMER0_TOGGLE2 191 /* TIMER0 Toggle Output 2 */ +#define K210_PCF_TIMER0_TOGGLE3 192 /* TIMER0 Toggle Output 3 */ +#define K210_PCF_TIMER0_TOGGLE4 193 /* TIMER0 Toggle Output 4 */ +#define K210_PCF_TIMER1_TOGGLE1 194 /* TIMER1 Toggle Output 1 */ +#define K210_PCF_TIMER1_TOGGLE2 195 /* TIMER1 Toggle Output 2 */ +#define K210_PCF_TIMER1_TOGGLE3 196 /* TIMER1 Toggle Output 3 */ +#define K210_PCF_TIMER1_TOGGLE4 197 /* TIMER1 Toggle Output 4 */ +#define K210_PCF_TIMER2_TOGGLE1 198 /* TIMER2 Toggle Output 1 */ +#define K210_PCF_TIMER2_TOGGLE2 199 /* TIMER2 Toggle Output 2 */ +#define K210_PCF_TIMER2_TOGGLE3 200 /* TIMER2 Toggle Output 3 */ +#define K210_PCF_TIMER2_TOGGLE4 201 /* TIMER2 Toggle Output 4 */ +#define K210_PCF_CLK_SPI2 202 /* Clock SPI2 */ +#define K210_PCF_CLK_I2C2 203 /* Clock I2C2 */ +#define K210_PCF_INTERNAL0 204 /* Internal function signal 0 */ +#define K210_PCF_INTERNAL1 205 /* Internal function signal 1 */ +#define K210_PCF_INTERNAL2 206 /* Internal function signal 2 */ +#define K210_PCF_INTERNAL3 207 /* Internal function signal 3 */ +#define K210_PCF_INTERNAL4 208 /* Internal function signal 4 */ +#define K210_PCF_INTERNAL5 209 /* Internal function signal 5 */ +#define K210_PCF_INTERNAL6 210 /* Internal function signal 6 */ +#define K210_PCF_INTERNAL7 211 /* Internal function signal 7 */ +#define K210_PCF_INTERNAL8 212 /* Internal function signal 8 */ +#define K210_PCF_INTERNAL9 213 /* Internal function signal 9 */ +#define K210_PCF_INTERNAL10 214 /* Internal function signal 10 */ +#define K210_PCF_INTERNAL11 215 /* Internal function signal 11 */ +#define K210_PCF_INTERNAL12 216 /* Internal function signal 12 */ +#define K210_PCF_INTERNAL13 217 /* Internal function signal 13 */ +#define K210_PCF_INTERNAL14 218 /* Internal function signal 14 */ +#define K210_PCF_INTERNAL15 219 /* Internal function signal 15 */ +#define K210_PCF_INTERNAL16 220 /* Internal function signal 16 */ +#define K210_PCF_INTERNAL17 221 /* Internal function signal 17 */ +#define K210_PCF_CONSTANT 222 /* Constant function */ +#define K210_PCF_INTERNAL18 223 /* Internal function signal 18 */ +#define K210_PCF_DEBUG0 224 /* Debug function 0 */ +#define K210_PCF_DEBUG1 225 /* Debug function 1 */ +#define K210_PCF_DEBUG2 226 /* Debug function 2 */ +#define K210_PCF_DEBUG3 227 /* Debug function 3 */ +#define K210_PCF_DEBUG4 228 /* Debug function 4 */ +#define K210_PCF_DEBUG5 229 /* Debug function 5 */ +#define K210_PCF_DEBUG6 230 /* Debug function 6 */ +#define K210_PCF_DEBUG7 231 /* Debug function 7 */ +#define K210_PCF_DEBUG8 232 /* Debug function 8 */ +#define K210_PCF_DEBUG9 233 /* Debug function 9 */ +#define K210_PCF_DEBUG10 234 /* Debug function 10 */ +#define K210_PCF_DEBUG11 235 /* Debug function 11 */ +#define K210_PCF_DEBUG12 236 /* Debug function 12 */ +#define K210_PCF_DEBUG13 237 /* Debug function 13 */ +#define K210_PCF_DEBUG14 238 /* Debug function 14 */ +#define K210_PCF_DEBUG15 239 /* Debug function 15 */ +#define K210_PCF_DEBUG16 240 /* Debug function 16 */ +#define K210_PCF_DEBUG17 241 /* Debug function 17 */ +#define K210_PCF_DEBUG18 242 /* Debug function 18 */ +#define K210_PCF_DEBUG19 243 /* Debug function 19 */ +#define K210_PCF_DEBUG20 244 /* Debug function 20 */ +#define K210_PCF_DEBUG21 245 /* Debug function 21 */ +#define K210_PCF_DEBUG22 246 /* Debug function 22 */ +#define K210_PCF_DEBUG23 247 /* Debug function 23 */ +#define K210_PCF_DEBUG24 248 /* Debug function 24 */ +#define K210_PCF_DEBUG25 249 /* Debug function 25 */ +#define K210_PCF_DEBUG26 250 /* Debug function 26 */ +#define K210_PCF_DEBUG27 251 /* Debug function 27 */ +#define K210_PCF_DEBUG28 252 /* Debug function 28 */ +#define K210_PCF_DEBUG29 253 /* Debug function 29 */ +#define K210_PCF_DEBUG30 254 /* Debug function 30 */ +#define K210_PCF_DEBUG31 255 /* Debug function 31 */ + +#define K210_FPIOA(pin, func) (((pin) << 16) | (func)) +#define K210_FPIOA_DO(pin, func) (((pin) << 16) | (1 << 8) | (func)) + +#define K210_PC_POWER_3V3 0 +#define K210_PC_POWER_1V8 1 + +#endif /* PINCTRL_K210_SYSCTL_H */ From patchwork Sat Nov 7 08:14:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396069 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=Nk9na0o/; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqnB4zBKz9sRR for ; Sat, 7 Nov 2020 19:15:10 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727901AbgKGIPK (ORCPT ); Sat, 7 Nov 2020 03:15:10 -0500 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:57208 "EHLO esa3.hgst.iphmx.com" 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ng2GDwGNn5CNdyEfSwoxvKD/MrGzxeVapDW6xdraan3O0IMBvRzo6DSry6xRb/JUXnS6nVvYBP MrQ= X-IronPort-AV: E=Sophos;i="5.77,459,1596470400"; d="scan'208";a="156564397" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 07 Nov 2020 16:15:08 +0800 IronPort-SDR: FH39SVUv08nLOxG1dKsM1eZwvx+s7dUed2GaNI+j3z+CrkbP+umQKleuOipfyeAnV+L6BrfkEU e6ZlVhamcu6sGe2f+3ww2ltMgR1FaoD0PR08dAEJuNoN5U71j/stxB6SPo8wjtQgYAri25d/zb IwiCvpGGwZoNtfXk6VSXMCJUr2PesQcOW7298QRWWvb4uShZFjS/hjmlLcoi84Nvq0SMJGsnxb zqzHsZ8GWit5y/+XP4jOYIZC7jg5PnQGtBmdRep79HuXoaLFIBVuXK21Z7vnNoaWU1Tfkz3j2z aeYGU8wA73xsnA12/noA5V3E Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2020 00:00:00 -0800 IronPort-SDR: y1qTH6RGguGSyluxLK/fBd4YoKIYIBAHDBFAdJDQnfLjUxogD/HMVQV51PGP4PWDtiHU7L5lXh Ks0iRlB+NUDic6UsOlYiPQeN7Sa7eXGftVRNUnS53IRichEDB5BqeldCwo72sfTn2QQDblZvWX RisdudAF1jcncJw0uUSGiwjWt+bVWimOOgsvFBdNd4+YimsR0TBA//fGYaan2doQ2vHP1rTsfh oQrdxVYyDy+UDB00awl1jR/S0/pdo6CeH33MIgTe/wg/bW5ZNjUhktJ78wfuahcIGR5Ym1N2ub JZA= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:15:07 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 17/32] dt-bindings: Define Kendryte K210 reset signals Date: Sat, 7 Nov 2020 17:14:05 +0900 Message-Id: <20201107081420.60325-18-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Introduce the dt-bindings file include/dt-bindings/reset/k210_sysctl.h to define IDs for all 30 reset signals available on the Kendryte K210 RISC-V SoC. Signed-off-by: Damien Le Moal Reviewed-by: Sean Anderson --- include/dt-bindings/reset/k210-rst.h | 42 ++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 include/dt-bindings/reset/k210-rst.h diff --git a/include/dt-bindings/reset/k210-rst.h b/include/dt-bindings/reset/k210-rst.h new file mode 100644 index 000000000000..883c1aed50e8 --- /dev/null +++ b/include/dt-bindings/reset/k210-rst.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Sean Anderson + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + */ +#ifndef RESET_K210_SYSCTL_H +#define RESET_K210_SYSCTL_H + +/* + * Kendryte K210 SoC system controller K210_SYSCTL_SOFT_RESET register bits. + * Taken from Kendryte SDK (kendryte-standalone-sdk). + */ +#define K210_RST_ROM 0 +#define K210_RST_DMA 1 +#define K210_RST_AI 2 +#define K210_RST_DVP 3 +#define K210_RST_FFT 4 +#define K210_RST_GPIO 5 +#define K210_RST_SPI0 6 +#define K210_RST_SPI1 7 +#define K210_RST_SPI2 8 +#define K210_RST_SPI3 9 +#define K210_RST_I2S0 10 +#define K210_RST_I2S1 11 +#define K210_RST_I2S2 12 +#define K210_RST_I2C0 13 +#define K210_RST_I2C1 14 +#define K210_RST_I2C2 15 +#define K210_RST_UART1 16 +#define K210_RST_UART2 17 +#define K210_RST_UART3 18 +#define K210_RST_AES 19 +#define K210_RST_FPIOA 20 +#define K210_RST_TIMER0 21 +#define K210_RST_TIMER1 22 +#define K210_RST_TIMER2 23 +#define K210_RST_WDT0 24 +#define K210_RST_WDT1 25 +#define K210_RST_SHA 26 +#define K210_RST_RTC 29 + +#endif /* RESET_K210_SYSCTL_H */ From patchwork Sat Nov 7 08:14:06 2020 Content-Type: text/plain; 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07 Nov 2020 00:15:10 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 18/32] riscv: Add Kendryte K210 SoC clock driver Date: Sat, 7 Nov 2020 17:14:06 +0900 Message-Id: <20201107081420.60325-19-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add a clock provider driver for the Kendryte K210 RISC-V SoC. This new driver with compatible string "kendryte,k210-clk", implements the full clock structure of the K210 SoC. Since it is required for the correct operation of the SoC, this driver is automatically selected for compilation when the SOC_KENDRYTE option is selected. With this change, the k210-sysctl driver is turned into a simple platform driver which enables its power bus clock and triggers populating its child nodes. The sysctl soc driver retains the SOC early initialization code, but the implementation now relies on the new function k210_clk_early_init() provided by the new clk-k210 driver. This function declaration is done using the new header file include/soc/kendryte/k210-sysctl.h. The clock structure implemented and many of the coding ideas for the driver come from the work by Sean Anderson on the Kendryte K210 support for the U-Boot project. Signed-off-by: Damien Le Moal Reviewed-by: Sean Anderson --- arch/riscv/Kconfig.socs | 1 + drivers/clk/Kconfig | 9 + drivers/clk/Makefile | 1 + drivers/clk/clk-k210.c | 962 +++++++++++++++++++++++++++++ drivers/soc/kendryte/k210-sysctl.c | 241 ++------ include/soc/kendryte/k210-sysctl.h | 11 + 6 files changed, 1025 insertions(+), 200 deletions(-) create mode 100644 drivers/clk/clk-k210.c create mode 100644 include/soc/kendryte/k210-sysctl.h diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 97ef393d0ed0..a4c851ffc6b0 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -30,6 +30,7 @@ config SOC_KENDRYTE select SERIAL_SIFIVE_CONSOLE if TTY select SIFIVE_PLIC select SOC_K210 + select CLK_K210 help This enables support for Kendryte K210 SoC platform hardware. diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c715d4681a0b..07a30a7b90b1 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -359,6 +359,15 @@ config COMMON_CLK_FIXED_MMIO help Support for Memory Mapped IO Fixed clocks +config CLK_K210 + bool "Clock driver for the Kendryte K210 SoC" + depends on RISCV && SOC_KENDRYTE + depends on COMMON_CLK && OF + help + Support for the Kendryte K210 RISC-V SoC clocks. This option + is automatically selected when the SOC_KENDRYTE option is selected + in the "SOC selection" menu. + source "drivers/clk/actions/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/baikal-t1/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index da8fcf147eb1..ccac89e0fdfe 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -69,6 +69,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o +obj-$(CONFIG_CLK_K210) += clk-k210.o # please keep this section sorted lexicographically by directory path name obj-y += actions/ diff --git a/drivers/clk/clk-k210.c b/drivers/clk/clk-k210.c new file mode 100644 index 000000000000..7be5a8cdfef6 --- /dev/null +++ b/drivers/clk/clk-k210.c @@ -0,0 +1,962 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + */ +#define pr_fmt(fmt) "k210-clk: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* + * in0: fixed-rate 26MHz oscillator base clock. + */ +#define K210_IN0_RATE 26000000UL + +/* + * Clocks parameters. + */ +struct k210_clk_cfg { + u8 gate_reg; + u8 gate_bit; + u8 div_reg; + u8 div_shift; + u8 div_width; + u8 div_type; + u8 mux_reg; + u8 mux_bit; +}; + +enum k210_clk_div_type { + DIV_NONE, + DIV_ONE_BASED, + DIV_DOUBLE_ONE_BASED, + DIV_POWER_OF_TWO, +}; + +#define GATE(_reg, _bit) \ + .gate_reg = (_reg), \ + .gate_bit = (_bit) +#define DIV(_reg, _shift, _width, _type) \ + .div_reg = (_reg), \ + .div_shift = (_shift), \ + .div_width = (_width), \ + .div_type = (_type) +#define MUX(_reg, _bit) \ + .mux_reg = (_reg), \ + .mux_bit = (_bit) + +static struct k210_clk_cfg k210_clks[K210_NUM_CLKS] = { + + /* Gated clocks, no mux, no divider */ + [K210_CLK_CPU] = { GATE(K210_SYSCTL_EN_CENT, 0) }, + [K210_CLK_DMA] = { GATE(K210_SYSCTL_EN_PERI, 1) }, + [K210_CLK_FFT] = { GATE(K210_SYSCTL_EN_PERI, 4) }, + [K210_CLK_GPIO] = { GATE(K210_SYSCTL_EN_PERI, 5) }, + [K210_CLK_UART1] = { GATE(K210_SYSCTL_EN_PERI, 16) }, + [K210_CLK_UART2] = { GATE(K210_SYSCTL_EN_PERI, 17) }, + [K210_CLK_UART3] = { GATE(K210_SYSCTL_EN_PERI, 18) }, + [K210_CLK_FPIOA] = { GATE(K210_SYSCTL_EN_PERI, 20) }, + [K210_CLK_SHA] = { GATE(K210_SYSCTL_EN_PERI, 26) }, + [K210_CLK_AES] = { GATE(K210_SYSCTL_EN_PERI, 19) }, + [K210_CLK_OTP] = { GATE(K210_SYSCTL_EN_PERI, 27) }, + [K210_CLK_RTC] = { GATE(K210_SYSCTL_EN_PERI, 29) }, + + /* Gated divider clocks */ + [K210_CLK_SRAM0] = { + GATE(K210_SYSCTL_EN_CENT, 1), + DIV(K210_SYSCTL_THR0, 0, 4, DIV_ONE_BASED) + }, + [K210_CLK_SRAM1] = { + GATE(K210_SYSCTL_EN_CENT, 2), + DIV(K210_SYSCTL_THR0, 4, 4, DIV_ONE_BASED) + }, + [K210_CLK_ROM] = { + GATE(K210_SYSCTL_EN_PERI, 0), + DIV(K210_SYSCTL_THR0, 16, 4, DIV_ONE_BASED) + }, + [K210_CLK_DVP] = { + GATE(K210_SYSCTL_EN_PERI, 3), + DIV(K210_SYSCTL_THR0, 12, 4, DIV_ONE_BASED) + }, + [K210_CLK_APB0] = { + GATE(K210_SYSCTL_EN_CENT, 3), + DIV(K210_SYSCTL_SEL0, 3, 3, DIV_ONE_BASED) + }, + [K210_CLK_APB1] = { + GATE(K210_SYSCTL_EN_CENT, 4), + DIV(K210_SYSCTL_SEL0, 6, 3, DIV_ONE_BASED) + }, + [K210_CLK_APB2] = { + GATE(K210_SYSCTL_EN_CENT, 5), + DIV(K210_SYSCTL_SEL0, 9, 3, DIV_ONE_BASED) + }, + [K210_CLK_AI] = { + GATE(K210_SYSCTL_EN_PERI, 2), + DIV(K210_SYSCTL_THR0, 8, 4, DIV_ONE_BASED) + }, + [K210_CLK_SPI0] = { + GATE(K210_SYSCTL_EN_PERI, 6), + DIV(K210_SYSCTL_THR1, 0, 8, DIV_DOUBLE_ONE_BASED) + }, + [K210_CLK_SPI1] = { + GATE(K210_SYSCTL_EN_PERI, 7), + DIV(K210_SYSCTL_THR1, 8, 8, DIV_DOUBLE_ONE_BASED) + }, + [K210_CLK_SPI2] = { + GATE(K210_SYSCTL_EN_PERI, 8), + DIV(K210_SYSCTL_THR1, 16, 8, DIV_DOUBLE_ONE_BASED) + }, + [K210_CLK_I2C0] = { + GATE(K210_SYSCTL_EN_PERI, 13), + DIV(K210_SYSCTL_THR5, 8, 8, DIV_DOUBLE_ONE_BASED) + }, + [K210_CLK_I2C1] = { + GATE(K210_SYSCTL_EN_PERI, 14), + DIV(K210_SYSCTL_THR5, 16, 8, DIV_DOUBLE_ONE_BASED) + }, + [K210_CLK_I2C2] = { + GATE(K210_SYSCTL_EN_PERI, 15), + DIV(K210_SYSCTL_THR5, 24, 8, DIV_DOUBLE_ONE_BASED) + }, + [K210_CLK_WDT0] = { + GATE(K210_SYSCTL_EN_PERI, 24), + DIV(K210_SYSCTL_THR6, 0, 8, DIV_DOUBLE_ONE_BASED) + }, + [K210_CLK_WDT1] = { + GATE(K210_SYSCTL_EN_PERI, 25), + DIV(K210_SYSCTL_THR6, 8, 8, DIV_DOUBLE_ONE_BASED) + }, + [K210_CLK_I2S0] = { + GATE(K210_SYSCTL_EN_PERI, 10), + DIV(K210_SYSCTL_THR3, 0, 16, DIV_DOUBLE_ONE_BASED) + }, + [K210_CLK_I2S1] = { + GATE(K210_SYSCTL_EN_PERI, 11), + DIV(K210_SYSCTL_THR3, 16, 16, DIV_DOUBLE_ONE_BASED) + }, + [K210_CLK_I2S2] = { + GATE(K210_SYSCTL_EN_PERI, 12), + DIV(K210_SYSCTL_THR4, 0, 16, DIV_DOUBLE_ONE_BASED) + }, + + /* Divider clocks, no gate, no mux */ + [K210_CLK_I2S0_M] = { + DIV(K210_SYSCTL_THR4, 16, 8, DIV_DOUBLE_ONE_BASED) + }, + [K210_CLK_I2S1_M] = { + DIV(K210_SYSCTL_THR4, 24, 8, DIV_DOUBLE_ONE_BASED) + }, + [K210_CLK_I2S2_M] = { + DIV(K210_SYSCTL_THR4, 0, 8, DIV_DOUBLE_ONE_BASED) + }, + + /* Muxed gated divider clocks */ + [K210_CLK_SPI3] = { + GATE(K210_SYSCTL_EN_PERI, 9), + DIV(K210_SYSCTL_THR1, 24, 8, DIV_DOUBLE_ONE_BASED), + MUX(K210_SYSCTL_SEL0, 12) + }, + [K210_CLK_TIMER0] = { + GATE(K210_SYSCTL_EN_PERI, 21), + DIV(K210_SYSCTL_THR2, 0, 8, DIV_DOUBLE_ONE_BASED), + MUX(K210_SYSCTL_SEL0, 13) + }, + [K210_CLK_TIMER1] = { + GATE(K210_SYSCTL_EN_PERI, 22), + DIV(K210_SYSCTL_THR2, 8, 8, DIV_DOUBLE_ONE_BASED), + MUX(K210_SYSCTL_SEL0, 14) + }, + [K210_CLK_TIMER2] = { + GATE(K210_SYSCTL_EN_PERI, 23), + DIV(K210_SYSCTL_THR2, 16, 8, DIV_DOUBLE_ONE_BASED), + MUX(K210_SYSCTL_SEL0, 15) + }, +}; + +/* + * PLL control register bits. + */ +#define K210_PLL_CLKR GENMASK(3, 0) +#define K210_PLL_CLKF GENMASK(9, 4) +#define K210_PLL_CLKOD GENMASK(13, 10) +#define K210_PLL_BWADJ GENMASK(19, 14) +#define K210_PLL_RESET (1 << 20) +#define K210_PLL_PWRD (1 << 21) +#define K210_PLL_INTFB (1 << 22) +#define K210_PLL_BYPASS (1 << 23) +#define K210_PLL_TEST (1 << 24) +#define K210_PLL_EN (1 << 25) +#define K210_PLL_SEL GENMASK(27, 26) /* PLL2 only */ + +/* + * PLL lock register bits. + */ +#define K210_PLL_LOCK 0 +#define K210_PLL_CLEAR_SLIP 2 +#define K210_PLL_TEST_OUT 3 + +/* + * Clock selector register bits. + */ +#define K210_ACLK_SEL BIT(0) +#define K210_ACLK_DIV GENMASK(2, 1) + +/* + * PLLs. + */ +enum k210_pll_id { + K210_PLL0, K210_PLL1, K210_PLL2, K210_PLL_NUM +}; + +struct k210_pll { +enum k210_pll_id id; + /* PLL setup register */ + void __iomem *reg; + + /* Common lock register */ + void __iomem *lock; + + /* Offset and width of lock bits */ + u8 lock_shift; + u8 lock_width; + + struct clk_hw hw; +}; +#define to_k210_pll(hw) container_of(hw, struct k210_pll, hw) + +struct k210_pll_cfg { + /* PLL setup register offset */ + u32 reg; + + /* Offset and width fo the lock bits */ + u8 lock_shift; + u8 lock_width; + + /* PLL setup initial factors */ + u32 r, f, od, bwadj; +}; + +/* + * PLL factors: + * By default, PLL0 runs at 780 MHz and PLL1 at 299 MHz. + * The first 2 sram banks depend on ACLK/CPU clock which is by default + * PLL0 rate divided by 2. Set PLL1 to 390 MHz so that the third sram + * bank has the same clock. + */ +static struct k210_pll_cfg k210_plls_cfg[] = { + { K210_SYSCTL_PLL0, 0, 2, 0, 59, 1, 59 }, /* 780 MHz */ + { K210_SYSCTL_PLL1, 8, 1, 0, 59, 3, 59 }, /* 390 MHz */ + { K210_SYSCTL_PLL2, 16, 1, 0, 22, 1, 22 }, /* 299 MHz */ +}; + +/* + * Clocks data. + */ +struct k210_clk { + void __iomem *regs; + spinlock_t clk_lock; + struct k210_pll plls[K210_PLL_NUM]; + struct clk_hw aclk; + struct clk_hw clks[K210_NUM_CLKS]; + struct clk_hw_onecell_data *clk_data; +}; + +static struct k210_clk *kcl; + +/* + * Set ACLK parent selector: 0 for IN0, 1 for PLL0. + */ +static void k210_aclk_set_selector(u8 sel) +{ + u32 reg = readl(kcl->regs + K210_SYSCTL_SEL0); + + if (sel) + reg |= K210_ACLK_SEL; + else + reg &= K210_ACLK_SEL; + writel(reg, kcl->regs + K210_SYSCTL_SEL0); +} + +static void k210_init_pll(struct k210_pll *pll, enum k210_pll_id id, + void __iomem *base) +{ + pll->id = id; + pll->lock = base + K210_SYSCTL_PLL_LOCK; + pll->reg = base + k210_plls_cfg[id].reg; + pll->lock_shift = k210_plls_cfg[id].lock_shift; + pll->lock_width = k210_plls_cfg[id].lock_width; +} + +static void k210_pll_wait_for_lock(struct k210_pll *pll) +{ + u32 reg, mask = GENMASK(pll->lock_width - 1, 0) << pll->lock_shift; + + while (true) { + reg = readl(pll->lock); + if ((reg & mask) == mask) + break; + + reg |= BIT(pll->lock_shift + K210_PLL_CLEAR_SLIP); + writel(reg, pll->lock); + } +} + +static bool k210_pll_hw_is_enabled(struct k210_pll *pll) +{ + u32 reg = readl(pll->reg); + u32 mask = K210_PLL_PWRD | K210_PLL_EN; + + if (reg & K210_PLL_RESET) + return false; + + return (reg & mask) == mask; +} + +static void k210_pll_enable_hw(struct k210_pll *pll) +{ + struct k210_pll_cfg *pll_cfg = &k210_plls_cfg[pll->id]; + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&kcl->clk_lock, flags); + + if (k210_pll_hw_is_enabled(pll)) + goto unlock; + + if (pll->id == K210_PLL0) { + /* Re-parent aclk to IN0 to keep the CPUs running */ + k210_aclk_set_selector(0); + } + + /* Set factors */ + reg = readl(pll->reg); + reg &= ~GENMASK(19, 0); + reg |= FIELD_PREP(K210_PLL_CLKR, pll_cfg->r); + reg |= FIELD_PREP(K210_PLL_CLKF, pll_cfg->f); + reg |= FIELD_PREP(K210_PLL_CLKOD, pll_cfg->od); + reg |= FIELD_PREP(K210_PLL_BWADJ, pll_cfg->bwadj); + reg |= K210_PLL_PWRD; + writel(reg, pll->reg); + + /* Ensure reset is low before asserting it */ + reg &= ~K210_PLL_RESET; + writel(reg, pll->reg); + reg |= K210_PLL_RESET; + writel(reg, pll->reg); + nop(); + nop(); + reg &= ~K210_PLL_RESET; + writel(reg, pll->reg); + + k210_pll_wait_for_lock(pll); + + reg &= ~K210_PLL_BYPASS; + reg |= K210_PLL_EN; + writel(reg, pll->reg); + + if (pll->id == K210_PLL0) { + /* Re-parent aclk back to PLL0 */ + k210_aclk_set_selector(1); + } +unlock: + spin_unlock_irqrestore(&kcl->clk_lock, flags); +} + +static void k210_pll_disable_hw(struct k210_pll *pll) +{ + unsigned long flags; + u32 reg; + + /* + * Bypassing before powering off is important so child clocks don't stop + * working. This is especially important for pll0, the indirect parent + * of the cpu clock. + */ + spin_lock_irqsave(&kcl->clk_lock, flags); + reg = readl(pll->reg); + reg |= K210_PLL_BYPASS; + writel(reg, pll->reg); + + reg &= ~K210_PLL_PWRD; + reg &= ~K210_PLL_EN; + writel(reg, pll->reg); + spin_unlock_irqrestore(&kcl->clk_lock, flags); +} + +static int k210_pll_enable(struct clk_hw *hw) +{ + k210_pll_enable_hw(to_k210_pll(hw)); + + return 0; +} + +static void k210_pll_disable(struct clk_hw *hw) +{ + k210_pll_disable_hw(to_k210_pll(hw)); +} + +static int k210_pll_is_enabled(struct clk_hw *hw) +{ + return k210_pll_hw_is_enabled(to_k210_pll(hw)); +} + +static int k210_pll_set_parent(struct clk_hw *hw, u8 index) +{ + struct k210_pll *pll = to_k210_pll(hw); + unsigned long flags; + int ret = 0; + u32 reg; + + spin_lock_irqsave(&kcl->clk_lock, flags); + + switch (pll->id) { + case K210_PLL0: + case K210_PLL1: + if (WARN_ON(index != 0)) + ret = -EINVAL; + break; + case K210_PLL2: + if (WARN_ON(index > 2)) { + ret = -EINVAL; + break; + } + reg = readl(pll->reg); + reg &= ~K210_PLL_SEL; + reg |= FIELD_PREP(K210_PLL_SEL, index); + writel(reg, pll->reg); + break; + default: + ret = -EINVAL; + break; + } + + spin_unlock_irqrestore(&kcl->clk_lock, flags); + + return ret; +} + +static u8 k210_pll_get_parent(struct clk_hw *hw) +{ + struct k210_pll *pll = to_k210_pll(hw); + u32 reg; + + switch (pll->id) { + case K210_PLL0: + case K210_PLL1: + return 0; + case K210_PLL2: + reg = readl(pll->reg); + return FIELD_GET(K210_PLL_SEL, reg); + default: + return 0; + } +} + +static unsigned long k210_pll_get_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct k210_pll *pll = to_k210_pll(hw); + u32 reg = readl(pll->reg); + u32 r, f, od; + + if (reg & K210_PLL_BYPASS) + return parent_rate; + + if (!(reg & K210_PLL_PWRD)) + return 0; + + r = FIELD_GET(K210_PLL_CLKR, reg) + 1; + f = FIELD_GET(K210_PLL_CLKF, reg) + 1; + od = FIELD_GET(K210_PLL_CLKOD, reg) + 1; + + return (u64)parent_rate * f / (r * od); +} + +static const struct clk_ops k210_pll_ops = { + .enable = k210_pll_enable, + .disable = k210_pll_disable, + .is_enabled = k210_pll_is_enabled, + .set_parent = k210_pll_set_parent, + .get_parent = k210_pll_get_parent, + .recalc_rate = k210_pll_get_rate, +}; + +static const char *pll_parents[] = { NULL, "pll0", "pll1" }; + +static struct clk_hw *k210_register_pll(enum k210_pll_id id, const char *name, + const char **parent_names, int num_parents, + unsigned long flags) +{ + struct k210_pll *pll = &kcl->plls[id]; + struct clk_init_data init = {}; + int ret; + + init.name = name; + init.parent_names = parent_names; + init.num_parents = num_parents; + init.flags = flags; + init.ops = &k210_pll_ops; + pll->hw.init = &init; + + ret = clk_hw_register(NULL, &pll->hw); + if (ret) + return ERR_PTR(ret); + + return &pll->hw; +} + +static int k210_aclk_set_parent(struct clk_hw *hw, u8 index) +{ + if (WARN_ON(index > 1)) + return -EINVAL; + + k210_aclk_set_selector(index); + + return 0; +} + +static u8 k210_aclk_get_parent(struct clk_hw *hw) +{ + u32 sel = readl(kcl->regs + K210_SYSCTL_SEL0); + + return (sel & K210_ACLK_SEL) ? 1 : 0; +} + +static unsigned long k210_aclk_get_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + u32 reg = readl(kcl->regs + K210_SYSCTL_SEL0); + unsigned int shift; + + if (!(reg & 0x1)) + return parent_rate; + + shift = FIELD_GET(K210_ACLK_DIV, reg); + + return parent_rate / (2UL << shift); +} + +static const struct clk_ops k210_aclk_ops = { + .set_parent = k210_aclk_set_parent, + .get_parent = k210_aclk_get_parent, + .recalc_rate = k210_aclk_get_rate, +}; + +static const char *aclk_parents[] = { NULL, "pll0" }; + +static struct clk_hw *k210_register_aclk(void) +{ + struct clk_init_data init = {}; + int ret; + + init.name = "aclk"; + init.parent_names = aclk_parents; + init.num_parents = 2; + init.flags = 0; + init.ops = &k210_aclk_ops; + kcl->aclk.init = &init; + + ret = clk_hw_register(NULL, &kcl->aclk); + if (ret) + return ERR_PTR(ret); + + return &kcl->aclk; +} + +#define to_k210_clk_id(hw) ((unsigned int)((hw) - &kcl->clks[0])) +#define to_k210_clk_cfg(hw) (&k210_clks[to_k210_clk_id(hw)]) + +static u32 k210_clk_get_div_val(struct k210_clk_cfg *kclk) +{ + u32 reg = readl(kcl->regs + kclk->div_reg); + + return (reg >> kclk->div_shift) & GENMASK(kclk->div_width - 1, 0); +} + +static unsigned long k210_clk_divider(struct k210_clk_cfg *kclk, + u32 div_val) +{ + switch (kclk->div_type) { + case DIV_ONE_BASED: + return div_val + 1; + case DIV_DOUBLE_ONE_BASED: + return (div_val + 1) * 2; + case DIV_POWER_OF_TWO: + return 2UL << div_val; + case DIV_NONE: + default: + return 0; + } +} + +static int k210_clk_enable(struct clk_hw *hw) +{ + struct k210_clk_cfg *kclk = to_k210_clk_cfg(hw); + unsigned long flags; + u32 reg; + + if (!kclk->gate_reg) + return 0; + + spin_lock_irqsave(&kcl->clk_lock, flags); + reg = readl(kcl->regs + kclk->gate_reg); + reg |= BIT(kclk->gate_bit); + writel(reg, kcl->regs + kclk->gate_reg); + spin_unlock_irqrestore(&kcl->clk_lock, flags); + + return 0; +} + +static void k210_clk_disable(struct clk_hw *hw) +{ + struct k210_clk_cfg *kclk = to_k210_clk_cfg(hw); + unsigned long flags; + u32 reg; + + if (!kclk->gate_reg) + return; + + spin_lock_irqsave(&kcl->clk_lock, flags); + reg = readl(kcl->regs + kclk->gate_reg); + reg &= ~BIT(kclk->gate_bit); + writel(reg, kcl->regs + kclk->gate_reg); + spin_unlock_irqrestore(&kcl->clk_lock, flags); +} + +static int k210_clk_is_enabled(struct clk_hw *hw) +{ + struct k210_clk_cfg *kclk = to_k210_clk_cfg(hw); + + if (!kclk->gate_reg) + return 1; + + return readl(kcl->regs + kclk->gate_reg) & BIT(kclk->gate_bit); +} + +static int k210_clk_set_parent(struct clk_hw *hw, u8 index) +{ + struct k210_clk_cfg *kclk = to_k210_clk_cfg(hw); + unsigned long flags; + u32 reg; + + if (!kclk->mux_reg) { + if (WARN_ON(index != 0)) + return -EINVAL; + return 0; + } + + spin_lock_irqsave(&kcl->clk_lock, flags); + reg = readl(kcl->regs + kclk->mux_reg); + if (index) + reg |= BIT(kclk->mux_bit); + else + reg &= ~BIT(kclk->mux_bit); + spin_unlock_irqrestore(&kcl->clk_lock, flags); + + return 0; +} + +static u8 k210_clk_get_parent(struct clk_hw *hw) +{ + struct k210_clk_cfg *kclk = to_k210_clk_cfg(hw); + unsigned long flags; + u32 reg, idx; + + if (!kclk->mux_reg) + return 0; + + spin_lock_irqsave(&kcl->clk_lock, flags); + reg = readl(kcl->regs + kclk->mux_reg); + idx = (reg & BIT(kclk->mux_bit)) ? 1 : 0; + spin_unlock_irqrestore(&kcl->clk_lock, flags); + + return idx; +} + +static unsigned long k210_clk_get_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct k210_clk_cfg *kclk = to_k210_clk_cfg(hw); + unsigned long divider; + + if (!kclk->div_reg) + return parent_rate; + + divider = k210_clk_divider(kclk, k210_clk_get_div_val(kclk)); + if (WARN_ON(!divider)) + return 0; + + return parent_rate / divider; +} + +static const struct clk_ops k210_clk_ops = { + .enable = k210_clk_enable, + .is_enabled = k210_clk_is_enabled, + .disable = k210_clk_disable, + .set_parent = k210_clk_set_parent, + .get_parent = k210_clk_get_parent, + .recalc_rate = k210_clk_get_rate, +}; + +static const char *mux_parents[] = { NULL, "pll0" }; + +static struct clk_hw *k210_register_clk(int id, const char *name, + const char *parent, unsigned long flags) +{ + struct clk_init_data init = {}; + int ret; + + init.name = name; + if (parent) { + init.parent_names = &parent; + init.num_parents = 1; + } else { + init.parent_names = mux_parents; + init.num_parents = 2; + } + init.flags = flags; + init.ops = &k210_clk_ops; + kcl->clks[id].init = &init; + + ret = clk_hw_register(NULL, &kcl->clks[id]); + if (ret) + return ERR_PTR(ret); + + return &kcl->clks[id]; +} + +static void __init k210_clk_init(struct device_node *np) +{ + struct device_node *sysctl_np; + struct clk *in0_clk; + const char *in0; + struct clk_hw **hws; + int i, ret; + + pr_info("%pOFP\n", np); + + kcl = kzalloc(sizeof(*kcl), GFP_KERNEL); + if (!kcl) + return; + + sysctl_np = of_find_compatible_node(NULL, NULL, "kendryte,k210-sysctl"); + if (!sysctl_np) + goto err; + + kcl->regs = of_iomap(sysctl_np, 0); + if (!kcl->regs) + goto err; + + kcl->clk_data = kzalloc(struct_size(kcl->clk_data, hws, K210_NUM_CLKS), + GFP_KERNEL); + if (!kcl->clk_data) + goto err; + + for (i = 0; i < K210_PLL_NUM; i++) + k210_init_pll(&kcl->plls[i], i, kcl->regs); + spin_lock_init(&kcl->clk_lock); + kcl->clk_data->num = K210_NUM_CLKS; + hws = kcl->clk_data->hws; + for (i = 1; i < K210_NUM_CLKS; i++) + hws[i] = ERR_PTR(-EPROBE_DEFER); + + /* + * in0 is the system base fixed-rate 26MHz oscillator which + * should already be defined by the device tree. If it is not, + * create it here. + */ + in0_clk = of_clk_get(np, 0); + if (IS_ERR(in0_clk)) { + pr_warn("%pOFP: in0 oscillator not found\n", np); + hws[K210_CLK_IN0] = + clk_hw_register_fixed_rate(NULL, "in0", NULL, + 0, K210_IN0_RATE); + } else { + hws[K210_CLK_IN0] = __clk_get_hw(in0_clk); + } + if (IS_ERR(hws[K210_CLK_IN0])) { + pr_err("%pOFP: failed to get base oscillator\n", np); + goto err; + } + + in0 = clk_hw_get_name(hws[K210_CLK_IN0]); + aclk_parents[0] = in0; + pll_parents[0] = in0; + mux_parents[0] = in0; + + pr_info("%pOFP: fixed-rate %lu MHz %s base clock\n", + np, clk_hw_get_rate(hws[K210_CLK_IN0]) / 1000000, in0); + + /* PLLs */ + hws[K210_CLK_PLL0] = + k210_register_pll(K210_PLL0, "pll0", pll_parents, 1, 0); + hws[K210_CLK_PLL1] = + k210_register_pll(K210_PLL1, "pll1", pll_parents, 1, 0); + hws[K210_CLK_PLL2] = + k210_register_pll(K210_PLL2, "pll2", pll_parents, 3, 0); + + /* aclk: muxed of in0 and pll0_d, no gate */ + hws[K210_CLK_ACLK] = k210_register_aclk(); + + /* + * Clocks with aclk as source: the CPU clock is obviously critical. + * So is the CLINT clock as the scheduler clocksource. + */ + hws[K210_CLK_CPU] = + k210_register_clk(K210_CLK_CPU, "cpu", "aclk", CLK_IS_CRITICAL); + hws[K210_CLK_CLINT] = + clk_hw_register_fixed_factor(NULL, "clint", "aclk", + CLK_IS_CRITICAL, 1, 50); + hws[K210_CLK_DMA] = + k210_register_clk(K210_CLK_DMA, "dma", "aclk", 0); + hws[K210_CLK_FFT] = + k210_register_clk(K210_CLK_FFT, "fft", "aclk", 0); + hws[K210_CLK_ROM] = + k210_register_clk(K210_CLK_ROM, "rom", "aclk", 0); + hws[K210_CLK_DVP] = + k210_register_clk(K210_CLK_DVP, "dvp", "aclk", 0); + hws[K210_CLK_APB0] = + k210_register_clk(K210_CLK_APB0, "apb0", "aclk", 0); + hws[K210_CLK_APB1] = + k210_register_clk(K210_CLK_APB1, "apb1", "aclk", 0); + hws[K210_CLK_APB2] = + k210_register_clk(K210_CLK_APB2, "apb2", "aclk", 0); + + /* + * There is no sram driver taking a ref on the sram banks clocks. + * So make them critical so they are not disabled due to being unused + * as seen by the clock infrastructure. + */ + hws[K210_CLK_SRAM0] = + k210_register_clk(K210_CLK_SRAM0, + "sram0", "aclk", CLK_IS_CRITICAL); + hws[K210_CLK_SRAM1] = + k210_register_clk(K210_CLK_SRAM1, + "sram1", "aclk", CLK_IS_CRITICAL); + + /* Clocks with PLL0 as source */ + hws[K210_CLK_SPI0] = + k210_register_clk(K210_CLK_SPI0, "spi0", "pll0", 0); + hws[K210_CLK_SPI1] = + k210_register_clk(K210_CLK_SPI1, "spi1", "pll0", 0); + hws[K210_CLK_SPI2] = + k210_register_clk(K210_CLK_SPI2, "spi2", "pll0", 0); + hws[K210_CLK_I2C0] = + k210_register_clk(K210_CLK_I2C0, "i2c0", "pll0", 0); + hws[K210_CLK_I2C1] = + k210_register_clk(K210_CLK_I2C1, "i2c1", "pll0", 0); + hws[K210_CLK_I2C2] = + k210_register_clk(K210_CLK_I2C2, "i2c2", "pll0", 0); + + /* + * Clocks with PLL1 as source: there is only the AI clock for the + * (unused) KPU device. As this clock also drives the aisram bank + * which is used as general memory, make it critical. + */ + hws[K210_CLK_AI] = + k210_register_clk(K210_CLK_AI, "ai", "pll1", CLK_IS_CRITICAL); + + /* Clocks with PLL2 as source */ + hws[K210_CLK_I2S0] = + k210_register_clk(K210_CLK_I2S0, "i2s0", "pll2", 0); + hws[K210_CLK_I2S1] = + k210_register_clk(K210_CLK_I2S1, "i2s1", "pll2", 0); + hws[K210_CLK_I2S2] = + k210_register_clk(K210_CLK_I2S2, "i2s2", "pll2", 0); + hws[K210_CLK_I2S0_M] = + k210_register_clk(K210_CLK_I2S0_M, "i2s0_m", "pll2", 0); + hws[K210_CLK_I2S1_M] = + k210_register_clk(K210_CLK_I2S1_M, "i2s1_m", "pll2", 0); + hws[K210_CLK_I2S2_M] = + k210_register_clk(K210_CLK_I2S2_M, "i2s2_m", "pll2", 0); + + /* Clocks with IN0 as source */ + hws[K210_CLK_WDT0] = + k210_register_clk(K210_CLK_WDT0, "wdt0", in0, 0); + hws[K210_CLK_WDT1] = + k210_register_clk(K210_CLK_WDT1, "wdt1", in0, 0); + hws[K210_CLK_RTC] = + k210_register_clk(K210_CLK_RTC, "rtc", in0, 0); + + /* Clocks with APB0 as source */ + hws[K210_CLK_GPIO] = + k210_register_clk(K210_CLK_GPIO, "gpio", "apb0", 0); + hws[K210_CLK_UART1] = + k210_register_clk(K210_CLK_UART1, "uart1", "apb0", 0); + hws[K210_CLK_UART2] = + k210_register_clk(K210_CLK_UART2, "uart2", "apb0", 0); + hws[K210_CLK_UART3] = + k210_register_clk(K210_CLK_UART3, "uart3", "apb0", 0); + hws[K210_CLK_FPIOA] = + k210_register_clk(K210_CLK_FPIOA, "fpioa", "apb0", 0); + hws[K210_CLK_SHA] = + k210_register_clk(K210_CLK_SHA, "sha", "apb0", 0); + + /* Clocks with APB1 as source */ + hws[K210_CLK_AES] = + k210_register_clk(K210_CLK_AES, "aes", "apb1", 0); + hws[K210_CLK_OTP] = + k210_register_clk(K210_CLK_OTP, "otp", "apb1", 0); + + /* Muxed clocks with in0/pll0 as source */ + hws[K210_CLK_SPI3] = + k210_register_clk(K210_CLK_SPI3, "spi3", NULL, 0); + hws[K210_CLK_TIMER0] = + k210_register_clk(K210_CLK_TIMER0, "timer0", NULL, 0); + hws[K210_CLK_TIMER1] = + k210_register_clk(K210_CLK_TIMER1, "timer1", NULL, 0); + hws[K210_CLK_TIMER2] = + k210_register_clk(K210_CLK_TIMER2, "timer2", NULL, 0); + + for (i = 0; i < K210_NUM_CLKS; i++) { + if (IS_ERR(hws[i])) { + pr_err("%pOFP: register clock %d failed %ld\n", + np, i, PTR_ERR(hws[i])); + goto err; + } + } + + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, kcl->clk_data); + if (ret) + pr_err("%pOFP: add clock provider failed %d\n", np, ret); + + return; +err: + pr_err("%pOFP: clock initialization failed\n", np); + iounmap(kcl->regs); + kfree(kcl->clk_data); + kfree(kcl); + kcl = NULL; +} + +CLK_OF_DECLARE_DRIVER(k210_clk, "kendryte,k210-clk", k210_clk_init); + +/* + * Enable PLL1 to be able to use the AI SRAM. + */ +void k210_clk_early_init(void __iomem *regs) +{ + struct k210_pll pll1; + + /* Make sure aclk selector is set to PLL0 */ + k210_aclk_set_selector(1); + + /* Startup PLL1 to enable the aisram bank for general memory use */ + k210_init_pll(&pll1, K210_PLL1, regs); + k210_pll_enable_hw(&pll1); +} diff --git a/drivers/soc/kendryte/k210-sysctl.c b/drivers/soc/kendryte/k210-sysctl.c index 4608fbca20e1..336f4b119bdd 100644 --- a/drivers/soc/kendryte/k210-sysctl.c +++ b/drivers/soc/kendryte/k210-sysctl.c @@ -3,201 +3,41 @@ * Copyright (c) 2019 Christoph Hellwig. * Copyright (c) 2019 Western Digital Corporation or its affiliates. */ -#include #include -#include #include -#include -#include -#include +#include +#include #include -#define K210_SYSCTL_CLK0_FREQ 26000000UL +#include -/* Registers base address */ -#define K210_SYSCTL_SYSCTL_BASE_ADDR 0x50440000ULL - -/* Registers */ -#define K210_SYSCTL_PLL0 0x08 -#define K210_SYSCTL_PLL1 0x0c -/* clkr: 4bits, clkf1: 6bits, clkod: 4bits, bwadj: 4bits */ -#define PLL_RESET (1 << 20) -#define PLL_PWR (1 << 21) -#define PLL_INTFB (1 << 22) -#define PLL_BYPASS (1 << 23) -#define PLL_TEST (1 << 24) -#define PLL_OUT_EN (1 << 25) -#define PLL_TEST_EN (1 << 26) -#define K210_SYSCTL_PLL_LOCK 0x18 -#define PLL0_LOCK1 (1 << 0) -#define PLL0_LOCK2 (1 << 1) -#define PLL0_SLIP_CLEAR (1 << 2) -#define PLL0_TEST_CLK_OUT (1 << 3) -#define PLL1_LOCK1 (1 << 8) -#define PLL1_LOCK2 (1 << 9) -#define PLL1_SLIP_CLEAR (1 << 10) -#define PLL1_TEST_CLK_OUT (1 << 11) -#define PLL2_LOCK1 (1 << 16) -#define PLL2_LOCK2 (1 << 16) -#define PLL2_SLIP_CLEAR (1 << 18) -#define PLL2_TEST_CLK_OUT (1 << 19) -#define K210_SYSCTL_CLKSEL0 0x20 -#define CLKSEL_ACLK (1 << 0) -#define K210_SYSCTL_CLKEN_CENT 0x28 -#define CLKEN_CPU (1 << 0) -#define CLKEN_SRAM0 (1 << 1) -#define CLKEN_SRAM1 (1 << 2) -#define CLKEN_APB0 (1 << 3) -#define CLKEN_APB1 (1 << 4) -#define CLKEN_APB2 (1 << 5) -#define K210_SYSCTL_CLKEN_PERI 0x2c -#define CLKEN_ROM (1 << 0) -#define CLKEN_DMA (1 << 1) -#define CLKEN_AI (1 << 2) -#define CLKEN_DVP (1 << 3) -#define CLKEN_FFT (1 << 4) -#define CLKEN_GPIO (1 << 5) -#define CLKEN_SPI0 (1 << 6) -#define CLKEN_SPI1 (1 << 7) -#define CLKEN_SPI2 (1 << 8) -#define CLKEN_SPI3 (1 << 9) -#define CLKEN_I2S0 (1 << 10) -#define CLKEN_I2S1 (1 << 11) -#define CLKEN_I2S2 (1 << 12) -#define CLKEN_I2C0 (1 << 13) -#define CLKEN_I2C1 (1 << 14) -#define CLKEN_I2C2 (1 << 15) -#define CLKEN_UART1 (1 << 16) -#define CLKEN_UART2 (1 << 17) -#define CLKEN_UART3 (1 << 18) -#define CLKEN_AES (1 << 19) -#define CLKEN_FPIO (1 << 20) -#define CLKEN_TIMER0 (1 << 21) -#define CLKEN_TIMER1 (1 << 22) -#define CLKEN_TIMER2 (1 << 23) -#define CLKEN_WDT0 (1 << 24) -#define CLKEN_WDT1 (1 << 25) -#define CLKEN_SHA (1 << 26) -#define CLKEN_OTP (1 << 27) -#define CLKEN_RTC (1 << 29) - -struct k210_sysctl { - void __iomem *regs; - struct clk_hw hw; -}; - -static void k210_set_bits(u32 val, void __iomem *reg) -{ - writel(readl(reg) | val, reg); -} - -static void k210_clear_bits(u32 val, void __iomem *reg) -{ - writel(readl(reg) & ~val, reg); -} - -static void k210_pll1_enable(void __iomem *regs) +static int __init k210_sysctl_probe(struct platform_device *pdev) { - u32 val; + struct device *dev = &pdev->dev; + struct clk *pclk; + int ret; - val = readl(regs + K210_SYSCTL_PLL1); - val &= ~GENMASK(19, 0); /* clkr1 = 0 */ - val |= FIELD_PREP(GENMASK(9, 4), 0x3B); /* clkf1 = 59 */ - val |= FIELD_PREP(GENMASK(13, 10), 0x3); /* clkod1 = 3 */ - val |= FIELD_PREP(GENMASK(19, 14), 0x3B); /* bwadj1 = 59 */ - writel(val, regs + K210_SYSCTL_PLL1); + dev_info(dev, "K210 system controller\n"); - k210_clear_bits(PLL_BYPASS, regs + K210_SYSCTL_PLL1); - k210_set_bits(PLL_PWR, regs + K210_SYSCTL_PLL1); - - /* - * Reset the pll. The magic NOPs come from the Kendryte reference SDK. - */ - k210_clear_bits(PLL_RESET, regs + K210_SYSCTL_PLL1); - k210_set_bits(PLL_RESET, regs + K210_SYSCTL_PLL1); - nop(); - nop(); - k210_clear_bits(PLL_RESET, regs + K210_SYSCTL_PLL1); - - for (;;) { - val = readl(regs + K210_SYSCTL_PLL_LOCK); - if (val & PLL1_LOCK2) - break; - writel(val | PLL1_SLIP_CLEAR, regs + K210_SYSCTL_PLL_LOCK); + /* Get power bus clock */ + pclk = devm_clk_get(dev, NULL); + if (IS_ERR(pclk)) { + dev_err(dev, "Get bus clock failed\n"); + return PTR_ERR(pclk); } - k210_set_bits(PLL_OUT_EN, regs + K210_SYSCTL_PLL1); -} - -static unsigned long k210_sysctl_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct k210_sysctl *s = container_of(hw, struct k210_sysctl, hw); - u32 clksel0, pll0; - u64 pll0_freq, clkr0, clkf0, clkod0; - - /* - * If the clock selector is not set, use the base frequency. - * Otherwise, use PLL0 frequency with a frequency divisor. - */ - clksel0 = readl(s->regs + K210_SYSCTL_CLKSEL0); - if (!(clksel0 & CLKSEL_ACLK)) - return K210_SYSCTL_CLK0_FREQ; - - /* - * Get PLL0 frequency: - * freq = base frequency * clkf0 / (clkr0 * clkod0) - */ - pll0 = readl(s->regs + K210_SYSCTL_PLL0); - clkr0 = 1 + FIELD_GET(GENMASK(3, 0), pll0); - clkf0 = 1 + FIELD_GET(GENMASK(9, 4), pll0); - clkod0 = 1 + FIELD_GET(GENMASK(13, 10), pll0); - pll0_freq = clkf0 * K210_SYSCTL_CLK0_FREQ / (clkr0 * clkod0); - - /* Get the frequency divisor from the clock selector */ - return pll0_freq / (2ULL << FIELD_GET(0x00000006, clksel0)); -} - -static const struct clk_ops k210_sysctl_clk_ops = { - .recalc_rate = k210_sysctl_clk_recalc_rate, -}; - -static const struct clk_init_data k210_clk_init_data = { - .name = "k210-sysctl-pll1", - .ops = &k210_sysctl_clk_ops, -}; - -static int k210_sysctl_probe(struct platform_device *pdev) -{ - struct k210_sysctl *s; - int error; - - pr_info("Kendryte K210 SoC sysctl\n"); - - s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL); - if (!s) - return -ENOMEM; - - s->regs = devm_ioremap_resource(&pdev->dev, - platform_get_resource(pdev, IORESOURCE_MEM, 0)); - if (IS_ERR(s->regs)) - return PTR_ERR(s->regs); - - s->hw.init = &k210_clk_init_data; - error = devm_clk_hw_register(&pdev->dev, &s->hw); - if (error) { - dev_err(&pdev->dev, "failed to register clk"); - return error; + ret = clk_prepare_enable(pclk); + if (ret) { + dev_err(dev, "Enable bus clock failed\n"); + return ret; } - error = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_simple_get, - &s->hw); - if (error) { - dev_err(&pdev->dev, "adding clk provider failed\n"); - return error; - } + /* Populate children */ + ret = devm_of_platform_populate(dev); + if (ret) + dev_err(dev, "Populate platform failed %d\n", ret); - return 0; + return ret; } static const struct of_device_id k210_sysctl_of_match[] = { @@ -213,11 +53,22 @@ static struct platform_driver k210_sysctl_driver = { .probe = k210_sysctl_probe, }; +/* + * Most devices on the K210 SoC depend on the early initialization of sysctl + * fpioa and reset child nodes. So initialize this driver early as part of + * the post core initialization. + */ static int __init k210_sysctl_init(void) { return platform_driver_register(&k210_sysctl_driver); } -core_initcall(k210_sysctl_init); +postcore_initcall(k210_sysctl_init); + +/* + * System controller registers base address and size. + */ +#define K210_SYSCTL_BASE_ADDR 0x50440000ULL +#define K210_SYSCTL_BASE_SIZE 0x1000 /* * This needs to be called very early during initialization, given that @@ -225,24 +76,14 @@ core_initcall(k210_sysctl_init); */ static void __init k210_soc_early_init(const void *fdt) { - void __iomem *regs; - - regs = ioremap(K210_SYSCTL_SYSCTL_BASE_ADDR, 0x1000); - if (!regs) - panic("K210 sysctl ioremap"); - - /* Enable PLL1 to make the KPU SRAM useable */ - k210_pll1_enable(regs); - - k210_set_bits(PLL_OUT_EN, regs + K210_SYSCTL_PLL0); + void __iomem *sysctl_base; - k210_set_bits(CLKEN_CPU | CLKEN_SRAM0 | CLKEN_SRAM1, - regs + K210_SYSCTL_CLKEN_CENT); - k210_set_bits(CLKEN_ROM | CLKEN_TIMER0 | CLKEN_RTC, - regs + K210_SYSCTL_CLKEN_PERI); + sysctl_base = ioremap(K210_SYSCTL_BASE_ADDR, K210_SYSCTL_BASE_SIZE); + if (!sysctl_base) + panic("k210-sysctl: ioremap failed"); - k210_set_bits(CLKSEL_ACLK, regs + K210_SYSCTL_CLKSEL0); + k210_clk_early_init(sysctl_base); - iounmap(regs); + iounmap(sysctl_base); } -SOC_EARLY_INIT_DECLARE(generic_k210, "kendryte,k210", k210_soc_early_init); +SOC_EARLY_INIT_DECLARE(k210_soc, "kendryte,k210", k210_soc_early_init); diff --git a/include/soc/kendryte/k210-sysctl.h b/include/soc/kendryte/k210-sysctl.h new file mode 100644 index 000000000000..73e38a8fc31d --- /dev/null +++ b/include/soc/kendryte/k210-sysctl.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + */ +#ifndef K210_SYSCTL_H +#define K210_SYSCTL_H + +void k210_clk_early_init(void __iomem *regs); + +#endif From patchwork Sat Nov 7 08:14:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396072 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=Jcw7g+e2; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqnH67t0z9sTD for ; Sat, 7 Nov 2020 19:15:15 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728124AbgKGIPP (ORCPT ); Sat, 7 Nov 2020 03:15:15 -0500 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:57208 "EHLO esa3.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727896AbgKGIPP (ORCPT ); Sat, 7 Nov 2020 03:15:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; 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07 Nov 2020 16:15:14 +0800 IronPort-SDR: 6elAszZyP8FpFDX1xg+oJE18MDif54flIfosvdl6gb2aS7zEe5oXTKo+loDT1QJUWFspKUcFYZ QIJ2yr5nQW+1K6Efr42VtHkpCuZm5rTjpBc1oBQe0atd9HYye7t7O/uGPC4xNr6mIMX1Ep1sVm L5qt4NwgNrYB+oNTjk2fYBMmRd59zntPGa55mF/ZgpiK0tlExxxSuJKmXxYy9YoC4xIn26Ge5r ObYdYmeW/b5XHvhEDPKnepaHN7dLqfRrtlL8/EkDXb7ygDyDkMIttw9QQoo5iP6dfB5qlaeq1r mLrSRj16X4HLtxhQu2GXjdLO Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2020 00:00:05 -0800 IronPort-SDR: cq//chzutH4wXylm4H8jmtnMe1aNpH0Uu4Whn6FkmWJy6febas7+Y3rO0Zc90N9BsNIrZx3kH+ v0gyxR4aAqacsoAftph7QwdLBEw5g7puc3sMfZIwrUqLoOxw+FCfCHSfQn1Y6ZoX5QEeuT0frw OqacY0epJSaqMfB0cOwlkjduc04QBxwAUoNYVXLY1GFPqLeBMqRMMO7gLHiiaCKFC0KhcF27cg 5JWPtHYiThqG/mY+GP6D55fS00eOvc5QNPI5tFFF7HbsnDjggeQvLLge1PS0lf+dd3/VF5MbSA e5k= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:15:12 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 19/32] riscv: Add Kendryte K210 SoC reset controller Date: Sat, 7 Nov 2020 17:14:07 +0900 Message-Id: <20201107081420.60325-20-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add a reset controller driver for the Kendryte K210 SoC. This driver relies on its syscon compatible parent node for its register mapping. Automatically select this driver for compilation when the SOC_KENDRYTE option is selected. Signed-off-by: Damien Le Moal Reviewed-by: Sean Anderson --- arch/riscv/Kconfig.socs | 3 + drivers/reset/Kconfig | 9 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-k210.c | 186 +++++++++++++++++++++++++++++++++++++ 4 files changed, 199 insertions(+) create mode 100644 drivers/reset/reset-k210.c diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index a4c851ffc6b0..4d8e66d0556a 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -31,6 +31,9 @@ config SOC_KENDRYTE select SIFIVE_PLIC select SOC_K210 select CLK_K210 + select ARCH_HAS_RESET_CONTROLLER + select RESET_CONTROLLER + select RESET_K210 help This enables support for Kendryte K210 SoC platform hardware. diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 07d162b179fc..c943051b5fc8 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -245,6 +245,15 @@ config RESET_ZYNQ help This enables the reset controller driver for Xilinx Zynq SoCs. +config RESET_K210 + bool "Reset controller driver for Kendryte K210 SoC" + depends on RISCV && SOC_KENDRYTE + depends on OF && MFD_SYSCON + help + Support for the Kendryte K210 RISC-V SoC reset controller. If + Say Y if you want to control reset signals provided by this + controller. + source "drivers/reset/sti/Kconfig" source "drivers/reset/hisilicon/Kconfig" source "drivers/reset/tegra/Kconfig" diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 16947610cc3b..1730a31e6871 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -33,4 +33,5 @@ obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_RESET_UNIPHIER_GLUE) += reset-uniphier-glue.o obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o obj-$(CONFIG_ARCH_ZYNQMP) += reset-zynqmp.o +obj-$(CONFIG_RESET_K210) += reset-k210.o diff --git a/drivers/reset/reset-k210.c b/drivers/reset/reset-k210.c new file mode 100644 index 000000000000..b6401aef2923 --- /dev/null +++ b/drivers/reset/reset-k210.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +struct k210_rst { + struct regmap *map; + u32 offset; + u32 mask; + u32 assert_high; + struct reset_controller_dev rcdev; +}; + +static inline struct k210_rst * +to_k210_rst(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct k210_rst, rcdev); +} + +static inline int k210_rst_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct k210_rst *ksr = to_k210_rst(rcdev); + u32 bit = BIT(id); + + if (!(bit & ksr->mask)) { + dev_err(rcdev->dev, "Invalid assert id %lu\n", id); + return -EINVAL; + } + + dev_dbg(rcdev->dev, "assert %s %lu\n", + ksr->assert_high ? "high" : "low", id); + + regmap_update_bits(ksr->map, ksr->offset, bit, + ksr->assert_high ? bit : 0); + + return 0; +} + +static inline int k210_rst_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct k210_rst *ksr = to_k210_rst(rcdev); + u32 bit = BIT(id); + + if (!(bit & ksr->mask)) { + dev_err(rcdev->dev, "Invalid deassert id %lu\n", id); + return -EINVAL; + } + + dev_dbg(rcdev->dev, "deassert %s %lu\n", + ksr->assert_high ? "high" : "low", id); + + regmap_update_bits(ksr->map, ksr->offset, bit, + ksr->assert_high ? 0 : bit); + + return 0; +} + +static int k210_rst_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct k210_rst *ksr = to_k210_rst(rcdev); + int ret; + + dev_dbg(rcdev->dev, "reset %s %lu\n", + ksr->assert_high ? "high" : "low", id); + + ret = k210_rst_assert(rcdev, id); + if (ret == 0) { + udelay(10); + ret = k210_rst_deassert(rcdev, id); + } + + return ret; +} + +static int k210_rst_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct k210_rst *ksr = to_k210_rst(rcdev); + u32 reg, bit = BIT(id); + int ret; + + if (!(bit & ksr->mask)) { + dev_err(rcdev->dev, "Invalid reset %lx\n", id); + return -EINVAL; + } + + ret = regmap_read(ksr->map, ksr->offset, ®); + if (ret) + return ret; + + if (ksr->assert_high) + return ret & bit; + + return !(ret & bit); +} + +static const struct reset_control_ops k210_rst_ops = { + .assert = k210_rst_assert, + .deassert = k210_rst_deassert, + .reset = k210_rst_reset, + .status = k210_rst_status, +}; + +static int __init k210_rst_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct k210_rst *ksr; + int ret, nr_resets; + + dev_info(dev, "K210 reset controller\n"); + + ksr = devm_kzalloc(dev, sizeof(*ksr), GFP_KERNEL); + if (!ksr) + return -ENOMEM; + + ksr->map = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap"); + if (IS_ERR(ksr->map)) { + ksr->map = syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(ksr->map)) { + dev_err(dev, "get register map failed\n"); + return PTR_ERR(ksr->map); + } + } + + ret = of_property_read_u32(dev->of_node, "offset", &ksr->offset); + ret = of_property_read_u32(dev->of_node, "assert-high", + &ksr->assert_high); + if (ret) { + dev_err(dev, "unable to read 'offset' and 'assert-high'\n"); + return -EINVAL; + } + + ret = of_property_read_u32(dev->of_node, "mask", &ksr->mask); + if (ret) { + /* Use default mask */ + ksr->mask = 0x27FFFFFF; + } + nr_resets = fls(ksr->mask); + if (!nr_resets) { + dev_err(dev, "Invalid mask 0x%08x\n", ksr->mask); + return -EINVAL; + } + + ksr->rcdev.owner = THIS_MODULE; + ksr->rcdev.dev = dev; + ksr->rcdev.of_node = dev->of_node; + ksr->rcdev.nr_resets = nr_resets; + ksr->rcdev.ops = &k210_rst_ops; + + return devm_reset_controller_register(dev, &ksr->rcdev); +} + +static const struct of_device_id k210_rst_dt_ids[] = { + { .compatible = "kendryte,k210-rst" }, +}; + +static struct platform_driver k210_rst_driver = { + .probe = k210_rst_probe, + .driver = { + .name = "k210-rst", + .of_match_table = k210_rst_dt_ids, + }, +}; + +/* + * Most devices on the K210 SoC need reset as part of their initialization. + * So initialize this driver early as part of the post core initialization. + */ +static int __init k210_rst_init(void) +{ + return platform_driver_register(&k210_rst_driver); +} +postcore_initcall(k210_rst_init); From patchwork Sat Nov 7 08:14:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396073 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; 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07 Nov 2020 00:00:08 -0800 IronPort-SDR: nqkq6N2Ki3bg5tj4gCcDEzcFwq7OavLAU6nmICvjBc9/ZFgfmCIH56zzD6eMjfIvGyaDJZdxIA P07vtuSXBjkv7A+RgMyndswQ1nmhHwZZQ8jydI8YMlnMCwDZhJJWPf7FdUSkkQ7ohvCO4dEf/7 Sd5zNrJO1zdaqnEuUOlQ6ORZwB3mHbmDSuUhJ9+IK5vw0VINZip5LXvPuGmsCAwqmAXAaKhSWX kAHWFY8ShnGUFCUsTIO+w6184KWjfrYIxT0ZcgMrvZ2YP8LSTfDgKNuQFz3um9dYVK/LP1n68p APw= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:15:15 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 20/32] riscv: Add Kendryte K210 FPIOA pinctrl driver Date: Sat, 7 Nov 2020 17:14:08 +0900 Message-Id: <20201107081420.60325-21-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add the pinctrl-k210.c pinctrl driver for the Kendryte K210 FPIOA (fully programmable IO array) to allow configuring the SoC pin functions. The K210 has 48 programmable pins which can take any of 256 possible functions. This patch is inspired from the k210 pinctrl driver for the u-boot project and contains many direct contributions from Sean Anderson. Signed-off-by: Sean Anderson Signed-off-by: Damien Le Moal --- arch/riscv/Kconfig.socs | 2 + drivers/pinctrl/Kconfig | 15 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-k210.c | 999 +++++++++++++++++++++++++++++++++ 4 files changed, 1017 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-k210.c diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 4d8e66d0556a..56ba82a64e18 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -34,6 +34,8 @@ config SOC_KENDRYTE select ARCH_HAS_RESET_CONTROLLER select RESET_CONTROLLER select RESET_K210 + select PINCTRL + select PINCTRL_K210 help This enables support for Kendryte K210 SoC platform hardware. diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 815095326e2d..a5073afb8bfe 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -374,6 +374,21 @@ config PINCTRL_OCELOT select OF_GPIO select REGMAP_MMIO +config PINCTRL_K210 + bool "Pinctrl driver for the Kendryte K210 SoC" + depends on RISCV && SOC_KENDRYTE + depends on OF && HAS_IOMEM + select PINMUX + select GENERIC_PINCONF + select GPIOLIB + select OF_GPIO + select REGMAP_MMIO + help + Add support for the Kendryte K210 RISC-V SOC Field Programmable + IO Array (FPIOA) controller. Support for this controller is + automatically selected when the SOC_KENDRYTE option is selected + in the "SOC selection" menu. + source "drivers/pinctrl/actions/Kconfig" source "drivers/pinctrl/aspeed/Kconfig" source "drivers/pinctrl/bcm/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index f53933b2ff02..d6f913adb04a 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o +obj-$(CONFIG_PINCTRL_K210) += pinctrl-k210.o obj-y += actions/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ diff --git a/drivers/pinctrl/pinctrl-k210.c b/drivers/pinctrl/pinctrl-k210.c new file mode 100644 index 000000000000..48741023fcf7 --- /dev/null +++ b/drivers/pinctrl/pinctrl-k210.c @@ -0,0 +1,999 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2020 Sean Anderson + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "core.h" +#include "pinconf.h" +#include "pinctrl-utils.h" + +/* + * The K210 only implements 8 drive levels, even though + * there is register space for 16 + */ +#define K210_PC_DRIVE_MASK GENMASK(11, 8) +#define K210_PC_DRIVE_SHIFT 8 +#define K210_PC_DRIVE_0 (0 << K210_PC_DRIVE_SHIFT) +#define K210_PC_DRIVE_1 (1 << K210_PC_DRIVE_SHIFT) +#define K210_PC_DRIVE_2 (2 << K210_PC_DRIVE_SHIFT) +#define K210_PC_DRIVE_3 (3 << K210_PC_DRIVE_SHIFT) +#define K210_PC_DRIVE_4 (4 << K210_PC_DRIVE_SHIFT) +#define K210_PC_DRIVE_5 (5 << K210_PC_DRIVE_SHIFT) +#define K210_PC_DRIVE_6 (6 << K210_PC_DRIVE_SHIFT) +#define K210_PC_DRIVE_7 (7 << K210_PC_DRIVE_SHIFT) +#define K210_PC_DRIVE_MAX 7 +#define K210_PC_MODE_MASK GENMASK(23, 12) + +/* + * output enabled == PC_OE & (PC_OE_INV ^ FUNCTION_OE) + * where FUNCTION_OE is a physical signal from the function. + */ +#define K210_PC_OE BIT(12) /* Output Enable */ +#define K210_PC_OE_INV BIT(13) /* INVert Output Enable */ +#define K210_PC_DO_OE BIT(14) /* set Data Out to Output Enable sig */ +#define K210_PC_DO_INV BIT(15) /* INVert final Data Output */ +#define K210_PC_PU BIT(16) /* Pull Up */ +#define K210_PC_PD BIT(17) /* Pull Down */ +/* Strong pull up not implemented on K210 */ +#define K210_PC_SL BIT(19) /* reduce SLew rate */ +/* Same semantics as OE above */ +#define K210_PC_IE BIT(20) /* Input Enable */ +#define K210_PC_IE_INV BIT(21) /* INVert Input Enable */ +#define K210_PC_DI_INV BIT(22) /* INVert Data Input */ +#define K210_PC_ST BIT(23) /* Schmitt Trigger */ +#define K210_PC_DI BIT(31) /* raw Data Input */ + +#define K210_PC_BIAS_MASK (K210_PC_PU & K210_PC_PD) + +#define K210_PC_MODE_IN (K210_PC_IE | K210_PC_ST) +#define K210_PC_MODE_OUT (K210_PC_DRIVE_7 | K210_PC_OE) +#define K210_PC_MODE_I2C (K210_PC_MODE_IN | K210_PC_SL | \ + K210_PC_OE | K210_PC_PU) +#define K210_PC_MODE_SCCB (K210_PC_MODE_I2C | \ + K210_PC_OE_INV | K210_PC_IE_INV) +#define K210_PC_MODE_SPI (K210_PC_MODE_IN | K210_PC_IE_INV | \ + K210_PC_MODE_OUT | K210_PC_OE_INV) +#define K210_PC_MODE_GPIO (K210_PC_MODE_IN | K210_PC_MODE_OUT) + +#define K210_PG_FUNC GENMASK(7, 0) +#define K210_PG_DO BIT(8) +#define K210_PG_PIN GENMASK(22, 16) + +/* + * struct k210_fpioa: Kendryte K210 FPIOA memory mapped registers + * @pins: 48 32-bits IO pin registers + * @tie_en: 256 (one per function) input tie enable bits + * @tie_val: 256 (one per function) input tie value bits + */ +struct k210_fpioa { + u32 pins[48]; + u32 tie_en[8]; + u32 tie_val[8]; +}; + +struct k210_fpioa_data { + + struct device *dev; + struct pinctrl_dev *pctl; + + struct k210_fpioa __iomem *fpioa; + struct regmap *sysctl_map; + u32 power_offset; + struct clk *clk; + struct clk *pclk; +}; + +#define K210_PIN(i) [i] = PINCTRL_PIN(i, "IO_" #i) + +static const struct pinctrl_pin_desc k210_pins[] = { + K210_PIN(0), K210_PIN(1), K210_PIN(2), + K210_PIN(3), K210_PIN(4), K210_PIN(5), + K210_PIN(6), K210_PIN(7), K210_PIN(8), + K210_PIN(9), K210_PIN(10), K210_PIN(11), + K210_PIN(12), K210_PIN(13), K210_PIN(14), + K210_PIN(15), K210_PIN(16), K210_PIN(17), + K210_PIN(18), K210_PIN(19), K210_PIN(20), + K210_PIN(21), K210_PIN(22), K210_PIN(23), + K210_PIN(24), K210_PIN(25), K210_PIN(26), + K210_PIN(27), K210_PIN(28), K210_PIN(29), + K210_PIN(30), K210_PIN(31), K210_PIN(32), + K210_PIN(33), K210_PIN(34), K210_PIN(35), + K210_PIN(36), K210_PIN(37), K210_PIN(38), + K210_PIN(39), K210_PIN(40), K210_PIN(41), + K210_PIN(42), K210_PIN(43), K210_PIN(44), + K210_PIN(45), K210_PIN(46), K210_PIN(47) +}; + +#define K210_NPINS ARRAY_SIZE(k210_pins) + +/* + * Pin groups: each of the 48 programmable pins is a group. + * To this are added 8 power domain groups, which for the purposes of + * the pin subsystem, contain no pins. The power domain groups only exist + * to set the power level. The id should never be used (since there are + * no pins 48-55). + */ +#define K210_PIN_NAME(i) [i] = k210_pins[i].name +static const char *const k210_group_names[] = { + /* The first 48 groups are for pins, one each */ + K210_PIN_NAME(0), K210_PIN_NAME(1), K210_PIN_NAME(2), + K210_PIN_NAME(3), K210_PIN_NAME(4), K210_PIN_NAME(5), + K210_PIN_NAME(6), K210_PIN_NAME(7), K210_PIN_NAME(8), + K210_PIN_NAME(9), K210_PIN_NAME(10), K210_PIN_NAME(11), + K210_PIN_NAME(12), K210_PIN_NAME(13), K210_PIN_NAME(14), + K210_PIN_NAME(15), K210_PIN_NAME(16), K210_PIN_NAME(17), + K210_PIN_NAME(18), K210_PIN_NAME(19), K210_PIN_NAME(20), + K210_PIN_NAME(21), K210_PIN_NAME(22), K210_PIN_NAME(23), + K210_PIN_NAME(24), K210_PIN_NAME(25), K210_PIN_NAME(26), + K210_PIN_NAME(27), K210_PIN_NAME(28), K210_PIN_NAME(29), + K210_PIN_NAME(30), K210_PIN_NAME(31), K210_PIN_NAME(32), + K210_PIN_NAME(33), K210_PIN_NAME(34), K210_PIN_NAME(35), + K210_PIN_NAME(36), K210_PIN_NAME(37), K210_PIN_NAME(38), + K210_PIN_NAME(39), K210_PIN_NAME(40), K210_PIN_NAME(41), + K210_PIN_NAME(42), K210_PIN_NAME(43), K210_PIN_NAME(44), + K210_PIN_NAME(45), K210_PIN_NAME(46), K210_PIN_NAME(47), + [48] = "A0", [49] = "A1", [50] = "A2", + [51] = "B3", [52] = "B4", [53] = "B5", + [54] = "C6", [55] = "C7" +}; + +#define K210_NGROUPS ARRAY_SIZE(k210_group_names) + +enum k210_pinctrl_mode_id { + K210_PC_DEFAULT_DISABLED, + K210_PC_DEFAULT_IN, + K210_PC_DEFAULT_IN_TIE, + K210_PC_DEFAULT_OUT, + K210_PC_DEFAULT_I2C, + K210_PC_DEFAULT_SCCB, + K210_PC_DEFAULT_SPI, + K210_PC_DEFAULT_GPIO, + K210_PC_DEFAULT_INT13, +}; + +#define K210_PC_DEFAULT(mode) \ + [K210_PC_DEFAULT_##mode] = K210_PC_MODE_##mode + +static const u32 k210_pinconf_mode_id_to_mode[] = { + [K210_PC_DEFAULT_DISABLED] = 0, + K210_PC_DEFAULT(IN), + [K210_PC_DEFAULT_IN_TIE] = K210_PC_MODE_IN, + K210_PC_DEFAULT(OUT), + K210_PC_DEFAULT(I2C), + K210_PC_DEFAULT(SCCB), + K210_PC_DEFAULT(SPI), + K210_PC_DEFAULT(GPIO), + [K210_PC_DEFAULT_INT13] = K210_PC_MODE_IN | K210_PC_PU, +}; + +#undef DEFAULT + +/* + * Pin functions configuration information. + */ +struct k210_pcf_info { + char name[15]; + u8 mode_id; +}; + +#define K210_FUNC(id, mode) \ + [K210_PCF_##id] = { \ + .name = #id, \ + .mode_id = K210_PC_DEFAULT_##mode \ + } + +static const struct k210_pcf_info k210_pcf_infos[] = { + K210_FUNC(JTAG_TCLK, IN), + K210_FUNC(JTAG_TDI, IN), + K210_FUNC(JTAG_TMS, IN), + K210_FUNC(JTAG_TDO, OUT), + K210_FUNC(SPI0_D0, SPI), + K210_FUNC(SPI0_D1, SPI), + K210_FUNC(SPI0_D2, SPI), + K210_FUNC(SPI0_D3, SPI), + K210_FUNC(SPI0_D4, SPI), + K210_FUNC(SPI0_D5, SPI), + K210_FUNC(SPI0_D6, SPI), + K210_FUNC(SPI0_D7, SPI), + K210_FUNC(SPI0_SS0, OUT), + K210_FUNC(SPI0_SS1, OUT), + K210_FUNC(SPI0_SS2, OUT), + K210_FUNC(SPI0_SS3, OUT), + K210_FUNC(SPI0_ARB, IN_TIE), + K210_FUNC(SPI0_SCLK, OUT), + K210_FUNC(UARTHS_RX, IN), + K210_FUNC(UARTHS_TX, OUT), + K210_FUNC(RESV6, IN), + K210_FUNC(RESV7, IN), + K210_FUNC(CLK_SPI1, OUT), + K210_FUNC(CLK_I2C1, OUT), + K210_FUNC(GPIOHS0, GPIO), + K210_FUNC(GPIOHS1, GPIO), + K210_FUNC(GPIOHS2, GPIO), + K210_FUNC(GPIOHS3, GPIO), + K210_FUNC(GPIOHS4, GPIO), + K210_FUNC(GPIOHS5, GPIO), + K210_FUNC(GPIOHS6, GPIO), + K210_FUNC(GPIOHS7, GPIO), + K210_FUNC(GPIOHS8, GPIO), + K210_FUNC(GPIOHS9, GPIO), + K210_FUNC(GPIOHS10, GPIO), + K210_FUNC(GPIOHS11, GPIO), + K210_FUNC(GPIOHS12, GPIO), + K210_FUNC(GPIOHS13, GPIO), + K210_FUNC(GPIOHS14, GPIO), + K210_FUNC(GPIOHS15, GPIO), + K210_FUNC(GPIOHS16, GPIO), + K210_FUNC(GPIOHS17, GPIO), + K210_FUNC(GPIOHS18, GPIO), + K210_FUNC(GPIOHS19, GPIO), + K210_FUNC(GPIOHS20, GPIO), + K210_FUNC(GPIOHS21, GPIO), + K210_FUNC(GPIOHS22, GPIO), + K210_FUNC(GPIOHS23, GPIO), + K210_FUNC(GPIOHS24, GPIO), + K210_FUNC(GPIOHS25, GPIO), + K210_FUNC(GPIOHS26, GPIO), + K210_FUNC(GPIOHS27, GPIO), + K210_FUNC(GPIOHS28, GPIO), + K210_FUNC(GPIOHS29, GPIO), + K210_FUNC(GPIOHS30, GPIO), + K210_FUNC(GPIOHS31, GPIO), + K210_FUNC(GPIO0, GPIO), + K210_FUNC(GPIO1, GPIO), + K210_FUNC(GPIO2, GPIO), + K210_FUNC(GPIO3, GPIO), + K210_FUNC(GPIO4, GPIO), + K210_FUNC(GPIO5, GPIO), + K210_FUNC(GPIO6, GPIO), + K210_FUNC(GPIO7, GPIO), + K210_FUNC(UART1_RX, IN), + K210_FUNC(UART1_TX, OUT), + K210_FUNC(UART2_RX, IN), + K210_FUNC(UART2_TX, OUT), + K210_FUNC(UART3_RX, IN), + K210_FUNC(UART3_TX, OUT), + K210_FUNC(SPI1_D0, SPI), + K210_FUNC(SPI1_D1, SPI), + K210_FUNC(SPI1_D2, SPI), + K210_FUNC(SPI1_D3, SPI), + K210_FUNC(SPI1_D4, SPI), + K210_FUNC(SPI1_D5, SPI), + K210_FUNC(SPI1_D6, SPI), + K210_FUNC(SPI1_D7, SPI), + K210_FUNC(SPI1_SS0, OUT), + K210_FUNC(SPI1_SS1, OUT), + K210_FUNC(SPI1_SS2, OUT), + K210_FUNC(SPI1_SS3, OUT), + K210_FUNC(SPI1_ARB, IN_TIE), + K210_FUNC(SPI1_SCLK, OUT), + K210_FUNC(SPI2_D0, SPI), + K210_FUNC(SPI2_SS, IN), + K210_FUNC(SPI2_SCLK, IN), + K210_FUNC(I2S0_MCLK, OUT), + K210_FUNC(I2S0_SCLK, OUT), + K210_FUNC(I2S0_WS, OUT), + K210_FUNC(I2S0_IN_D0, IN), + K210_FUNC(I2S0_IN_D1, IN), + K210_FUNC(I2S0_IN_D2, IN), + K210_FUNC(I2S0_IN_D3, IN), + K210_FUNC(I2S0_OUT_D0, OUT), + K210_FUNC(I2S0_OUT_D1, OUT), + K210_FUNC(I2S0_OUT_D2, OUT), + K210_FUNC(I2S0_OUT_D3, OUT), + K210_FUNC(I2S1_MCLK, OUT), + K210_FUNC(I2S1_SCLK, OUT), + K210_FUNC(I2S1_WS, OUT), + K210_FUNC(I2S1_IN_D0, IN), + K210_FUNC(I2S1_IN_D1, IN), + K210_FUNC(I2S1_IN_D2, IN), + K210_FUNC(I2S1_IN_D3, IN), + K210_FUNC(I2S1_OUT_D0, OUT), + K210_FUNC(I2S1_OUT_D1, OUT), + K210_FUNC(I2S1_OUT_D2, OUT), + K210_FUNC(I2S1_OUT_D3, OUT), + K210_FUNC(I2S2_MCLK, OUT), + K210_FUNC(I2S2_SCLK, OUT), + K210_FUNC(I2S2_WS, OUT), + K210_FUNC(I2S2_IN_D0, IN), + K210_FUNC(I2S2_IN_D1, IN), + K210_FUNC(I2S2_IN_D2, IN), + K210_FUNC(I2S2_IN_D3, IN), + K210_FUNC(I2S2_OUT_D0, OUT), + K210_FUNC(I2S2_OUT_D1, OUT), + K210_FUNC(I2S2_OUT_D2, OUT), + K210_FUNC(I2S2_OUT_D3, OUT), + K210_FUNC(RESV0, DISABLED), + K210_FUNC(RESV1, DISABLED), + K210_FUNC(RESV2, DISABLED), + K210_FUNC(RESV3, DISABLED), + K210_FUNC(RESV4, DISABLED), + K210_FUNC(RESV5, DISABLED), + K210_FUNC(I2C0_SCLK, I2C), + K210_FUNC(I2C0_SDA, I2C), + K210_FUNC(I2C1_SCLK, I2C), + K210_FUNC(I2C1_SDA, I2C), + K210_FUNC(I2C2_SCLK, I2C), + K210_FUNC(I2C2_SDA, I2C), + K210_FUNC(DVP_XCLK, OUT), + K210_FUNC(DVP_RST, OUT), + K210_FUNC(DVP_PWDN, OUT), + K210_FUNC(DVP_VSYNC, IN), + K210_FUNC(DVP_HSYNC, IN), + K210_FUNC(DVP_PCLK, IN), + K210_FUNC(DVP_D0, IN), + K210_FUNC(DVP_D1, IN), + K210_FUNC(DVP_D2, IN), + K210_FUNC(DVP_D3, IN), + K210_FUNC(DVP_D4, IN), + K210_FUNC(DVP_D5, IN), + K210_FUNC(DVP_D6, IN), + K210_FUNC(DVP_D7, IN), + K210_FUNC(SCCB_SCLK, SCCB), + K210_FUNC(SCCB_SDA, SCCB), + K210_FUNC(UART1_CTS, IN), + K210_FUNC(UART1_DSR, IN), + K210_FUNC(UART1_DCD, IN), + K210_FUNC(UART1_RI, IN), + K210_FUNC(UART1_SIR_IN, IN), + K210_FUNC(UART1_DTR, OUT), + K210_FUNC(UART1_RTS, OUT), + K210_FUNC(UART1_OUT2, OUT), + K210_FUNC(UART1_OUT1, OUT), + K210_FUNC(UART1_SIR_OUT, OUT), + K210_FUNC(UART1_BAUD, OUT), + K210_FUNC(UART1_RE, OUT), + K210_FUNC(UART1_DE, OUT), + K210_FUNC(UART1_RS485_EN, OUT), + K210_FUNC(UART2_CTS, IN), + K210_FUNC(UART2_DSR, IN), + K210_FUNC(UART2_DCD, IN), + K210_FUNC(UART2_RI, IN), + K210_FUNC(UART2_SIR_IN, IN), + K210_FUNC(UART2_DTR, OUT), + K210_FUNC(UART2_RTS, OUT), + K210_FUNC(UART2_OUT2, OUT), + K210_FUNC(UART2_OUT1, OUT), + K210_FUNC(UART2_SIR_OUT, OUT), + K210_FUNC(UART2_BAUD, OUT), + K210_FUNC(UART2_RE, OUT), + K210_FUNC(UART2_DE, OUT), + K210_FUNC(UART2_RS485_EN, OUT), + K210_FUNC(UART3_CTS, IN), + K210_FUNC(UART3_DSR, IN), + K210_FUNC(UART3_DCD, IN), + K210_FUNC(UART3_RI, IN), + K210_FUNC(UART3_SIR_IN, IN), + K210_FUNC(UART3_DTR, OUT), + K210_FUNC(UART3_RTS, OUT), + K210_FUNC(UART3_OUT2, OUT), + K210_FUNC(UART3_OUT1, OUT), + K210_FUNC(UART3_SIR_OUT, OUT), + K210_FUNC(UART3_BAUD, OUT), + K210_FUNC(UART3_RE, OUT), + K210_FUNC(UART3_DE, OUT), + K210_FUNC(UART3_RS485_EN, OUT), + K210_FUNC(TIMER0_TOGGLE1, OUT), + K210_FUNC(TIMER0_TOGGLE2, OUT), + K210_FUNC(TIMER0_TOGGLE3, OUT), + K210_FUNC(TIMER0_TOGGLE4, OUT), + K210_FUNC(TIMER1_TOGGLE1, OUT), + K210_FUNC(TIMER1_TOGGLE2, OUT), + K210_FUNC(TIMER1_TOGGLE3, OUT), + K210_FUNC(TIMER1_TOGGLE4, OUT), + K210_FUNC(TIMER2_TOGGLE1, OUT), + K210_FUNC(TIMER2_TOGGLE2, OUT), + K210_FUNC(TIMER2_TOGGLE3, OUT), + K210_FUNC(TIMER2_TOGGLE4, OUT), + K210_FUNC(CLK_SPI2, OUT), + K210_FUNC(CLK_I2C2, OUT), + K210_FUNC(INTERNAL0, OUT), + K210_FUNC(INTERNAL1, OUT), + K210_FUNC(INTERNAL2, OUT), + K210_FUNC(INTERNAL3, OUT), + K210_FUNC(INTERNAL4, OUT), + K210_FUNC(INTERNAL5, OUT), + K210_FUNC(INTERNAL6, OUT), + K210_FUNC(INTERNAL7, OUT), + K210_FUNC(INTERNAL8, OUT), + K210_FUNC(INTERNAL9, IN), + K210_FUNC(INTERNAL10, IN), + K210_FUNC(INTERNAL11, IN), + K210_FUNC(INTERNAL12, IN), + K210_FUNC(INTERNAL13, INT13), + K210_FUNC(INTERNAL14, I2C), + K210_FUNC(INTERNAL15, IN), + K210_FUNC(INTERNAL16, IN), + K210_FUNC(INTERNAL17, IN), + K210_FUNC(CONSTANT, DISABLED), + K210_FUNC(INTERNAL18, IN), + K210_FUNC(DEBUG0, OUT), + K210_FUNC(DEBUG1, OUT), + K210_FUNC(DEBUG2, OUT), + K210_FUNC(DEBUG3, OUT), + K210_FUNC(DEBUG4, OUT), + K210_FUNC(DEBUG5, OUT), + K210_FUNC(DEBUG6, OUT), + K210_FUNC(DEBUG7, OUT), + K210_FUNC(DEBUG8, OUT), + K210_FUNC(DEBUG9, OUT), + K210_FUNC(DEBUG10, OUT), + K210_FUNC(DEBUG11, OUT), + K210_FUNC(DEBUG12, OUT), + K210_FUNC(DEBUG13, OUT), + K210_FUNC(DEBUG14, OUT), + K210_FUNC(DEBUG15, OUT), + K210_FUNC(DEBUG16, OUT), + K210_FUNC(DEBUG17, OUT), + K210_FUNC(DEBUG18, OUT), + K210_FUNC(DEBUG19, OUT), + K210_FUNC(DEBUG20, OUT), + K210_FUNC(DEBUG21, OUT), + K210_FUNC(DEBUG22, OUT), + K210_FUNC(DEBUG23, OUT), + K210_FUNC(DEBUG24, OUT), + K210_FUNC(DEBUG25, OUT), + K210_FUNC(DEBUG26, OUT), + K210_FUNC(DEBUG27, OUT), + K210_FUNC(DEBUG28, OUT), + K210_FUNC(DEBUG29, OUT), + K210_FUNC(DEBUG30, OUT), + K210_FUNC(DEBUG31, OUT), +}; + +#define PIN_CONFIG_OUTPUT_INVERT (PIN_CONFIG_END + 1) +#define PIN_CONFIG_INPUT_INVERT (PIN_CONFIG_END + 2) + +static const struct pinconf_generic_params k210_pinconf_custom_params[] = { + { "output-polarity-invert", PIN_CONFIG_OUTPUT_INVERT, 1 }, + { "input-polarity-invert", PIN_CONFIG_INPUT_INVERT, 1 }, +}; + +/* + * Max drive strength in uA. + */ +static const int k210_pinconf_drive_strength[] = { + [0] = 11200, + [1] = 16800, + [2] = 22300, + [3] = 27800, + [4] = 33300, + [5] = 38700, + [6] = 44100, + [7] = 49500, +}; + +static int k210_pinconf_get_drive(unsigned int max_strength_ua) +{ + int i; + + for (i = K210_PC_DRIVE_MAX; i; i--) { + if (k210_pinconf_drive_strength[i] <= max_strength_ua) + return i; + } + + return -EINVAL; +} + +static void k210_pinmux_set_pin_function(struct pinctrl_dev *pctldev, + u32 pin, u32 func) +{ + struct k210_fpioa_data *pdata = pinctrl_dev_get_drvdata(pctldev); + const struct k210_pcf_info *info = &k210_pcf_infos[func]; + u32 mode = k210_pinconf_mode_id_to_mode[info->mode_id]; + u32 val = func | mode; + + dev_dbg(pdata->dev, "set pin %u function %s (%u) -> 0x%08x\n", + pin, info->name, func, val); + + writel(val, &pdata->fpioa->pins[pin]); +} + +static int k210_pinconf_set_param(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned int param, unsigned int arg) +{ + struct k210_fpioa_data *pdata = pinctrl_dev_get_drvdata(pctldev); + u32 val = readl(&pdata->fpioa->pins[pin]); + int drive; + + dev_dbg(pdata->dev, "set pin %u param %u, arg 0x%x\n", + pin, param, arg); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + val &= ~K210_PC_BIAS_MASK; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (!arg) + return -EINVAL; + val |= K210_PC_PD; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (!arg) + return -EINVAL; + val |= K210_PC_PD; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + arg *= 1000; + fallthrough; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + drive = k210_pinconf_get_drive(arg); + if (drive < 0) + return drive; + val &= ~K210_PC_DRIVE_MASK; + val |= FIELD_PREP(K210_PC_DRIVE_MASK, drive); + break; + case PIN_CONFIG_INPUT_ENABLE: + if (arg) + val |= K210_PC_IE; + else + val &= ~K210_PC_IE; + break; + case PIN_CONFIG_INPUT_SCHMITT: + arg = 1; + fallthrough; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (arg) + val |= K210_PC_ST; + else + val &= ~K210_PC_ST; + break; + case PIN_CONFIG_OUTPUT: + k210_pinmux_set_pin_function(pctldev, pin, K210_PCF_CONSTANT); + val = readl(&pdata->fpioa->pins[pin]); + val |= K210_PC_MODE_OUT; + if (!arg) + val |= K210_PC_DO_INV; + break; + case PIN_CONFIG_OUTPUT_ENABLE: + if (arg) + val |= K210_PC_OE; + else + val &= ~K210_PC_OE; + break; + case PIN_CONFIG_SLEW_RATE: + if (arg) + val |= K210_PC_SL; + else + val &= ~K210_PC_SL; + break; + case PIN_CONFIG_OUTPUT_INVERT: + if (arg) + val |= K210_PC_DO_INV; + else + val &= ~K210_PC_DO_INV; + break; + case PIN_CONFIG_INPUT_INVERT: + if (arg) + val |= K210_PC_DI_INV; + else + val &= ~K210_PC_DI_INV; + break; + default: + return -EINVAL; + } + + writel(val, &pdata->fpioa->pins[pin]); + + return 0; +} + +static int k210_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + unsigned int param, arg; + int i, ret; + + if (WARN_ON(pin >= K210_NPINS)) + return -EINVAL; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + ret = k210_pinconf_set_param(pctldev, pin, param, arg); + if (ret) + return ret; + } + + return 0; +} + +static void k210_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin) +{ + struct k210_fpioa_data *pdata = pinctrl_dev_get_drvdata(pctldev); + + seq_printf(s, "%#x", readl(&pdata->fpioa->pins[pin])); +} + +static int k210_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int selector, unsigned long *configs, + unsigned int num_configs) +{ + struct k210_fpioa_data *pdata = pinctrl_dev_get_drvdata(pctldev); + unsigned int param, arg; + u32 bit; + int i; + + /* Pins should be configured with pinmux, not groups*/ + if (selector < K210_NPINS) + return -EINVAL; + + /* Otherwise it's a power domain */ + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + if (param != PIN_CONFIG_POWER_SOURCE) + return -EINVAL; + + arg = pinconf_to_config_argument(configs[i]); + bit = BIT(selector - K210_NPINS); + regmap_update_bits(pdata->sysctl_map, + pdata->power_offset, + bit, arg ? bit : 0); + } + + return 0; +} + +static void k210_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned int selector) +{ + struct k210_fpioa_data *pdata = pinctrl_dev_get_drvdata(pctldev); + int ret; + u32 val; + + if (selector < K210_NPINS) + return k210_pinconf_dbg_show(pctldev, s, selector); + + ret = regmap_read(pdata->sysctl_map, pdata->power_offset, &val); + if (ret) { + dev_err(pdata->dev, "Failed to read power reg\n"); + return; + } + + seq_printf(s, "%s: %s V", k210_group_names[selector], + val & BIT(selector - K210_NPINS) ? "1.8" : "3.3"); +} + +static const struct pinconf_ops k210_pinconf_ops = { + .is_generic = true, + .pin_config_set = k210_pinconf_set, + .pin_config_group_set = k210_pinconf_group_set, + .pin_config_dbg_show = k210_pinconf_dbg_show, + .pin_config_group_dbg_show = k210_pinconf_group_dbg_show, +}; + +static int k210_pinmux_get_function_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(k210_pcf_infos); +} + +static const char *k210_pinmux_get_function_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return k210_pcf_infos[selector].name; +} + +static int k210_pinmux_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + /* Any function can be mapped to any pin */ + *groups = k210_group_names; + *num_groups = K210_NPINS; + + return 0; +} + +static int k210_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, + unsigned int group) +{ + /* Can't mux power domains */ + if (group >= K210_NPINS) + return -EINVAL; + + k210_pinmux_set_pin_function(pctldev, group, function); + + return 0; +} + +static const struct pinmux_ops k210_pinmux_ops = { + .get_functions_count = k210_pinmux_get_function_count, + .get_function_name = k210_pinmux_get_function_name, + .get_function_groups = k210_pinmux_get_function_groups, + .set_mux = k210_pinmux_set_mux, + .strict = true, +}; + +static int k210_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + return K210_NGROUPS; +} + +static const char *k210_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned int group) +{ + return k210_group_names[group]; +} + +static int k210_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int group, + const unsigned int **pins, + unsigned int *npins) +{ + if (group >= K210_NPINS) { + *pins = NULL; + *npins = 0; + return 0; + } + + *pins = &k210_pins[group].number; + *npins = 1; + + return 0; +} + +static void k210_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int offset) +{ + seq_printf(s, "%s", dev_name(pctldev->dev)); +} + +static int k210_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *reserved_maps, + unsigned int *num_maps) +{ + struct property *prop; + const __be32 *p; + int ret, pinmux_groups; + u32 pinmux_group; + unsigned long *configs = NULL; + unsigned int num_configs = 0; + unsigned int reserve = 0; + + ret = of_property_count_strings(np, "groups"); + if (!ret) + return pinconf_generic_dt_subnode_to_map(pctldev, np, map, + reserved_maps, num_maps, + PIN_MAP_TYPE_CONFIGS_GROUP); + + pinmux_groups = of_property_count_u32_elems(np, "pinmux"); + if (pinmux_groups <= 0) { + /* Ignore this node */ + return 0; + } + + ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, + &num_configs); + if (ret < 0) { + dev_err(pctldev->dev, "%pOF: could not parse node property\n", + np); + return ret; + } + + reserve = pinmux_groups * (1 + num_configs); + ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps, + reserve); + if (ret < 0) + goto exit; + + of_property_for_each_u32(np, "pinmux", prop, p, pinmux_group) { + const char *group_name, *func_name; + u32 pin = FIELD_GET(K210_PG_PIN, pinmux_group); + u32 func = FIELD_GET(K210_PG_FUNC, pinmux_group); + + if (pin >= K210_NPINS) { + ret = -EINVAL; + goto exit; + } + + group_name = k210_group_names[pin]; + func_name = k210_pcf_infos[func].name; + + dev_dbg(pctldev->dev, "Pinmux %s: pin %u func %s\n", + np->name, pin, func_name); + + ret = pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, + num_maps, group_name, + func_name); + if (ret < 0) { + dev_err(pctldev->dev, "%pOF add mux map failed %d\n", + np, ret); + goto exit; + } + + if (num_configs) { + ret = pinctrl_utils_add_map_configs(pctldev, map, + reserved_maps, num_maps, group_name, + configs, num_configs, + PIN_MAP_TYPE_CONFIGS_PIN); + if (ret < 0) { + dev_err(pctldev->dev, + "%pOF add configs map failed %d\n", + np, ret); + goto exit; + } + } + } + + ret = 0; + +exit: + kfree(configs); + return ret; +} + +int k210_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, unsigned int *num_maps) +{ + unsigned int reserved_maps; + struct device_node *np; + int ret; + + reserved_maps = 0; + *map = NULL; + *num_maps = 0; + + ret = k210_pinctrl_dt_subnode_to_map(pctldev, np_config, map, + &reserved_maps, num_maps); + if (ret < 0) + goto err; + + for_each_available_child_of_node(np_config, np) { + ret = k210_pinctrl_dt_subnode_to_map(pctldev, np, map, + &reserved_maps, num_maps); + if (ret < 0) + goto err; + } + return 0; + +err: + pinctrl_utils_free_map(pctldev, *map, *num_maps); + return ret; +} + + +static const struct pinctrl_ops k210_pinctrl_ops = { + .get_groups_count = k210_pinctrl_get_groups_count, + .get_group_name = k210_pinctrl_get_group_name, + .get_group_pins = k210_pinctrl_get_group_pins, + .pin_dbg_show = k210_pinctrl_pin_dbg_show, + .dt_node_to_map = k210_pinctrl_dt_node_to_map, + .dt_free_map = pinconf_generic_dt_free_map, +}; + +static struct pinctrl_desc k210_pinctrl_desc = { + .name = "k210-pinctrl", + .pins = k210_pins, + .npins = K210_NPINS, + .pctlops = &k210_pinctrl_ops, + .pmxops = &k210_pinmux_ops, + .confops = &k210_pinconf_ops, + .custom_params = k210_pinconf_custom_params, + .num_custom_params = ARRAY_SIZE(k210_pinconf_custom_params), +}; + +static void k210_fpioa_init_ties(struct k210_fpioa_data *pdata) +{ + struct k210_fpioa *fpioa = pdata->fpioa; + u32 val; + int i, j; + + dev_dbg(pdata->dev, "Init pin ties\n"); + + /* Init pin functions input ties */ + for (i = 0; i < ARRAY_SIZE(fpioa->tie_en); i++) { + val = 0; + for (j = 0; j < 32; j++) { + if (k210_pcf_infos[i * 32 + j].mode_id == + K210_PC_DEFAULT_IN_TIE) { + dev_dbg(pdata->dev, + "tie_en function %d (%s)\n", + i * 32 + j, + k210_pcf_infos[i * 32 + j].name); + val |= BIT(j); + } + } + + /* Set value before enable */ + writel(val, &fpioa->tie_val[i]); + writel(val, &fpioa->tie_en[i]); + } +} + +static int k210_fpioa_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct k210_fpioa_data *pdata; + int ret; + + dev_info(dev, "K210 FPIOA pin controller\n"); + + pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + pdata->dev = dev; + platform_set_drvdata(pdev, pdata); + + pdata->fpioa = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pdata->fpioa)) + return PTR_ERR(pdata->fpioa); + + pdata->clk = devm_clk_get(dev, "ref"); + if (IS_ERR(pdata->clk)) + return PTR_ERR(pdata->clk); + + ret = clk_prepare_enable(pdata->clk); + if (ret) + return ret; + + pdata->pclk = devm_clk_get_optional(dev, "pclk"); + if (!IS_ERR(pdata->pclk)) + clk_prepare_enable(pdata->pclk); + + pdata->sysctl_map = + syscon_regmap_lookup_by_phandle(np, "kendryte,sysctl"); + if (IS_ERR(pdata->sysctl_map)) + return PTR_ERR(pdata->sysctl_map); + + ret = of_property_read_u32(np, "kendryte,power-offset", + &pdata->power_offset); + if (ret) + return -EINVAL; + + k210_fpioa_init_ties(pdata); + + pdata->pctl = pinctrl_register(&k210_pinctrl_desc, dev, (void *)pdata); + if (IS_ERR(pdata->pctl)) + return PTR_ERR(pdata->pctl); + + return 0; +} + +static const struct of_device_id k210_fpioa_dt_ids[] = { + { .compatible = "kendryte,k210-fpioa" }, +}; + +static struct platform_driver k210_fpioa_driver = { + .probe = k210_fpioa_probe, + .driver = { + .name = "k210-fpioa", + .of_match_table = k210_fpioa_dt_ids, + }, +}; + +/* + * Most devices on the K210 SoC depend on pin mapping changes to initialize + * correctly. So initialize this driver early as part of the post core + * initialization. + */ +static int __init k210_fpioa_init(void) +{ + return platform_driver_register(&k210_fpioa_driver); +} +postcore_initcall(k210_fpioa_init); From patchwork Sat Nov 7 08:14:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396074 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=WPXbg8VN; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqnP58Jqz9sRR for ; Sat, 7 Nov 2020 19:15:21 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728141AbgKGIPV (ORCPT ); Sat, 7 Nov 2020 03:15:21 -0500 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:57208 "EHLO esa3.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727896AbgKGIPU (ORCPT ); Sat, 7 Nov 2020 03:15:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1604736919; x=1636272919; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mT3pTXQexT9Dgnt/dopD8ONmHSaoe0HrxwBKmVk9pvo=; b=WPXbg8VNLNvhK8/mhDMCUfDRpdGMs1O9HJ8JVTGDH/suF0H37N3OsZjA GOegH2MBUAAnvxlAYo0dqLj5l3xtXiF8zfBix/4PnXB0lWOMvWq7eCja+ rnNzs9/m5+5EgI7v5V8j3eRYkLkYvLIXWGbEJqSeAwjl8eEjiD0e1Mm7f Ifg1YNAh8zpM5kfBaK8zcwg9hRhoEyOcaBsJJQfuYI9+LGKsQJjitiQFS 1rUbZit2S0Y5rxHVPVzXiaoWvBwJWUKSkIGa2auR4uc3I7eNlDBknkpEs eA0RS8lIZfMtqNskeyq+YHw84Z1OZpPUF+fGo112aYxDUYB4GlndagxvX g==; IronPort-SDR: PvujEE7T4qzq3tSLmeHgOy0920IpY8ah539avwPTG/d3P8jL+HRdUiJCAvO4qP8WR7aGtbIq6N Mp2eY6MH3JthWlQsK5qmK9Kl19Nf5/QeP3xMvGnh8VfKUHodj4fjrnk88TWU6Lu4k6Ot9WPNKa OjC+L0ihBn9wqh6lcYUC3Hfz0wQeszdLReRsthl13qk76JOOVsp6ggaSTr61MvXqhCmEzknR3X HIYv0djrm2BoUlvw/vr6dW/ddVk48sYdUikV5JoMW6af/ZTVFRjF6OGci1ampy2mbARnbSFtzd j6M= X-IronPort-AV: E=Sophos;i="5.77,459,1596470400"; d="scan'208";a="156564412" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 07 Nov 2020 16:15:19 +0800 IronPort-SDR: pWfFSy3MMowsC+GyZzx1sOTDYXGThvXr9H1EbHwR1dwxQ7ZZ6rNamyz3fUonZ6HrYzslw+ELF1 Im1K1h8ylZDFpDCdvxsD8mc/QpilDgvHYdIzjcKBr9e4vN7/pyWeIRdWuSqqFEQ76/QG1ZoIgN O0S+T1XGJuG8W1DY7H9wLeySg3GtydH7Ql9Ch5gp9AbDsEbUgIijiHx9jH9fJ+WwFiuhSxCZtV /xfb+cE/XeoX8Cu511083sNzKjf9ti7EWjwW4q6nDXRcHH2U7GKSDgXD4iTPs2jCMM5TVe129q NFl7lvzKwachoX8jOmzMHkCu Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2020 00:00:10 -0800 IronPort-SDR: nsSrpRMvEDvSs1TeA0fMTqHiFneFxHjZmLfdiZ87YpKj8Av1NoJkpTT29IXc4QkCHCdg6d+K/y zVGcDYrgUlDAfCTc+znMu3URNsQ3kk3ic6fmy40H5NFAj8SQwDDMBehX3TbPn8UYRGm+mzfuhQ DJC3TOp0zMejeMzCFqodVr59FKdboNmBIlVIJflbfggqVHWF6ocv7cwqJTb4YP+Ci2XKOErP8e NIeljGbMnfObFqEuZg9gln+SgXE+TnW8kID6vacvc37Da0BkapPZ9YbWTCsul4IYeM6yuSlmTt lAk= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:15:18 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 21/32] dt-bindings: Add Kendryte and Canaan vendor prefix Date: Sat, 7 Nov 2020 17:14:09 +0900 Message-Id: <20201107081420.60325-22-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Update Documentation/devicetree/bindings/vendor-prefixes.yaml to include "Kendryte" and "canaan" as a vendor prefix for "Canaan Inc." Signed-off-by: Damien Le Moal --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 2735be1a8470..f53d4d8e7f2a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -179,6 +179,8 @@ patternProperties: description: CALAO Systems SAS "^calxeda,.*": description: Calxeda + "^canaan,.*": + description: Canaan, Inc. "^caninos,.*": description: Caninos Loucos Program "^capella,.*": @@ -537,6 +539,8 @@ patternProperties: description: Ka-Ro electronics GmbH "^keithkoep,.*": description: Keith & Koep GmbH + "^kendryte,.*": + description: Canaan, Inc. "^keymile,.*": description: Keymile GmbH "^khadas,.*": From patchwork Sat Nov 7 08:14:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396077 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=GjIsz+F/; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqnS0h5Jz9sSs for ; Sat, 7 Nov 2020 19:15:24 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728160AbgKGIPX (ORCPT ); Sat, 7 Nov 2020 03:15:23 -0500 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:57208 "EHLO esa3.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727896AbgKGIPW (ORCPT ); Sat, 7 Nov 2020 03:15:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1604736922; x=1636272922; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6hQFOpsBQqm+ohKs0w/Ib6ThhS/q66nb5zcwWEvGTPw=; b=GjIsz+F/gUrttBC13mbWH7m/RFU1OsFiMYynyYaswVZ2qNiMJLf0eBid D+dr6ztcsuuo+KQ738WjESiFvnoqtxgyDhKZS9JZ3UD8xN2BPtVN371En 0jodtTVwDg59eVvpYbEBVHgfPor9CbK8tVy/l4Ar6vPiABx6zPs5nOYfJ /PRIg/Rz+9IXHFI9c8I4+NyeRanIQ1Tfn8KDnVz45E2dbM1+2nEEdFJpG 4jTsIppPyJIb6vsju1kRhIww5cB6OrIWsIxOVpDE8gJ1HeMsPY5MHNMr7 rpSZ+YD73QUypRHpf4muDuP6l15YztsymNawtlIqVrKDVa7WxenFBQcKt w==; IronPort-SDR: GY1Itue+JUKSOnxitwRnOq3auQ7/TBB5XtlrLsW/JynLp8q+4cSDQ65iJk8D6HzdoHlKiGoRxl pZQQXKP1vo9ziYgrYhsoKGfmFjUZAl5B/Oa9v6azlyPly5hnmSD8H33APiJhXvY7kQfat6TzCF 1G5C+GqMnm6amRA/iQHkZeYzczHOqm0NzXYgwbX7oGS7KO3C/o7VVz05C2wgZTPp/XlWIiHaxJ qZiQAmgfIUpcK2YBizdlsNk7swUmshEsK8jqOrtNpjqtVf+S2S7HQ6MgGAYHozjDd53xeJQMRT 9EM= X-IronPort-AV: E=Sophos;i="5.77,459,1596470400"; d="scan'208";a="156564416" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 07 Nov 2020 16:15:22 +0800 IronPort-SDR: Bw9gEIOBE3cN50/D7lsuvC6ywLh65NSFjAL1PtNAvnQouBXHENCCYoSKPgeuZzo19UVgkEqPRv 8rx9tnet5fMQJ0MBP/0Z/rY3XhnFp4cGZL0374j2hVWGjG7P29s4J5a5rpBQexLvImBmFXFu/a 0uklOm8onfQs91otyDkqm9wvBwZGlpKqouxYuAo5P5XrjXF5iFAS7nD/wcRf4FnWJblmq8P+9s Fs4XiuVsmjlxugKPuMyhjBOmX7TBhUKqmQpwF29LDQFM1fd1XrFTzXro8Aa3Wn9sWrR4rfTObV kEh7gXiXLo3wWjQak6bOu8O3 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2020 00:00:13 -0800 IronPort-SDR: BXlHUw/HDcF1F7ONaRWXXDTETsH6nr1+NpS8wIP/O/H9VAx/bcEfmJtb+W1CFGgZIE6Q+Dpecu W3rToKZcr96OLjkNsggtSMp75Le/onPmWlBJoE3YlGT1vpsNb5+X3V0mZ3R7j0Ek3gARGpo0wV zQtKI+OpzjxC8nTt21mnSH0dzmrwNuPruMdgrkmsSEJImr+NjmyVEAjBMYsoIM98GIOkoLSUE6 aEdVse9g1XVwgAiMF4C8EJa4mUadQH1/Elmv15IgrfAyhgUSj5DD3bw0eOhImxLZo7zAcfOFrE fLk= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:15:20 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 22/32] dt-binding: Document kendryte,k210-sysctl bindings Date: Sat, 7 Nov 2020 17:14:10 +0900 Message-Id: <20201107081420.60325-23-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Document the device tree bindings of the Kendryte K210 SoC system controller driver in Documentation/devicetree/bindings/mfd/kendryte,k210-sysctl.yaml. Signed-off-by: Damien Le Moal Reviewed-by: Sean Anderson --- .../bindings/mfd/kendryte,k210-sysctl.yaml | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/kendryte,k210-sysctl.yaml diff --git a/Documentation/devicetree/bindings/mfd/kendryte,k210-sysctl.yaml b/Documentation/devicetree/bindings/mfd/kendryte,k210-sysctl.yaml new file mode 100644 index 000000000000..8c002d2078f4 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/kendryte,k210-sysctl.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/kendryte,k210-sysctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Kendryte K210 System Controller Device Tree Bindings + +maintainers: + - Damien Le Moal + +description: | + Kendryte K210 system controller driver which provides a register map for + clocks and peripherals within the SoC. + + See also: + - dt-bindings/mfd/kendryte,k210-sysctl.h + +properties: + compatible: + allOf: + - items: + - const: kendryte,k210-sysctl + - const: syscon + - const: simple-mfd + + clocks: + minItems: 1 + maxItems: 1 + items: + - description: APB interface clock source + + clock-names: + minItems: 1 + items: + - const: pclk + + reg: + items: + - description: system controller register space base address and size + + reg-io-width: + const: 4 + +required: + - compatible + - clocks + - reg + +additionalProperties: false + +examples: + - | + #include + + sysctl: system-controller@50440000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "kendryte,k210-sysctl", + "syscon", "simple-mfd"; + reg = <0x50440000 0x1000>; + reg-io-width = <4>; + /* ... */ + }; + From patchwork Sat Nov 7 08:14:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396078 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=eJDxYjNh; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqnV244Fz9sRR for ; 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07 Nov 2020 00:00:15 -0800 IronPort-SDR: kNbmK/ZaWtIhWERqlBQPde5LebiYxI9kiEu8NrnS1rg2xhz2B9moqa38rqRkEw4qXSs9kQD4gN 1UduA2IXuax8AVRO+HiLUrNXDyjrKKiSozhKTsiF3RxCpJFY4Izb9tYfB9DUOm24HSwDeDrc5f DIVlk9KPPSh0q5zYG99b2uOUnzNsQ9GEZWS/qfDsygdI0Gxw4henwmOBCRTyUJQwX7XsqhsZF2 rGgGTdzOkGf/EgDjlylToDdHm8+sDeWdNFeRfndSZUrbFXJTg4QsMJj4H2dJ+0GNRdDXZYmpm4 N4s= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:15:23 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 23/32] dt-binding: Document kendryte,k210-clk bindings Date: Sat, 7 Nov 2020 17:14:11 +0900 Message-Id: <20201107081420.60325-24-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Document the device tree bindings of the Kendryte K210 SoC clock driver in Documentation/devicetree/bindings/clock/kendryte,k210-clk.yaml. Signed-off-by: Damien Le Moal Reviewed-by: Sean Anderson --- .../bindings/clock/kendryte,k210-clk.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/kendryte,k210-clk.yaml diff --git a/Documentation/devicetree/bindings/clock/kendryte,k210-clk.yaml b/Documentation/devicetree/bindings/clock/kendryte,k210-clk.yaml new file mode 100644 index 000000000000..02f5f8a86bc8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/kendryte,k210-clk.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/kendryte,k210-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Kendryte K210 Clock Device Tree Bindings + +maintainers: + - Damien Le Moal + +description: | + Kendryte K210 clock controller driver which support the system controller + subsystem supplied clocks for the various controllers and peripherals within + the SoC. + + See also: + - dt-bindings/clock/k210-clk.h + +properties: + compatible: + const: kendryte,k210-clk + + clocks: + maxItems: 1 + description: System fixed rate oscillator clock + + '#clock-cells': + const: 1 + +required: + - compatible + - '#clock-cells' + - clocks + +additionalProperties: false + +examples: + - | + #include + + clocks { + in0: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + /* ... */ + + sysctl: system-controller@50440000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "kendryte,k210-sysctl", + "syscon", "simple-mfd"; + reg = <0x50440000 0x1000>; + /* ... */ + sysclk: clock-controller { + #clock-cells = <1>; + compatible = "kendryte,k210-clk"; + clocks = <&in0>; + }; + /* ... */ + }; + }; + From patchwork Sat Nov 7 08:14:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396080 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; 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07 Nov 2020 00:00:18 -0800 IronPort-SDR: lC38bnsFdGbEDhiXXBwS2FuK3LUBKTJG9/sIdS/BmLHzQq47Lq7wiPIe/n0+Pa4G5zKX/9obAs MW6ZnTIe/mef/fQtJtygQQqUkGr4ROa+MFR4745KE8fs1xWpf/l042WWaSRr31opWGu1ODAdRh 8Kzs63FzBD1uJm7tfHGzzbcVCWWI2/iSkCf2jvAjo/2sNRYOVt73cd2/59931z+EyEZcE5lnvP kA5H2BV50bAfZFhNESNcs3Ymyt5ELv1KNRp1vxy6l5rgkD2jEDmbd7mDqZ2pqCS6Xjwe0K8PRv HcI= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:15:25 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 24/32] dt-bindings: Document kendryte,k210-fpioa bindings Date: Sat, 7 Nov 2020 17:14:12 +0900 Message-Id: <20201107081420.60325-25-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Document the device tree bindings for the Kendryte K210 SoC Fully Programmable IO Array (FPIOA) pinctrl driver in Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml Signed-off-by: Damien Le Moal Reviewed-by: Sean Anderson --- .../bindings/pinctrl/kendryte,k210-fpioa.yaml | 106 ++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml b/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml new file mode 100644 index 000000000000..8730add88ee0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/kendryte,k210-fpioa.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/kendryte,k210-fpioa.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Kendryte K210 FPIOA (Fully Programmable IO Array) Device Tree Bindings + +maintainers: + - Damien Le Moal + +description: + The Kendryte K210 SoC Fully Programmable IO Array controller allows assiging + any of 256 possible functions to any of 48 IO pins. Pin function configuration + is performed on a per-pin basis. + +properties: + compatible: + const: kendryte,k210-fpioa + + reg: + description: FPIOA controller register space base address and size + + clocks: + minItems: 2 + maxItems: 2 + items: + - description: Controller reference clock source + - description: APB interface clock source + + clock-names: + minItems: 2 + maxItems: 2 + items: + - const: ref + - const: pclk + + resets: + maxItems: 1 + + kendryte,sysctl: + minItems: 1 + maxItems: 1 + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + phandle to the system controller node + + kendryte,power-offset: + minItems: 1 + maxItems: 1 + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Offset of the power domain control register of the system controller. + The value should be the macro K210_SYSCTL_POWER_SEL defined in + dt-bindings/mfd/k210-sysctl.h. + +patternProperties: + '^.*$': + if: + type: object + then: + patternProperties: + "^pinmux$": + $ref: /schemas/pinctrl/pincfg-node.yaml + description: + An array of IO pins alternate functions. The values for each + IO pin is a combination of an IO pin number (0 to 47) with the + desired function for the IO pin. Functions are defined as macros in + dt-bindings/pinctrl/k210-pinctrl.h. The K210_FPIOA(IO pin, function) + is provided to facilitate the combination of IO pin numbers and + functions. + +required: + - compatible + - reg + - clocks + - resets + - kendryte,sysctl + - kendryte,power-offset + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + fpioa: pinmux@502B0000 { + compatible = "kendryte,k210-fpioa"; + reg = <0x502B0000 0x100>; + clocks = <&sysclk K210_CLK_FPIOA>; + resets = <&sysrst K210_RST_FPIOA>; + kendryte,sysctl = <&sysctl>; + kendryte,power-offset = ; + pinctrl-0 = <&fpioa_jtag>; + pinctrl-names = "default"; + + fpioa_jtag: jtag { + pinmux = , + , + , + ; + }; + }; From patchwork Sat Nov 7 08:14:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396083 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=XAxLTqRj; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqnc0tPbz9sTD for ; Sat, 7 Nov 2020 19:15:32 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728181AbgKGIPb (ORCPT ); Sat, 7 Nov 2020 03:15:31 -0500 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:57208 "EHLO esa3.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727868AbgKGIPa (ORCPT ); Sat, 7 Nov 2020 03:15:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1604736930; x=1636272930; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VhB8WEnLoq7dAyllPLVCuTHZzGrie11gmx4BWMw3mkw=; b=XAxLTqRjZH1mU8r9jbSO9z8XTPetLWgu0Kc8kdJmBBT2CoTGGvOJB55q PO7LkfWqcksbowQQYiEIzirPejos2dPmQy1AlY/C4RWoTMO44XWYSAWVM qUT0cPz/QSXZHqFHZcvUsM/tNL2I1zrJlzrgTMUQB8GKbtt6aPP+xOCwi aw2GCyjMxslXqF5FirN8i+7tQKeMuV2g+I/JN3mbU/CCI2H4ZnLDUP7DD MZQxJC7NYgsC7ow155tmfrzjN/dIaG2HpXYdCtM2IbiOe5Sx569HVg/sa SBBQN2AC9moA0ppeXAA00YhAx3Lb/3dtvRzKoSLSh9Y8lO5a1nnYhgux/ g==; IronPort-SDR: F/bsWOBVVHGr6C0ZAMKYljVjYYAKGYpvDT7vtZSjoZBgNxfSwo5xZeTWGCf6SJKxTGUlMLUc5B /ZINnUoNUNcG6HZv6D8Xfenq0eym6TpvVi8jVMno816dbFqZ3MVggJfduwx7wBEfGtI1id5gDw a8ETBhYt/HfIt94tNyRR2FzKagE+csm+4ZS7/+aXTIliI/iHq234ejplB4BcEMofwmBMbOyiLp cpb1SRaUlTrYEub8iXPjYjtwSBMt01PvKTjokyxahtrkzzYbvFz8ZyTqoGVDmK00WvHQVcjIub rlA= X-IronPort-AV: E=Sophos;i="5.77,459,1596470400"; d="scan'208";a="156564424" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 07 Nov 2020 16:15:30 +0800 IronPort-SDR: Vb5k+BNGdFYwckMGgd3PdyOj5zsGNg1s3OMHWScAi4kWexQfcbuJOS0GmFTvnXbQJvkakjsD38 RP3B2r2xFfV5XFx17SWiPlJe9BSqaajzOfaxCa0O3rq9+CiXZN5GbFilFZ2KEgUi8NN2R/T/90 GKWzLYITDTKGBJlkN//Vuq/+UGlcRYa4rinHvTDxqGW3q4m2DbiMd00cvI+QVi+NWe1sT8UHOe 6E+kDNDFUNM6EybA3GzQLFCHHrnJ57xbxDXTTSdTRVhQfz4DIES7AqX3qtWqJjtPRJoGUp5RuK atvX5ZpWqSeJZP0fwMDD6oPr Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2020 00:00:21 -0800 IronPort-SDR: g1LXRXd+/vgJ9IQncw2auwsajYAcwYINfKzbezBRCv21wTeb+4TC2P+2Vj/iBQmxJBB45LBQj0 l5q85yU7Y5IxQPC6YDL8wJ6s2yw5ifSfcS4uEur59uOiiZhSIq2KyjS/xOTtDFFGUpogNmVNgh W3bV8pgfvT6gMtYfw4feEgZ12ceRVUKYQTICyrggf4ECaNlz3vG2J6Tykawi01JX/qECgpllK1 ENVmP1kUckKQArkTkryMA/cYdKiL102RvqWUbmmXG23V3tmB5HD6CuaF4lgqjvspuD7UGI8iIL 0Dk= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:15:28 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 25/32] dt-bindings: Document kendryte,k210-rst bindings Date: Sat, 7 Nov 2020 17:14:13 +0900 Message-Id: <20201107081420.60325-26-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Document the device tree bindings for the Kendryte K210 SoC reset controller driver in Documentation/devicetree/bindings/reset/kendryte,k210-rst.yaml. Signed-off-by: Damien Le Moal Reviewed-by: Sean Anderson --- .../bindings/reset/kendryte,k210-rst.yaml | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/kendryte,k210-rst.yaml diff --git a/Documentation/devicetree/bindings/reset/kendryte,k210-rst.yaml b/Documentation/devicetree/bindings/reset/kendryte,k210-rst.yaml new file mode 100644 index 000000000000..bdd0bf37bdfb --- /dev/null +++ b/Documentation/devicetree/bindings/reset/kendryte,k210-rst.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/kendryte,k210-rst.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Kendryte K210 Reset Controller Device Tree Bindings + +maintainers: + - Damien Le Moal + +description: | + Kendryte K210 reset controller driver which support the system controller + subsystem supplied reset registers for the various peripherals within + the SoC. + + See also: + - dt-bindings/reset/k210-rst.h + +properties: + compatible: + allOf: + - items: + - const: kendryte,k210-rst + - const: syscon-reset + + regmap: + maxItems: 1 + description: phandle of the system controller (sysctl) node + + offset: + maxItems: 1 + description: peripheral reset register offset in the system controller + controller register map + + mask: + maxItems: 1 + description: bit-mask indicating valid reset bits in the reset register + + assert-high: + maxItems: 1 + description: bit value to write when asserting a reset + + '#reset-cells': + const: 1 + +required: + - '#reset-cells' + - compatible + - regmap + - offset + - mask + - assert-high + +additionalProperties: false + +examples: + - | + #include + #include + + sysctl: system-controller@50440000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "kendryte,k210-sysctl", + "syscon", "simple-mfd"; + reg = <0x50440000 0x1000>; + /* ... */ + sysrst: reset-controller { + compatible = "kendryte,k210-rst", + "syscon-reset"; + #reset-cells = <1>; + regmap = <&sysctl>; + offset = ; + mask = <0x27FFFFFF>; + assert-high = <1>; + }; + }; From patchwork Sat Nov 7 08:14:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396084 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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07 Nov 2020 00:00:23 -0800 IronPort-SDR: QwjA/r2UeXXlEJzX2W+Brk1cEF+8CVnZOwivgSu4xCQS0RYCagUS2tHvApkc2W51DnklgZokEj 84etHKVmB2gMEFkliYNKsdkg84r+bT2EwI31elLX5r3s4tmlp3hE8o2fhnkpYo4RLfAjiQ9TAy PyGoty3CBtF6wX+4z7DbEc7rfwTB1gaujy+SvazJUBRSQ3rb3PB0BAjYTmvf9IwaePWLkcWQBR VlvPT7WRYLheqQ8EWfb3aWkP/ZS2FbBhFfLma7AYEvC9J4uZugd6rZvs1GZmrMKnpSo2djrJz/ nWU= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:15:31 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 26/32] riscv: Update Kendryte K210 device tree Date: Sat, 7 Nov 2020 17:14:14 +0900 Message-Id: <20201107081420.60325-27-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Update the Kendryte K210 base device tree k210.dtsi to define all peripherals of the SoC, their clocks and reset lines. The device tree file k210.dts is renamed to k210_generic.dts and becomes the default dwivalue selection of the SOC_KENDRYTE_K210_DTB_BUILTIN_SOURCE configuration option. No device beside the serial console is defined by this device tree. This makes it suitable for all known K210 boards using a builtin initramfs. Most updates to the k210.dtsi file come from Sean Anderson's work on U-Boot support for the Kendryte K210. Signed-off-by: Damien Le Moal Reviewed-by: Sean Anderson --- arch/riscv/Kconfig.socs | 2 +- arch/riscv/boot/dts/kendryte/k210.dts | 23 - arch/riscv/boot/dts/kendryte/k210.dtsi | 564 +++++++++++++++++- arch/riscv/boot/dts/kendryte/k210_generic.dts | 46 ++ 4 files changed, 583 insertions(+), 52 deletions(-) delete mode 100644 arch/riscv/boot/dts/kendryte/k210.dts create mode 100644 arch/riscv/boot/dts/kendryte/k210_generic.dts diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 56ba82a64e18..9230af7fb763 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -59,7 +59,7 @@ config SOC_KENDRYTE_K210_DTB_SOURCE string "Source file for the Kendryte K210 builtin DTB" depends on SOC_KENDRYTE depends on SOC_KENDRYTE_K210_DTB_BUILTIN - default "k210" + default "k210_generic" help Base name (without suffix, relative to arch/riscv/boot/dts/kendryte) for the DTS file that will be used to produce the DTB linked into the diff --git a/arch/riscv/boot/dts/kendryte/k210.dts b/arch/riscv/boot/dts/kendryte/k210.dts deleted file mode 100644 index 0d1f28fce6b2..000000000000 --- a/arch/riscv/boot/dts/kendryte/k210.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2020 Western Digital Corporation or its affiliates. - */ - -/dts-v1/; - -#include "k210.dtsi" - -/ { - model = "Kendryte K210 generic"; - compatible = "kendryte,k210"; - - chosen { - bootargs = "earlycon console=ttySIF0"; - stdout-path = "serial0"; - }; -}; - -&uarths0 { - status = "okay"; -}; - diff --git a/arch/riscv/boot/dts/kendryte/k210.dtsi b/arch/riscv/boot/dts/kendryte/k210.dtsi index d2d0ff645632..b8706fe78b21 100644 --- a/arch/riscv/boot/dts/kendryte/k210.dtsi +++ b/arch/riscv/boot/dts/kendryte/k210.dtsi @@ -1,9 +1,12 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Sean Anderson + * Copyright (C) 2019-20 Sean Anderson * Copyright (C) 2020 Western Digital Corporation or its affiliates. */ #include +#include +#include +#include / { /* @@ -15,7 +18,26 @@ / { compatible = "kendryte,k210"; aliases { + cpu0 = &cpu0; + cpu1 = &cpu1; + dma0 = &dmac0; + gpio0 = &gpio0; + gpio1 = &gpio1_0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + pinctrl0 = &fpioa; serial0 = &uarths0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + timer0 = &timer0; + timer1 = &timer1; + timer2 = &timer2; }; /* @@ -30,16 +52,15 @@ cpus { timebase-frequency = <7800000>; cpu0: cpu@0 { device_type = "cpu"; - reg = <0>; compatible = "kendryte,k210", "sifive,rocket0", "riscv"; - riscv,isa = "rv64imafdc"; + reg = <0>; + riscv,isa = "rv64imafdgc"; mmu-type = "none"; - i-cache-size = <0x8000>; i-cache-block-size = <64>; - d-cache-size = <0x8000>; + i-cache-size = <0x8000>; d-cache-block-size = <64>; - clocks = <&sysctl K210_CLK_CPU>; - clock-frequency = <390000000>; + d-cache-size = <0x8000>; + clocks = <&sysclk K210_CLK_CPU>; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; @@ -48,16 +69,15 @@ cpu0_intc: interrupt-controller { }; cpu1: cpu@1 { device_type = "cpu"; - reg = <1>; compatible = "kendryte,k210", "sifive,rocket0", "riscv"; - riscv,isa = "rv64imafdc"; + reg = <1>; + riscv,isa = "rv64imafdgc"; mmu-type = "none"; - i-cache-size = <0x8000>; i-cache-block-size = <64>; - d-cache-size = <0x8000>; + i-cache-size = <0x8000>; d-cache-block-size = <64>; - clocks = <&sysctl K210_CLK_CPU>; - clock-frequency = <390000000>; + d-cache-size = <0x8000>; + clocks = <&sysclk K210_CLK_CPU>; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; @@ -68,14 +88,19 @@ cpu1_intc: interrupt-controller { sram: memory@80000000 { device_type = "memory"; + compatible = "kendryte,k210-sram"; reg = <0x80000000 0x400000>, <0x80400000 0x200000>, <0x80600000 0x200000>; reg-names = "sram0", "sram1", "aisram"; + clocks = <&sysclk K210_CLK_SRAM0>, + <&sysclk K210_CLK_SRAM1>, + <&sysclk K210_CLK_AI>; + clock-names = "sram0", "sram1", "aisram"; }; clocks { - in0: oscillator { + in0: osc { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; @@ -89,28 +114,34 @@ soc { ranges; interrupt-parent = <&plic0>; - sysctl: sysctl@50440000 { - compatible = "kendryte,k210-sysctl", "simple-mfd"; - reg = <0x50440000 0x1000>; - #clock-cells = <1>; + debug0: debug@0 { + compatible = "kendryte,k210-debug", "riscv,debug"; + reg = <0x0 0x1000>; + status = "disabled"; + }; + + rom0: nvmem@1000 { + reg = <0x1000 0x1000>; + read-only; + status = "disabled"; }; clint0: clint@2000000 { #interrupt-cells = <1>; - compatible = "riscv,clint0"; + compatible = "kendryte,k210-clint", "riscv,clint0"; reg = <0x2000000 0xC000>; - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7>; - clocks = <&sysctl K210_CLK_ACLK>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>; + clocks = <&sysclk K210_CLK_CLINT>; }; - plic0: interrupt-controller@c000000 { + plic0: interrupt-controller@C000000 { #interrupt-cells = <1>; - interrupt-controller; - compatible = "kendryte,k210-plic0", "riscv,plic0"; + compatible = "kendryte,k210-plic", "riscv,plic0"; reg = <0xC000000 0x4000000>; - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 0xffffffff>, - <&cpu1_intc 11>, <&cpu1_intc 0xffffffff>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11>, + <&cpu1_intc 11>; riscv,ndev = <65>; riscv,max-priority = <7>; }; @@ -119,7 +150,484 @@ uarths0: serial@38000000 { compatible = "kendryte,k210-uarths", "sifive,uart0"; reg = <0x38000000 0x1000>; interrupts = <33>; - clocks = <&sysctl K210_CLK_CPU>; + clocks = <&sysclk K210_CLK_CPU>; + status = "disabled"; + }; + + gpio0: gpio-controller@38001000 { + #interrupt-cells = <2>; + #gpio-cells = <2>; + compatible = "kendryte,k210-gpiohs", "sifive,gpio0"; + reg = <0x38001000 0x1000>; + interrupt-controller; + interrupts = <34 35 36 37 38 39 40 41 + 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 + 58 59 60 61 62 63 64 65>; + gpio-controller; + ngpios = <32>; + status = "disabled"; + }; + + kpu0: kpu@40800000 { + compatible = "kendryte,k210-kpu"; + reg = <0x40800000 0xc00000>; + interrupts = <25>; + clocks = <&sysclk K210_CLK_AI>; + status = "disabled"; + }; + + fft0: fft@42000000 { + compatible = "kendryte,k210-fft"; + reg = <0x42000000 0x400000>; + interrupts = <26>; + clocks = <&sysclk K210_CLK_FFT>; + resets = <&sysrst K210_RST_FFT>; + status = "disabled"; + }; + + dmac0: dma-controller@50000000 { + compatible = "kendryte,k210-dmac", "snps,axi-dma-1.01a"; + reg = <0x50000000 0x1000>; + interrupts = <27 28 29 30 31 32>; + clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>; + clock-names = "core-clk", "cfgr-clk"; + resets = <&sysrst K210_RST_DMA>; + dma-channels = <6>; + snps,dma-masters = <2>; + snps,priority = <0 1 2 3 4 5>; + snps,data-width = <5>; + snps,block-size = <0x200000 0x200000 0x200000 + 0x200000 0x200000 0x200000>; + snps,axi-max-burst-len = <256>; + status = "disabled"; + }; + + apb0: bus@50200000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "kendryte,k210-apb", "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB0>; + + gpio1: gpio-controller@50200000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "kendryte,k210-gpio", + "snps,dw-apb-gpio"; + reg = <0x50200000 0x80>; + clocks = <&sysclk K210_CLK_APB0>, + <&sysclk K210_CLK_GPIO>; + clock-names = "bus", "db"; + resets = <&sysrst K210_RST_GPIO>; + status = "disabled"; + + gpio1_0: gpio1@0 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + interrupt-controller; + interrupts = <23>; + gpio-controller; + snps,nr-gpios = <8>; + }; + }; + + uart1: serial@50210000 { + compatible = "kendryte,k210-uart", + "snps,dw-apb-uart"; + reg = <0x50210000 0x100>; + interrupts = <11>; + clocks = <&sysclk K210_CLK_UART1>, + <&sysclk K210_CLK_APB0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&sysrst K210_RST_UART1>; + reg-io-width = <4>; + reg-shift = <2>; + dcd-override; + dsr-override; + cts-override; + ri-override; + status = "disabled"; + }; + + uart2: serial@50220000 { + compatible = "kendryte,k210-uart", + "snps,dw-apb-uart"; + reg = <0x50220000 0x100>; + interrupts = <12>; + clocks = <&sysclk K210_CLK_UART2>, + <&sysclk K210_CLK_APB0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&sysrst K210_RST_UART2>; + reg-io-width = <4>; + reg-shift = <2>; + dcd-override; + dsr-override; + cts-override; + ri-override; + status = "disabled"; + }; + + uart3: serial@50230000 { + compatible = "kendryte,k210-uart", + "snps,dw-apb-uart"; + reg = <0x50230000 0x100>; + interrupts = <13>; + clocks = <&sysclk K210_CLK_UART3>, + <&sysclk K210_CLK_APB0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&sysrst K210_RST_UART3>; + reg-io-width = <4>; + reg-shift = <2>; + dcd-override; + dsr-override; + cts-override; + ri-override; + status = "disabled"; + }; + + spi2: spi@50240000 { + compatible = "canaan,kendryte-k210-spi", + "snps,dw-apb-ssi-4.01", + "snps,dw-apb-ssi"; + spi-slave; + reg = <0x50240000 0x100>; + interrupts = <3>; + clocks = <&sysclk K210_CLK_SPI2>, + <&sysclk K210_CLK_APB0>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI2>; + spi-max-frequency = <25000000>; + status = "disabled"; + }; + + i2s0: i2s@50250000 { + compatible = "kendryte,k210-i2s", + "snps,designware-i2s"; + reg = <0x50250000 0x200>; + interrupts = <5>; + clocks = <&sysclk K210_CLK_I2S0>; + clock-names = "i2sclk"; + resets = <&sysrst K210_RST_I2S0>; + status = "disabled"; + }; + + apu0: sound@520250200 { + compatible = "kendryte,k210-apu"; + reg = <0x50250200 0x200>; + status = "disabled"; + }; + + i2s1: i2s@50260000 { + compatible = "kendryte,k210-i2s", + "snps,designware-i2s"; + reg = <0x50260000 0x200>; + interrupts = <6>; + clocks = <&sysclk K210_CLK_I2S1>; + clock-names = "i2sclk"; + resets = <&sysrst K210_RST_I2S1>; + status = "disabled"; + }; + + i2s2: i2s@50270000 { + compatible = "kendryte,k210-i2s", + "snps,designware-i2s"; + reg = <0x50270000 0x200>; + interrupts = <7>; + clocks = <&sysclk K210_CLK_I2S2>; + clock-names = "i2sclk"; + resets = <&sysrst K210_RST_I2S2>; + status = "disabled"; + }; + + i2c0: i2c@50280000 { + compatible = "kendryte,k210-i2c", + "snps,designware-i2c"; + reg = <0x50280000 0x100>; + interrupts = <8>; + clocks = <&sysclk K210_CLK_I2C0>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_I2C0>; + status = "disabled"; + }; + + i2c1: i2c@50290000 { + compatible = "kendryte,k210-i2c", + "snps,designware-i2c"; + reg = <0x50290000 0x100>; + interrupts = <9>; + clocks = <&sysclk K210_CLK_I2C1>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@502A0000 { + compatible = "kendryte,k210-i2c", + "snps,designware-i2c"; + reg = <0x502A0000 0x100>; + interrupts = <10>; + clocks = <&sysclk K210_CLK_I2C2>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_I2C2>; + status = "disabled"; + }; + + fpioa: pinmux@502B0000 { + compatible = "kendryte,k210-fpioa"; + reg = <0x502B0000 0x100>; + clocks = <&sysclk K210_CLK_FPIOA>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_FPIOA>; + kendryte,sysctl = <&sysctl>; + kendryte,power-offset = ; + status = "disabled"; + }; + + sha256: sha256@502C0000 { + compatible = "kendryte,k210-sha256"; + reg = <0x502C0000 0x100>; + clocks = <&sysclk K210_CLK_SHA>; + resets = <&sysrst K210_RST_SHA>; + status = "disabled"; + }; + + timer0: timer@502D0000 { + compatible = "kendryte,k210-timer", + "snps,dw-apb-timer"; + reg = <0x502D0000 0x100>; + interrupts = <14 15>; + clocks = <&sysclk K210_CLK_TIMER0>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER0>; + status = "disabled"; + }; + + timer1: timer@502E0000 { + compatible = "kendryte,k210-timer", + "snps,dw-apb-timer"; + reg = <0x502E0000 0x100>; + interrupts = <16 17>; + clocks = <&sysclk K210_CLK_TIMER1>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER1>; + status = "disabled"; + }; + + timer2: timer@502F0000 { + compatible = "kendryte,k210-timer", + "snps,dw-apb-timer"; + reg = <0x502F0000 0x100>; + interrupts = <18 19>; + clocks = <&sysclk K210_CLK_TIMER2>, + <&sysclk K210_CLK_APB0>; + clock-names = "timer", "pclk"; + resets = <&sysrst K210_RST_TIMER2>; + status = "disabled"; + }; + }; + + apb1: bus@50400000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "kendryte,k210-apb", "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB1>; + + wdt0: watchdog@50400000 { + compatible = "kendryte,k210-wdt", "snps,dw-wdt"; + reg = <0x50400000 0x100>; + interrupts = <21>; + clocks = <&sysclk K210_CLK_WDT0>, + <&sysclk K210_CLK_APB1>; + clock-names = "tclk", "pclk"; + resets = <&sysrst K210_RST_WDT0>; + status = "disabled"; + }; + + wdt1: watchdog@50410000 { + compatible = "kendryte,k210-wdt", "snps,dw-wdt"; + reg = <0x50410000 0x100>; + interrupts = <22>; + clocks = <&sysclk K210_CLK_WDT1>, + <&sysclk K210_CLK_APB1>; + clock-names = "tclk", "pclk"; + resets = <&sysrst K210_RST_WDT1>; + status = "disabled"; + }; + + otp0: nvmem@50420000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "kendryte,k210-otp"; + reg = <0x50420000 0x100>, + <0x88000000 0x20000>; + reg-names = "reg", "mem"; + clocks = <&sysclk K210_CLK_ROM>; + resets = <&sysrst K210_RST_ROM>; + read-only; + status = "disabled"; + + /* Bootloader */ + firmware@00000 { + reg = <0x00000 0xC200>; + }; + + /* + * config string as described in RISC-V + * privileged spec 1.9 + */ + config-1-9@1c000 { + reg = <0x1C000 0x1000>; + }; + + /* + * Device tree containing only registers, + * interrupts, and cpus + */ + fdt@1d000 { + reg = <0x1D000 0x2000>; + }; + + /* CPU/ROM credits */ + credits@1f000 { + reg = <0x1F000 0x1000>; + }; + }; + + dvp0: camera@50430000 { + compatible = "kendryte,k210-dvp"; + reg = <0x50430000 0x100>; + interrupts = <24>; + clocks = <&sysclk K210_CLK_DVP>; + resets = <&sysrst K210_RST_DVP>; + kendryte,sysctl = <&sysctl>; + kendryte,misc-offset = ; + status = "disabled"; + }; + + sysctl: syscon@50440000 { + compatible = "kendryte,k210-sysctl", + "syscon", "simple-mfd"; + reg = <0x50440000 0x100>; + reg-io-width = <4>; + clocks = <&sysclk K210_CLK_APB1>; + clock-names = "pclk"; + + sysclk: clock-controller { + #clock-cells = <1>; + compatible = "kendryte,k210-clk"; + clocks = <&in0>; + }; + + sysrst: reset-controller { + compatible = "kendryte,k210-rst", + "syscon-reset"; + #reset-cells = <1>; + regmap = <&sysctl>; + offset = ; + mask = <0x27FFFFFF>; + assert-high = <1>; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&sysctl>; + offset = ; + mask = <1>; + value = <1>; + }; + }; + + aes0: aes@50450000 { + compatible = "kendryte,k210-aes"; + reg = <0x50450000 0x100>; + clocks = <&sysclk K210_CLK_AES>; + resets = <&sysrst K210_RST_AES>; + status = "disabled"; + }; + + rtc: rtc@50460000 { + compatible = "kendryte,k210-rtc"; + reg = <0x50460000 0x100>; + clocks = <&in0>; + resets = <&sysrst K210_RST_RTC>; + interrupts = <20>; + status = "disabled"; + }; + }; + + apb2: bus@52000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "kendryte,k210-apb", "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB2>; + + spi0: spi@52000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "canaan,kendryte-k210-spi", + "snps,dw-apb-ssi-4.01", + "snps,dw-apb-ssi"; + reg = <0x52000000 0x100>; + interrupts = <1>; + clocks = <&sysclk K210_CLK_SPI0>, + <&sysclk K210_CLK_APB2>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI0>; + reset-names = "spi"; + spi-max-frequency = <25000000>; + num-cs = <4>; + reg-io-width = <4>; + status = "disabled"; + }; + + spi1: spi@53000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "canaan,kendryte-k210-spi", + "snps,dw-apb-ssi-4.01", + "snps,dw-apb-ssi"; + reg = <0x53000000 0x100>; + interrupts = <2>; + clocks = <&sysclk K210_CLK_SPI1>, + <&sysclk K210_CLK_APB2>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI1>; + reset-names = "spi"; + spi-max-frequency = <25000000>; + num-cs = <4>; + reg-io-width = <4>; + status = "disabled"; + }; + + spi3: spi@54000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "canaan,kendryte-k210-ssi", + "snps,dwc-ssi-1.01a"; + reg = <0x54000000 0x200>; + interrupts = <4>; + clocks = <&sysclk K210_CLK_SPI3>, + <&sysclk K210_CLK_APB2>; + clock-names = "ssi_clk", "pclk"; + resets = <&sysrst K210_RST_SPI3>; + reset-names = "spi"; + /* Could possibly go up to 200 MHz */ + spi-max-frequency = <100000000>; + num-cs = <4>; + reg-io-width = <4>; + status = "disabled"; + }; }; }; }; diff --git a/arch/riscv/boot/dts/kendryte/k210_generic.dts b/arch/riscv/boot/dts/kendryte/k210_generic.dts new file mode 100644 index 000000000000..f336f60dc15d --- /dev/null +++ b/arch/riscv/boot/dts/kendryte/k210_generic.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include + +/ { + model = "Kendryte K210 generic"; + compatible = "kendryte,k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; +}; + +&fpioa { + pinctrl-0 = <&fpioa_jtag>; + pinctrl-names = "default"; + status = "okay"; + + fpioa_jtag: jtag { + pinmux = , + , + , + ; + }; + + fpioa_uarths: uarths { + pinmux = , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&fpioa_uarths>; + pinctrl-names = "default"; + status = "okay"; +}; From patchwork Sat Nov 7 08:14:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396085 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=fb3oXHC6; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqnk20hpz9sSs for ; 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07 Nov 2020 00:00:26 -0800 IronPort-SDR: wm66Qy/0HChucDX9w7hQOkrgUfMD8sdsv9JyXig2wbzGofnzoKmJIXIyPg8/eli6D5dkanBxYf bD7VpSATO851A/BzXhEw2iTnQjpuOOxrm9ci6Ipqoi8Rs7lc83cAzHhesV0MZqpNJ80dXvM/O+ MAOvOPbQR6VrfDEq2qGT89g3zKgHQpmbd4nazHPE6n793KPZGHKblkLcmuYKmZ81EQlXFEBUL4 gXgxBvRN49eBK4yiMnyMrJqHKoX+lPlbViXHhvGc6S4ppbxVaIqnRXo79Wpebe8F3vgq3FUR4Y HcM= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:15:33 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 27/32] riscv: Add SiPeed MAIX BiT board device tree Date: Sat, 7 Nov 2020 17:14:15 +0900 Message-Id: <20201107081420.60325-28-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add a device tree for the SiPeed MAIX BiT and MAIX BiTm boards. This device tree enables LEDs, gpio, i2c and spi/mmc SD card devices. Signed-off-by: Damien Le Moal Reviewed-by: Sean Anderson --- .../riscv/boot/dts/kendryte/k210_maix_bit.dts | 226 ++++++++++++++++++ 1 file changed, 226 insertions(+) create mode 100644 arch/riscv/boot/dts/kendryte/k210_maix_bit.dts diff --git a/arch/riscv/boot/dts/kendryte/k210_maix_bit.dts b/arch/riscv/boot/dts/kendryte/k210_maix_bit.dts new file mode 100644 index 000000000000..fc814f7c1173 --- /dev/null +++ b/arch/riscv/boot/dts/kendryte/k210_maix_bit.dts @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include + +/ { + model = "SiPeed MAIX BiT"; + compatible = "sipeed,maix-bitm", "sipeed,maix-bit", + "kendryte,k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + green { + gpios = <&gpio1_0 4 GPIO_ACTIVE_LOW>; + }; + + red { + gpios = <&gpio1_0 5 GPIO_ACTIVE_LOW>; + }; + + blue { + gpios = <&gpio1_0 6 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + boot { + label = "BOOT"; + linux,code = ; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + }; + + simple-audio-card,codec { + sound-dai = <&mic>; + }; + }; + + mic: mic { + #sound-dai-cells = <0>; + compatible = "memsensing,msm261s4030h0"; + status = "disabled"; + }; +}; + +&fpioa { + pinctrl-0 = <&fpioa_jtag>; + pinctrl-names = "default"; + status = "okay"; + + fpioa_jtag: jtag { + pinmux = , + , + , + ; + }; + + fpioa_uarths: uarths { + pinmux = , + ; + }; + + fpioa_gpio: gpio { + pinmux = , + , + , + , + , + , + , + ; + }; + + fpioa_gpiohs: gpiohs { + pinmux = , + , + , + , + , + , + , + , + , + , + ; + }; + + fpioa_i2s0: i2s0 { + pinmux = , + , + ; + }; + + fpioa_dvp: dvp { + pinmux = , + , + , + , + , + , + , + ; + }; + + fpioa_spi0: spi0 { + pinmux = , /* cs */ + , /* rst */ + , /* dc */ + ; /* wr */ + }; + + fpioa_spi1: spi1 { + pinmux = , + , + , + ; /* cs */ + }; + + fpioa_i2c1: i2c1 { + pinmux = , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&fpioa_uarths>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + pinctrl-0 = <&fpioa_gpiohs>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio1 { + pinctrl-0 = <&fpioa_gpio>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2s0 { + #sound-dai-cells = <1>; + pinctrl-0 = <&fpioa_i2s0>; + pinctrl-names = "default"; +}; + +&i2c1 { + pinctrl-0 = <&fpioa_i2c1>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&dvp0 { + pinctrl-0 = <&fpioa_dvp>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&fpioa_spi0>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 20 0>; + + panel@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 22 0>; + spi-max-frequency = <15000000>; + status = "disabled"; + }; +}; + +&spi1 { + pinctrl-0 = <&fpioa_spi1>; + pinctrl-names = "default"; + num-cs = <1>; + polling; + status = "okay"; + + slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <4000000>; + broken-cd; + }; +}; + +&spi3 { + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + broken-flash-reset; + }; +}; From patchwork Sat Nov 7 08:14:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396086 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=NrGbMPtj; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqnl6g5cz9sTD for ; Sat, 7 Nov 2020 19:15:39 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728210AbgKGIPj (ORCPT ); Sat, 7 Nov 2020 03:15:39 -0500 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:57208 "EHLO esa3.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727801AbgKGIPj (ORCPT ); Sat, 7 Nov 2020 03:15:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1604736937; x=1636272937; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; 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07 Nov 2020 00:00:28 -0800 IronPort-SDR: iHc9bO5CQX/eWPe1AaEqyZ6T4+018t506iYLnnqFSvHCD+ZkebhjwAgxSe3mnhHw2APgvS182z 1r+3jcwy17MJU0QLhac7aimsEScFJfFvQucaLe8i3FUAOyZZ9quUryCSHKSqIEMLsES7dpvAr1 LUTGkqJ288yxUhlKxDzlCJ63ctVdmQzAGrPgcPvo6geb826DjCHJ9P9RbA5khgDZg10kvjaUNA QKOZ/pfbqV+qKlj8fJRdTQXrq11hje0U+hhkYDOJoOBPm7nN0bVDRvDMPUWogCXcMtm1nHcXBA 38U= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:15:36 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 28/32] riscv: Add SiPeed MAIX DOCK board device tree Date: Sat, 7 Nov 2020 17:14:16 +0900 Message-Id: <20201107081420.60325-29-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add a device tree for the SiPeed MAIX DOCK m1 and m1w boards. This device tree enables LEDs, gpio, i2c and spi/mmc SD card devices. Signed-off-by: Damien Le Moal --- .../boot/dts/kendryte/k210_maix_dock.dts | 229 ++++++++++++++++++ 1 file changed, 229 insertions(+) create mode 100644 arch/riscv/boot/dts/kendryte/k210_maix_dock.dts diff --git a/arch/riscv/boot/dts/kendryte/k210_maix_dock.dts b/arch/riscv/boot/dts/kendryte/k210_maix_dock.dts new file mode 100644 index 000000000000..2ae8413b1e4c --- /dev/null +++ b/arch/riscv/boot/dts/kendryte/k210_maix_dock.dts @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include + +/ { + model = "SiPeed MAIX Dock"; + compatible = "sipeed,maix-dock-m1wm", "sipeed,maix-dock-m1", + "kendryte,k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + /* + * Note: the board specification document green on gpio #4, + * red on gpio #5 and blue on gpio #6. However, the board + * is actually wired differently as defined here. + */ + blue { + gpios = <&gpio1_0 4 GPIO_ACTIVE_LOW>; + }; + + green { + gpios = <&gpio1_0 5 GPIO_ACTIVE_LOW>; + }; + + red { + gpios = <&gpio1_0 6 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + boot { + label = "BOOT"; + linux,code = ; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + }; + + simple-audio-card,codec { + sound-dai = <&mic>; + }; + }; + + mic: mic { + #sound-dai-cells = <0>; + compatible = "memsensing,msm261s4030h0"; + status = "disabled"; + }; +}; + +&fpioa { + pinctrl-0 = <&fpioa_jtag>; + pinctrl-names = "default"; + status = "okay"; + + fpioa_jtag: jtag { + pinmux = , + , + , + ; + }; + + fpioa_uarths: uarths { + pinmux = , + ; + }; + + fpioa_gpio: gpio { + pinmux = , + , + , + , + , + ; + }; + + fpioa_gpiohs: gpiohs { + pinmux = , + , + , + , + , + , + , + , + , + , + ; + }; + + fpioa_i2s0: i2s0 { + pinmux = , + , + ; + }; + + fpioa_dvp: dvp { + pinmux = , + , + , + , + , + , + , + ; + }; + + fpioa_spi0: spi0 { + pinmux = , /* cs */ + , /* rst */ + , /* dc */ + ; /* wr */ + }; + + fpioa_spi1: spi1 { + pinmux = , + , + , + ; /* cs */ + }; + + fpioa_i2c1: i2c1 { + pinmux = , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&fpioa_uarths>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + pinctrl-0 = <&fpioa_gpiohs>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio1 { + pinctrl-0 = <&fpioa_gpio>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2s0 { + #sound-dai-cells = <1>; + pinctrl-0 = <&fpioa_i2s0>; + pinctrl-names = "default"; +}; + +&i2c1 { + pinctrl-0 = <&fpioa_i2c1>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&dvp0 { + pinctrl-0 = <&fpioa_dvp>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&fpioa_spi0>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 20 0>; + + panel@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 22 0>; + spi-max-frequency = <15000000>; + status = "disabled"; + }; +}; + +&spi1 { + pinctrl-0 = <&fpioa_spi1>; + pinctrl-names = "default"; + num-cs = <1>; + polling; + status = "okay"; + + slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <4000000>; + broken-cd; + }; +}; + +&spi3 { + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + broken-flash-reset; + }; +}; From patchwork Sat Nov 7 08:14:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396087 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=Kh96Y4hj; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqnp12HTz9sRR for ; Sat, 7 Nov 2020 19:15:42 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727873AbgKGIPl (ORCPT ); Sat, 7 Nov 2020 03:15:41 -0500 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:57208 "EHLO esa3.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727801AbgKGIPl (ORCPT ); Sat, 7 Nov 2020 03:15:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1604736940; 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07 Nov 2020 16:15:40 +0800 IronPort-SDR: 5zW93m5p0Calv9I4J4xiE08cXAvyZtaWqTj91yHvgc9AlcpB+9IbetHPLVaqw+QU74hE49LsAY lr+Oy9NQviZljX3fG0nVUdR0Q8OE9R2hDGXs17KJ4QQOfi7M9HAklxsG6jDk0YfrEG2B9cV/aP 0VKWgsZdZv6+8COaJx9p7cYHDcQhv/HjgV2u/9vJwPoldewpcTOIAbI3dJM0LpQq3diEsfk40c USY+PDi2cZoq27HN0WuXY8CqgHcDQeCRoJWaZYohbhwe5mi/YhC3bp9gCshFnC+FetAVnekkpv /g1CiPac+rVNkU9UNyX2e9CB Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2020 00:00:31 -0800 IronPort-SDR: MBGZyaKY5Z+WE1I0AHYNyaKif90gu5vRzLUfMzKGP0olVXLyXoGjgS9sN+vLb6mThTKKRvAsnA KesyVKW0F2+XssFoUj6WT2XxCpDG+IfVLrYeVe3waXM3lTcrLUdWGCZs/MK55ZdUoqud9WnuM+ L9SOM3DQP/GpwcBZrhGHkGYCBuTw1JjepSx2/BYej8cFy6g6jQHmkvSOFBQXUZqh26cIHyajkp DPJLkysL4cn+puRPtRU6uZfUrjtVCz5UK3DkxkFxIedX7zbUopPYOOnNkWJvLCcp+wk9P5Myiy wLs= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:15:38 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 29/32] riscv: Add SiPeed MAIX GO board device tree Date: Sat, 7 Nov 2020 17:14:17 +0900 Message-Id: <20201107081420.60325-30-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add a device tree for the SiPeed MAIX GO board. This device tree enables buttons, LEDs, gpio, i2c and spi/mmc SD card devices. Signed-off-by: Damien Le Moal --- arch/riscv/boot/dts/kendryte/k210_maix_go.dts | 237 ++++++++++++++++++ 1 file changed, 237 insertions(+) create mode 100644 arch/riscv/boot/dts/kendryte/k210_maix_go.dts diff --git a/arch/riscv/boot/dts/kendryte/k210_maix_go.dts b/arch/riscv/boot/dts/kendryte/k210_maix_go.dts new file mode 100644 index 000000000000..8254d93a5e82 --- /dev/null +++ b/arch/riscv/boot/dts/kendryte/k210_maix_go.dts @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include + +/ { + model = "SiPeed MAIX GO"; + compatible = "sipeed,maix-go", "kendryte,k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + green { + gpios = <&gpio1_0 4 GPIO_ACTIVE_LOW>; + }; + + red { + gpios = <&gpio1_0 5 GPIO_ACTIVE_LOW>; + }; + + blue { + gpios = <&gpio1_0 6 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + up { + label = "UP"; + linux,code = ; + gpios = <&gpio1_0 7 GPIO_ACTIVE_LOW>; + }; + + press { + label = "PRESS"; + linux,code = ; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + + down { + label = "DOWN"; + linux,code = ; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + }; + + simple-audio-card,codec { + sound-dai = <&mic>; + }; + }; + + mic: mic { + #sound-dai-cells = <0>; + compatible = "memsensing,msm261s4030h0"; + status = "disabled"; + }; +}; + +&fpioa { + pinctrl-0 = <&fpioa_jtag>; + pinctrl-names = "default"; + status = "okay"; + + fpioa_jtag: jtag { + pinmux = , + , + , + ; + }; + + fpioa_uarths: uarths { + pinmux = , + ; + }; + + fpioa_gpio: gpio { + pinmux = , + , + , + , + , + , + , + ; + }; + + fpioa_gpiohs: gpiohs { + pinmux = , + , + , + , + , + , + , + , + , + , + ; + }; + + fpioa_i2s0: i2s0 { + pinmux = , + , + ; + }; + + fpioa_dvp: dvp { + pinmux = , + , + , + , + , + , + , + ; + }; + + fpioa_spi0: spi0 { + pinmux = , /* cs */ + , /* rst */ + , /* dc */ + ; /* wr */ + }; + + fpioa_spi1: spi1 { + pinmux = , + , + , + ; /* cs */ + }; + + fpioa_i2c1: i2c1 { + pinmux = , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&fpioa_uarths>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + pinctrl-0 = <&fpioa_gpiohs>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio1 { + pinctrl-0 = <&fpioa_gpio>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2s0 { + #sound-dai-cells = <1>; + pinctrl-0 = <&fpioa_i2s0>; + pinctrl-names = "default"; +}; + +&i2c1 { + pinctrl-0 = <&fpioa_i2c1>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&dvp0 { + pinctrl-0 = <&fpioa_dvp>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&fpioa_spi0>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 20 0>; + + panel@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 22 0>; + spi-max-frequency = <15000000>; + status = "disabled"; + }; +}; + +&spi1 { + pinctrl-0 = <&fpioa_spi1>; + pinctrl-names = "default"; + num-cs = <1>; + polling; + status = "okay"; + + slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <4000000>; + broken-cd; + }; +}; + +&spi3 { + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + broken-flash-reset; + }; +}; From patchwork Sat Nov 7 08:14:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396088 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=V7ZtBhHf; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqns0V6nz9sRR for ; Sat, 7 Nov 2020 19:15:45 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728241AbgKGIPo (ORCPT ); Sat, 7 Nov 2020 03:15:44 -0500 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:57208 "EHLO esa3.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727801AbgKGIPn (ORCPT ); Sat, 7 Nov 2020 03:15:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1604736943; 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07 Nov 2020 16:15:42 +0800 IronPort-SDR: FaLBOhuAiDQtt/VhCJDRlxcCJTwRVOk3BJDoWbV5bdwGIv+kf12BRzwgnr1FyNOp/Ui9Ed0i4O o3BY8OipJbyzBBu17KAwz1Ia0b++JLFnXlbXm7RRwqqHxHv0iGMDPxT4Xch16xlVQLykZEv7J3 Wm3Umx51lbylbPrFKD6OS1rH54hijIAG0diSsUFjZNK2QhY2mE7NwBx0jjA/DNHcXVVRRpVuIs NbqhA3GjhMVXsdpmdxkhoGuAFyPRiVean6sD9DpZShNCWKWdGGVUTZai2kCxyh8UlUQjwb4g8A GfKIb6zNwfNti7k+mH6p8OV+ Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2020 00:00:34 -0800 IronPort-SDR: 8bVSfo5HMd0qf0dwK5d4k2No6GNG/G+0XTossZQ1bZ2/g/jb4AIdK+c4/aNgFEpBv85e4HpS0v yMigZybGad6iqKmgtWPdYk+ygK7UPOD7ezWTLZOV/XewloNu+dWFl2lzzDbqP09lQC/Howd4Fy yrBCKAf5MgwwaDhwX2AhmtoTdz3TXHcsMHb3XOn0HWx+SnAh4oGTNRH+88eWpeXbq3D5isSADc cJKYh4FsNSi+UaBFfMwmlEGNEX/OL0kaZtZXsdwxcmulAfDOK9hFD0Rc6NyY/c+QSG6oUBpceD qh4= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:15:41 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 30/32] riscv: Add SiPeed MAIXDUINO board device tree Date: Sat, 7 Nov 2020 17:14:18 +0900 Message-Id: <20201107081420.60325-31-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add a device tree for the SiPeed MAIXDUINO board. This device tree enables LEDs and spi/mmc SD card device. Additionally, gpios and i2c are also enabled and mapped to the board header pins as indicated on the board itself. Signed-off-by: Damien Le Moal Reviewed-by: Sean Anderson --- .../boot/dts/kendryte/k210_maixduino.dts | 203 ++++++++++++++++++ 1 file changed, 203 insertions(+) create mode 100644 arch/riscv/boot/dts/kendryte/k210_maixduino.dts diff --git a/arch/riscv/boot/dts/kendryte/k210_maixduino.dts b/arch/riscv/boot/dts/kendryte/k210_maixduino.dts new file mode 100644 index 000000000000..78a37cf9df97 --- /dev/null +++ b/arch/riscv/boot/dts/kendryte/k210_maixduino.dts @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include + +/ { + model = "SiPeed MAIXDUINO"; + compatible = "sipeed,maixduino", "kendryte,k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + boot { + label = "BOOT"; + linux,code = ; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + }; + + simple-audio-card,codec { + sound-dai = <&mic>; + }; + }; + + mic: mic { + #sound-dai-cells = <0>; + compatible = "memsensing,msm261s4030h0"; + status = "disabled"; + }; +}; + +&fpioa { + status = "okay"; + + fpioa_uarths: uarths { + pinmux = , /* Header "0" */ + ; /* Header "1" */ + }; + + fpioa_gpio: gpio { + pinmux = , + ; + }; + + fpioa_gpiohs: gpiohs { + pinmux = , /* BOOT */ + , + , /* Header "2" */ + , /* Header "3" */ + , /* Header "4" */ + , /* Header "5" */ + , /* Header "6" */ + , /* Header "7" */ + , /* Header "8" */ + , /* Header "9" */ + , /* Header "10" */ + , /* Header "11" */ + , /* Header "12" */ + , /* Header "13" */ + ; + }; + + fpioa_i2s0: i2s0 { + pinmux = , + , + ; + }; + + fpioa_spi1: spi1 { + pinmux = , + , + , + ; /* cs */ + }; + + fpioa_i2c1: i2c1 { + pinmux = , /* Header "scl" */ + ; /* Header "sda" */ + }; + + fpioa_i2s1: i2s1 { + pinmux = , + , + ; + }; + + fpioa_spi0: spi0 { + pinmux = , /* cs */ + , /* rst */ + , /* dc */ + ; /* wr */ + }; + + fpioa_dvp: dvp { + pinmux = , + , + , + , + , + , + , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&fpioa_uarths>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + pinctrl-0 = <&fpioa_gpiohs>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio1 { + pinctrl-0 = <&fpioa_gpio>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2s0 { + #sound-dai-cells = <1>; + pinctrl-0 = <&fpioa_i2s0>; + pinctrl-names = "default"; +}; + +&i2c1 { + pinctrl-0 = <&fpioa_i2c1>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&dvp0 { + pinctrl-0 = <&fpioa_dvp>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&fpioa_spi0>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 20 0>; + + panel@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 22 0>; + spi-max-frequency = <15000000>; + }; +}; + +&spi1 { + pinctrl-0 = <&fpioa_spi1>; + pinctrl-names = "default"; + num-cs = <1>; + polling; + status = "okay"; + + slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <4000000>; + broken-cd; + }; +}; + +&spi3 { + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + broken-flash-reset; + }; +}; From patchwork Sat Nov 7 08:14:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396089 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; 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bh=GmhwMX9pbWxmfz+QRdKTLzObv1YycYb4GELhGYcECjA=; b=r1AQ55MPVsIXAR64nQLhC/adrvo+4teHJsyDjnP6ceBOqzN9wOecYxvx SwGONCSurftg8xPts1bY/GNYYLG9xMqf8RXYZEsxqCVwbYbz9/jzslb7f T0aVZSjTDNuEunWBcjF9q17rrestSGQAd5fkzNMuG1VvNAYVr6i/TY9XD FV/+8T8IPLCWmDsglFiG14Z6fUzDdR6pkanTA3GTQnHrxV635wCsBXf5Y MPAgwM67F1seUXEZzHwONSNqpVpC5r3G+ZsKq01pxIio+tlOAGY7zfrz2 G2mhAB+3s1AN0lcGNQiXAp25CY3eFOPcJgwDE3RHm26Rmq2MeDfWfSnUz w==; IronPort-SDR: +a225qV5Quc1/tlSeup0J977zac5/aBay2J9J52W687J3LbesVrRo52D0/fn9PdhSwSRhlv/ZN /627Or025fvO4nz5Eng2kMcvXpdDAztJ8qCn4YTK7hz5Grs12woaixJ/qAKfkaWslYw68iYS2/ 9YrslnF54mLGnsQ9+fwG66qRLeSH0JkhLEWVYV/4m9xZD4bHa5IpdDklbAgiocuxJmLnhpLxyv spU+F+F8TQx7pB/1d5AtrxF8eH0rh0+MngrMZbdaIfPXuRdr46rLwxQlPtOxiXp/n2ksalRGqb PHo= X-IronPort-AV: E=Sophos;i="5.77,459,1596470400"; d="scan'208";a="156564445" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 07 Nov 2020 16:15:45 +0800 IronPort-SDR: 41hywgjos2tj0aVvPfy3M1PPpFYFxCXiAQ/z6JlxYAWebqkefad8sa+04z8d9sBgf/NM0kF6P1 Lv49B9Gv+OlyA8Bml/BNVxK9yXO8CaCaHriAVCjHhHnSFi3GpHxkttwlI349F1kIzWja17IT+f Ut75mW0DP9Muj4mUjB250qbI6Is8X+COblrJWIAGjKYqsGIGaRu2NmJsuQjArA5GbyzvCeUzdT hb6EjDCD5wmOsnGQtHaHb9dqQU3e4PUfwlSMRDe5VqYLPhlYU7JmCvQcOX9Szaf4Zq2jHRWobi 9H7u/N652TNqr6sXPRW6SOAY Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2020 00:00:36 -0800 IronPort-SDR: xCg9hHScmcPMA7NrAzIOkRS1P0z5qRbJmWI70ya+rahrx3zb4jN2f3iPZh5CfHQF/8DP8yHJLL d46dF2QbfVTcuFr+1osT9UEquiqjtVzaPTWRssWDn8R1i5h8Sl1gGaijKF4zPIgh6ZooP5VwAU v2G7Ka+DHfnDDZzn/8q1RrY98li5TRVgLfWWBBFWXaboiLozCGil5d8zJRvPvma88LytSa4MR8 rjxx32RTlLd/LBco2Kjdleg8CZPaTR9MW75R5KAZG5xyYBhQmITQsGtO0gH5yUzim/8iuAUvNS 2Jk= WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.85]) by uls-op-cesaip01.wdc.com with ESMTP; 07 Nov 2020 00:15:43 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 31/32] riscv: Add Kendryte KD233 board device tree Date: Sat, 7 Nov 2020 17:14:19 +0900 Message-Id: <20201107081420.60325-32-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add a device tree for the Kendryte KD233 board (K210 test board). This device tree enables LEDs, some gpios and spi/mmc SD card device. The WS2812B RGB LED and the 10 position rotary dip switch present on the board are left undefined. Signed-off-by: Damien Le Moal --- arch/riscv/boot/dts/kendryte/k210_kd233.dts | 177 ++++++++++++++++++++ 1 file changed, 177 insertions(+) create mode 100644 arch/riscv/boot/dts/kendryte/k210_kd233.dts diff --git a/arch/riscv/boot/dts/kendryte/k210_kd233.dts b/arch/riscv/boot/dts/kendryte/k210_kd233.dts new file mode 100644 index 000000000000..b4e721a31000 --- /dev/null +++ b/arch/riscv/boot/dts/kendryte/k210_kd233.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include + +/ { + model = "Kendryte KD233"; + compatible = "kendryte,kd233", "kendryte,k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led0 { + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + }; + + led1 { + gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key0 { + label = "KEY0"; + linux,code = ; + gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + }; + + simple-audio-card,codec { + sound-dai = <&mic>; + }; + }; + + mic: mic { + #sound-dai-cells = <0>; + compatible = "memsensing,msm261s4030h0"; + status = "disabled"; + }; +}; + +&fpioa { + pinctrl-0 = <&fpioa_jtag>; + pinctrl-names = "default"; + status = "okay"; + + fpioa_jtag: jtag { + pinmux = , + , + , + ; + }; + + fpioa_uarths: uarths { + pinmux = , + ; + }; + + fpioa_spi0: spi0 { + pinmux = , /* cs */ + , /* wr */ + ; /* dc */ + }; + + fpioa_dvp: dvp { + pinmux = , + , + , + , + , + , + , + ; + }; + + fpioa_gpiohs: gpiohs { + pinmux = , + , /* Rot. dip sw line 8 */ + , /* Rot. dip sw line 4 */ + , /* Rot. dip sw line 2 */ + , /* Rot. dip sw line 1 */ + , + , + ; + }; + + fpioa_spi1: spi1 { + pinmux = , + , + , + ; /* cs */ + }; + + fpioa_i2s0: i2s0 { + pinmux = , + , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&fpioa_uarths>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + pinctrl-0 = <&fpioa_gpiohs>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2s0 { + #sound-dai-cells = <1>; + pinctrl-0 = <&fpioa_i2s0>; + pinctrl-names = "default"; +}; + +&dvp0 { + pinctrl-0 = <&fpioa_dvp>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&fpioa_spi0>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 20 0>; + + panel@0 { + compatible = "ilitek,ili9341"; + reg = <0>; + dc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + spi-max-frequency = <15000000>; + status = "disabled"; + }; +}; + +&spi1 { + pinctrl-0 = <&fpioa_spi1>; + pinctrl-names = "default"; + num-cs = <1>; + polling; + status = "okay"; + + slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <4000000>; + broken-cd; + }; +}; From patchwork Sat Nov 7 08:14:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1396090 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=AjTeXa+h; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CSqnx60Jbz9sSs for ; Sat, 7 Nov 2020 19:15:49 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728257AbgKGIPt (ORCPT ); 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07 Nov 2020 00:15:46 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Serge Semin , Mark Brown , linux-spi@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH 32/32] riscv: Update Kendryte K210 defconfig Date: Sat, 7 Nov 2020 17:14:20 +0900 Message-Id: <20201107081420.60325-33-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201107081420.60325-1-damien.lemoal@wdc.com> References: <20201107081420.60325-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Update the k210 nommu default configuration nommu_k210_defconfig to include device drivers for reset, reboot, I2C, gpio, LEDs and SD card support. The boot options are modified to mount the file system on the first partition of the SD card as the root file system. Signed-off-by: Damien Le Moal --- arch/riscv/configs/nommu_k210_defconfig | 45 +++++++++++++++++++------ 1 file changed, 34 insertions(+), 11 deletions(-) diff --git a/arch/riscv/configs/nommu_k210_defconfig b/arch/riscv/configs/nommu_k210_defconfig index cd1df62b13c7..dda0f437de21 100644 --- a/arch/riscv/configs/nommu_k210_defconfig +++ b/arch/riscv/configs/nommu_k210_defconfig @@ -1,13 +1,6 @@ # CONFIG_CPU_ISOLATION is not set -CONFIG_LOG_BUF_SHIFT=15 +CONFIG_LOG_BUF_SHIFT=14 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=12 -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_FORCE=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -# CONFIG_RD_XZ is not set -# CONFIG_RD_LZO is not set -# CONFIG_RD_LZ4 is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y # CONFIG_SYSFS_SYSCALL is not set # CONFIG_FHANDLE is not set @@ -25,22 +18,26 @@ CONFIG_EMBEDDED=y # CONFIG_VM_EVENT_COUNTERS is not set # CONFIG_COMPAT_BRK is not set CONFIG_SLOB=y -# CONFIG_SLAB_MERGE_DEFAULT is not set # CONFIG_MMU is not set CONFIG_SOC_KENDRYTE=y CONFIG_MAXPHYSMEM_2GB=y CONFIG_SMP=y CONFIG_NR_CPUS=2 -CONFIG_CMDLINE="earlycon console=ttySIF0" +CONFIG_CMDLINE="earlycon console=ttySIF0 rootdelay=2 root=/dev/mmcblk0p1 rw" CONFIG_CMDLINE_FORCE=y CONFIG_JUMP_LABEL=y -# CONFIG_BLOCK is not set +# CONFIG_SECCOMP is not set +# CONFIG_STACKPROTECTOR_STRONG is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_MQ_IOSCHED_DEADLINE is not set +# CONFIG_MQ_IOSCHED_KYBER is not set CONFIG_BINFMT_FLAT=y # CONFIG_COREDUMP is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y # CONFIG_FW_LOADER is not set # CONFIG_ALLOW_DEV_COREDUMP is not set +# CONFIG_BLK_DEV is not set # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_SERIO is not set @@ -48,16 +45,42 @@ CONFIG_DEVTMPFS_MOUNT=y # CONFIG_LDISC_AUTOLOAD is not set # CONFIG_HW_RANDOM is not set # CONFIG_DEVMEM is not set +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_SPI=y +# CONFIG_SPI_MEM is not set +CONFIG_SPI_DESIGNWARE=y +CONFIG_SPI_DW_MMIO=y +CONFIG_GPIO_SYSFS=y +# CONFIG_GPIO_CDEV_V1 is not set +CONFIG_GPIO_DWAPB=y +CONFIG_GPIO_SIFIVE=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y # CONFIG_HWMON is not set # CONFIG_VGA_CONSOLE is not set # CONFIG_HID is not set # CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +# CONFIG_PWRSEQ_EMMC is not set +# CONFIG_PWRSEQ_SIMPLE is not set +CONFIG_MMC_SPI=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_USER=y # CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_FILE_LOCKING is not set # CONFIG_DNOTIFY is not set # CONFIG_INOTIFY_USER is not set # CONFIG_MISC_FILESYSTEMS is not set CONFIG_LSM="[]" CONFIG_PRINTK_TIME=y +# CONFIG_SYMBOLIC_ERRNAME is not set +# CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_MISC is not set CONFIG_PANIC_ON_OOPS=y # CONFIG_SCHED_DEBUG is not set