From patchwork Fri Nov 6 02:16:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1395391 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-ide-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=OJbUVBI6; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CS3sm6Jg4z9sVT for ; Fri, 6 Nov 2020 13:16:28 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726075AbgKFCQJ (ORCPT ); Thu, 5 Nov 2020 21:16:09 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:9186 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726847AbgKFCQJ (ORCPT ); Thu, 5 Nov 2020 21:16:09 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Thu, 05 Nov 2020 18:16:12 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 6 Nov 2020 02:16:08 +0000 Received: from skomatineni-linux.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Fri, 6 Nov 2020 02:16:08 +0000 From: Sowjanya Komatineni To: , , , CC: , , , Subject: [PATCH v1 1/4] dt-bindings: ata: tegra: Convert binding documentation to YAML Date: Thu, 5 Nov 2020 18:16:05 -0800 Message-ID: <1604628968-1501-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604628968-1501-1-git-send-email-skomatineni@nvidia.com> References: <1604628968-1501-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1604628972; bh=Y0gfu4oFjOlbeIFVzhHvOaFOiOI+h4jTM3OnjcXID+g=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=OJbUVBI6ru0uW/GTGP9lA3C9FGNxOEzMtEsq04I8jCBk//pXCGlPk5cQvGwVE4IlF jIYJ+hezTvW6Ra6z749Fqdc+kyOye9hyfrO5Je4P7s9YJsdha+h7i7k/hZ6WguBtzS UZIQMO1ROYx94MvMxMRppWlidfCY7zFApe/8qsXQOOP5YpxtgXppCfYCzSqrZCFPrt 6d8+GCmu8LLMHWYwBGlBpOSwRBpSf0zVxl7znGNcBim0G0Ty9jFaIoVcXJPdkhFe/A rBgGHSGQI+IBQ+TE9voyLcSBmTCT2VwC+6WLwZ041ztB9OwJxeCBG/8ll14C3slnd2 Io/q6ifAL1Vhg== Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org This patch converts text based dt-binding document to YAML based dt-binding document. Signed-off-by: Sowjanya Komatineni --- .../devicetree/bindings/ata/nvidia,tegra-ahci.yaml | 152 +++++++++++++++++++++ .../bindings/ata/nvidia,tegra124-ahci.txt | 44 ------ 2 files changed, 152 insertions(+), 44 deletions(-) create mode 100644 Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml delete mode 100644 Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml b/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml new file mode 100644 index 0000000..ac20f6e --- /dev/null +++ b/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/nvidia,tegra-ahci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra AHCI SATA Controller + +maintainers: + - Thierry Reding + - Jonathan Hunter + +properties: + compatible: + enum: + - nvidia,tegra124-ahci + - nvidia,tegra132-ahci + - nvidia,tegra210-ahci + + reg: + minItems: 2 + maxItems: 3 + items: + - description: AHCI registers + - description: SATA configuration and IPFS registers + - description: SATA AUX registers + + interrupts: + maxItems: 1 + + clock-names: + maxItems: 2 + items: + - const: sata + - const: sata-oob + + clocks: + maxItems: 2 + description: + Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. + + reset-names: + maxItems: 3 + + resets: + maxItems: 3 + description: + Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + + phy-names: + items: + - const: sata-0 + + phys: + maxItems: 1 + description: + Must contain an entry for each entry in phy-names. + See ../phy/phy-bindings.txt for details. + + hvdd-supply: + description: SATA HVDD regulator supply. + + vddio-supply: + description: SATA VDDIO regulator supply. + + avdd-supply: + description: SATA AVDD regulator supply. + + target-5v-supply: + description: SATA 5V power regulator supply. + + target-12v-supply: + description: SATA 12V power regulator supply. + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + - reset-names + - resets + +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra124-ahci + - nvidia,tegra132-ahci + then: + properties: + reg: + maxItems: 2 + reset-names: + minItems: 3 + items: + - const: sata + - const: sata-oob + - const: sata-cold + resets: + minItems: 3 + required: + - phys + - phy-names + - hvdd-supply + - vddio-supply + - avdd-supply + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra210-ahci + then: + properties: + reg: + minItems: 3 + reset-names: + minItems: 3 + items: + - const: sata + - const: sata-oob + - const: sata-cold + resets: + minItems: 3 + +additionalProperties: true + +examples: + - | + #include + #include + + sata@70020000 { + compatible = "nvidia,tegra210-ahci"; + reg = <0x0 0x70027000 0x0 0x00002000>, /* AHCI */ + <0x0 0x70020000 0x0 0x00007000>, /* SATA */ + <0x0 0x70001100 0x0 0x00010000>; /* SATA AUX */ + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_SATA>, + <&tegra_car TEGRA210_CLK_SATA_OOB>; + clock-names = "sata", "sata-oob"; + resets = <&tegra_car 124>, + <&tegra_car 123>, + <&tegra_car 129>; + reset-names = "sata", "sata-oob", "sata-cold"; + }; diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt deleted file mode 100644 index 12ab2f7..0000000 --- a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt +++ /dev/null @@ -1,44 +0,0 @@ -Tegra SoC SATA AHCI controller - -Required properties : -- compatible : Must be one of: - - Tegra124 : "nvidia,tegra124-ahci" - - Tegra132 : "nvidia,tegra132-ahci", "nvidia,tegra124-ahci" - - Tegra210 : "nvidia,tegra210-ahci" -- reg : Should contain 2 entries: - - AHCI register set (SATA BAR5) - - SATA register set -- interrupts : Defines the interrupt used by SATA -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - - sata - - sata-oob -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - sata - - sata-oob - - sata-cold -- phys : Must contain an entry for each entry in phy-names. - See ../phy/phy-bindings.txt for details. -- phy-names : Must include the following entries: - - For Tegra124 and Tegra132: - - sata-phy : XUSB PADCTL SATA PHY -- For Tegra124 and Tegra132: - - hvdd-supply : Defines the SATA HVDD regulator - - vddio-supply : Defines the SATA VDDIO regulator - - avdd-supply : Defines the SATA AVDD regulator - - target-5v-supply : Defines the SATA 5V power regulator - - target-12v-supply : Defines the SATA 12V power regulator - -Optional properties: -- reg : - - AUX register set -- clock-names : - - cml1 : - cml1 clock should be defined here if the PHY driver - doesn't manage them. If it does, they should not be. -- phy-names : - - For T210: - - sata-phy From patchwork Fri Nov 6 02:16:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1395389 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-ide-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=jJPyXga4; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CS3sl43WCz9sSs for ; Fri, 6 Nov 2020 13:16:27 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727133AbgKFCQL (ORCPT ); Thu, 5 Nov 2020 21:16:11 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:12511 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726878AbgKFCQK (ORCPT ); Thu, 5 Nov 2020 21:16:10 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Thu, 05 Nov 2020 18:16:11 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 6 Nov 2020 02:16:09 +0000 Received: from skomatineni-linux.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Fri, 6 Nov 2020 02:16:08 +0000 From: Sowjanya Komatineni To: , , , CC: , , , Subject: [PATCH v1 2/4] dt-binding: ata: tegra: Add dt-binding documentation for Tegra186 Date: Thu, 5 Nov 2020 18:16:06 -0800 Message-ID: <1604628968-1501-3-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604628968-1501-1-git-send-email-skomatineni@nvidia.com> References: <1604628968-1501-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1604628971; bh=jTCl6Qui3XoTGmW5zT6XFx017c0RVcq1UfUg5rPZ/6Y=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=jJPyXga4yjtzIteUeGjBqAg1iSwn4oZudVkByinHNF+1+zxs5/vpz3L3hS/HggWtu dfu9C3Rw/47sklgttiud1hze/9mcrbpT9lraEcAffhp47OR6EFRfQDl/99N2OgnUtX nfyyFogd37xKKLsKizf9pKZ6Ax2Bh3pnzGPXXAuY4BUs6EOjzg5KyMtkrc3rwusPQw Fv4ugjkL8belQq8qWNbttljDH5oX2aIA4xCRv2Kjku3iatNwwFk28HZ3+67WMyckLk HFoXLN90VV215IDzQpQkD9tSeNC/joKzPYHEt0zO5K1E8Qo5Q8w1l5UqP4NxZt6GLj ihJQZa6IMzs+A== Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org This patch adds dt-bindings documentation for Tegra186 AHCI controller. Signed-off-by: Sowjanya Komatineni --- .../devicetree/bindings/ata/nvidia,tegra-ahci.yaml | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml b/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml index ac20f6e..db382a0 100644 --- a/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml +++ b/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml @@ -16,6 +16,7 @@ properties: - nvidia,tegra124-ahci - nvidia,tegra132-ahci - nvidia,tegra210-ahci + - nvidia,tegra186-ahci reg: minItems: 2 @@ -41,14 +42,37 @@ properties: See ../clocks/clock-bindings.txt for details. reset-names: + minItems: 2 maxItems: 3 resets: + minItems: 2 maxItems: 3 description: Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. + iommus: + maxItems: 1 + description: + A reference to the IOMMU. See ../iommu/iommu.txt for details. + + interconnect-names: + items: + - const: dma-mem + - const: write + + interconnects: + maxItems: 2 + description: + Pairs of phandles and interconnect provider specififer to denote + the edge source and destination ports of the interconnect path. + See ../interconnect/interconnect.txt for details. + + power-domains: + items: + - description: SAX power-domain + phy-names: items: - const: sata-0 @@ -129,6 +153,29 @@ allOf: resets: minItems: 3 + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-ahci + then: + properties: + reg: + minItems: 3 + reset-names: + maxItems: 2 + items: + - const: sata + - const: sata-cold + resets: + maxItems: 2 + required: + - iommus + - interconnect-names + - interconnects + - power-domains + additionalProperties: true examples: From patchwork Fri Nov 6 02:16:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1395385 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-ide-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=nDHroDoe; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CS3sT5wS2z9sVS for ; Fri, 6 Nov 2020 13:16:13 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727192AbgKFCQM (ORCPT ); Thu, 5 Nov 2020 21:16:12 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:12513 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727008AbgKFCQK (ORCPT ); Thu, 5 Nov 2020 21:16:10 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Thu, 05 Nov 2020 18:16:12 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 6 Nov 2020 02:16:10 +0000 Received: from skomatineni-linux.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Fri, 6 Nov 2020 02:16:09 +0000 From: Sowjanya Komatineni To: , , , CC: , , , Subject: [PATCH v1 3/4] arm64: tegra: Enable AHCI on Jetson TX2 Date: Thu, 5 Nov 2020 18:16:07 -0800 Message-ID: <1604628968-1501-4-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604628968-1501-1-git-send-email-skomatineni@nvidia.com> References: <1604628968-1501-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1604628972; bh=r3AVUbvt3RNfrllkiehC3fL0fC0040AbIRoa2VJA/gs=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=nDHroDoejbEUUp7P4sZcKrbV1s/Y+2GaJiSrVvpZU3h7y372aL6QtnWMh5GYyAYHc TeeZq8JB15LHD5X+8mJtTW4YjPoi4IkGY0qFfQHjTHRrEZSMpS5Q/aXWDNVibKKrbQ ZV7/nx4MFpYsfVduNO+z/kTjJjeU5XpecQQDAXK+pZw2UQvN1B8QuuupLMQziz9pBt IOaqhdMoN56/tHOJYBX3KQT/3ScGLPehM+8fI2c00mUbuOGJUA3DKqjjp/upuQibow 1wnMETaUuxQnUQCPm0Cc1FfWG5k57Fzj8/qGRvHt6optQrbsjsTWnuRRQTO3/oJFH+ OS6pQq2StCc+Q== Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org This patch enables AHCI on Jetson TX2. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 4 ++++ arch/arm64/boot/dts/nvidia/tegra186.dtsi | 28 ++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 381a84912..7e1723e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -297,6 +297,10 @@ }; }; + sata@3507000 { + status = "okay"; + }; + gpio-keys { compatible = "gpio-keys"; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 0c46ab7..7f5c002 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1501,6 +1501,34 @@ }; }; + sata@3507000 { + compatible = "nvidia,tegra186-ahci"; + reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ + <0x0 0x03500000 0x0 0x00007000>, /* SATA */ + <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ + interrupts = ; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_SATA>; + + clocks = <&bpmp TEGRA186_CLK_SATA>, + <&bpmp TEGRA186_CLK_SATA_OOB>; + clock-names = "sata", "sata-oob"; + assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, + <&bpmp TEGRA186_CLK_SATA_OOB>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, + <&bpmp TEGRA186_CLK_PLLP>; + assigned-clock-rates = <102000000>, + <204000000>; + resets = <&bpmp TEGRA186_RESET_SATA>, + <&bpmp TEGRA186_RESET_SATACOLD>; + reset-names = "sata", "sata-cold"; + status = "disabled"; + }; + bpmp: bpmp { compatible = "nvidia,tegra186-bpmp"; interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, From patchwork Fri Nov 6 02:16:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1395387 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-ide-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=hh+lYfEh; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CS3sc4v4Gz9sTD for ; Fri, 6 Nov 2020 13:16:20 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727027AbgKFCQU (ORCPT ); Thu, 5 Nov 2020 21:16:20 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:9190 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727055AbgKFCQL (ORCPT ); Thu, 5 Nov 2020 21:16:11 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Thu, 05 Nov 2020 18:16:14 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 6 Nov 2020 02:16:10 +0000 Received: from skomatineni-linux.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Fri, 6 Nov 2020 02:16:10 +0000 From: Sowjanya Komatineni To: , , , CC: , , , Subject: [PATCH v1 4/4] ata: ahci_tegra: Add AHCI support for Tegra186 Date: Thu, 5 Nov 2020 18:16:08 -0800 Message-ID: <1604628968-1501-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604628968-1501-1-git-send-email-skomatineni@nvidia.com> References: <1604628968-1501-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1604628974; bh=bqvYhM4gfczmD1UkOCBSQi6kCpayixLg2a8u43aYS8U=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=hh+lYfEhV8FLeCv8AXVzAksSQqoPTkC9vrZw2Y4QRhKLwrYG7oqLyP9fzzIIZ4Bby 9vmMvXEy4efwS9qc20oFTctXR5dxFOFcDgSHFJvRMMqYwqEkQyr+/GkViZyIBD/s0Z mmo7SlNzkpYkkaBgdjK9RiGAXOtFzH4VBrxoLngzRTKZLjn/yzGRO45ttz/ddVjQ8O F6395YPreV9L44J6RlCee6U2QpPYU3czoZvSIvI71cU0TBsZGDYs4cK8wO+m15UvJC 2Fm/hNorLf5+xD/E5brDtAs4hLyNAxPgYE0b46o3HWJc06PTlrPNfIHjKTHF4ohIy+ w+l79lowE8ZaA== Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org This patch adds support for AHCI-compliant Serial ATA controller on Tegra186 SoC. Tegra186 does not have sata-oob reset. Tegra186 SATA_NVOOB register filed COMMA_CNT position and width are different compared to Tegra210 and prior. So, this patch adds a flag has_sata_oob_rst and tegra_ahci_regs to SoC specific strcuture tegra_ahci_soc and updated their implementation accordingly. Signed-off-by: Sowjanya Komatineni --- drivers/ata/ahci_tegra.c | 60 +++++++++++++++++++++++++++++++++++++----------- 1 file changed, 47 insertions(+), 13 deletions(-) diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c index cb55ebc1..56612af 100644 --- a/drivers/ata/ahci_tegra.c +++ b/drivers/ata/ahci_tegra.c @@ -59,8 +59,6 @@ #define T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN BIT(22) #define T_SATA0_NVOOB 0x114 -#define T_SATA0_NVOOB_COMMA_CNT_MASK (0xff << 16) -#define T_SATA0_NVOOB_COMMA_CNT (0x07 << 16) #define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK (0x3 << 24) #define T_SATA0_NVOOB_SQUELCH_FILTER_MODE (0x1 << 24) #define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK (0x3 << 26) @@ -154,11 +152,18 @@ struct tegra_ahci_ops { int (*init)(struct ahci_host_priv *hpriv); }; +struct tegra_ahci_regs { + unsigned int nvoob_comma_cnt_mask; + unsigned int nvoob_comma_cnt_val; +}; + struct tegra_ahci_soc { const char *const *supply_names; u32 num_supplies; bool supports_devslp; + bool has_sata_oob_rst; const struct tegra_ahci_ops *ops; + const struct tegra_ahci_regs *regs; }; struct tegra_ahci_priv { @@ -240,11 +245,13 @@ static int tegra_ahci_power_on(struct ahci_host_priv *hpriv) if (ret) return ret; - ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA, - tegra->sata_clk, - tegra->sata_rst); - if (ret) - goto disable_regulators; + if (!tegra->pdev->dev.pm_domain) { + ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA, + tegra->sata_clk, + tegra->sata_rst); + if (ret) + goto disable_regulators; + } reset_control_assert(tegra->sata_oob_rst); reset_control_assert(tegra->sata_cold_rst); @@ -330,10 +337,10 @@ static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv) writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0); val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB); - val &= ~(T_SATA0_NVOOB_COMMA_CNT_MASK | + val &= ~(tegra->soc->regs->nvoob_comma_cnt_mask | T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK | T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK); - val |= (T_SATA0_NVOOB_COMMA_CNT | + val |= (tegra->soc->regs->nvoob_comma_cnt_val | T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH | T_SATA0_NVOOB_SQUELCH_FILTER_MODE); writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB); @@ -449,15 +456,35 @@ static const struct tegra_ahci_ops tegra124_ahci_ops = { .init = tegra124_ahci_init, }; +static const struct tegra_ahci_regs tegra124_ahci_regs = { + .nvoob_comma_cnt_mask = GENMASK(30, 28), + .nvoob_comma_cnt_val = (7 << 28), +}; + static const struct tegra_ahci_soc tegra124_ahci_soc = { .supply_names = tegra124_supply_names, .num_supplies = ARRAY_SIZE(tegra124_supply_names), .supports_devslp = false, + .has_sata_oob_rst = true, .ops = &tegra124_ahci_ops, + .regs = &tegra124_ahci_regs, }; static const struct tegra_ahci_soc tegra210_ahci_soc = { .supports_devslp = false, + .has_sata_oob_rst = true, + .regs = &tegra124_ahci_regs, +}; + +static const struct tegra_ahci_regs tegra186_ahci_regs = { + .nvoob_comma_cnt_mask = GENMASK(23, 16), + .nvoob_comma_cnt_val = (7 << 16), +}; + +static const struct tegra_ahci_soc tegra186_ahci_soc = { + .supports_devslp = false, + .has_sata_oob_rst = false, + .regs = &tegra186_ahci_regs, }; static const struct of_device_id tegra_ahci_of_match[] = { @@ -469,6 +496,10 @@ static const struct of_device_id tegra_ahci_of_match[] = { .compatible = "nvidia,tegra210-ahci", .data = &tegra210_ahci_soc }, + { + .compatible = "nvidia,tegra186-ahci", + .data = &tegra186_ahci_soc + }, {} }; MODULE_DEVICE_TABLE(of, tegra_ahci_of_match); @@ -518,10 +549,13 @@ static int tegra_ahci_probe(struct platform_device *pdev) return PTR_ERR(tegra->sata_rst); } - tegra->sata_oob_rst = devm_reset_control_get(&pdev->dev, "sata-oob"); - if (IS_ERR(tegra->sata_oob_rst)) { - dev_err(&pdev->dev, "Failed to get sata-oob reset\n"); - return PTR_ERR(tegra->sata_oob_rst); + if (tegra->soc->has_sata_oob_rst) { + tegra->sata_oob_rst = devm_reset_control_get(&pdev->dev, + "sata-oob"); + if (IS_ERR(tegra->sata_oob_rst)) { + dev_err(&pdev->dev, "Failed to get sata-oob reset\n"); + return PTR_ERR(tegra->sata_oob_rst); + } } tegra->sata_cold_rst = devm_reset_control_get(&pdev->dev, "sata-cold");