From patchwork Thu Nov 5 23:19:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Coiby Xu X-Patchwork-Id: 1395329 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=cn6K2b44; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CRzxl54bCz9sSs for ; Fri, 6 Nov 2020 10:19:39 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731330AbgKEXTj (ORCPT ); Thu, 5 Nov 2020 18:19:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729162AbgKEXTi (ORCPT ); Thu, 5 Nov 2020 18:19:38 -0500 Received: from mail-pg1-x543.google.com (mail-pg1-x543.google.com [IPv6:2607:f8b0:4864:20::543]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D35F9C0613CF; Thu, 5 Nov 2020 15:19:38 -0800 (PST) Received: by mail-pg1-x543.google.com with SMTP id i7so2444726pgh.6; Thu, 05 Nov 2020 15:19:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5wFU/mPUt5bnAn1NYJxaqVm9bqWLQ5tB7/uIHYHp0HQ=; b=cn6K2b44llt5xafOSAO120AEwzEoNgw63pmlOhOEOxCQd/0fzG5KHm8RyBquoOp26I ppmDj+msJvT4FQRv41AYoVm4nZ6CAg9SAvX0rt0y9HEOBTbx017Fl6V/xEVpbNHdmUpE d5nR+ARHJi7jdguTx/McGVl7pjROBNHHrM8WcRERo4R3i+VelOsPdMJHwP/kUwmebX+v kujhrMX2ID9ma1rl8/aNpKTb7f7/BI72zJwwYvfsB+KyHAUJdTXM0buchCc7hg6+Boyz Xc0wkKeVMPLwONbmipyIGr/U7OpU3DuUCqW8bXKohMEFjoGoTPQrH1vG0Ypcu6102FMt R3Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5wFU/mPUt5bnAn1NYJxaqVm9bqWLQ5tB7/uIHYHp0HQ=; b=EuTRgaabmCWQW9B+NFwifB4u9776tUHljhgOhsGSvjc/nlqhJefcVW2SYoBJSEfsvK dDGGdcbV6qioUF6CykpLcKCoCDPTK246HsxibNILUG9Gab9D4mZ3/DJ6pB3iLKzI8nn6 /ZVjroxtpJcCZJuYVcUHg/EZOEkKnP0ZHoA0VWI/cTFQLdtDG+LcYbfNklNfytTAHET7 f5JJAVCLlNqn4ZEJe2tNFuAAOyuuxN08VlDx4Rb9lj8MSfliA+QjClSvzpvBU3nFxvxE e/M7npl5dCZ3E+0zUHA+LGhULpi/40wAHFQDUPh7Rwh9RATfTP/7mb1wHv0AEMs4JVRX ZF8g== X-Gm-Message-State: AOAM533I/wwjzhT00sVf24BVX/jwSzFSQCxqmmSIsFlH+klI256Qf6zI XEVoWPdLgJIxgG3YBPxxWA8= X-Google-Smtp-Source: ABdhPJz7e1bDCO+OFo736hlZQfHXy/j66FNz6orcdPRCyRtDa0RUARQJD4awYaTYz1X6MHGmHYRGGg== X-Received: by 2002:a17:90a:a10e:: with SMTP id s14mr4466229pjp.62.1604618378487; Thu, 05 Nov 2020 15:19:38 -0800 (PST) Received: from localhost ([160.16.113.140]) by smtp.gmail.com with ESMTPSA id k5sm3487465pjs.14.2020.11.05.15.19.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2020 15:19:38 -0800 (PST) From: Coiby Xu To: Linus Walleij Cc: Andy Shevchenko , linux-gpio@vger.kernel.org, Hans de Goede , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 1/4] pinctrl: amd: fix incorrect way to disable debounce filter Date: Fri, 6 Nov 2020 07:19:09 +0800 Message-Id: <20201105231912.69527-2-coiby.xu@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201105231912.69527-1-coiby.xu@gmail.com> References: <20201105231912.69527-1-coiby.xu@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The correct way to disable debounce filter is to clear bit 5 and 6 of the register. Cc: Hans de Goede Link: https://lore.kernel.org/linux-gpio/df2c008b-e7b5-4fdd-42ea-4d1c62b52139@redhat.com/ Signed-off-by: Coiby Xu Reviewed-by: Hans de Goede --- drivers/pinctrl/pinctrl-amd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 9a760f5cd7ed..d6b2b4bd337c 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -166,14 +166,14 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); pin_reg |= BIT(DB_TMR_LARGE_OFF); } else { - pin_reg &= ~DB_CNTRl_MASK; + pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); ret = -EINVAL; } } else { pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); pin_reg &= ~BIT(DB_TMR_LARGE_OFF); pin_reg &= ~DB_TMR_OUT_MASK; - pin_reg &= ~DB_CNTRl_MASK; + pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); } writel(pin_reg, gpio_dev->base + offset * 4); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); From patchwork Thu Nov 5 23:19:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Coiby Xu X-Patchwork-Id: 1395330 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=uSzJkTaI; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CRzxt1NWDz9sSs for ; Fri, 6 Nov 2020 10:19:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732434AbgKEXTp (ORCPT ); Thu, 5 Nov 2020 18:19:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732430AbgKEXTo (ORCPT ); Thu, 5 Nov 2020 18:19:44 -0500 Received: from mail-pf1-x443.google.com (mail-pf1-x443.google.com [IPv6:2607:f8b0:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F840C0613CF; Thu, 5 Nov 2020 15:19:43 -0800 (PST) Received: by mail-pf1-x443.google.com with SMTP id e7so2557243pfn.12; Thu, 05 Nov 2020 15:19:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cU4M3aO8qNJPEDcKvc9bBkdj1lsD85B54nwk8zjxH+w=; b=uSzJkTaI8hT3mLK+ArT+3F+RuaNucDSTpT0h7/8Ymo4J0M80PMs+32Uyx+KulVsXn2 uDEl51QZtfSKP2reRpI2nb97nk9X8BkxiR6uCASh11HueeouSIws0W2lCiMHjangXABn Xdk+JU6VqGcPV2b4c0mmGQUnLjreB/y4C1btMNNsy7CWWFEyQICeuFw5/3Dr63KhLHVC kaX0TjL1P+3RkrqDYy5//IpT2EuWppraY7UFJjpjkUC22XFCo6wYZJal1NxiFNheumco uFgX5/HqPYZb2RqzKN67CjqNH/N0rYj6ONyw8BNjOciiLK1RWuceGG/D3V2N5ZDkjHHz fB/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cU4M3aO8qNJPEDcKvc9bBkdj1lsD85B54nwk8zjxH+w=; b=tOfbxtfIxWDj9DfwFI6aw4P+CU5Y/eVRgdqf/QH0wFpZuW+cnturVvBIqwOxspgqK0 BMC05TJHXsQHHc2xZJiKz0gGnr5vNvMh7CYqmalVNHlaDtVSYE4uzw96bARCDYELL+Ac 57N8ucPjTj8Xb7MHuzYy7FpusGZYsEhN2u47CZxyJstki3EszZH8ADLyHq57cgcZegW8 vEr8eR3wN2/sgQOTW5blBFWSRwiP++X+NrpSLSpau7qSP0GVHrA2NxFoN6u2ifTPTKnP fqcU1nLp5uO61dgTNcJxrMv04vQQH1uLNky7NEH6w8FqMMgVnVt3+JMbQus/0qngsmPT j9Fw== X-Gm-Message-State: AOAM532I1vBGqxXaAY6uLmGw0xTzSTNrEp2B+Nd85XGFy+LbfAIAbHnY g6gbNBOLEEZmrvR2Zk/ifWA= X-Google-Smtp-Source: ABdhPJzG+698/3x4qsSqZKPRK6U5QQsJRfmcRkBLQwF3ME8sDn+cvyXpuYK44n6CcES+uipk38t7iQ== X-Received: by 2002:a63:c6:: with SMTP id 189mr170411pga.417.1604618382788; Thu, 05 Nov 2020 15:19:42 -0800 (PST) Received: from localhost ([160.16.113.140]) by smtp.gmail.com with ESMTPSA id 34sm3393528pgv.53.2020.11.05.15.19.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2020 15:19:42 -0800 (PST) From: Coiby Xu To: Linus Walleij Cc: Andy Shevchenko , linux-gpio@vger.kernel.org, Hans de Goede , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 2/4] pinctrl: amd: use higher precision for 512 RtcClk Date: Fri, 6 Nov 2020 07:19:10 +0800 Message-Id: <20201105231912.69527-3-coiby.xu@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201105231912.69527-1-coiby.xu@gmail.com> References: <20201105231912.69527-1-coiby.xu@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org RTC is 32.768kHz thus 512 RtcClk equals 15625 usec. The documentation likely has dropped precision and that's why the driver mistakenly took the slightly deviated value. Reported-by: Andy Shevchenko Suggested-by: Andy Shevchenko Suggested-by: Hans de Goede Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/linux-gpio/2f4706a1-502f-75f0-9596-cc25b4933b6c@redhat.com/ Signed-off-by: Coiby Xu Reviewed-by: Hans de Goede --- drivers/pinctrl/pinctrl-amd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index d6b2b4bd337c..4aea3e05e8c6 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -156,7 +156,7 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); pin_reg &= ~BIT(DB_TMR_LARGE_OFF); } else if (debounce < 250000) { - time = debounce / 15600; + time = debounce / 15625; pin_reg |= time & DB_TMR_OUT_MASK; pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); pin_reg |= BIT(DB_TMR_LARGE_OFF); From patchwork Thu Nov 5 23:19:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Coiby Xu X-Patchwork-Id: 1395331 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=k+pgNX0q; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CRzy06x8Hz9sVL for ; Fri, 6 Nov 2020 10:19:52 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732414AbgKEXTs (ORCPT ); Thu, 5 Nov 2020 18:19:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732527AbgKEXTr (ORCPT ); Thu, 5 Nov 2020 18:19:47 -0500 Received: from mail-pg1-x543.google.com (mail-pg1-x543.google.com [IPv6:2607:f8b0:4864:20::543]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 97995C0613CF; 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Thu, 05 Nov 2020 15:19:47 -0800 (PST) Received: from localhost ([160.16.113.140]) by smtp.gmail.com with ESMTPSA id d4sm3397400pjj.45.2020.11.05.15.19.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2020 15:19:46 -0800 (PST) From: Coiby Xu To: Linus Walleij Cc: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 3/4] pinctrl: amd: print debounce filter info in debugfs Date: Fri, 6 Nov 2020 07:19:11 +0800 Message-Id: <20201105231912.69527-4-coiby.xu@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201105231912.69527-1-coiby.xu@gmail.com> References: <20201105231912.69527-1-coiby.xu@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Print the status of debounce filter as follows, $ cat /sys/kernel/debug/gpio pin129 interrupt is disabled| interrupt is masked| disable wakeup in S0i3 state| disable wakeup in S3 state| disable wakeup in S4/S5 state| input is high| pull-up is disabled| Pull-down is disabled| output is disabled| debouncing filter disabled| 0x50000 ^^^^^^^^^^^^^^^^^^^^^^^^^^ pin130 interrupt is disabled| interrupt is masked| disable wakeup in S0i3 state| disable wakeup in S3 state| disable wakeup in S4/S5 state| input is high| pull-up is disabled| Pull-down is disabled| output is disabled| debouncing filter (high) enabled| debouncing timeout is 124800 (us)| 0x503c8 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Signed-off-by: Coiby Xu --- drivers/pinctrl/pinctrl-amd.c | 43 +++++++++++++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 4aea3e05e8c6..e9b761c2b77a 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -197,10 +197,16 @@ static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) { u32 pin_reg; + u32 db_cntrl; unsigned long flags; unsigned int bank, i, pin_num; struct amd_gpio *gpio_dev = gpiochip_get_data(gc); + bool tmr_out_unit; + unsigned int time; + unsigned int unit; + bool tmr_large; + char *level_trig; char *active_level; char *interrupt_enable; @@ -214,6 +220,8 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) char *pull_down_enable; char *output_value; char *output_enable; + char debounce_value[40]; + char *debounce_enable; for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { seq_printf(s, "GPIO bank%d\t", bank); @@ -327,13 +335,44 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) pin_sts = "input is low|"; } + db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg; + if (db_cntrl) { + tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF); + tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF); + time = pin_reg & DB_TMR_OUT_MASK; + if (tmr_large) { + if (tmr_out_unit) + unit = 62500; + else + unit = 15625; + } else { + if (tmr_out_unit) + unit = 244; + else + unit = 61; + } + if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl) + debounce_enable = "debouncing filter (high and low) enabled|"; + else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl) + debounce_enable = "debouncing filter (low) enabled|"; + else + debounce_enable = "debouncing filter (high) enabled|"; + + snprintf(debounce_value, sizeof(debounce_value), + "debouncing timeout is %u (us)|", time * unit); + } else { + debounce_enable = "debouncing filter disabled|"; + snprintf(debounce_value, sizeof(debounce_value), " "); + } + seq_printf(s, "%s %s %s %s %s %s\n" - " %s %s %s %s %s %s %s 0x%x\n", + " %s %s %s %s %s %s %s %s %s 0x%x\n", level_trig, active_level, interrupt_enable, interrupt_mask, wake_cntrl0, wake_cntrl1, wake_cntrl2, pin_sts, pull_up_sel, pull_up_enable, pull_down_enable, - output_value, output_enable, pin_reg); + output_value, output_enable, + debounce_enable, debounce_value, pin_reg); } } } From patchwork Thu Nov 5 23:19:12 2020 Content-Type: text/plain; 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Thu, 05 Nov 2020 15:19:50 -0800 (PST) From: Coiby Xu To: Linus Walleij Cc: Andy Shevchenko , linux-gpio@vger.kernel.org, Hans de Goede , Benjamin Tissoires , stable@vger.kernel.org, linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 4/4] pinctrl: amd: remove debounce filter setting in IRQ type setting Date: Fri, 6 Nov 2020 07:19:12 +0800 Message-Id: <20201105231912.69527-5-coiby.xu@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201105231912.69527-1-coiby.xu@gmail.com> References: <20201105231912.69527-1-coiby.xu@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Debounce filter setting should be independent from IRQ type setting because according to the ACPI specs, there are separate arguments for specifying debounce timeout and IRQ type in GpioIo() and GpioInt(). This will fix broken touchpads for laptops whose BIOS set the debounce timeout to a relatively large value. For example, the BIOS of Lenovo Legion-5 AMD gaming laptops including 15ARH05 (R7000) and R7000P set the debounce timeout to 124.8ms. This led to the kernel receiving only ~7 HID reports per second from the Synaptics touchpad (MSFT0001:00 06CB:7F28). Existing touchpads like [1][2] are not troubled by this bug because the debounce timeout has been set to 0 by the BIOS before enabling the debounce filter in setting IRQ type. [1] https://github.com/Syniurge/i2c-amd-mp2/issues/11#issuecomment-721331582 [2] https://forum.manjaro.org/t/random-short-touchpad-freezes/30832/28 Cc: Hans de Goede Cc: Andy Shevchenko Cc: Benjamin Tissoires Cc: stable@vger.kernel.org Reviewed-by: Andy Shevchenko BugLink: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1887190 Link: https://lore.kernel.org/linux-gpio/CAHp75VcwiGREBUJ0A06EEw-SyabqYsp%2Bdqs2DpSrhaY-2GVdAA%40mail.gmail.com/ Signed-off-by: Coiby Xu Acked-by: Linus Walleij --- drivers/pinctrl/pinctrl-amd.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index e9b761c2b77a..2d4acf21117c 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -468,7 +468,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) pin_reg &= ~BIT(LEVEL_TRIG_OFF); pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; - pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; irq_set_handler_locked(d, handle_edge_irq); break; @@ -476,7 +475,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) pin_reg &= ~BIT(LEVEL_TRIG_OFF); pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; - pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; irq_set_handler_locked(d, handle_edge_irq); break; @@ -484,7 +482,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) pin_reg &= ~BIT(LEVEL_TRIG_OFF); pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; - pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; irq_set_handler_locked(d, handle_edge_irq); break; @@ -492,8 +489,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; - pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); - pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF; irq_set_handler_locked(d, handle_level_irq); break; @@ -501,8 +496,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; - pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); - pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF; irq_set_handler_locked(d, handle_level_irq); break;