From patchwork Wed Nov 4 08:50:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1393706 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=qcoyRoCZ; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CR0lh63wdz9sPB for ; Wed, 4 Nov 2020 19:52:32 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728678AbgKDIw2 (ORCPT ); Wed, 4 Nov 2020 03:52:28 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:2627 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728675AbgKDIwU (ORCPT ); Wed, 4 Nov 2020 03:52:20 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Wed, 04 Nov 2020 00:52:22 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 4 Nov 2020 08:52:16 +0000 Received: from vidyas-desktop.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Wed, 4 Nov 2020 08:52:12 +0000 From: Vidya Sagar To: , , , , , , , CC: , , , , , , Subject: [PATCH V3 1/5] PCI: tegra: Fix ASPM-L1SS advertisement disable code Date: Wed, 4 Nov 2020 14:20:14 +0530 Message-ID: <20201104085018.13021-2-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201104085018.13021-1-vidyas@nvidia.com> References: <20201104085018.13021-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1604479942; bh=pE6B5W32IRU6jU0blW1A2aBVvj4gHjrSf7CmW+Ju6pg=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=qcoyRoCZ0piUYe73ac3RXhzFqb2XBUMAuLGZRxa+DjUUQ5uozNBm3gFVaoF5cyHQQ mbqzO9QHYJTjrKgl4cAn++kssJLlXXLQebPPOghBi4Y3q1rnKU89Thed9MLnWW9HeD xbhG0wgKxqBSk4esSaGr2HY66uIbG/Q5alsc9BdnUjORlIp8kuGfRX20iV9GwCeDan aab0YZCQbePSm0DP2XG/UlH0qNLAJADjyYKvcNdik0SdB7KViwJo2hGTgVyXjRC6F5 PY+0BIpRq4DV5+HHt7nSRwiZt3V4OhydPMpC+d9rnw0UfjDG4Yr3fiLhWdmnAtCb0r dhUpxYsdCUumw== Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org If the absence of CLKREQ# signal is indicated by the absence of "supports-clkreq" in the device-tree node, current driver is disabling the advertisement of ASPM-L1 Sub-States *before* the ASPM-L1 Sub-States offset is correctly initialized. Since default value of the ASPM-L1SS offset is zero, this is causing the Vendor-ID wrongly programmed to 0x10d2 instead of Nvidia's 0x10de thereby the quirks applicable for Tegra194 are not being applied. This patch fixes this issue by refactoring the code that disables the ASPM-L1SS advertisement. Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Signed-off-by: Vidya Sagar --- V3: * None V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index aa511ec0d800..b172b1d49713 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -896,6 +896,12 @@ static void tegra_pcie_prepare_host(struct pcie_port *pp) init_host_aspm(pcie); + /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ + if (!pcie->supports_clkreq) { + disable_aspm_l11(pcie); + disable_aspm_l12(pcie); + } + val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); @@ -1400,12 +1406,6 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, PCI_CAP_ID_EXP); - /* Disable ASPM-L1SS advertisement as there is no CLKREQ routing */ - if (!pcie->supports_clkreq) { - disable_aspm_l11(pcie); - disable_aspm_l12(pcie); - } - return ret; fail_phy: From patchwork Wed Nov 4 08:50:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1393703 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=pljk4JTc; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CR0lX6M5bz9sPB for ; Wed, 4 Nov 2020 19:52:24 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728683AbgKDIwX (ORCPT ); Wed, 4 Nov 2020 03:52:23 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:5993 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728679AbgKDIwX (ORCPT ); Wed, 4 Nov 2020 03:52:23 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Wed, 04 Nov 2020 00:52:22 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 4 Nov 2020 08:52:22 +0000 Received: from vidyas-desktop.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Wed, 4 Nov 2020 08:52:18 +0000 From: Vidya Sagar To: , , , , , , , CC: , , , , , , Subject: [PATCH V3 2/5] PCI: tegra: Map configuration space as nGnRnE Date: Wed, 4 Nov 2020 14:20:15 +0530 Message-ID: <20201104085018.13021-3-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201104085018.13021-1-vidyas@nvidia.com> References: <20201104085018.13021-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1604479942; bh=iPvrvcjkmUg2V+eK69c4S38RPbTDBf/mrJL3XR/YNOw=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=pljk4JTcxqstuGwgb41fF7V5SpD+760cLPwp6NT7T9fHva87gIjLHHhlZ+iJu9oBD aXDL7D8GtMj/BBK45zRnlinym4ycJ9bH+VtJz7uoGHgsck9/nYyuJ/qHWstHCIKXjH nJV7TG/T1Aap+TKzlE4BqQ3OpS9jjl+tCvuO8gtP0Z8TccRtFAimlXjqrLyXRg81xu gzBLogEAeLB2DJDIEDxU/pAdUbosfbwGiG/6rLNUtgl482QT7jwzBJMz0hqg0u07DU u8nHgprObbsMgqaXhWRod66HcnjF8XgDQNfrneGRqlpbgV8xm5tTm/LK35aqGjzCrx poU8JNycMV3Sw== Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org As specified in the comment for pci_remap_cfgspace() define in arch/arm64/include/asm/io.h file, PCIe configuration space should be mapped as nGnRnE. Hence changing to dev_pci_remap_cfgspace() from devm_ioremap_resource() for mapping DBI space as that is nothing but the root port's own configuration space. Signed-off-by: Vidya Sagar --- V3: * None V2: * Changed 'Strongly Ordered' to 'nGnRnE' drivers/pci/controller/dwc/pcie-tegra194.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index b172b1d49713..7a0c64436861 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2108,7 +2108,9 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev) } pcie->dbi_res = dbi_res; - pci->dbi_base = devm_ioremap_resource(dev, dbi_res); + pci->dbi_base = devm_pci_remap_cfgspace(dev, + dbi_res->start, + resource_size(dbi_res)); if (IS_ERR(pci->dbi_base)) return PTR_ERR(pci->dbi_base); From patchwork Wed Nov 4 08:50:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1393708 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=pRAaalLv; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CR0ln6CrNz9sTK for ; Wed, 4 Nov 2020 19:52:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726029AbgKDIwd (ORCPT ); Wed, 4 Nov 2020 03:52:33 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:6017 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728841AbgKDIwd (ORCPT ); Wed, 4 Nov 2020 03:52:33 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Wed, 04 Nov 2020 00:52:32 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 4 Nov 2020 08:52:29 +0000 Received: from vidyas-desktop.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Wed, 4 Nov 2020 08:52:25 +0000 From: Vidya Sagar To: , , , , , , , CC: , , , , , , Subject: [PATCH V3 3/5] PCI: tegra: Set DesignWare IP version Date: Wed, 4 Nov 2020 14:20:16 +0530 Message-ID: <20201104085018.13021-4-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201104085018.13021-1-vidyas@nvidia.com> References: <20201104085018.13021-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1604479952; bh=vQOp09k8Olf7pGN54LhCH3GMJTN3ReO8f6pSXafBmVc=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=pRAaalLvdnzxFZ7tmAVZRSxBZ7S5qIQHUxwJ8/U/K8iw73G5yTilDuIXTSyp4rG/4 v5E9WyW11VzQCEyPY7RY6r224imkxk3wNQamF/AMsr5CM8ZyDxxsTBs+1SNo0y3W+J 8j4qYUuoYl2D2E7XwoDPvIB0JTKHF7piN/oodXmIZMWYhZCgv4grDeHYj5tgBbMq0I dnB5uH+grqrAeFMSFGAfC5pWv20BxUfgkZn3qVR6Zd7aNBIDy3Kb0C1AomkAnwBsaL 5Je+0vxT+QvecKIeXY4SdkuoU24jHeN59S9esnP395wObN9Wn6JQTxjXWBFljpWxNp +cjb1t9B/QdsQ== Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Set the DesignWare IP version for Tegra194 to 0x490A. This would be used by the DesigWare sub-system to do any version specific configuration (Ex:- TD bit programming for ECRC). Signed-off-by: Vidya Sagar --- V3: * None V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 7a0c64436861..253d91033bc3 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2011,6 +2011,7 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev) pci->ops = &tegra_dw_pcie_ops; pci->n_fts[0] = N_FTS_VAL; pci->n_fts[1] = FTS_VAL; + pci->version = 0x490A; pp = &pci->pp; pcie->dev = &pdev->dev; From patchwork Wed Nov 4 08:50:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1393710 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=TgqudBjD; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CR0lq15nQz9sPB for ; Wed, 4 Nov 2020 19:52:39 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728889AbgKDIwi (ORCPT ); Wed, 4 Nov 2020 03:52:38 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:6022 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728675AbgKDIwh (ORCPT ); Wed, 4 Nov 2020 03:52:37 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Wed, 04 Nov 2020 00:52:36 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 4 Nov 2020 08:52:36 +0000 Received: from vidyas-desktop.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Wed, 4 Nov 2020 08:52:32 +0000 From: Vidya Sagar To: , , , , , , , CC: , , , , , , Subject: [PATCH V3 4/5] PCI: tegra: Continue unconfig sequence even if parts fail Date: Wed, 4 Nov 2020 14:20:17 +0530 Message-ID: <20201104085018.13021-5-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201104085018.13021-1-vidyas@nvidia.com> References: <20201104085018.13021-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1604479956; bh=NTU9fqj88EFlCQxwql10C8vOX1XMlMilgH1XPS4W2nA=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=TgqudBjDRvToLkVVuuS9hsuTrRZqka4zOE5gdItbk6bSrwALi5PWL1+YBDdG9SBdk 1IuOaNJ1+QjsHhWsxQreEXV8QdrfZk8YQW5+DAg/JNYh1LQmruI6lx2CTe1LSNTfHo +0WADPijaPEbtnnX8W6NIxicNH4ortTdSaSAf3pPfPUUPpADTCDqe6dccThDN6A9iU aheTpGztR5p4w3wxtvytlWb4B4V3ILoIOGTgPtxOCUTWn7VYLE6URaWS6VyajhfqCN 2nlkXS9xJNXXb1OsfhEwcObh25ndwKgQTl+vpmHO6blQKxxHFJaW5UMehf70p9cpIN l7XHiLpyGszUQ== Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Currently the driver checks for error value of different APIs during the uninitialization sequence. It just returns from there if there is any error observed for one of those calls. Comparatively it is better to continue the uninitialization sequence irrespective of whether some of them are returning error. That way, it is more closer to complete uninitialization. Signed-off-by: Vidya Sagar --- V3: * Modified subject as per Bjorn's suggestion * Removed tegra_pcie_init_controller()'s error checking part and pushed a separate patch for it V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 39 +++++++++------------- 1 file changed, 15 insertions(+), 24 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 253d91033bc3..9be10c8953df 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1422,43 +1422,32 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, return ret; } -static int __deinit_controller(struct tegra_pcie_dw *pcie) +static void tegra_pcie_unconfig_controller(struct tegra_pcie_dw *pcie) { int ret; ret = reset_control_assert(pcie->core_rst); - if (ret) { - dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", - ret); - return ret; - } + if (ret) + dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", ret); tegra_pcie_disable_phy(pcie); ret = reset_control_assert(pcie->core_apb_rst); - if (ret) { + if (ret) dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret); - return ret; - } clk_disable_unprepare(pcie->core_clk); ret = regulator_disable(pcie->pex_ctl_supply); - if (ret) { + if (ret) dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret); - return ret; - } tegra_pcie_disable_slot_regulators(pcie); ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false); - if (ret) { + if (ret) dev_err(pcie->dev, "Failed to disable controller %d: %d\n", pcie->cid, ret); - return ret; - } - - return ret; } static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie) @@ -1482,7 +1471,8 @@ static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie) return 0; fail_host_init: - return __deinit_controller(pcie); + tegra_pcie_unconfig_controller(pcie); + return ret; } static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie) @@ -1551,13 +1541,12 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie) appl_writel(pcie, data, APPL_PINMUX); } -static int tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie) +static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie) { tegra_pcie_downstream_dev_to_D0(pcie); dw_pcie_host_deinit(&pcie->pci.pp); tegra_pcie_dw_pme_turnoff(pcie); - - return __deinit_controller(pcie); + tegra_pcie_unconfig_controller(pcie); } static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) @@ -2238,8 +2227,9 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev) PORT_LOGIC_MSI_CTRL_INT_0_EN); tegra_pcie_downstream_dev_to_D0(pcie); tegra_pcie_dw_pme_turnoff(pcie); + tegra_pcie_unconfig_controller(pcie); - return __deinit_controller(pcie); + return 0; } static int tegra_pcie_dw_resume_noirq(struct device *dev) @@ -2267,7 +2257,8 @@ static int tegra_pcie_dw_resume_noirq(struct device *dev) return 0; fail_host_init: - return __deinit_controller(pcie); + tegra_pcie_unconfig_controller(pcie); + return ret; } static int tegra_pcie_dw_resume_early(struct device *dev) @@ -2305,7 +2296,7 @@ static void tegra_pcie_dw_shutdown(struct platform_device *pdev) disable_irq(pcie->pci.pp.msi_irq); tegra_pcie_dw_pme_turnoff(pcie); - __deinit_controller(pcie); + tegra_pcie_unconfig_controller(pcie); } static const struct tegra_pcie_dw_of_data tegra_pcie_dw_rc_of_data = { From patchwork Wed Nov 4 08:50:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1393712 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=pZrMuYJE; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CR0m23cX9z9sPB for ; Wed, 4 Nov 2020 19:52:50 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728902AbgKDIwq (ORCPT ); Wed, 4 Nov 2020 03:52:46 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:2695 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728886AbgKDIwp (ORCPT ); Wed, 4 Nov 2020 03:52:45 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Wed, 04 Nov 2020 00:52:47 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 4 Nov 2020 08:52:42 +0000 Received: from vidyas-desktop.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Wed, 4 Nov 2020 08:52:37 +0000 From: Vidya Sagar To: , , , , , , , CC: , , , , , , Subject: [PATCH V3 5/5] PCI: tegra: Check return value of tegra_pcie_init_controller() Date: Wed, 4 Nov 2020 14:20:18 +0530 Message-ID: <20201104085018.13021-6-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201104085018.13021-1-vidyas@nvidia.com> References: <20201104085018.13021-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1604479967; bh=n8XdfeCZduO7ogcyhJVAlYbsvTFqkbs1wknNZ3ixbf4=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=pZrMuYJElTBvismIA6kjwVHxaFE7FOuOChV1MmIorPgM+RhqDiJy8iiv9KlR5oVNW QylfQbhVrOJU/rAGAJ1+EfK4wzHIz1SnGUDFHuRQOnEd1rgytRVYZv0U5pkTh1fqGO YqSCoHqVq6vEGSApK/hxHN434Qb2o0SCkKN/iN8L7/1lU8ThikxdcfB4mV/J8b+cIM 9pYpoI4Ti1QYh6P3JOfOb1IH75RfqD6Q3CdviNkTzHPrXkimf2zwZpynPowkKl0jaS 35nqtU/5psp54DQ6LwFO0K/aJSXJg2rylUVTcU0BoRn2Lrb+BbG0di9y1FUBPJhE/t pK41dEitL4G3Q== Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The return value of tegra_pcie_init_controller() must be checked before PCIe link up check and registering debugfs entries subsequently as it doesn't make sense to do these when the controller initialization itself has failed. Signed-off-by: Vidya Sagar --- V3: * New patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 9be10c8953df..8c08998b9ce1 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1579,7 +1579,11 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) goto fail_pm_get_sync; } - tegra_pcie_init_controller(pcie); + ret = tegra_pcie_init_controller(pcie); + if (ret < 0) { + dev_err(dev, "Failed to initialize controller: %d\n", ret); + goto fail_pm_get_sync; + } pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci); if (!pcie->link_state) {