From patchwork Fri Sep 8 07:11:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 811363 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="fbrs3Wwm"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xpTFB6181z9s83 for ; Fri, 8 Sep 2017 17:18:22 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755155AbdIHHSK (ORCPT ); Fri, 8 Sep 2017 03:18:10 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:35924 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754895AbdIHHOK (ORCPT ); Fri, 8 Sep 2017 03:14:10 -0400 Received: by mail-wm0-f65.google.com with SMTP id p17so1126473wmd.3; Fri, 08 Sep 2017 00:14:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7ByCPcpjDFJcAIBA+PvkRivoKy4yVINsIMWthyYfHsk=; b=fbrs3Wwm3ai9vNJt6wnCeHKtbFcAdBTyVehYDnYNCDnkcvUOw4CHD/oa1u/z5Gy5Ra omhr4F603Wgz6FLVkCHHWZjShdeipd8dMoEBzNkYUvoXTuu9xIFQmWCtWxCPPcqX5BSW egQ3/N+Fb+Gp9c7/Xscdq4Dlj4qq/4guDbwskG1+lbzOmfk26DPfx+/I96c9uMAUdLUg N71T/+uXXQBvcgteWQhw8qHenszhdjwQ37FhAS717JAEGHQJ3n+BfkZejHWkBhT5Fd9k aoQckgGB/ppszmoY0Gt1BXAyl3CLigLrlffEXkdwNZprhMv5NZjd0R60Uhdd292k/A+b GP7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7ByCPcpjDFJcAIBA+PvkRivoKy4yVINsIMWthyYfHsk=; b=gIb6MLGb5C38ISeMHwlj5voK8DxGI+In8RVNvrlp57v7urt0vNBI5DLphQtpsuq59Z lOEy2KqaXhFdUx/HFIKaN9EjBvGh8Y2/aTuVOI1DpjTj82mE1NXo4pLR9oHUvzqmeYzS DO1mIR1at52tutmt9d2+4mmQrgNhRxjf6AJz019SR3Wx8mD36v7ZEkUHQ9ZYBwZGv5/t vcVUeVZ6WXcfKe5y7Edi/cVMULpiRSASFd8VC49ALhmnn+ZIq681l/TK3iDB+BycC5yr HF4fbKbjFIsC8nuchs8nOZ1OdOdWn0rluIp/37/31QYrMrZn7Dm77koBYVYiPnHuSb7b crtg== X-Gm-Message-State: AHPjjUio1qX+nn9v+v50VJ2tcjSC+bvZcEvXMh7DTltrAjtVcwI41agf 9oaAzfNeeXKZ8g== X-Google-Smtp-Source: AOwi7QCKSqL5FDxnvap5SPnAkhcwLKxnP22uT3JtPfEQ7m7RfREhW7s2/+W+lecCOJ4OCttamCHv5Q== X-Received: by 10.28.30.21 with SMTP id e21mr860464wme.7.1504854848733; Fri, 08 Sep 2017 00:14:08 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id l19sm684566wrl.47.2017.09.08.00.14.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Sep 2017 00:14:08 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v5 01/10] arm64: dts: allwinner: Restore EMAC changes Date: Fri, 8 Sep 2017 09:11:47 +0200 Message-Id: <20170908071156.5115-2-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170908071156.5115-1-clabbe.montjoie@gmail.com> References: <20170908071156.5115-1-clabbe.montjoie@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch restore arm64 DT about dwmac-sun8i This reverts commit 87e1f5e8bb4b ("arm64: dts: allwinner: Revert EMAC changes") Signed-off-by: Corentin Labbe --- .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 16 ++++++++++++++++ .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 15 +++++++++++++++ arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 17 +++++++++++++++++ .../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 20 ++++++++++++++++++++ .../boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 17 +++++++++++++++++ .../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 17 +++++++++++++++++ .../boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 17 +++++++++++++++++ 8 files changed, 135 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index d347f52e27f6..45bdbfb96126 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -51,6 +51,7 @@ compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64"; aliases { + ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; }; @@ -69,6 +70,14 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + status = "okay"; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; @@ -79,6 +88,13 @@ bias-pull-up; }; +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts index f82ccf332c0f..24f1aac366d6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts @@ -48,3 +48,18 @@ /* TODO: Camera, touchscreen, etc. */ }; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts index caf8b6fbe5e3..6f209bb10a2f 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -51,6 +51,7 @@ compatible = "pine64,pine64", "allwinner,sun50i-a64"; aliases { + ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -78,6 +79,15 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins>; + phy-mode = "rmii"; + phy-handle = <&ext_rmii_phy1>; + status = "okay"; + +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; @@ -88,6 +98,13 @@ bias-pull-up; }; +&mdio { + ext_rmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts index 17ccc12b58df..0eb2acedf8c3 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts @@ -53,6 +53,7 @@ "allwinner,sun50i-a64"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -76,6 +77,21 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 75e8d3182535..4dd9ffef0d80 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -461,6 +461,26 @@ #size-cells = <0>; }; + emac: ethernet@1c30000 { + compatible = "allwinner,sun50i-a64-emac"; + syscon = <&syscon>; + reg = <0x01c30000 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts index 1c2387bd5df6..968908761194 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts @@ -50,6 +50,7 @@ compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -108,6 +109,22 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts index 4f77c8470f6c..a8296feee884 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts @@ -59,6 +59,7 @@ }; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -136,12 +137,28 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; status = "okay"; }; +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts index 6be06873e5af..d906b302cbcd 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts @@ -54,6 +54,7 @@ compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -143,12 +144,28 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; status = "okay"; }; +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; From patchwork Fri Sep 8 07:11:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 811359 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="INLF5B7R"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xpTCd5LYTz9sBd for ; Fri, 8 Sep 2017 17:17:01 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755070AbdIHHOO (ORCPT ); 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id l19sm684566wrl.47.2017.09.08.00.14.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Sep 2017 00:14:09 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v5 02/10] dt-bindings: net: Restore sun8i dwmac binding Date: Fri, 8 Sep 2017 09:11:48 +0200 Message-Id: <20170908071156.5115-3-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170908071156.5115-1-clabbe.montjoie@gmail.com> References: <20170908071156.5115-1-clabbe.montjoie@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch restore dt-bindings documentation about dwmac-sun8i This reverts commit 8aa33ec2f481 ("dt-bindings: net: Revert sun8i dwmac binding") Signed-off-by: Corentin Labbe Acked-by: Rob Herring --- .../devicetree/bindings/net/dwmac-sun8i.txt | 84 ++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt new file mode 100644 index 000000000000..725f3b187886 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt @@ -0,0 +1,84 @@ +* Allwinner sun8i GMAC ethernet controller + +This device is a platform glue layer for stmmac. +Please see stmmac.txt for the other unchanged properties. + +Required properties: +- compatible: should be one of the following string: + "allwinner,sun8i-a83t-emac" + "allwinner,sun8i-h3-emac" + "allwinner,sun8i-v3s-emac" + "allwinner,sun50i-a64-emac" +- reg: address and length of the register for the device. +- interrupts: interrupt for the device +- interrupt-names: should be "macirq" +- clocks: A phandle to the reference clock for this device +- clock-names: should be "stmmaceth" +- resets: A phandle to the reset control for this device +- reset-names: should be "stmmaceth" +- phy-mode: See ethernet.txt +- phy-handle: See ethernet.txt +- #address-cells: shall be 1 +- #size-cells: shall be 0 +- syscon: A phandle to the syscon of the SoC with one of the following + compatible string: + - allwinner,sun8i-h3-system-controller + - allwinner,sun8i-v3s-system-controller + - allwinner,sun50i-a64-system-controller + - allwinner,sun8i-a83t-system-controller + +Optional properties: +- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0) +- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0) +Both delay properties need to be a multiple of 100. They control the delay for +external PHY. + +Optional properties for the following compatibles: + - "allwinner,sun8i-h3-emac", + - "allwinner,sun8i-v3s-emac": +- allwinner,leds-active-low: EPHY LEDs are active low + +Required child node of emac: +- mdio bus node: should be named mdio + +Required properties of the mdio node: +- #address-cells: shall be 1 +- #size-cells: shall be 0 + +The device node referenced by "phy" or "phy-handle" should be a child node +of the mdio node. See phy.txt for the generic PHY bindings. + +Required properties of the phy node with the following compatibles: + - "allwinner,sun8i-h3-emac", + - "allwinner,sun8i-v3s-emac": +- clocks: a phandle to the reference clock for the EPHY +- resets: a phandle to the reset control for the EPHY + +Example: + +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; +}; From patchwork Fri Sep 8 07:11:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 811361 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="A/AoMMuu"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xpTDN5GNrz9sBd for ; Fri, 8 Sep 2017 17:17:40 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932464AbdIHHRi (ORCPT ); Fri, 8 Sep 2017 03:17:38 -0400 Received: from mail-wr0-f195.google.com ([209.85.128.195]:34172 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754997AbdIHHOM (ORCPT ); Fri, 8 Sep 2017 03:14:12 -0400 Received: by mail-wr0-f195.google.com with SMTP id k20so828451wre.1; Fri, 08 Sep 2017 00:14:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jjow1PiJRghfIdXg0T9kG+hE68uHysVJ6Loe8SEP3js=; b=A/AoMMuuoFQQ7mPJasfarUP0BTcpPeuPMCwbdD45Xgu7JNdIpFJEeIkvRza4dRqyGI EskRZxkkwB3J21njWJnaKxq6EV+LESzTCYZ0JJ6QTf7BGEyNtdxHUgqGHDyBVFSZ/Lcy yJUoyW7Jnx+l/ONdbniCP7i05rVS07e0U9gS55dV0T1YGpkroUpCYeiVaT64bPhOgW54 fZKg0D9V9PBUzxcLeR0nnDqaAwwvdchMAiYVGnjbcFuJPtysYZKlfUQsMxUwCN50oxCF 3fG24dIj2UWd60eeBexqfpf7bxDWkO3LeGh5fvQ4/pyiUZZnAHt60I4nHQKdYNY/ZKJB 3NRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jjow1PiJRghfIdXg0T9kG+hE68uHysVJ6Loe8SEP3js=; b=P6yl0ePH/XDQaAXkA8Sx0/CojpkMuIGqCy44LhdTJTeHcbfE3o1Lh6V6bg7CVenG/T LHgKxa93a+j/pcVI8X4XjkJ0K/gRoC8v10DQlZ8//iVNEktxW7Ym3x+X1JkTZ5rKW72x gpHXRdGzz/H/8rFbTPB3YNNFyIiq/L9udbr3ymtSh80TquKpGik4BM6ilMxNgK5rHsjg GEVkILym/wxVhczDeJfn/PUBRak8IKSBmpzMGifjyIu6sEcPhbxk7fWWxfjZDTg3lVxv De+A3FFRFNtuIFge/2uYMke0VbHs9Q610ZZdpJ7Y4MRfOjO+0yB7tlmAwGgVA1mdACjA oeZQ== X-Gm-Message-State: AHPjjUhpXklF5xtAznRe3FRlkaHKv6VyAWfn4YIXJ68gOOpf0qkOxkaN 8dmzSnTH5mvXiw== X-Google-Smtp-Source: ADKCNb6lR/lFhLzyBsM4J+RocbeJD+U72ezIo0oie12B85/T4qcgckYpXga8XRShI5aKKso79FNM2w== X-Received: by 10.223.139.200 with SMTP id w8mr1317502wra.172.1504854850981; Fri, 08 Sep 2017 00:14:10 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id l19sm684566wrl.47.2017.09.08.00.14.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Sep 2017 00:14:10 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v5 03/10] arm: dts: sunxi: Restore EMAC changes Date: Fri, 8 Sep 2017 09:11:49 +0200 Message-Id: <20170908071156.5115-4-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170908071156.5115-1-clabbe.montjoie@gmail.com> References: <20170908071156.5115-1-clabbe.montjoie@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch restore arm DT about dwmac-sun8i This reverts commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes") Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 9 ++++++++ arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 19 +++++++++++++++++ arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 ++++++ arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 +++++++ arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 8 +++++++ arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 5 +++++ arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 8 +++++++ arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 22 +++++++++++++++++++ arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts | 16 ++++++++++++++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 26 +++++++++++++++++++++++ 10 files changed, 128 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts index b1502df7b509..6713d0f2b3f4 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts @@ -56,6 +56,8 @@ aliases { serial0 = &uart0; + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet0 = &emac; ethernet1 = &xr819; }; @@ -102,6 +104,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts index a337af1de322..d756ff825116 100644 --- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts @@ -52,6 +52,7 @@ compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; }; @@ -114,12 +115,30 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + allwinner,leds-active-low; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; status = "okay"; }; +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts index 8d2cc6e9a03f..78f6c24952dd 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts @@ -46,3 +46,10 @@ model = "FriendlyARM NanoPi NEO"; compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; }; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts index 8ff71b1bb45b..17cdeae19c6f 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -54,6 +54,7 @@ aliases { serial0 = &uart0; /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet0 = &emac; ethernet1 = &rtl8189; }; @@ -117,6 +118,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts index 5fea430e0eb1..6880268e8b87 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts @@ -52,6 +52,7 @@ compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -97,6 +98,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts index 8b93f5c781a7..a10281b455f5 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts @@ -53,6 +53,11 @@ }; }; +&emac { + /* LEDs changed to active high on the plus */ + /delete-property/ allwinner,leds-active-low; +}; + &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts index c88518b3f538..f5f0f15a2088 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts @@ -52,6 +52,7 @@ compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -117,6 +118,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts index 828ae7a526d9..331ed683ac62 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts @@ -47,6 +47,10 @@ model = "Xunlong Orange Pi Plus / Plus 2"; compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; + aliases { + ethernet0 = &emac; + }; + reg_gmac_3v3: gmac-3v3 { compatible = "regulator-fixed"; regulator-name = "gmac-3v3"; @@ -74,6 +78,24 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + allwinner,leds-active-low; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_8bit_pins>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts index 97920b12a944..80026f3caafc 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts @@ -61,3 +61,19 @@ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ }; }; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 34fe2b8b3f33..4b599b5d26f6 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -403,6 +403,32 @@ clocks = <&osc24M>; }; + emac: ethernet@1c30000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c30000 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + }; + spi0: spi@01c68000 { compatible = "allwinner,sun8i-h3-spi"; reg = <0x01c68000 0x1000>; From patchwork Fri Sep 8 07:11:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 811360 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Oi6J8kbc"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xpTD31YGXz9sPk for ; Fri, 8 Sep 2017 17:17:23 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932393AbdIHHRM (ORCPT ); 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id l19sm684566wrl.47.2017.09.08.00.14.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Sep 2017 00:14:11 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v5 04/10] net: stmmac: sun8i: Restore the compatibles Date: Fri, 8 Sep 2017 09:11:50 +0200 Message-Id: <20170908071156.5115-5-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170908071156.5115-1-clabbe.montjoie@gmail.com> References: <20170908071156.5115-1-clabbe.montjoie@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch restore compatibles about dwmac-sun8i This reverts commit ad4540cc5aa3 ("net: stmmac: sun8i: Remove the compatibles") Signed-off-by: Corentin Labbe --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index 39c2122a4f26..fffd6d5fc907 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -979,6 +979,14 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) } static const struct of_device_id sun8i_dwmac_match[] = { + { .compatible = "allwinner,sun8i-h3-emac", + .data = &emac_variant_h3 }, + { .compatible = "allwinner,sun8i-v3s-emac", + .data = &emac_variant_v3s }, + { .compatible = "allwinner,sun8i-a83t-emac", + .data = &emac_variant_a83t }, + { .compatible = "allwinner,sun50i-a64-emac", + .data = &emac_variant_a64 }, { } }; MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); From patchwork Fri Sep 8 07:11:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 811356 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="cOT/WfUU"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xpTBq6xfgz9sBd for ; Fri, 8 Sep 2017 17:16:19 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756094AbdIHHQK (ORCPT ); Fri, 8 Sep 2017 03:16:10 -0400 Received: from mail-wr0-f194.google.com ([209.85.128.194]:32909 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755041AbdIHHOO (ORCPT ); Fri, 8 Sep 2017 03:14:14 -0400 Received: by mail-wr0-f194.google.com with SMTP id b9so832846wra.0; Fri, 08 Sep 2017 00:14:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=v3OUF9wjayWVPy9qPBPci63XPYFyt5bnNKMvxB0Ytbc=; b=cOT/WfUU5zhn5ZxhajtgrZgqc1oR23G84iaRnxbK+I4c8iqSmb4qLgQwn3NZtWkEWc 20li5fGk/t8lW+/1rgGYpPPLxo1W5n20MsbWW52wxIBACkzujHXngKedcrecGNENyK0h rTDtQtBAdWW8ANecMJKspLnxUnhHwJCi4oJVlO5wpWOZhAt8ZVh2Tz/maHmogMUUf5BL 2vy9H0r5Jvu+cj1aQNz5dVv/nX30u12Qn4OUUA4WZu6P3m8jfjk87foGkQLz3E73pIKi ajSyL9v5oHIhlosaEMufDtN4tB0xlVhDGFLDVARvul04HMidwsqyW4+zh5B2P9UzbOv8 kCwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=v3OUF9wjayWVPy9qPBPci63XPYFyt5bnNKMvxB0Ytbc=; b=J9MaZerEUKuq8X1w7uYytAgM8QV4WesLqBGXRCSWUd/YWmycTbfyUTkW1QsQ29twj0 zHHSJ0wRpLjjpjfQYmVNYAxLe/YBq3Bj9mc67artg9lmjwNUdG2Knbb0fajn+CSgQ3aP TFbreZMUTpTmxEFklo4FYH5cwNh7FxubK6ES1IEKLJ5K6SIkJfXYnJTB0KwzsP2GE5gH hJSioFbNhC4nk5nyJ8KSs5xAJa+rv08beYWKFCQJ/giKwC/3KPxlspHaZysTjc1WKBMh vOIbP6/mYD0oxuOjGiVIsa7X6AxWQl1Q06XqkNiLHrWjbgkOmGSu0ckVeQFaiBkBXrUe FQxQ== X-Gm-Message-State: AHPjjUhSKkAcDveoxBOTnR/c0M30L7DmWW79+HGHOMsNf7BN3myqLiKf 78Xh8s/UMFEOAQ== X-Google-Smtp-Source: ADKCNb66qebnX3Asp0WoXrDRKAuqySN185agnrZKo6A5JceON4kvT1JToULP6KGjqBgicwBYIyOEfg== X-Received: by 10.223.174.214 with SMTP id y80mr1257142wrc.192.1504854853236; Fri, 08 Sep 2017 00:14:13 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id l19sm684566wrl.47.2017.09.08.00.14.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Sep 2017 00:14:12 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v5 05/10] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY Date: Fri, 8 Sep 2017 09:11:51 +0200 Message-Id: <20170908071156.5115-6-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170908071156.5115-1-clabbe.montjoie@gmail.com> References: <20170908071156.5115-1-clabbe.montjoie@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch add documentation about the MDIO switch used on sun8i-h3-emac for integrated PHY. Signed-off-by: Corentin Labbe --- .../devicetree/bindings/net/dwmac-sun8i.txt | 127 +++++++++++++++++++-- 1 file changed, 120 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt index 725f3b187886..3fa0e54825ea 100644 --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt @@ -39,7 +39,7 @@ Optional properties for the following compatibles: - allwinner,leds-active-low: EPHY LEDs are active low Required child node of emac: -- mdio bus node: should be named mdio +- mdio bus node: should be labelled mdio Required properties of the mdio node: - #address-cells: shall be 1 @@ -48,14 +48,28 @@ Required properties of the mdio node: The device node referenced by "phy" or "phy-handle" should be a child node of the mdio node. See phy.txt for the generic PHY bindings. -Required properties of the phy node with the following compatibles: +The following compatibles require an mdio-mux node called "mdio-mux": + - "allwinner,sun8i-h3-emac" + - "allwinner,sun8i-v3s-emac": +Required properties for the mdio-mux node: + - compatible = "mdio-mux" + - one child mdio for the integrated mdio + - one child mdio for the external mdio if present (V3s have none) +Required properties for the mdio-mux children node: + - reg: 0 for internal MDIO bus, 1 for external MDIO bus + +The following compatibles require a PHY node representing the integrated +PHY, under the integrated MDIO bus node if an mdio-mux node is used: - "allwinner,sun8i-h3-emac", - "allwinner,sun8i-v3s-emac": + +Required properties of the integrated phy node: - clocks: a phandle to the reference clock for the EPHY - resets: a phandle to the reset control for the EPHY +- phy-is-integrated +- Should be a child of the integrated mdio -Example: - +Example with integrated PHY: emac: ethernet@1c0b000 { compatible = "allwinner,sun8i-h3-emac"; syscon = <&syscon>; @@ -72,13 +86,112 @@ emac: ethernet@1c0b000 { phy-handle = <&int_mii_phy>; phy-mode = "mii"; allwinner,leds-active-low; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + + mdio-mux { + compatible = "mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + int_mdio: mdio@1 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + phy-is-integrated + }; + }; + ext_mdio: mdio@0 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +Example with external PHY: +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + allwinner,leds-active-low; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + + mdio-mux { + compatible = "mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + int_mdio: mdio@1 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + phy-is-integrated + }; + }; + ext_mdio: mdio@0 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + ext_rgmii_phy: ethernet-phy@1 { + reg = <1>; + }; + }; + }; +}; + +Example with SoC without integrated PHY + +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-a83t-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + mdio: mdio { + compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; - int_mii_phy: ethernet-phy@1 { + ext_rgmii_phy: ethernet-phy@1 { reg = <1>; - clocks = <&ccu CLK_BUS_EPHY>; - resets = <&ccu RST_BUS_EPHY>; }; }; }; From patchwork Fri Sep 8 07:11:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 811355 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="J94f4xhD"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xpTBG3Gdkz9sBd for ; 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id l19sm684566wrl.47.2017.09.08.00.14.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Sep 2017 00:14:13 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v5 06/10] ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac Date: Fri, 8 Sep 2017 09:11:52 +0200 Message-Id: <20170908071156.5115-7-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170908071156.5115-1-clabbe.montjoie@gmail.com> References: <20170908071156.5115-1-clabbe.montjoie@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Since dwmac-sun8i could use either an integrated PHY or an external PHY (which could be at same MDIO address), we need to represent this selection by a MDIO switch. Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 4b599b5d26f6..e137377b312d 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -417,14 +417,34 @@ #size-cells = <0>; status = "disabled"; - mdio: mdio { + mdio0: mdio { #address-cells = <1>; #size-cells = <0>; - int_mii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; + compatible = "snps,dwmac-mdio"; + }; + + mdio-mux { + compatible = "mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + /* Only one MDIO is usable at the time */ + internal_mdio: mdio@1 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + phy-is-integrated; + }; + }; + mdio: mdio@0 { reg = <1>; - clocks = <&ccu CLK_BUS_EPHY>; - resets = <&ccu RST_BUS_EPHY>; + #address-cells = <1>; + #size-cells = <0>; }; }; }; From patchwork Fri Sep 8 07:11:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 811351 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="YqQHqKCV"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xpT9C1HsBz9s83 for ; Fri, 8 Sep 2017 17:14:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755137AbdIHHOT (ORCPT ); Fri, 8 Sep 2017 03:14:19 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:35946 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755106AbdIHHOR (ORCPT ); Fri, 8 Sep 2017 03:14:17 -0400 Received: by mail-wm0-f66.google.com with SMTP id p17so1126624wmd.3; Fri, 08 Sep 2017 00:14:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b54F7Z1QJr2x8DVpi9YzbUxdrfThtIfExAZvYfbvWkU=; b=YqQHqKCVGeC2VAb0OQtmUHVJ/rZsvraPkKv+UszYKQp6zxaobQ7qzpvQ3o46PnGVEn K9fUL4RFeCCPZidkHlrgiA9J53KB80n2tmvdIsSc/Q02FYsb53OgmFwWn9KQnDVhzUZz ifZ65mOQJ3Z7/7LgrLCiPMoo5QwUWa//zjOXHtBExSzxO6s9L9BL3aWBHO/VAaMJAR3r uJ+QQO+zqnjzEP7ZxaYWTHjXqg66sfNmcac3Rmz18QjkIOQsrxI1qDmIsMbJbwFXYdy6 ZKLU4X0nd9fvkTqpBGPL3dnehhw/Y94BN88g3rXs+2S4Fbd1BMsche5l7dqrQljtOIb6 Yctg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=b54F7Z1QJr2x8DVpi9YzbUxdrfThtIfExAZvYfbvWkU=; b=UVSGhWL7ik2KU4BAFamOJ4aYiaws+PDKdCUNAnQhPkZwnm621IF/ZHzh2HHTeQDdeM NCgB13nr65jLHMKrHzONvattug5nGoADuVcBJKAmhtCgkEy00I1W2PT4cAd/7cF2Q/sn 6XxXWUXYoAOuRWirqKysvs23NjGQ59cVh783hm7CL/s9mnrM0p1rpOAB/hZD1T+1AI6E i+IHy+mVuOotd120eUMUkbW2mR7KGSeOTjuiHT01al7YpZVgqHHEv3M8v+XfR6LzoC1k rO02/C9TkUiOJBatMNEZEWqYtKGyUm6vZEBBhOaPeg02iY/bvvfyGA+Z8/aeDBe/aa74 8xKg== X-Gm-Message-State: AHPjjUjD15b+2ge8LT+Po98KXhjMzPRNT/tPDYVRSHhvWQfPIVUSg66s G+jPuCsE+ZDKAA== X-Google-Smtp-Source: AOwi7QANOp4NsYRDKRD7PZ0PQYbFKHyKyPbz4F6+1Bs54dAykvIR9Z3cKViqmVF0TF4MxP6L/SuMuQ== X-Received: by 10.28.22.72 with SMTP id 69mr964265wmw.129.1504854855581; Fri, 08 Sep 2017 00:14:15 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id l19sm684566wrl.47.2017.09.08.00.14.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Sep 2017 00:14:15 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v5 07/10] arm64: dts: allwinner: add snps, dwmac-mdio compatible to emac/mdio Date: Fri, 8 Sep 2017 09:11:53 +0200 Message-Id: <20170908071156.5115-8-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170908071156.5115-1-clabbe.montjoie@gmail.com> References: <20170908071156.5115-1-clabbe.montjoie@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org stmmac bindings docs said that its mdio node must have compatible = "snps,dwmac-mdio"; Since dwmac-sun8i does not have any good reasons to not doing it, all their MDIO node must have it. Signed-off-by: Corentin Labbe --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 4dd9ffef0d80..5dceebd81f09 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -476,6 +476,7 @@ #size-cells = <0>; mdio: mdio { + compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; }; From patchwork Fri Sep 8 07:11:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 811354 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Gx4ouKee"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xpTB14hzjz9s83 for ; Fri, 8 Sep 2017 17:15:37 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755564AbdIHHPX (ORCPT ); Fri, 8 Sep 2017 03:15:23 -0400 Received: from mail-wr0-f193.google.com ([209.85.128.193]:34824 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755013AbdIHHOS (ORCPT ); Fri, 8 Sep 2017 03:14:18 -0400 Received: by mail-wr0-f193.google.com with SMTP id n64so827750wrb.2; Fri, 08 Sep 2017 00:14:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZDRqn6oM7YLvC7qyulEsdiG4u/Ek3wP9CmcxSAqe5YU=; b=Gx4ouKee8qpfDta/NQS+KDkCr3DdnR0+9lBqzs1mdm3BIcpndYniu6+jzWsAjimDK2 Eyvd9B3c6pYir9Bse7MePflJgU5ZgiSzyrO3jEOtmXBFewx9kHEU1Ac2fn5XLT5VYHca k6HIu0WEJT3Sf9RaWsk8m3cNIAV1yzhisNcE3IrXBfJ5hx9SLZPB3vRsZagM5kBvX3dX y5PQiEI9ezTL5qn2QXjFc6kBFZ7j0huzVGVo/Vrlg2YLTWf/hsAFRu2WgLNYZAFbLcn6 52l2LAZoDCRl1KoYdYY+QYXQ2visBB0CeFae8/+riZPF8g4Al4BazBfFvQZdGlcWCt5R 9xZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZDRqn6oM7YLvC7qyulEsdiG4u/Ek3wP9CmcxSAqe5YU=; b=rusEi4w0C+VQAHXHA3bkpm84RZu4VXj5Jg61Ozn3a0jn6frsZYXKdV8wr0JxS7W14v XcrgK54/oqWXYABf0vrYQFRvrya9ySGnrXexU7OKtaGoHYigfGCyNEExRWKlI8Kmb7LY plFQXAQjqPea4olnuhJ++bi8Op5ig7fOFRjWz10dKwixuM87qBI3RCq8Ho+szcs1InJM xMVBP1i9BuVbBmikdHyPR85mBpgfPAf9qALV90ufAOz/H+bKcX8HeArbCf3j/QP3fLYW e2ZAU5bAVkAZ8G1dXpFsHG763daoxrp/hOdWWBDpnDRQpktO1hK5G4hnd7gqc/ZKvD3t EEXA== X-Gm-Message-State: AHPjjUgVAsVxznQd3pnduLIGb8QyTGqkauv2XCDPHClqdDjTvc92FCqA BZyp0cNFv6A0/A== X-Google-Smtp-Source: ADKCNb4z3ywIzIXc17DTrY3eRhgS7GdHnwPgPow+b3AipK3o/03OM+48frHpnpawGXI+zweKmE+84Q== X-Received: by 10.223.130.77 with SMTP id 71mr1178456wrb.247.1504854856643; Fri, 08 Sep 2017 00:14:16 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id l19sm684566wrl.47.2017.09.08.00.14.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Sep 2017 00:14:16 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v5 08/10] net: stmmac: dwmac-sun8i: choose internal PHY via phy-is-integrated Date: Fri, 8 Sep 2017 09:11:54 +0200 Message-Id: <20170908071156.5115-9-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170908071156.5115-1-clabbe.montjoie@gmail.com> References: <20170908071156.5115-1-clabbe.montjoie@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The current way to find if the phy is internal is to compare DT phy-mode and emac_variant/internal_phy. But it will negate a possible future SoC where an external PHY use the same phy mode than the internal one. This patch adds a new way to find if the PHY is internal, via the phy-is-integrated property. Since the internal_phy variable does not need anymore to contain the xMII mode used by the internal PHY, it is still used for knowing the presence of an internal PHY, so it is modified to a boolean soc_has_internal_phy. Signed-off-by: Corentin Labbe Acked-by: Chen-Yu Tsai Reviewed-by: Florian Fainelli --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index fffd6d5fc907..672553b652bd 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -41,14 +41,14 @@ * This value is used for disabling properly EMAC * and used as a good starting value in case of the * boot process(uboot) leave some stuff. - * @internal_phy: Does the MAC embed an internal PHY + * @soc_has_internal_phy: Does the MAC embed an internal PHY * @support_mii: Does the MAC handle MII * @support_rmii: Does the MAC handle RMII * @support_rgmii: Does the MAC handle RGMII */ struct emac_variant { u32 default_syscon_value; - int internal_phy; + bool soc_has_internal_phy; bool support_mii; bool support_rmii; bool support_rgmii; @@ -75,7 +75,7 @@ struct sunxi_priv_data { static const struct emac_variant emac_variant_h3 = { .default_syscon_value = 0x58000, - .internal_phy = PHY_INTERFACE_MODE_MII, + .soc_has_internal_phy = true, .support_mii = true, .support_rmii = true, .support_rgmii = true @@ -83,20 +83,20 @@ static const struct emac_variant emac_variant_h3 = { static const struct emac_variant emac_variant_v3s = { .default_syscon_value = 0x38000, - .internal_phy = PHY_INTERFACE_MODE_MII, + .soc_has_internal_phy = true, .support_mii = true }; static const struct emac_variant emac_variant_a83t = { .default_syscon_value = 0, - .internal_phy = 0, + .soc_has_internal_phy = false, .support_mii = true, .support_rgmii = true }; static const struct emac_variant emac_variant_a64 = { .default_syscon_value = 0, - .internal_phy = 0, + .soc_has_internal_phy = false, .support_mii = true, .support_rmii = true, .support_rgmii = true @@ -648,7 +648,7 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) "Current syscon value is not the default %x (expect %x)\n", val, reg); - if (gmac->variant->internal_phy) { + if (gmac->variant->soc_has_internal_phy) { if (!gmac->use_internal_phy) { /* switch to external PHY interface */ reg &= ~H3_EPHY_SELECT; @@ -932,7 +932,7 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) } plat_dat->interface = of_get_phy_mode(dev->of_node); - if (plat_dat->interface == gmac->variant->internal_phy) { + if (of_property_read_bool(plat_dat->phy_node, "phy-is-integrated")) { dev_info(&pdev->dev, "Will use internal PHY\n"); gmac->use_internal_phy = true; gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0); From patchwork Fri Sep 8 07:11:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 811352 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; 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[90.118.159.96]) by smtp.googlemail.com with ESMTPSA id l19sm684566wrl.47.2017.09.08.00.14.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Sep 2017 00:14:17 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v5 09/10] net: stmmac: snps, dwmac-mdio MDIOs are automatically registered Date: Fri, 8 Sep 2017 09:11:55 +0200 Message-Id: <20170908071156.5115-10-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170908071156.5115-1-clabbe.montjoie@gmail.com> References: <20170908071156.5115-1-clabbe.montjoie@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org stmmac bindings docs said that its mdio node must have compatible = "snps,dwmac-mdio"; Since dwmac-sun8i does not have any good reasons to not doing it, all their MDIO node must have it. Since these compatible is automatically registered, dwmac-sun8i compatible does not need to be in need_mdio_ids. Signed-off-by: Corentin Labbe --- drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index a366b3747eeb..3de5501e34fe 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -311,10 +311,6 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat, bool mdio = true; static const struct of_device_id need_mdio_ids[] = { { .compatible = "snps,dwc-qos-ethernet-4.10" }, - { .compatible = "allwinner,sun8i-a83t-emac" }, - { .compatible = "allwinner,sun8i-h3-emac" }, - { .compatible = "allwinner,sun8i-v3s-emac" }, - { .compatible = "allwinner,sun50i-a64-emac" }, }; /* If phy-handle property is passed from DT, use it as the PHY */ From patchwork Fri Sep 8 07:11:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 811350 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="TbnzA1YB"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xpT8t3gbYz9s83 for ; Fri, 8 Sep 2017 17:14:38 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755215AbdIHHOY (ORCPT ); Fri, 8 Sep 2017 03:14:24 -0400 Received: from mail-wr0-f193.google.com ([209.85.128.193]:36546 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755141AbdIHHOU (ORCPT ); Fri, 8 Sep 2017 03:14:20 -0400 Received: by mail-wr0-f193.google.com with SMTP id g50so823137wra.3; Fri, 08 Sep 2017 00:14:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4u7/ZPCRQyQggk4YAw5FLvttfswqgq4S5B8xflhFWNU=; b=TbnzA1YBJmhfeNmFz3jMQU2FhBJyOWZhUt66zPXSG8BM4sjGnVFwZmnSTgh9gh+Ye3 2cFVK4mqRtthjgcIFylI9KvUIkiAQLun7xwVPULDKYLuoKd985FNB8bh1LfY7Qdahast Pma0hVkRFF8zWFuCU8xKT/9XBz9Zl5Jawwgm/K9Li2kf5qYLoJXmm9fjObNq1ipQ/K3M Sh9pVhK/jS0KEaDRUrodgMd6g6+xW3qyBw4Q+U1T7VH8EggzxUZaOK1LaC4P1OePMwz0 gWhKhRXBX2uoUhpMxlxTG2g0lvZLeV+SNLyxGWhoBpPcTUtrnNQmMC/nLrf+mE9uZEJ8 fyFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4u7/ZPCRQyQggk4YAw5FLvttfswqgq4S5B8xflhFWNU=; b=kutf909E5fdUS/RWfSNiyQpT54v/Wrf7lFTip9oAHfx+AJLEqvPW9obDgkGDpa7eym R8JlYHkjiDPrl/bWt27JfAVFcVw0ObJ57V/e1RAjy5G/rH4/5rC0v72TfLMN4V9DxkfT YTP3E7RaVJntbdmH7WxhiL6VT9Oe1pZvy4OShDssZXB71vzpsfNmRc+4HSF8NYHqMYwF YkBgKAu11bjF2GZFHtVud1xfnw+JhprEUHSqwP5BL9PANIKYCGOIxFA4UCqQfMm0WcUY 1cmEuGb0pPJ9niMSBVPu97A5p56QsCtKCUQpf+TluR7Nb5Mw0e50wvabyeya2Hq0TIsJ /Qtg== X-Gm-Message-State: AHPjjUirTJkb+YSGf3xLKnIi00JcaAem+EqVbqRQnemWtGROBlIWH8j0 eMymdfFuzkibng== X-Google-Smtp-Source: ADKCNb6yIr6cma8rD8L5+mR976UIqUrYDQ4gn7uIaQu71IyyPXROkjOyNty6xMo1/P9Vr8p59YD1wg== X-Received: by 10.223.164.150 with SMTP id g22mr1421730wrb.331.1504854858825; Fri, 08 Sep 2017 00:14:18 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id l19sm684566wrl.47.2017.09.08.00.14.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Sep 2017 00:14:18 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs Date: Fri, 8 Sep 2017 09:11:56 +0200 Message-Id: <20170908071156.5115-11-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170908071156.5115-1-clabbe.montjoie@gmail.com> References: <20170908071156.5115-1-clabbe.montjoie@gmail.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The Allwinner H3 SoC have two distinct MDIO bus, only one could be active at the same time. The selection of the active MDIO bus are done via some bits in the EMAC register of the system controller. This patch implement this MDIO switch via a custom MDIO-mux. Signed-off-by: Corentin Labbe --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 + drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 116 +++++++++++++++++++--- 2 files changed, 104 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index 97035766c291..e28c0d2c58e9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -159,6 +159,7 @@ config DWMAC_SUN8I tristate "Allwinner sun8i GMAC support" default ARCH_SUNXI depends on OF && (ARCH_SUNXI || COMPILE_TEST) + select MDIO_BUS_MUX ---help--- Support for Allwinner H3 A83T A64 EMAC ethernet controllers. diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index 672553b652bd..ddd5695886ac 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -71,6 +72,7 @@ struct sunxi_priv_data { const struct emac_variant *variant; struct regmap *regmap; bool use_internal_phy; + void *mux_handle; }; static const struct emac_variant emac_variant_h3 = { @@ -195,6 +197,9 @@ static const struct emac_variant emac_variant_a64 = { #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ +#define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT) +#define DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID 0 +#define DWMAC_sUN8I_MDIO_MUX_EXTERNAL_ID 1 /* H3/A64 specific bits */ #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ @@ -634,6 +639,76 @@ static int sun8i_dwmac_reset(struct stmmac_priv *priv) return 0; } +/* MDIO multiplexing switch function + * This function is called by the mdio-mux layer when it thinks the mdio bus + * multiplexer needs to switch. + * 'current_child' is the current value of the mux register + * 'desired_child' is the value of the 'reg' property of the target child MDIO + * node. + * The first time this function is called, current_child == -1. + * If current_child == desired_child, then the mux is already set to the + * correct bus. + * + * Note that we do not use reg/mask like mdio-mux-mmioreg because we need to + * know easily which bus is used (reset must be done only for desired bus). + */ +static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, + void *data) +{ + struct stmmac_priv *priv = data; + struct sunxi_priv_data *gmac = priv->plat->bsp_priv; + u32 reg, val; + int ret = 0; + bool need_reset = false; + + if (current_child ^ desired_child) { + regmap_read(gmac->regmap, SYSCON_EMAC_REG, ®); + switch (desired_child) { + case DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID: + dev_info(priv->device, "Switch mux to internal PHY"); + val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT; + if (gmac->use_internal_phy) + need_reset = true; + break; + case DWMAC_sUN8I_MDIO_MUX_EXTERNAL_ID: + dev_info(priv->device, "Switch mux to external PHY"); + val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN; + if (!gmac->use_internal_phy) + need_reset = true; + break; + default: + dev_err(priv->device, "Invalid child id %x\n", desired_child); + return -EINVAL; + } + regmap_write(gmac->regmap, SYSCON_EMAC_REG, val); + /* After changing syscon value, the MAC need reset or it will use + * the last value (and so the last PHY set). + * Reset is necessary only when we reach the needed MDIO, + * it timeout in other case. + */ + if (need_reset) + ret = sun8i_dwmac_reset(priv); + else + dev_dbg(priv->device, "skipped reset\n"); + } + return ret; +} + +static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv) +{ + int ret; + struct device_node *mdio_mux; + struct sunxi_priv_data *gmac = priv->plat->bsp_priv; + + mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); + if (!mdio_mux) + return -ENODEV; + + ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn, + &gmac->mux_handle, priv, priv->mii); + return ret; +} + static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) { struct sunxi_priv_data *gmac = priv->plat->bsp_priv; @@ -649,12 +724,7 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) val, reg); if (gmac->variant->soc_has_internal_phy) { - if (!gmac->use_internal_phy) { - /* switch to external PHY interface */ - reg &= ~H3_EPHY_SELECT; - } else { - reg |= H3_EPHY_SELECT; - reg &= ~H3_EPHY_SHUTDOWN; + if (gmac->use_internal_phy) { dev_dbg(priv->device, "Select internal_phy %x\n", reg); if (of_property_read_bool(priv->plat->phy_node, @@ -743,6 +813,8 @@ static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac) { u32 reg = gmac->variant->default_syscon_value; + if (gmac->variant->soc_has_internal_phy) + mdio_mux_uninit(gmac->mux_handle); regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg); } @@ -801,12 +873,6 @@ static int sun8i_power_phy(struct stmmac_priv *priv) if (ret) return ret; - /* After changing syscon value, the MAC need reset or it will use - * the last value (and so the last PHY set. - */ - ret = sun8i_dwmac_reset(priv); - if (ret) - return ret; return 0; } @@ -889,6 +955,8 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) struct sunxi_priv_data *gmac; struct device *dev = &pdev->dev; int ret; + struct stmmac_priv *priv; + struct net_device *ndev; ret = stmmac_get_platform_resources(pdev, &stmmac_res); if (ret) @@ -973,9 +1041,31 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); if (ret) - sun8i_dwmac_exit(pdev, plat_dat->bsp_priv); + goto dwmac_exit; + + ndev = dev_get_drvdata(&pdev->dev); + priv = netdev_priv(ndev); + /* The mux must be registered after parent MDIO + * so after stmmac_dvr_probe() + */ + if (gmac->variant->soc_has_internal_phy) { + ret = sun8i_dwmac_register_mdio_mux(priv); + if (ret) { + dev_err(&pdev->dev, "Failed to register mux\n"); + goto dwmac_mux; + } + } else { + ret = sun8i_dwmac_reset(priv); + if (ret) + goto dwmac_exit; + } return ret; +dwmac_mux: + sun8i_dwmac_unset_syscon(gmac); +dwmac_exit: + sun8i_dwmac_exit(pdev, plat_dat->bsp_priv); +return ret; } static const struct of_device_id sun8i_dwmac_match[] = {