From patchwork Fri Oct 30 09:22:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Coplan X-Patchwork-Id: 1390891 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gcc.gnu.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=byqluycY; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CMxfc2DfRz9sRk for ; Fri, 30 Oct 2020 20:22:29 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0FC8C3870913; Fri, 30 Oct 2020 09:22:26 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0FC8C3870913 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1604049746; bh=DidI2Zs141cMsn5EGx8WcdEcfSvTOTfAqFH6AEip+/8=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=byqluycYqsznwBA87qu2LTmC5W94TF+kP3I4TLEhILyImUJQ0qoIZpDrNhxQGZMbq 2ihRVrViZnRtIhWjIArxWq2Cs/jx9YsDO2WcbdkmP0DaUGlUegZSyULMP1Dw1q2Pkw emMlcIWIBcTQaa/jjgABM9koOh1L6Se9sToXFpTg= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR03-DB5-obe.outbound.protection.outlook.com (mail-eopbgr40087.outbound.protection.outlook.com [40.107.4.87]) by sourceware.org (Postfix) with ESMTPS id 7BE873857822 for ; Fri, 30 Oct 2020 09:22:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 7BE873857822 Received: from DB7PR05CA0051.eurprd05.prod.outlook.com (2603:10a6:10:2e::28) by AM9PR08MB5921.eurprd08.prod.outlook.com (2603:10a6:20b:2d4::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18; Fri, 30 Oct 2020 09:22:19 +0000 Received: from DB5EUR03FT050.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:2e:cafe::16) by DB7PR05CA0051.outlook.office365.com (2603:10a6:10:2e::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18 via Frontend Transport; Fri, 30 Oct 2020 09:22:19 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; gcc.gnu.org; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;gcc.gnu.org; dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DB5EUR03FT050.mail.protection.outlook.com (10.152.21.128) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3520.15 via Frontend Transport; Fri, 30 Oct 2020 09:22:19 +0000 Received: ("Tessian outbound 68da730eaaba:v64"); Fri, 30 Oct 2020 09:22:19 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: a7ca1eda98ffb267 X-CR-MTA-TID: 64aa7808 Received: from 886abfc20910.2 by 64aa7808-outbound-1.mta.getcheckrecipient.com id A9B8117F-DE74-4668-ADCA-29A121D7ACCE.1; Fri, 30 Oct 2020 09:22:12 +0000 Received: from EUR04-HE1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 886abfc20910.2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Fri, 30 Oct 2020 09:22:12 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=DqBi8SbTVZroSu+8mPCCSIQXeTS1GRoKVwOipf4DnqkNhDEdp2Q05tW699ttdcBeycwpUhE/EeWg6uzisYz9nyKZH2Bh8l9TFKnE/rw15tdTPITb+kBjWwJSEv88XIYYaublS/2IgP2SbAtlBj/mCWPeN8zjQYFOEvlDqYDCpduL+KKKaqR44groit3jyrTH91CAGMFLrLO6fOWcDBjpUD2+cgL0l+WzbltmM9cdB16Gtx+CLEqIAZJhxeHt+0RgOOdEyMS5uBIHCRAE/zYhRYqH9YKKo/hgwJ65yKwcaDh1wV2XJUV9scDSZVJRfsGGnfyUuCRjxBFCYYKVebr3Ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=DidI2Zs141cMsn5EGx8WcdEcfSvTOTfAqFH6AEip+/8=; b=Ugcw01XE8xtwwaexOEsWqYwKduN53VQNz/lbtXaeIWU1eVIg7x8ImM85GLFEx86Fr/NQECNGjI/ZLbDUi3H1zfopYiNhqLZFDNxBknpS5rmUNqevvAIGkecW3lrYI01uppTOn2tNmRTaDfZTJ6g3IOCdnz1h1QQ6pCpGGH3quJlzbSJ2B4dYC3QwWlGNVTa8LSwJ/FsDCMFoLd+iI+q+jJAy3jLcNgTu7sQSv4nwU0oQe6QB0BIvGS56vB13ZPrZhjStIhJTJ6q2MZGBqw9miEAEjBuU4eYjWp6G4R0xSOc3zD42bSSszbAUEUREU+/OLyJn1L1K0SQ25jTukaPuNg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none Authentication-Results-Original: gcc.gnu.org; dkim=none (message not signed) header.d=none;gcc.gnu.org; dmarc=none action=none header.from=arm.com; Received: from VI1PR08MB4029.eurprd08.prod.outlook.com (2603:10a6:803:ec::14) by VE1PR08MB4638.eurprd08.prod.outlook.com (2603:10a6:802:b1::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18; Fri, 30 Oct 2020 09:22:09 +0000 Received: from VI1PR08MB4029.eurprd08.prod.outlook.com ([fe80::9d3c:5e65:2ad4:a5c6]) by VI1PR08MB4029.eurprd08.prod.outlook.com ([fe80::9d3c:5e65:2ad4:a5c6%7]) with mapi id 15.20.3499.029; Fri, 30 Oct 2020 09:22:09 +0000 Date: Fri, 30 Oct 2020 09:22:07 +0000 To: gcc-patches@gcc.gnu.org Subject: [committed] aarch64: Fix PR96998 and restore code quality in combine Message-ID: <20201030092204.fd3vj5q4jggwunsw@arm.com> Content-Disposition: inline User-Agent: NeoMutt/20171215 X-Originating-IP: [217.140.106.52] X-ClientProxiedBy: LO2P265CA0077.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:8::17) To VI1PR08MB4029.eurprd08.prod.outlook.com (2603:10a6:803:ec::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from arm.com (217.140.106.52) by LO2P265CA0077.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:8::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18 via Frontend Transport; Fri, 30 Oct 2020 09:22:08 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 6337d351-f6cf-49bb-0913-08d87cb54d0b X-MS-TrafficTypeDiagnostic: VE1PR08MB4638:|AM9PR08MB5921: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:8882;OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: s8emymqK7UnmWp4gQeqIPJEMFSUiLNKIKIld/r1SzJKkuOl9PqvCp4H+UcNADV4pTMxcvn1jsC5TCoN/qfj4gEdmcJmkMTuQxk8Ytya6qG1OuCRTjtb37aag9LWoFfq6xsuJA/S2GmuBvyo76pbebf4zdsCa2uV/fS8PVT6RX5/zaME2NFsKwAQBM03OBfOak60ADGtHRsGcardSEeOHFMDTuitQLPsfohYyl8qm28o6okrYLJ+mypZU0U7TABe5KGwUqqEBzsjGuCybbyLXc0onE5UfS8zpPnrs//7oFAzzqWcRuu+d8AzS6gPtAs/57ZpnVw0CtTDSOUPS4Nw7lRcKSNz7DBQPEFK0r17BEgprJwqZ/v0hGI80DZozzMVDojNBbzibOgj0modIOPDaSzPTM1HoUgOdQ5ZTlD3nrN+pu2EcQhzUcY5vOj6WIY3oCFlwHKiAv5r2X6hq9TQzog== X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:VI1PR08MB4029.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(366004)(396003)(136003)(376002)(346002)(39860400002)(6916009)(83380400001)(5660300002)(66556008)(66946007)(235185007)(36756003)(66616009)(66476007)(966005)(2906002)(86362001)(186003)(2616005)(16526019)(478600001)(8676002)(1076003)(44832011)(26005)(956004)(44144004)(55016002)(8936002)(54906003)(7696005)(4326008)(8886007)(21480400003)(33964004)(316002)(52116002)(2700100001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: GdBbtWBI8eE5HGpUXcOoxBj2PhAPFo6ypCPs0ecPozXiWr1H/cRUuKfSqAvAswBuPfTuuFwQYORGNudRipwyk4sF1HCVplrf5pTGTc/aGFw7oUvt0KSHJlk1/G8fCcl2UfB2s5hoiIdwbmaBmuujWY5Zf2pbfcLJZHCCh2fbS6vxlIll16QCsbejFr2JlvzKsXhLKovRG1HluL+/+s/xdaWX8F2GIGY5VTS3a8XcJspw/3uchOo6+W93p2vEkGRiCjWK09+QwHFAcuvVjRwblBftxfmu0P+stZASWKzmiBgaHiBZwP8RifxwazerS0Nx20aXeRwEIdXYtdtcpVGgeQA1iWqverl5WzQtNHyQosa5nCizkbHF0eyb4QtL8a4E5erSKX2XepihPa4PU4biMyOgNqgnIXN0ONV+HqFaJHqT7A13KiHYONeIC1iKfEi3puvK7OqWKfRnEQOX1+2SQd4WpaaTqnqqIO904xGnSBbXBVbRi8awp3uSuoD2sVvEeqIKLkMzs+inZTALOzhZ+AGxHr3BiIVq2XMpjF3NQlK/lxmt3+Ld3firalPfZ3+TCUi6ghmpv+ACkRl8FZqiyCNbi7KENOE09I42uEvhObTo8wPw5DDSbUZsf9T8uzarHOrxv2yrfam6UuRmeZwGrg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB4638 Original-Authentication-Results: gcc.gnu.org; dkim=none (message not signed) header.d=none;gcc.gnu.org; dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DB5EUR03FT050.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: 30ad5933-df10-4154-8069-08d87cb546a7 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jUtfXIkoWxbF0PTdSQXozh90EWkz/qJHg4r2GKqK6Ji6PYu1lSLPUI7uPVbL54HTvTajEAZZgcz4tZ8eykEzM8lmD8J3HU9mRBgzoJqkO1tQ/BqWRjkdyCqZwWGKXyTrVCNYBJYxmb14YCSMeQeLyyPI+Pi4k2shJc1dVDvm55USiddllsPkglhKG937Ghf11XZoNSnN1fEroI8jk+TJmK0D4fxT16tf2JxT9njWbcpDF/rhONQU9N7f1OzzyPD0UaUqYs8V2RQQpxMePyVjjyJA3E8J9zsXwy6hu2ats92a2LPEPEZN2hjpijDUetQnQ9XgJHD1ChOInIT+041rQ7ObceRjwpkf1qyMbErTCasWiWWsrRSPB+Xbrh9U/CetPNtVM/9L3wpCaL2kzYVFatPVv+Za+21Uio74GxHS3/fdhYSmisTgFG7UUUIBNYOQ04//DVYF1gy3zS4WoXUXgPmsiDhT9TlX3wvcAUf7KgEYD/rFO6+sgkn4JEIiyyro X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(136003)(39850400004)(346002)(396003)(376002)(46966005)(316002)(44144004)(66616009)(8936002)(7696005)(33964004)(70206006)(44832011)(4326008)(356005)(55016002)(8676002)(36756003)(6916009)(5660300002)(86362001)(26005)(82310400003)(16526019)(186003)(235185007)(70586007)(83380400001)(54906003)(1076003)(8886007)(966005)(956004)(2616005)(2906002)(47076004)(107886003)(478600001)(82740400003)(336012)(21480400003)(81166007)(2700100001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2020 09:22:19.6338 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6337d351-f6cf-49bb-0913-08d87cb54d0b X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT050.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR08MB5921 X-Spam-Status: No, score=-14.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, MSGID_FROM_MTA_HEADER, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Alex Coplan via Gcc-patches From: Alex Coplan Reply-To: Alex Coplan Cc: Richard Earnshaw , Segher Boessenkool , Richard Sandiford Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" This patch fixes a bug in the AArch64 backend. Currently, we accept an odd sign_extract representation of addresses, but don't accept that same odd form of address as an LEA. This is the cause of PR96998. In the testcase given in the PR, combine produces: (insn 9 8 10 3 (set (mem:SI (plus:DI (sign_extract:DI (mult:DI (subreg:DI (reg/v:SI 92 [ g ]) 0) (const_int 4 [0x4])) (const_int 34 [0x22]) (const_int 0 [0])) (reg/f:DI 96)) [3 *i_5+0 S4 A32]) (asm_operands:SI ("") ("=Q") 0 [] [] [] test.c:11)) "test.c":11:5 -1 (expr_list:REG_DEAD (reg/v:SI 92 [ g ]) (nil))) Then LRA reloads the address and we ICE because we fail to recognize the sign_extract outside the mem: (insn 33 8 34 3 (set (reg:DI 100) (sign_extract:DI (ashift:DI (subreg:DI (reg/v:SI 92 [ g ]) 0) (const_int 2 [0x2])) (const_int 34 [0x22]) (const_int 0 [0]))) "test.c":11:5 -1 (nil)) The aarch64 changes here remove the support for this sign_extract representation of addresses, fixing PR96998. Now this by itself would regress code quality, so this change is paired with an improvement to combine which prevents an extract rtx from being emitted in this case: we now write the rtx above as a shift of an extend, which allows the combination to go ahead. Prior to this, combine.c:make_extraction() identified where we can emit an ashift of an extend in place of an extraction, but failed to make the corresponding canonicalization/simplification when presented with a mult by a power of two. Such a representation is canonical when representing a left-shifted address inside a mem. This change remedies this situation. For rtxes such as: (mult:DI (subreg:DI (reg:SI r) 0) (const_int 2^n)) where the bottom 32 + n bits are valid (the higher-order bits are undefined) and make_extraction() is being asked to sign_extract the lower (valid) bits, after the patch, we rewrite this as: (mult:DI (sign_extend:DI (reg:SI r)) (const_int 2^n)) instead of using a sign_extract. gcc/ChangeLog: PR target/96998 * combine.c (make_extraction): Also handle shifts written as (mult x 2^n), avoid creating an extract rtx for these. * config/aarch64/aarch64.c (aarch64_is_extend_from_extract): Delete. (aarch64_classify_index): Remove extract-based address handling. (aarch64_strip_extend): Likewise. (aarch64_rtx_arith_op_extract_p): Likewise, remove now-unused parameter. Update callers... (aarch64_rtx_costs): ... here. gcc/testsuite/ChangeLog: PR target/96998 * gcc.c-torture/compile/pr96998.c: New test. --- aarch64 change approved here: https://gcc.gnu.org/pipermail/gcc-patches/2020-October/556267.html combine change approved here: https://gcc.gnu.org/pipermail/gcc-patches/2020-October/557387.html Committing as one change to avoid regressing the trunk. Testing: * Bootstrapped and regtested on aarch64-linux-gnu, arm-linux-gnueabihf, and x86_64-linux-gnu: no regressions. Pushed to master. Thanks, Alex diff --git a/gcc/combine.c b/gcc/combine.c index 4782e1d9dcc..ed1ad45de83 100644 --- a/gcc/combine.c +++ b/gcc/combine.c @@ -7665,6 +7665,24 @@ make_extraction (machine_mode mode, rtx inner, HOST_WIDE_INT pos, if (new_rtx != 0) return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1)); } + else if (GET_CODE (inner) == MULT + && CONST_INT_P (XEXP (inner, 1)) + && pos_rtx == 0 && pos == 0) + { + /* We're extracting the least significant bits of an rtx + (mult X (const_int 2^C)), where LEN > C. Extract the + least significant (LEN - C) bits of X, giving an rtx + whose mode is MODE, then multiply it by 2^C. */ + const HOST_WIDE_INT shift_amt = exact_log2 (INTVAL (XEXP (inner, 1))); + if (IN_RANGE (shift_amt, 1, len - 1)) + { + new_rtx = make_extraction (mode, XEXP (inner, 0), + 0, 0, len - shift_amt, + unsignedp, in_dest, in_compare); + if (new_rtx) + return gen_rtx_MULT (mode, new_rtx, XEXP (inner, 1)); + } + } else if (GET_CODE (inner) == TRUNCATE /* If trying or potentionally trying to extract bits outside of is_mode, don't look through diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 35d6f2e2f01..db991e59cbe 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -2886,33 +2886,6 @@ aarch64_is_noplt_call_p (rtx sym) return false; } -/* Return true if the offsets to a zero/sign-extract operation - represent an expression that matches an extend operation. The - operands represent the parameters from - - (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */ -bool -aarch64_is_extend_from_extract (scalar_int_mode mode, rtx mult_imm, - rtx extract_imm) -{ - HOST_WIDE_INT mult_val, extract_val; - - if (! CONST_INT_P (mult_imm) || ! CONST_INT_P (extract_imm)) - return false; - - mult_val = INTVAL (mult_imm); - extract_val = INTVAL (extract_imm); - - if (extract_val > 8 - && extract_val < GET_MODE_BITSIZE (mode) - && exact_log2 (extract_val & ~7) > 0 - && (extract_val & 7) <= 4 - && mult_val == (1 << (extract_val & 7))) - return true; - - return false; -} - /* Emit an insn that's a simple single-set. Both the operands must be known to be valid. */ inline static rtx_insn * @@ -8936,22 +8909,6 @@ aarch64_classify_index (struct aarch64_address_info *info, rtx x, index = XEXP (XEXP (x, 0), 0); shift = INTVAL (XEXP (x, 1)); } - /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */ - else if ((GET_CODE (x) == SIGN_EXTRACT - || GET_CODE (x) == ZERO_EXTRACT) - && GET_MODE (x) == DImode - && GET_CODE (XEXP (x, 0)) == MULT - && GET_MODE (XEXP (XEXP (x, 0), 0)) == DImode - && CONST_INT_P (XEXP (XEXP (x, 0), 1))) - { - type = (GET_CODE (x) == SIGN_EXTRACT) - ? ADDRESS_REG_SXTW : ADDRESS_REG_UXTW; - index = XEXP (XEXP (x, 0), 0); - shift = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1))); - if (INTVAL (XEXP (x, 1)) != 32 + shift - || INTVAL (XEXP (x, 2)) != 0) - shift = -1; - } /* (and:DI (mult:DI (reg:DI) (const_int scale)) (const_int 0xffffffff< (GET_MODE (op), &mode)) return op; - /* Zero and sign extraction of a widened value. */ - if ((GET_CODE (op) == ZERO_EXTRACT || GET_CODE (op) == SIGN_EXTRACT) - && XEXP (op, 2) == const0_rtx - && GET_CODE (XEXP (op, 0)) == MULT - && aarch64_is_extend_from_extract (mode, XEXP (XEXP (op, 0), 1), - XEXP (op, 1))) - return XEXP (XEXP (op, 0), 0); - - /* It can also be represented (for zero-extend) as an AND with an - immediate. */ if (GET_CODE (op) == AND && GET_CODE (XEXP (op, 0)) == MULT && CONST_INT_P (XEXP (XEXP (op, 0), 1)) @@ -11704,35 +11635,15 @@ aarch64_branch_cost (bool speed_p, bool predictable_p) return branch_costs->unpredictable; } -/* Return true if the RTX X in mode MODE is a zero or sign extract +/* Return true if X is a zero or sign extract usable in an ADD or SUB (extended register) instruction. */ static bool -aarch64_rtx_arith_op_extract_p (rtx x, scalar_int_mode mode) -{ - /* Catch add with a sign extract. - This is add__multp2. */ - if (GET_CODE (x) == SIGN_EXTRACT - || GET_CODE (x) == ZERO_EXTRACT) - { - rtx op0 = XEXP (x, 0); - rtx op1 = XEXP (x, 1); - rtx op2 = XEXP (x, 2); - - if (GET_CODE (op0) == MULT - && CONST_INT_P (op1) - && op2 == const0_rtx - && CONST_INT_P (XEXP (op0, 1)) - && aarch64_is_extend_from_extract (mode, - XEXP (op0, 1), - op1)) - { - return true; - } - } +aarch64_rtx_arith_op_extract_p (rtx x) +{ /* The simple case , XD, XN, XM, [us]xt. No shift. */ - else if (GET_CODE (x) == SIGN_EXTEND - || GET_CODE (x) == ZERO_EXTEND) + if (GET_CODE (x) == SIGN_EXTEND + || GET_CODE (x) == ZERO_EXTEND) return REG_P (XEXP (x, 0)); return false; @@ -12419,8 +12330,8 @@ cost_minus: } /* Look for SUB (extended register). */ - if (is_a (mode, &int_mode) - && aarch64_rtx_arith_op_extract_p (op1, int_mode)) + if (is_a (mode) + && aarch64_rtx_arith_op_extract_p (op1)) { if (speed) *cost += extra_cost->alu.extend_arith; @@ -12499,8 +12410,8 @@ cost_plus: *cost += rtx_cost (op1, mode, PLUS, 1, speed); /* Look for ADD (extended register). */ - if (is_a (mode, &int_mode) - && aarch64_rtx_arith_op_extract_p (op0, int_mode)) + if (is_a (mode) + && aarch64_rtx_arith_op_extract_p (op0)) { if (speed) *cost += extra_cost->alu.extend_arith; diff --git a/gcc/testsuite/gcc.c-torture/compile/pr96998.c b/gcc/testsuite/gcc.c-torture/compile/pr96998.c new file mode 100644 index 00000000000..a75d5dcfe08 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/pr96998.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target arm*-*-* aarch64*-*-* } } */ + +int h(void); +struct c d; +struct c { + int e[1]; +}; + +void f(void) { + int g; + for (;; g = h()) { + int *i = &d.e[g]; + asm("" : "=Q"(*i)); + } +}