From patchwork Wed Oct 21 08:53:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Madhavan Srinivasan X-Patchwork-Id: 1385443 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CGPTQ1qr7z9sRk for ; Wed, 21 Oct 2020 19:55:22 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=mbkdqJek; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4CGPTQ0X93zDqfp for ; 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Wed, 21 Oct 2020 08:53:49 +0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 09L8rlss32899502 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 21 Oct 2020 08:53:47 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6C261A4055; Wed, 21 Oct 2020 08:53:47 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D0441A405E; Wed, 21 Oct 2020 08:53:45 +0000 (GMT) Received: from Madhavan.com (unknown [9.85.89.85]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 21 Oct 2020 08:53:45 +0000 (GMT) From: Madhavan Srinivasan To: mpe@ellerman.id.au Subject: [PATCH 1/5] powerpc/perf: Add new power pmu flag "PPMU_P10_DD1" for power10 DD1 Date: Wed, 21 Oct 2020 14:23:25 +0530 Message-Id: <20201021085329.384535-1-maddy@linux.ibm.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.737 definitions=2020-10-21_03:2020-10-20, 2020-10-21 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_spam_definite policy=outbound score=100 phishscore=0 mlxscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 adultscore=0 spamscore=0 bulkscore=0 mlxlogscore=485 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2010210065 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: atrajeev@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org, Madhavan Srinivasan Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Athira Rajeev Add a new power PMU flag "PPMU_P10_DD1" which can be used to conditionally add any code path for power10 DD1 processor version. Also modify power10 PMU driver code to set this flag only for DD1, based on the Processor Version Register (PVR) value. Signed-off-by: Athira Rajeev Signed-off-by: Madhavan Srinivasan --- arch/powerpc/include/asm/perf_event_server.h | 1 + arch/powerpc/perf/power10-pmu.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/powerpc/include/asm/perf_event_server.h index f6acabb6c9be..3b7baba01c92 100644 --- a/arch/powerpc/include/asm/perf_event_server.h +++ b/arch/powerpc/include/asm/perf_event_server.h @@ -82,6 +82,7 @@ struct power_pmu { #define PPMU_ARCH_207S 0x00000080 /* PMC is architecture v2.07S */ #define PPMU_NO_SIAR 0x00000100 /* Do not use SIAR */ #define PPMU_ARCH_31 0x00000200 /* Has MMCR3, SIER2 and SIER3 */ +#define PPMU_P10_DD1 0x00000400 /* Is power10 DD1 processor version */ /* * Values for flags to get_alternatives() diff --git a/arch/powerpc/perf/power10-pmu.c b/arch/powerpc/perf/power10-pmu.c index 9dbe8f9b89b4..a01e87f0b8d0 100644 --- a/arch/powerpc/perf/power10-pmu.c +++ b/arch/powerpc/perf/power10-pmu.c @@ -403,6 +403,7 @@ static struct power_pmu power10_pmu = { int init_power10_pmu(void) { + unsigned int pvr; int rc; /* Comes from cpu_specs[] */ @@ -410,6 +411,11 @@ int init_power10_pmu(void) strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power10")) return -ENODEV; + pvr = mfspr(SPRN_PVR); + /* Add the ppmu flag for power10 DD1 */ + if ((PVR_CFG(pvr) == 1)) + power10_pmu.flags |= PPMU_P10_DD1; + /* Set the PERF_REG_EXTENDED_MASK here */ PERF_REG_EXTENDED_MASK = PERF_REG_PMU_MASK_31; From patchwork Wed Oct 21 08:53:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Madhavan Srinivasan X-Patchwork-Id: 1385444 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CGPWH3JwBz9sRk for ; Wed, 21 Oct 2020 19:56:59 +1100 (AEDT) Authentication-Results: ozlabs.org; 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Wed, 21 Oct 2020 08:53:52 +0000 (GMT) Received: from Madhavan.com (unknown [9.85.89.85]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 21 Oct 2020 08:53:52 +0000 (GMT) From: Madhavan Srinivasan To: mpe@ellerman.id.au Subject: [PATCH v2 2/5] powerpc/perf: Drop the check for SIAR_VALID Date: Wed, 21 Oct 2020 14:23:26 +0530 Message-Id: <20201021085329.384535-2-maddy@linux.ibm.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201021085329.384535-1-maddy@linux.ibm.com> References: <20201021085329.384535-1-maddy@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.737 definitions=2020-10-21_03:2020-10-20, 2020-10-21 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_spam_definite policy=outbound score=100 mlxscore=0 bulkscore=0 spamscore=0 impostorscore=0 mlxlogscore=533 priorityscore=1501 malwarescore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 adultscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2010210065 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: atrajeev@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org, Madhavan Srinivasan Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Athira Rajeev In power10 DD1, there is an issue that causes the SIAR_VALID bit of Sampled Instruction Event Register(SIER) not to be set. But the SIAR_VALID bit is used for fetching the instruction address from Sampled Instruction Address Register(SIAR), and marked events are sampled only if the SIAR_VALID bit is set. So drop the check for SIAR_VALID and return true always incase of power10 DD1. Signed-off-by: Athira Rajeev Signed-off-by: Madhavan Srinivasan --- Changelog v1: - Drop the check for SIER[CMPL] and retur true instead - Made changes to commit message arch/powerpc/perf/core-book3s.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index 08643cba1494..3b62dbb94796 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -350,7 +350,14 @@ static inline int siar_valid(struct pt_regs *regs) int marked = mmcra & MMCRA_SAMPLE_ENABLE; if (marked) { - if (ppmu->flags & PPMU_HAS_SIER) + /* + * SIER[SIAR_VALID] is not set for some + * marked events on power10 DD1, so drop + * the check for SIER[SIAR_VALID] and return true. + */ + if (ppmu->flags & PPMU_P10_DD1) + return 0x1; + else if (ppmu->flags & PPMU_HAS_SIER) return regs->dar & SIER_SIAR_VALID; if (ppmu->flags & PPMU_SIAR_VALID) From patchwork Wed Oct 21 08:53:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Madhavan Srinivasan X-Patchwork-Id: 1385451 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CGPdW59m6z9sRk for ; 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Wed, 21 Oct 2020 08:53:56 +0000 (GMT) Received: from Madhavan.com (unknown [9.85.89.85]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 21 Oct 2020 08:53:56 +0000 (GMT) From: Madhavan Srinivasan To: mpe@ellerman.id.au Subject: [PATCH 3/5] powerpc/perf: Use the address from SIAR register to set cpumode flags Date: Wed, 21 Oct 2020 14:23:27 +0530 Message-Id: <20201021085329.384535-3-maddy@linux.ibm.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201021085329.384535-1-maddy@linux.ibm.com> References: <20201021085329.384535-1-maddy@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.737 definitions=2020-10-21_03:2020-10-20, 2020-10-21 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_spam_definite policy=outbound score=100 mlxscore=0 mlxlogscore=468 spamscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 adultscore=0 suspectscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2010210065 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: atrajeev@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org, Madhavan Srinivasan Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Athira Rajeev While setting the processor mode for any sample, `perf_get_misc_flags` expects the privilege level to differentiate the userspace and kernel address. On power10 DD1, there is an issue that causes [MSR_HV MSR_PR] bits of Sampled Instruction Event Register (SIER) not to be set for marked events. Hence add a check to use the address in Sampled Instruction Address Register (SIAR) to identify the privilege level. Signed-off-by: Athira Rajeev Signed-off-by: Madhavan Srinivasan --- arch/powerpc/perf/core-book3s.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index 3b62dbb94796..6be0349e01ad 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -250,10 +250,24 @@ static inline u32 perf_flags_from_msr(struct pt_regs *regs) static inline u32 perf_get_misc_flags(struct pt_regs *regs) { bool use_siar = regs_use_siar(regs); + unsigned long mmcra = regs->dsisr; + int marked = mmcra & MMCRA_SAMPLE_ENABLE; if (!use_siar) return perf_flags_from_msr(regs); + /* + * Check the address in SIAR to identify the + * privilege levels since the SIER[MSR_HV, MSR_PR] + * bits are not set for marked events in power10 + * DD1. + */ + if (marked && (ppmu->flags & PPMU_P10_DD1)) { + if (is_kernel_addr(mfspr(SPRN_SIAR))) + return PERF_RECORD_MISC_KERNEL; + return PERF_RECORD_MISC_USER; + } + /* * If we don't have flags in MMCRA, rather than using * the MSR, we intuit the flags from the address in From patchwork Wed Oct 21 08:53:28 2020 Content-Type: text/plain; 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Wed, 21 Oct 2020 08:54:08 GMT Received: from b06cxnps4076.portsmouth.uk.ibm.com (d06relay13.portsmouth.uk.ibm.com [9.149.109.198]) by ppma03ams.nl.ibm.com with ESMTP id 348d5qu95h-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 21 Oct 2020 08:54:08 +0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 09L8s6Dr29360564 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 21 Oct 2020 08:54:06 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4D52CA4053; Wed, 21 Oct 2020 08:54:06 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A8780A4057; Wed, 21 Oct 2020 08:54:04 +0000 (GMT) Received: from Madhavan.com (unknown [9.85.89.85]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 21 Oct 2020 08:54:04 +0000 (GMT) From: Madhavan Srinivasan To: mpe@ellerman.id.au Subject: [PATCH 4/5] powerpc/perf: Exclude kernel samples while counting events in user space. Date: Wed, 21 Oct 2020 14:23:28 +0530 Message-Id: <20201021085329.384535-4-maddy@linux.ibm.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201021085329.384535-1-maddy@linux.ibm.com> References: <20201021085329.384535-1-maddy@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.737 definitions=2020-10-21_03:2020-10-20, 2020-10-21 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_spam_definite policy=outbound score=100 bulkscore=0 impostorscore=0 mlxscore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 spamscore=0 malwarescore=0 phishscore=0 clxscore=1015 mlxlogscore=681 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2010210065 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: atrajeev@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org, Madhavan Srinivasan Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Athira Rajeev By setting exclude_kernel for user space profiling, we set the freeze bits in Monitor Mode Control Register. Due to hardware limitation, sometimes, Sampled Instruction Address register (SIAR) captures kernel address even when counter freeze bits are set in Monitor Mode Control Register (MMCR2). Patch adds a check to drop these samples at such conditions. Signed-off-by: Athira Rajeev Signed-off-by: Madhavan Srinivasan --- arch/powerpc/perf/core-book3s.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index 6be0349e01ad..e675c7c8ce0e 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -2142,6 +2142,18 @@ static void record_and_restart(struct perf_event *event, unsigned long val, local64_set(&event->hw.period_left, left); perf_event_update_userpage(event); + /* + * Setting exclude_kernel will only freeze the + * Performance Monitor counters and we may have + * kernel address captured in SIAR. Hence drop + * the kernel sample captured during user space + * profiling. Setting `record` to zero will also + * make sure event throlling is handled. + */ + if (event->attr.exclude_kernel && record) + if (is_kernel_addr(mfspr(SPRN_SIAR))) + record = 0; + /* * Finally record data if requested. */ From patchwork Wed Oct 21 08:53:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Madhavan Srinivasan X-Patchwork-Id: 1385452 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CGPg461XJz9sRk for ; Wed, 21 Oct 2020 20:03:44 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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Wed, 21 Oct 2020 08:54:07 +0000 (GMT) Received: from Madhavan.com (unknown [9.85.89.85]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 21 Oct 2020 08:54:07 +0000 (GMT) From: Madhavan Srinivasan To: mpe@ellerman.id.au Subject: [PATCH 5/5] powerpc/perf: use regs->nip when siar is zero Date: Wed, 21 Oct 2020 14:23:29 +0530 Message-Id: <20201021085329.384535-5-maddy@linux.ibm.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201021085329.384535-1-maddy@linux.ibm.com> References: <20201021085329.384535-1-maddy@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.737 definitions=2020-10-21_03:2020-10-20, 2020-10-21 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_spam_definite policy=outbound score=100 adultscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 suspectscore=0 phishscore=0 mlxlogscore=456 spamscore=0 lowpriorityscore=0 malwarescore=0 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2010210069 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: atrajeev@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org, Madhavan Srinivasan Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" In power10 DD1, there is an issue where the Sampled Instruction Address Register (SIAR) not latching to the sampled address during random sampling. This results in value of 0s in the SIAR. Patch adds a check to use regs->nip when SIAR is zero. Signed-off-by: Madhavan Srinivasan --- arch/powerpc/perf/core-book3s.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index e675c7c8ce0e..63de77eb0ac0 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -263,9 +263,16 @@ static inline u32 perf_get_misc_flags(struct pt_regs *regs) * DD1. */ if (marked && (ppmu->flags & PPMU_P10_DD1)) { - if (is_kernel_addr(mfspr(SPRN_SIAR))) - return PERF_RECORD_MISC_KERNEL; - return PERF_RECORD_MISC_USER; + unsigned long siar = mfspr(SPRN_SIAR); + if (siar) { + if (is_kernel_addr(siar)) + return PERF_RECORD_MISC_KERNEL; + return PERF_RECORD_MISC_USER; + } else { + if (is_kernel_addr(regs->nip)) + return PERF_RECORD_MISC_KERNEL; + return PERF_RECORD_MISC_USER; + } } /* @@ -2211,8 +2218,14 @@ unsigned long perf_misc_flags(struct pt_regs *regs) unsigned long perf_instruction_pointer(struct pt_regs *regs) { bool use_siar = regs_use_siar(regs); + unsigned long siar = mfspr(SPRN_SIAR); - if (use_siar && siar_valid(regs)) + if (ppmu->flags & PPMU_P10_DD1) { + if (siar) + return siar; + else + return regs->nip; + } else if (use_siar && siar_valid(regs)) return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); else if (use_siar) return 0; // no valid instruction pointer