From patchwork Mon Oct 19 14:10:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 1384347 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=0x0f.com header.i=@0x0f.com header.a=rsa-sha256 header.s=google header.b=HpOqAHzY; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CFJZD3KwCz9sWL for ; Tue, 20 Oct 2020 01:10:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729178AbgJSOKV (ORCPT ); Mon, 19 Oct 2020 10:10:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729155AbgJSOKU (ORCPT ); Mon, 19 Oct 2020 10:10:20 -0400 Received: from mail-pg1-x541.google.com (mail-pg1-x541.google.com [IPv6:2607:f8b0:4864:20::541]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D9C1C0613D1 for ; Mon, 19 Oct 2020 07:10:19 -0700 (PDT) Received: by mail-pg1-x541.google.com with SMTP id l18so44676pgg.0 for ; Mon, 19 Oct 2020 07:10:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sDf2wpUuzblvqUz0TuYPHYF7CNvy5nJj5wlwfBiA9Cc=; b=HpOqAHzYkbFF5EvXP78Au0CjG9EmpOZbfd4X/1c/HTraPCSeMIHRSQcWo05jZ9CqqS j8JLSTcuYn9AetcrcKp7ZEHx/FKxpSdNCTR+1Ac0JHwdLTl0RkGInpzLXbHuqmZThNel EpONuf9v61dahukEdqkmWKeUsKqQcnUQH4M0U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sDf2wpUuzblvqUz0TuYPHYF7CNvy5nJj5wlwfBiA9Cc=; b=jBsQgcRxmoF4GLOtPVztGOWm3jOIrvasyxogBrciJNpg+UTkbbgYwsPDnhJMIsJftA +SnMJ7kyAJI0/0iFKbO78vX7IjQKAohhpda+14M9FJaYOfWxQtZAA52iG1mZRac5ke4P 2/ZNTKYpjUfoGyZ9gCoEv6u0vw1YLdbRadB0Ndp8+jkQyElGb5xq9MXpcbmrbAsvci4E valL19xzuiBoHi+MDsl6kjmB6BoX+QZGtK1yGrEorHWNcxZYVbKQA5HOba/8RuHdZTHA wHp//YRJXNZyTr20GhtncD/rrbHqFw4UXZzG5+xpqmKJ5Ew7FfdOAfoRYezobVFRX8ET IUCw== X-Gm-Message-State: AOAM532itCNDj2CG8a4J8p+ksFVKFH09qa8S9Y4gN3xo7PnEKYvJeVXO +esmfgNeHJtRfNh5b2WMj4XCB040A0C7cg== X-Google-Smtp-Source: ABdhPJzEdWMHwmzuKcel1JcctN9VzFL0wzme9sHn8luNQVG+SQYgKgKwtwMkcc+NBv2dyYE336znmg== X-Received: by 2002:a63:1e65:: with SMTP id p37mr14684476pgm.131.1603116618537; Mon, 19 Oct 2020 07:10:18 -0700 (PDT) Received: from shiro.work (p1268123-ipngn200803sizuokaden.shizuoka.ocn.ne.jp. [118.13.124.123]) by smtp.googlemail.com with ESMTPSA id 131sm78999pfy.5.2020.10.19.07.10.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2020 07:10:17 -0700 (PDT) From: Daniel Palmer To: linux-gpio@vger.kernel.org Cc: devicetree@vger.kernel.org, arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linus.walleij@linaro.org, Daniel Palmer Subject: [PATCH v2 1/5] dt-bindings: gpio: Add a binding header for the MSC313 GPIO driver Date: Mon, 19 Oct 2020 23:10:04 +0900 Message-Id: <20201019141008.871177-2-daniel@0x0f.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201019141008.871177-1-daniel@0x0f.com> References: <20201019141008.871177-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Header adds defines for the gpio number of each pin from the driver view. The gpio block seems to support 128 lines but what line is mapped to a physical pin depends on the chip. The driver itself uses the index of a pin's offset in an array of the possible offsets for a chip as the gpio number. The defines remove the need to work out that index to consume a pin in the device tree. Signed-off-by: Daniel Palmer --- MAINTAINERS | 1 + include/dt-bindings/gpio/msc313-gpio.h | 95 ++++++++++++++++++++++++++ 2 files changed, 96 insertions(+) create mode 100644 include/dt-bindings/gpio/msc313-gpio.h diff --git a/MAINTAINERS b/MAINTAINERS index 3f345f36c22c..a188fae8c04e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2132,6 +2132,7 @@ W: http://linux-chenxing.org/ F: Documentation/devicetree/bindings/arm/mstar/* F: arch/arm/boot/dts/mstar-* F: arch/arm/mach-mstar/ +F: include/dt-bindings/gpio/msc313-gpio.h ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT M: Michael Petchkovsky diff --git a/include/dt-bindings/gpio/msc313-gpio.h b/include/dt-bindings/gpio/msc313-gpio.h new file mode 100644 index 000000000000..9b8cd6ffb7c4 --- /dev/null +++ b/include/dt-bindings/gpio/msc313-gpio.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * GPIO definitions for MStar/SigmaStar MSC313 and later SoCs + * + * Copyright (C) 2020 Daniel Palmer + */ + +#ifndef _DT_BINDINGS_MSC313_GPIO_H +#define _DT_BINDINGS_MSC313_GPIO_H + +/* pin names for fuart, same for all SoCs so far */ +#define MSC313_PINNAME_FUART_RX "fuart_rx" +#define MSC313_PINNAME_FUART_TX "fuart_tx" +#define MSC313_PINNAME_FUART_CTS "fuart_cts" +#define MSC313_PINNAME_FUART_RTS "fuart_rts" + +/* pin names for sr, mercury5 is different */ +#define MSC313_PINNAME_SR_IO2 "sr_io2" +#define MSC313_PINNAME_SR_IO3 "sr_io3" +#define MSC313_PINNAME_SR_IO4 "sr_io4" +#define MSC313_PINNAME_SR_IO5 "sr_io5" +#define MSC313_PINNAME_SR_IO6 "sr_io6" +#define MSC313_PINNAME_SR_IO7 "sr_io7" +#define MSC313_PINNAME_SR_IO8 "sr_io8" +#define MSC313_PINNAME_SR_IO9 "sr_io9" +#define MSC313_PINNAME_SR_IO10 "sr_io10" +#define MSC313_PINNAME_SR_IO11 "sr_io11" +#define MSC313_PINNAME_SR_IO12 "sr_io12" +#define MSC313_PINNAME_SR_IO13 "sr_io13" +#define MSC313_PINNAME_SR_IO14 "sr_io14" +#define MSC313_PINNAME_SR_IO15 "sr_io15" +#define MSC313_PINNAME_SR_IO16 "sr_io16" +#define MSC313_PINNAME_SR_IO17 "sr_io17" + +/* pin names for sd, same for all SoCs so far */ +#define MSC313_PINNAME_SD_CLK "sd_clk" +#define MSC313_PINNAME_SD_CMD "sd_cmd" +#define MSC313_PINNAME_SD_D0 "sd_d0" +#define MSC313_PINNAME_SD_D1 "sd_d1" +#define MSC313_PINNAME_SD_D2 "sd_d2" +#define MSC313_PINNAME_SD_D3 "sd_d3" + +/* pin names for i2c1, same for all SoCs so for */ +#define MSC313_PINNAME_I2C1_SCL "i2c1_scl" +#define MSC313_PINNAME_I2C1_SCA "i2c1_sda" + +/* pin names for spi0, same for all SoCs so far */ +#define MSC313_PINNAME_SPI0_CZ "spi0_cz" +#define MSC313_PINNAME_SPI0_CK "spi0_ck" +#define MSC313_PINNAME_SPI0_DI "spi0_di" +#define MSC313_PINNAME_SPI0_DO "spi0_do" + +#define MSC313_GPIO_FUART 0 +#define MSC313_GPIO_FUART_RX (MSC313_GPIO_FUART + 0) +#define MSC313_GPIO_FUART_TX (MSC313_GPIO_FUART + 1) +#define MSC313_GPIO_FUART_CTS (MSC313_GPIO_FUART + 2) +#define MSC313_GPIO_FUART_RTS (MSC313_GPIO_FUART + 3) + +#define MSC313_GPIO_SR (MSC313_GPIO_FUART_RTS + 1) +#define MSC313_GPIO_SR_IO2 (MSC313_GPIO_SR + 0) +#define MSC313_GPIO_SR_IO3 (MSC313_GPIO_SR + 1) +#define MSC313_GPIO_SR_IO4 (MSC313_GPIO_SR + 2) +#define MSC313_GPIO_SR_IO5 (MSC313_GPIO_SR + 3) +#define MSC313_GPIO_SR_IO6 (MSC313_GPIO_SR + 4) +#define MSC313_GPIO_SR_IO7 (MSC313_GPIO_SR + 5) +#define MSC313_GPIO_SR_IO8 (MSC313_GPIO_SR + 6) +#define MSC313_GPIO_SR_IO9 (MSC313_GPIO_SR + 7) +#define MSC313_GPIO_SR_IO10 (MSC313_GPIO_SR + 8) +#define MSC313_GPIO_SR_IO11 (MSC313_GPIO_SR + 9) +#define MSC313_GPIO_SR_IO12 (MSC313_GPIO_SR + 10) +#define MSC313_GPIO_SR_IO13 (MSC313_GPIO_SR + 11) +#define MSC313_GPIO_SR_IO14 (MSC313_GPIO_SR + 12) +#define MSC313_GPIO_SR_IO15 (MSC313_GPIO_SR + 13) +#define MSC313_GPIO_SR_IO16 (MSC313_GPIO_SR + 14) +#define MSC313_GPIO_SR_IO17 (MSC313_GPIO_SR + 15) + +#define MSC313_GPIO_SD (MSC313_GPIO_SR_IO17 + 1) +#define MSC313_GPIO_SD_CLK (MSC313_GPIO_SD + 0) +#define MSC313_GPIO_SD_CMD (MSC313_GPIO_SD + 1) +#define MSC313_GPIO_SD_D0 (MSC313_GPIO_SD + 2) +#define MSC313_GPIO_SD_D1 (MSC313_GPIO_SD + 3) +#define MSC313_GPIO_SD_D2 (MSC313_GPIO_SD + 4) +#define MSC313_GPIO_SD_D3 (MSC313_GPIO_SD + 5) + +#define MSC313_GPIO_I2C1 (MSC313_GPIO_SD_D3 + 1) +#define MSC313_GPIO_I2C1_SCL (MSC313_GPIO_I2C1 + 0) +#define MSC313_GPIO_I2C1_SDA (MSC313_GPIO_I2C1 + 1) + +#define MSC313_GPIO_SPI0 (MSC313_GPIO_I2C1_SDA + 1) +#define MSC313_GPIO_SPI0_CZ (MSC313_GPIO_SPI0 + 0) +#define MSC313_GPIO_SPI0_CK (MSC313_GPIO_SPI0 + 1) +#define MSC313_GPIO_SPI0_DI (MSC313_GPIO_SPI0 + 2) +#define MSC313_GPIO_SPI0_DO (MSC313_GPIO_SPI0 + 3) + +#endif /* _DT_BINDINGS_MSC313_GPIO_H */ From patchwork Mon Oct 19 14:10:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 1384342 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=0x0f.com header.i=@0x0f.com header.a=rsa-sha256 header.s=google header.b=T9yXXAo2; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CFJYr5Q9Vz9sW0 for ; Tue, 20 Oct 2020 01:10:24 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729182AbgJSOKX (ORCPT ); Mon, 19 Oct 2020 10:10:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729295AbgJSOKX (ORCPT ); Mon, 19 Oct 2020 10:10:23 -0400 Received: from mail-pj1-x1042.google.com (mail-pj1-x1042.google.com [IPv6:2607:f8b0:4864:20::1042]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EEF1DC0613D0 for ; Mon, 19 Oct 2020 07:10:21 -0700 (PDT) Received: by mail-pj1-x1042.google.com with SMTP id az3so5384288pjb.4 for ; Mon, 19 Oct 2020 07:10:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=W7YA8x/YJ4hzstR6fHI6wY0DfW4AJFQtQe/riUUB+yw=; b=T9yXXAo2lls4cGBq9D+RVumXVsoXW+ItpctPehVNWYA68UIJ+EU0DTyZ26m7NGtrxU dBfTHx0jxt18mlTxv8ecE1P+QH3jzG8CDOUO3Xow1U17SLr0ja2nSQz1AuYb481cDk94 4RteL8SZnhOkVwWbjttU/0cK8GyDQMivD/DpU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W7YA8x/YJ4hzstR6fHI6wY0DfW4AJFQtQe/riUUB+yw=; b=N2O0dC/8pycA5onMoU3NrtGAG9XouyHAnTA5c38mr1mAnq8nHrZk79GzV3rIEMqMY/ 4OnGW6Ccm8DXLWdKOm2ole5pfwbbAcsgYr1U2Yn3Q1+IpnJm/Q2djs7NpAzZ+cFJ/TjP F9KrdcaShNsoHXC15y4IxYwCZvdslnqVSkgvWITcuk4msFG/PMlZPk72Rs2qeCVvWV4l HFFLd6cF4QeM9plsEXcHYq8L2323cyIkd5UJRH7n9t/SBPf87FLlWLiiD8ylzp9DckcR +ypiCKANvV71F7xG7LMSVqWl80dWuO7m2z/Pl9gsWS2wRPJ9X9vJrEOw8DfzpxLkw1tj yd4A== X-Gm-Message-State: AOAM530GMRJ3buvnzo35Ps3xqUwKcxlPja7RMEUMlndnmzc/Tlmbi8Ve 2zTM/rkwTjXq59/GzaLcY7sCJceslz+EDg== X-Google-Smtp-Source: ABdhPJy7b/9ZGZ6Y4S/BLeEOCApn/XzXT6jUA59yxj+eeHb2wmqtJDbFERQXT8y/nyT0EC0uxO8Qlw== X-Received: by 2002:a17:90a:5889:: with SMTP id j9mr17886422pji.109.1603116620985; Mon, 19 Oct 2020 07:10:20 -0700 (PDT) Received: from shiro.work (p1268123-ipngn200803sizuokaden.shizuoka.ocn.ne.jp. [118.13.124.123]) by smtp.googlemail.com with ESMTPSA id 131sm78999pfy.5.2020.10.19.07.10.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2020 07:10:20 -0700 (PDT) From: Daniel Palmer To: linux-gpio@vger.kernel.org Cc: devicetree@vger.kernel.org, arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linus.walleij@linaro.org, Daniel Palmer Subject: [PATCH v2 2/5] dt-bindings: gpio: Binding for MStar MSC313 GPIO controller Date: Mon, 19 Oct 2020 23:10:05 +0900 Message-Id: <20201019141008.871177-3-daniel@0x0f.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201019141008.871177-1-daniel@0x0f.com> References: <20201019141008.871177-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add a binding description for the MStar/SigmaStar GPIO controller found in the MSC313 and later ARMv7 SoCs. Signed-off-by: Daniel Palmer --- .../bindings/gpio/mstar,msc313-gpio.yaml | 61 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml diff --git a/Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml b/Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml new file mode 100644 index 000000000000..8c69153ac27e --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/mstar,msc313-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MStar/SigmaStar GPIO controller + +maintainers: + - Daniel Palmer + +properties: + $nodename: + pattern: "^gpio@[0-9a-f]+$" + + compatible: + const: mstar,msc313-gpio + + reg: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-ranges: true + + gpio-ranges-group-names: + $ref: /schemas/types.yaml#/definitions/string-array + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + +examples: + - | + #include + + gpio: gpio@207800 { + compatible = "mstar,msc313e-gpio"; + #gpio-cells = <2>; + reg = <0x207800 0x200>; + gpio-controller; + gpio-ranges = <&pinctrl 0 36 22>, + <&pinctrl 22 63 4>, + <&pinctrl 26 68 6>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&intc_fiq>; + status = "okay"; + }; diff --git a/MAINTAINERS b/MAINTAINERS index a188fae8c04e..102aedca81dc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2130,6 +2130,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained W: http://linux-chenxing.org/ F: Documentation/devicetree/bindings/arm/mstar/* +F: Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml F: arch/arm/boot/dts/mstar-* F: arch/arm/mach-mstar/ F: include/dt-bindings/gpio/msc313-gpio.h From patchwork Mon Oct 19 14:10:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 1384344 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=0x0f.com header.i=@0x0f.com header.a=rsa-sha256 header.s=google header.b=r8kovHa3; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CFJYx0ll0z9sW9 for ; Tue, 20 Oct 2020 01:10:29 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729372AbgJSOK0 (ORCPT ); Mon, 19 Oct 2020 10:10:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729329AbgJSOKZ (ORCPT ); Mon, 19 Oct 2020 10:10:25 -0400 Received: from mail-pl1-x642.google.com (mail-pl1-x642.google.com [IPv6:2607:f8b0:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7045FC0613D3 for ; Mon, 19 Oct 2020 07:10:24 -0700 (PDT) Received: by mail-pl1-x642.google.com with SMTP id 1so5051368ple.2 for ; Mon, 19 Oct 2020 07:10:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M5rPKt1LwXecMgA/aUeoArPTkPYIqvjmfoxEeqlJkKk=; b=r8kovHa3T7+YriOL07aafDoKEIOmgG5TYVIaUGzmSM5b7dCR3rGWZ2LojYPO4q5Ttl dM/W4wmdfY6ArFSDE+X0Nk6IXPI6fSSV1TwqLr6oDi/7YwiJxXTC/onPSJ7kSGWTL5gv 5sZJ+7ztNq/HiWkYtzQ0d3Al8YJ7FKEsSMfLI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M5rPKt1LwXecMgA/aUeoArPTkPYIqvjmfoxEeqlJkKk=; b=dFmKEnClne6V9MEvGKjP72gVV8e2Z450vv/61jjB7qbXyuBFwuBItoG9yONl0EINV1 IwwkGjOg1ha9nogUUMkPyed9E/0GwRjpsBnoWIchIdiCz8BzE2+9jF5bSsgWN7JIlgqz 2+vDQA679SDBY03RzJ/8I2M1wlmJ2m+c3C8iaRPSaarO5x7bJ7KlDcIAen/wn3m4xgc0 dL4JQyaZmT5tbMZN0kCgkQwJeMoMp6/5S0q7OAujWhtGjmA7DgnNHzad6b8sFUverGzy DN6fKV7volAUzrtkoooOeH8cquP+13jaa4IdZG2/FB3Gjgvwee6k7lQDujvnGo7smHgZ tr+g== X-Gm-Message-State: AOAM533pcBjBdrlNo5LVkGol2Nh6FqnlFk1A6QJJ8PA6Hz2pLLi88den Uc+f34wn6ufbrGfNbKXL/m/pg3FL7pFSYw== X-Google-Smtp-Source: ABdhPJx2kuN89wNsZVVMc+QW6hWY8xLrzX1QED9mfciOIoiTmcAY73n1lOm6+A5TGQP/9Hdzp0Vh6A== X-Received: by 2002:a17:90a:668e:: with SMTP id m14mr17237707pjj.61.1603116623430; Mon, 19 Oct 2020 07:10:23 -0700 (PDT) Received: from shiro.work (p1268123-ipngn200803sizuokaden.shizuoka.ocn.ne.jp. [118.13.124.123]) by smtp.googlemail.com with ESMTPSA id 131sm78999pfy.5.2020.10.19.07.10.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2020 07:10:22 -0700 (PDT) From: Daniel Palmer To: linux-gpio@vger.kernel.org Cc: devicetree@vger.kernel.org, arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linus.walleij@linaro.org, Daniel Palmer Subject: [PATCH v2 3/5] gpio: msc313: MStar MSC313 GPIO driver Date: Mon, 19 Oct 2020 23:10:06 +0900 Message-Id: <20201019141008.871177-4-daniel@0x0f.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201019141008.871177-1-daniel@0x0f.com> References: <20201019141008.871177-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This adds a driver that supports the GPIO block found in MStar/SigmaStar ARMv7 SoCs. The controller seems to support 128 lines but where they are wired up differs between chips and no currently known chip uses anywhere near 128 lines so there needs to be some per-chip data to collect together what lines actually have physical pins attached and map the right names to them. The core peripherals seem to use the same lines on the currently known chips but the lines used for the sensor interface, lcd controller etc pins seem to be totally different between the infinity and mercury chips The code tries to collect all of the re-usable names, offsets etc together so that it's easy to build the extra per-chip data for other chips in the future. So far this only supports the MSC313 and MSC313E chips. Support for the SSC8336N (mercury5) is trivial to add once all of the lines have been mapped out. Signed-off-by: Daniel Palmer --- MAINTAINERS | 1 + drivers/gpio/Kconfig | 9 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-msc313.c | 406 +++++++++++++++++++++++++++++++++++++ 4 files changed, 417 insertions(+) create mode 100644 drivers/gpio/gpio-msc313.c diff --git a/MAINTAINERS b/MAINTAINERS index 102aedca81dc..86b16452c505 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2133,6 +2133,7 @@ F: Documentation/devicetree/bindings/arm/mstar/* F: Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml F: arch/arm/boot/dts/mstar-* F: arch/arm/mach-mstar/ +F: drivers/gpio/gpio-msc313.c F: include/dt-bindings/gpio/msc313-gpio.h ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 5d4de5cd6759..64160cc0a477 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -737,6 +737,15 @@ config GPIO_AMD_FCH Note: This driver doesn't registers itself automatically, as it needs to be provided with platform specific configuration. (See eg. CONFIG_PCENGINES_APU2.) + +config GPIO_MSC313 + bool "MStar MSC313 GPIO support" + default y if ARCH_MSTARV7 + depends on ARCH_MSTARV7 + select GPIOLIB_IRQCHIP + help + Say Y here to support GPIO on MStar MSC313 and later SoCs. + endmenu menu "Port-mapped I/O GPIO drivers" diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 09dada80ac34..b6c116a7c785 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -101,6 +101,7 @@ obj-$(CONFIG_GPIO_MOCKUP) += gpio-mockup.o obj-$(CONFIG_GPIO_MOXTET) += gpio-moxtet.o obj-$(CONFIG_GPIO_MPC5200) += gpio-mpc5200.o obj-$(CONFIG_GPIO_MPC8XXX) += gpio-mpc8xxx.o +obj-$(CONFIG_GPIO_MSC313) += gpio-msc313.o obj-$(CONFIG_GPIO_MSIC) += gpio-msic.o obj-$(CONFIG_GPIO_MT7621) += gpio-mt7621.o obj-$(CONFIG_GPIO_MVEBU) += gpio-mvebu.o diff --git a/drivers/gpio/gpio-msc313.c b/drivers/gpio/gpio-msc313.c new file mode 100644 index 000000000000..2751ee520b86 --- /dev/null +++ b/drivers/gpio/gpio-msc313.c @@ -0,0 +1,406 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Daniel Palmer + */ + +#include +#include +#include + +#include +#include + +#define DRIVER_NAME "gpio-msc313" + +#define MSC313_GPIO_IN BIT(0) +#define MSC313_GPIO_OUT BIT(4) +#define MSC313_GPIO_OEN BIT(5) + +/* These bits need to be saved to correctly restore the + * gpio state when resuming from suspend to memory. + */ +#define MSC313_GPIO_BITSTOSAVE (MSC313_GPIO_OUT | MSC313_GPIO_OEN) + +#define FUART_NAMES \ + MSC313_PINNAME_FUART_RX, \ + MSC313_PINNAME_FUART_TX, \ + MSC313_PINNAME_FUART_CTS, \ + MSC313_PINNAME_FUART_RTS + +#define OFF_FUART_RX 0x50 +#define OFF_FUART_TX 0x54 +#define OFF_FUART_CTS 0x58 +#define OFF_FUART_RTS 0x5c + +#define FUART_OFFSETS \ + OFF_FUART_RX, \ + OFF_FUART_TX, \ + OFF_FUART_CTS, \ + OFF_FUART_RTS + +#define SR_NAMES \ + MSC313_PINNAME_SR_IO2, \ + MSC313_PINNAME_SR_IO3, \ + MSC313_PINNAME_SR_IO4, \ + MSC313_PINNAME_SR_IO5, \ + MSC313_PINNAME_SR_IO6, \ + MSC313_PINNAME_SR_IO7, \ + MSC313_PINNAME_SR_IO8, \ + MSC313_PINNAME_SR_IO9, \ + MSC313_PINNAME_SR_IO10, \ + MSC313_PINNAME_SR_IO11, \ + MSC313_PINNAME_SR_IO12, \ + MSC313_PINNAME_SR_IO13, \ + MSC313_PINNAME_SR_IO14, \ + MSC313_PINNAME_SR_IO15, \ + MSC313_PINNAME_SR_IO16, \ + MSC313_PINNAME_SR_IO17 + +#define OFF_SR_IO2 0x88 +#define OFF_SR_IO3 0x8c +#define OFF_SR_IO4 0x90 +#define OFF_SR_IO5 0x94 +#define OFF_SR_IO6 0x98 +#define OFF_SR_IO7 0x9c +#define OFF_SR_IO8 0xa0 +#define OFF_SR_IO9 0xa4 +#define OFF_SR_IO10 0xa8 +#define OFF_SR_IO11 0xac +#define OFF_SR_IO12 0xb0 +#define OFF_SR_IO13 0xb4 +#define OFF_SR_IO14 0xb8 +#define OFF_SR_IO15 0xbc +#define OFF_SR_IO16 0xc0 +#define OFF_SR_IO17 0xc4 + +#define SR_OFFSETS \ + OFF_SR_IO2, \ + OFF_SR_IO3, \ + OFF_SR_IO4, \ + OFF_SR_IO5, \ + OFF_SR_IO6, \ + OFF_SR_IO7, \ + OFF_SR_IO8, \ + OFF_SR_IO9, \ + OFF_SR_IO10, \ + OFF_SR_IO11, \ + OFF_SR_IO12, \ + OFF_SR_IO13, \ + OFF_SR_IO14, \ + OFF_SR_IO15, \ + OFF_SR_IO16, \ + OFF_SR_IO17 + +#define SD_NAMES \ + MSC313_PINNAME_SD_CLK, \ + MSC313_PINNAME_SD_CMD, \ + MSC313_PINNAME_SD_D0, \ + MSC313_PINNAME_SD_D1, \ + MSC313_PINNAME_SD_D2, \ + MSC313_PINNAME_SD_D3 + +#define OFF_SD_CLK 0x140 +#define OFF_SD_CMD 0x144 +#define OFF_SD_D0 0x148 +#define OFF_SD_D1 0x14c +#define OFF_SD_D2 0x150 +#define OFF_SD_D3 0x154 + +#define SD_OFFSETS \ + OFF_SD_CLK, \ + OFF_SD_CMD, \ + OFF_SD_D0, \ + OFF_SD_D1, \ + OFF_SD_D2, \ + OFF_SD_D3 + +#define I2C1_NAMES \ + MSC313_PINNAME_I2C1_SCL, \ + MSC313_PINNAME_I2C1_SCA + +#define OFF_I2C1_SCL 0x188 +#define OFF_I2C1_SCA 0x18c + +#define I2C1_OFFSETS \ + OFF_I2C1_SCL, \ + OFF_I2C1_SCA + +#define SPI0_NAMES \ + MSC313_PINNAME_SPI0_CZ, \ + MSC313_PINNAME_SPI0_CK, \ + MSC313_PINNAME_SPI0_DI, \ + MSC313_PINNAME_SPI0_DO + +#define OFF_SPI0_CZ 0x1c0 +#define OFF_SPI0_CK 0x1c4 +#define OFF_SPI0_DI 0x1c8 +#define OFF_SPI0_DO 0x1cc + +#define SPI0_OFFSETS \ + OFF_SPI0_CZ, \ + OFF_SPI0_CK, \ + OFF_SPI0_DI, \ + OFF_SPI0_DO + +struct msc313_gpio_data { + const char * const *names; + const unsigned int *offsets; + const unsigned int num; +}; + +#define MSC313_GPIO_CHIPDATA(_chip) \ +static const struct msc313_gpio_data _chip##_data = { \ + .names = _chip##_names, \ + .offsets = _chip##_offsets, \ + .num = ARRAY_SIZE(_chip##_offsets), \ +} + +#ifdef CONFIG_MACH_INFINITY +static const char * const msc313_names[] = { + FUART_NAMES, + SR_NAMES, + SD_NAMES, + I2C1_NAMES, + SPI0_NAMES, +}; + +static const unsigned int msc313_offsets[] = { + FUART_OFFSETS, + SR_OFFSETS, + SD_OFFSETS, + I2C1_OFFSETS, + SPI0_OFFSETS, +}; + +MSC313_GPIO_CHIPDATA(msc313); +#endif + +struct msc313_gpio { + void __iomem *base; + const struct msc313_gpio_data *gpio_data; + u8 *saved; +}; + +static void msc313_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + struct msc313_gpio *gpio = gpiochip_get_data(chip); + u8 gpioreg = readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]); + + if (value) + gpioreg |= MSC313_GPIO_OUT; + else + gpioreg &= ~MSC313_GPIO_OUT; + + writeb_relaxed(gpioreg, gpio->base + gpio->gpio_data->offsets[offset]); +} + +static int msc313_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct msc313_gpio *gpio = gpiochip_get_data(chip); + + return readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]) + & MSC313_GPIO_IN; +} + +static int msc313_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + struct msc313_gpio *gpio = gpiochip_get_data(chip); + u8 gpioreg = readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]); + + gpioreg |= MSC313_GPIO_OEN; + writeb_relaxed(gpioreg, gpio->base + gpio->gpio_data->offsets[offset]); + + return 0; +} + +static int msc313_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value) +{ + struct msc313_gpio *gpio = gpiochip_get_data(chip); + u8 gpioreg = readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]); + + gpioreg &= ~MSC313_GPIO_OEN; + if (value) + gpioreg |= MSC313_GPIO_OUT; + else + gpioreg &= ~MSC313_GPIO_OUT; + writeb_relaxed(gpioreg, gpio->base + gpio->gpio_data->offsets[offset]); + + return 0; +} + +/* + * The interrupt handling happens in the parent interrupt controller, + * we don't do anything here. + */ +static struct irq_chip msc313_gpio_irqchip = { + .name = "GPIO", + .irq_eoi = irq_chip_eoi_parent, + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent, + .irq_set_type = irq_chip_set_type_parent, +}; + +/* The parent interrupt controller needs the GIC interrupt type set to GIC_SPI + * so we need to provide the fwspec. Essentially gpiochip_populate_parent_fwspec_twocell + * that puts GIC_SPI into the first cell. + */ +static void *msc313_gpio_populate_parent_fwspec(struct gpio_chip *gc, + unsigned int parent_hwirq, + unsigned int parent_type) +{ + struct irq_fwspec *fwspec; + + fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL); + if (!fwspec) + return NULL; + + fwspec->fwnode = gc->irq.parent_domain->fwnode; + fwspec->param_count = 3; + fwspec->param[0] = GIC_SPI; + fwspec->param[1] = parent_hwirq; + fwspec->param[2] = parent_type; + + return fwspec; +} + +static int msc313e_gpio_child_to_parent_hwirq(struct gpio_chip *chip, + unsigned int child, + unsigned int child_type, + unsigned int *parent, + unsigned int *parent_type) +{ + struct msc313_gpio *priv = gpiochip_get_data(chip); + unsigned int offset = priv->gpio_data->offsets[child]; + int ret = -EINVAL; + + /* only the spi0 pins have interrupts on the parent + * on all of the known chips and so far they are all + * mapped to the same place + */ + if (offset >= OFF_SPI0_CZ && offset <= OFF_SPI0_DO) { + *parent_type = child_type; + *parent = ((offset - OFF_SPI0_CZ) >> 2) + 28; + ret = 0; + } + + return ret; +} + +static int msc313_gpio_probe(struct platform_device *pdev) +{ + const struct msc313_gpio_data *match_data; + struct msc313_gpio *gpio; + struct gpio_chip *gpiochip; + struct gpio_irq_chip *gpioirqchip; + struct resource *res; + struct irq_domain *parent_domain; + struct device_node *parent_node; + int ret; + + match_data = of_device_get_match_data(&pdev->dev); + if (!match_data) + return -EINVAL; + + parent_node = of_irq_find_parent(pdev->dev.of_node); + if (!parent_node) + return -ENODEV; + + parent_domain = irq_find_host(parent_node); + if (!parent_domain) + return -ENODEV; + + gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); + if (!gpio) + return -ENOMEM; + + gpio->gpio_data = match_data; + + gpio->saved = devm_kzalloc(&pdev->dev, gpio->gpio_data->num * sizeof(*gpio->saved), GFP_KERNEL); + if (!gpio->saved) + return -ENOMEM; + + platform_set_drvdata(pdev, gpio); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + gpio->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(gpio->base)) + return PTR_ERR(gpio->base); + + gpiochip = devm_kzalloc(&pdev->dev, sizeof(*gpiochip), GFP_KERNEL); + if (!gpiochip) + return -ENOMEM; + + gpiochip->label = DRIVER_NAME; + gpiochip->parent = &pdev->dev; + gpiochip->request = gpiochip_generic_request; + gpiochip->free = gpiochip_generic_free; + gpiochip->direction_input = msc313_gpio_direction_input; + gpiochip->direction_output = msc313_gpio_direction_output; + gpiochip->get = msc313_gpio_get; + gpiochip->set = msc313_gpio_set; + gpiochip->base = -1; + gpiochip->ngpio = gpio->gpio_data->num; + gpiochip->names = gpio->gpio_data->names; + + gpioirqchip = &gpiochip->irq; + gpioirqchip->chip = &msc313_gpio_irqchip; + gpioirqchip->fwnode = of_node_to_fwnode(pdev->dev.of_node); + gpioirqchip->parent_domain = parent_domain; + gpioirqchip->child_to_parent_hwirq = msc313e_gpio_child_to_parent_hwirq; + gpioirqchip->populate_parent_alloc_arg = msc313_gpio_populate_parent_fwspec; + gpioirqchip->handler = handle_bad_irq; + gpioirqchip->default_type = IRQ_TYPE_NONE; + + ret = gpiochip_add_data(gpiochip, gpio); + return ret; +} + +static const struct of_device_id msc313_gpio_of_match[] = { +#ifdef CONFIG_MACH_INFINITY + { + .compatible = "mstar,msc313-gpio", + .data = &msc313_data, + }, +#endif + { } +}; + +/* The GPIO controller loses the state of the registers when the + * SoC goes into suspend to memory mode so we need to save some + * of the register bits before suspending and put it back when resuming + */ + +static int __maybe_unused msc313_gpio_suspend(struct device *dev) +{ + struct msc313_gpio *gpio = dev_get_drvdata(dev); + int i; + + for (i = 0; i < gpio->gpio_data->num; i++) + gpio->saved[i] = readb_relaxed(gpio->base + gpio->gpio_data->offsets[i]) & MSC313_GPIO_BITSTOSAVE; + + return 0; +} + +static int __maybe_unused msc313_gpio_resume(struct device *dev) +{ + struct msc313_gpio *gpio = dev_get_drvdata(dev); + int i; + + for (i = 0; i < gpio->gpio_data->num; i++) + writeb_relaxed(gpio->saved[i], gpio->base + gpio->gpio_data->offsets[i]); + + return 0; +} + +static SIMPLE_DEV_PM_OPS(msc313_gpio_ops, msc313_gpio_suspend, msc313_gpio_resume); + +static struct platform_driver msc313_gpio_driver = { + .driver = { + .name = DRIVER_NAME, + .of_match_table = msc313_gpio_of_match, + .pm = &msc313_gpio_ops, + }, + .probe = msc313_gpio_probe, +}; + +builtin_platform_driver(msc313_gpio_driver); From patchwork Mon Oct 19 14:10:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 1384345 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=0x0f.com header.i=@0x0f.com header.a=rsa-sha256 header.s=google header.b=mkJM/n6E; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CFJYx5tMdz9sVX for ; Tue, 20 Oct 2020 01:10:29 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729329AbgJSOK1 (ORCPT ); Mon, 19 Oct 2020 10:10:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729296AbgJSOK0 (ORCPT ); Mon, 19 Oct 2020 10:10:26 -0400 Received: from mail-pj1-x1044.google.com (mail-pj1-x1044.google.com [IPv6:2607:f8b0:4864:20::1044]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D42D7C0613D3 for ; Mon, 19 Oct 2020 07:10:26 -0700 (PDT) Received: by mail-pj1-x1044.google.com with SMTP id gv6so5788791pjb.4 for ; Mon, 19 Oct 2020 07:10:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RHyYXiO83Q4FCDuGfX/cpic280vZhbkkvEAhDolqn+s=; b=mkJM/n6EXDlZYwVEnawgoIFm6dqCY6R9NjJbR89/bcVmSvdpzN1AHqc2/u0BxwwU/S NYlMkoXzPxqjuS4TK4oNIoN5V2y1vTDaWET6wya+UVtfr1AAMJujv7BkbXJ5tGVuSTkn TBK27YOkqogUQ4Rs0Ny5gt7iPQF/VJfZ2Rwbk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RHyYXiO83Q4FCDuGfX/cpic280vZhbkkvEAhDolqn+s=; b=Uc6aFDXQNdPVGerIUxTPKSkTcgwXx8/LSkhZ2Ci1VNbpCCF7ZxpepoRy1JI+QYe2lA gPftZQN8bZp12hAcQ2thyWsQB/wR20IqguIIPPPJXbbOSm31b2+0d7xzKQypUW9AFP4P +QVEwyhb/7PlyUyHkX4cl+Vio8zh8BZHrt3QY2NLD6Gq9GlJnmYbQw4E787GJmDBlrsb +lY/ttUymGjdzjclErz0cscwUDYJpC4w7vE5ROR2J+2BQG/I6Ug7j9ehDbWxeOU/ayyq 5YjTVspmiKIaYbx2Fk2uTZEwkdpRoyyyj1Ap6HuAliwwNDaOfqpO4BJwgmY9+SM16/ZP a1lg== X-Gm-Message-State: AOAM530JGmtNnlr4xYK7o+ovaHYRvkrn9azGHeo2XuaZgXBNxNXQ5/Ki JfFyME4QPFuZgGGkUf7k5REmU8TS1gv1lA== X-Google-Smtp-Source: ABdhPJzzR/OkKdoNnwbobkh1vDYbyHxPt5SYohAM2bfMZJBFeI8RqaHLIN60/Ddf/1iP7g+VcoGwLA== X-Received: by 2002:a17:90a:3fcd:: with SMTP id u13mr17879285pjm.85.1603116626067; Mon, 19 Oct 2020 07:10:26 -0700 (PDT) Received: from shiro.work (p1268123-ipngn200803sizuokaden.shizuoka.ocn.ne.jp. [118.13.124.123]) by smtp.googlemail.com with ESMTPSA id 131sm78999pfy.5.2020.10.19.07.10.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2020 07:10:25 -0700 (PDT) From: Daniel Palmer To: linux-gpio@vger.kernel.org Cc: devicetree@vger.kernel.org, arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linus.walleij@linaro.org, Daniel Palmer Subject: [PATCH v2 4/5] ARM: mstar: Add gpio controller to MStar base dtsi Date: Mon, 19 Oct 2020 23:10:07 +0900 Message-Id: <20201019141008.871177-5-daniel@0x0f.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201019141008.871177-1-daniel@0x0f.com> References: <20201019141008.871177-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The GPIO controller is at the same address in all of the currently known chips so create a node for it in the base dtsi. Some extra properties are needed to actually use it so disable it by default. Signed-off-by: Daniel Palmer Acked-by: Linus Walleij --- arch/arm/boot/dts/mstar-v7.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index f07880561e11..81369bc07f78 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -109,6 +109,16 @@ l3bridge: l3bridge@204400 { reg = <0x204400 0x200>; }; + gpio: gpio@207800 { + #gpio-cells = <2>; + reg = <0x207800 0x200>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&intc_fiq>; + status = "disabled"; + }; + pm_uart: uart@221000 { compatible = "ns16550a"; reg = <0x221000 0x100>; From patchwork Mon Oct 19 14:10:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 1384346 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=0x0f.com header.i=@0x0f.com header.a=rsa-sha256 header.s=google header.b=PpbzUn3b; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CFJZ21XZbz9sSC for ; Tue, 20 Oct 2020 01:10:34 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729418AbgJSOKa (ORCPT ); Mon, 19 Oct 2020 10:10:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729404AbgJSOK3 (ORCPT ); Mon, 19 Oct 2020 10:10:29 -0400 Received: from mail-pl1-x644.google.com (mail-pl1-x644.google.com [IPv6:2607:f8b0:4864:20::644]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 498A0C0613D1 for ; Mon, 19 Oct 2020 07:10:29 -0700 (PDT) Received: by mail-pl1-x644.google.com with SMTP id t22so2081288plr.9 for ; Mon, 19 Oct 2020 07:10:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1yRFSCl/mRcUkS6OvmVba08bS0ib90mEnvumV93631A=; b=PpbzUn3bSYybM/B+P67kwVSTJcSculclJ5cYp+qp02sY9e/t2qzNdkZoyBhy1uYr/G ihQHQwNUe/HNv99lgh72wXRgzmFk0PD3Jaxkj4mdBrs6csNqGxPob+KkU30UKCpyayu4 HFSlbcGJutFyRy5lWg97w43r3cIY7W+gesEZ4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1yRFSCl/mRcUkS6OvmVba08bS0ib90mEnvumV93631A=; b=Tea3UTboKV3sPJu2nzG0IkrAS0ruhVip26HixiwDGTmzNdM7kY3gzmxwItZTy4kiNP fLZCGRL4PnTNUoWunXP0rPYzdDlj90Z2mTGiLuMXi8PvoAuqTsWwpR2VZbWi2DPv5JF2 FucwGqd6LfuKoj7Z59A9Ivsqq9dJiaRZjQcjJ+MvcgOfhkxdWnZFhtQmUUU1uU+DPUdc 0rKdJwCUtO6aYluSTDv/CIW9dQtnzI447k327+DEcCB7kY3b+yzvdCMzjQjilvlJJQSR zA3DViwmTf8e2XjnMf0aky7VJ0Wv52mMt9kOjY1fyvWr8H6Do/zrhFjqSzG5NXtsu5cE 2D1Q== X-Gm-Message-State: AOAM531BeLZBzqhpTjlnGNpjXK90wbi5xvk8yFM9OeZQHNID2R9Lud0D iOHDdI5Eli03UnG6MnuVz3AO+YFecZFYCQ== X-Google-Smtp-Source: ABdhPJyICwRj7p9WMfp/BM1uvsfQPI+SYkKUzGl5TcvdYBXqf14o3hbbIsviNl3qL3r4B3WvD+HnFQ== X-Received: by 2002:a17:90a:3e4a:: with SMTP id t10mr17389449pjm.151.1603116628488; Mon, 19 Oct 2020 07:10:28 -0700 (PDT) Received: from shiro.work (p1268123-ipngn200803sizuokaden.shizuoka.ocn.ne.jp. [118.13.124.123]) by smtp.googlemail.com with ESMTPSA id 131sm78999pfy.5.2020.10.19.07.10.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2020 07:10:27 -0700 (PDT) From: Daniel Palmer To: linux-gpio@vger.kernel.org Cc: devicetree@vger.kernel.org, arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linus.walleij@linaro.org, Daniel Palmer Subject: [PATCH v2 5/5] ARM: mstar: Fill in GPIO controller properties for infinity Date: Mon, 19 Oct 2020 23:10:08 +0900 Message-Id: <20201019141008.871177-6-daniel@0x0f.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201019141008.871177-1-daniel@0x0f.com> References: <20201019141008.871177-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Fill in the properties needed to use the GPIO controller in the infinity and infinity3 chips. Signed-off-by: Daniel Palmer Acked-by: Linus Walleij --- arch/arm/boot/dts/mstar-infinity.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity.dtsi b/arch/arm/boot/dts/mstar-infinity.dtsi index cd911adef014..0bee517797f4 100644 --- a/arch/arm/boot/dts/mstar-infinity.dtsi +++ b/arch/arm/boot/dts/mstar-infinity.dtsi @@ -6,6 +6,13 @@ #include "mstar-v7.dtsi" +#include + &imi { reg = <0xa0000000 0x16000>; }; + +&gpio { + compatible = "mstar,msc313-gpio"; + status = "okay"; +};