From patchwork Thu Oct 15 19:30:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 1382878 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=default header.b=Ajk+KNbd; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CBzsS1xvmz9sTr for ; Fri, 16 Oct 2020 06:30:52 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391577AbgJOTau (ORCPT ); Thu, 15 Oct 2020 15:30:50 -0400 Received: from mail.kernel.org ([198.145.29.99]:58800 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391610AbgJOTau (ORCPT ); Thu, 15 Oct 2020 15:30:50 -0400 Received: from localhost (170.sub-72-107-125.myvzw.com [72.107.125.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5EE93206DD; Thu, 15 Oct 2020 19:30:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1602790249; bh=AAl1svi5X5RLBT8xujD80/Js1bxdtUHZvExslzti8zo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ajk+KNbdq6idjSsqV1OgLcwI38QG3sm1KD0LwRBmF4zWy88CiM4ar65FafxUsRhH/ Y4P9NWHnwIwhK7OYjGzk4gvM2c0m5cqYb/xEynh0RaoQ/2kCp9huhdpCRsu0p/bULs N3n9zOMY8lNrSEhW88TEWj51KbFjpzbmtFRzkQnY= From: Bjorn Helgaas To: "Saheed O . Bolarinwa" Cc: Puranjay Mohan , Rajat Jain , Kai-Heng Feng , Yicong Yang , Heiner Kallweit , linux-pci@vger.kernel.org, Bjorn Helgaas Subject: [PATCH v3 01/12] PCI/ASPM: Move pci_clear_and_set_dword() earlier Date: Thu, 15 Oct 2020 14:30:28 -0500 Message-Id: <20201015193039.12585-2-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201015193039.12585-1-helgaas@kernel.org> References: <20201015193039.12585-1-helgaas@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bjorn Helgaas Move pci_clear_and_set_dword() earlier in file to prepare for future patch. No functional change intended. Signed-off-by: Bjorn Helgaas --- drivers/pci/pcie/aspm.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 253c30cc1967..237a423e53ae 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -493,6 +493,17 @@ static struct pci_dev *pci_function_0(struct pci_bus *linkbus) return NULL; } +static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos, + u32 clear, u32 set) +{ + u32 val; + + pci_read_config_dword(pdev, pos, &val); + val &= ~clear; + val |= set; + pci_write_config_dword(pdev, pos, val); +} + /* Calculate L1.2 PM substate timing parameters */ static void aspm_calc_l1ss_info(struct pcie_link_state *link, struct aspm_register_info *upreg, @@ -651,17 +662,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) } } -static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos, - u32 clear, u32 set) -{ - u32 val; - - pci_read_config_dword(pdev, pos, &val); - val &= ~clear; - val |= set; - pci_write_config_dword(pdev, pos, val); -} - /* Configure the ASPM L1 substates */ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) { From patchwork Thu Oct 15 19:30:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 1382879 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=default header.b=lDIdOmKg; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CBzsV6J3pz9sTs for ; Fri, 16 Oct 2020 06:30:54 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391541AbgJOTaw (ORCPT ); Thu, 15 Oct 2020 15:30:52 -0400 Received: from mail.kernel.org ([198.145.29.99]:58848 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391629AbgJOTaw (ORCPT ); Thu, 15 Oct 2020 15:30:52 -0400 Received: from localhost (170.sub-72-107-125.myvzw.com [72.107.125.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 3F245206E5; Thu, 15 Oct 2020 19:30:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1602790251; bh=p2j/WDrrVUQ9hJ1Htvj6Dt6Xf3cMJEzNnG/RuqjHYO4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lDIdOmKg1go4ppMTJ/ex8NrHpS5zaonqKw2pOCn2CDz5AXy3FRVhhUzkLItONk4eZ 0S+r9EHHyEn6qCk7RLn1CKyYzuepKpkm4lTz/PMQjBQI9PoghA7cqGSDtLP+hskTVX N0Erd53tDnCPNhOJASz4uTDMQUPWK4S0apZbzhmg= From: Bjorn Helgaas To: "Saheed O . Bolarinwa" Cc: Puranjay Mohan , Rajat Jain , Kai-Heng Feng , Yicong Yang , Heiner Kallweit , linux-pci@vger.kernel.org, Bjorn Helgaas Subject: [PATCH v3 02/12] PCI/ASPM: Move LTR path check to where it's used Date: Thu, 15 Oct 2020 14:30:29 -0500 Message-Id: <20201015193039.12585-3-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201015193039.12585-1-helgaas@kernel.org> References: <20201015193039.12585-1-helgaas@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bjorn Helgaas pcie_get_aspm_reg() mostly reads ASPM-related registers, but in some cases it also updates the value read from PCI_L1SS_CAP based on LTR properties. Move this update to the point where the value is used to make the code more readable. No functional change intended, although previously we could clear PCI_L1SS_CAP_ASPM_L1_2 for both ends of the link, and now we'll only do it for the downstream end of a link. This shouldn't matter because we always test that bit by ANDing l1ss_cap for the upstream and downstream ends. Signed-off-by: Bjorn Helgaas --- drivers/pci/pcie/aspm.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 237a423e53ae..386b45eb79ba 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -418,14 +418,6 @@ static void pcie_get_aspm_reg(struct pci_dev *pdev, return; } - /* - * If we don't have LTR for the entire path from the Root Complex - * to this device, we can't use ASPM L1.2 because it relies on the - * LTR_L1.2_THRESHOLD. See PCIe r4.0, secs 5.5.4, 6.18. - */ - if (!pdev->ltr_path) - info->l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2; - pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL1, &info->l1ss_ctl1); pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL2, @@ -612,7 +604,14 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1); link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1); - /* Setup L1 substate */ + /* Setup L1 substate + * If we don't have LTR for the entire path from the Root Complex + * to this device, we can't use ASPM L1.2 because it relies on the + * LTR_L1.2_THRESHOLD. See PCIe r4.0, secs 5.5.4, 6.18. + */ + if (!child->ltr_path) + dwreg.l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2; + if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1) link->aspm_support |= ASPM_STATE_L1_1; if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2) From patchwork Thu Oct 15 19:30:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 1382880 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=default header.b=rYha7sjs; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CBzsc2Pdxz9sTr for ; Fri, 16 Oct 2020 06:31:00 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391638AbgJOTa7 (ORCPT ); Thu, 15 Oct 2020 15:30:59 -0400 Received: from mail.kernel.org ([198.145.29.99]:58938 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391630AbgJOTay (ORCPT ); Thu, 15 Oct 2020 15:30:54 -0400 Received: from localhost (170.sub-72-107-125.myvzw.com [72.107.125.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 26C60206DC; Thu, 15 Oct 2020 19:30:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1602790253; bh=A6GOy1297OFSjOFxP8sRZqYqoBjX7BnzTmvMbvnJmaM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rYha7sjs8IzJX4w2g7ssdZjmCDjXsmJ2w3mI7j/frN31c9O3L4QxRHqEfbhjy1K2i 0koYM0dZM/ESxtspNOqFiZJs5ySbHT81bTVkbAdBEXuXzKed/2maSP/lGjvieV2Go1 nF4Eoax9OqkO8WGT+fmw30kwO6fhGAxTu1P30ogE= From: Bjorn Helgaas To: "Saheed O . Bolarinwa" Cc: Puranjay Mohan , Rajat Jain , Kai-Heng Feng , Yicong Yang , Heiner Kallweit , linux-pci@vger.kernel.org, Bjorn Helgaas Subject: [PATCH v3 03/12] PCI/ASPM: Use 'parent' and 'child' for readability Date: Thu, 15 Oct 2020 14:30:30 -0500 Message-Id: <20201015193039.12585-4-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201015193039.12585-1-helgaas@kernel.org> References: <20201015193039.12585-1-helgaas@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bjorn Helgaas Other users of link->pdev and link->downstream, e.g., pcie_aspm_cap_init(), pcie_config_aspm_l1ss(), and pcie_config_aspm_link(), use "parent" and "child" as local names. Do the same in aspm_calc_l1ss_info() for readability. No functional change intended. Signed-off-by: Bjorn Helgaas --- drivers/pci/pcie/aspm.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 386b45eb79ba..0725511cbeb5 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -501,6 +501,7 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, struct aspm_register_info *upreg, struct aspm_register_info *dwreg) { + struct pci_dev *child = link->downstream, *parent = link->pdev; u32 val1, val2, scale1, scale2; u32 t_common_mode, t_power_on, l1_2_threshold, scale, value; @@ -522,13 +523,13 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19; scale2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16; - if (calc_l1ss_pwron(link->pdev, scale1, val1) > - calc_l1ss_pwron(link->downstream, scale2, val2)) { + if (calc_l1ss_pwron(parent, scale1, val1) > + calc_l1ss_pwron(child, scale2, val2)) { link->l1ss.ctl2 |= scale1 | (val1 << 3); - t_power_on = calc_l1ss_pwron(link->pdev, scale1, val1); + t_power_on = calc_l1ss_pwron(parent, scale1, val1); } else { link->l1ss.ctl2 |= scale2 | (val2 << 3); - t_power_on = calc_l1ss_pwron(link->downstream, scale2, val2); + t_power_on = calc_l1ss_pwron(child, scale2, val2); } /* From patchwork Thu Oct 15 19:30:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 1382881 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=default header.b=wOKmVGIZ; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CBzsc4zsZz9sTs for ; Fri, 16 Oct 2020 06:31:00 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391630AbgJOTa7 (ORCPT ); Thu, 15 Oct 2020 15:30:59 -0400 Received: from mail.kernel.org ([198.145.29.99]:59028 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391633AbgJOTa4 (ORCPT ); Thu, 15 Oct 2020 15:30:56 -0400 Received: from localhost (170.sub-72-107-125.myvzw.com [72.107.125.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 57948206E5; Thu, 15 Oct 2020 19:30:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1602790255; bh=BIWdlt3KOFitTsFFJJmAHPLrPeeq0eDqqnfZrl8ia9U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=wOKmVGIZxLBBdzS/Rb95uD5mEwEpILfigVY672NDEy52ts6q1wT6epWy4LriiC4wo mP+sMUBeWS2uM3n7Hlc9HGdlg/fHeMRxlsBc8VV0yWZAnZOV92atC4P5RYM6H15DhC oiT8n50ud9AgSQQBrPJTrRQp0N2WgyvPNv8CGOLA= From: Bjorn Helgaas To: "Saheed O . Bolarinwa" Cc: Puranjay Mohan , Rajat Jain , Kai-Heng Feng , Yicong Yang , Heiner Kallweit , linux-pci@vger.kernel.org, Bjorn Helgaas Subject: [PATCH v3 04/12] PCI/ASPM: Remove struct aspm_register_info.support Date: Thu, 15 Oct 2020 14:30:31 -0500 Message-Id: <20201015193039.12585-5-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201015193039.12585-1-helgaas@kernel.org> References: <20201015193039.12585-1-helgaas@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: "Saheed O. Bolarinwa" Previously we stored the "ASPM Support" field from the Link Capabilities register in the struct aspm_register_info. Read the Link Capabilities directly when needed and remove it from the struct aspm_register_info. No functional change intended. [bhelgaas: remove pci_dev cached copy since LNKCAP isn't truly read-only, add PCI_EXP_LNKCAP_ASPM_L0S & PCI_EXP_LNKCAP_ASPM_L1, check them directly instead of adding aspm_support()] Signed-off-by: Saheed O. Bolarinwa Signed-off-by: Bjorn Helgaas --- drivers/pci/pcie/aspm.c | 25 ++++++++++++++----------- include/uapi/linux/pci_regs.h | 2 ++ 2 files changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 0725511cbeb5..82ce34e2ef53 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -381,7 +381,6 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) } struct aspm_register_info { - u32 support:2; u32 enabled:2; u32 latency_encoding_l0s; u32 latency_encoding_l1; @@ -400,7 +399,6 @@ static void pcie_get_aspm_reg(struct pci_dev *pdev, u32 reg32; pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32); - info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, ®16); @@ -550,6 +548,7 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) { struct pci_dev *child = link->downstream, *parent = link->pdev; + u32 parent_lnkcap, child_lnkcap; struct pci_bus *linkbus = parent->subordinate; struct aspm_register_info upreg, dwreg; @@ -560,24 +559,26 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) return; } - /* Get upstream/downstream components' register state */ - pcie_get_aspm_reg(parent, &upreg); - pcie_get_aspm_reg(child, &dwreg); - /* * If ASPM not supported, don't mess with the clocks and link, * bail out now. */ - if (!(upreg.support & dwreg.support)) + pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap); + pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap); + if (!(parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPMS)) return; /* Configure common clock before checking latencies */ pcie_aspm_configure_common_clock(link); /* - * Re-read upstream/downstream components' register state - * after clock configuration + * Re-read upstream/downstream components' register state after + * clock configuration. L0s & L1 exit latencies in the otherwise + * read-only Link Capabilities may change depending on common clock + * configuration (PCIe r5.0, sec 7.5.3.6). */ + pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap); + pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap); pcie_get_aspm_reg(parent, &upreg); pcie_get_aspm_reg(child, &dwreg); @@ -588,8 +589,9 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) * given link unless components on both sides of the link each * support L0s. */ - if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S) + if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L0S) link->aspm_support |= ASPM_STATE_L0S; + if (dwreg.enabled & PCIE_LINK_STATE_L0S) link->aspm_enabled |= ASPM_STATE_L0S_UP; if (upreg.enabled & PCIE_LINK_STATE_L0S) @@ -598,8 +600,9 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s); /* Setup L1 state */ - if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1) + if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L1) link->aspm_support |= ASPM_STATE_L1; + if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1) link->aspm_enabled |= ASPM_STATE_L1; link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1); diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index f9701410d3b5..06846ec2e071 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -532,6 +532,8 @@ #define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */ #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ +#define PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */ +#define PCI_EXP_LNKCAP_ASPM_L1 0x00000800 /* ASPM L1 Support */ #define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */ #define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */ #define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* Clock Power Management */ From patchwork Thu Oct 15 19:30:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 1382882 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=default header.b=WW4z/2Ki; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CBzsd27gfz9sTr for ; Fri, 16 Oct 2020 06:31:01 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391633AbgJOTbA (ORCPT ); Thu, 15 Oct 2020 15:31:00 -0400 Received: from mail.kernel.org ([198.145.29.99]:59054 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391634AbgJOTa6 (ORCPT ); Thu, 15 Oct 2020 15:30:58 -0400 Received: from localhost (170.sub-72-107-125.myvzw.com [72.107.125.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 46A58206DD; Thu, 15 Oct 2020 19:30:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1602790257; bh=ImMkU88F5g3mY5suNRCtu2cVYxORtR49r56fUGVzaFE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WW4z/2KiXlOjaQr9oQMyToCWXiDC8CqLQJgIuIl+vYa7/TzIXD+s0WuNrtuNMdV7X 8o4upWU5IyoIkSf1OrIkFZTt2rFz2S0IQ8DI0UEM0EMpD9y7ghXP5JGmv8L9twNA1V 5TGpvAKUnmjMaX/hZzpTIWE1feXPHboAtIzDLdR8= From: Bjorn Helgaas To: "Saheed O . Bolarinwa" Cc: Puranjay Mohan , Rajat Jain , Kai-Heng Feng , Yicong Yang , Heiner Kallweit , linux-pci@vger.kernel.org, Bjorn Helgaas Subject: [PATCH v3 05/12] PCI/ASPM: Remove struct aspm_register_info.enabled Date: Thu, 15 Oct 2020 14:30:32 -0500 Message-Id: <20201015193039.12585-6-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201015193039.12585-1-helgaas@kernel.org> References: <20201015193039.12585-1-helgaas@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: "Saheed O. Bolarinwa" Previously we stored the "ASPM Control" bits from the Link Control register in the struct aspm_register_info. Read PCI_EXP_LNKCTL directly when needed. This means we can use the PCI_EXP_LNKCTL_ASPM_* bits directly instead of the similar but different PCIE_LINK_STATE_* bits. No functional change intended. [bhelgaas: drop get_aspm_enable() and read LNKCTL once directly] Signed-off-by: Saheed O. Bolarinwa Signed-off-by: Bjorn Helgaas --- drivers/pci/pcie/aspm.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 82ce34e2ef53..36540879586b 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -381,10 +381,8 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) } struct aspm_register_info { - u32 enabled:2; u32 latency_encoding_l0s; u32 latency_encoding_l1; - /* L1 substates */ u32 l1ss_cap_ptr; u32 l1ss_cap; @@ -395,14 +393,11 @@ struct aspm_register_info { static void pcie_get_aspm_reg(struct pci_dev *pdev, struct aspm_register_info *info) { - u16 reg16; u32 reg32; pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32); info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; - pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, ®16); - info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC; /* Read L1 PM substate capabilities */ info->l1ss_cap = info->l1ss_ctl1 = info->l1ss_ctl2 = 0; @@ -549,6 +544,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) { struct pci_dev *child = link->downstream, *parent = link->pdev; u32 parent_lnkcap, child_lnkcap; + u16 parent_lnkctl, child_lnkctl; struct pci_bus *linkbus = parent->subordinate; struct aspm_register_info upreg, dwreg; @@ -579,6 +575,8 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) */ pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap); pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap); + pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl); + pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl); pcie_get_aspm_reg(parent, &upreg); pcie_get_aspm_reg(child, &dwreg); @@ -592,9 +590,9 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L0S) link->aspm_support |= ASPM_STATE_L0S; - if (dwreg.enabled & PCIE_LINK_STATE_L0S) + if (child_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S) link->aspm_enabled |= ASPM_STATE_L0S_UP; - if (upreg.enabled & PCIE_LINK_STATE_L0S) + if (parent_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S) link->aspm_enabled |= ASPM_STATE_L0S_DW; link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s); link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s); @@ -603,7 +601,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L1) link->aspm_support |= ASPM_STATE_L1; - if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1) + if (parent_lnkctl & child_lnkctl & PCI_EXP_LNKCTL_ASPM_L1) link->aspm_enabled |= ASPM_STATE_L1; link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1); link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1); From patchwork Thu Oct 15 19:30:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 1382883 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=default header.b=YTCpHvcX; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CBzsd5dqLz9sTv for ; Fri, 16 Oct 2020 06:31:01 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391634AbgJOTbA (ORCPT ); Thu, 15 Oct 2020 15:31:00 -0400 Received: from mail.kernel.org ([198.145.29.99]:59076 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391639AbgJOTbA (ORCPT ); Thu, 15 Oct 2020 15:31:00 -0400 Received: from localhost (170.sub-72-107-125.myvzw.com [72.107.125.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 2B988206ED; Thu, 15 Oct 2020 19:30:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1602790259; bh=RLHkM1QIOUSxqpToyowl1bo3pN3+QbP1dLvimrH1T9I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YTCpHvcX5vNSICS49zdHUmwf3bu0fTWFIzNIwM5WmlKD+XxZQ1ZuYY2RfzWThivIw SHgwuRMNJdEBWJAVX5njEIp49YP0tNvNXeXis8WwDbFDGHiGY+XNaYXhY7E+JKA8I3 VICsTH23nSAAbkC83QkchvCXU7FLJWu1LWm6Tp3A= From: Bjorn Helgaas To: "Saheed O . Bolarinwa" Cc: Puranjay Mohan , Rajat Jain , Kai-Heng Feng , Yicong Yang , Heiner Kallweit , linux-pci@vger.kernel.org, Bjorn Helgaas Subject: [PATCH v3 06/12] PCI/ASPM: Remove struct aspm_register_info.latency_encoding Date: Thu, 15 Oct 2020 14:30:33 -0500 Message-Id: <20201015193039.12585-7-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201015193039.12585-1-helgaas@kernel.org> References: <20201015193039.12585-1-helgaas@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: "Saheed O. Bolarinwa" Previously we stored L0s and L1 Exit Latency information from the Link Capabilities register in the struct aspm_register_info. We only need these latencies when we already have the Link Capabilities values, so use those directly and remove the latencies from struct aspm_register_info. No functional change intended. Signed-off-by: Saheed O. Bolarinwa Signed-off-by: Bjorn Helgaas --- drivers/pci/pcie/aspm.c | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 36540879586b..fd6e597b9d74 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -308,8 +308,10 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) } /* Convert L0s latency encoding to ns */ -static u32 calc_l0s_latency(u32 encoding) +static u32 calc_l0s_latency(u32 lnkcap) { + u32 encoding = (lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12; + if (encoding == 0x7) return (5 * 1000); /* > 4us */ return (64 << encoding); @@ -324,8 +326,10 @@ static u32 calc_l0s_acceptable(u32 encoding) } /* Convert L1 latency encoding to ns */ -static u32 calc_l1_latency(u32 encoding) +static u32 calc_l1_latency(u32 lnkcap) { + u32 encoding = (lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15; + if (encoding == 0x7) return (65 * 1000); /* > 64us */ return (1000 << encoding); @@ -381,8 +385,6 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) } struct aspm_register_info { - u32 latency_encoding_l0s; - u32 latency_encoding_l1; /* L1 substates */ u32 l1ss_cap_ptr; u32 l1ss_cap; @@ -393,12 +395,6 @@ struct aspm_register_info { static void pcie_get_aspm_reg(struct pci_dev *pdev, struct aspm_register_info *info) { - u32 reg32; - - pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32); - info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; - info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; - /* Read L1 PM substate capabilities */ info->l1ss_cap = info->l1ss_ctl1 = info->l1ss_ctl2 = 0; info->l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); @@ -594,8 +590,8 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) link->aspm_enabled |= ASPM_STATE_L0S_UP; if (parent_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S) link->aspm_enabled |= ASPM_STATE_L0S_DW; - link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s); - link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s); + link->latency_up.l0s = calc_l0s_latency(parent_lnkcap); + link->latency_dw.l0s = calc_l0s_latency(child_lnkcap); /* Setup L1 state */ if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L1) @@ -603,8 +599,8 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) if (parent_lnkctl & child_lnkctl & PCI_EXP_LNKCTL_ASPM_L1) link->aspm_enabled |= ASPM_STATE_L1; - link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1); - link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1); + link->latency_up.l1 = calc_l1_latency(parent_lnkcap); + link->latency_dw.l1 = calc_l1_latency(child_lnkcap); /* Setup L1 substate * If we don't have LTR for the entire path from the Root Complex From patchwork Thu Oct 15 19:30:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 1382889 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=default header.b=kizkFFCn; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CBzt05lGJz9sTm for ; Fri, 16 Oct 2020 06:31:20 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391652AbgJOTbR (ORCPT ); Thu, 15 Oct 2020 15:31:17 -0400 Received: from mail.kernel.org ([198.145.29.99]:59146 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391629AbgJOTbC (ORCPT ); Thu, 15 Oct 2020 15:31:02 -0400 Received: from localhost (170.sub-72-107-125.myvzw.com [72.107.125.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 1A6DF20776; Thu, 15 Oct 2020 19:31:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1602790261; bh=DsIgBKxRXuJv/hTxg7yIUIDKWsTz1FUIZxPkb8yzog8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kizkFFCnftiIBBRYDI/GBKo1dtEZLVHN1LqdWIYJKDDV4AK9XIRQhhuwzNIm0YHh2 o3BIl/sFq8ckIZ5DXtQGXI2wvMmPcY5sX0AHF+nYfhv5QndK183dyZKav3gqFGaSXK l96nOIwLKHEu9m42l+J6oV+VAaNfsvGQ9tTt3LNU= From: Bjorn Helgaas To: "Saheed O . Bolarinwa" Cc: Puranjay Mohan , Rajat Jain , Kai-Heng Feng , Yicong Yang , Heiner Kallweit , linux-pci@vger.kernel.org, Bjorn Helgaas Subject: [PATCH v3 07/12] PCI/ASPM: Remove struct aspm_register_info.l1ss_cap_ptr Date: Thu, 15 Oct 2020 14:30:34 -0500 Message-Id: <20201015193039.12585-8-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201015193039.12585-1-helgaas@kernel.org> References: <20201015193039.12585-1-helgaas@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: "Saheed O. Bolarinwa" Save the L1 Substates Capability pointer in struct pci_dev. Then we don't have to keep track of it in the struct aspm_register_info and struct pcie_link_state, which makes the code easier to read. No functional change intended. [bhelgaas: split to a separate patch] Signed-off-by: Saheed O. Bolarinwa Signed-off-by: Bjorn Helgaas --- drivers/pci/pcie/aspm.c | 36 +++++++++++++++--------------------- drivers/pci/probe.c | 3 +++ include/linux/pci.h | 1 + 3 files changed, 19 insertions(+), 21 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index fd6e597b9d74..77316262f982 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -77,8 +77,6 @@ struct pcie_link_state { /* L1 PM Substate info */ struct { - u32 up_cap_ptr; /* L1SS cap ptr in upstream dev */ - u32 dw_cap_ptr; /* L1SS cap ptr in downstream dev */ u32 ctl1; /* value to be programmed in ctl1 */ u32 ctl2; /* value to be programmed in ctl2 */ } l1ss; @@ -386,7 +384,6 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) struct aspm_register_info { /* L1 substates */ - u32 l1ss_cap_ptr; u32 l1ss_cap; u32 l1ss_ctl1; u32 l1ss_ctl2; @@ -397,19 +394,20 @@ static void pcie_get_aspm_reg(struct pci_dev *pdev, { /* Read L1 PM substate capabilities */ info->l1ss_cap = info->l1ss_ctl1 = info->l1ss_ctl2 = 0; - info->l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); - if (!info->l1ss_cap_ptr) + + if (!pdev->l1ss) return; - pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CAP, + + pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CAP, &info->l1ss_cap); if (!(info->l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) { info->l1ss_cap = 0; return; } - pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL1, + pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1, &info->l1ss_ctl1); - pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL2, + pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL2, &info->l1ss_ctl2); } @@ -494,8 +492,6 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, u32 val1, val2, scale1, scale2; u32 t_common_mode, t_power_on, l1_2_threshold, scale, value; - link->l1ss.up_cap_ptr = upreg->l1ss_cap_ptr; - link->l1ss.dw_cap_ptr = dwreg->l1ss_cap_ptr; link->l1ss.ctl1 = link->l1ss.ctl2 = 0; if (!(link->aspm_support & ASPM_STATE_L1_2_MASK)) @@ -664,8 +660,6 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) { u32 val, enable_req; struct pci_dev *child = link->downstream, *parent = link->pdev; - u32 up_cap_ptr = link->l1ss.up_cap_ptr; - u32 dw_cap_ptr = link->l1ss.dw_cap_ptr; enable_req = (link->aspm_enabled ^ state) & state; @@ -683,9 +677,9 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) */ /* Disable all L1 substates */ - pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1, + pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, PCI_L1SS_CTL1_L1SS_MASK, 0); - pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, + pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, PCI_L1SS_CTL1_L1SS_MASK, 0); /* * If needed, disable L1, and it gets enabled later @@ -701,22 +695,22 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) if (enable_req & ASPM_STATE_L1_2_MASK) { /* Program T_POWER_ON times in both ports */ - pci_write_config_dword(parent, up_cap_ptr + PCI_L1SS_CTL2, + pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, link->l1ss.ctl2); - pci_write_config_dword(child, dw_cap_ptr + PCI_L1SS_CTL2, + pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, link->l1ss.ctl2); /* Program Common_Mode_Restore_Time in upstream device */ - pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, + pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, PCI_L1SS_CTL1_CM_RESTORE_TIME, link->l1ss.ctl1); /* Program LTR_L1.2_THRESHOLD time in both ports */ - pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, + pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, PCI_L1SS_CTL1_LTR_L12_TH_VALUE | PCI_L1SS_CTL1_LTR_L12_TH_SCALE, link->l1ss.ctl1); - pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1, + pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, PCI_L1SS_CTL1_LTR_L12_TH_VALUE | PCI_L1SS_CTL1_LTR_L12_TH_SCALE, link->l1ss.ctl1); @@ -733,9 +727,9 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) val |= PCI_L1SS_CTL1_PCIPM_L1_2; /* Enable what we need to enable */ - pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, + pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, PCI_L1SS_CTL1_L1SS_MASK, val); - pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1, + pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, PCI_L1SS_CTL1_L1SS_MASK, val); } diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 03d37128a24f..06f6bbcd8131 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2106,6 +2106,9 @@ static void pci_configure_ltr(struct pci_dev *dev) if (!pci_is_pcie(dev)) return; + /* Read L1 PM substate capabilities */ + dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS); + pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); if (!(cap & PCI_EXP_DEVCAP2_LTR)) return; diff --git a/include/linux/pci.h b/include/linux/pci.h index 835530605c0d..c5288cd71a2e 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -380,6 +380,7 @@ struct pci_dev { struct pcie_link_state *link_state; /* ASPM link state */ unsigned int ltr_path:1; /* Latency Tolerance Reporting supported from root to here */ + int l1ss; /* L1SS Capability pointer */ #endif unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ From patchwork Thu Oct 15 19:30:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 1382888 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=default header.b=BazraFT1; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CBzt02Db2z9sTL for ; Fri, 16 Oct 2020 06:31:20 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391669AbgJOTbR (ORCPT ); Thu, 15 Oct 2020 15:31:17 -0400 Received: from mail.kernel.org ([198.145.29.99]:59232 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391652AbgJOTbD (ORCPT ); Thu, 15 Oct 2020 15:31:03 -0400 Received: from localhost (170.sub-72-107-125.myvzw.com [72.107.125.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id EECC3206DC; Thu, 15 Oct 2020 19:31:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1602790263; bh=Ts9Ogq/knq60d2xJ/wIIS286CrO21aBQp0RqyebmSj0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BazraFT1uzNK04UCUubGrBQYAlwMBEfJgYU5FqpfKBEP0d0V+dwkQTfK8tKrtUnQa qjremlj/mxR95JLaYF4UYhiXCfISKW1wQfjUw1pyHdGm2LOYH4rcLKVBaRU0i6+6Ow xKYlgbPcXRB3j0exOaUcopHZwhmv+ox6mZTfA9wA= From: Bjorn Helgaas To: "Saheed O . Bolarinwa" Cc: Puranjay Mohan , Rajat Jain , Kai-Heng Feng , Yicong Yang , Heiner Kallweit , linux-pci@vger.kernel.org, Bjorn Helgaas Subject: [PATCH v3 08/12] PCI/ASPM: Remove struct aspm_register_info.l1ss_ctl2 (unused) Date: Thu, 15 Oct 2020 14:30:35 -0500 Message-Id: <20201015193039.12585-9-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201015193039.12585-1-helgaas@kernel.org> References: <20201015193039.12585-1-helgaas@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bjorn Helgaas We never use the aspm_register_info.l1ss_ctl2 value, so remove it. No functional change intended. Signed-off-by: Bjorn Helgaas --- drivers/pci/pcie/aspm.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 77316262f982..3afa6c418f54 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -386,14 +386,13 @@ struct aspm_register_info { /* L1 substates */ u32 l1ss_cap; u32 l1ss_ctl1; - u32 l1ss_ctl2; }; static void pcie_get_aspm_reg(struct pci_dev *pdev, struct aspm_register_info *info) { /* Read L1 PM substate capabilities */ - info->l1ss_cap = info->l1ss_ctl1 = info->l1ss_ctl2 = 0; + info->l1ss_cap = info->l1ss_ctl1 = 0; if (!pdev->l1ss) return; @@ -407,8 +406,6 @@ static void pcie_get_aspm_reg(struct pci_dev *pdev, pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1, &info->l1ss_ctl1); - pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL2, - &info->l1ss_ctl2); } static void pcie_aspm_check_latency(struct pci_dev *endpoint) From patchwork Thu Oct 15 19:30:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 1382884 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=default header.b=qcD1Hhz2; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CBzsy2mPwz9sTL for ; Fri, 16 Oct 2020 06:31:18 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391675AbgJOTbP (ORCPT ); Thu, 15 Oct 2020 15:31:15 -0400 Received: from mail.kernel.org ([198.145.29.99]:59302 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391663AbgJOTbG (ORCPT ); Thu, 15 Oct 2020 15:31:06 -0400 Received: from localhost (170.sub-72-107-125.myvzw.com [72.107.125.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 43EE7206DD; Thu, 15 Oct 2020 19:31:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1602790265; bh=OR17RUHbbCdmzYzX8/EpGdbQZ2+xd5ITl0T/6gUEYfU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qcD1Hhz2getDd6qENJV6NODbXhV6KRDy4Y3T4fyCWZlFFbr2hdyeUj5AUyXf19XEw 36NuZHQa09d+ohVtgQhPeEpmqlYeqr7/mOMBul2il1L3+hgwJWIL8BMG6wCOhyaYJM 7SWlRVvCtEftKnmHUX+9wYeg4p8lf/pdY6DGDpik= From: Bjorn Helgaas To: "Saheed O . Bolarinwa" Cc: Puranjay Mohan , Rajat Jain , Kai-Heng Feng , Yicong Yang , Heiner Kallweit , linux-pci@vger.kernel.org, Bjorn Helgaas Subject: [PATCH v3 09/12] PCI/ASPM: Remove struct aspm_register_info.l1ss_ctl1 Date: Thu, 15 Oct 2020 14:30:36 -0500 Message-Id: <20201015193039.12585-10-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201015193039.12585-1-helgaas@kernel.org> References: <20201015193039.12585-1-helgaas@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: "Saheed O. Bolarinwa" Previously we stored the L1SS Control 1 register in the struct aspm_register_info. We only need this information in one place, so read it there and remove it from struct aspm_register_info. No functional change intended. [bhelgaas: split ctl1/ctl2] Signed-off-by: Saheed O. Bolarinwa Signed-off-by: Bjorn Helgaas --- drivers/pci/pcie/aspm.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 3afa6c418f54..896f6c0b08c6 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -385,27 +385,21 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) struct aspm_register_info { /* L1 substates */ u32 l1ss_cap; - u32 l1ss_ctl1; }; static void pcie_get_aspm_reg(struct pci_dev *pdev, struct aspm_register_info *info) { /* Read L1 PM substate capabilities */ - info->l1ss_cap = info->l1ss_ctl1 = 0; + info->l1ss_cap = 0; if (!pdev->l1ss) return; pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CAP, &info->l1ss_cap); - if (!(info->l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) { + if (!(info->l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) info->l1ss_cap = 0; - return; - } - - pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1, - &info->l1ss_ctl1); } static void pcie_aspm_check_latency(struct pci_dev *endpoint) @@ -534,6 +528,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) struct pci_dev *child = link->downstream, *parent = link->pdev; u32 parent_lnkcap, child_lnkcap; u16 parent_lnkctl, child_lnkctl; + u32 parent_l1ss_ctl1 = 0, child_l1ss_ctl1 = 0; struct pci_bus *linkbus = parent->subordinate; struct aspm_register_info upreg, dwreg; @@ -612,13 +607,20 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2) link->aspm_support |= ASPM_STATE_L1_2_PCIPM; - if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1) + if (upreg.l1ss_cap) + pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, + &parent_l1ss_ctl1); + if (dwreg.l1ss_cap) + pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, + &child_l1ss_ctl1); + + if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1) link->aspm_enabled |= ASPM_STATE_L1_1; - if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2) + if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2) link->aspm_enabled |= ASPM_STATE_L1_2; - if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1) + if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1) link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM; - if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2) + if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2) link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM; if (link->aspm_support & ASPM_STATE_L1SS) From patchwork Thu Oct 15 19:30:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 1382885 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=default header.b=JsL/0Lme; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CBzsy6CGhz9sTm for ; Fri, 16 Oct 2020 06:31:18 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391663AbgJOTbQ (ORCPT ); Thu, 15 Oct 2020 15:31:16 -0400 Received: from mail.kernel.org ([198.145.29.99]:59338 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391637AbgJOTbI (ORCPT ); Thu, 15 Oct 2020 15:31:08 -0400 Received: from localhost (170.sub-72-107-125.myvzw.com [72.107.125.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 244E8206E5; Thu, 15 Oct 2020 19:31:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1602790267; bh=fzYC92L7X4Hn79/HZ6Iz7ZTmwjYRvUEuCXRY/FDqu2w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JsL/0LmeXSXmTGebejjynw2LN2Oeo1dZQ5X2SVGAh/ufTBdgiBJl54wNHMce11Enj OgGc6UuBnEC3+14lFzeJ7q+IUwkxvk3TPtKXfCTLu9RV3ygTZVZNUPZvgha93cvEwt gQK4/YMv2847CZBFj47Elb9WPQa9yaqTbvfZP7rg= From: Bjorn Helgaas To: "Saheed O . Bolarinwa" Cc: Puranjay Mohan , Rajat Jain , Kai-Heng Feng , Yicong Yang , Heiner Kallweit , linux-pci@vger.kernel.org, Bjorn Helgaas Subject: [PATCH v3 10/12] PCI/ASPM: Pass L1SS Capabilities value, not struct aspm_register_info Date: Thu, 15 Oct 2020 14:30:37 -0500 Message-Id: <20201015193039.12585-11-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201015193039.12585-1-helgaas@kernel.org> References: <20201015193039.12585-1-helgaas@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bjorn Helgaas aspm_calc_l1ss_info() needs only the L1SS Capabilities. It doesn't need anything else from struct aspm_register_info, so pass only the Capabilities value. No functional change intended. Signed-off-by: Bjorn Helgaas --- drivers/pci/pcie/aspm.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 896f6c0b08c6..8c6b976d8b50 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -476,8 +476,7 @@ static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos, /* Calculate L1.2 PM substate timing parameters */ static void aspm_calc_l1ss_info(struct pcie_link_state *link, - struct aspm_register_info *upreg, - struct aspm_register_info *dwreg) + u32 parent_l1ss_cap, u32 child_l1ss_cap) { struct pci_dev *child = link->downstream, *parent = link->pdev; u32 val1, val2, scale1, scale2; @@ -489,15 +488,15 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, return; /* Choose the greater of the two Port Common_Mode_Restore_Times */ - val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; - val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; + val1 = (parent_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; + val2 = (child_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; t_common_mode = max(val1, val2); /* Choose the greater of the two Port T_POWER_ON times */ - val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19; - scale1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16; - val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19; - scale2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16; + val1 = (parent_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19; + scale1 = (parent_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16; + val2 = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19; + scale2 = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16; if (calc_l1ss_pwron(parent, scale1, val1) > calc_l1ss_pwron(child, scale2, val2)) { @@ -624,7 +623,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM; if (link->aspm_support & ASPM_STATE_L1SS) - aspm_calc_l1ss_info(link, &upreg, &dwreg); + aspm_calc_l1ss_info(link, upreg.l1ss_cap, dwreg.l1ss_cap); /* Save default state */ link->aspm_default = link->aspm_enabled; From patchwork Thu Oct 15 19:30:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 1382887 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=default header.b=N9/nhA1G; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CBzsz5th4z9sTm for ; Fri, 16 Oct 2020 06:31:19 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391674AbgJOTbR (ORCPT ); Thu, 15 Oct 2020 15:31:17 -0400 Received: from mail.kernel.org ([198.145.29.99]:59410 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391669AbgJOTbK (ORCPT ); Thu, 15 Oct 2020 15:31:10 -0400 Received: from localhost (170.sub-72-107-125.myvzw.com [72.107.125.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 020812072D; Thu, 15 Oct 2020 19:31:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1602790269; bh=JutDbIjNo+0FiqISzqPkyw0jmSNipIeACOXqS9f0RQs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=N9/nhA1GbVN+TnsOFMWZHvlA6cVcArYawDwceJL18WEmftWVkXFnoT8wE+585yVer 1+BIRrxxTMyGHppvRyFvO7OaH4qrfA9KZQB2rVB4GEXv/ihoRcD3EjgGmgZ8MERIVR sLoWa5/gYlaOft+U6f6HXpXhwcEmTlR9bvKRKHUo= From: Bjorn Helgaas To: "Saheed O . Bolarinwa" Cc: Puranjay Mohan , Rajat Jain , Kai-Heng Feng , Yicong Yang , Heiner Kallweit , linux-pci@vger.kernel.org, Bjorn Helgaas Subject: [PATCH v3 11/12] PCI/ASPM: Remove struct aspm_register_info.l1ss_cap Date: Thu, 15 Oct 2020 14:30:38 -0500 Message-Id: <20201015193039.12585-12-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201015193039.12585-1-helgaas@kernel.org> References: <20201015193039.12585-1-helgaas@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: "Saheed O. Bolarinwa" Previously we stored the L1SS Capabilities value in the struct aspm_register_info. We only need this information in one place, so read it there and remove struct aspm_register_info completely, since it's now empty. No functional change intended. [bhelgaas: split up, don't cache l1ss_cap in pci_dev] Signed-off-by: Saheed O. Bolarinwa Signed-off-by: Bjorn Helgaas --- drivers/pci/pcie/aspm.c | 53 ++++++++++++++++------------------------- 1 file changed, 21 insertions(+), 32 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 8c6b976d8b50..d76f23908d67 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -382,26 +382,6 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) } } -struct aspm_register_info { - /* L1 substates */ - u32 l1ss_cap; -}; - -static void pcie_get_aspm_reg(struct pci_dev *pdev, - struct aspm_register_info *info) -{ - /* Read L1 PM substate capabilities */ - info->l1ss_cap = 0; - - if (!pdev->l1ss) - return; - - pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CAP, - &info->l1ss_cap); - if (!(info->l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) - info->l1ss_cap = 0; -} - static void pcie_aspm_check_latency(struct pci_dev *endpoint) { u32 latency, l1_switch_latency = 0; @@ -527,9 +507,9 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) struct pci_dev *child = link->downstream, *parent = link->pdev; u32 parent_lnkcap, child_lnkcap; u16 parent_lnkctl, child_lnkctl; + u32 parent_l1ss_cap, child_l1ss_cap; u32 parent_l1ss_ctl1 = 0, child_l1ss_ctl1 = 0; struct pci_bus *linkbus = parent->subordinate; - struct aspm_register_info upreg, dwreg; if (blacklist) { /* Set enabled/disable so that we will disable ASPM later */ @@ -560,8 +540,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap); pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl); pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl); - pcie_get_aspm_reg(parent, &upreg); - pcie_get_aspm_reg(child, &dwreg); /* * Setup L0s state @@ -589,27 +567,38 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) link->latency_up.l1 = calc_l1_latency(parent_lnkcap); link->latency_dw.l1 = calc_l1_latency(child_lnkcap); - /* Setup L1 substate + /* Setup L1 substate */ + pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP, + &parent_l1ss_cap); + pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP, + &child_l1ss_cap); + + if (!(parent_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) + parent_l1ss_cap = 0; + if (!(child_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) + child_l1ss_cap = 0; + + /* * If we don't have LTR for the entire path from the Root Complex * to this device, we can't use ASPM L1.2 because it relies on the * LTR_L1.2_THRESHOLD. See PCIe r4.0, secs 5.5.4, 6.18. */ if (!child->ltr_path) - dwreg.l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2; + child_l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2; - if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1) + if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1) link->aspm_support |= ASPM_STATE_L1_1; - if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2) + if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2) link->aspm_support |= ASPM_STATE_L1_2; - if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1) + if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1) link->aspm_support |= ASPM_STATE_L1_1_PCIPM; - if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2) + if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2) link->aspm_support |= ASPM_STATE_L1_2_PCIPM; - if (upreg.l1ss_cap) + if (parent_l1ss_cap) pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, &parent_l1ss_ctl1); - if (dwreg.l1ss_cap) + if (child_l1ss_cap) pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, &child_l1ss_ctl1); @@ -623,7 +612,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM; if (link->aspm_support & ASPM_STATE_L1SS) - aspm_calc_l1ss_info(link, upreg.l1ss_cap, dwreg.l1ss_cap); + aspm_calc_l1ss_info(link, parent_l1ss_cap, child_l1ss_cap); /* Save default state */ link->aspm_default = link->aspm_enabled; From patchwork Thu Oct 15 19:30:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 1382886 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=default header.b=LCykd/HY; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CBzsz2T1zz9sTL for ; Fri, 16 Oct 2020 06:31:19 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391637AbgJOTbQ (ORCPT ); Thu, 15 Oct 2020 15:31:16 -0400 Received: from mail.kernel.org ([198.145.29.99]:59474 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391674AbgJOTbQ (ORCPT ); Thu, 15 Oct 2020 15:31:16 -0400 Received: from localhost (170.sub-72-107-125.myvzw.com [72.107.125.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id D4260206ED; Thu, 15 Oct 2020 19:31:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1602790271; bh=20VF0dUejZGIec0Iens0CsGAB0kFAAjoztVbOd3j29w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LCykd/HYdHRQgMN6Z+vuCV6bXrA0lC1BBANa57dhbchwVjudkNCYwplm+magj7Kwy MJxkr7hZKfJm9cFpDjvtm/bM/ItIombX6pdK1SWqUrDdKKCTv1vxdjEtAMCjzxQO3h rGusy83lEHoHMhE/YaXOrJhK1fAV0SGbM6iLsGQk= From: Bjorn Helgaas To: "Saheed O . Bolarinwa" Cc: Puranjay Mohan , Rajat Jain , Kai-Heng Feng , Yicong Yang , Heiner Kallweit , linux-pci@vger.kernel.org, Bjorn Helgaas Subject: [PATCH v3 12/12] PCI/ASPM: Remove struct pcie_link_state.l1ss Date: Thu, 15 Oct 2020 14:30:39 -0500 Message-Id: <20201015193039.12585-13-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201015193039.12585-1-helgaas@kernel.org> References: <20201015193039.12585-1-helgaas@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: "Saheed O. Bolarinwa" Previously we computed L1.2 parameters in the enumeration path, saved them in struct pcie_link_state.l1ss, and programmed them into the devices whenever we enabled or disabled L1.2 on the link. But these parameters are constant and don't need to be updated when enabling/disabling L1.2. Compute and program the L1.2 parameters once during enumeration and remove the struct pcie_link_state.l1ss member. No functional change intended. [bhelgaas: rework to program L1.2 parameters during enumeration] Signed-off-by: Saheed O. Bolarinwa Signed-off-by: Bjorn Helgaas --- drivers/pci/pcie/aspm.c | 55 +++++++++++++++-------------------------- 1 file changed, 20 insertions(+), 35 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index d76f23908d67..361eaa0c615d 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -74,12 +74,6 @@ struct pcie_link_state { * has one slot under it, so at most there are 8 functions. */ struct aspm_latency acceptable[8]; - - /* L1 PM Substate info */ - struct { - u32 ctl1; /* value to be programmed in ctl1 */ - u32 ctl2; /* value to be programmed in ctl2 */ - } l1ss; }; static int aspm_disabled, aspm_force; @@ -461,8 +455,7 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, struct pci_dev *child = link->downstream, *parent = link->pdev; u32 val1, val2, scale1, scale2; u32 t_common_mode, t_power_on, l1_2_threshold, scale, value; - - link->l1ss.ctl1 = link->l1ss.ctl2 = 0; + u32 ctl1 = 0, ctl2 = 0; if (!(link->aspm_support & ASPM_STATE_L1_2_MASK)) return; @@ -480,10 +473,10 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, if (calc_l1ss_pwron(parent, scale1, val1) > calc_l1ss_pwron(child, scale2, val2)) { - link->l1ss.ctl2 |= scale1 | (val1 << 3); + ctl2 |= scale1 | (val1 << 3); t_power_on = calc_l1ss_pwron(parent, scale1, val1); } else { - link->l1ss.ctl2 |= scale2 | (val2 << 3); + ctl2 |= scale2 | (val2 << 3); t_power_on = calc_l1ss_pwron(child, scale2, val2); } @@ -499,7 +492,23 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, */ l1_2_threshold = 2 + 4 + t_common_mode + t_power_on; encode_l12_threshold(l1_2_threshold, &scale, &value); - link->l1ss.ctl1 |= t_common_mode << 8 | scale << 29 | value << 16; + ctl1 |= t_common_mode << 8 | scale << 29 | value << 16; + + /* Program T_POWER_ON times in both ports */ + pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, ctl2); + pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2); + + /* Program Common_Mode_Restore_Time in upstream device */ + pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, + PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1); + + /* Program LTR_L1.2_THRESHOLD time in both ports */ + pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, + PCI_L1SS_CTL1_LTR_L12_TH_VALUE | + PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1); + pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, + PCI_L1SS_CTL1_LTR_L12_TH_VALUE | + PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1); } static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) @@ -679,30 +688,6 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) PCI_EXP_LNKCTL_ASPM_L1, 0); } - if (enable_req & ASPM_STATE_L1_2_MASK) { - - /* Program T_POWER_ON times in both ports */ - pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, - link->l1ss.ctl2); - pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, - link->l1ss.ctl2); - - /* Program Common_Mode_Restore_Time in upstream device */ - pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, - PCI_L1SS_CTL1_CM_RESTORE_TIME, - link->l1ss.ctl1); - - /* Program LTR_L1.2_THRESHOLD time in both ports */ - pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, - PCI_L1SS_CTL1_LTR_L12_TH_VALUE | - PCI_L1SS_CTL1_LTR_L12_TH_SCALE, - link->l1ss.ctl1); - pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, - PCI_L1SS_CTL1_LTR_L12_TH_VALUE | - PCI_L1SS_CTL1_LTR_L12_TH_SCALE, - link->l1ss.ctl1); - } - val = 0; if (state & ASPM_STATE_L1_1) val |= PCI_L1SS_CTL1_ASPM_L1_1;