From patchwork Mon Oct 12 06:12:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen (ThunderTown)" X-Patchwork-Id: 1380636 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=huawei.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4C8pJ437d3z9sTq for ; Mon, 12 Oct 2020 17:12:52 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727263AbgJLGMt (ORCPT ); Mon, 12 Oct 2020 02:12:49 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:33556 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727214AbgJLGMs (ORCPT ); Mon, 12 Oct 2020 02:12:48 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id C60512300DE390C4CF61; Mon, 12 Oct 2020 14:12:45 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.134) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Mon, 12 Oct 2020 14:12:40 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH v2 09/10] dt-bindings: arm: hisilicon: add missing properties into sysctrl.yaml Date: Mon, 12 Oct 2020 14:12:24 +0800 Message-ID: <20201012061225.1597-10-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20201012061225.1597-1-thunder.leizhen@huawei.com> References: <20201012061225.1597-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.134] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add properties: #reset-cells, #address-cells, #size-cells and ranges. Due to the Hisilicon system controller node may contains child nodes, change the value of "additionalProperties" from "false" to "type: object". The examples have also been updated. Signed-off-by: Zhen Lei --- .../bindings/arm/hisilicon/controller/sysctrl.yaml | 28 +++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/sysctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/sysctrl.yaml index 449140f89ddbc3b..5a53d433b6f0891 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/sysctrl.yaml +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/sysctrl.yaml @@ -71,21 +71,43 @@ properties: '#clock-cells': const: 1 + '#reset-cells': + const: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: true + required: - compatible - reg -additionalProperties: false +additionalProperties: + type: object examples: - | /* Hisilicon system controller */ - system-controller@fc802000 { + system-controller@802000 { compatible = "hisilicon,sysctrl", "syscon"; - reg = <0xfc802000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x802000 0x1000>; + reg = <0x802000 0x1000>; + smp-offset = <0x31c>; resume-offset = <0x308>; reboot-offset = <0x4>; + + clock: clock@0 { + compatible = "hisilicon,hi3620-clock"; + reg = <0 0x10000>; + #clock-cells = <1>; + }; }; /* HiP01 system controller */ From patchwork Mon Oct 12 06:12:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen (ThunderTown)" X-Patchwork-Id: 1380639 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=huawei.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4C8pJj2VS6z9sTf for ; Mon, 12 Oct 2020 17:13:25 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727386AbgJLGNE (ORCPT ); Mon, 12 Oct 2020 02:13:04 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:45554 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727337AbgJLGM5 (ORCPT ); Mon, 12 Oct 2020 02:12:57 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id C3802C80DC9FBB15F377; Mon, 12 Oct 2020 14:12:50 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.134) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Mon, 12 Oct 2020 14:12:40 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH v2 10/10] dt-bindings: arm: hisilicon: add missing properties into cpuctrl.yaml Date: Mon, 12 Oct 2020 14:12:25 +0800 Message-ID: <20201012061225.1597-11-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20201012061225.1597-1-thunder.leizhen@huawei.com> References: <20201012061225.1597-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.134] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add properties: #address-cells, #size-cells and ranges. Due to the Hisilicon CPU controller node may contains child nodes, change the value of "additionalProperties" from "false" to "type: object". The corresponding examples are also added. Signed-off-by: Zhen Lei --- .../bindings/arm/hisilicon/controller/cpuctrl.yaml | 27 +++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml index f6a314db3a59416..528dad4cde3cd19 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml @@ -21,9 +21,34 @@ properties: reg: maxItems: 1 + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + required: - compatible - reg -additionalProperties: false +additionalProperties: + type: object + +examples: + - | + cpuctrl@a22000 { + compatible = "hisilicon,cpuctrl"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00a22000 0x2000>; + ranges = <0 0x00a22000 0x2000>; + + clock: clock@0 { + compatible = "hisilicon,hix5hd2-clock"; + reg = <0 0x2000>; + #clock-cells = <1>; + }; + }; ...