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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id l6sm117535qkb.56.2020.09.29.07.18.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2020 07:18:47 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Bin Meng , Rick Chen , Heinrich Schuchardt , Sean Anderson , Damien Le Moal , Lukasz Majewski Subject: [PATCH 01/10] clk: k210: Fix PLLs not being enabled Date: Tue, 29 Sep 2020 10:18:26 -0400 Message-Id: <20200929141835.38435-2-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200929141835.38435-1-seanga2@gmail.com> References: <20200929141835.38435-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean After starting or setting the rate of a PLL, the enable bit must be set. This fixes a bug where the AI ram would not be accessible, because it requires PLL1 to be running. Signed-off-by: Sean Anderson --- drivers/clk/kendryte/pll.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c index ab6d75d585..f198920113 100644 --- a/drivers/clk/kendryte/pll.c +++ b/drivers/clk/kendryte/pll.c @@ -531,6 +531,7 @@ static int k210_pll_enable(struct clk *clk) k210_pll_waitfor_lock(pll); reg &= ~K210_PLL_BYPASS; + reg |= K210_PLL_EN; writel(reg, pll->reg); return 0; @@ -550,6 +551,7 @@ static int k210_pll_disable(struct clk *clk) writel(reg, pll->reg); reg &= ~K210_PLL_PWRD; + reg &= ~K210_PLL_EN; writel(reg, pll->reg); return 0; } From patchwork Tue Sep 29 14:18:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 1373469 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=dXfgUy/3; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C11jS3pVYz9ryj for ; Wed, 30 Sep 2020 00:19:24 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3FBBA8174F; Tue, 29 Sep 2020 16:18:58 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="dXfgUy/3"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id F2E2781996; Tue, 29 Sep 2020 16:18:52 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-qv1-xf43.google.com (mail-qv1-xf43.google.com [IPv6:2607:f8b0:4864:20::f43]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C1ECD81996 for ; Tue, 29 Sep 2020 16:18:49 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=seanga2@gmail.com Received: by mail-qv1-xf43.google.com with SMTP id j10so2317576qvk.11 for ; Tue, 29 Sep 2020 07:18:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=p7k1YAcG6ZKjr6WOhBwRUYjJMsgCvz+WnO7//X3Y0XQ=; b=dXfgUy/35ib+EQhrXulikqR0q3YoI5gFpaykXCPcHM+WAF7plLBlOUyZhm58kflecn vJXsD/miRGbbzQfdhFlTbAVAbH+BQLoC+fnl2GYHQPTXQast4fM63gfZet/T+g2/GqJa UiP3d/Mpt2iopzJltE4jkV09DnGkVi8UhCKKZRg4C2MRpdjZ3B8RsveCCI7iJ4g7R+bm li8E8iYpms1a/nKeNzRnjd7mea7WMMDev0CnIE0iGHU2kn2CGA3KKHmKljo6iaLLQGYG xhrHU/hmyrDuedvJrYI7XqtS4pNfIGDDHDQipQd15+UnJMDeHLtC/iV/CHfWsmDVaKVw Er1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=p7k1YAcG6ZKjr6WOhBwRUYjJMsgCvz+WnO7//X3Y0XQ=; b=HJFilE6e4+4TKN9oRkP+KHnY9K7YH5CzaoT2nGNRoRUG/lh+IK6xiVXK1d5SBXJ1aX OazQYHTW7bp4BFqw6JbqPrakc91xYEr/FACJAIjqUqg16EGOGCZiL1HrQI0SaCpczjPi +HjqzYvRyEouhhi7qez9Rg35DCCgfEPaVWhH7L4vAo4q+nkFf5p/vyn1qsk5aR8FRGj6 tMy2XGwXO94Em/4vWmMT1krB7/cG5zlZ5b/Xp9ytPjB0CbFuxUl4xfYNsUjDzP83wzkH 59fnkw1FzPeDGG2P09zGqVIC6bcwsaL0r8Lmi/xIxqwyAPHfv8Nd/rkRMv0e/4bvmhFr SiYA== X-Gm-Message-State: AOAM533pjAxCWg7A/yWtKL47f+PJXbXeDrCEmsu0rejNeeyXyj4Qylht bQEHwgw8PlX4OZHxdNEfPK8ZpHRSKKNt1w== X-Google-Smtp-Source: ABdhPJynPa9n0W8ivuRNxJBSk89FA3ovYcpjrFe1Om/vReT3hLI+dajBN6OtL/hHJWj2raGBYENTRA== X-Received: by 2002:a0c:8c4c:: with SMTP id o12mr4388959qvb.46.1601389128531; Tue, 29 Sep 2020 07:18:48 -0700 (PDT) Received: from godwin.fios-router.home (pool-108-51-35-162.washdc.fios.verizon.net. [108.51.35.162]) by smtp.gmail.com with ESMTPSA id l6sm117535qkb.56.2020.09.29.07.18.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2020 07:18:48 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Bin Meng , Rick Chen , Heinrich Schuchardt , Sean Anderson , Lukasz Majewski Subject: [PATCH 02/10] clk: Add support for the k210 clock driver pre-relocation Date: Tue, 29 Sep 2020 10:18:27 -0400 Message-Id: <20200929141835.38435-3-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200929141835.38435-1-seanga2@gmail.com> References: <20200929141835.38435-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Variables which had previously been stored in .bss are moved to .data. In addition, probed needs to be reset when the clock driver is re-bound post-relocation. Signed-off-by: Sean Anderson --- drivers/clk/kendryte/clk.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c index 981b3b7699..7d179d755e 100644 --- a/drivers/clk/kendryte/clk.c +++ b/drivers/clk/kendryte/clk.c @@ -347,9 +347,7 @@ static const struct k210_comp_params k210_comps[] = { #undef COMP_NOMUX_ID #undef COMP_LIST -static struct clk *k210_bypass_children = { - NULL, -}; +static struct clk __section(.data) *k210_bypass_children; /* Helper functions to create sub-clocks */ static struct clk_mux *k210_create_mux(const struct k210_mux_params *params, @@ -476,7 +474,14 @@ cleanup_mux: return comp; } -static bool probed; +static bool __section(.data) probed; + +/* reset probed so we will probe again post-relocation */ +static int k210_clk_bind(struct udevice *dev) +{ + probed = false; + return 0; +} static int k210_clk_probe(struct udevice *dev) { @@ -659,5 +664,6 @@ U_BOOT_DRIVER(k210_clk) = { .id = UCLASS_CLK, .of_match = k210_clk_ids, .ops = &k210_clk_ops, + .bind = k210_clk_bind, .probe = k210_clk_probe, }; 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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id l6sm117535qkb.56.2020.09.29.07.18.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2020 07:18:49 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Bin Meng , Rick Chen , Heinrich Schuchardt , Sean Anderson Subject: [PATCH 03/10] riscv: Enable some devices pre-relocation Date: Tue, 29 Sep 2020 10:18:28 -0400 Message-Id: <20200929141835.38435-4-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200929141835.38435-1-seanga2@gmail.com> References: <20200929141835.38435-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean These devices are necessary for the clock driver, which is required by the sram driver, to run pre-relocation. Signed-off-by: Sean Anderson --- arch/riscv/dts/k210.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi index 2546c7d4e0..f7843985aa 100644 --- a/arch/riscv/dts/k210.dtsi +++ b/arch/riscv/dts/k210.dtsi @@ -88,6 +88,7 @@ <&sysclk K210_CLK_SRAM1>, <&sysclk K210_CLK_PLL1>; clock-names = "sram0", "sram1", "airam"; + u-boot,dm-pre-reloc; }; reserved-memory { @@ -106,6 +107,7 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; + u-boot,dm-pre-reloc; }; }; @@ -490,11 +492,13 @@ "syscon", "simple-mfd"; reg = <0x50440000 0x100>; reg-io-width = <4>; + u-boot,dm-pre-reloc; sysclk: clock-controller { #clock-cells = <1>; compatible = "kendryte,k210-clk"; clocks = <&in0>; + u-boot,dm-pre-reloc; }; sysrst: reset-controller { From patchwork Tue Sep 29 14:18:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 1373471 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=eDBe/bZB; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C11jz1kcfz9ryj for ; Wed, 30 Sep 2020 00:19:51 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id EA8F782304; Tue, 29 Sep 2020 16:19:02 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="eDBe/bZB"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id E221D821A8; Tue, 29 Sep 2020 16:18:54 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-qt1-x842.google.com (mail-qt1-x842.google.com [IPv6:2607:f8b0:4864:20::842]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id E7F468174F for ; Tue, 29 Sep 2020 16:18:51 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=seanga2@gmail.com Received: by mail-qt1-x842.google.com with SMTP id c18so3647637qtw.5 for ; Tue, 29 Sep 2020 07:18:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GzpRSpo3x1nxnExJnj0Tfxypqak9TnBoXWf8IJKH0v8=; b=eDBe/bZBCZafL24/yAH4Cg1NEGy1o+JvX72kLjVjbnY7mKCjcTTK4A0JYr23VZFYy1 fEBO/98Db3r48w4QbVy6/A+oSLYVSEZP0o0FJ/SlNTyOOOCqLBoLhsXnxhTZ7GQnRLY/ LKdfVXa8esDkGR3YWULM4uas74ywhrGuQHetx/zGyMGijTwYzTmprOMWCUPpJOqOZPOP wsMDNchR3BTW8wztk5p85Yf1Q5vANHwqcyP22n6l+P68eVa0nbKPk3NXM5fckS4AOMCQ 3vpc7iyEHJBGKQusOSiZe5GZ8ukION/XUTSvi/0KDP5ye+H4LuMAimtIn9J06xsvjlUU ZuXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GzpRSpo3x1nxnExJnj0Tfxypqak9TnBoXWf8IJKH0v8=; b=hsxfJ2ILb0NCmLyn0ev8UGRaVRfQdGMs5CMaur6/j6YXNoDix3f8liVw7qGcujmohe 568+ZmDJKS3BE3fstpB9z6g2fAZxCtNff959eTimjKAWkmivUXiuCO8gUNcIhQ+1T3T1 vGrZcLxu85X7C63n+uuS9hBdZrZEt59e2ANE8eGrz0aMKsLUhYZpYYoTvY3XaWP5A0hk JHO62Wb1ks/3igqN5B5sehDmApTuMdXct0AAtV54MUbz7eUQrokJUWSMcifmaLjNxP9w KnL+fWLIb69FpMfMxdl7lARp3b3yH6Z6n+lw/z65OTYAZGWqt5P/yHF+zqWhNlZO6pg7 +upQ== X-Gm-Message-State: AOAM5316/v0OpeU6nzr+gEU9Dyq/oMV7l/cTS6H2N4fHXo27BIDzg1JB EVQKeL4C19vKQjlg0fzciPFu87xlQiqvzg== X-Google-Smtp-Source: ABdhPJxuOE++t3B5PuMJZgwzAuNesw+M39VHS6mqnWWaRj74XRWQYNgCwnPl2DFr4TC11PzsCLNYFA== X-Received: by 2002:ac8:4052:: with SMTP id j18mr3497089qtl.352.1601389130592; Tue, 29 Sep 2020 07:18:50 -0700 (PDT) Received: from godwin.fios-router.home (pool-108-51-35-162.washdc.fios.verizon.net. [108.51.35.162]) by smtp.gmail.com with ESMTPSA id l6sm117535qkb.56.2020.09.29.07.18.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2020 07:18:50 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Bin Meng , Rick Chen , Heinrich Schuchardt , Sean Anderson , Simon Glass Subject: [PATCH 04/10] lib: fdt: Add fdtdec_setup_mem_size_base_highest Date: Tue, 29 Sep 2020 10:18:29 -0400 Message-Id: <20200929141835.38435-5-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200929141835.38435-1-seanga2@gmail.com> References: <20200929141835.38435-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean This is very similar to fdtdec_setup_mem_size_base_lowest, except we pick the highest ram bank, instead of the lowest. This is helpful for boards which use separate but contiguous ram banks, as it leaves the most space for loading programs. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- include/fdtdec.h | 19 ++++++++++++++++++- lib/fdtdec.c | 34 +++++++++++++++++++++++++++++----- 2 files changed, 47 insertions(+), 6 deletions(-) diff --git a/include/fdtdec.h b/include/fdtdec.h index 152eb07b9e..0ccea1a77d 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -944,7 +944,7 @@ int fdtdec_setup_mem_size_base(void); * gd->ram_start by lowest available memory base * * Decode the /memory 'reg' property to determine the lowest start of the memory - * bank bank and populate the global data with it. + * bank and populate the global data with it. * * This function should be called from a boards dram_init(). This helper * function allows for boards to query the device tree for DRAM size and start @@ -956,6 +956,23 @@ int fdtdec_setup_mem_size_base(void); */ int fdtdec_setup_mem_size_base_lowest(void); +/** + * fdtdec_setup_mem_size_base_highest() - decode and setup gd->ram_size and + * gd->ram_start by highest available memory top + * + * Decode the /memory 'reg' property to determine the highest end of the memory + * bank and populate the global data with it. + * + * This function should be called from a boards dram_init(). This helper + * function allows for boards to query the device tree for DRAM size and start + * address instead of hard coding the value in the case where the memory size + * and start address cannot be detected automatically. + * + * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or + * invalid + */ +int fdtdec_setup_mem_size_base_highest(void); + /** * fdtdec_setup_memory_banksize() - decode and populate gd->bd->bi_dram * diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 5f41f58a63..439ab6525c 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1125,7 +1125,7 @@ int fdtdec_setup_memory_banksize(void) return 0; } -int fdtdec_setup_mem_size_base_lowest(void) +static int fdtdec_setup_mem_size_base_superlative(bool lowest) { int bank, ret, reg = 0; struct resource res; @@ -1133,7 +1133,16 @@ int fdtdec_setup_mem_size_base_lowest(void) phys_size_t size; ofnode mem = ofnode_null(); - gd->ram_base = (unsigned long)~0; + /* + * Size must be 1 so we don't underflow when doing the subtraction below + * when lowest = false. Hopefully any real ram banks will have a greater + * size :) + */ + gd->ram_size = 1; + if (lowest) + gd->ram_base = (unsigned long)~0; + else + gd->ram_base = 0; mem = get_next_memory_node(mem); if (!ofnode_valid(mem)) { @@ -1160,16 +1169,31 @@ int fdtdec_setup_mem_size_base_lowest(void) base = (unsigned long)res.start; size = (phys_size_t)(res.end - res.start + 1); - if (gd->ram_base > base && size) { + if (!size) + continue; + + if ((lowest && gd->ram_base > base) || + (!lowest && gd->ram_base + gd->ram_size - 1 < res.end)) { gd->ram_base = base; gd->ram_size = size; - debug("%s: Initial DRAM base %lx size %lx\n", - __func__, base, (unsigned long)size); } } + if (gd->ram_size) + debug("%s: Initial DRAM base %lx size %lx\n", __func__, + gd->ram_base, (unsigned long)gd->ram_size); return 0; } + +int fdtdec_setup_mem_size_base_lowest(void) +{ + return fdtdec_setup_mem_size_base_superlative(true); +} + +int fdtdec_setup_mem_size_base_highest(void) +{ + return fdtdec_setup_mem_size_base_superlative(false); +} #endif #if CONFIG_IS_ENABLED(MULTI_DTB_FIT) From patchwork Tue Sep 29 14:18:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 1373472 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=afNo/pWC; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C11kH6thPz9ryj for ; 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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id l6sm117535qkb.56.2020.09.29.07.18.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2020 07:18:51 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Bin Meng , Rick Chen , Heinrich Schuchardt , Sean Anderson , Simon Glass Subject: [PATCH 05/10] test: Add a test for fdtdec_setup_mem_size_base et al. Date: Tue, 29 Sep 2020 10:18:30 -0400 Message-Id: <20200929141835.38435-6-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200929141835.38435-1-seanga2@gmail.com> References: <20200929141835.38435-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean This adds a test for the various methods of extracting ram_base and ram_size from a device tree. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- arch/sandbox/dts/test.dts | 12 ++++++++++ configs/sandbox64_defconfig | 2 +- configs/sandbox_defconfig | 2 +- configs/sandbox_flattree_defconfig | 2 +- test/dm/fdtdec.c | 38 ++++++++++++++++++++++++++++++ 5 files changed, 53 insertions(+), 3 deletions(-) diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 9f45c48e4e..e98f0cbe25 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -1122,6 +1122,18 @@ resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>; reset-names = "valid", "no_mask", "out_of_range"; }; + + memory@0000 { + device_type = "memory"; + reg = <0x1000 0x2000>, + <0x0000 0x1000>; + }; + + memory@8000 { + device_type = "memory"; + reg = <0x8000 0x0000>, + <0x4000 0x3000>; + }; }; #include "sandbox_pmic.dtsi" diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index c3ca796d51..6324961cf1 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -1,5 +1,5 @@ CONFIG_SYS_TEXT_BASE=0 -CONFIG_NR_DRAM_BANKS=1 +CONFIG_NR_DRAM_BANKS=4 CONFIG_ENV_SIZE=0x2000 CONFIG_PRE_CON_BUF_ADDR=0x100000 CONFIG_BOOTSTAGE_STASH_ADDR=0x0 diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 6e9f029cc9..20718d26c8 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -1,5 +1,5 @@ CONFIG_SYS_TEXT_BASE=0 -CONFIG_NR_DRAM_BANKS=1 +CONFIG_NR_DRAM_BANKS=4 CONFIG_ENV_SIZE=0x2000 CONFIG_PRE_CON_BUF_ADDR=0xf0000 CONFIG_BOOTSTAGE_STASH_ADDR=0x0 diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index dd93167e1b..a4941b54d3 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -1,5 +1,5 @@ CONFIG_SYS_TEXT_BASE=0 -CONFIG_NR_DRAM_BANKS=1 +CONFIG_NR_DRAM_BANKS=4 CONFIG_ENV_SIZE=0x2000 CONFIG_BOOTSTAGE_STASH_ADDR=0x0 CONFIG_DEFAULT_DEVICE_TREE="sandbox" diff --git a/test/dm/fdtdec.c b/test/dm/fdtdec.c index 716993f706..5fcda1cd13 100644 --- a/test/dm/fdtdec.c +++ b/test/dm/fdtdec.c @@ -128,3 +128,41 @@ static int dm_test_fdtdec_add_reserved_memory(struct unit_test_state *uts) } DM_TEST(dm_test_fdtdec_add_reserved_memory, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE); + +static int _dm_test_fdtdec_setup_mem(struct unit_test_state *uts) +{ + ut_assertok(fdtdec_setup_mem_size_base()); + ut_asserteq(0x1000, gd->ram_base); + ut_asserteq(0x2000, gd->ram_size); + + ut_assertok(fdtdec_setup_mem_size_base_lowest()); + ut_asserteq(0x0000, gd->ram_base); + ut_asserteq(0x1000, gd->ram_size); + + ut_assertok(fdtdec_setup_mem_size_base_highest()); + ut_asserteq(0x4000, gd->ram_base); + ut_asserteq(0x3000, gd->ram_size); + + return 0; +} + +/* + * We need to wrap the actual test so that we don't overwrite the ram parameters + * for the rest of U-Boot + */ +static int dm_test_fdtdec_setup_mem(struct unit_test_state *uts) +{ + int ret; + unsigned long base, size; + + base = gd->ram_base; + size = gd->ram_size; + + ret = _dm_test_fdtdec_setup_mem(uts); + + gd->ram_base = base; + gd->ram_size = size; + + return ret; +} +DM_TEST(dm_test_fdtdec_setup_mem, UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE); From patchwork Tue Sep 29 14:18:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 1373473 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id l6sm117535qkb.56.2020.09.29.07.18.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2020 07:18:52 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Bin Meng , Rick Chen , Heinrich Schuchardt , Sean Anderson , Simon Glass Subject: [PATCH 06/10] ram: Add driver for K210 SRAM Date: Tue, 29 Sep 2020 10:18:31 -0400 Message-Id: <20200929141835.38435-7-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200929141835.38435-1-seanga2@gmail.com> References: <20200929141835.38435-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean This adds a driver to handle enabling the clock for the AI SRAM. This was previously done in board_init, but it needs to happen before relocation now. An alternative would be to move this to board_init_early_f, but by doing it this way we can use clk_bulk. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- MAINTAINERS | 1 + drivers/ram/Kconfig | 7 ++++++ drivers/ram/Makefile | 1 + drivers/ram/kendryte.c | 56 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 65 insertions(+) create mode 100644 drivers/ram/kendryte.c diff --git a/MAINTAINERS b/MAINTAINERS index 7e46470c70..70e01e5e7a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -928,6 +928,7 @@ M: Sean Anderson S: Maintained F: doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt F: drivers/clk/kendryte/ +F: drivers/ram/kendryte.c F: include/kendryte/ RNG diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 7e6e981897..faeacdf014 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -73,6 +73,13 @@ config IMXRT_SDRAM to support external memories like sdram, psram & nand. This driver is for the sdram memory interface with the SEMC. +config K210_SRAM + bool "Enable Kendryte K210 SRAM support" + depends on RAM + help + The Kendryte K210 has three banks of SRAM. This driver does the + necessary initialization. + source "drivers/ram/rockchip/Kconfig" source "drivers/ram/sifive/Kconfig" source "drivers/ram/stm32mp1/Kconfig" diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index 769c9d6218..d36b955e00 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -19,3 +19,4 @@ obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/ obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o obj-$(CONFIG_RAM_SIFIVE) += sifive/ +obj-$(CONFIG_K210_SRAM) += kendryte.o diff --git a/drivers/ram/kendryte.c b/drivers/ram/kendryte.c new file mode 100644 index 0000000000..50818bf005 --- /dev/null +++ b/drivers/ram/kendryte.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Sean Anderson + */ + +#include +#include +#include +#include + +static int k210_sram_probe(struct udevice *dev) +{ + int ret; + struct clk_bulk clocks; + + /* Relocate as high as possible to leave more space to load payloads */ + ret = fdtdec_setup_mem_size_base_highest(); + if (ret) + return ret; + + /* Enable ram bank clocks */ + ret = clk_get_bulk(dev, &clocks); + if (ret) + return ret; + + ret = clk_enable_bulk(&clocks); + if (ret) + return ret; + + return 0; +} + +static int k210_sram_get_info(struct udevice *dev, struct ram_info *info) +{ + info->base = gd->ram_base; + info->size = gd->ram_size; + + return 0; +} + +static struct ram_ops k210_sram_ops = { + .get_info = k210_sram_get_info, +}; + +static const struct udevice_id k210_sram_ids[] = { + { .compatible = "kendryte,k210-sram" }, + { } +}; + +U_BOOT_DRIVER(fu540_ddr) = { + .name = "k210_sram", + .id = UCLASS_RAM, + .of_match = k210_sram_ids, + .ops = &k210_sram_ops, + .probe = k210_sram_probe, +}; From patchwork Tue Sep 29 14:18:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 1373474 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id l6sm117535qkb.56.2020.09.29.07.18.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2020 07:18:53 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Bin Meng , Rick Chen , Heinrich Schuchardt , Sean Anderson , Pragnesh Patel Subject: [PATCH 07/10] ram: sifive: Default to y only if compiling for fu540 Date: Tue, 29 Sep 2020 10:18:32 -0400 Message-Id: <20200929141835.38435-8-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200929141835.38435-1-seanga2@gmail.com> References: <20200929141835.38435-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Other RISC-V targets should not have RAM_SIFIVE enabled by default. Signed-off-by: Sean Anderson Reviewed-by: Pragnesh Patel --- drivers/ram/sifive/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ram/sifive/Kconfig b/drivers/ram/sifive/Kconfig index 6aca22ab2a..b24153d971 100644 --- a/drivers/ram/sifive/Kconfig +++ b/drivers/ram/sifive/Kconfig @@ -1,7 +1,7 @@ config RAM_SIFIVE bool "Ram drivers support for SiFive SoCs" depends on RAM && RISCV - default y + default y if TARGET_SIFIVE_FU540 help This enables support for ram drivers of SiFive SoCs. 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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id l6sm117535qkb.56.2020.09.29.07.18.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2020 07:18:54 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Bin Meng , Rick Chen , Heinrich Schuchardt , Sean Anderson Subject: [PATCH 08/10] riscv: Probe ram in dram_init Date: Tue, 29 Sep 2020 10:18:33 -0400 Message-Id: <20200929141835.38435-9-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200929141835.38435-1-seanga2@gmail.com> References: <20200929141835.38435-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean If CONFIG_RAM is enabled, use the ram device to get the base/size of memory. This provides an easy way for boards/cpus to hook into the dram_init logic, without needing to provide a second SYS_CPU. Signed-off-by: Sean Anderson --- arch/riscv/cpu/generic/dram.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c index 1dc77efeca..fbcd4ddf5f 100644 --- a/arch/riscv/cpu/generic/dram.c +++ b/arch/riscv/cpu/generic/dram.c @@ -4,15 +4,41 @@ */ #include +#include #include #include +#include +#include #include DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { +#if CONFIG_IS_ENABLED(RAM) + int ret; + struct ram_info info; + struct udevice *dev; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return ret; + } + + ret = ram_get_info(dev, &info); + if (ret) { + debug("Cannot get DRAM size: %d\n", ret); + return ret; + } + + gd->ram_base = info.base; + gd->ram_size = info.size; + + return 0; +#else return fdtdec_setup_mem_size_base(); +#endif } int dram_init_banksize(void) From patchwork Tue Sep 29 14:18:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 1373477 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id l6sm117535qkb.56.2020.09.29.07.18.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2020 07:18:55 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Bin Meng , Rick Chen , Heinrich Schuchardt , Sean Anderson Subject: [PATCH 09/10] riscv: Enable AI ram on K210 Date: Tue, 29 Sep 2020 10:18:34 -0400 Message-Id: <20200929141835.38435-10-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200929141835.38435-1-seanga2@gmail.com> References: <20200929141835.38435-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean CONFIG_SYS_SDRAM_{BASE,SIZE} are no longer necessary. The default get_effective_memsize will also work. The clock driver creates a bunch of devices, so we need to increase the pre-reloc malloc arena. Signed-off-by: Sean Anderson --- board/sipeed/maix/Kconfig | 2 ++ board/sipeed/maix/maix.c | 26 -------------------------- configs/sipeed_maix_bitm_defconfig | 1 + include/configs/sipeed-maix.h | 4 ---- 4 files changed, 3 insertions(+), 30 deletions(-) diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig index 0cdcd32adc..e456a6396d 100644 --- a/board/sipeed/maix/Kconfig +++ b/board/sipeed/maix/Kconfig @@ -44,4 +44,6 @@ config BOARD_SPECIFIC_OPTIONS imply RESET_SYSCON imply SYSRESET imply SYSRESET_SYSCON + imply RAM + imply K210_SRAM endif diff --git a/board/sipeed/maix/maix.c b/board/sipeed/maix/maix.c index cbcb23cf5c..1b6f8a5115 100644 --- a/board/sipeed/maix/maix.c +++ b/board/sipeed/maix/maix.c @@ -9,33 +9,7 @@ #include #include -phys_size_t get_effective_memsize(void) -{ - return CONFIG_SYS_SDRAM_SIZE; -} - int board_init(void) { - int ret, i; - const char * const banks[] = { "sram0", "sram1", "airam" }; - ofnode memory; - struct clk clk; - - /* Enable RAM clocks */ - memory = ofnode_by_compatible(ofnode_null(), "kendryte,k210-sram"); - if (ofnode_equal(memory, ofnode_null())) - return -ENOENT; - - for (i = 0; i < ARRAY_SIZE(banks); i++) { - ret = clk_get_by_name_nodev(memory, banks[i], &clk); - if (ret) - continue; - - ret = clk_enable(&clk); - clk_free(&clk); - if (ret) - return ret; - } - return 0; } diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig index 459bf0d530..d0100ad9e9 100644 --- a/configs/sipeed_maix_bitm_defconfig +++ b/configs/sipeed_maix_bitm_defconfig @@ -1,4 +1,5 @@ CONFIG_RISCV=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_TARGET_SIPEED_MAIX=y CONFIG_ARCH_RV64I=y CONFIG_STACK_SIZE=0x100000 diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h index 36ff522e4b..81956cccfd 100644 --- a/include/configs/sipeed-maix.h +++ b/include/configs/sipeed-maix.h @@ -14,10 +14,6 @@ #define CONFIG_SYS_MALLOC_LEN SZ_128K #define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -/* Don't relocate into AI ram since it isn't set up yet */ -#define CONFIG_SYS_SDRAM_SIZE (SZ_4M + SZ_2M) - /* For early init */ #define K210_SYSCTL_BASE 0x50440000 From patchwork Tue Sep 29 14:18:35 2020 Content-Type: text/plain; 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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id l6sm117535qkb.56.2020.09.29.07.18.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2020 07:18:56 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Bin Meng , Rick Chen , Heinrich Schuchardt , Sean Anderson Subject: [PATCH 10/10] riscv: Don't reserve AI ram in k210 dts Date: Tue, 29 Sep 2020 10:18:35 -0400 Message-Id: <20200929141835.38435-11-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200929141835.38435-1-seanga2@gmail.com> References: <20200929141835.38435-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean It is no longer necessary to disallow ai ram, since it is enabled by the sram driver. Signed-off-by: Sean Anderson --- arch/riscv/dts/k210.dtsi | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi index f7843985aa..7b0cd4f8f6 100644 --- a/arch/riscv/dts/k210.dtsi +++ b/arch/riscv/dts/k210.dtsi @@ -91,17 +91,6 @@ u-boot,dm-pre-reloc; }; - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - ai_reserved: ai@80600000 { - reg = <0x80600000 0x200000>; - reusable; - }; - }; - clocks { in0: osc { compatible = "fixed-clock"; @@ -177,7 +166,6 @@ reg = <0x40800000 0xc00000>; interrupts = <25>; clocks = <&sysclk K210_CLK_AI>; - memory-region = <&ai_reserved>; status = "disabled"; };