From patchwork Tue Sep 29 05:44:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qian Jianhua X-Patchwork-Id: 1373014 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=cn.fujitsu.com Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C0pJ61BH2z9s0b for ; Tue, 29 Sep 2020 15:45:08 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A56683986434; Tue, 29 Sep 2020 05:45:04 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from heian.cn.fujitsu.com (mail.cn.fujitsu.com [183.91.158.132]) by sourceware.org (Postfix) with ESMTP id A46CB3857C63 for ; Tue, 29 Sep 2020 05:44:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org A46CB3857C63 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=cn.fujitsu.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=qianjh@cn.fujitsu.com X-IronPort-AV: E=Sophos;i="5.77,317,1596470400"; d="scan'208";a="99702161" Received: from unknown (HELO cn.fujitsu.com) ([10.167.33.5]) by heian.cn.fujitsu.com with ESMTP; 29 Sep 2020 13:44:55 +0800 Received: from G08CNEXMBPEKD06.g08.fujitsu.local (unknown [10.167.33.206]) by cn.fujitsu.com (Postfix) with ESMTP id 7347D48990E8 for ; Tue, 29 Sep 2020 13:44:52 +0800 (CST) Received: from G08CNEXCHPEKD05.g08.fujitsu.local (10.167.33.203) by G08CNEXMBPEKD06.g08.fujitsu.local (10.167.33.206) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 29 Sep 2020 13:44:49 +0800 Received: from localhost (10.167.226.69) by G08CNEXCHPEKD05.g08.fujitsu.local (10.167.33.209) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 29 Sep 2020 13:44:51 +0800 From: Qian Jianhua To: Subject: [PATCH] arm&aarch64: subdivide the type attribute "alu_shfit_imm" Date: Tue, 29 Sep 2020 13:44:02 +0800 Message-ID: <20200929054402.27430-1-qianjh@cn.fujitsu.com> X-Mailer: git-send-email 2.18.1 MIME-Version: 1.0 X-yoursite-MailScanner-ID: 7347D48990E8.A2EDC X-yoursite-MailScanner: Found to be clean X-yoursite-MailScanner-From: qianjh@cn.fujitsu.com X-Spam-Status: No, score=-10.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" The type attribute "alu_shfit_imm" is subdivided into "alu_shift_imm_lsl_1to4" and "alu_shift_imm_other", to accommodate optimazations of some microarchitectures. Here is the detailed discussion. https://gcc.gnu.org/pipermail/gcc/2020-September/233594.html ChangeLog: 2020-09-29 Qian jianhua gcc/ * config/arm/types.md (define_attr "autodetect_type"): New. (define_attr "type"): Subdivide alu_shift_imm. * config/arm/common.md: New file. * config/aarch64/predicates.md:Include common.md. * config/arm/predicates.md:Include common.md. * config/aarch64/aarch64.md (*add__): Set autodetect_type. (*add__si_uxtw): Likewise. (*sub__): Likewise. (*sub__si_uxtw): Likewise. (*neg__2): Likewise. (*neg__si2_uxtw): Likewise. * config/arm/arm.md (*addsi3_carryin_shift): Likewise. (add_not_shift_cin): Likewise. (*subsi3_carryin_shift): Likewise. (*subsi3_carryin_shift_alt): Likewise. (*rsbsi3_carryin_shift): Likewise. (*rsbsi3_carryin_shift_alt): Likewise. (*arm_shiftsi3): Likewise. (*_multsi): Likewise. (*_shiftsi): Likewise. (subsi3_carryin): Set new type. (*if_arith_move): Set new type. (*if_move_arith): Set new type. (define_attr "core_cycles"): Use new type. * config/arm/arm-fixed.md (arm_ssatsihi_shift): Set autodetect_type. * config/arm/thumb2.md (*orsi_not_shiftsi_si): Likewise. (*thumb2_shiftsi3_short): Set new type. * config/aarch64/falkor.md (falkor_alu_1_xyz): Use new type. * config/aarch64/saphira.md (saphira_alu_1_xyz): Likewise. * config/aarch64/thunderx.md (thunderx_arith_shift): Likewise. * config/aarch64/thunderx2t99.md (thunderx2t99_alu_shift): Likewise. * config/aarch64/thunderx3t110.md (thunderx3t110_alu_shift): Likewise. (thunderx3t110_alu_shift1): Likewise. * config/aarch64/tsv110.md (tsv110_alu_shift): Likewise. * config/arm/arm1020e.md (1020alu_shift_op): Likewise. * config/arm/arm1026ejs.md (alu_shift_op): Likewise. * config/arm/arm1136jfs.md (11_alu_shift_op): Likewise. * config/arm/arm926ejs.md (9_alu_op): Likewise. * config/arm/cortex-a15.md (cortex_a15_alu_shift): Likewise. * config/arm/cortex-a17.md (cortex_a17_alu_shiftimm): Likewise. * config/arm/cortex-a5.md (cortex_a5_alu_shift): Likewise. * config/arm/cortex-a53.md (cortex_a53_alu_shift): Likewise. * config/arm/cortex-a57.md (cortex_a57_alu_shift): Likewise. * config/arm/cortex-a7.md (cortex_a7_alu_shift): Likewise. * config/arm/cortex-a8.md (cortex_a8_alu_shift): Likewise. * config/arm/cortex-a9.md (cortex_a9_dp_shift): Likewise. * config/arm/cortex-m4.md (cortex_m4_alu): Likewise. * config/arm/cortex-m7.md (cortex_m7_alu_shift): Likewise. * config/arm/cortex-r4.md (cortex_r4_alu_shift): Likewise. * config/arm/exynos-m1.md (exynos_m1_alu_shift): Likewise. * config/arm/fa526.md (526_alu_shift_op): Likewise. * config/arm/fa606te.md (606te_alu_op): Likewise. * config/arm/fa626te.md (626te_alu_shift_op): Likewise. * config/arm/fa726te.md (726te_alu_shift_op): Likewise. * config/arm/fmp626.md (mp626_alu_shift_op): Likewise. * config/arm/marvell-pj4.md (pj4_shift): Likewise. (pj4_shift_conds): Likewise. (pj4_alu_shift): Likewise. (pj4_alu_shift_conds): Likewise. * config/arm/xgene1.md (xgene1_alu): Likewise. * config/arm/arm.c (xscale_sched_adjust_cost): Likewise. Test Results: * Bootstrap on aarch64 ------------------------------- [OK] * Regression tests on aarch64------------------------- [OK] --- gcc/config/aarch64/aarch64.md | 12 ++--- gcc/config/aarch64/falkor.md | 2 +- gcc/config/aarch64/predicates.md | 2 + gcc/config/aarch64/saphira.md | 2 +- gcc/config/aarch64/thunderx.md | 2 +- gcc/config/aarch64/thunderx2t99.md | 2 +- gcc/config/aarch64/thunderx3t110.md | 4 +- gcc/config/aarch64/tsv110.md | 2 +- gcc/config/arm/arm-fixed.md | 2 +- gcc/config/arm/arm.c | 3 +- gcc/config/arm/arm.md | 39 ++++++++++------ gcc/config/arm/arm1020e.md | 2 +- gcc/config/arm/arm1026ejs.md | 2 +- gcc/config/arm/arm1136jfs.md | 2 +- gcc/config/arm/arm926ejs.md | 2 +- gcc/config/arm/common.md | 37 +++++++++++++++ gcc/config/arm/cortex-a15.md | 2 +- gcc/config/arm/cortex-a17.md | 2 +- gcc/config/arm/cortex-a5.md | 2 +- gcc/config/arm/cortex-a53.md | 2 +- gcc/config/arm/cortex-a57.md | 2 +- gcc/config/arm/cortex-a7.md | 2 +- gcc/config/arm/cortex-a8.md | 2 +- gcc/config/arm/cortex-a9.md | 2 +- gcc/config/arm/cortex-m4.md | 2 +- gcc/config/arm/cortex-m7.md | 2 +- gcc/config/arm/cortex-r4.md | 2 +- gcc/config/arm/exynos-m1.md | 2 +- gcc/config/arm/fa526.md | 2 +- gcc/config/arm/fa606te.md | 2 +- gcc/config/arm/fa626te.md | 2 +- gcc/config/arm/fa726te.md | 2 +- gcc/config/arm/fmp626.md | 2 +- gcc/config/arm/marvell-pj4.md | 8 ++-- gcc/config/arm/predicates.md | 2 + gcc/config/arm/thumb2.md | 6 ++- gcc/config/arm/types.md | 71 +++++++++++++++++++++++++++-- gcc/config/arm/xgene1.md | 2 +- 38 files changed, 179 insertions(+), 61 deletions(-) create mode 100644 gcc/config/arm/common.md diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index dbc6b1db176..12418f42ee5 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2447,7 +2447,7 @@ (match_operand:GPI 3 "register_operand" "r")))] "" "add\\t%0, %3, %1, %2" - [(set_attr "type" "alu_shift_imm")] + [(set_attr "autodetect_type" "alu_shift_operator")] ) ;; zero_extend version of above @@ -2459,7 +2459,7 @@ (match_operand:SI 3 "register_operand" "r"))))] "" "add\\t%w0, %w3, %w1, %2" - [(set_attr "type" "alu_shift_imm")] + [(set_attr "autodetect_type" "alu_shift_operator_zextend")] ) (define_insn "*add__" @@ -3094,7 +3094,7 @@ (match_operand:QI 2 "aarch64_shift_imm_" "n"))))] "" "sub\\t%0, %3, %1, %2" - [(set_attr "type" "alu_shift_imm")] + [(set_attr "autodetect_type" "alu_shift_operator")] ) ;; zero_extend version of above @@ -3107,7 +3107,7 @@ (match_operand:QI 2 "aarch64_shift_imm_si" "n")))))] "" "sub\\t%w0, %w3, %w1, %2" - [(set_attr "type" "alu_shift_imm")] + [(set_attr "autodetect_type" "alu_shift_operator_zextend")] ) (define_insn "*sub__" @@ -3508,7 +3508,7 @@ (match_operand:QI 2 "aarch64_shift_imm_" "n"))))] "" "neg\\t%0, %1, %2" - [(set_attr "type" "alu_shift_imm")] + [(set_attr "autodetect_type" "alu_shift_operator")] ) ;; zero_extend version of above @@ -3520,7 +3520,7 @@ (match_operand:QI 2 "aarch64_shift_imm_si" "n")))))] "" "neg\\t%w0, %w1, %2" - [(set_attr "type" "alu_shift_imm")] + [(set_attr "autodetect_type" "alu_shift_operator_zextend")] ) (define_insn "mul3" diff --git a/gcc/config/aarch64/falkor.md b/gcc/config/aarch64/falkor.md index b501771fc0b..ecfe4d4791b 100644 --- a/gcc/config/aarch64/falkor.md +++ b/gcc/config/aarch64/falkor.md @@ -302,7 +302,7 @@ (define_insn_reservation "falkor_alu_1_xyz" 1 (and (eq_attr "tune" "falkor") - (eq_attr "type" "alus_sreg,alus_imm,alus_shift_imm,csel,adc_reg,alu_imm,alu_sreg,alu_shift_imm,alu_ext,alus_ext,logic_imm,logic_reg,logic_shift_imm,logics_imm,logics_reg,logics_shift_imm,mov_reg")) + (eq_attr "type" "alus_sreg,alus_imm,alus_shift_imm,csel,adc_reg,alu_imm,alu_sreg,alu_shift_imm_lsl_1to4,alu_shift_imm_other,alu_ext,alus_ext,logic_imm,logic_reg,logic_shift_imm,logics_imm,logics_reg,logics_shift_imm,mov_reg")) "falkor_xyz") ;; SIMD Miscellaneous Instructions diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 91b51483f33..4f074a25a4a 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -18,6 +18,8 @@ ;; along with GCC; see the file COPYING3. If not see ;; . +(include "../arm/common.md") + (define_special_predicate "cc_register" (and (match_code "reg") (and (match_test "REGNO (op) == CC_REGNUM") diff --git a/gcc/config/aarch64/saphira.md b/gcc/config/aarch64/saphira.md index 78a495b2dd1..6e623c4a33d 100644 --- a/gcc/config/aarch64/saphira.md +++ b/gcc/config/aarch64/saphira.md @@ -224,7 +224,7 @@ (define_insn_reservation "saphira_alu_1_xyz" 1 (and (eq_attr "tune" "saphira") - (eq_attr "type" "alus_sreg,alus_imm,alus_shift_imm,csel,adc_reg,alu_imm,alu_sreg,alu_shift_imm,alu_ext,alus_ext,logic_imm,logic_reg,logic_shift_imm,logics_imm,logics_reg,logics_shift_imm,mov_reg")) + (eq_attr "type" "alus_sreg,alus_imm,alus_shift_imm,csel,adc_reg,alu_imm,alu_sreg,alu_shift_imm_lsl_1to4,alu_shift_imm_other,alu_ext,alus_ext,logic_imm,logic_reg,logic_shift_imm,logics_imm,logics_reg,logics_shift_imm,mov_reg")) "saphira_xyzb") ;; SIMD Miscellaneous Instructions diff --git a/gcc/config/aarch64/thunderx.md b/gcc/config/aarch64/thunderx.md index 52cd171bf67..c8c9f5cbd7a 100644 --- a/gcc/config/aarch64/thunderx.md +++ b/gcc/config/aarch64/thunderx.md @@ -51,7 +51,7 @@ (define_insn_reservation "thunderx_arith_shift" 2 (and (eq_attr "tune" "thunderx") - (eq_attr "type" "alu_ext,alu_shift_imm,alu_shift_reg,alus_ext,logic_shift_imm,logic_shift_reg,logics_shift_imm,logics_shift_reg,alus_shift_imm")) + (eq_attr "type" "alu_ext,alu_shift_imm_lsl_1to4,alu_shift_imm_other,alu_shift_reg,alus_ext,logic_shift_imm,logic_shift_reg,logics_shift_imm,logics_shift_reg,alus_shift_imm")) "thunderx_pipe0 | thunderx_pipe1") (define_insn_reservation "thunderx_csel" 2 diff --git a/gcc/config/aarch64/thunderx2t99.md b/gcc/config/aarch64/thunderx2t99.md index 064e1ca631d..d9da80dcee7 100644 --- a/gcc/config/aarch64/thunderx2t99.md +++ b/gcc/config/aarch64/thunderx2t99.md @@ -109,7 +109,7 @@ (define_insn_reservation "thunderx2t99_alu_shift" 2 (and (eq_attr "tune" "thunderx2t99") - (eq_attr "type" "alu_shift_imm,alu_ext,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alu_ext,\ alus_shift_imm,alus_ext,\ logic_shift_imm,logics_shift_imm")) "thunderx2t99_i012,thunderx2t99_i012") diff --git a/gcc/config/aarch64/thunderx3t110.md b/gcc/config/aarch64/thunderx3t110.md index f8d6204279a..ee1dd96272f 100644 --- a/gcc/config/aarch64/thunderx3t110.md +++ b/gcc/config/aarch64/thunderx3t110.md @@ -126,14 +126,14 @@ ; is it actually 1,1/2,{i0,i1} vs 2,1/4,{i0,i1,i2,i3} (define_insn_reservation "thunderx3t110_alu_shift" 2 (and (eq_attr "tune" "thunderx3t110") - (eq_attr "type" "alu_shift_imm,alu_ext,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alu_ext,\ alus_shift_imm,alus_ext,\ logic_shift_imm,logics_shift_imm")) "thunderx3t110_i0123") (define_insn_reservation "thunderx3t110_alu_shift1" 1 (and (eq_attr "tune" "thunderx3t110") - (eq_attr "type" "alu_shift_imm,alu_ext,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alu_ext,\ alus_shift_imm,alus_ext,\ logic_shift_imm,logics_shift_imm")) "thunderx3t110_i01") diff --git a/gcc/config/aarch64/tsv110.md b/gcc/config/aarch64/tsv110.md index 53293f5055a..b35ff2d0779 100644 --- a/gcc/config/aarch64/tsv110.md +++ b/gcc/config/aarch64/tsv110.md @@ -295,7 +295,7 @@ (define_insn_reservation "tsv110_alu_shift" 2 (and (eq_attr "tune" "tsv110") (eq_attr "type" "extend,\ - alu_shift_imm,alu_shift_reg,\ + alu_shift_imm_lsl_1to4,alu_shift_imm_other,alu_shift_reg,\ crc,logic_shift_imm,logic_shift_reg,\ mov_shift,mvn_shift,\ mov_shift_reg,mvn_shift_reg")) diff --git a/gcc/config/arm/arm-fixed.md b/gcc/config/arm/arm-fixed.md index c8ebf1b0314..ee18eeea239 100644 --- a/gcc/config/arm/arm-fixed.md +++ b/gcc/config/arm/arm-fixed.md @@ -482,7 +482,7 @@ "ssat%?\\t%0, #16, %2%S1" [(set_attr "predicable" "yes") (set_attr "shift" "1") - (set_attr "type" "alu_shift_imm")]) + (set_attr "autodetect_type" "alu_shift_operator1")]) (define_insn "arm_usatsihi" [(set (match_operand:HI 0 "s_register_operand" "=r") diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 932f90794c8..c415ad1c9b5 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -11898,7 +11898,8 @@ xscale_sched_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep, instruction we depend on is another ALU instruction, then we may have to account for an additional stall. */ if (shift_opnum != 0 - && (attr_type == TYPE_ALU_SHIFT_IMM + && (attr_type == TYPE_ALU_SHIFT_IMM_LSL_1TO4 + || attr_type == TYPE_ALU_SHIFT_IMM_OTHER || attr_type == TYPE_ALUS_SHIFT_IMM || attr_type == TYPE_LOGIC_SHIFT_IMM || attr_type == TYPE_LOGICS_SHIFT_IMM diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index dd13c77e889..a47df9e9bb8 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -336,7 +336,8 @@ (define_attr "core_cycles" "single,multi" (if_then_else (eq_attr "type" "adc_imm, adc_reg, adcs_imm, adcs_reg, adr, alu_ext, alu_imm, alu_sreg,\ - alu_shift_imm, alu_shift_reg, alu_dsp_reg, alus_ext, alus_imm, alus_sreg,\ + alu_shift_imm_lsl_1to4, alu_shift_imm_other, alu_shift_reg, alu_dsp_reg,\ + alus_ext, alus_imm, alus_sreg,\ alus_shift_imm, alus_shift_reg, bfm, csel, rev, logic_imm, logic_reg,\ logic_shift_imm, logic_shift_reg, logics_imm, logics_reg,\ logics_shift_imm, logics_shift_reg, extend, shift_imm, float, fcsel,\ @@ -1370,7 +1371,8 @@ (set_attr "arch" "32,a") (set_attr "shift" "3") (set_attr "predicable" "yes") - (set_attr "type" "alu_shift_imm,alu_shift_reg")] + (set_attr "autodetect_type" "alu_shift_operator2,none") + (set_attr "type" "*,alu_shift_reg")] ) (define_insn "*addsi3_carryin_clobercc" @@ -1679,7 +1681,7 @@ [(set_attr "conds" "use") (set_attr "arch" "*,a,t2") (set_attr "predicable" "yes") - (set_attr "type" "adc_reg,adc_imm,alu_shift_imm")] + (set_attr "type" "adc_reg,adc_imm,alu_shift_imm_lsl_1to4")] ) ;; Special canonicalization of the above when operand1 == (const_int 1): @@ -1727,7 +1729,8 @@ "rsc%?\\t%0, %4, %1%S3" [(set_attr "conds" "use") (set_attr "predicable" "yes") - (set_attr "type" "alu_shift_imm,alu_shift_reg")] + (set_attr "autodetect_type" "alu_shift_operator3,none") + (set_attr "type" "*,alu_shift_reg")] ) (define_insn "cmpsi3_carryin_out" @@ -1811,7 +1814,8 @@ (set_attr "arch" "32,a") (set_attr "shift" "3") (set_attr "predicable" "yes") - (set_attr "type" "alu_shift_imm,alu_shift_reg")] + (set_attr "autodetect_type" "alu_shift_operator2,none") + (set_attr "type" "*,alu_shift_reg")] ) (define_insn "*subsi3_carryin_shift_alt" @@ -1828,7 +1832,8 @@ (set_attr "arch" "32,a") (set_attr "shift" "3") (set_attr "predicable" "yes") - (set_attr "type" "alu_shift_imm,alu_shift_reg")] + (set_attr "autodetect_type" "alu_shift_operator2,none") + (set_attr "type" "*,alu_shift_reg")] ) ;; No RSC in Thumb2 @@ -1844,7 +1849,8 @@ "rsc%?\\t%0, %1, %3%S2" [(set_attr "conds" "use") (set_attr "predicable" "yes") - (set_attr "type" "alu_shift_imm,alu_shift_reg")] + (set_attr "autodetect_type" "alu_shift_operator2,none") + (set_attr "type" "*,alu_shift_reg")] ) (define_insn "*rsbsi3_carryin_shift_alt" @@ -1859,7 +1865,8 @@ "rsc%?\\t%0, %1, %3%S2" [(set_attr "conds" "use") (set_attr "predicable" "yes") - (set_attr "type" "alu_shift_imm,alu_shift_reg")] + (set_attr "autodetect_type" "alu_shift_operator2,none") + (set_attr "type" "*,alu_shift_reg")] ) ; transform ((x << y) - 1) to ~(~(x-1) << y) Where X is a constant. @@ -4646,7 +4653,8 @@ (set_attr "predicable_short_it" "yes,yes,no,no") (set_attr "length" "4") (set_attr "shift" "1") - (set_attr "type" "alu_shift_reg,alu_shift_imm,alu_shift_imm,alu_shift_reg")] + (set_attr "autodetect_type" "none,alu_shift_operator3,alu_shift_operator3,none") + (set_attr "type" "alu_shift_reg,*,*,alu_shift_reg")] ) (define_insn "*shiftsi3_compare0" @@ -9501,7 +9509,7 @@ [(set_attr "predicable" "yes") (set_attr "shift" "2") (set_attr "arch" "a,t2") - (set_attr "type" "alu_shift_imm")]) + (set_attr "autodetect_type" "alu_shift_lsl_op3")]) (define_insn "*_shiftsi" [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") @@ -9515,7 +9523,8 @@ [(set_attr "predicable" "yes") (set_attr "shift" "3") (set_attr "arch" "a,t2,a") - (set_attr "type" "alu_shift_imm,alu_shift_imm,alu_shift_reg")]) + (set_attr "autodetect_type" "alu_shift_operator2,alu_shift_operator2,none") + (set_attr "type" "*,*,alu_shift_reg")]) (define_split [(set (match_operand:SI 0 "s_register_operand" "") @@ -10854,7 +10863,9 @@ (set_attr "length" "4,8") (set_attr_alternative "type" [(if_then_else (match_operand 3 "const_int_operand" "") - (const_string "alu_shift_imm" ) + (if_then_else (match_operand 5 "alu_shift_operator_lsl_1_to_4") + (const_string "alu_shift_imm_lsl_1to4") + (const_string "alu_shift_imm_other")) (const_string "alu_shift_reg")) (const_string "multiple")])] ) @@ -10919,7 +10930,9 @@ (set_attr "length" "4,8") (set_attr_alternative "type" [(if_then_else (match_operand 3 "const_int_operand" "") - (const_string "alu_shift_imm" ) + (if_then_else (match_operand 5 "alu_shift_operator_lsl_1_to_4") + (const_string "alu_shift_imm_lsl_1to4") + (const_string "alu_shift_imm_other")) (const_string "alu_shift_reg")) (const_string "multiple")])] ) diff --git a/gcc/config/arm/arm1020e.md b/gcc/config/arm/arm1020e.md index d1043f572a4..16fbd88b2e8 100644 --- a/gcc/config/arm/arm1020e.md +++ b/gcc/config/arm/arm1020e.md @@ -78,7 +78,7 @@ ;; ALU operations with a shift-by-constant operand (define_insn_reservation "1020alu_shift_op" 1 (and (eq_attr "tune" "arm10e") - (eq_attr "type" "alu_shift_imm,alus_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ extend,mov_shift,mvn_shift")) "1020a_e,1020a_m,1020a_w") diff --git a/gcc/config/arm/arm1026ejs.md b/gcc/config/arm/arm1026ejs.md index 59506298a0f..ae8c03fd193 100644 --- a/gcc/config/arm/arm1026ejs.md +++ b/gcc/config/arm/arm1026ejs.md @@ -78,7 +78,7 @@ ;; ALU operations with a shift-by-constant operand (define_insn_reservation "alu_shift_op" 1 (and (eq_attr "tune" "arm1026ejs") - (eq_attr "type" "alu_shift_imm,alus_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ extend,mov_shift,mvn_shift")) "a_e,a_m,a_w") diff --git a/gcc/config/arm/arm1136jfs.md b/gcc/config/arm/arm1136jfs.md index ead4eef0565..7968d9d5973 100644 --- a/gcc/config/arm/arm1136jfs.md +++ b/gcc/config/arm/arm1136jfs.md @@ -87,7 +87,7 @@ ;; ALU operations with a shift-by-constant operand (define_insn_reservation "11_alu_shift_op" 2 (and (eq_attr "tune" "arm1136js,arm1136jfs") - (eq_attr "type" "alu_shift_imm,alus_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ extend,mov_shift,mvn_shift")) "e_1,e_2,e_3,e_wb") diff --git a/gcc/config/arm/arm926ejs.md b/gcc/config/arm/arm926ejs.md index ba9c942c1d9..34da6be2e03 100644 --- a/gcc/config/arm/arm926ejs.md +++ b/gcc/config/arm/arm926ejs.md @@ -62,7 +62,7 @@ alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ adr,bfm,rev,\ - alu_shift_imm,alus_shift_imm,\ + alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ shift_imm,shift_reg,extend,\ mov_imm,mov_reg,mov_shift,\ diff --git a/gcc/config/arm/common.md b/gcc/config/arm/common.md new file mode 100644 index 00000000000..1a5da834d61 --- /dev/null +++ b/gcc/config/arm/common.md @@ -0,0 +1,37 @@ +;; Common predicate definitions for ARM, Thumb and AArch64 +;; Copyright (C) 2020 Free Software Foundation, Inc. +;; Contributed by Fujitsu Ltd. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; Return true if constant is CONST_INT >= 1 and <= 4 +(define_predicate "const_1_to_4_operand" + (and (match_code "const_int") + (match_test "IN_RANGE(INTVAL (op), 1, 4)"))) + +;; Return true if constant is 2 or 4 or 8 or 16 +(define_predicate "const_2_4_8_16_operand" + (and (match_code "const_int") + (match_test (" INTVAL (op) == 2 + || INTVAL (op) == 4 + || INTVAL (op) == 8 + || INTVAL (op) == 16 ")))) + +;; Return true if shift type is lsl and amount is in[1,4]. +(define_predicate "alu_shift_operator_lsl_1_to_4" + (and (match_code "ashift") + (match_test "const_1_to_4_operand(XEXP(op, 1), mode)"))) diff --git a/gcc/config/arm/cortex-a15.md b/gcc/config/arm/cortex-a15.md index 3cd1c4351d3..3d22eb3bb56 100644 --- a/gcc/config/arm/cortex-a15.md +++ b/gcc/config/arm/cortex-a15.md @@ -78,7 +78,7 @@ (define_insn_reservation "cortex_a15_alu_shift" 3 (and (eq_attr "tune" "cortexa15") (eq_attr "type" "extend,\ - alu_shift_imm,alus_shift_imm,\ + alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ crc,logic_shift_imm,logics_shift_imm,\ mov_shift,mvn_shift")) "ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\ diff --git a/gcc/config/arm/cortex-a17.md b/gcc/config/arm/cortex-a17.md index ad524c6d57e..dfd0343e8c7 100644 --- a/gcc/config/arm/cortex-a17.md +++ b/gcc/config/arm/cortex-a17.md @@ -47,7 +47,7 @@ (define_insn_reservation "cortex_a17_alu_shiftimm" 2 (and (eq_attr "tune" "cortexa17") - (eq_attr "type" "bfm,clz,rev,rbit, alu_shift_imm, alus_shift_imm, + (eq_attr "type" "bfm,clz,rev,rbit, alu_shift_imm_lsl_1to4,alu_shift_imm_other, alus_shift_imm, logic_shift_imm,alu_dsp_reg, logics_shift_imm,shift_imm,\ shift_reg, mov_shift,mvn_shift")) "ca17_alu") diff --git a/gcc/config/arm/cortex-a5.md b/gcc/config/arm/cortex-a5.md index fd346965cb6..e9ee730d6b2 100644 --- a/gcc/config/arm/cortex-a5.md +++ b/gcc/config/arm/cortex-a5.md @@ -70,7 +70,7 @@ (define_insn_reservation "cortex_a5_alu_shift" 2 (and (eq_attr "tune" "cortexa5") (eq_attr "type" "extend,\ - alu_shift_imm,alus_shift_imm,\ + alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ alu_shift_reg,alus_shift_reg,\ logic_shift_reg,logics_shift_reg,\ diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md index afa3b789122..a7c8666fbd2 100644 --- a/gcc/config/arm/cortex-a53.md +++ b/gcc/config/arm/cortex-a53.md @@ -91,7 +91,7 @@ (define_insn_reservation "cortex_a53_alu_shift" 3 (and (eq_attr "tune" "cortexa53") - (eq_attr "type" "alu_shift_imm,alus_shift_imm, + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm, crc,logic_shift_imm,logics_shift_imm, alu_ext,alus_ext,bfm,bfx,extend,mvn_shift")) "cortex_a53_slot_any") diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md index 93d756b64cd..ac5876f228a 100644 --- a/gcc/config/arm/cortex-a57.md +++ b/gcc/config/arm/cortex-a57.md @@ -313,7 +313,7 @@ (define_insn_reservation "cortex_a57_alu_shift" 3 (and (eq_attr "tune" "cortexa57") (eq_attr "type" "bfm,\ - alu_shift_imm,alus_shift_imm,\ + alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ crc,logic_shift_imm,logics_shift_imm,\ mov_shift,mvn_shift")) "ca57_mx") diff --git a/gcc/config/arm/cortex-a7.md b/gcc/config/arm/cortex-a7.md index 1106cf84a1a..254b2cc6eec 100644 --- a/gcc/config/arm/cortex-a7.md +++ b/gcc/config/arm/cortex-a7.md @@ -143,7 +143,7 @@ (define_insn_reservation "cortex_a7_alu_shift" 2 (and (eq_attr "tune" "cortexa7") - (eq_attr "type" "alu_shift_imm,alus_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ alu_shift_reg,alus_shift_reg,\ logic_shift_reg,logics_shift_reg,\ diff --git a/gcc/config/arm/cortex-a8.md b/gcc/config/arm/cortex-a8.md index 9032cb3709e..23c617d8aad 100644 --- a/gcc/config/arm/cortex-a8.md +++ b/gcc/config/arm/cortex-a8.md @@ -95,7 +95,7 @@ (define_insn_reservation "cortex_a8_alu_shift" 2 (and (eq_attr "tune" "cortexa8") - (eq_attr "type" "alu_shift_imm,alus_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ extend")) "cortex_a8_default") diff --git a/gcc/config/arm/cortex-a9.md b/gcc/config/arm/cortex-a9.md index 3a880d724ec..6ddc1203e18 100644 --- a/gcc/config/arm/cortex-a9.md +++ b/gcc/config/arm/cortex-a9.md @@ -93,7 +93,7 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1") ;; An instruction using the shifter will go down E1. (define_insn_reservation "cortex_a9_dp_shift" 3 (and (eq_attr "tune" "cortexa9") - (eq_attr "type" "alu_shift_imm,alus_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ alu_shift_reg,alus_shift_reg,\ logic_shift_reg,logics_shift_reg,\ diff --git a/gcc/config/arm/cortex-m4.md b/gcc/config/arm/cortex-m4.md index 20037caf342..4367b76231c 100644 --- a/gcc/config/arm/cortex-m4.md +++ b/gcc/config/arm/cortex-m4.md @@ -36,7 +36,7 @@ adc_imm,adcs_imm,adc_reg,adcs_reg,\ adr,bfm,clz,rbit,rev,alu_dsp_reg,\ shift_imm,shift_reg,extend,\ - alu_shift_imm,alus_shift_imm,\ + alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ alu_shift_reg,alus_shift_reg,\ logic_shift_reg,logics_shift_reg,\ diff --git a/gcc/config/arm/cortex-m7.md b/gcc/config/arm/cortex-m7.md index b616a95a50c..df03e06cae2 100644 --- a/gcc/config/arm/cortex-m7.md +++ b/gcc/config/arm/cortex-m7.md @@ -54,7 +54,7 @@ ;; Simple alu with inline shift operation. (define_insn_reservation "cortex_m7_alu_shift" 2 (and (eq_attr "tune" "cortexm7") - (eq_attr "type" "alu_shift_imm,alus_shift_imm")) + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm")) "cm7_i0|cm7_i1,(cm7_a0|cm7_a1)+cm7_shf+cm7_branch") ;; Only one ALU can be used for DSP instructions. diff --git a/gcc/config/arm/cortex-r4.md b/gcc/config/arm/cortex-r4.md index e8fad309d25..9be4b4c7d47 100644 --- a/gcc/config/arm/cortex-r4.md +++ b/gcc/config/arm/cortex-r4.md @@ -92,7 +92,7 @@ (define_insn_reservation "cortex_r4_alu_shift" 2 (and (eq_attr "tune_cortexr4" "yes") - (eq_attr "type" "alu_shift_imm,alus_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ extend,mov_shift,mvn_shift")) "cortex_r4_alu") diff --git a/gcc/config/arm/exynos-m1.md b/gcc/config/arm/exynos-m1.md index 48d0e9ed384..c31c8504fbd 100644 --- a/gcc/config/arm/exynos-m1.md +++ b/gcc/config/arm/exynos-m1.md @@ -386,7 +386,7 @@ (define_insn_reservation "exynos_m1_alu_shift" 2 (and (eq_attr "tune" "exynosm1") (eq_attr "type" "alu_ext, alus_ext,\ - alu_shift_imm, alus_shift_imm,\ + alu_shift_imm_lsl_1to4,alu_shift_imm_other, alus_shift_imm,\ logic_shift_imm, logics_shift_imm,\ mov_shift, mvn_shift")) "(em1_alu)") diff --git a/gcc/config/arm/fa526.md b/gcc/config/arm/fa526.md index e854be186e1..c8a2311ebf9 100644 --- a/gcc/config/arm/fa526.md +++ b/gcc/config/arm/fa526.md @@ -74,7 +74,7 @@ (define_insn_reservation "526_alu_shift_op" 2 (and (eq_attr "tune" "fa526") (eq_attr "type" "extend,\ - alu_shift_imm,alus_shift_imm,\ + alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ alu_shift_reg,alus_shift_reg,\ logic_shift_reg,logics_shift_reg,\ diff --git a/gcc/config/arm/fa606te.md b/gcc/config/arm/fa606te.md index d5dc24faae4..11e1484d830 100644 --- a/gcc/config/arm/fa606te.md +++ b/gcc/config/arm/fa606te.md @@ -67,7 +67,7 @@ adc_imm,adcs_imm,adc_reg,adcs_reg,\ adr,bfm,rev,\ shift_imm,shift_reg,extend,\ - alu_shift_imm,alus_shift_imm,\ + alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ alu_shift_reg,alus_shift_reg,\ logic_shift_reg,logics_shift_reg,\ diff --git a/gcc/config/arm/fa626te.md b/gcc/config/arm/fa626te.md index 89019658fef..00cf7f6d83d 100644 --- a/gcc/config/arm/fa626te.md +++ b/gcc/config/arm/fa626te.md @@ -80,7 +80,7 @@ (define_insn_reservation "626te_alu_shift_op" 2 (and (eq_attr "tune" "fa626,fa626te") (eq_attr "type" "extend,\ - alu_shift_imm,alus_shift_imm,\ + alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ alu_shift_reg,alus_shift_reg,\ logic_shift_reg,logics_shift_reg,\ diff --git a/gcc/config/arm/fa726te.md b/gcc/config/arm/fa726te.md index 4d52246712e..2fc54a8f7c6 100644 --- a/gcc/config/arm/fa726te.md +++ b/gcc/config/arm/fa726te.md @@ -100,7 +100,7 @@ ;; it takes 3 cycles. (define_insn_reservation "726te_alu_shift_op" 3 (and (eq_attr "tune" "fa726te") - (eq_attr "type" "extend,alu_shift_imm,alus_shift_imm,\ + (eq_attr "type" "extend,alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\ logic_shift_imm,logics_shift_imm")) "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)") diff --git a/gcc/config/arm/fmp626.md b/gcc/config/arm/fmp626.md index 8fee6783517..b0f96ac7478 100644 --- a/gcc/config/arm/fmp626.md +++ b/gcc/config/arm/fmp626.md @@ -73,7 +73,7 @@ (define_insn_reservation "mp626_alu_shift_op" 2 (and (eq_attr "tune" "fmp626") - (eq_attr "type" "alu_shift_imm,logic_shift_imm,alus_shift_imm,logics_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,logic_shift_imm,alus_shift_imm,logics_shift_imm,\ alu_shift_reg,logic_shift_reg,alus_shift_reg,logics_shift_reg,\ extend,\ mov_shift,mov_shift_reg,\ diff --git a/gcc/config/arm/marvell-pj4.md b/gcc/config/arm/marvell-pj4.md index c415e0df376..0255810f633 100644 --- a/gcc/config/arm/marvell-pj4.md +++ b/gcc/config/arm/marvell-pj4.md @@ -73,7 +73,7 @@ (define_insn_reservation "pj4_shift" 1 (and (eq_attr "tune" "marvell_pj4") - (eq_attr "type" "alu_shift_imm,logic_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,logic_shift_imm,\ alus_shift_imm,logics_shift_imm,\ alu_shift_reg,logic_shift_reg,\ alus_shift_reg,logics_shift_reg,\ @@ -84,7 +84,7 @@ (define_insn_reservation "pj4_shift_conds" 4 (and (eq_attr "tune" "marvell_pj4") - (eq_attr "type" "alu_shift_imm,logic_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,logic_shift_imm,\ alus_shift_imm,logics_shift_imm,\ alu_shift_reg,logic_shift_reg,\ alus_shift_reg,logics_shift_reg,\ @@ -96,7 +96,7 @@ (define_insn_reservation "pj4_alu_shift" 1 (and (eq_attr "tune" "marvell_pj4") (not (eq_attr "conds" "set")) - (eq_attr "type" "alu_shift_imm,logic_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,logic_shift_imm,\ alus_shift_imm,logics_shift_imm,\ alu_shift_reg,logic_shift_reg,\ alus_shift_reg,logics_shift_reg,\ @@ -107,7 +107,7 @@ (define_insn_reservation "pj4_alu_shift_conds" 4 (and (eq_attr "tune" "marvell_pj4") (eq_attr "conds" "set") - (eq_attr "type" "alu_shift_imm,logic_shift_imm,alus_shift_imm,logics_shift_imm,\ + (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,logic_shift_imm,alus_shift_imm,logics_shift_imm,\ alu_shift_reg,logic_shift_reg,alus_shift_reg,logics_shift_reg,\ extend,\ mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg")) diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 981eec520ba..0d0baa5cdd9 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -18,6 +18,8 @@ ;; along with GCC; see the file COPYING3. If not see ;; . +(include "common.md") + (define_predicate "s_register_operand" (match_code "reg,subreg") { diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 1a5f24e5276..12139645a9e 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -1214,7 +1214,9 @@ (set_attr "shift" "1") (set_attr "length" "2") (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") - (const_string "alu_shift_imm") + (if_then_else (match_operand 3 "alu_shift_operator_lsl_1_to_4") + (const_string "alu_shift_imm_lsl_1to4") + (const_string "alu_shift_imm_other")) (const_string "alu_shift_reg")))] ) @@ -1483,7 +1485,7 @@ "orn%?\\t%0, %1, %2%S4" [(set_attr "predicable" "yes") (set_attr "shift" "2") - (set_attr "type" "alu_shift_imm")] + (set_attr "autodetect_type" "alu_shift_operator4")] ) (define_peephole2 diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index 83983452f52..d1303c6fd76 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -19,6 +19,20 @@ ;; along with GCC; see the file COPYING3. If not see ;; . +; The insn need to autodetect for specific type attribute +(define_attr "autodetect_type" + "none,\ + alu_shift_lsl_op2,\ + alu_shift_lsl_op3,\ + alu_shift_operator,\ + alu_shift_operator_zextend,\ + alu_shift_operator1,\ + alu_shift_operator2,\ + alu_shift_operator3,\ + alu_shift_operator4,\ + alu_shift_operator5" + (const_string "none")) + ; TYPE attribute is used to classify instructions for use in scheduling. ; ; Instruction classification: @@ -39,16 +53,22 @@ ; or an immediate operand. This excludes ; MOV and MVN but includes MOVT. This also excludes ; DSP-kind instructions. This is also the default. -; alu_shift_imm any arithmetic instruction that has a source operand +; alu_shift_imm_lsl_1to4 +; any arithmetic instruction that has a source operand ; shifted by a constant. This excludes simple shifts. -; alu_shift_reg as alu_shift_imm, with the shift amount specified in a +; The shift type is LSL. And the shift amount is greater +; than or equal 1, and less than or equal 4. +; alu_shift_imm_other +; as alu_shift_imm_lsl_1to4, with she shift type is LSR or +; ASR, or the shift amount is greater than or equal 5. +; alu_shift_reg as alu_shift_imm_*, with the shift amount specified in a ; register. ; alu_dsp_reg any DSP-kind instruction like QSUB8. ; alus_ext From ARMv8-A: as alu_ext, setting condition flags. ; AArch64 Only. ; alus_imm as alu_imm, setting condition flags. ; alus_sreg as alu_sreg, setting condition flags. -; alus_shift_imm as alu_shift_imm, setting condition flags. +; alus_shift_imm as alu_shift_imm_*, setting condition flags. ; alus_shift_reg as alu_shift_reg, setting condition flags. ; bfm bitfield move operation. ; bfx bitfield extract operation. @@ -565,7 +585,8 @@ alu_ext,\ alu_imm,\ alu_sreg,\ - alu_shift_imm,\ + alu_shift_imm_lsl_1to4,\ + alu_shift_imm_other,\ alu_shift_reg,\ alu_dsp_reg,\ alus_ext,\ @@ -1106,7 +1127,47 @@ mve_move,\ mve_store,\ mve_load" - (const_string "untyped")) + (cond [(eq_attr "autodetect_type" "alu_shift_lsl_op2") + (if_then_else (match_operand 2 "const_1_to_4_operand") + (const_string "alu_shift_imm_lsl_1to4") + (const_string "alu_shift_imm_other")) + (eq_attr "autodetect_type" "alu_shift_lsl_op3") + (if_then_else (match_operand 3 "const_2_4_8_16_operand") + (const_string "alu_shift_imm_lsl_1to4") + (const_string "alu_shift_imm_other")) + (eq_attr "autodetect_type" "alu_shift_operator") + (if_then_else (match_test "alu_shift_operator_lsl_1_to_4 + (XEXP(XEXP(PATTERN(insn),1),0), VOIDmode)") + (const_string "alu_shift_imm_lsl_1to4") + (const_string "alu_shift_imm_other")) + (eq_attr "autodetect_type" "alu_shift_operator_zextend") + (if_then_else (match_test "alu_shift_operator_lsl_1_to_4 + (XEXP(XEXP(XEXP(PATTERN(insn),1),0),0), VOIDmode)") + (const_string "alu_shift_imm_lsl_1to4") + (const_string "alu_shift_imm_other")) + (eq_attr "autodetect_type" "alu_shift_operator1") + (if_then_else (match_operand 1 "alu_shift_operator_lsl_1_to_4") + (const_string "alu_shift_imm_lsl_1to4") + (const_string "alu_shift_imm_other")) + (eq_attr "autodetect_type" "alu_shift_operator2") + (if_then_else (match_operand 2 "alu_shift_operator_lsl_1_to_4") + (const_string "alu_shift_imm_lsl_1to4") + (const_string "alu_shift_imm_other")) + (eq_attr "autodetect_type" "alu_shift_operator3") + (if_then_else (match_operand 3 "alu_shift_operator_lsl_1_to_4") + (const_string "alu_shift_imm_lsl_1to4") + (const_string "alu_shift_imm_other")) + (eq_attr "autodetect_type" "alu_shift_operator4") + (if_then_else (match_operand 4 "alu_shift_operator_lsl_1_to_4") + (const_string "alu_shift_imm_lsl_1to4") + (const_string "alu_shift_imm_other")) + (eq_attr "autodetect_type" "alu_shift_operator5") + (if_then_else (match_operand 5 "alu_shift_operator_lsl_1_to_4") + (const_string "alu_shift_imm_lsl_1to4") + (const_string "alu_shift_imm_other")) + ] + (const_string "untyped"))) + ; Is this an (integer side) multiply with a 32-bit (or smaller) result? (define_attr "mul32" "no,yes" diff --git a/gcc/config/arm/xgene1.md b/gcc/config/arm/xgene1.md index a2f6b8a1346..5860adc0448 100644 --- a/gcc/config/arm/xgene1.md +++ b/gcc/config/arm/xgene1.md @@ -132,7 +132,7 @@ (define_insn_reservation "xgene1_alu" 1 (and (eq_attr "tune" "xgene1") - (eq_attr "type" "alu_imm,alu_sreg,alu_shift_imm,\ + (eq_attr "type" "alu_imm,alu_sreg,alu_shift_imm_lsl_1to4,alu_shift_imm_other,\ alu_ext,adc_reg,logic_imm,\ logic_reg,logic_shift_imm,clz,\ rbit,adr,mov_reg,shift_imm,\