From patchwork Thu Dec 28 09:10:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jakub Jelinek X-Patchwork-Id: 853377 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-469855-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="SUKyMag8"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3z6kTK1Hbqz9s72 for ; Thu, 28 Dec 2017 20:10:28 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:reply-to:mime-version :content-type; q=dns; s=default; b=vE755/6+TqA21kH+ydDcZKHuKxrxp u8JjEW3uaGNNuEu1nKWGFSKASM0+jKDCwyp9agfPmP78wZA3CS0KSbtwzAq5zWi3 VSDNyghb/vScAPNkF3n8xSf56oX/hXtES7jv8Dx5pCpM389Q7e7uM73Xm1Dabv1m +1sAyoOyDe5mvY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:reply-to:mime-version :content-type; s=default; bh=t5WduuUiwHnr7hz1ylJ5eGNyQow=; b=SUK yMag8KSk64SNjjn3roF6xGB0am/xgDQWaLXfTtPgHP1zvnFca9zKHJdvcl7tCb/E PRO/dHHRR6AvtyltsHYGz/uJFfgigOpfGJdxwk47splmjtnySvZtsmoWvFiSQMuS 2d1k+7DQCG7T57q/mzXJ77DpkqtnJBvlxtYRUXBs= Received: (qmail 120261 invoked by alias); 28 Dec 2017 09:10:21 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 120250 invoked by uid 89); 28 Dec 2017 09:10:21 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-11.9 required=5.0 tests=BAYES_00, GIT_PATCH_2, GIT_PATCH_3, SPF_HELO_PASS, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy= X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 28 Dec 2017 09:10:19 +0000 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 213DAC047B91; Thu, 28 Dec 2017 09:10:18 +0000 (UTC) Received: from tucnak.zalov.cz (ovpn-116-90.ams2.redhat.com [10.36.116.90]) by smtp.corp.redhat.com (Postfix) with ESMTPS id B8DB15C545; Thu, 28 Dec 2017 09:10:17 +0000 (UTC) Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.15.2/8.15.2) with ESMTP id vBS9AFXX030759; Thu, 28 Dec 2017 10:10:15 +0100 Received: (from jakub@localhost) by tucnak.zalov.cz (8.15.2/8.15.2/Submit) id vBS9AEku030758; Thu, 28 Dec 2017 10:10:14 +0100 Date: Thu, 28 Dec 2017 10:10:14 +0100 From: Jakub Jelinek To: Uros Bizjak , Kirill Yukhin Cc: gcc-patches@gcc.gnu.org, Julia Koval , Sebastian Peryt Subject: [PATCH] Fix a vbmi2 ICE (PR target/83604) Message-ID: <20171228091014.GG1833@tucnak> Reply-To: Jakub Jelinek MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.9.1 (2017-09-22) X-IsSubscribed: yes Hi! These insns don't really need AVX512BW in any way themselves, only their masked variants might need it for reloading of the mask register, but that should be covered in builtins.def, doesn't need duplication in sse.md. For non-masked it causes ICEs, because the builtins properly aren't guarded with AVX512BW, but the insns incorrectly require that. Fixed thusly, bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2017-12-28 Jakub Jelinek PR target/83604 * config/i386/sse.md (VI248_VLBW): Rename to ... (VI248_AVX512VL): ... this. Don't guard V32HI with TARGET_AVX512BW. (vpshrd_, vpshld_, vpshrdv_, vpshrdv__mask, vpshrdv__maskz, vpshrdv__maskz_1, vpshldv_, vpshldv__mask, vpshldv__maskz, vpshldv__maskz_1): Use VI248_AVX512VL mode iterator instead of VI248_VLBW. * gcc.target/i386/pr83604.c: New test. Jakub --- gcc/config/i386/sse.md.jj 2017-12-27 19:19:58.081660733 +0100 +++ gcc/config/i386/sse.md 2017-12-27 18:43:32.200347561 +0100 @@ -448,8 +448,8 @@ (define_mode_iterator VI124_AVX2 (define_mode_iterator VI2_AVX2_AVX512BW [(V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI]) -(define_mode_iterator VI248_VLBW - [(V32HI "TARGET_AVX512BW") V16SI V8DI +(define_mode_iterator VI248_AVX512VL + [V32HI V16SI V8DI (V16HI "TARGET_AVX512VL") (V8SI "TARGET_AVX512VL") (V4DI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) @@ -20134,10 +20134,10 @@ (define_insn "vgf2p8mulb_")]) (define_insn "vpshrd_" - [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") - (unspec:VI248_VLBW - [(match_operand:VI248_VLBW 1 "register_operand" "v") - (match_operand:VI248_VLBW 2 "nonimmediate_operand" "vm") + [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v") + (unspec:VI248_AVX512VL + [(match_operand:VI248_AVX512VL 1 "register_operand" "v") + (match_operand:VI248_AVX512VL 2 "nonimmediate_operand" "vm") (match_operand:SI 3 "const_0_to_255_operand" "n")] UNSPEC_VPSHRD))] "TARGET_AVX512VBMI2" @@ -20145,10 +20145,10 @@ (define_insn "vpshrd_" [(set_attr ("prefix") ("evex"))]) (define_insn "vpshld_" - [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") - (unspec:VI248_VLBW - [(match_operand:VI248_VLBW 1 "register_operand" "v") - (match_operand:VI248_VLBW 2 "nonimmediate_operand" "vm") + [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v") + (unspec:VI248_AVX512VL + [(match_operand:VI248_AVX512VL 1 "register_operand" "v") + (match_operand:VI248_AVX512VL 2 "nonimmediate_operand" "vm") (match_operand:SI 3 "const_0_to_255_operand" "n")] UNSPEC_VPSHLD))] "TARGET_AVX512VBMI2" @@ -20156,11 +20156,11 @@ (define_insn "vpshld_" [(set_attr ("prefix") ("evex"))]) (define_insn "vpshrdv_" - [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") - (unspec:VI248_VLBW - [(match_operand:VI248_VLBW 1 "register_operand" "0") - (match_operand:VI248_VLBW 2 "register_operand" "v") - (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] + [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v") + (unspec:VI248_AVX512VL + [(match_operand:VI248_AVX512VL 1 "register_operand" "0") + (match_operand:VI248_AVX512VL 2 "register_operand" "v") + (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")] UNSPEC_VPSHRDV))] "TARGET_AVX512VBMI2" "vpshrdv\t{%3, %2, %0|%0, %2, %3 }" @@ -20168,12 +20168,12 @@ (define_insn "vpshrdv_" (set_attr "mode" "")]) (define_insn "vpshrdv__mask" - [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") - (vec_merge:VI248_VLBW - (unspec:VI248_VLBW - [(match_operand:VI248_VLBW 1 "register_operand" "0") - (match_operand:VI248_VLBW 2 "register_operand" "v") - (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] + [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI248_AVX512VL + (unspec:VI248_AVX512VL + [(match_operand:VI248_AVX512VL 1 "register_operand" "0") + (match_operand:VI248_AVX512VL 2 "register_operand" "v") + (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")] UNSPEC_VPSHRDV) (match_dup 1) (match_operand: 4 "register_operand" "Yk")))] @@ -20183,10 +20183,10 @@ (define_insn "vpshrdv__mask" (set_attr "mode" "")]) (define_expand "vpshrdv__maskz" - [(match_operand:VI248_VLBW 0 "register_operand") - (match_operand:VI248_VLBW 1 "register_operand") - (match_operand:VI248_VLBW 2 "register_operand") - (match_operand:VI248_VLBW 3 "nonimmediate_operand") + [(match_operand:VI248_AVX512VL 0 "register_operand") + (match_operand:VI248_AVX512VL 1 "register_operand") + (match_operand:VI248_AVX512VL 2 "register_operand") + (match_operand:VI248_AVX512VL 3 "nonimmediate_operand") (match_operand: 4 "register_operand")] "TARGET_AVX512VBMI2" { @@ -20198,14 +20198,14 @@ (define_expand "vpshrdv__maskz" }) (define_insn "vpshrdv__maskz_1" - [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") - (vec_merge:VI248_VLBW - (unspec:VI248_VLBW - [(match_operand:VI248_VLBW 1 "register_operand" "0") - (match_operand:VI248_VLBW 2 "register_operand" "v") - (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] + [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI248_AVX512VL + (unspec:VI248_AVX512VL + [(match_operand:VI248_AVX512VL 1 "register_operand" "0") + (match_operand:VI248_AVX512VL 2 "register_operand" "v") + (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")] UNSPEC_VPSHRDV) - (match_operand:VI248_VLBW 4 "const0_operand" "C") + (match_operand:VI248_AVX512VL 4 "const0_operand" "C") (match_operand: 5 "register_operand" "Yk")))] "TARGET_AVX512VBMI2" "vpshrdv\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" @@ -20213,11 +20213,11 @@ (define_insn "vpshrdv__maskz_1" (set_attr "mode" "")]) (define_insn "vpshldv_" - [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") - (unspec:VI248_VLBW - [(match_operand:VI248_VLBW 1 "register_operand" "0") - (match_operand:VI248_VLBW 2 "register_operand" "v") - (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] + [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v") + (unspec:VI248_AVX512VL + [(match_operand:VI248_AVX512VL 1 "register_operand" "0") + (match_operand:VI248_AVX512VL 2 "register_operand" "v") + (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")] UNSPEC_VPSHLDV))] "TARGET_AVX512VBMI2" "vpshldv\t{%3, %2, %0|%0, %2, %3 }" @@ -20225,12 +20225,12 @@ (define_insn "vpshldv_" (set_attr "mode" "")]) (define_insn "vpshldv__mask" - [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") - (vec_merge:VI248_VLBW - (unspec:VI248_VLBW - [(match_operand:VI248_VLBW 1 "register_operand" "0") - (match_operand:VI248_VLBW 2 "register_operand" "v") - (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] + [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI248_AVX512VL + (unspec:VI248_AVX512VL + [(match_operand:VI248_AVX512VL 1 "register_operand" "0") + (match_operand:VI248_AVX512VL 2 "register_operand" "v") + (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")] UNSPEC_VPSHLDV) (match_dup 1) (match_operand: 4 "register_operand" "Yk")))] @@ -20240,10 +20240,10 @@ (define_insn "vpshldv__mask" (set_attr "mode" "")]) (define_expand "vpshldv__maskz" - [(match_operand:VI248_VLBW 0 "register_operand") - (match_operand:VI248_VLBW 1 "register_operand") - (match_operand:VI248_VLBW 2 "register_operand") - (match_operand:VI248_VLBW 3 "nonimmediate_operand") + [(match_operand:VI248_AVX512VL 0 "register_operand") + (match_operand:VI248_AVX512VL 1 "register_operand") + (match_operand:VI248_AVX512VL 2 "register_operand") + (match_operand:VI248_AVX512VL 3 "nonimmediate_operand") (match_operand: 4 "register_operand")] "TARGET_AVX512VBMI2" { @@ -20255,14 +20255,14 @@ (define_expand "vpshldv__maskz" }) (define_insn "vpshldv__maskz_1" - [(set (match_operand:VI248_VLBW 0 "register_operand" "=v") - (vec_merge:VI248_VLBW - (unspec:VI248_VLBW - [(match_operand:VI248_VLBW 1 "register_operand" "0") - (match_operand:VI248_VLBW 2 "register_operand" "v") - (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")] + [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI248_AVX512VL + (unspec:VI248_AVX512VL + [(match_operand:VI248_AVX512VL 1 "register_operand" "0") + (match_operand:VI248_AVX512VL 2 "register_operand" "v") + (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")] UNSPEC_VPSHLDV) - (match_operand:VI248_VLBW 4 "const0_operand" "C") + (match_operand:VI248_AVX512VL 4 "const0_operand" "C") (match_operand: 5 "register_operand" "Yk")))] "TARGET_AVX512VBMI2" "vpshldv\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" --- gcc/testsuite/gcc.target/i386/pr83604.c.jj 2017-12-27 19:33:19.835077783 +0100 +++ gcc/testsuite/gcc.target/i386/pr83604.c 2017-12-27 19:32:37.661052000 +0100 @@ -0,0 +1,11 @@ +/* PR target/83604 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx" } */ + +typedef short V __attribute__((__vector_size__(64))); + +__attribute__((target ("avx512vbmi2"))) V +foo (V x, V y, V z) +{ + return __builtin_ia32_vpshrdv_v32hi (x, y, z); +}