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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id k20sm14770988qtb.34.2020.09.14.07.23.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2020 07:23:16 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: alankao@andestech.com, Leo Liang , Heinrich Schuchardt , Bin Meng , Rick Chen , Sean Anderson Subject: [PATCH v2 1/7] Revert "riscv: Clear pending interrupts before enabling IPIs" Date: Mon, 14 Sep 2020 10:22:57 -0400 Message-Id: <20200914142303.21307-2-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200914142303.21307-1-seanga2@gmail.com> References: <20200914142303.21307-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Clearing MIP.MSIP is not guaranteed to do anything by the spec. In addition, most existing RISC-V hardware does nothing when this bit is set. The following commits "riscv: Use a valid bit to ignore already-pending IPIs" and "riscv: Clear pending IPIs on initialization" should implement the original intent of the reverted commit in a more robust manner. This reverts commit 9472630337e7c4ac442066b5a752aaa8c3b4d4a6. Signed-off-by: Sean Anderson Reviewed-by: Bin Meng --- I know there is still some discussion in the last series on whether to include this commit, but I'd like to put out another revision and get feedback. (no changes since v1) arch/riscv/cpu/start.S | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index bf9fdf369b..e3222b1ea7 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -65,8 +65,6 @@ _start: #else li t0, SIE_SSIE #endif - /* Clear any pending IPIs */ - csrc MODE_PREFIX(ip), t0 csrs MODE_PREFIX(ie), t0 #endif From patchwork Mon Sep 14 14:22:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 1363642 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=Qp+SANYl; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BqpWP6cPLz9sV1 for ; Tue, 15 Sep 2020 00:23:45 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1FABD82319; Mon, 14 Sep 2020 16:23:26 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Qp+SANYl"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 89A33821ED; Mon, 14 Sep 2020 16:23:22 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-qt1-x843.google.com (mail-qt1-x843.google.com [IPv6:2607:f8b0:4864:20::843]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A9E2D81996 for ; Mon, 14 Sep 2020 16:23:19 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=seanga2@gmail.com Received: by mail-qt1-x843.google.com with SMTP id p65so13591046qtd.2 for ; Mon, 14 Sep 2020 07:23:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jkvHO5kOKNVVLaIuvobXZdymCZ4LpSHu602oT1pGDuA=; b=Qp+SANYlfToSrhPTmIPqMj+M1TJPLce7OuKp0Z8Re3t9n7FdogmBd0Hf9bsqaCz9Fx DJahpoTEsKkKC86BJ+d88DtwPr/IJ/pqm28a+6F2XEbgGOUaBAzZiwkMthu+9oDcoEmJ NbCBzgoyY87nKqi2yKcH2MgKOgYFL1aiWSZI4C44AuNtyasdzQbYByD7i1iqpj7jdXE4 cCN8FPe5fBrX+NENGU8zjsN1IQxx/HZBF8ZxCbR4b1eVKWqfx9lqou7cKFD3N8+i/Fru 05h/vsbCEJ4Amptfr/gunBUoBErSgxuhkPByYwGp6b4HhzuJylH2H1G/fWycDWtQN1fj O8jA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jkvHO5kOKNVVLaIuvobXZdymCZ4LpSHu602oT1pGDuA=; b=h1o7BdMMHSfivaoWuYxoKiIVP1qQJe2gJ9B6PulFtBpMA63jYezAr04Jtj6wg2szxV qLphXxxeFY7xvVEIhccwlfmVc9rmnpVeQ5dIsg5QUBZYA/tkEju8YiFDKCZLxNBnZcPO 98jh85to6eb2ByeTN25ykW8OLrrK3BcQJwyQ6PGav2sTvu0gXIIwX3/4c6Xpu4hW7u/0 DQIUIm7ma0W7pGw3XVasIqeO2BIoQMYzIthg1IG2XLhSoPj2OPhAR/pjcOb+irzOAG7H +4OYWXbY1dlRYcYm4WcPk80QPmJGuREiO4HPo+cwqjJC7+trwQwZsE4+4CNyBfdyslsl yJLA== X-Gm-Message-State: AOAM533EzC5/iRCRfK+KWtrDfmhyVtfqZ6qnOvo839IGMDs4s14W+Aey WHU5TYuhvPGqiI2Dfq1DDq1iX6Mmu7ugwg== X-Google-Smtp-Source: ABdhPJzJRar9fe24DixxyRG9hyq8HyNamQmE2b6Bf7cwe/xbQINEZ7l3WqhkZwJMsf1xkeCiFFkfwA== X-Received: by 2002:aed:2907:: with SMTP id s7mr12415902qtd.321.1600093398448; Mon, 14 Sep 2020 07:23:18 -0700 (PDT) Received: from godwin.fios-router.home (pool-108-51-35-162.washdc.fios.verizon.net. [108.51.35.162]) by smtp.gmail.com with ESMTPSA id k20sm14770988qtb.34.2020.09.14.07.23.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2020 07:23:17 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: alankao@andestech.com, Leo Liang , Heinrich Schuchardt , Bin Meng , Rick Chen , Sean Anderson , Bin Meng Subject: [PATCH v2 2/7] riscv: Match memory barriers between send_ipi_many and handle_ipi Date: Mon, 14 Sep 2020 10:22:58 -0400 Message-Id: <20200914142303.21307-3-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200914142303.21307-1-seanga2@gmail.com> References: <20200914142303.21307-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Without a matching barrier on the write side, the barrier in handle_ipi does nothing. It was entirely possible for the boot hart to write to addr, arg0, and arg1 *after* sending the IPI, because there was no barrier on the sending side. Fixes: 90ae281437 ("riscv: add option to wait for ack from secondary harts in smp functions") Signed-off-by: Sean Anderson Reviewed-by: Bin Meng Reviewed-by: Rick Chen Reviewed-by: Leo Liang --- (no changes since v1) arch/riscv/lib/smp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index ac22136314..ab6d8bd7fa 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -54,6 +54,8 @@ static int send_ipi_many(struct ipi_data *ipi, int wait) gd->arch.ipi[reg].arg0 = ipi->arg0; gd->arch.ipi[reg].arg1 = ipi->arg1; + __smp_mb(); + ret = riscv_send_ipi(reg); if (ret) { pr_err("Cannot send IPI to hart %d\n", reg); From patchwork Mon Sep 14 14:22:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 1363643 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=Sm3CY8vI; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BqpWd72qwz9sTq for ; Tue, 15 Sep 2020 00:23:57 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5B03882314; Mon, 14 Sep 2020 16:23:27 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Sm3CY8vI"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 67E7D82304; Mon, 14 Sep 2020 16:23:23 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-qk1-x743.google.com (mail-qk1-x743.google.com [IPv6:2607:f8b0:4864:20::743]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B6A3481BD2 for ; Mon, 14 Sep 2020 16:23:20 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=seanga2@gmail.com Received: by mail-qk1-x743.google.com with SMTP id g72so206780qke.8 for ; Mon, 14 Sep 2020 07:23:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wv1UGJvWTLqKY3P8UkrJiQZAlsSmgK7en4b/yUI/aos=; b=Sm3CY8vIrAifURwJvC6HXIUfMUgWV8h9kdnnOVh1aKvqmHGsmKzWj8E7MCvZUXpyIm Zr6tVxVjKXtQfhwFhOpm3Lm2Z7sQVQtKKaIZq80Ja6FHT6AEm7VD8OGmAb1WFwLfxeKH jMbcP8bSADMGK1Rh3+OsXU94pezTY9sw7JcuMll/Wa6UdjbQCPI8U/n/GCgy/ywe7XyJ wO4tU7xO5BAJn+g+8PPsV+3x/pdmRXHgYXQmxcV1l+wCt0wRwyLEIaGJ5zFN4cZsbp5/ 71tQLP44QGacJiP/mUjn++2uRfcGnoiNPOFY4NORR9ac9m7KLBcIsfZeJsB3rDNQzNuY oBmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wv1UGJvWTLqKY3P8UkrJiQZAlsSmgK7en4b/yUI/aos=; b=tJKANkAm60Z0KmS5opkc/2jbeGS/dINyUl9Iysfpt4S2K8MysO4NeJUrR4JQJmknbz CxusADPbkszqMoHIAPyhg+qYpXMFg9+UcVXRMl0ZkRYt1GMrTrfgZi9sJblqzIblAGRK 4lb9CT5PzIR6j4A/n101YXV/HDnmejuoJMASmC8a2KX1dsiZXKPatsNowwgYTQKlSQWc royXxRT70ZECouBpS7mlJCKAi1Q5HzU+TqNnEvwFQhImgmEOsdOiA9uPlYVW33cQm78r 0cnKpREpyMZEBviZPgliCGwL48IAyYcw11VJGiZekZGWQlD08G447GkI9qUs/LD6sJ7Q wvGA== X-Gm-Message-State: AOAM531ggA5bNl+2UjYL6bv271xMeRX6C7nIqt7bcjM4KOFBFpHHCd9R oEbD+fYGXTxGpR2qXDMG/BAlbBxLSNEabQ== X-Google-Smtp-Source: ABdhPJxd3i4UE3UeCr9Whwc3LbgNSEd5dBao5IzQH6+l2PLhfIrX0+zTnSW2jfd9VATL01NjyRwFtQ== X-Received: by 2002:a37:8902:: with SMTP id l2mr13401261qkd.415.1600093399453; Mon, 14 Sep 2020 07:23:19 -0700 (PDT) Received: from godwin.fios-router.home (pool-108-51-35-162.washdc.fios.verizon.net. [108.51.35.162]) by smtp.gmail.com with ESMTPSA id k20sm14770988qtb.34.2020.09.14.07.23.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2020 07:23:18 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: alankao@andestech.com, Leo Liang , Heinrich Schuchardt , Bin Meng , Rick Chen , Sean Anderson Subject: [PATCH v2 3/7] riscv: Use a valid bit to ignore already-pending IPIs Date: Mon, 14 Sep 2020 10:22:59 -0400 Message-Id: <20200914142303.21307-4-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200914142303.21307-1-seanga2@gmail.com> References: <20200914142303.21307-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Some IPIs may already be pending when U-Boot is started. This could be a problem if a secondary hart tries to handle an IPI before the boot hart has initialized the IPI device. This commit introduces a valid bit so secondary harts know when and IPI originates from U-boot, and it is safe to use the IPI API. The valid bit is initialized to 0 by board_init_f_init_reserve. Before this, secondary harts wait in wait_for_gd_init. Signed-off-by: Sean Anderson Reviewed-by: Bin Meng Reviewed-by: Rick Chen Reviewed-by: Leo Liang --- Changes in v2: - Use a valid bit instead of addr to validate IPIs arch/riscv/include/asm/smp.h | 7 +++++++ arch/riscv/lib/smp.c | 16 ++++++++++++++-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 1b428856b2..2dae0800ce 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -18,14 +18,21 @@ * IPI data structure. The hart ID is inserted by the hart handling the IPI and * calling the function. * + * @valid is used to determine whether a sent IPI originated from U-Boot. It is + * initialized to zero by board_init_f_alloc_reserve. When U-Boot sends its + * first IPI, it is set to 1. This prevents already-pending IPIs not sent by + * U-Boot from being taken. + * * @addr: Address of function * @arg0: First argument of function * @arg1: Second argument of function + * @valid: Whether this IPI is valid */ struct ipi_data { ulong addr; ulong arg0; ulong arg1; + unsigned int valid; }; /** diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index ab6d8bd7fa..8f33ce1fe3 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -54,7 +54,13 @@ static int send_ipi_many(struct ipi_data *ipi, int wait) gd->arch.ipi[reg].arg0 = ipi->arg0; gd->arch.ipi[reg].arg1 = ipi->arg1; - __smp_mb(); + /* + * Ensure valid only becomes set when the IPI parameters are + * set. An IPI may already be pending on other harts, so we + * need a way to signal that the IPI device has been + * initialized, and that it is ok to call the function. + */ + __smp_store_release(&gd->arch.ipi[reg].valid, 1); ret = riscv_send_ipi(reg); if (ret) { @@ -83,7 +89,13 @@ void handle_ipi(ulong hart) if (hart >= CONFIG_NR_CPUS) return; - __smp_mb(); + /* + * If valid is not set, then U-Boot has not requested the IPI. The + * IPI device may not be initialized, so all we can do is wait for + * U-Boot to initialize it and send an IPI + */ + if (!__smp_load_acquire(&gd->arch.ipi[hart].valid)) + return; smp_function = (void (*)(ulong, ulong, ulong))gd->arch.ipi[hart].addr; invalidate_icache_all(); From patchwork Mon Sep 14 14:23:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 1363645 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=Kj2kDzed; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BqpX06czJz9sT6 for ; Tue, 15 Sep 2020 00:24:16 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 23DE282332; Mon, 14 Sep 2020 16:23:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Kj2kDzed"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4E5048230E; Mon, 14 Sep 2020 16:23:24 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-qv1-xf43.google.com (mail-qv1-xf43.google.com [IPv6:2607:f8b0:4864:20::f43]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B5EDF808B2 for ; Mon, 14 Sep 2020 16:23:21 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=seanga2@gmail.com Received: by mail-qv1-xf43.google.com with SMTP id h1so9004944qvo.9 for ; Mon, 14 Sep 2020 07:23:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vp6tPwWy+UrdhUd6Ybj40Jv/jZPzK47gnT4dAKWaFhk=; b=Kj2kDzedZQVMCjzaZc1529UR63wSwzMh3OoPPP3KbMhFBOrcrFtt729a6Rg22EFvgx QfR0It3B0lcPxl00iu5ATSCxgGYfBFecWd7YaSMg67ubpKPrRPYCcaSylABDRGCZ7+sn pb+zQpKsz2RWNgT0Cvu3a/XRPWEsjuohN1T6vMi2VEOYVqWE0BO2rwXCHZcIzjpaywDg vK2XKUcLYhZohvo5oa2bh6RCQZAuci/0rIzW3t8DBI1YaiUuAzHNp61z9EQi9jtWj4Ge dg4GE1U1qz53UCXF44R4aB9f1sx2ez4uITkRquJtRyQPqPnAlNWTRDGlVcWP3VhPKiY8 iIYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vp6tPwWy+UrdhUd6Ybj40Jv/jZPzK47gnT4dAKWaFhk=; b=JTq+dIOZoGyoP4kOwmMQfjbT9JUsJPbasSNt20X5gUWS6I0IP2rCL6idYYSdOMy8dp Rshmln9UZkH3kIq2xfBIcElFjkks4DXHfFqZAjSmau8r+jf+LJIFl7cj4a2f4+EOVcT3 /gr1BWmlJx3FlchD1iq2d3enFiqqAPEzVoP7ZDj3MKmkfPnErPWoUzLYhaYO1OSxc1E7 7kwuGUjmitANqyhanA7qFG4ISvEE7bo/uOR9wVkCuhmOdkf5VYhmtufJ8R0/Gjw0YWZ9 d8eUIhrruNBjNHeHPjGq+xlzPqqvh4PV0+PbXLqXbEsmEIAeiAG5kN//a0NO2HoI2plr 58Mg== X-Gm-Message-State: AOAM5301FvuuQgr83mwv4hiMF5ynUL6jR5b7IsOHsGlY1ErQjIVNnV25 o9WJE4Co3X43fPfseQPiphu+lqvSy4gK+g== X-Google-Smtp-Source: ABdhPJwjMYkizF7Csa+vxcM7V431pDGWe7KUueqpdqcUxnvmZ62CJYZFmYDv7ZgCojiZzbSH8BXQrQ== X-Received: by 2002:a05:6214:a61:: with SMTP id ef1mr13968726qvb.115.1600093400455; Mon, 14 Sep 2020 07:23:20 -0700 (PDT) Received: from godwin.fios-router.home (pool-108-51-35-162.washdc.fios.verizon.net. [108.51.35.162]) by smtp.gmail.com with ESMTPSA id k20sm14770988qtb.34.2020.09.14.07.23.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2020 07:23:20 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: alankao@andestech.com, Leo Liang , Heinrich Schuchardt , Bin Meng , Rick Chen , Sean Anderson , Bin Meng Subject: [PATCH v2 4/7] riscv: Clear pending IPIs on initialization Date: Mon, 14 Sep 2020 10:23:00 -0400 Message-Id: <20200914142303.21307-5-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200914142303.21307-1-seanga2@gmail.com> References: <20200914142303.21307-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Even though we no longer call smp_function if an IPI was not sent by U-Boot, we still need to clear any IPIs which were pending from the execution environment. Otherwise, secondary harts will busy-wait in secondary_hart_loop, instead of relaxing. Signed-off-by: Sean Anderson Reviewed-by: Bin Meng --- Changes in v2: - Make riscv_ipi_init_secondary_hart static arch/riscv/cpu/cpu.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index bfa2d4a426..ab08af5a33 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -72,6 +72,15 @@ static int riscv_cpu_probe(void) return 0; } +/* + * This is called on secondary harts just after the IPI is init'd. Currently + * there's nothing to do, since we just need to clear any existing IPIs, and + * that is handled by the sending of an ipi itself. + */ +static void riscv_ipi_init_secondary_hart(ulong hart, ulong arg0, ulong arg1) +{ +} + int arch_cpu_init_dm(void) { int ret; @@ -111,6 +120,15 @@ int arch_cpu_init_dm(void) ret = riscv_init_ipi(); if (ret) return ret; + + /* + * Clear all pending IPIs on secondary harts. We don't do anything on + * the boot hart, since we never send an IPI to ourselves, and no + * interrupts are enabled + */ + ret = smp_call_function((ulong)riscv_ipi_init_secondary_hart, 0, 0, 0); + if (ret) + return ret; #endif return 0; From patchwork Mon Sep 14 14:23:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 1363647 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=sDE+eToS; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BqpXB4CcGz9sT6 for ; Tue, 15 Sep 2020 00:24:26 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1381A82336; Mon, 14 Sep 2020 16:23:31 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="sDE+eToS"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 7085982317; Mon, 14 Sep 2020 16:23:25 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-qv1-xf44.google.com (mail-qv1-xf44.google.com [IPv6:2607:f8b0:4864:20::f44]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id DF6CD821A4 for ; Mon, 14 Sep 2020 16:23:22 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=seanga2@gmail.com Received: by mail-qv1-xf44.google.com with SMTP id b13so9028071qvl.2 for ; Mon, 14 Sep 2020 07:23:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eHxDIWQSQJk1gNvi7MXDOlxcdWShEH19hlgdNmBvj/I=; b=sDE+eToSUWeC6b52+IqGLSgjhAscMc1o5Ab7Yp5CnjvmcAAw7TIEwm8NBN7CgVi5Xh YZA7HTFwfGtFret1XdG5T0Y1oyfdt3R2t7Z5GlyQDhauEWC322N/o3YWpdBPhoiGtsqh IagirZAO5CI3yGsKHin0JdnYfgMkZtP1fOrvvZoGaHGQRCffcE3GfbWS0Hg+ydT9Q89b 9gVhtzK+b3BMHt4rYk7Os7kU4cxZUDVe62sisQTB4ndcbiz2klPt42bCtwERpkBDYlZg 0lB/30OuoE/qVv/A6Qt9w2qWNJJcJV9OVbai76nxS1EMW86PnRMCqFnDnlxVg9FphFTw ebRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eHxDIWQSQJk1gNvi7MXDOlxcdWShEH19hlgdNmBvj/I=; b=bIFgyqcVNPIr3LkVoh321DRDi4ke4bDJdEbUYZ3+ys5znvmLM/ejVR15hJlzj/qXY1 ezI5Trdhoip9HsdtCG56FOdQ7B5pSL+hOU3Ufb7SLNlF9jTWXoyKA8Zh04IDhUNFddbr r67jR8ZBsQQLibDCGl/VpH4hOnKzT+QdmCw8DfXQvwrMny2C1/YukFTKSdrW8aDpJbY2 idPcEjgkmRqfW+dORJ4tbrV40UJgBlMrtCfm70OmhFoSbzrKkITRY8tZrPlOKP8VzKTY pOgIk2JUpll08Ctro0aS6NBktzhsYFOO+SI42K9BQYsa2u0t+yJ3IZ5SwYmdDbV4XKFt vMOA== X-Gm-Message-State: AOAM531/HM8x6JgHkzbeOq4K9I1bPA1seSOMT/LNCNUN8qbJvg1t8kQD wGSrhIbrkrslcOP/NtTzR/63QzSdCrauxw== X-Google-Smtp-Source: ABdhPJw+5jAySeXVZfB7io4VezG1cXeOEt4jxJnBew/oIZfVCRQIohT4XLTU4L3XSKYjFJu4SktVpA== X-Received: by 2002:a0c:eac5:: with SMTP id y5mr13454132qvp.2.1600093401456; Mon, 14 Sep 2020 07:23:21 -0700 (PDT) Received: from godwin.fios-router.home (pool-108-51-35-162.washdc.fios.verizon.net. [108.51.35.162]) by smtp.gmail.com with ESMTPSA id k20sm14770988qtb.34.2020.09.14.07.23.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2020 07:23:20 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: alankao@andestech.com, Leo Liang , Heinrich Schuchardt , Bin Meng , Rick Chen , Sean Anderson Subject: [PATCH v2 5/7] riscv: Consolidate fences into AMOs for available_harts_lock Date: Mon, 14 Sep 2020 10:23:01 -0400 Message-Id: <20200914142303.21307-6-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200914142303.21307-1-seanga2@gmail.com> References: <20200914142303.21307-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean We can reduce the number of instructions needed to use available_harts_lock by using the aq and rl suffixes for AMOs. Signed-off-by: Sean Anderson Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- Changes in v2: - Remove fences after amoswaps - Reword commit message arch/riscv/cpu/start.S | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index e3222b1ea7..66ca1c7020 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -125,14 +125,12 @@ call_board_init_f_0: #ifndef CONFIG_XIP la t0, available_harts_lock - fence rw, w - amoswap.w zero, zero, 0(t0) + amoswap.w.rl zero, zero, 0(t0) wait_for_gd_init: la t0, available_harts_lock li t1, 1 -1: amoswap.w t1, t1, 0(t0) - fence r, rw +1: amoswap.w.aq t1, t1, 0(t0) bnez t1, 1b /* register available harts in the available_harts mask */ @@ -142,8 +140,7 @@ wait_for_gd_init: or t2, t2, t1 SREG t2, GD_AVAILABLE_HARTS(gp) - fence rw, w - amoswap.w zero, zero, 0(t0) + amoswap.w.rl zero, zero, 0(t0) /* * Continue on hart lottery winner, others branch to From patchwork Mon Sep 14 14:23:02 2020 Content-Type: text/plain; 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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id k20sm14770988qtb.34.2020.09.14.07.23.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2020 07:23:21 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: alankao@andestech.com, Leo Liang , Heinrich Schuchardt , Bin Meng , Rick Chen , Sean Anderson Subject: [PATCH v2 6/7] riscv: Ensure gp is NULL or points to valid data Date: Mon, 14 Sep 2020 10:23:02 -0400 Message-Id: <20200914142303.21307-7-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200914142303.21307-1-seanga2@gmail.com> References: <20200914142303.21307-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean This allows code to use a construct like `if (gd & gd->...) { ... }` when accessing the global data pointer. Without this change, it was possible for a very early trap to cause _exit_trap to read arbitrary memory. This could cause a second trap, preventing show_regs from being printed. XIP cannot use locks because flash is not writable. This leaves it vulnerable to the same class of bugs regarding already-pending IPIs as before this series. Fixing that would require finding another method of synchronization, which is outside the scope of this series. Fixes: 7c6ca03eae ("riscv: additional crash information") Signed-off-by: Sean Anderson Reviewed-by: Bin Meng --- Changes in v2: - Set gp early with XIP arch/riscv/cpu/start.S | 26 +++++++++++++++++++++++--- arch/riscv/lib/interrupts.c | 3 ++- 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 66ca1c7020..a16af79fbe 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -47,6 +47,13 @@ _start: mv tp, a0 mv s1, a1 + /* + * Set the global data pointer to a known value in case we get a very + * early trap. The global data pointer will be set its actual value only + * after it has been initialized. + */ + mv gp, zero + la t0, trap_entry csrw MODE_PREFIX(tvec), t0 @@ -85,10 +92,10 @@ call_board_init_f_0: jal board_init_f_alloc_reserve /* - * Set global data pointer here for all harts, uninitialized at this - * point. + * Save global data pointer for later. We don't set it here because it + * is not initialized yet. */ - mv gp, a0 + mv s0, a0 /* setup stack */ #if CONFIG_IS_ENABLED(SMP) @@ -109,6 +116,12 @@ call_board_init_f_0: amoswap.w s2, t1, 0(t0) bnez s2, wait_for_gd_init #else + /* + * FIXME: gp is set before it is initialized. If an XIP U-Boot ever + * encounters a pending IPI on boot it is liable to jump to whatever + * memory happens to be in ipi_data.addr on boot. + */ + mv gp, s0 bnez tp, secondary_hart_loop #endif @@ -133,6 +146,13 @@ wait_for_gd_init: 1: amoswap.w.aq t1, t1, 0(t0) bnez t1, 1b + /* + * Set the global data pointer only when gd_t has been initialized. + * This was already set by arch_setup_gd on the boot hart, but all other + * harts' global data pointers gets set here. + */ + mv gp, s0 + /* register available harts in the available_harts mask */ li t1, 1 sll t1, t1, tp diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index cd47e64487..ad870e98d8 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -78,7 +78,8 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) printf("EPC: " REG_FMT " RA: " REG_FMT " TVAL: " REG_FMT "\n", epc, regs->ra, tval); - if (gd->flags & GD_FLG_RELOC) + /* Print relocation adjustments, but only if gd is initialized */ + if (gd && gd->flags & GD_FLG_RELOC) printf("EPC: " REG_FMT " RA: " REG_FMT " reloc adjusted\n\n", epc - gd->reloc_off, regs->ra - gd->reloc_off); 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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id k20sm14770988qtb.34.2020.09.14.07.23.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2020 07:23:22 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: alankao@andestech.com, Leo Liang , Heinrich Schuchardt , Bin Meng , Rick Chen , Sean Anderson Subject: [PATCH v2 7/7] riscv: Add some comments to start.S Date: Mon, 14 Sep 2020 10:23:03 -0400 Message-Id: <20200914142303.21307-8-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200914142303.21307-1-seanga2@gmail.com> References: <20200914142303.21307-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean This adds comments regarding the ordering and purpose of certain instructions as I understand them. Signed-off-by: Sean Anderson Reviewed-by: Bin Meng Reviewed-by: Rick Chen Reviewed-by: Leo Liang --- Changes in v2: - Clarify comments regarding tp arch/riscv/cpu/start.S | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index a16af79fbe..cb1347559c 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -43,7 +43,10 @@ _start: csrr a0, CSR_MHARTID #endif - /* save hart id and dtb pointer */ + /* + * Save hart id and dtb pointer. The thread pointer register is not + * modified by C code. It is used by secondary_hart_loop. + */ mv tp, a0 mv s1, a1 @@ -54,10 +57,18 @@ _start: */ mv gp, zero + /* + * Set the trap handler. This must happen after initializing gp because + * the handler may use it. + */ la t0, trap_entry csrw MODE_PREFIX(tvec), t0 - /* mask all interrupts */ + /* + * Mask all interrupts. Interrupts are disabled globally (in m/sstatus) + * for U-Boot, but we will need to read m/sip to determine if we get an + * IPI + */ csrw MODE_PREFIX(ie), zero #if CONFIG_IS_ENABLED(SMP) @@ -410,6 +421,10 @@ secondary_hart_relocate: mv gp, a2 #endif +/* + * Interrupts are disabled globally, but they can still be read from m/sip. The + * wfi function will wake us up if we get an IPI, even if we do not trap. + */ secondary_hart_loop: wfi