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Mon, 14 Sep 2020 14:19:52 +0000 Received: from VE1PR08MB5599.eurprd08.prod.outlook.com ([fe80::60b7:2d8b:81cb:bc0d]) by VE1PR08MB5599.eurprd08.prod.outlook.com ([fe80::60b7:2d8b:81cb:bc0d%3]) with mapi id 15.20.3370.019; Mon, 14 Sep 2020 14:19:52 +0000 From: Wilco Dijkstra To: GCC Patches Subject: [PATCH 1/2] AArch64: Cleanup CPU option processing code Thread-Topic: [PATCH 1/2] AArch64: Cleanup CPU option processing code Thread-Index: AQHWiqHMJF4CfrGTTUSKWpfl0ovDqg== Date: Mon, 14 Sep 2020 14:19:52 +0000 Message-ID: Accept-Language: en-GB, en-US Content-Language: en-GB X-MS-Has-Attach: X-MS-TNEF-Correlator: Authentication-Results-Original: gcc.gnu.org; dkim=none (message not signed) header.d=none;gcc.gnu.org; dmarc=none action=none header.from=arm.com; x-originating-ip: [82.24.199.97] x-ms-publictraffictype: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 96f7f370-98c3-44df-9d35-08d858b94446 x-ms-traffictypediagnostic: VI1PR08MB2990:|DB6PR08MB2885: x-ms-exchange-transport-forked: True X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true nodisclaimer: true x-ms-oob-tlc-oobclassifiers: OLM:207;OLM:207; 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DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2020 14:20:00.9458 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 96f7f370-98c3-44df-9d35-08d858b94446 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT024.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR08MB2885 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_LOTSOFHASH, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Earnshaw Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" The --with-cpu/--with-arch configure option processing not only checks valid arguments but also sets TARGET_CPU_DEFAULT with a CPU and extension bitmask. This isn't used however since a --with-cpu is translated into a -mcpu option which is processed as if written on the command-line (so TARGET_CPU_DEFAULT is never accessed). So remove all the complex processing and bitmask, and just validate the option. Fix a bug that always reports valid architecture extensions as invalid. As a result the CPU processing in aarch64.c can be simplified. Bootstrap OK, regress pass, OK for commit? ChangeLog: 2020-09-03 Wilco Dijkstra * config.gcc (aarch64*-*-*): Simplify --with-cpu and --with-arch processing. Add support for architectural extensions. * config/aarch64/aarch64.h (TARGET_CPU_DEFAULT): Remove AARCH64_CPU_DEFAULT_FLAGS. * config/aarch64/aarch64.c (AARCH64_CPU_DEFAULT_FLAGS): Remove define. (get_tune_cpu): Assert CPU is always valid. (get_arch): Assert architecture is always valid. (aarch64_override_options): Cleanup CPU selection code and simplify logic. diff --git a/gcc/config.gcc b/gcc/config.gcc index 88e428fd2ad0fb605a53f5dfa58d9f14603b4302..918320573ade712ddc252045e0b70fb8b65e0c66 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -4067,8 +4067,6 @@ case "${target}" in pattern=AARCH64_CORE fi - ext_mask=AARCH64_CPU_DEFAULT_FLAGS - # Find the base CPU or ARCH id in aarch64-cores.def or # aarch64-arches.def if [ x"$base_val" = x ] \ @@ -4076,23 +4074,6 @@ case "${target}" in ${srcdir}/config/aarch64/$def \ > /dev/null; then - if [ $which = arch ]; then - base_id=`grep "^$pattern(\"$base_val\"," \ - ${srcdir}/config/aarch64/$def | \ - sed -e 's/^[^,]*,[ ]*//' | \ - sed -e 's/,.*$//'` - # Extract the architecture flags from aarch64-arches.def - ext_mask=`grep "^$pattern(\"$base_val\"," \ - ${srcdir}/config/aarch64/$def | \ - sed -e 's/)$//' | \ - sed -e 's/^.*,//'` - else - base_id=`grep "^$pattern(\"$base_val\"," \ - ${srcdir}/config/aarch64/$def | \ - sed -e 's/^[^,]*,[ ]*//' | \ - sed -e 's/,.*$//'` - fi - # Use the pre-processor to strip flatten the options. # This makes the format less rigid than if we use # grep and sed directly here. @@ -4117,25 +4098,7 @@ case "${target}" in grep "^\"$base_ext\""` if [ x"$base_ext" = x ] \ - || [[ -n $opt_line ]]; then - - # These regexp extract the elements based on - # their group match index in the regexp. - ext_canon=`echo -e "$opt_line" | \ - sed -e "s/$sed_patt/\2/"` - ext_on=`echo -e "$opt_line" | \ - sed -e "s/$sed_patt/\3/"` - ext_off=`echo -e "$opt_line" | \ - sed -e "s/$sed_patt/\4/"` - - if [ $ext = $base_ext ]; then - # Adding extension - ext_mask="("$ext_mask") | ("$ext_on" | "$ext_canon")" - else - # Removing extension - ext_mask="("$ext_mask") & ~("$ext_off" | "$ext_canon")" - fi - + || [ x"$opt_line" != x ]; then true else echo "Unknown extension used in --with-$which=$val" 1>&2 @@ -4144,10 +4107,6 @@ case "${target}" in ext_val=`echo $ext_val | sed -e 's/[a-z0-9]\+//'` done - ext_mask="(("$ext_mask") << 6)" - if [ x"$base_id" != x ]; then - target_cpu_cname="TARGET_CPU_$base_id | $ext_mask" - fi true else echo "Unknown $which used in --with-$which=$val" 1>&2 diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index d3e89d1789a23c2fa4d62744084adfdedac6a116..30b3a28a6d2893cc29bec4aa5b7cfbe1fd51e0b7 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -767,8 +767,7 @@ enum target_cpus /* If there is no CPU defined at configure, use generic as default. */ #ifndef TARGET_CPU_DEFAULT -#define TARGET_CPU_DEFAULT \ - (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6)) +# define TARGET_CPU_DEFAULT TARGET_CPU_generic #endif /* If inserting NOP before a mult-accumulate insn remember to adjust the diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 24b455fd627bca1bdd7d81d5933aa46275061d7c..803562df25751f2eb6dbe18b67cae46ea7c478dd 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -1472,8 +1472,6 @@ static const struct attribute_spec aarch64_attribute_table[] = { NULL, 0, 0, false, false, false, false, NULL, NULL } }; -#define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0) - /* An ISA extension in the co-processor and main instruction set space. */ struct aarch64_option_extension { @@ -14824,35 +14822,24 @@ aarch64_validate_mtune (const char *str, const struct processor **res) return false; } -/* Return the CPU corresponding to the enum CPU. - If it doesn't specify a cpu, return the default. */ +/* Return the CPU corresponding to the enum CPU. */ static const struct processor * aarch64_get_tune_cpu (enum aarch64_processor cpu) { - if (cpu != aarch64_none) - return &all_cores[cpu]; + gcc_assert (cpu != aarch64_none); - /* The & 0x3f is to extract the bottom 6 bits that encode the - default cpu as selected by the --with-cpu GCC configure option - in config.gcc. - ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS - flags mechanism should be reworked to make it more sane. */ - return &all_cores[TARGET_CPU_DEFAULT & 0x3f]; + return &all_cores[cpu]; } -/* Return the architecture corresponding to the enum ARCH. - If it doesn't specify a valid architecture, return the default. */ +/* Return the architecture corresponding to the enum ARCH. */ static const struct processor * aarch64_get_arch (enum aarch64_arch arch) { - if (arch != aarch64_no_arch) - return &all_architectures[arch]; - - const struct processor *cpu = &all_cores[TARGET_CPU_DEFAULT & 0x3f]; + gcc_assert (arch != aarch64_no_arch); - return &all_architectures[cpu->arch]; + return &all_architectures[arch]; } /* Return the VG value associated with -msve-vector-bits= value VALUE. */ @@ -14890,10 +14877,6 @@ aarch64_override_options (void) uint64_t arch_isa = 0; aarch64_isa_flags = 0; - bool valid_cpu = true; - bool valid_tune = true; - bool valid_arch = true; - selected_cpu = NULL; selected_arch = NULL; selected_tune = NULL; @@ -14908,77 +14891,56 @@ aarch64_override_options (void) If either of -march or -mtune is given, they override their respective component of -mcpu. */ if (aarch64_cpu_string) - valid_cpu = aarch64_validate_mcpu (aarch64_cpu_string, &selected_cpu, - &cpu_isa); + aarch64_validate_mcpu (aarch64_cpu_string, &selected_cpu, &cpu_isa); if (aarch64_arch_string) - valid_arch = aarch64_validate_march (aarch64_arch_string, &selected_arch, - &arch_isa); + aarch64_validate_march (aarch64_arch_string, &selected_arch, &arch_isa); if (aarch64_tune_string) - valid_tune = aarch64_validate_mtune (aarch64_tune_string, &selected_tune); + aarch64_validate_mtune (aarch64_tune_string, &selected_tune); #ifdef SUBTARGET_OVERRIDE_OPTIONS SUBTARGET_OVERRIDE_OPTIONS; #endif - /* If the user did not specify a processor, choose the default - one for them. This will be the CPU set during configuration using - --with-cpu, otherwise it is "generic". */ - if (!selected_cpu) - { - if (selected_arch) - { - selected_cpu = &all_cores[selected_arch->ident]; - aarch64_isa_flags = arch_isa; - explicit_arch = selected_arch->arch; - } - else - { - /* Get default configure-time CPU. */ - selected_cpu = aarch64_get_tune_cpu (aarch64_none); - aarch64_isa_flags = TARGET_CPU_DEFAULT >> 6; - } - - if (selected_tune) - explicit_tune_core = selected_tune->ident; - } - /* If both -mcpu and -march are specified check that they are architecturally - compatible, warn if they're not and prefer the -march ISA flags. */ - else if (selected_arch) + if (selected_cpu && selected_arch) { + /* If both -mcpu and -march are specified, warn if they are not + architecturally compatible and prefer the -march ISA flags. */ if (selected_arch->arch != selected_cpu->arch) { warning (0, "switch %<-mcpu=%s%> conflicts with %<-march=%s%> switch", aarch64_cpu_string, aarch64_arch_string); } + aarch64_isa_flags = arch_isa; - explicit_arch = selected_arch->arch; - explicit_tune_core = selected_tune ? selected_tune->ident - : selected_cpu->ident; } - else + else if (selected_cpu) { - /* -mcpu but no -march. */ - aarch64_isa_flags = cpu_isa; - explicit_tune_core = selected_tune ? selected_tune->ident - : selected_cpu->ident; - gcc_assert (selected_cpu); selected_arch = &all_architectures[selected_cpu->arch]; - explicit_arch = selected_arch->arch; + aarch64_isa_flags = cpu_isa; } - - /* Set the arch as well as we will need it when outputing - the .arch directive in assembly. */ - if (!selected_arch) + else if (selected_arch) { - gcc_assert (selected_cpu); + selected_cpu = &all_cores[selected_arch->ident]; + aarch64_isa_flags = arch_isa; + } + else + { + /* No -mcpu or -march specified, so use the default CPU. */ + selected_cpu = &all_cores[TARGET_CPU_DEFAULT]; selected_arch = &all_architectures[selected_cpu->arch]; + aarch64_isa_flags = selected_cpu->flags; } + explicit_arch = selected_arch->arch; if (!selected_tune) selected_tune = selected_cpu; + explicit_tune_core = selected_tune->ident; + + gcc_assert (explicit_tune_core != aarch64_none); + gcc_assert (explicit_arch != aarch64_no_arch); if (aarch64_enable_bti == 2) { @@ -15014,15 +14976,6 @@ aarch64_override_options (void) if (aarch64_ra_sign_scope != AARCH64_FUNCTION_NONE && TARGET_ILP32) sorry ("return address signing is only supported for %<-mabi=lp64%>"); - /* Make sure we properly set up the explicit options. */ - if ((aarch64_cpu_string && valid_cpu) - || (aarch64_tune_string && valid_tune)) - gcc_assert (explicit_tune_core != aarch64_none); - - if ((aarch64_cpu_string && valid_cpu) - || (aarch64_arch_string && valid_arch)) - gcc_assert (explicit_arch != aarch64_no_arch); - /* The pass to insert speculation tracking runs before shrink-wrapping and the latter does not know how to update the tracking status. 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DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2020 14:22:03.5421 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 20c82bbb-ac34-4b24-64d6-08d858b98d51 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT017.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR08MB3080 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_LOTSOFHASH, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Earnshaw Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Add support for --with-tune. Like --with-cpu and --with-arch, the argument is validated and transformed into a -mtune option to be processed like any other command-line option. --with-tune has no effect if a -mcpu or -mtune option is used. The validating code didn't allow --with-cpu=native, so explicitly allow that. Co-authored-by: Delia Burduv Bootstrap OK, regress pass, OK to commit? ChangeLog 2020-09-03 Wilco Dijkstra * config.gcc (aarch64*-*-*): Add --with-tune. Support --with-cpu=native. * config/aarch64/aarch64.h (OPTION_DEFAULT_SPECS): Add --with-tune. 2020-09-03 Wilco Dijkstra * gcc/testsuite/lib/target-supports.exp: (check_effective_target_tune_cortex_a76): New effective target test. * gcc.target/aarch64/with-tune-config.c: New test. * gcc.target/aarch64/with-tune-march.c: Likewise. * gcc.target/aarch64/with-tune-mcpu.c: Likewise. * gcc.target/aarch64/with-tune-mtune.c: Likewise. diff --git a/gcc/config.gcc b/gcc/config.gcc index 918320573ade712ddc252045e0b70fb8b65e0c66..947cebb0960d403a9ce40b65bef948fbbe8916a9 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -4052,8 +4052,8 @@ fi supported_defaults= case "${target}" in aarch64*-*-*) - supported_defaults="abi cpu arch" - for which in cpu arch; do + supported_defaults="abi cpu arch tune" + for which in cpu arch tune; do eval "val=\$with_$which" base_val=`echo $val | sed -e 's/\+.*//'` @@ -4074,6 +4074,12 @@ case "${target}" in ${srcdir}/config/aarch64/$def \ > /dev/null; then + # Disallow extensions in --with-tune=cortex-a53+crc. + if [ $which = tune ] && [ x"$ext_val" != x ]; then + echo "Architecture extensions not supported in --with-$which=$val" 1>&2 + exit 1 + fi + # Use the pre-processor to strip flatten the options. # This makes the format less rigid than if we use # grep and sed directly here. @@ -4109,8 +4115,13 @@ case "${target}" in true else - echo "Unknown $which used in --with-$which=$val" 1>&2 - exit 1 + # Allow --with-$which=native. + if [ "$val" = native ]; then + true + else + echo "Unknown $which used in --with-$which=$val" 1>&2 + exit 1 + fi fi done ;; diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 30b3a28a6d2893cc29bec4aa5b7cfbe1fd51e0b7..09d1f7f8a84e726129f8ec7f59dacae7fe132eaa 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -1200,12 +1200,14 @@ extern enum aarch64_code_model aarch64_cmodel; #define ENDIAN_LANE_N(NUNITS, N) \ (BYTES_BIG_ENDIAN ? NUNITS - 1 - N : N) -/* Support for a configure-time default CPU, etc. We currently support - --with-arch and --with-cpu. Both are ignored if either is specified - explicitly on the command line at run time. */ +/* Support for configure-time --with-arch, --with-cpu and --with-tune. + --with-arch and --with-cpu are ignored if either -mcpu or -march is used. + --with-tune is ignored if either -mtune or -mcpu is used (but is not + affected by -march). */ #define OPTION_DEFAULT_SPECS \ {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ - {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, + {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ + {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}"}, #define MCPU_TO_MARCH_SPEC \ " %{mcpu=*:-march=%:rewrite_mcpu(%{mcpu=*:%*})}" diff --git a/gcc/testsuite/gcc.target/aarch64/with-tune-config.c b/gcc/testsuite/gcc.target/aarch64/with-tune-config.c new file mode 100644 index 0000000000000000000000000000000000000000..0940e9eea892770fada0b9bc0e05e22bebef1167 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/with-tune-config.c @@ -0,0 +1,7 @@ +/* { dg-do compile { target { tune_cortex_a76 } } } */ +/* { dg-additional-options " -dA " } */ + +void foo () +{} + +/* { dg-final { scan-assembler "//.tune cortex-a76" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/with-tune-march.c b/gcc/testsuite/gcc.target/aarch64/with-tune-march.c new file mode 100644 index 0000000000000000000000000000000000000000..61039adea71878222dc27633d0818bac2daefeea --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/with-tune-march.c @@ -0,0 +1,8 @@ +/* { dg-do compile { target { tune_cortex_a76 } } } */ +/* { dg-additional-options " -dA -march=armv8.6-a " } */ + +void foo () +{} + +/* { dg-final { scan-assembler "//.tune cortex-a76" } } */ +/* { dg-final { scan-assembler ".arch armv8.6-a" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/with-tune-mcpu.c b/gcc/testsuite/gcc.target/aarch64/with-tune-mcpu.c new file mode 100644 index 0000000000000000000000000000000000000000..4f8267a5c167cbeda28537811a4f41d51afb05b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/with-tune-mcpu.c @@ -0,0 +1,8 @@ +/* { dg-do compile { target { tune_cortex_a76 } } } */ +/* { dg-additional-options " -dA -mcpu=cortex-a73" } */ + +void foo () +{} + +/* { dg-final { scan-assembler "//.tune cortex-a73" } } */ +/* { dg-final { scan-assembler ".arch armv8-a" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/with-tune-mtune.c b/gcc/testsuite/gcc.target/aarch64/with-tune-mtune.c new file mode 100644 index 0000000000000000000000000000000000000000..60f795a3919968153ba7bf092e22b135d9078294 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/with-tune-mtune.c @@ -0,0 +1,7 @@ +/* { dg-do compile { target { tune_cortex_a76 } } } */ +/* { dg-additional-options " -dA -mtune=cortex-a73" } */ + +void foo () +{} + +/* { dg-final { scan-assembler "//.tune cortex-a73" } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index f3fc5b80aea34911536de6535c9ca28c9a3d83a6..bbf03624c0960053cd4a7333d991bae0c67d225b 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -10435,6 +10435,11 @@ proc check_effective_target_msp430_large {} { } ""] } +# Return 1 if GCC was configured with --with-tune=cortex-a76 +proc check_effective_target_tune_cortex_a76 { } { + return [check_configured_with "with-tune=cortex-a76"] +} + # Return 1 if the target has an efficient means to encode large initializers # in the assembly.