From patchwork Thu Sep 3 06:35:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aaron Ma X-Patchwork-Id: 1356334 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Bhrf55QJjz9sTp; Thu, 3 Sep 2020 16:35:25 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1kDiq5-0004K8-TC; Thu, 03 Sep 2020 06:35:17 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1kDiq4-0004Jy-H2 for kernel-team@lists.ubuntu.com; Thu, 03 Sep 2020 06:35:16 +0000 Received: from [222.129.35.104] (helo=localhost.localdomain) by youngberry.canonical.com with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1kDiq2-0003kb-PE for kernel-team@lists.ubuntu.com; Thu, 03 Sep 2020 06:35:16 +0000 From: Aaron Ma To: kernel-team@lists.ubuntu.com Subject: [PATCH][FOCAL/OEM-5.6] UBUNTU: SAUCE: xhci: workaround for S3 issue on AMD SNPS 3.0 xHC Date: Thu, 3 Sep 2020 14:35:02 +0800 Message-Id: <20200903063503.153721-2-aaron.ma@canonical.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200903063503.153721-1-aaron.ma@canonical.com> References: <20200903063503.153721-1-aaron.ma@canonical.com> MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Nehal Bakulchandra Shah BugLink: https://bugs.launchpad.net/bugs/1893914 On some platform of AMD, S3 fails with HCE and SRE errors.To fix this, sparse controller enable bit has to be disabled. Signed-off-by: Nehal Bakulchandra Shah (backported from https://lkml.org/lkml/2020/8/31/86) Signed-off-by: Aaron Ma --- drivers/usb/host/xhci-pci.c | 12 ++++++++++++ drivers/usb/host/xhci.h | 1 + 2 files changed, 13 insertions(+) diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index bbd616324faa..831da1bdb071 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -149,6 +149,9 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) (pdev->device == 0x15e0 || pdev->device == 0x15e1)) xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; + if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) + xhci->quirks |= XHCI_DISABLE_SPARSE; + if (pdev->vendor == PCI_VENDOR_ID_AMD) xhci->quirks |= XHCI_TRUST_TX_LENGTH; @@ -351,6 +354,15 @@ static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) /* USB 2.0 roothub is stored in the PCI device now. */ hcd = dev_get_drvdata(&dev->dev); xhci = hcd_to_xhci(hcd); + + if (xhci->quirks & XHCI_DISABLE_SPARSE) { + u32 reg; + + reg = readl(hcd->regs + 0xC12C); + reg &= ~BIT(17); + writel(reg, hcd->regs + 0xC12C); + } + xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, pci_name(dev), hcd); if (!xhci->shared_hcd) { diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index c656b41b57b5..13fd4863539d 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1873,6 +1873,7 @@ struct xhci_hcd { #define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33) #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34) #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35) +#define XHCI_DISABLE_SPARSE BIT_ULL(37) unsigned int num_active_eps; unsigned int limit_active_eps;