From patchwork Thu Dec 21 12:14:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaehoon Chung X-Patchwork-Id: 851900 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=samsung.com header.i=@samsung.com header.b="ErUoXucK"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3z2Vvz31GNz9s7B for ; Thu, 21 Dec 2017 23:15:27 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753517AbdLUMOR (ORCPT ); Thu, 21 Dec 2017 07:14:17 -0500 Received: from mailout1.samsung.com ([203.254.224.24]:30132 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753274AbdLUMOM (ORCPT ); Thu, 21 Dec 2017 07:14:12 -0500 Received: from epcas1p4.samsung.com (unknown [182.195.41.48]) by mailout1.samsung.com (KnoxPortal) with ESMTP id 20171221121410epoutp018980242ea25446474b770653ab8ca832~CTj1_1KC00260502605epoutp01a; Thu, 21 Dec 2017 12:14:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.samsung.com 20171221121410epoutp018980242ea25446474b770653ab8ca832~CTj1_1KC00260502605epoutp01a DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1513858450; bh=VPzsPaTxI6KPXuAzEsk1BTYlmkU4k7XmQ6LXSS/8b3U=; h=From:To:Cc:Subject:Date:In-reply-to:References:From; b=ErUoXucKXUx71BFI32nlWVPr6MzRN7nvAEOoPZN7X/6uh5TMRqrvFLpSHm63+E3d0 j5sbaTHTHHx+nhLytmMRZZ5YLhll7IKdEp8MB2BhBQ3oJRnqfiC10V1wHK4Jz/8GQ5 /F4nslOaTsffDMFUUdgN/IVeMGiDvk0JGD2euQOc= Received: from epsmges1p5.samsung.com (unknown [182.195.40.67]) by epcas1p3.samsung.com (KnoxPortal) with ESMTP id 20171221121410epcas1p339d7b3352e6a33fc5b1d35549b475331~CTj1YnQM_2770827708epcas1p3A; Thu, 21 Dec 2017 12:14:10 +0000 (GMT) Received: from epcas1p4.samsung.com ( [182.195.41.48]) by epsmges1p5.samsung.com (Symantec Messaging Gateway) with SMTP id EB.7A.04317.295AB3A5; Thu, 21 Dec 2017 21:14:10 +0900 (KST) Received: from epsmgms2p1new.samsung.com (unknown [182.195.42.142]) by epcas1p1.samsung.com (KnoxPortal) with ESMTP id 20171221121409epcas1p1a12d0f3b0b5d5e732da865ee78f6bb47~CTj1ICUFl3274432744epcas1p1v; Thu, 21 Dec 2017 12:14:09 +0000 (GMT) X-AuditID: b6c32a39-e27ff700000010dd-a5-5a3ba5923d05 Received: from epmmp2 ( [203.254.227.17]) by epsmgms2p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 55.D9.04148.195AB3A5; Thu, 21 Dec 2017 21:14:09 +0900 (KST) Received: from localhost.localdomain ([10.113.77.174]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0P1B00K8U8NLG070@mmp2.samsung.com>; Thu, 21 Dec 2017 21:14:09 +0900 (KST) From: Jaehoon Chung To: linux-pci@vger.kernel.org Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, krzk@kernel.org, jingoohan1@gmail.com, kgene@kernel.org, lorenzo.pieralisi@arm.com, Jaehoon Chung Subject: [RFC 2/2] pci: dwc: pci-exynos: add the codes to support the exynos5433 Date: Thu, 21 Dec 2017 21:14:07 +0900 Message-id: <20171221121408.22636-2-jh80.chung@samsung.com> X-Mailer: git-send-email 2.15.1 In-reply-to: <20171221121408.22636-1-jh80.chung@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrBKsWRmVeSWpSXmKPExsWy7bCmge6kpdZRBjs/MVvMP3KO1eLGrzZW ixVfZrJb9D9+zWxx/vwGdovLu+awWZydd5zNYsb5fUwWb36/YLdo3XuE3YHLY828NYweO2fd ZffYtKqTzaNvyypGj8+b5AJYo1JtMlITU1KLFFLzkvNTMvPSbZW8g+Od403NDAx1DS0tzJUU 8hJzU22VXHwCdN0yc4CuUlIoS8wpBQoFJBYXK+nb2RTll5akKmTkF5fYKkUbGhrpGRqY6xkZ GemZGMdaGZkClSSkZiw4v4SlYH9ExaJfi5gaGJd6dTFyckgImEg8XPeHpYuRi0NIYAejxJZH LVDOd0aJWctfssBUTe56zQ6R2MAosengGiYI5wejxPx5L1lBqtgEdCS2fzvOBGKLCMhKfLy8 hw2kiFngK6NEx9kV7CAJYYEgic4/J5lBbBYBVYm5D16DNfAKWEs8PfmIGWKdvMSELU1gqzkF bCS+bN8JdcYCNonuR44QtovEry/d7BC2sMSr41uAbA4gW1ri0lFbiHA7o8TZ2cIgN0gITGGU WDGjmwkiYSzxbGEXmM0swCfx7msPK0Qvr0RHmxBEiYfEgV0/odY6Srw7OI8Z4uF+Ronr13Yx T2CUWsDIsIpRLLWgODc9tdiwwFSvODG3uDQvXS85P3cTIzjVaFnuYDx2zucQowAHoxIPb0Oy VZQQa2JZcWXuIUYJDmYlEd7qz5ZRQrwpiZVVqUX58UWlOanFhxhNgUEzkVlKNDkfmAbzSuIN TSwNTMyMgInB0tBQSZxXdP21CCGB9MSS1OzU1ILUIpg+Jg5OqQZGi1udqoVlByxfWe9Ijq9I vL7lMesNh7yPXFdTwrrDjJ7XrP6v/rxila2gwMHVC1/qak+fvyjkxTTLxdct2DT+F9hy3la0 drr++EP9YxOzPZuPFauyZ6pd8fbfmj2b+/JUrauFHunVXdHp/+rvaoktd16qcPWZ5Jq4+Wmn w1w15DiULZ/P3HBaiaU4I9FQi7moOBEAGD8Bo0sDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprNLMWRmVeSWpSXmKPExsVy+t9jQd2JS62jDPYc1beYf+Qcq8WNX22s Fiu+zGS36H/8mtni/PkN7BaXd81hszg77zibxYzz+5gs3vx+wW7RuvcIuwOXx5p5axg9ds66 y+6xaVUnm0ffllWMHp83yQWwRnHZpKTmZJalFunbJXBlLDi/hKVgf0TFol+LmBoYl3p1MXJy SAiYSEzues3excjFISSwjlHi67R3zBDOD0aJl58mM4NUsQnoSGz/dpwJxBYRkJX4eHkPG4jN LPCVUeJjbyiILSwQILHkxlmwOIuAqsTcB6/B6nkFrCWennzEDLFNXmLCliYWEJtTwEbiy/ad YLYQUM3rJ83sExh5FjAyrGKUTC0ozk3PLTYqMMxLLdcrTswtLs1L10vOz93ECAyybYe1+nYw 3l8Sf4hRgINRiYe3IdkqSog1say4MvcQowQHs5IIb/Vnyygh3pTEyqrUovz4otKc1OJDjNIc LErivLfzjkUKCaQnlqRmp6YWpBbBZJk4OKUaGJfcUOKZLNFdZtrE1se/nGmlRQzLDbXAwrol q18LVOx5mxnb4bpBdd7GnFT9bPU7cuVTQnbLO7xbZ+80/9ZkS7Uji5015ZfP+Hdw9pU5qzzn TLjIxCo7+4bV3b62xnvJ9Yv4ui2PfD2dsLXvwk7pbTq/2I8ViM1pfLi2QOREfmfpt+Oe+0Q6 GJVYijMSDbWYi4oTAQjucYguAgAA X-CMS-MailID: 20171221121409epcas1p1a12d0f3b0b5d5e732da865ee78f6bb47 X-Msg-Generator: CA CMS-TYPE: 101P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20171221121409epcas1p1a12d0f3b0b5d5e732da865ee78f6bb47 X-RootMTR: 20171221121409epcas1p1a12d0f3b0b5d5e732da865ee78f6bb47 References: <20171221121408.22636-1-jh80.chung@samsung.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Exynos5433 has the PCIe for WiFi. Added the codes relevant to PCIe for supporting the exynos5433. Also changed the binding documentation name to 'samsung,exynos-pcie.txt'. (It's not only exynos5440 anymore.) Signed-off-by: Jaehoon Chung --- ...exynos5440-pcie.txt => samsung,exynos-pcie.txt} | 2 +- drivers/pci/dwc/pci-exynos.c | 183 ++++++++++++++++----- 2 files changed, 144 insertions(+), 41 deletions(-) rename Documentation/devicetree/bindings/pci/{samsung,exynos5440-pcie.txt => samsung,exynos-pcie.txt} (97%) diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.txt similarity index 97% rename from Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt rename to Documentation/devicetree/bindings/pci/samsung,exynos-pcie.txt index 34a11bfbfb60..958dcc150505 100644 --- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.txt @@ -4,7 +4,7 @@ This PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in designware-pcie.txt. Required properties: -- compatible: "samsung,exynos5440-pcie" +- compatible: "samsung,exynos5440-pcie" or "samsung,exynos5433-pcie" - reg: base addresses and lengths of the PCIe controller, the PHY controller, additional register for the PHY controller. (Registers for the PHY controller are DEPRECATED. diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c index 5596fdedbb94..8dee2e90347e 100644 --- a/drivers/pci/dwc/pci-exynos.c +++ b/drivers/pci/dwc/pci-exynos.c @@ -40,6 +40,8 @@ #define PCIE_IRQ_SPECIAL 0x008 #define PCIE_IRQ_EN_PULSE 0x00c #define PCIE_IRQ_EN_LEVEL 0x010 +#define PCIE_SW_WAKE 0x018 +#define PCIE_BUS_EN BIT(1) #define IRQ_MSI_ENABLE BIT(2) #define PCIE_IRQ_EN_SPECIAL 0x014 #define PCIE_PWR_RESET 0x018 @@ -49,7 +51,8 @@ #define PCIE_NONSTICKY_RESET 0x024 #define PCIE_APP_INIT_RESET 0x028 #define PCIE_APP_LTSSM_ENABLE 0x02c -#define PCIE_ELBI_RDLH_LINKUP 0x064 +#define PCIE_ELBI_RDLH_LINKUP 0x074 +#define PCIE_ELBI_XMLH_LINKUP BIT(4) #define PCIE_ELBI_LTSSM_ENABLE 0x1 #define PCIE_ELBI_SLV_AWMISC 0x11c #define PCIE_ELBI_SLV_ARMISC 0x120 @@ -94,6 +97,10 @@ #define PCIE_PHY_TRSV3_PD_TSV BIT(7) #define PCIE_PHY_TRSV3_LVCC 0x31c +/* DBI register */ +#define PCIE_MISC_CONTROL_1_OFF 0x8BC +#define DBI_RO_WR_EN BIT(0) + struct exynos_pcie_mem_res { void __iomem *elbi_base; /* DT 0th resource: PCIe CTRL */ void __iomem *phy_base; /* DT 1st resource: PHY CTRL */ @@ -221,6 +228,96 @@ static const struct exynos_pcie_ops exynos5440_pcie_ops = { .deinit_clk_resources = exynos5440_pcie_deinit_clk_resources, }; +static int exynos5433_pcie_get_mem_resources(struct platform_device *pdev, + struct exynos_pcie *ep) +{ + struct dw_pcie *pci = ep->pci; + struct device *dev = pci->dev; + struct resource *res; + + ep->mem_res = devm_kzalloc(dev, sizeof(*ep->mem_res), GFP_KERNEL); + if (!ep->mem_res) + return -ENOMEM; + + /* External Local Bus interface(ELBI) Register */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi"); + ep->mem_res->elbi_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(ep->mem_res->elbi_base)) + return PTR_ERR(ep->mem_res->elbi_base); + + /* Data Bus Interface(DBI) Register */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); + pci->dbi_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pci->dbi_base)) + return PTR_ERR(pci->dbi_base); + + return 0; +} + +static int exynos5433_pcie_get_clk_resources(struct exynos_pcie *ep) +{ + struct dw_pcie *pci = ep->pci; + struct device *dev = pci->dev; + + ep->clk_res = devm_kzalloc(dev, sizeof(*ep->clk_res), GFP_KERNEL); + if (!ep->clk_res) + return -ENOMEM; + + ep->clk_res->clk = devm_clk_get(dev, "pcie"); + if (IS_ERR(ep->clk_res->clk)) { + dev_err(dev, "Failed to get pcie rc clock\n"); + return PTR_ERR(ep->clk_res->clk); + } + + ep->clk_res->bus_clk = devm_clk_get(dev, "pcie_bus"); + if (IS_ERR(ep->clk_res->bus_clk)) { + dev_err(dev, "Failed to get pcie bus clock\n"); + return PTR_ERR(ep->clk_res->bus_clk); + } + + return 0; +} + +static void exynos5433_pcie_deinit_clk_resources(struct exynos_pcie *ep) +{ + clk_disable_unprepare(ep->clk_res->bus_clk); + clk_disable_unprepare(ep->clk_res->clk); +} + + +static int exynos5433_pcie_init_clk_resources(struct exynos_pcie *ep) +{ + struct dw_pcie *pci = ep->pci; + struct device *dev = pci->dev; + int ret; + + ret = clk_prepare_enable(ep->clk_res->clk); + if (ret) { + dev_err(dev, "cannot enable pcie rc clock"); + return ret; + } + + ret = clk_prepare_enable(ep->clk_res->bus_clk); + if (ret) { + dev_err(dev, "cannot enable pcie bus clock"); + goto err_bus_clk; + } + + return 0; + +err_bus_clk: + clk_disable_unprepare(ep->clk_res->clk); + + return ret; +} + +static const struct exynos_pcie_ops exynos5433_pcie_ops = { + .get_mem_resources = exynos5433_pcie_get_mem_resources, + .get_clk_resources = exynos5433_pcie_get_clk_resources, + .init_clk_resources = exynos5433_pcie_init_clk_resources, + .deinit_clk_resources = exynos5433_pcie_deinit_clk_resources, +}; + static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg) { writel(val, base + reg); @@ -279,7 +376,9 @@ static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep) exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_NONSTICKY_RESET); exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_APP_INIT_RESET); exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_APP_INIT_RESET); - exynos_pcie_writel(ep->mem_res->block_base, 1, PCIE_PHY_MAC_RESET); + if (ep->mem_res->block_base) + exynos_pcie_writel(ep->mem_res->block_base, 1, + PCIE_PHY_MAC_RESET); } static void exynos_pcie_assert_phy_reset(struct exynos_pcie *ep) @@ -413,9 +512,6 @@ static int exynos_pcie_establish_link(struct exynos_pcie *ep) if (ep->using_phy) { phy_reset(ep->phy); - exynos_pcie_writel(ep->mem_res->elbi_base, 1, - PCIE_PWR_RESET); - phy_power_on(ep->phy); phy_init(ep->phy); } else { @@ -430,14 +526,16 @@ static int exynos_pcie_establish_link(struct exynos_pcie *ep) udelay(500); exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_COMMON_RESET); + exynos_pcie_deassert_core_reset(ep); } - /* pulse for common reset */ - exynos_pcie_writel(ep->mem_res->block_base, 1, PCIE_PHY_COMMON_RESET); - udelay(500); - exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_COMMON_RESET); + /* + * Enable DBI_RO_WR_EN bit. + * - When set to 1, some RO and HWinit bits are wriatble from + * the local application through the DBI. + */ + dw_pcie_writel_dbi(pci, PCIE_MISC_CONTROL_1_OFF, DBI_RO_WR_EN); - exynos_pcie_deassert_core_reset(ep); dw_pcie_setup_rc(pp); exynos_pcie_assert_reset(ep); @@ -472,16 +570,6 @@ static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep) exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_PULSE); } -static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep) -{ - u32 val; - - /* enable INTX interrupt */ - val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | - IRQ_INTC_ASSERT | IRQ_INTD_ASSERT; - exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_PULSE); -} - static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) { struct exynos_pcie *ep = arg; @@ -513,9 +601,16 @@ static void exynos_pcie_msi_init(struct exynos_pcie *ep) exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_LEVEL); } -static void exynos_pcie_enable_interrupts(struct exynos_pcie *ep) +static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep) { - exynos_pcie_enable_irq_pulse(ep); + u32 val; + + val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | + IRQ_INTC_ASSERT | IRQ_INTD_ASSERT; + exynos_pcie_writel(ep->mem_res->elbi_base, val, PCIE_IRQ_EN_PULSE); + + exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_IRQ_EN_LEVEL); + exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_IRQ_EN_SPECIAL); if (IS_ENABLED(CONFIG_PCI_MSI)) exynos_pcie_msi_init(ep); @@ -575,10 +670,8 @@ static int exynos_pcie_link_up(struct dw_pcie *pci) u32 val; val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_ELBI_RDLH_LINKUP); - if (val == PCIE_ELBI_LTSSM_ENABLE) - return 1; - return 0; + return (val & PCIE_ELBI_XMLH_LINKUP); } static int exynos_pcie_host_init(struct pcie_port *pp) @@ -587,7 +680,7 @@ static int exynos_pcie_host_init(struct pcie_port *pp) struct exynos_pcie *ep = to_exynos_pcie(pci); exynos_pcie_establish_link(ep); - exynos_pcie_enable_interrupts(ep); + exynos_pcie_enable_irq_pulse(ep); return 0; } @@ -608,8 +701,11 @@ static int __init exynos_add_pcie_port(struct exynos_pcie *ep, pp->irq = platform_get_irq(pdev, 1); if (pp->irq < 0) { - dev_err(dev, "failed to get irq\n"); - return pp->irq; + pp->irq = platform_get_irq_byname(pdev, "intr"); + if (pp->irq < 0) { + dev_err(dev, "failed to get irq\n"); + return pp->irq; + } } ret = devm_request_irq(dev, pp->irq, exynos_pcie_irq_handler, IRQF_SHARED, "exynos-pcie", ep); @@ -678,13 +774,23 @@ static int __init exynos_pcie_probe(struct platform_device *pdev) ep->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); - /* Assume that controller doesn't use the PHY framework */ - ep->using_phy = false; + /* + * In case of Exynos5440, + * Assume that controller doesn't use the PHY frameork. + * Other SoCs might be used the PHY framework. + */ + + if (of_device_is_compatible(np, "samsung,exynos5440-pcie")) + ep->using_phy = false; - ep->phy = devm_of_phy_get(dev, np, NULL); + ep->phy = devm_of_phy_get(dev, np, "pcie-phy"); if (IS_ERR(ep->phy)) { if (PTR_ERR(ep->phy) == -EPROBE_DEFER) return PTR_ERR(ep->phy); + if (!of_device_is_compatible(np, "samsung,exynos5440-pcie")) { + dev_err(dev, "Can't find the pcie-phy\n"); + return PTR_ERR(ep->phy); + } dev_warn(dev, "Use the 'phy' property. Current DT of pci-exynos was deprecated!!\n"); } else ep->using_phy = true; @@ -734,23 +840,20 @@ static int __exit exynos_pcie_remove(struct platform_device *pdev) static const struct of_device_id exynos_pcie_of_match[] = { { .compatible = "samsung,exynos5440-pcie", - .data = &exynos5440_pcie_ops + .data = &exynos5440_pcie_ops, + }, { + .compatible = "samsung,exynos5433-pcie", + .data = &exynos5433_pcie_ops, }, {}, }; static struct platform_driver exynos_pcie_driver = { + .probe = exynos_pcie_probe, .remove = __exit_p(exynos_pcie_remove), .driver = { .name = "exynos-pcie", .of_match_table = exynos_pcie_of_match, }, }; - -/* Exynos PCIe driver does not allow module unload */ - -static int __init exynos_pcie_init(void) -{ - return platform_driver_probe(&exynos_pcie_driver, exynos_pcie_probe); -} -subsys_initcall(exynos_pcie_init); +builtin_platform_driver(exynos_pcie_driver);