From patchwork Fri Aug 14 16:40:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1345108 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=LR6kurrO; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSq4x1VCBz9sT6 for ; Sat, 15 Aug 2020 02:43:29 +1000 (AEST) Received: from localhost ([::1]:44876 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k6cne-0002Ea-Q9 for incoming@patchwork.ozlabs.org; Fri, 14 Aug 2020 12:43:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47076) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k6clY-0006vX-Hf; Fri, 14 Aug 2020 12:41:16 -0400 Received: from mail-pj1-x1042.google.com ([2607:f8b0:4864:20::1042]:50232) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1k6clW-0002cs-3j; Fri, 14 Aug 2020 12:41:15 -0400 Received: by mail-pj1-x1042.google.com with SMTP id e4so4673410pjd.0; Fri, 14 Aug 2020 09:41:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lKUs7RsfnQHorD24cOgxBvy/CDttu+urOseKddDE6Ek=; b=LR6kurrOlFO0Rx3THi+2AlQha+YhDd9sVvQyOSSSKfMkf4nRrmBXFnB3bWDkyYMiCv O6sNKOth7zNiNyagGkaiEE2QHxoEKMjH6iLXz/7bIBG068DK8HBcLPMYxNhGyneyyG0c y8uP9GVSkAgXQXhYmIDZcwk+BLKi9/buMoQr2lynb5QeTOi2tf26cPjJbLI2SG673zG7 M0groblXZQAN276rjt7ct/jXbvSFIpm7TLdlauM9w+8rCPWyhLqBoZbgfRXcT16DI1jW VjAfSLEWzdpCQVAPOtBYT2Lu0VL5b6KovOleuJsGudKVHhvbzNYR0vWdyRcz6inHmVtz /FkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lKUs7RsfnQHorD24cOgxBvy/CDttu+urOseKddDE6Ek=; b=dAf4KhVUN01BqBukuas7JgoqJVNqoA8V01IyjBVhGCQwtgxB+/K/UTYlg42HTcP+0g E1rpgcmR+cREDAvssrSbsKTLBTO5R97JkYtoka6G9KtMWvdEf9izwbLVD3wqGQKKM3xV jOSObRUwVjIsvW5QGLPkUx0zXjwFIuqPIYplCe8oa86lUzUoU4/ESZkTbK8YRxo7LnRu l4Z8JwwvZuszlrbqRG04y7LCNXs81OsTQHKWybyLL6j2mcgrfGALM2gqi+sZ9PH63Jg3 XTT3S2pGAOdHzPCvDyxpmccC2L5J29IRBDBnFkW2c1XhmNeOvR3YUpHYMiacdphrTOm7 /JIA== X-Gm-Message-State: AOAM532BE8N3ltjZeZ/iEfXw9JAiV0JMx07ZRSgVo4r+Ui3+yHsGZ0Ki Dx44zbHhOD9VmXYDFaVlG9w= X-Google-Smtp-Source: ABdhPJwVVNRQJZDzxzOwpMBPVLYtDEeQGRjbkSqFaWHEsxlMNn7RfFoZJU7OhiCer1XE2ZUtb7eyeQ== X-Received: by 2002:a17:902:9883:: with SMTP id s3mr2551764plp.271.1597423271182; Fri, 14 Aug 2020 09:41:11 -0700 (PDT) Received: from pek-vx-bsp2.wrs.com (unknown-146-144.windriver.com. [147.11.146.144]) by smtp.gmail.com with ESMTPSA id 16sm9836332pfi.161.2020.08.14.09.41.08 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Aug 2020 09:41:10 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 01/18] target/riscv: cpu: Add a new 'resetvec' property Date: Sat, 15 Aug 2020 00:40:39 +0800 Message-Id: <1597423256-14847-2-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> References: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Currently the reset vector address is hard-coded in a RISC-V CPU's instance_init() routine. In a real world we can have 2 exact same CPUs except for the reset vector address, which is pretty common in the RISC-V core IP licensing business. Normally reset vector address is a configurable parameter. Let's create a 64-bit property to store the reset vector address which covers both 32-bit and 64-bit CPUs. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + 2 files changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 228b9bd..8067a26 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -518,6 +518,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a804a5d..d34bcfa 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -291,6 +291,7 @@ typedef struct RISCVCPU { uint16_t elen; bool mmu; bool pmp; + uint64_t resetvec; } cfg; } RISCVCPU; From patchwork Fri Aug 14 16:40:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1345105 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=j7hl98eI; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSq3W5c3rz9sTQ for ; Sat, 15 Aug 2020 02:42:15 +1000 (AEST) Received: from localhost ([::1]:38504 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k6cmS-000816-5Q for incoming@patchwork.ozlabs.org; Fri, 14 Aug 2020 12:42:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47106) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k6clb-0006y5-OR; Fri, 14 Aug 2020 12:41:19 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:41659) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1k6clZ-0002d5-5S; Fri, 14 Aug 2020 12:41:19 -0400 Received: by mail-pl1-x643.google.com with SMTP id f10so4412695plj.8; Fri, 14 Aug 2020 09:41:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xaCbEcQNVinUp7yjQHa/3V60LKlx1/zzDfks3aE0/Gk=; b=j7hl98eICtaliygiUKYqTV0f+mXMkv2NQ5fK5NdV7CNli0p6hcpjLum22eBv0o0FhA W+FBxQItVvRbRURqFrhUefesRWINQ8isB5atojfsqQOtNhnWU4xsDRdymQa5a3D8ODw2 twg90FxTJM9R10ZNM3m09ou24fekb1SHbt0jL1mPrG+mTlHsPS8j22+gPbN5xnz6NX+F KPOG7QnoP5Y8LQdSdLcQup3k74dfmxE+Cp0lVwE/mgIL9NpwymxyEYmQH+OZgqz27+5t t+Cp8JpT0elqRsJHMm+OdK5liuk63+t63okLyxDkeNBeqsYGkVWOzBus+HEa7agLaRnL 2LlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xaCbEcQNVinUp7yjQHa/3V60LKlx1/zzDfks3aE0/Gk=; b=RmDcQXNgP9rM1wL4OBlYRqnRjnGb2E654Q2QbVWO7/89EkWQZ8iTvSRSZLR7DyFyyS Ais/eGers8inEeHvdXI/f+IaGTWMN/p9hGnQL0C/AW85euBl0SCAQ8d6U56kPVt/DrSC 6HazhSS3tz4/bHXtZRLRbNqqZdojEDHkXAvxb8HWkY9+N++tyv09XYsiRTUlD2GmWoBp VcjoDMRkjceVbma6D6bROXB4NXiAlM6hEDRYnz3L1yPlKaqghVPQlfiYpya4ZXAqXoUM CR334R/BaIMDhiscAMOyTxmAR7rN65zrhy09Vy9QlimdG+2Dwt5vonDa+4hMu4qqb+Bu ZEjg== X-Gm-Message-State: AOAM53071+tL8JCFdgXYeUuiJ2ROqnng/2zWJ6Si/vAhtx9OG6oW3aa5 5utcKZKamoSNw8nf3KLS7rY= X-Google-Smtp-Source: ABdhPJyaacMhZVvO0SvlEjI8nLtLi1pKhj6zmA1jEg7Ni4Xw4mxItvIaHdcZhuafH95Gci7PY+4O+Q== X-Received: by 2002:a17:902:be12:: with SMTP id r18mr2543010pls.116.1597423275293; Fri, 14 Aug 2020 09:41:15 -0700 (PDT) Received: from pek-vx-bsp2.wrs.com (unknown-146-144.windriver.com. [147.11.146.144]) by smtp.gmail.com with ESMTPSA id 16sm9836332pfi.161.2020.08.14.09.41.11 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Aug 2020 09:41:14 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 02/18] hw/riscv: hart: Add a new 'resetvec' property Date: Sat, 15 Aug 2020 00:40:40 +0800 Message-Id: <1597423256-14847-3-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> References: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::643; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x643.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng RISC-V machines do not instantiate RISC-V CPUs directly, instead they do that via the hart array. Add a new property for the reset vector address to allow the value to be passed to the CPU, before CPU is realized. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/riscv_hart.c | 3 +++ include/hw/riscv/riscv_hart.h | 1 + 2 files changed, 4 insertions(+) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index f59fe52..613ea2a 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -31,6 +31,8 @@ static Property riscv_harts_props[] = { DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1), DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0), DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type), + DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec, + DEFAULT_RSTVEC), DEFINE_PROP_END_OF_LIST(), }; @@ -44,6 +46,7 @@ static bool riscv_hart_realize(RISCVHartArrayState *s, int idx, char *cpu_type, Error **errp) { object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type); + qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec); s->harts[idx].env.mhartid = s->hartid_base + idx; qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp); diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h index c75856f..77aa4bc 100644 --- a/include/hw/riscv/riscv_hart.h +++ b/include/hw/riscv/riscv_hart.h @@ -37,6 +37,7 @@ typedef struct RISCVHartArrayState { uint32_t num_harts; uint32_t hartid_base; char *cpu_type; + uint64_t resetvec; RISCVCPU *harts; } RISCVHartArrayState; From patchwork Fri Aug 14 16:40:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1345110 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=RSVg7xYv; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSq7W3sygz9sT6 for ; Sat, 15 Aug 2020 02:45:43 +1000 (AEST) Received: from localhost ([::1]:53206 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k6cpp-0005ba-5V for incoming@patchwork.ozlabs.org; Fri, 14 Aug 2020 12:45:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47128) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k6clf-00072R-5l; Fri, 14 Aug 2020 12:41:23 -0400 Received: from mail-pj1-x1044.google.com ([2607:f8b0:4864:20::1044]:40259) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1k6clc-0002dO-GY; Fri, 14 Aug 2020 12:41:22 -0400 Received: by mail-pj1-x1044.google.com with SMTP id d4so4631437pjx.5; Fri, 14 Aug 2020 09:41:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Y2tMjmXkDl0fq+x9uIcxt1w/4Y6jZovYHNuWJ4DjJgo=; b=RSVg7xYv9Q/IoWSyVhG4Trl7MuaGmKnnz9X6pLvw93NeFrCjstbjDht99FpyMZP9zB +lH1BqGqTQc/+KvozaDdM7Ih7QeO7UUJyf0Wo8EMr0FyPT3Ox6Nl1tFOzaAYpAc98H38 9NLCxilIr/XRA+jzFK7iLFDjUkzyRa2V+ta92vxLaswHOeH6AXV24OSpWK35Ntv6P4AB q3E9nnG6Jstf+Ki5OEpkgu0AOjB2fwOiWpRZMLCL1F6Lauir0eL1WzVvjXSbQbqB3TKA DIyDo1gc6ljk94opH0znZwBNIcQdxbwz0yz3tWUc/oQ0ROfy7iCsY05XYtr/ewb1/IRM m73w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Y2tMjmXkDl0fq+x9uIcxt1w/4Y6jZovYHNuWJ4DjJgo=; b=NJqxBkIIsxkEqnQ5v0QhGf8ugKXDjle3KEIcDYFHb5uinVrwQMkT5MW0mRoz6KUy3X UW7Ue6yqgLpW+LkIOsivrsVcZJNjsOT1R6OzU9f2dlA740vdO3q4oADr2v4dAua23B+V 5cbgCDf9N64xi8zTLQA9EwfjwZrbN8/mDnz9gUR4ZED6NKNg+520ksGNLVW6xU1AT7o2 4nfCsaQFLE03pdvRFwsfnHZIcq6KTIX3Ze+a2I7usR066AlGHxulLfo6rsV0bfJutMAo 6rU7N7ikgNqsy2DynwLkmjZlbWTgCOJetqzdJ9dHwFoV17zzX682hFJ7iK93DeOJeMJL D/EQ== X-Gm-Message-State: AOAM530VaYUR/oT5FrAN0h8jx003XI0BfHXoUpfjy5DHdCaIReQc9bMs pEK15iUbD+78kw34FOCFi1vUJ5skH2vviqKO X-Google-Smtp-Source: ABdhPJwaXsD85aSqD8jYaNOcaEoR/4TH4nUmKoQQmth2Y6pdC17NTaLtvfKbsjJjk1Z/6AhX/u4njQ== X-Received: by 2002:a17:90a:ea13:: with SMTP id w19mr3116136pjy.18.1597423278660; Fri, 14 Aug 2020 09:41:18 -0700 (PDT) Received: from pek-vx-bsp2.wrs.com (unknown-146-144.windriver.com. [147.11.146.144]) by smtp.gmail.com with ESMTPSA id 16sm9836332pfi.161.2020.08.14.09.41.15 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Aug 2020 09:41:18 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 03/18] target/riscv: cpu: Set reset vector based on the configured property value Date: Sat, 15 Aug 2020 00:40:41 +0800 Message-Id: <1597423256-14847-4-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> References: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Now that we have the newly introduced 'resetvec' property in the RISC-V CPU and HART, instead of hard-coding the reset vector addr in the CPU's instance_init(), move that to riscv_cpu_realize() based on the configured property value from the RISC-V machines. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/opentitan.c | 1 + hw/riscv/sifive_e.c | 1 + hw/riscv/sifive_u.c | 2 ++ target/riscv/cpu.c | 7 ++----- 4 files changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index a8f0039..b0a4eae 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -111,6 +111,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) &error_abort); object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, &error_abort); + object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort); /* Boot ROM */ diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index c8b0604..c84d407 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -177,6 +177,7 @@ static void sifive_e_soc_init(Object *obj) object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, &error_abort); + object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort); object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio, TYPE_SIFIVE_GPIO); } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 18301e6..e256da2 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -611,6 +611,7 @@ static void sifive_u_soc_instance_init(Object *obj) qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); + qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); @@ -620,6 +621,7 @@ static void sifive_u_soc_instance_init(Object *obj) qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU); + qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8067a26..bd41286 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -128,7 +128,6 @@ static void riscv_any_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_11_0); - set_resetvec(env, DEFAULT_RSTVEC); } static void riscv_base_cpu_init(Object *obj) @@ -136,7 +135,6 @@ static void riscv_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, 0); - set_resetvec(env, DEFAULT_RSTVEC); } static void rvxx_sifive_u_cpu_init(Object *obj) @@ -144,7 +142,6 @@ static void rvxx_sifive_u_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); - set_resetvec(env, 0x1004); } static void rvxx_sifive_e_cpu_init(Object *obj) @@ -152,7 +149,6 @@ static void rvxx_sifive_e_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); - set_resetvec(env, 0x1004); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } @@ -163,7 +159,6 @@ static void rv32_ibex_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, RV32 | RVI | RVM | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); - set_resetvec(env, 0x8090); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } @@ -373,6 +368,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) set_feature(env, RISCV_FEATURE_PMP); } + set_resetvec(env, cpu->cfg.resetvec); + /* If misa isn't set (rv32 and rv64 machines) set it here */ if (!env->misa) { /* Do some ISA extension error checking */ From patchwork Fri Aug 14 16:40:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1345107 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=ui3qfcKz; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSq4t5tqKz9sT6 for ; Sat, 15 Aug 2020 02:43:26 +1000 (AEST) Received: from localhost ([::1]:44558 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k6cnc-00026W-GA for incoming@patchwork.ozlabs.org; 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id 16sm9836332pfi.161.2020.08.14.09.41.19 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Aug 2020 09:41:21 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 04/18] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board Date: Sat, 15 Aug 2020 00:40:42 +0800 Message-Id: <1597423256-14847-5-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> References: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::643; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x643.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng This is an initial support for Microchip PolarFire SoC Icicle Kit. The Icicle Kit board integrates a PolarFire SoC, with one SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA. For more details about Microchip PolarFire Soc, please see: https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000. The following perepherals are created as an unimplemented device: - Bus Error Uint 0/1/2/3/4 - L2 cache controller - SYSREG - MPUCFG - IOSCBCFG More devices will be added later. The BIOS image used by this machine is hss.bin, aka Hart Software Services, which can be built from: https://github.com/polarfire-soc/hart-software-services To launch this machine: $ qemu-system-riscv64 -nographic -M microchip-icicle-kit The memory is set to 1 GiB by default to match the hardware. A sanity check on ram size is performed in the machine init routine to prompt user to increase the RAM size to > 1 GiB when less than 1 GiB ram is detected. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- MAINTAINERS | 7 + default-configs/riscv64-softmmu.mak | 1 + hw/riscv/Kconfig | 6 + hw/riscv/Makefile.objs | 1 + hw/riscv/microchip_pfsoc.c | 312 ++++++++++++++++++++++++++++++++++++ include/hw/riscv/microchip_pfsoc.h | 88 ++++++++++ 6 files changed, 415 insertions(+) create mode 100644 hw/riscv/microchip_pfsoc.c create mode 100644 include/hw/riscv/microchip_pfsoc.h diff --git a/MAINTAINERS b/MAINTAINERS index 0886eb3..8716cb6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1314,6 +1314,13 @@ F: include/hw/riscv/opentitan.h F: include/hw/char/ibex_uart.h F: include/hw/intc/ibex_plic.h +Microchip PolarFire SoC Icicle Kit +M: Bin Meng +L: qemu-riscv@nongnu.org +S: Supported +F: hw/riscv/microchip_pfsoc.c +F: include/hw/riscv/microchip_pfsoc.h + RX Machines ----------- rx-gdbsim diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak index aaf6d73..76b6195 100644 --- a/default-configs/riscv64-softmmu.mak +++ b/default-configs/riscv64-softmmu.mak @@ -10,3 +10,4 @@ CONFIG_SPIKE=y CONFIG_SIFIVE_E=y CONFIG_SIFIVE_U=y CONFIG_RISCV_VIRT=y +CONFIG_MICROCHIP_PFSOC=y diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 28947ef..3292fae 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -48,3 +48,9 @@ config RISCV_VIRT select PCI_EXPRESS_GENERIC_BRIDGE select PFLASH_CFI01 select SIFIVE + +config MICROCHIP_PFSOC + bool + select HART + select SIFIVE + select UNIMP diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs index 57cc708..419a5a0 100644 --- a/hw/riscv/Makefile.objs +++ b/hw/riscv/Makefile.objs @@ -14,3 +14,4 @@ obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o obj-$(CONFIG_SIFIVE) += sifive_uart.o obj-$(CONFIG_SPIKE) += spike.o obj-$(CONFIG_RISCV_VIRT) += virt.o +obj-$(CONFIG_MICROCHIP_PFSOC) += microchip_pfsoc.o diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c new file mode 100644 index 0000000..20a642c --- /dev/null +++ b/hw/riscv/microchip_pfsoc.c @@ -0,0 +1,312 @@ +/* + * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit + * + * Copyright (c) 2020 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit + * + * 0) CLINT (Core Level Interruptor) + * 1) PLIC (Platform Level Interrupt Controller) + * 2) eNVM (Embedded Non-Volatile Memory) + * + * This board currently generates devicetree dynamically that indicates at least + * two harts and up to five harts. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "qemu/units.h" +#include "qemu/cutils.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/irq.h" +#include "hw/loader.h" +#include "hw/sysbus.h" +#include "hw/cpu/cluster.h" +#include "target/riscv/cpu.h" +#include "hw/misc/unimp.h" +#include "hw/riscv/boot.h" +#include "hw/riscv/riscv_hart.h" +#include "hw/riscv/sifive_clint.h" +#include "hw/riscv/sifive_plic.h" +#include "hw/riscv/microchip_pfsoc.h" + +/* + * The BIOS image used by this machine is called Hart Software Services (HSS). + * See https://github.com/polarfire-soc/hart-software-services + */ +#define BIOS_FILENAME "hss.bin" +#define RESET_VECTOR 0x20220000 + +static const struct MemmapEntry { + hwaddr base; + hwaddr size; +} microchip_pfsoc_memmap[] = { + [MICROCHIP_PFSOC_DEBUG] = { 0x0, 0x1000 }, + [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 }, + [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 }, + [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 }, + [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 }, + [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 }, + [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 }, + [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 }, + [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 }, + [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 }, + [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 }, + [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, + [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, + [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, + [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, + [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 }, + [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 }, +}; + +static void microchip_pfsoc_soc_instance_init(Object *obj) +{ + MachineState *ms = MACHINE(qdev_get_machine()); + MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj); + + object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); + qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); + + object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, + TYPE_RISCV_HART_ARRAY); + qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); + qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); + qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", + TYPE_RISCV_CPU_SIFIVE_E51); + qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR); + + object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); + qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); + + object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, + TYPE_RISCV_HART_ARRAY); + qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); + qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); + qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", + TYPE_RISCV_CPU_SIFIVE_U54); + qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR); +} + +static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) +{ + MachineState *ms = MACHINE(qdev_get_machine()); + MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev); + const struct MemmapEntry *memmap = microchip_pfsoc_memmap; + MemoryRegion *system_memory = get_system_memory(); + MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1); + MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); + MemoryRegion *envm_data = g_new(MemoryRegion, 1); + char *plic_hart_config; + size_t plic_hart_config_len; + int i; + + sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); + sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); + /* + * The cluster must be realized after the RISC-V hart array container, + * as the container's CPU object is only created on realize, and the + * CPU must exist and have been parented into the cluster before the + * cluster is realized. + */ + qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); + qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); + + /* E51 DTIM */ + memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem", + memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal); + memory_region_add_subregion(system_memory, + memmap[MICROCHIP_PFSOC_E51_DTIM].base, + e51_dtim_mem); + + /* Bus Error Units */ + create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem", + memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base, + memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size); + create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem", + memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base, + memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size); + create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem", + memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base, + memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size); + create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem", + memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base, + memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size); + create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem", + memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base, + memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size); + + /* CLINT */ + sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base, + memmap[MICROCHIP_PFSOC_CLINT].size, ms->smp.cpus, + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); + + /* L2 cache controller */ + create_unimplemented_device("microchip.pfsoc.l2cc", + memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size); + + /* + * Add L2-LIM at reset size. + * This should be reduced in size as the L2 Cache Controller WayEnable + * register is incremented. Unfortunately I don't see a nice (or any) way + * to handle reducing or blocking out the L2 LIM while still allowing it + * be re returned to all enabled after a reset. For the time being, just + * leave it enabled all the time. This won't break anything, but will be + * too generous to misbehaving guests. + */ + memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim", + memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal); + memory_region_add_subregion(system_memory, + memmap[MICROCHIP_PFSOC_L2LIM].base, + l2lim_mem); + + /* create PLIC hart topology configuration string */ + plic_hart_config_len = (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1) * + ms->smp.cpus; + plic_hart_config = g_malloc0(plic_hart_config_len); + for (i = 0; i < ms->smp.cpus; i++) { + if (i != 0) { + strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG, + plic_hart_config_len); + } else { + strncat(plic_hart_config, "M", plic_hart_config_len); + } + plic_hart_config_len -= (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1); + } + + /* PLIC */ + s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base, + plic_hart_config, + MICROCHIP_PFSOC_PLIC_NUM_SOURCES, + MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES, + MICROCHIP_PFSOC_PLIC_PRIORITY_BASE, + MICROCHIP_PFSOC_PLIC_PENDING_BASE, + MICROCHIP_PFSOC_PLIC_ENABLE_BASE, + MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE, + MICROCHIP_PFSOC_PLIC_CONTEXT_BASE, + MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE, + memmap[MICROCHIP_PFSOC_PLIC].size); + g_free(plic_hart_config); + + /* SYSREG */ + create_unimplemented_device("microchip.pfsoc.sysreg", + memmap[MICROCHIP_PFSOC_SYSREG].base, + memmap[MICROCHIP_PFSOC_SYSREG].size); + + /* MPUCFG */ + create_unimplemented_device("microchip.pfsoc.mpucfg", + memmap[MICROCHIP_PFSOC_MPUCFG].base, + memmap[MICROCHIP_PFSOC_MPUCFG].size); + + /* eNVM */ + memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data", + memmap[MICROCHIP_PFSOC_ENVM_DATA].size, + &error_fatal); + memory_region_add_subregion(system_memory, + memmap[MICROCHIP_PFSOC_ENVM_DATA].base, + envm_data); + + /* IOSCBCFG */ + create_unimplemented_device("microchip.pfsoc.ioscb.cfg", + memmap[MICROCHIP_PFSOC_IOSCB_CFG].base, + memmap[MICROCHIP_PFSOC_IOSCB_CFG].size); +} + +static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + dc->realize = microchip_pfsoc_soc_realize; + /* Reason: Uses serial_hds in realize function, thus can't be used twice */ + dc->user_creatable = false; +} + +static const TypeInfo microchip_pfsoc_soc_type_info = { + .name = TYPE_MICROCHIP_PFSOC, + .parent = TYPE_DEVICE, + .instance_size = sizeof(MicrochipPFSoCState), + .instance_init = microchip_pfsoc_soc_instance_init, + .class_init = microchip_pfsoc_soc_class_init, +}; + +static void microchip_pfsoc_soc_register_types(void) +{ + type_register_static(µchip_pfsoc_soc_type_info); +} + +type_init(microchip_pfsoc_soc_register_types) + +static void microchip_icicle_kit_machine_init(MachineState *machine) +{ + MachineClass *mc = MACHINE_GET_CLASS(machine); + const struct MemmapEntry *memmap = microchip_pfsoc_memmap; + MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine); + MemoryRegion *system_memory = get_system_memory(); + MemoryRegion *main_mem = g_new(MemoryRegion, 1); + + /* Sanity check on RAM size */ + if (machine->ram_size < mc->default_ram_size) { + char *sz = size_to_str(mc->default_ram_size); + error_report("Invalid RAM size, should be bigger than %s", sz); + g_free(sz); + exit(EXIT_FAILURE); + } + + /* Initialize SoC */ + object_initialize_child(OBJECT(machine), "soc", &s->soc, + TYPE_MICROCHIP_PFSOC); + qdev_realize(DEVICE(&s->soc), NULL, &error_abort); + + /* Register RAM */ + memory_region_init_ram(main_mem, NULL, "microchip.icicle.kit.ram", + machine->ram_size, &error_fatal); + memory_region_add_subregion(system_memory, + memmap[MICROCHIP_PFSOC_DRAM].base, main_mem); + + /* Load the firmware */ + riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL); +} + +static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + + mc->desc = "Microchip PolarFire SoC Icicle Kit"; + mc->init = microchip_icicle_kit_machine_init; + mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + + MICROCHIP_PFSOC_COMPUTE_CPU_COUNT; + mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1; + mc->default_cpus = mc->min_cpus; + mc->default_ram_size = 1 * GiB; +} + +static const TypeInfo microchip_icicle_kit_machine_typeinfo = { + .name = MACHINE_TYPE_NAME("microchip-icicle-kit"), + .parent = TYPE_MACHINE, + .class_init = microchip_icicle_kit_machine_class_init, + .instance_size = sizeof(MicrochipIcicleKitState), +}; + +static void microchip_icicle_kit_machine_init_register_types(void) +{ + type_register_static(µchip_icicle_kit_machine_typeinfo); +} + +type_init(microchip_icicle_kit_machine_init_register_types) diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h new file mode 100644 index 0000000..1953ef1 --- /dev/null +++ b/include/hw/riscv/microchip_pfsoc.h @@ -0,0 +1,88 @@ +/* + * Microchip PolarFire SoC machine interface + * + * Copyright (c) 2020 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef HW_MICROCHIP_PFSOC_H +#define HW_MICROCHIP_PFSOC_H + +typedef struct MicrochipPFSoCState { + /*< private >*/ + DeviceState parent_obj; + + /*< public >*/ + CPUClusterState e_cluster; + CPUClusterState u_cluster; + RISCVHartArrayState e_cpus; + RISCVHartArrayState u_cpus; + DeviceState *plic; +} MicrochipPFSoCState; + +#define TYPE_MICROCHIP_PFSOC "microchip.pfsoc" +#define MICROCHIP_PFSOC(obj) \ + OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC) + +typedef struct MicrochipIcicleKitState { + /*< private >*/ + MachineState parent_obj; + + /*< public >*/ + MicrochipPFSoCState soc; +} MicrochipIcicleKitState; + +#define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \ + MACHINE_TYPE_NAME("microchip-icicle-kit") +#define MICROCHIP_ICICLE_KIT_MACHINE(obj) \ + OBJECT_CHECK(MicrochipIcicleKitState, (obj), \ + TYPE_MICROCHIP_ICICLE_KIT_MACHINE) + +enum { + MICROCHIP_PFSOC_DEBUG, + MICROCHIP_PFSOC_E51_DTIM, + MICROCHIP_PFSOC_BUSERR_UNIT0, + MICROCHIP_PFSOC_BUSERR_UNIT1, + MICROCHIP_PFSOC_BUSERR_UNIT2, + MICROCHIP_PFSOC_BUSERR_UNIT3, + MICROCHIP_PFSOC_BUSERR_UNIT4, + MICROCHIP_PFSOC_CLINT, + MICROCHIP_PFSOC_L2CC, + MICROCHIP_PFSOC_L2LIM, + MICROCHIP_PFSOC_PLIC, + MICROCHIP_PFSOC_SYSREG, + MICROCHIP_PFSOC_MPUCFG, + MICROCHIP_PFSOC_ENVM_CFG, + MICROCHIP_PFSOC_ENVM_DATA, + MICROCHIP_PFSOC_IOSCB_CFG, + MICROCHIP_PFSOC_DRAM, +}; + +#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1 +#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4 + +#define MICROCHIP_PFSOC_PLIC_HART_CONFIG "MS" +#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185 +#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7 +#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04 +#define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000 +#define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000 +#define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80 +#define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE 0x200000 +#define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE 0x1000 + +#endif /* HW_MICROCHIP_PFSOC_H */ From patchwork Fri Aug 14 16:40:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1345112 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id 16sm9836332pfi.161.2020.08.14.09.41.22 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Aug 2020 09:41:24 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 05/18] hw/char: Add Microchip PolarFire SoC MMUART emulation Date: Sat, 15 Aug 2020 00:40:43 +0800 Message-Id: <1597423256-14847-6-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> References: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Bin Meng , Paolo Bonzini Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Microchip PolarFire SoC MMUART is ns16550 compatible, with some additional registers. Create a simple MMUART model built on top of the existing ns16550 model. Signed-off-by: Bin Meng --- MAINTAINERS | 2 + hw/char/Kconfig | 3 ++ hw/char/Makefile.objs | 1 + hw/char/mchp_pfsoc_mmuart.c | 82 +++++++++++++++++++++++++++++++++++++ include/hw/char/mchp_pfsoc_mmuart.h | 61 +++++++++++++++++++++++++++ 5 files changed, 149 insertions(+) create mode 100644 hw/char/mchp_pfsoc_mmuart.c create mode 100644 include/hw/char/mchp_pfsoc_mmuart.h diff --git a/MAINTAINERS b/MAINTAINERS index 8716cb6..e51edac 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1319,7 +1319,9 @@ M: Bin Meng L: qemu-riscv@nongnu.org S: Supported F: hw/riscv/microchip_pfsoc.c +F: hw/char/mchp_pfsoc_mmuart.c F: include/hw/riscv/microchip_pfsoc.h +F: include/hw/char/mchp_pfsoc_mmuart.h RX Machines ----------- diff --git a/hw/char/Kconfig b/hw/char/Kconfig index b7e0e4d..1d64555 100644 --- a/hw/char/Kconfig +++ b/hw/char/Kconfig @@ -52,3 +52,6 @@ config RENESAS_SCI config AVR_USART bool + +config MCHP_PFSOC_MMUART + bool diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs index bf177ac..f705845 100644 --- a/hw/char/Makefile.objs +++ b/hw/char/Makefile.objs @@ -33,6 +33,7 @@ common-obj-$(CONFIG_LM32) += lm32_juart.o common-obj-$(CONFIG_LM32) += lm32_uart.o common-obj-$(CONFIG_MILKYMIST) += milkymist-uart.o common-obj-$(CONFIG_SCLPCONSOLE) += sclpconsole.o sclpconsole-lm.o +common-obj-$(CONFIG_MCHP_PFSOC_MMUART) += mchp_pfsoc_mmuart.o obj-$(CONFIG_VIRTIO) += virtio-serial-bus.o obj-$(CONFIG_PSERIES) += spapr_vty.o diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c new file mode 100644 index 0000000..9984acc --- /dev/null +++ b/hw/char/mchp_pfsoc_mmuart.c @@ -0,0 +1,82 @@ +/* + * Microchip PolarFire SoC MMUART emulation + * + * Copyright (c) 2020 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "chardev/char.h" +#include "exec/address-spaces.h" +#include "hw/char/mchp_pfsoc_mmuart.h" + +static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size) +{ + MchpPfSoCMMUartState *s = opaque; + + if ((addr % sizeof(uint32_t)) || (addr >= 0x34)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n", + __func__, addr); + return 0; + } + + return s->reg[addr / sizeof(uint32_t)]; +} + +static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + MchpPfSoCMMUartState *s = opaque; + uint32_t val32 = (uint32_t)value; + + if ((addr % sizeof(uint32_t)) || (addr >= 0x34)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx + " v=0x%x\n", __func__, addr, val32); + return; + } + + s->reg[addr / sizeof(uint32_t)] = val32; +} + +static const MemoryRegionOps mchp_pfsoc_mmuart_ops = { + .read = mchp_pfsoc_mmuart_read, + .write = mchp_pfsoc_mmuart_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem, + hwaddr base, qemu_irq irq, Chardev *chr) +{ + MchpPfSoCMMUartState *s; + + s = g_new0(MchpPfSoCMMUartState, 1); + + memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s, + "mchp.pfsoc.mmuart", 0x1000); + + s->base = base; + s->irq = irq; + + s->serial = serial_mm_init(sysmem, base, 2, irq, 399193, chr, + DEVICE_LITTLE_ENDIAN); + + memory_region_add_subregion(sysmem, base + 0x20, &s->iomem); + + return s; +} diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfsoc_mmuart.h new file mode 100644 index 0000000..f619902 --- /dev/null +++ b/include/hw/char/mchp_pfsoc_mmuart.h @@ -0,0 +1,61 @@ +/* + * Microchip PolarFire SoC MMUART emulation + * + * Copyright (c) 2020 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_MCHP_PFSOC_MMUART_H +#define HW_MCHP_PFSOC_MMUART_H + +#include "hw/char/serial.h" + +#define MCHP_PFSOC_MMUART_REG_SIZE 52 + +typedef struct MchpPfSoCMMUartState { + MemoryRegion iomem; + hwaddr base; + qemu_irq irq; + + SerialMM *serial; + + uint32_t reg[MCHP_PFSOC_MMUART_REG_SIZE / sizeof(uint32_t)]; +} MchpPfSoCMMUartState; + +/** + * mchp_pfsoc_mmuart_create - Create a Microchip PolarFire SoC MMUART + * + * This is a helper routine for board to create a MMUART device that is + * compatible with Microchip PolarFire SoC. + * + * @sysmem: system memory region to map + * @base: base address of the MMUART registers + * @irq: IRQ number of the MMUART device + * @chr: character device to associate to + * + * @return: a pointer to the device specific control structure + */ +MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem, + hwaddr base, qemu_irq irq, Chardev *chr); + +#endif /* HW_MCHP_PFSOC_MMUART_H */ From patchwork Fri Aug 14 16:40:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1345116 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=bGrfVYdS; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSqCd5qM2z9sT6 for ; Sat, 15 Aug 2020 02:49:17 +1000 (AEST) Received: from localhost ([::1]:40738 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k6ctH-0003kx-Hx for incoming@patchwork.ozlabs.org; Fri, 14 Aug 2020 12:49:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47232) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k6clo-0007P4-Ew; Fri, 14 Aug 2020 12:41:32 -0400 Received: from mail-pj1-x1042.google.com ([2607:f8b0:4864:20::1042]:50235) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1k6clm-0002eq-Gn; Fri, 14 Aug 2020 12:41:32 -0400 Received: by mail-pj1-x1042.google.com with SMTP id e4so4673813pjd.0; Fri, 14 Aug 2020 09:41:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mdPr+L46xcY0jrrcKDo2FpIIhtgmjgb2ImLyVvpn5I0=; b=bGrfVYdS4RZKNXSI0PR7SvLA9DfAvXyFZk3+z9Jo2r2EnbteF+fTd6PpJBV7/skFaT y2mZr3eYT2rQQMF6tCLqujLFfcDuwGQoWOYFL99xXz2qP2tF7ov1HoKu5IecCwaXziPs 5Db/Hp3RiIg/XvPdjetA6jt6OpH1ucOj5P9OciB2PXt8UWhC7Ml3KqdfcHbE5N/XrPbV ZqU6wJEmtX8QOnVGBhGmXxgtxwnY1UQOKBX5nUTaOLVXDOP9y/9yUztS1OQO2nCG2atx ai1r2m3pWnH2PbozlsrDrEfJ26q1/S04Xc+e2+Ei3MUVew31aPQ/qjz9KI5sy9OMzph+ /oFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mdPr+L46xcY0jrrcKDo2FpIIhtgmjgb2ImLyVvpn5I0=; b=mttaKykV76oibZoAGkBx756b9atIcJ2z7eWqXURidEsIRW2Fjdn8TpYZLZBORpg5he 3JOaM5hNya3FMexVcKKc8RyDpSByQpa6VK+cCVh72r1U8j/zkhezoVjRjAM07YsCd1fG Od3XHPYeFdP9iqoBi+U6TBzQhmj9oeJ3BE72DWjgdTvOdRnFNEce2T90fnmB8YpUNAvX yAlGc4tx3dKqgfm+qfiqZHlnl8xkPkNyrT/q4IZJkbWnOG4MteCy5WjYhnvEsvG4Xh3p 7yLIzY2NLOUXneZPI+/T1nmjeHpMrHzeti8vAXqVKAUu7LIXfUDjh5wcnapxD0GDpae2 2CtQ== X-Gm-Message-State: AOAM531fJqnQMmP2m5XoCZZlRrN8nZStJrN2jX3bPEQSxplczKn6PyiD h5L/F7RWKdJtXTdTeR7eMsg= X-Google-Smtp-Source: ABdhPJxsGKDTIr3altxRnkUBZIH8CLyKEX3TEsiEYEk5iXzBSoLq+mmyEJzcxEhlVCoyIqpHoz25wQ== X-Received: by 2002:a17:90b:2388:: with SMTP id mr8mr3202035pjb.64.1597423288857; Fri, 14 Aug 2020 09:41:28 -0700 (PDT) Received: from pek-vx-bsp2.wrs.com (unknown-146-144.windriver.com. [147.11.146.144]) by smtp.gmail.com with ESMTPSA id 16sm9836332pfi.161.2020.08.14.09.41.25 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Aug 2020 09:41:28 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 06/18] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs Date: Sat, 15 Aug 2020 00:40:44 +0800 Message-Id: <1597423256-14847-7-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> References: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board wires 4 of them out. Let's connect all 5 MMUARTs. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/Kconfig | 1 + hw/riscv/microchip_pfsoc.c | 30 ++++++++++++++++++++++++++++++ include/hw/riscv/microchip_pfsoc.h | 20 ++++++++++++++++++++ 3 files changed, 51 insertions(+) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 3292fae..ceb7c16 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -54,3 +54,4 @@ config MICROCHIP_PFSOC select HART select SIFIVE select UNIMP + select MCHP_PFSOC_MMUART diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 20a642c..f6b375c 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -11,6 +11,7 @@ * 0) CLINT (Core Level Interruptor) * 1) PLIC (Platform Level Interrupt Controller) * 2) eNVM (Embedded Non-Volatile Memory) + * 3) MMUARTs (Multi-Mode UART) * * This board currently generates devicetree dynamically that indicates at least * two harts and up to five harts. @@ -38,6 +39,7 @@ #include "hw/irq.h" #include "hw/loader.h" #include "hw/sysbus.h" +#include "chardev/char.h" #include "hw/cpu/cluster.h" #include "target/riscv/cpu.h" #include "hw/misc/unimp.h" @@ -46,6 +48,7 @@ #include "hw/riscv/sifive_clint.h" #include "hw/riscv/sifive_plic.h" #include "hw/riscv/microchip_pfsoc.h" +#include "sysemu/sysemu.h" /* * The BIOS image used by this machine is called Hart Software Services (HSS). @@ -69,8 +72,13 @@ static const struct MemmapEntry { [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 }, [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 }, [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 }, + [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, + [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 }, + [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, + [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, + [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 }, [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 }, @@ -215,6 +223,28 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) memmap[MICROCHIP_PFSOC_MPUCFG].base, memmap[MICROCHIP_PFSOC_MPUCFG].size); + /* MMUARTs */ + s->serial0 = mchp_pfsoc_mmuart_create(system_memory, + memmap[MICROCHIP_PFSOC_MMUART0].base, + qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ), + serial_hd(0)); + s->serial1 = mchp_pfsoc_mmuart_create(system_memory, + memmap[MICROCHIP_PFSOC_MMUART1].base, + qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ), + serial_hd(1)); + s->serial2 = mchp_pfsoc_mmuart_create(system_memory, + memmap[MICROCHIP_PFSOC_MMUART2].base, + qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ), + serial_hd(2)); + s->serial3 = mchp_pfsoc_mmuart_create(system_memory, + memmap[MICROCHIP_PFSOC_MMUART3].base, + qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ), + serial_hd(3)); + s->serial4 = mchp_pfsoc_mmuart_create(system_memory, + memmap[MICROCHIP_PFSOC_MMUART4].base, + qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ), + serial_hd(4)); + /* eNVM */ memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data", memmap[MICROCHIP_PFSOC_ENVM_DATA].size, diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index 1953ef1..a5efa1d 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -22,6 +22,8 @@ #ifndef HW_MICROCHIP_PFSOC_H #define HW_MICROCHIP_PFSOC_H +#include "hw/char/mchp_pfsoc_mmuart.h" + typedef struct MicrochipPFSoCState { /*< private >*/ DeviceState parent_obj; @@ -32,6 +34,11 @@ typedef struct MicrochipPFSoCState { RISCVHartArrayState e_cpus; RISCVHartArrayState u_cpus; DeviceState *plic; + MchpPfSoCMMUartState *serial0; + MchpPfSoCMMUartState *serial1; + MchpPfSoCMMUartState *serial2; + MchpPfSoCMMUartState *serial3; + MchpPfSoCMMUartState *serial4; } MicrochipPFSoCState; #define TYPE_MICROCHIP_PFSOC "microchip.pfsoc" @@ -64,14 +71,27 @@ enum { MICROCHIP_PFSOC_L2CC, MICROCHIP_PFSOC_L2LIM, MICROCHIP_PFSOC_PLIC, + MICROCHIP_PFSOC_MMUART0, MICROCHIP_PFSOC_SYSREG, MICROCHIP_PFSOC_MPUCFG, + MICROCHIP_PFSOC_MMUART1, + MICROCHIP_PFSOC_MMUART2, + MICROCHIP_PFSOC_MMUART3, + MICROCHIP_PFSOC_MMUART4, MICROCHIP_PFSOC_ENVM_CFG, MICROCHIP_PFSOC_ENVM_DATA, MICROCHIP_PFSOC_IOSCB_CFG, MICROCHIP_PFSOC_DRAM, }; +enum { + MICROCHIP_PFSOC_MMUART0_IRQ = 90, + MICROCHIP_PFSOC_MMUART1_IRQ = 91, + MICROCHIP_PFSOC_MMUART2_IRQ = 92, + MICROCHIP_PFSOC_MMUART3_IRQ = 93, + MICROCHIP_PFSOC_MMUART4_IRQ = 94, +}; + #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1 #define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4 From patchwork Fri Aug 14 16:40:45 2020 Content-Type: text/plain; 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id 16sm9836332pfi.161.2020.08.14.09.41.29 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Aug 2020 09:41:31 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 07/18] hw/sd: sd: Fix incorrect populated function switch status data structure Date: Sat, 15 Aug 2020 00:40:45 +0800 Message-Id: <1597423256-14847-8-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> References: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-block@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng At present the function switch status data structure bit [399:376] are wrongly pupulated. These 3 bytes encode function switch status for the 6 function groups, with 4 bits per group, starting from function group 6 at bit 399, then followed by function group 5 at bit 395, and so on. However the codes mistakenly fills in the function group 1 status at bit 399. This fixes the code logic. Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé --- hw/sd/sd.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index fad9cf1..51f5900 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -806,11 +806,15 @@ static void sd_function_switch(SDState *sd, uint32_t arg) sd->data[11] = 0x43; sd->data[12] = 0x80; /* Supported group 1 functions */ sd->data[13] = 0x03; + + sd->data[14] = 0; + sd->data[15] = 0; + sd->data[16] = 0; for (i = 0; i < 6; i ++) { new_func = (arg >> (i * 4)) & 0x0f; if (mode && new_func != 0x0f) sd->function_group[i] = new_func; - sd->data[14 + (i >> 1)] = new_func << ((i * 4) & 4); + sd->data[16 - (i >> 1)] |= new_func << ((i % 2) * 4); } memset(&sd->data[17], 0, 47); stw_be_p(sd->data + 64, sd_crc16(sd->data, 64)); From patchwork Fri Aug 14 16:40:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1345111 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=VrNTz2Xi; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSq7c2hwwz9sT6 for ; Sat, 15 Aug 2020 02:45:48 +1000 (AEST) Received: from localhost ([::1]:53722 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k6cpu-0005p1-1e for incoming@patchwork.ozlabs.org; Fri, 14 Aug 2020 12:45:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47284) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k6clu-0007f2-W4; Fri, 14 Aug 2020 12:41:39 -0400 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]:52753) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1k6clt-0002fq-ES; Fri, 14 Aug 2020 12:41:38 -0400 Received: by mail-pj1-x1043.google.com with SMTP id kr4so4665500pjb.2; Fri, 14 Aug 2020 09:41:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TqvXXs04ABgLxrxaiAku8/lC9UuRi+ByjZ0L4KKRwC0=; b=VrNTz2XilhuQ4nnjTUcNdSyg+wvvqZj/eddpkSNEzhfCgpj2cYSUKNz+n/7g2dEg0g AZJzwcpUhXLK3RcyrA2TAPwgFci9kesWJ1gldUNgUVGOQUjh+bCreQvJ89F9CZYuAKOF d7CJG7WVm+onmsMWhWiQNiFdXEWHo14Djip8y0HVtFrtomYlwO+YtXEpFrNBLhB0I8Cl GUmwU5wuaFJkzc4Z/w7ZBD3UjRwXu4qp99Km7fRWGbenfiOvH93Wdofuri6BC1BAIy8L /WxS2cFUUYQtwvTyE6KJavHVeveF8dOF9vVHjAArhrpydlZfX+G1VUBgAbOkxyuhs067 XM0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TqvXXs04ABgLxrxaiAku8/lC9UuRi+ByjZ0L4KKRwC0=; b=D/S/9FoMVBxR174EIN7ik6UmRRQ8oh5VYyobvuSjUCnKTavL2/Qbboxd/ZoZXitQ0z vnTOFUhvo0r37wHqaNlq1sNY5y7RrwwKXLAl4h7dR1hjD+RMDwKcvcCyCCAN1SOTEm9h vIiSimvD6Z1fAM9YKQNHgUqvHwxHN9DKvhHE+I5Z7VJZ24yiUzeCBWsyb9xKRGk0cpSl wBFzS/NMoMbBr0kJd6V2FCpOYHTq19r7GNXdjW3WhKSyoujCBMrPNy8kpzGSwkc/aGnh 8CLGfjvFEtVQ9xRFmUE9I7Iae8qJyP7ZpJ0UuounlcSbST77xJOY9ofhupkLFn5OUWVS xGlQ== X-Gm-Message-State: AOAM533U6iI34d6gSeyruE/XKo0h89wc/AMG22N1l7msB6QuS7i/jEm6 YaK8JMUtHznput4giG7jD+A= X-Google-Smtp-Source: ABdhPJzwqDQXKtlBBhYrwiYknUSf0aZet4vXu+BQHSNaaOGXB3KDnGWpay/TRqmqQx8ZDY937aCGcA== X-Received: by 2002:a17:90a:3645:: with SMTP id s63mr2968853pjb.30.1597423295651; Fri, 14 Aug 2020 09:41:35 -0700 (PDT) Received: from pek-vx-bsp2.wrs.com (unknown-146-144.windriver.com. [147.11.146.144]) by smtp.gmail.com with ESMTPSA id 16sm9836332pfi.161.2020.08.14.09.41.32 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Aug 2020 09:41:35 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 08/18] hw/sd: sd: Correctly set the high capacity bit Date: Sat, 15 Aug 2020 00:40:46 +0800 Message-Id: <1597423256-14847-9-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> References: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-block@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Per the SD spec, Standard Capacity SD Memory Card (SDSC) supports capacity up to and including 2 GiB. Signed-off-by: Bin Meng --- hw/sd/sd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 51f5900..5e7fc3f 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -313,7 +313,7 @@ static void sd_ocr_powerup(void *opaque) /* card power-up OK */ sd->ocr = FIELD_DP32(sd->ocr, OCR, CARD_POWER_UP, 1); - if (sd->size > 1 * GiB) { + if (sd->size > 2 * GiB) { sd->ocr = FIELD_DP32(sd->ocr, OCR, CARD_CAPACITY, 1); } } From patchwork Fri Aug 14 16:40:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1345114 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=Iw2ORdrO; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSq9p6Lc4z9sT6 for ; Sat, 15 Aug 2020 02:47:42 +1000 (AEST) Received: from localhost ([::1]:33964 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k6crk-0000y2-J4 for incoming@patchwork.ozlabs.org; Fri, 14 Aug 2020 12:47:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47310) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k6cly-0007oU-QI; Fri, 14 Aug 2020 12:41:42 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:33338) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1k6clx-0002hX-65; Fri, 14 Aug 2020 12:41:42 -0400 Received: by mail-pg1-x541.google.com with SMTP id o13so4805404pgf.0; Fri, 14 Aug 2020 09:41:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lLlhx5CzsuWNvvuCgJY3iCdBxbSqBU5q/tvZAS1xP3s=; b=Iw2ORdrOHoYtj2DcU/YD+vdQr+l9kZi5aWxxn4XNisZjnS2Q0lJb/MIow7oZQlFHJK SNOOsRImVPI2uuaNvGeRWR/9TcqukL+pIqJsCY7BK65Y4cblkgBglU2eAa1QyRrZLjNV QOC84d1OOuuZ7QvWWsOVEiOSSDvoeaFklNujaLCeZ2sCupSB4ScaUJlu7vwLrY/Masg8 FeByPra6l3iGGtcpYjzD7sl+++B+4lc5mhaSpItnVa0/6VAHjhTdZ1d//5WU2LvDIppR PpyaMmS7ecTjWbbpBd7ghNjf+n6TV3t00ztddRogjhDCnRbfKLLcuMmt0dJZiPpQ1ahR Sg+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lLlhx5CzsuWNvvuCgJY3iCdBxbSqBU5q/tvZAS1xP3s=; b=aR1dQZuh/VWttQlGfWEnz5RlQZ5wHgJJTHKBmDLzmml21oLgXYvhWjS3uEb4mRKcfv ULYxrPuHHDGMaWIRXMGYNTcLA2/U88FTsU982+qURrrAFKl8RIOTN1RXUExub+TBOG+c 1dbWpDLtiAin+w/ilnHKYET6f1L06EqZxgzptlxcBVs8+H8tz6Nb9YPtNPYukcbD55nY MkyF79Ps2160eMP72B/V1da3fLMZS0KO6fWGaWPZd9hj/gC1J0eKiHOlOvmUzqBNDBoj si2voxu5OsCqGAprGiTFKp7D9ldzD2XRvWtPfWVkkvloj3UsZtw294YtgtwK94YETV/g UrEg== X-Gm-Message-State: AOAM53291O7Ey8gvTavXGWntRqn2clFDRq8ew6ENS9WIr3xJENkhwo1G NO4PQaRDAfmUd5i8okWrFMY= X-Google-Smtp-Source: ABdhPJyfoqeRpC31wtCCW3DbDXFVAhm+TyzBnXTOW2B6QK04eOjCQ9+1Am6FBWo7VxLEBJlcaUamPw== X-Received: by 2002:a63:1a66:: with SMTP id a38mr2246103pgm.253.1597423299188; Fri, 14 Aug 2020 09:41:39 -0700 (PDT) Received: from pek-vx-bsp2.wrs.com (unknown-146-144.windriver.com. [147.11.146.144]) by smtp.gmail.com with ESMTPSA id 16sm9836332pfi.161.2020.08.14.09.41.36 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Aug 2020 09:41:38 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 09/18] hw/sd: sdhci: Make sdhci_poweron_reset() internal visible Date: Sat, 15 Aug 2020 00:40:47 +0800 Message-Id: <1597423256-14847-10-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> References: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-block@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng sdhci_poweron_reset() might be needed for any SDHCI compatible device that is built on top of the generic SDHCI device. Signed-off-by: Bin Meng --- hw/sd/sdhci-internal.h | 1 + hw/sd/sdhci.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index e8c753d..b587e8e 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -342,5 +342,6 @@ void sdhci_uninitfn(SDHCIState *s); void sdhci_common_realize(SDHCIState *s, Error **errp); void sdhci_common_unrealize(SDHCIState *s); void sdhci_common_class_init(ObjectClass *klass, void *data); +void sdhci_poweron_reset(DeviceState *dev); #endif diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index deac181..20f2fe0 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -294,7 +294,7 @@ static void sdhci_reset(SDHCIState *s) s->pending_insert_state = false; } -static void sdhci_poweron_reset(DeviceState *dev) +void sdhci_poweron_reset(DeviceState *dev) { /* QOM (ie power-on) reset. This is identical to reset * commanded via device register apart from handling of the From patchwork Fri Aug 14 16:40:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1345109 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=mjAqpr6G; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSq6S1SPQz9sTW for ; Sat, 15 Aug 2020 02:44:48 +1000 (AEST) Received: from localhost ([::1]:50670 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k6cov-0004Yh-TT for incoming@patchwork.ozlabs.org; Fri, 14 Aug 2020 12:44:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47338) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k6cm3-0007zj-AO; Fri, 14 Aug 2020 12:41:47 -0400 Received: from mail-pj1-x1042.google.com ([2607:f8b0:4864:20::1042]:52753) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1k6cm1-0002iJ-71; Fri, 14 Aug 2020 12:41:46 -0400 Received: by mail-pj1-x1042.google.com with SMTP id kr4so4665656pjb.2; Fri, 14 Aug 2020 09:41:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9ASlt84VPNpgMOgTGGDjknhiaN8WnaW8vF8XcV6uIN0=; b=mjAqpr6GUGFAtHvQKyMNQh+Y1xxmukmxKuF/thKgdsL4Uc8Gn6SsNCrmfob3AuClny ASgj90YQMx7N7iNoyTrAb8eCCDNzduz6VkzpqZWNQVsv9Ze0sdWGwZVlJe8xjL/GavgS KG7Qh+49qws+IB7h91fT0Y+nh3VOR52ZAItSdA0QzphbgrcghetjngfD2FzXZDSyx0Q3 UzgxG/Yd4LXxk4mwZPb9MPhtcFvhgc2CcI9CmuBvr5fqIdzggKEzMLxVektv808gtb2w b62lSwjHnJG/8gpIlOwdGA0K9aZ1o+hn7M/nlmACy3YulesPvZZjV8W/tdmkrPBIaiA7 ryLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9ASlt84VPNpgMOgTGGDjknhiaN8WnaW8vF8XcV6uIN0=; b=IkYAlpnIZVG2ZdBDC3LHytDVbMkvDE8IypPyO1jN/F4S9zPKb9G4G9J7Z3EIinElgQ ZoDjY7lqSfFjyDpC/ig5SmvU5hbUVtlCGd1faCAepehTOn3w+DS3XWtRzjL/AfVLE93U ricy76C8t2gK32YGbjMaj9LQJ9c1ASSMVOfj0FaxusHTES8IItxlwubmr/m3doCiE4dp q6j1OMLxdLHR6FkcKxm1P8/pv6fgFOE6D2l6Dn04ZjTXBg7whxheVZ24deg7jYyxSc1D A8W14HO4l4Q69kSWy0AHIMht2arnz9/BPehZaOzYT2ibx6fFRz4rDGH+HH/7PQ4TNi1T 0Z6A== X-Gm-Message-State: AOAM531KoF3OZS1/JAzfltFR0GWWzor39szX0+YQniUSHxPfYC3QRD/G D7ppjK1jkEIDtnoDLGw1ad8= X-Google-Smtp-Source: ABdhPJy7zG1SPvhcc0cMql5ijKKSaD37auSGzKz14JKlycTTtS7CoRbdvO0sVuk0c7PMQTICBVjasA== X-Received: by 2002:a17:90b:241:: with SMTP id fz1mr979491pjb.213.1597423303296; Fri, 14 Aug 2020 09:41:43 -0700 (PDT) Received: from pek-vx-bsp2.wrs.com (unknown-146-144.windriver.com. [147.11.146.144]) by smtp.gmail.com with ESMTPSA id 16sm9836332pfi.161.2020.08.14.09.41.39 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Aug 2020 09:41:42 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 10/18] hw/sd: Add Cadence SDHCI emulation Date: Sat, 15 Aug 2020 00:40:48 +0800 Message-Id: <1597423256-14847-11-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> References: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , Bin Meng , qemu-arm@nongnu.org, Alistair Francis , Peter Maydell Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible controller. The SDHCI compatible registers start from offset 0x200, which are called Slot Register Set (SRS) in its datasheet. This creates a Cadence SDHCI model built on top of the existing generic SDHCI model. Cadence specific Host Register Set (HRS) is implemented to make guest software happy. Signed-off-by: Bin Meng --- hw/sd/Kconfig | 4 ++ hw/sd/Makefile.objs | 1 + hw/sd/cadence_sdhci.c | 162 ++++++++++++++++++++++++++++++++++++++++++ include/hw/sd/cadence_sdhci.h | 65 +++++++++++++++++ 4 files changed, 232 insertions(+) create mode 100644 hw/sd/cadence_sdhci.c create mode 100644 include/hw/sd/cadence_sdhci.h diff --git a/hw/sd/Kconfig b/hw/sd/Kconfig index c5e1e55..633b9af 100644 --- a/hw/sd/Kconfig +++ b/hw/sd/Kconfig @@ -19,3 +19,7 @@ config SDHCI_PCI default y if PCI_DEVICES depends on PCI select SDHCI + +config CADENCE_SDHCI + bool + select SDHCI diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs index 0d1df17..4d500a6 100644 --- a/hw/sd/Makefile.objs +++ b/hw/sd/Makefile.objs @@ -10,3 +10,4 @@ common-obj-$(CONFIG_OMAP) += omap_mmc.o common-obj-$(CONFIG_PXA2XX) += pxa2xx_mmci.o common-obj-$(CONFIG_RASPI) += bcm2835_sdhost.o common-obj-$(CONFIG_ASPEED_SOC) += aspeed_sdhci.o +common-obj-$(CONFIG_CADENCE_SDHCI) += cadence_sdhci.o diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c new file mode 100644 index 0000000..67ffd14 --- /dev/null +++ b/hw/sd/cadence_sdhci.c @@ -0,0 +1,162 @@ +/* + * Cadence SDHCI emulation + * + * Copyright (c) 2020 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "migration/vmstate.h" +#include "hw/irq.h" +#include "hw/sd/cadence_sdhci.h" +#include "sdhci-internal.h" + +#define TO_REG(addr) ((addr) / sizeof(uint32_t)) + +static void cadence_sdhci_reset(DeviceState *dev) +{ + CadenceSDHCIState *sdhci = CADENCE_SDHCI(dev); + + memset(sdhci->regs, 0, CADENCE_SDHCI_REG_SIZE); + sdhci->regs[TO_REG(SDHCI_CDNS_HRS00)] = SDHCI_CDNS_HRS00_POR_VAL; +} + +static uint64_t cadence_sdhci_read(void *opaque, hwaddr addr, unsigned int size) +{ + uint32_t val = 0; + CadenceSDHCIState *sdhci = opaque; + + if (addr < CADENCE_SDHCI_REG_SIZE) { + val = sdhci->regs[TO_REG(addr)]; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds read at 0x%" HWADDR_PRIx "\n", + __func__, addr); + } + + return (uint64_t)val; +} + +static void cadence_sdhci_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int size) +{ + CadenceSDHCIState *sdhci = opaque; + uint32_t val32 = (uint32_t)val; + + switch (addr) { + case SDHCI_CDNS_HRS00: + /* + * The only writable bit is SWR (software reset) and it automatically + * clears to zero, so essentially this register remains unchanged. + */ + if (val32 & SDHCI_CDNS_HRS00_SWR) { + cadence_sdhci_reset(DEVICE(sdhci)); + sdhci_poweron_reset(DEVICE(&sdhci->slot)); + } + + break; + case SDHCI_CDNS_HRS04: + /* + * Only emulate the ACK bit behavior when read or write transaction + * are requested. + */ + if (val32 & (SDHCI_CDNS_HRS04_WR | SDHCI_CDNS_HRS04_RD)) { + val32 |= SDHCI_CDNS_HRS04_ACK; + } else { + val32 &= ~SDHCI_CDNS_HRS04_ACK; + } + + sdhci->regs[TO_REG(addr)] = val32; + break; + case SDHCI_CDNS_HRS06: + if (val32 & SDHCI_CDNS_HRS06_TUNE_UP) { + val32 &= ~SDHCI_CDNS_HRS06_TUNE_UP; + } + + sdhci->regs[TO_REG(addr)] = val32; + break; + default: + if (addr < CADENCE_SDHCI_REG_SIZE) { + sdhci->regs[TO_REG(addr)] = val32; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds write at 0x%" HWADDR_PRIx "\n", + __func__, addr); + } + } +} + +static const MemoryRegionOps cadence_sdhci_ops = { + .read = cadence_sdhci_read, + .write = cadence_sdhci_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + } +}; + +static void cadence_sdhci_realize(DeviceState *dev, Error **errp) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + CadenceSDHCIState *sdhci = CADENCE_SDHCI(dev); + SysBusDevice *sbd_slot = SYS_BUS_DEVICE(&sdhci->slot); + + memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &cadence_sdhci_ops, + sdhci, TYPE_CADENCE_SDHCI, 0x1000); + sysbus_init_mmio(sbd, &sdhci->iomem); + + sysbus_realize(sbd_slot, errp); + memory_region_add_subregion(&sdhci->iomem, SDHCI_CDNS_SRS_BASE, + &sdhci->slot.iomem); +} + +static const VMStateDescription vmstate_cadence_sdhci = { + .name = TYPE_CADENCE_SDHCI, + .version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, CadenceSDHCIState, CADENCE_SDHCI_NUM_REGS), + VMSTATE_END_OF_LIST(), + }, +}; + +static void cadence_sdhci_class_init(ObjectClass *classp, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(classp); + + dc->realize = cadence_sdhci_realize; + dc->reset = cadence_sdhci_reset; + dc->vmsd = &vmstate_cadence_sdhci; +} + +static TypeInfo cadence_sdhci_info = { + .name = TYPE_CADENCE_SDHCI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(CadenceSDHCIState), + .class_init = cadence_sdhci_class_init, +}; + +static void cadence_sdhci_register_types(void) +{ + type_register_static(&cadence_sdhci_info); +} + +type_init(cadence_sdhci_register_types) diff --git a/include/hw/sd/cadence_sdhci.h b/include/hw/sd/cadence_sdhci.h new file mode 100644 index 0000000..9ff78a9 --- /dev/null +++ b/include/hw/sd/cadence_sdhci.h @@ -0,0 +1,65 @@ +/* + * Cadence SDHCI emulation + * + * Copyright (c) 2020 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef CADENCE_SDHCI_H +#define CADENCE_SDHCI_H + +#include "qemu/bitops.h" +#include "hw/sd/sdhci.h" + +/* HRS - Host Register Set (specific to Cadence) */ + +#define SDHCI_CDNS_HRS00 0x00 /* general information */ +#define SDHCI_CDNS_HRS00_SWR BIT(0) +#define SDHCI_CDNS_HRS00_POR_VAL 0x00010000 + +#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */ +#define SDHCI_CDNS_HRS04_WR BIT(24) +#define SDHCI_CDNS_HRS04_RD BIT(25) +#define SDHCI_CDNS_HRS04_ACK BIT(26) + +#define SDHCI_CDNS_HRS06 0x18 /* eMMC control */ +#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15) + +/* SRS - Slot Register Set (SDHCI-compatible) */ +#define SDHCI_CDNS_SRS_BASE 0x200 + +#define CADENCE_SDHCI_CAPABILITIES 0x01E80080 +#define CADENCE_SDHCI_REG_SIZE 0x100 +#define CADENCE_SDHCI_NUM_REGS (CADENCE_SDHCI_REG_SIZE / sizeof(uint32_t)) + +typedef struct CadenceSDHCIState { + SysBusDevice parent; + + MemoryRegion iomem; + qemu_irq irq; + + uint32_t regs[CADENCE_SDHCI_NUM_REGS]; + + SDHCIState slot; +} CadenceSDHCIState; + +#define TYPE_CADENCE_SDHCI "cadence.sdhci" +#define CADENCE_SDHCI(obj) OBJECT_CHECK(CadenceSDHCIState, (obj), \ + TYPE_CADENCE_SDHCI) + +#endif /* CADENCE_SDHCI_H */ From patchwork Fri Aug 14 16:40:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1345113 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=ZwdayXy9; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSq8x1WxYz9sT6 for ; Sat, 15 Aug 2020 02:46:57 +1000 (AEST) Received: from localhost ([::1]:59220 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k6cr0-0008Ay-UM for incoming@patchwork.ozlabs.org; Fri, 14 Aug 2020 12:46:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47366) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k6cm6-00088m-Lk; Fri, 14 Aug 2020 12:41:50 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:38693) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1k6cm4-0002im-KG; Fri, 14 Aug 2020 12:41:50 -0400 Received: by mail-pf1-x444.google.com with SMTP id d22so4815587pfn.5; Fri, 14 Aug 2020 09:41:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FK50ORz16F3dnaLHeIWxnRqzsyIO5VCFaWwZ349ZLBQ=; b=ZwdayXy92Zc009OwTIbJbfKn8uCZoQP111ub8pqYd3cK9Nx9K7tFMvQWArFLSlQI7w dBcDNbbdIEOukzLAPqrh1SrnK05HNd+jxPsDYfQRp5dAhxVGCgpk5G32TnUxfYw1jlDS VotQ20tNL9PXRIisZjfleZxWc/uRVWDaNQKuV9nECvasxBZzAfWV6ETL5ItohLqN7utd L36lZAOKV3vib+/+u5pRMl+MwYHVYdRbuesydup5gHenhozN5MMVwk6SVqBmL47FrtA8 6b5gSEOOEsO2j/jHgci3W4/OitnoRkadKgnxaXgAUI3UwfTT443+LPLHFyZq6g2XoyaT B8zQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FK50ORz16F3dnaLHeIWxnRqzsyIO5VCFaWwZ349ZLBQ=; b=NPwF0hSN2G1lzWP3aZinY6xNYwIt/LWPvJJnAhUkHJHFNFHBmp4OHXWGWcbEx97JrJ +TVOZB0XklJAYf2UJmaUmUyG06mNDJMU+n75gGYIpuZAIWS5jCIPmusmvJ9jNUB0W9/A vK9PVeaRSiVaIWrFXafiN4T+07zzfDtPyhNdMf9T8/v0hLkBiil34VNXSfTGFEoVwzVQ kzCdGqPJYeO1gZQRGo3AFk7uMeh8DgAN7ZjfaHOAkSsKd2T7HcB8RjLTTAvmrafCs4hZ qwunQhzxO29qgOHwhbeoG1HCy2CawNQgDI/UKexR57vthONnAWKK2zUYZKzqnkEZqBwL SOIw== X-Gm-Message-State: AOAM5336naaQgbes+UZkbeYQGpTbvkpHaTp+wxs4rgTsQlHu+GJKy6lf lmoUCPWiFgvsnYJzavaCJw4= X-Google-Smtp-Source: ABdhPJxzS2vMKeKILxWuL1Ege8SIBqWqDAeic59RVa3oqxjTSVteoA48phwxoZZMAaWijIfT/36Bqw== X-Received: by 2002:a63:af47:: with SMTP id s7mr2381722pgo.335.1597423306955; Fri, 14 Aug 2020 09:41:46 -0700 (PDT) Received: from pek-vx-bsp2.wrs.com (unknown-146-144.windriver.com. [147.11.146.144]) by smtp.gmail.com with ESMTPSA id 16sm9836332pfi.161.2020.08.14.09.41.43 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Aug 2020 09:41:46 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 11/18] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card Date: Sat, 15 Aug 2020 00:40:49 +0800 Message-Id: <1597423256-14847-12-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> References: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Microchip PolarFire SoC integrates one Cadence SDHCI controller. On the Icicle Kit board, one eMMC chip and an external SD card connect to this controller depending on different configuration. As QEMU does not support eMMC yet, we just emulate the SD card configuration. To test this, the Hart Software Services (HSS) should choose the SD card configuration: $ cp boards/icicle-kit-es/def_config.sdcard .config $ make BOARD=icicle-kit-es The SD card image can be built from the Yocto BSP at: https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp Note the generated SD card image should be resized before use: $ qemu-img resize /path/to/sdcard.img 4G Launch QEMU with the following command: $ qemu-system-riscv64 -nographic -M microchip-icicle-kit -sd sdcard.img Signed-off-by: Bin Meng --- hw/riscv/Kconfig | 1 + hw/riscv/microchip_pfsoc.c | 26 ++++++++++++++++++++++++++ include/hw/riscv/microchip_pfsoc.h | 4 ++++ 3 files changed, 31 insertions(+) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index ceb7c16..7412db9 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -55,3 +55,4 @@ config MICROCHIP_PFSOC select SIFIVE select UNIMP select MCHP_PFSOC_MMUART + select CADENCE_SDHCI diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index f6b375c..7c09078 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -12,6 +12,7 @@ * 1) PLIC (Platform Level Interrupt Controller) * 2) eNVM (Embedded Non-Volatile Memory) * 3) MMUARTs (Multi-Mode UART) + * 4) Cadence eMMC/SDHC controller and an SD card connected to it * * This board currently generates devicetree dynamically that indicates at least * two harts and up to five harts. @@ -75,6 +76,7 @@ static const struct MemmapEntry { [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, + [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 }, [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 }, [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, @@ -111,6 +113,11 @@ static void microchip_pfsoc_soc_instance_init(Object *obj) qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", TYPE_RISCV_CPU_SIFIVE_U54); qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR); + + object_initialize_child(obj, "sd-controller", &s->sdhci, + TYPE_CADENCE_SDHCI); + object_initialize_child(OBJECT(&s->sdhci), "sd-controller.sdhci", + &s->sdhci.slot, TYPE_SYSBUS_SDHCI); } static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) @@ -223,6 +230,13 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) memmap[MICROCHIP_PFSOC_MPUCFG].base, memmap[MICROCHIP_PFSOC_MPUCFG].size); + /* SDHCI */ + sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, + memmap[MICROCHIP_PFSOC_EMMC_SD].base); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci.slot), 0, + qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ)); + /* MMUARTs */ s->serial0 = mchp_pfsoc_mmuart_create(system_memory, memmap[MICROCHIP_PFSOC_MMUART0].base, @@ -290,6 +304,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine); MemoryRegion *system_memory = get_system_memory(); MemoryRegion *main_mem = g_new(MemoryRegion, 1); + DriveInfo *dinfo = drive_get_next(IF_SD); /* Sanity check on RAM size */ if (machine->ram_size < mc->default_ram_size) { @@ -312,6 +327,17 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) /* Load the firmware */ riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL); + + /* Attach an SD card */ + if (dinfo) { + SDHCIState *sdhci = &(s->soc.sdhci.slot); + DeviceState *card = qdev_new(TYPE_SD_CARD); + BusState *bus = qdev_get_child_bus(DEVICE(sdhci), "sd-bus"); + + qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), + &error_fatal); + qdev_realize_and_unref(card, bus, &error_fatal); + } } static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index a5efa1d..d810ee8 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -23,6 +23,7 @@ #define HW_MICROCHIP_PFSOC_H #include "hw/char/mchp_pfsoc_mmuart.h" +#include "hw/sd/cadence_sdhci.h" typedef struct MicrochipPFSoCState { /*< private >*/ @@ -39,6 +40,7 @@ typedef struct MicrochipPFSoCState { MchpPfSoCMMUartState *serial2; MchpPfSoCMMUartState *serial3; MchpPfSoCMMUartState *serial4; + CadenceSDHCIState sdhci; } MicrochipPFSoCState; #define TYPE_MICROCHIP_PFSOC "microchip.pfsoc" @@ -74,6 +76,7 @@ enum { MICROCHIP_PFSOC_MMUART0, MICROCHIP_PFSOC_SYSREG, MICROCHIP_PFSOC_MPUCFG, + MICROCHIP_PFSOC_EMMC_SD, MICROCHIP_PFSOC_MMUART1, MICROCHIP_PFSOC_MMUART2, MICROCHIP_PFSOC_MMUART3, @@ -85,6 +88,7 @@ enum { }; enum { + MICROCHIP_PFSOC_EMMC_SD_IRQ = 88, MICROCHIP_PFSOC_MMUART0_IRQ = 90, MICROCHIP_PFSOC_MMUART1_IRQ = 91, MICROCHIP_PFSOC_MMUART2_IRQ = 92, From patchwork Fri Aug 14 16:40:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1345135 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id 16sm9836332pfi.161.2020.08.14.09.41.47 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Aug 2020 09:41:49 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 12/18] hw/dma: Add Microchip PolarFire Soc DMA controller emulation Date: Sat, 15 Aug 2020 00:40:50 +0800 Message-Id: <1597423256-14847-13-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> References: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x644.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Microchip PolarFire SoC integrates a DMA engine that supports: * Independent concurrent DMA transfers using 4 DMA channels * Generation of interrupts on various conditions during execution This creates a simple model to support polling mode which is enough for firmware usage. While there are codes for interrupts handling, please note the interrupt path has not been validated due to missing kernel driver for testing as of now. Signed-off-by: Bin Meng --- MAINTAINERS | 2 + hw/dma/Kconfig | 3 + hw/dma/Makefile.objs | 1 + hw/dma/mchp_pfsoc_dma.c | 322 ++++++++++++++++++++++++++++++++++++++++ include/hw/dma/mchp_pfsoc_dma.h | 57 +++++++ 5 files changed, 385 insertions(+) create mode 100644 hw/dma/mchp_pfsoc_dma.c create mode 100644 include/hw/dma/mchp_pfsoc_dma.h diff --git a/MAINTAINERS b/MAINTAINERS index e51edac..0aacc90 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1320,8 +1320,10 @@ L: qemu-riscv@nongnu.org S: Supported F: hw/riscv/microchip_pfsoc.c F: hw/char/mchp_pfsoc_mmuart.c +F: hw/dma/mchp_pfsoc_dma.c F: include/hw/riscv/microchip_pfsoc.h F: include/hw/char/mchp_pfsoc_mmuart.h +F: include/hw/dma/mchp_pfsoc_dma.h RX Machines ----------- diff --git a/hw/dma/Kconfig b/hw/dma/Kconfig index 5c61b67..778e20b 100644 --- a/hw/dma/Kconfig +++ b/hw/dma/Kconfig @@ -20,3 +20,6 @@ config ZYNQ_DEVCFG config STP2000 bool + +config MCHP_PFSOC_DMA + bool diff --git a/hw/dma/Makefile.objs b/hw/dma/Makefile.objs index f4b1cfe..fd7e836 100644 --- a/hw/dma/Makefile.objs +++ b/hw/dma/Makefile.objs @@ -14,3 +14,4 @@ common-obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zdma.o common-obj-$(CONFIG_OMAP) += omap_dma.o soc_dma.o common-obj-$(CONFIG_PXA2XX) += pxa2xx_dma.o common-obj-$(CONFIG_RASPI) += bcm2835_dma.o +common-obj-$(CONFIG_MCHP_PFSOC_DMA) += mchp_pfsoc_dma.o diff --git a/hw/dma/mchp_pfsoc_dma.c b/hw/dma/mchp_pfsoc_dma.c new file mode 100644 index 0000000..8531a6f --- /dev/null +++ b/hw/dma/mchp_pfsoc_dma.c @@ -0,0 +1,322 @@ +/* + * Microchip PolarFire SoC DMA emulation + * + * Copyright (c) 2020 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "hw/hw.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "sysemu/dma.h" +#include "hw/dma/mchp_pfsoc_dma.h" + +#define DMA_CONTROL 0x000 +#define CONTROL_CLAIM BIT(0) +#define CONTROL_RUN BIT(1) +#define CONTROL_DONE_IE BIT(14) +#define CONTROL_ERR_IE BIT(15) +#define CONTROL_DONE BIT(30) +#define CONTROL_ERR BIT(31) + +#define DMA_NEXT_CONFIG 0x004 +#define CONFIG_REPEAT BIT(2) +#define CONFIG_ORDER BIT(3) +#define CONFIG_WRSZ_SHIFT 24 +#define CONFIG_RDSZ_SHIFT 28 +#define CONFIG_SZ_MASK 0xf + +#define DMA_NEXT_BYTES 0x008 +#define DMA_NEXT_DST 0x010 +#define DMA_NEXT_SRC 0x018 +#define DMA_EXEC_CONFIG 0x104 +#define DMA_EXEC_BYTES 0x108 +#define DMA_EXEC_DST 0x110 +#define DMA_EXEC_SRC 0x118 + +enum dma_chan_state { + DMA_CHAN_STATE_IDLE, + DMA_CHAN_STATE_STARTED, + DMA_CHAN_STATE_ERROR, + DMA_CHAN_STATE_DONE +}; + +static void mchp_pfsoc_dma_run(MchpPfSoCDMAState *s, int ch) +{ + uint64_t bytes = s->chan[ch].next_bytes; + uint64_t dst = s->chan[ch].next_dst; + uint64_t src = s->chan[ch].next_src; + uint32_t config = s->chan[ch].next_config; + int wsize, rsize, size; + uint8_t buf[64]; + int n; + + /* do nothing if bytes to transfer is zero */ + if (!bytes) { + goto error; + } + + /* + * The manual does not describe how the hardware behaviors when + * config.wsize and config.rsize are given different values. + * A common case is memory to memory DMA, and in this case they + * are normally the same. Abort if this expectation fails. + */ + wsize = (config >> CONFIG_WRSZ_SHIFT) & CONFIG_SZ_MASK; + rsize = (config >> CONFIG_RDSZ_SHIFT) & CONFIG_SZ_MASK; + if (wsize != rsize) { + goto error; + } + + /* + * Calculate the transaction size + * + * size field is base 2 logarithm of DMA transaction size, + * but there is an upper limit of 64 bytes per transaction. + */ + size = wsize; + if (size > 6) { + size = 6; + } + size = 1 << size; + + /* the bytes to transfer should be multiple of transaction size */ + if (bytes % size) { + goto error; + } + + /* inidate a DMA transfer is started */ + s->chan[ch].state = DMA_CHAN_STATE_STARTED; + s->chan[ch].control |= CONTROL_CLAIM; + s->chan[ch].control &= ~CONTROL_DONE; + s->chan[ch].control &= ~CONTROL_ERR; + + /* load the next_ registers into their exec_ counterparts */ + s->chan[ch].exec_config = config; + s->chan[ch].exec_bytes = bytes; + s->chan[ch].exec_dst = dst; + s->chan[ch].exec_src = src; + + for (n = 0; n < bytes / size; n++) { + cpu_physical_memory_read(s->chan[ch].exec_src, buf, size); + cpu_physical_memory_write(s->chan[ch].exec_dst, buf, size); + s->chan[ch].exec_src += size; + s->chan[ch].exec_dst += size; + s->chan[ch].exec_bytes -= size; + } + + /* inidate a DMA transfer is done */ + s->chan[ch].state = DMA_CHAN_STATE_DONE; + s->chan[ch].control &= ~CONTROL_CLAIM; + s->chan[ch].control &= ~CONTROL_RUN; + s->chan[ch].control |= CONTROL_DONE; + + /* reload exec_ registers if repeat is required */ + if (s->chan[ch].next_config & CONFIG_REPEAT) { + s->chan[ch].exec_bytes = bytes; + s->chan[ch].exec_dst = dst; + s->chan[ch].exec_src = src; + } + + return; + +error: + s->chan[ch].state = DMA_CHAN_STATE_ERROR; + s->chan[ch].control |= CONTROL_ERR; + return; +} + +static inline void mchp_pfsoc_dma_update_irq(MchpPfSoCDMAState *s, int ch) +{ + bool done_ie, err_ie; + + done_ie = !!(s->chan[ch].control & CONTROL_DONE_IE); + err_ie = !!(s->chan[ch].control & CONTROL_ERR_IE); + + /* + * Todo: + * + * It's unclear from the manual when the interrupt will be lowered. + * It might be that the ISR reads the status bits and writes 1 to clear, + * Right now there is no driver that uses ISR to validate this guess. + * + * Also the manual does not clear describe how the 2 interrupt lines + * are routed to PLIC hence we assume only 1 line for now. + */ + if ((done_ie && (s->chan[ch].control & CONTROL_DONE)) || + (err_ie && (s->chan[ch].control & CONTROL_ERR))) { + qemu_irq_raise(s->irq); + } else { + qemu_irq_lower(s->irq); + } + + s->chan[ch].state = DMA_CHAN_STATE_IDLE; +} + +static uint64_t mchp_pfsoc_dma_read(void *opaque, hwaddr offset, unsigned size) +{ + MchpPfSoCDMAState *s = opaque; + int no = MCHP_PFSOC_DMA_CHAN_NO(offset); + uint64_t val = 0; + + if (no >= MCHP_PFSOC_DMA_CHANS) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n", + __func__, no); + return 0; + } + + switch (offset) { + case DMA_CONTROL: + val = s->chan[no].control; + break; + case DMA_NEXT_CONFIG: + val = s->chan[no].next_config; + break; + case DMA_NEXT_BYTES: + val = s->chan[no].next_bytes; + break; + case DMA_NEXT_DST: + val = s->chan[no].next_dst; + break; + case DMA_NEXT_SRC: + val = s->chan[no].next_src; + break; + case DMA_EXEC_CONFIG: + val = s->chan[no].exec_config; + break; + case DMA_EXEC_BYTES: + val = s->chan[no].exec_bytes; + break; + case DMA_EXEC_DST: + val = s->chan[no].exec_dst; + break; + case DMA_EXEC_SRC: + val = s->chan[no].exec_src; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", + __func__, offset); + break; + } + + return val; +} + +static void mchp_pfsoc_dma_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + MchpPfSoCDMAState *s = opaque; + int no = MCHP_PFSOC_DMA_CHAN_NO(offset); + + if (no >= MCHP_PFSOC_DMA_CHANS) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n", + __func__, no); + return; + } + + switch (offset) { + case DMA_CONTROL: + s->chan[no].control = value; + + if (value & CONTROL_CLAIM) { + s->chan[no].next_config = 0; + s->chan[no].next_bytes = 0; + s->chan[no].next_dst = 0; + s->chan[no].next_src = 0; + s->chan[no].control &= ~CONTROL_CLAIM; + } + + if (value & CONTROL_RUN) { + mchp_pfsoc_dma_run(s, no); + } + + mchp_pfsoc_dma_update_irq(s, no); + break; + case DMA_NEXT_CONFIG: + s->chan[no].next_config = value; + break; + case DMA_NEXT_BYTES: + s->chan[no].next_bytes = value; + break; + case DMA_NEXT_DST: + s->chan[no].next_dst = value; + break; + case DMA_NEXT_SRC: + s->chan[no].next_src = value; + break; + case DMA_EXEC_CONFIG: + case DMA_EXEC_BYTES: + case DMA_EXEC_DST: + case DMA_EXEC_SRC: + /* these are read-only registers */ + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", + __func__, offset); + break; + } +} + +static const MemoryRegionOps mchp_pfsoc_dma_ops = { + .read = mchp_pfsoc_dma_read, + .write = mchp_pfsoc_dma_write, + .endianness = DEVICE_LITTLE_ENDIAN, + /* there are 32-bit and 64-bit wide registers */ + .impl = { + .min_access_size = 4, + .max_access_size = 8, + } +}; + +static void mchp_pfsoc_dma_realize(DeviceState *dev, Error **errp) +{ + MchpPfSoCDMAState *s = MCHP_PFSOC_DMA(dev); + + memory_region_init_io(&s->iomem, OBJECT(dev), &mchp_pfsoc_dma_ops, s, + "mchp.pfsoc.dma", MCHP_PFSOC_DMA_REG_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); +} + +static void mchp_pfsoc_dma_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->desc = "Microchip PolarFire SoC DMA controller"; + dc->realize = mchp_pfsoc_dma_realize; +} + +static const TypeInfo mchp_pfsoc_dma_info = { + .name = TYPE_MCHP_PFSOC_DMA, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(MchpPfSoCDMAState), + .class_init = mchp_pfsoc_dma_class_init, +}; + +static void mchp_pfsoc_dma_register_types(void) +{ + type_register_static(&mchp_pfsoc_dma_info); +} + +type_init(mchp_pfsoc_dma_register_types) diff --git a/include/hw/dma/mchp_pfsoc_dma.h b/include/hw/dma/mchp_pfsoc_dma.h new file mode 100644 index 0000000..e474f67 --- /dev/null +++ b/include/hw/dma/mchp_pfsoc_dma.h @@ -0,0 +1,57 @@ +/* + * Microchip PolarFire SoC DMA emulation + * + * Copyright (c) 2020 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef MCHP_PFSOC_DMA_H +#define MCHP_PFSOC_DMA_H + +struct mchp_pfsoc_dma_chan { + uint32_t control; + uint32_t next_config; + uint64_t next_bytes; + uint64_t next_dst; + uint64_t next_src; + uint32_t exec_config; + uint64_t exec_bytes; + uint64_t exec_dst; + uint64_t exec_src; + int state; +}; + +#define MCHP_PFSOC_DMA_CHANS 4 +#define MCHP_PFSOC_DMA_REG_SIZE 0x100000 +#define MCHP_PFSOC_DMA_CHAN_NO(reg) \ + ((reg & (MCHP_PFSOC_DMA_REG_SIZE - 1)) >> 12) + +typedef struct MchpPfSoCDMAState { + SysBusDevice parent; + MemoryRegion iomem; + qemu_irq irq; + + struct mchp_pfsoc_dma_chan chan[MCHP_PFSOC_DMA_CHANS]; +} MchpPfSoCDMAState; + +#define TYPE_MCHP_PFSOC_DMA "mchp.pfsoc.dma" + +#define MCHP_PFSOC_DMA(obj) \ + OBJECT_CHECK(MchpPfSoCDMAState, (obj), TYPE_MCHP_PFSOC_DMA) + +#endif /* MCHP_PFSOC_DMA_H */ From patchwork Fri Aug 14 16:40:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1345115 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=AoQflcKA; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSqCC5x2qz9sT6 for ; Sat, 15 Aug 2020 02:48:55 +1000 (AEST) Received: from localhost ([::1]:38854 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k6csv-0002xv-1s for incoming@patchwork.ozlabs.org; Fri, 14 Aug 2020 12:48:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47400) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k6cmC-0008Mg-5U; Fri, 14 Aug 2020 12:41:56 -0400 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]:35679) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1k6cmA-0002jP-Ex; Fri, 14 Aug 2020 12:41:55 -0400 Received: by mail-pj1-x1043.google.com with SMTP id t6so4643297pjr.0; Fri, 14 Aug 2020 09:41:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ypar0ej4TvEEf95rRUUSazBC6MGwvwdLxXN4saosWNU=; b=AoQflcKAnHoQGs389FJn1npINdb38HAWSfyEay6VmmOfnsaR1WENT2f3wB78jOCTHp yhZEXN4FIGjW3BCwWrh3P5vYNUDbEdRNAmN4AWREADlTNJs15Zx3AnUjW/r63TTM8Sp5 ulSVtLNWTeymDgwAr5zzVl7x4FKM7e7N0bG7fpPjOhEKxQpf2OCVRvbDzxWj6mGheHSf ffDED0IAgKQuLX1DXwv1t+GJtRd1OePGZMtjSxkUONgJqVSMyWGQd6lDrqiv7s4dy4H0 sDF1fUK3GlrtlyILzS6AzYKGGh0xOpKpkyXOeDyvT/Y4KNxgRuF6y8MCI4QYdj5//HGd 0JZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ypar0ej4TvEEf95rRUUSazBC6MGwvwdLxXN4saosWNU=; b=Q7f0akWiw73CrGTuERUWaVEoQ6XCunMWOEnzWCL59n7/5qKTPfqef/dtSu0pwd75iy ea0YwnBunADvmpdp7Y76Tkeaevfzq5nUDDPOZxuFuwqVN2HmQNG6CA4WWHsVUok2RraJ zqA2aUu77M8TdhjNlnPq6lOCyt+KBR7yNnDgWJHo4JLZVTD1E0ndE+4xADdb8zgzGw0w xDhLXmSRMui6XtGMCPCdVJh67f9o32e2S9EVKefJftGfEuh3PC97Mlv2K0/0mWz0E4hp FR2HaNBJFUZ1f5tDjB4ck2Gihah9nrhqsmVd7kfZlMpcBHBRJA29Ml2gWzK5ADghKlrw Vbag== X-Gm-Message-State: AOAM530NrgLRuEme7SSIRKlwZyQcOmLskaCuNfMB1NJABDk42X6DniGZ 4L9vbGZaFbv59xO6ASC+w0IQugnY2aUIDUe+ X-Google-Smtp-Source: ABdhPJylzTeEaP8XlrgRz40Jlnt3brYtmaQaR5pcrVjnlB6Qd1g2JhZ4/RkY6gU8FYFkbhooRZeiIA== X-Received: by 2002:a17:902:be12:: with SMTP id r18mr2544536pls.116.1597423312997; Fri, 14 Aug 2020 09:41:52 -0700 (PDT) Received: from pek-vx-bsp2.wrs.com (unknown-146-144.windriver.com. [147.11.146.144]) by smtp.gmail.com with ESMTPSA id 16sm9836332pfi.161.2020.08.14.09.41.50 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Aug 2020 09:41:52 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 13/18] hw/riscv: microchip_pfsoc: Connect a DMA controller Date: Sat, 15 Aug 2020 00:40:51 +0800 Message-Id: <1597423256-14847-14-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> References: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Connect a DMA controller to Microchip PolarFire SoC. Note interrupt has not been connected due to missing information in the manual how interrupts are routed to PLIC. On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA controller to move the 2nd stage bootloader in the system memory. Signed-off-by: Bin Meng --- hw/riscv/Kconfig | 1 + hw/riscv/microchip_pfsoc.c | 10 ++++++++++ include/hw/riscv/microchip_pfsoc.h | 3 +++ 3 files changed, 14 insertions(+) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 7412db9..9323701 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -55,4 +55,5 @@ config MICROCHIP_PFSOC select SIFIVE select UNIMP select MCHP_PFSOC_MMUART + select MCHP_PFSOC_DMA select CADENCE_SDHCI diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 7c09078..1c67cbc 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -13,6 +13,7 @@ * 2) eNVM (Embedded Non-Volatile Memory) * 3) MMUARTs (Multi-Mode UART) * 4) Cadence eMMC/SDHC controller and an SD card connected to it + * 5) DMA (Direct Memory Access Controller) * * This board currently generates devicetree dynamically that indicates at least * two harts and up to five harts. @@ -71,6 +72,7 @@ static const struct MemmapEntry { [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 }, [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 }, [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 }, + [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 }, [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 }, [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 }, [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, @@ -114,6 +116,9 @@ static void microchip_pfsoc_soc_instance_init(Object *obj) TYPE_RISCV_CPU_SIFIVE_U54); qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR); + object_initialize_child(obj, "dma-controller", &s->dma, + TYPE_MCHP_PFSOC_DMA); + object_initialize_child(obj, "sd-controller", &s->sdhci, TYPE_CADENCE_SDHCI); object_initialize_child(OBJECT(&s->sdhci), "sd-controller.sdhci", @@ -220,6 +225,11 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) memmap[MICROCHIP_PFSOC_PLIC].size); g_free(plic_hart_config); + /* DMA */ + sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, + memmap[MICROCHIP_PFSOC_DMA].base); + /* SYSREG */ create_unimplemented_device("microchip.pfsoc.sysreg", memmap[MICROCHIP_PFSOC_SYSREG].base, diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index d810ee8..7825935 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -23,6 +23,7 @@ #define HW_MICROCHIP_PFSOC_H #include "hw/char/mchp_pfsoc_mmuart.h" +#include "hw/dma/mchp_pfsoc_dma.h" #include "hw/sd/cadence_sdhci.h" typedef struct MicrochipPFSoCState { @@ -40,6 +41,7 @@ typedef struct MicrochipPFSoCState { MchpPfSoCMMUartState *serial2; MchpPfSoCMMUartState *serial3; MchpPfSoCMMUartState *serial4; + MchpPfSoCDMAState dma; CadenceSDHCIState sdhci; } MicrochipPFSoCState; @@ -71,6 +73,7 @@ enum { MICROCHIP_PFSOC_BUSERR_UNIT4, MICROCHIP_PFSOC_CLINT, MICROCHIP_PFSOC_L2CC, + MICROCHIP_PFSOC_DMA, MICROCHIP_PFSOC_L2LIM, MICROCHIP_PFSOC_PLIC, MICROCHIP_PFSOC_MMUART0, From patchwork Fri Aug 14 16:40:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1345118 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id 16sm9836332pfi.161.2020.08.14.09.41.53 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Aug 2020 09:41:56 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 14/18] hw/net: cadence_gem: Add a new 'phy-addr' property Date: Sat, 15 Aug 2020 00:40:52 +0800 Message-Id: <1597423256-14847-15-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> References: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::543; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x543.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis , Jason Wang , Bin Meng , qemu-arm@nongnu.org, "Edgar E. Iglesias" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng At present the PHY address of the PHY connected to GEM is hard-coded to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for all boards. Add a new 'phy-addr' property so that board can specify the PHY address for each GEM instance. Signed-off-by: Bin Meng --- hw/net/cadence_gem.c | 7 +++++-- include/hw/net/cadence_gem.h | 2 ++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index a93b5c0..9fa03de 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -1446,7 +1446,8 @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) uint32_t phy_addr, reg_num; phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; - if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { + if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0 || + phy_addr == s->phy_addr) { reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; retval &= 0xFFFF0000; retval |= gem_phy_read(s, reg_num); @@ -1569,7 +1570,8 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val, uint32_t phy_addr, reg_num; phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; - if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { + if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0 || + phy_addr == s->phy_addr) { reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; gem_phy_write(s, reg_num, val); } @@ -1682,6 +1684,7 @@ static Property gem_properties[] = { DEFINE_NIC_PROPERTIES(CadenceGEMState, conf), DEFINE_PROP_UINT32("revision", CadenceGEMState, revision, GEM_MODID_VALUE), + DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, 0), DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState, num_priority_queues, 1), DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState, diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h index 54e646f..01c6189 100644 --- a/include/hw/net/cadence_gem.h +++ b/include/hw/net/cadence_gem.h @@ -73,6 +73,8 @@ typedef struct CadenceGEMState { /* Mask of register bits which are write 1 to clear */ uint32_t regs_w1c[CADENCE_GEM_MAXREG]; + /* PHY address */ + uint8_t phy_addr; /* PHY registers backing store */ uint16_t phy_regs[32]; From patchwork Fri Aug 14 16:40:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1345121 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id 16sm9836332pfi.161.2020.08.14.09.41.57 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Aug 2020 09:42:00 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 15/18] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs Date: Sat, 15 Aug 2020 00:40:53 +0800 Message-Id: <1597423256-14847-16-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> References: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Microchip PolarFire SoC integrates 2 Candence GEMs to provide IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface. On the Icicle Kit board, GEM0 connects to a PHY at address 8 while GEM1 connects to a PHY at address 9. The 2nd stage bootloader (U-Boot) is using GEM1 by default, so we must specify 2 '-nic' options from the command line in order to get a working ethernet. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/microchip_pfsoc.c | 39 ++++++++++++++++++++++++++++++++++++++ include/hw/riscv/microchip_pfsoc.h | 7 +++++++ 2 files changed, 46 insertions(+) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 1c67cbc..625b511 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -14,6 +14,7 @@ * 3) MMUARTs (Multi-Mode UART) * 4) Cadence eMMC/SDHC controller and an SD card connected to it * 5) DMA (Direct Memory Access Controller) + * 6) GEM (Gigabit Ethernet MAC Controller) * * This board currently generates devicetree dynamically that indicates at least * two harts and up to five harts. @@ -59,6 +60,9 @@ #define BIOS_FILENAME "hss.bin" #define RESET_VECTOR 0x20220000 +/* GEM version */ +#define GEM_REVISION 0x0107010c + static const struct MemmapEntry { hwaddr base; hwaddr size; @@ -83,6 +87,8 @@ static const struct MemmapEntry { [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 }, + [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 }, + [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 }, [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 }, @@ -119,6 +125,9 @@ static void microchip_pfsoc_soc_instance_init(Object *obj) object_initialize_child(obj, "dma-controller", &s->dma, TYPE_MCHP_PFSOC_DMA); + object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM); + object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM); + object_initialize_child(obj, "sd-controller", &s->sdhci, TYPE_CADENCE_SDHCI); object_initialize_child(OBJECT(&s->sdhci), "sd-controller.sdhci", @@ -136,6 +145,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) MemoryRegion *envm_data = g_new(MemoryRegion, 1); char *plic_hart_config; size_t plic_hart_config_len; + NICInfo *nd; int i; sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); @@ -269,6 +279,35 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ), serial_hd(4)); + /* GEMs */ + + nd = &nd_table[0]; + if (nd->used) { + qemu_check_nic_model(nd, TYPE_CADENCE_GEM); + qdev_set_nic_properties(DEVICE(&s->gem0), nd); + } + nd = &nd_table[1]; + if (nd->used) { + qemu_check_nic_model(nd, TYPE_CADENCE_GEM); + qdev_set_nic_properties(DEVICE(&s->gem1), nd); + } + + object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp); + object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp); + sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0, + memmap[MICROCHIP_PFSOC_GEM0].base); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0, + qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ)); + + object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp); + object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp); + sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0, + memmap[MICROCHIP_PFSOC_GEM1].base); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0, + qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ)); + /* eNVM */ memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data", memmap[MICROCHIP_PFSOC_ENVM_DATA].size, diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index 7825935..60f994c 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -24,6 +24,7 @@ #include "hw/char/mchp_pfsoc_mmuart.h" #include "hw/dma/mchp_pfsoc_dma.h" +#include "hw/net/cadence_gem.h" #include "hw/sd/cadence_sdhci.h" typedef struct MicrochipPFSoCState { @@ -42,6 +43,8 @@ typedef struct MicrochipPFSoCState { MchpPfSoCMMUartState *serial3; MchpPfSoCMMUartState *serial4; MchpPfSoCDMAState dma; + CadenceGEMState gem0; + CadenceGEMState gem1; CadenceSDHCIState sdhci; } MicrochipPFSoCState; @@ -84,6 +87,8 @@ enum { MICROCHIP_PFSOC_MMUART2, MICROCHIP_PFSOC_MMUART3, MICROCHIP_PFSOC_MMUART4, + MICROCHIP_PFSOC_GEM0, + MICROCHIP_PFSOC_GEM1, MICROCHIP_PFSOC_ENVM_CFG, MICROCHIP_PFSOC_ENVM_DATA, MICROCHIP_PFSOC_IOSCB_CFG, @@ -91,6 +96,8 @@ enum { }; enum { + MICROCHIP_PFSOC_GEM0_IRQ = 64, + MICROCHIP_PFSOC_GEM1_IRQ = 70, MICROCHIP_PFSOC_EMMC_SD_IRQ = 88, MICROCHIP_PFSOC_MMUART0_IRQ = 90, MICROCHIP_PFSOC_MMUART1_IRQ = 91, From patchwork Fri Aug 14 16:40:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1345151 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id 16sm9836332pfi.161.2020.08.14.09.42.01 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Aug 2020 09:42:03 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 16/18] hw/riscv: microchip_pfsoc: Hook GPIO controllers Date: Sat, 15 Aug 2020 00:40:54 +0800 Message-Id: <1597423256-14847-17-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> References: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::544; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x544.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems enough to create unimplemented devices to cover their register spaces at this point. With this commit, QEMU can boot to U-Boot (2nd stage bootloader) all the way to the Linux shell login prompt, with a modified HSS (1st stage bootloader). Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/microchip_pfsoc.c | 14 ++++++++++++++ include/hw/riscv/microchip_pfsoc.h | 3 +++ 2 files changed, 17 insertions(+) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 625b511..139284a 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -89,6 +89,9 @@ static const struct MemmapEntry { [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 }, [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 }, [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 }, + [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 }, + [MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 }, + [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 }, @@ -308,6 +311,17 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0, qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ)); + /* GPIOs */ + create_unimplemented_device("microchip.pfsoc.gpio0", + memmap[MICROCHIP_PFSOC_GPIO0].base, + memmap[MICROCHIP_PFSOC_GPIO0].size); + create_unimplemented_device("microchip.pfsoc.gpio1", + memmap[MICROCHIP_PFSOC_GPIO1].base, + memmap[MICROCHIP_PFSOC_GPIO1].size); + create_unimplemented_device("microchip.pfsoc.gpio2", + memmap[MICROCHIP_PFSOC_GPIO2].base, + memmap[MICROCHIP_PFSOC_GPIO2].size); + /* eNVM */ memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data", memmap[MICROCHIP_PFSOC_ENVM_DATA].size, diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index 60f994c..993b17c 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -89,6 +89,9 @@ enum { MICROCHIP_PFSOC_MMUART4, MICROCHIP_PFSOC_GEM0, MICROCHIP_PFSOC_GEM1, + MICROCHIP_PFSOC_GPIO0, + MICROCHIP_PFSOC_GPIO1, + MICROCHIP_PFSOC_GPIO2, MICROCHIP_PFSOC_ENVM_CFG, MICROCHIP_PFSOC_ENVM_DATA, MICROCHIP_PFSOC_IOSCB_CFG, From patchwork Fri Aug 14 16:40:55 2020 Content-Type: text/plain; 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id 16sm9836332pfi.161.2020.08.14.09.42.04 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Aug 2020 09:42:06 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 17/18] hw/riscv: clint: Avoid using hard-coded timebase frequency Date: Sat, 15 Aug 2020 00:40:55 +0800 Message-Id: <1597423256-14847-18-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> References: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng At present the CLINT timestamp is using a hard-coded timebase frequency value SIFIVE_CLINT_TIMEBASE_FREQ. This might not be true for all boards. Add a new 'timebase-freq' property to the CLINT device, and update various functions to accept this as a parameter. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/microchip_pfsoc.c | 6 +++++- hw/riscv/sifive_clint.c | 25 ++++++++++++++----------- hw/riscv/sifive_e.c | 3 ++- hw/riscv/sifive_u.c | 3 ++- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 3 ++- include/hw/riscv/sifive_clint.h | 3 ++- target/riscv/cpu.h | 6 ++++-- target/riscv/cpu_helper.c | 4 +++- target/riscv/csr.c | 4 ++-- 10 files changed, 37 insertions(+), 22 deletions(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 139284a..e8b7f86 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -60,6 +60,9 @@ #define BIOS_FILENAME "hss.bin" #define RESET_VECTOR 0x20220000 +/* CLINT timebase frequency */ +#define CLINT_TIMEBASE_FREQ 1000000 + /* GEM version */ #define GEM_REVISION 0x0107010c @@ -189,7 +192,8 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) /* CLINT */ sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base, memmap[MICROCHIP_PFSOC_CLINT].size, ms->smp.cpus, - SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, + CLINT_TIMEBASE_FREQ, false); /* L2 cache controller */ create_unimplemented_device("microchip.pfsoc.l2cc", diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c index 669c21a..a568568 100644 --- a/hw/riscv/sifive_clint.c +++ b/hw/riscv/sifive_clint.c @@ -29,22 +29,23 @@ #include "hw/riscv/sifive_clint.h" #include "qemu/timer.h" -static uint64_t cpu_riscv_read_rtc(void) +static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) { return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - SIFIVE_CLINT_TIMEBASE_FREQ, NANOSECONDS_PER_SECOND); + timebase_freq, NANOSECONDS_PER_SECOND); } /* * Called when timecmp is written to update the QEMU timer or immediately * trigger timer interrupt if mtimecmp <= current timer value. */ -static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value) +static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value, + uint32_t timebase_freq) { uint64_t next; uint64_t diff; - uint64_t rtc_r = cpu_riscv_read_rtc(); + uint64_t rtc_r = cpu_riscv_read_rtc(timebase_freq); cpu->env.timecmp = value; if (cpu->env.timecmp <= rtc_r) { @@ -59,7 +60,7 @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value) diff = cpu->env.timecmp - rtc_r; /* back to ns (note args switched in muldiv64) */ next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + - muldiv64(diff, NANOSECONDS_PER_SECOND, SIFIVE_CLINT_TIMEBASE_FREQ); + muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq); timer_mod(cpu->env.timer, next); } @@ -111,10 +112,10 @@ static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size) } } else if (addr == clint->time_base) { /* time_lo */ - return cpu_riscv_read_rtc() & 0xFFFFFFFF; + return cpu_riscv_read_rtc(clint->timebase_freq) & 0xFFFFFFFF; } else if (addr == clint->time_base + 4) { /* time_hi */ - return (cpu_riscv_read_rtc() >> 32) & 0xFFFFFFFF; + return (cpu_riscv_read_rtc(clint->timebase_freq) >> 32) & 0xFFFFFFFF; } error_report("clint: invalid read: %08x", (uint32_t)addr); @@ -151,13 +152,13 @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value, /* timecmp_lo */ uint64_t timecmp_hi = env->timecmp >> 32; sifive_clint_write_timecmp(RISCV_CPU(cpu), - timecmp_hi << 32 | (value & 0xFFFFFFFF)); + timecmp_hi << 32 | (value & 0xFFFFFFFF), clint->timebase_freq); return; } else if ((addr & 0x7) == 4) { /* timecmp_hi */ uint64_t timecmp_lo = env->timecmp; sifive_clint_write_timecmp(RISCV_CPU(cpu), - value << 32 | (timecmp_lo & 0xFFFFFFFF)); + value << 32 | (timecmp_lo & 0xFFFFFFFF), clint->timebase_freq); } else { error_report("clint: invalid timecmp write: %08x", (uint32_t)addr); } @@ -191,6 +192,7 @@ static Property sifive_clint_properties[] = { DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0), DEFINE_PROP_UINT32("time-base", SiFiveCLINTState, time_base, 0), DEFINE_PROP_UINT32("aperture-size", SiFiveCLINTState, aperture_size, 0), + DEFINE_PROP_UINT32("timebase-freq", SiFiveCLINTState, timebase_freq, 0), DEFINE_PROP_END_OF_LIST(), }; @@ -229,7 +231,7 @@ type_init(sifive_clint_register_types) */ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts, uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base, - bool provide_rdtime) + uint32_t timebase_freq, bool provide_rdtime) { int i; for (i = 0; i < num_harts; i++) { @@ -239,7 +241,7 @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts, continue; } if (provide_rdtime) { - riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc); + riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, timebase_freq); } env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &sifive_clint_timer_cb, cpu); @@ -252,6 +254,7 @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts, qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base); qdev_prop_set_uint32(dev, "time-base", time_base); qdev_prop_set_uint32(dev, "aperture-size", size); + qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); return dev; diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index c84d407..e7f6460 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -213,7 +213,8 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp) memmap[SIFIVE_E_PLIC].size); sifive_clint_create(memmap[SIFIVE_E_CLINT].base, memmap[SIFIVE_E_CLINT].size, ms->smp.cpus, - SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, + SIFIVE_CLINT_TIMEBASE_FREQ, false); create_unimplemented_device("riscv.sifive.e.aon", memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index e256da2..5ec9fca 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -706,7 +706,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); sifive_clint_create(memmap[SIFIVE_U_CLINT].base, memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, - SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, + SIFIVE_CLINT_TIMEBASE_FREQ, false); if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { return; diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 13958bd..ae8593a 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -235,7 +235,7 @@ static void spike_board_init(MachineState *machine) /* Core Local Interruptor (timer and IPI) */ sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, - false); + SIFIVE_CLINT_TIMEBASE_FREQ, false); } static void spike_machine_init(MachineClass *mc) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 6e91cf1..af0d06a 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -572,7 +572,8 @@ static void virt_machine_init(MachineState *machine) memmap[VIRT_PLIC].size); sifive_clint_create(memmap[VIRT_CLINT].base, memmap[VIRT_CLINT].size, smp_cpus, - SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true); + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, + SIFIVE_CLINT_TIMEBASE_FREQ, true); sifive_test_create(memmap[VIRT_TEST].base); for (i = 0; i < VIRTIO_COUNT; i++) { diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/riscv/sifive_clint.h index 4a720bf..eb8577a 100644 --- a/include/hw/riscv/sifive_clint.h +++ b/include/hw/riscv/sifive_clint.h @@ -38,11 +38,12 @@ typedef struct SiFiveCLINTState { uint32_t timecmp_base; uint32_t time_base; uint32_t aperture_size; + uint32_t timebase_freq; } SiFiveCLINTState; DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts, uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base, - bool provide_rdtime); + uint32_t timebase_freq, bool provide_rdtime); enum { SIFIVE_SIP_BASE = 0x0, diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d34bcfa..02486c3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -219,7 +219,8 @@ struct CPURISCVState { pmp_table_t pmp_state; /* machine specific rdtime callback */ - uint64_t (*rdtime_fn)(void); + uint64_t (*rdtime_fn)(uint32_t); + uint32_t rdtime_fn_arg; /* True if in debugger mode. */ bool debugger; @@ -347,7 +348,8 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void)); +void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), + uint32_t arg); #endif void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index fd1d373..c82a521 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -258,9 +258,11 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) return old; } -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void)) +void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), + uint32_t arg) { env->rdtime_fn = fn; + env->rdtime_fn_arg = arg; } void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6a96a01..6cef1ac 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -294,7 +294,7 @@ static int read_time(CPURISCVState *env, int csrno, target_ulong *val) return -1; } - *val = env->rdtime_fn() + delta; + *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; return 0; } @@ -307,7 +307,7 @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val) return -1; } - *val = (env->rdtime_fn() + delta) >> 32; + *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; return 0; } #endif From patchwork Fri Aug 14 16:40:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1345117 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id 16sm9836332pfi.161.2020.08.14.09.42.07 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Aug 2020 09:42:10 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 18/18] hw/riscv: microchip_pfsoc: Document the software used for testing Date: Sat, 15 Aug 2020 00:40:56 +0800 Message-Id: <1597423256-14847-19-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> References: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x642.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Add some useful comments to document the software used for testing. including how to patch HSS to bypass the DDR memory initialization, HSS and Yocto BSP build instructions, etc. To launch this machine for testing: $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \ -bios path/to/hss.bin -sd path/to/sdcard.img \ -nic user,model=cadence_gem \ -nic tap,ifname=tap,model=cadence_gem \ -display none -serial stdio \ -chardev socket,id=serial1,path=serial1.sock,server,wait \ -serial chardev:serial1 Signed-off-by: Bin Meng --- hw/riscv/microchip_pfsoc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index e8b7f86..1575fef 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -56,6 +56,27 @@ /* * The BIOS image used by this machine is called Hart Software Services (HSS). * See https://github.com/polarfire-soc/hart-software-services + * + * As of now the DDR memory controller in the Microchip PolarFire SoC has not + * been modeled. Simply creating unimplemented devices does not make HSS happy. + * Emulating the DDR memory controller is tedious, so a patched HSS should be + * used as the BIOS for this machine. + * + * To patch HSS, open boards/icicle-kit-es/hss_board_init.c in the HSS source + * tree, find the boardInitFunctions[] array that contains the initialization + * routines for this board, and remove the line that contains 'HSS_DDRInit'. + * + * QEMU does not support eMMC hence the SD configuration shall be used in the + * HSS and Yocto BSP build. The eMMC configuration is not supported. + * + * Instructions to build HSS: + * $ cp boards/icicle-kit-es/def_config.sdcard .config + * $ make BOARD=icicle-kit-es + * + * For Yocto build, "MACHINE=icicle-kit-es-sd" should be specified, otherwise + * when booting Linux kernel the rootfs cannot be mounted. The generated image + * is something like: mpfs-dev-cli-icicle-kit-es-sd.rootfs.wic. Resize the file + * with 'qemu-image' to a power of 2 before passing to QEMU '-sd' command line. */ #define BIOS_FILENAME "hss.bin" #define RESET_VECTOR 0x20220000