From patchwork Fri Aug 14 06:57:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344655 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ5K0WHZz9sTM; Fri, 14 Aug 2020 16:57:55 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1k6Tex-0007Uw-7I; Fri, 14 Aug 2020 06:57:51 +0000 Received: from mail-pg1-f195.google.com ([209.85.215.195]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1k6Tev-0007UT-7I for kernel-team@lists.ubuntu.com; Fri, 14 Aug 2020 06:57:49 +0000 Received: by mail-pg1-f195.google.com with SMTP id o13so4100202pgf.0 for ; Thu, 13 Aug 2020 23:57:48 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A9G+znhK6Fc6Gg9C2cFnVcfdyMh+t0a0VDDagJphVqY=; b=k4jo9ARhu2Z1R36OdaF1OEA9C1+KwhkKAqxoRRkeBtDz2/zmm11Bk71WVf9UJtMvFV GGchYsr/24elRm0Vla8C0sd3G4M9tvJ4PGzvzul4DHiMdu0C+F2XgyD6Y12jV2OuVB4h W3p3INj64WHvJqVz9erCJbKdB7f8WipdmOm+VRPT68vDs+ZYHt9UFsmGwLfUpLBJhBmN VWsYSs9bAtaMjq8w11V6xOBjsPKtEHjr6tW44XkbYBn6WyzzoU4BzylwsF5IAYt0bOt0 /i9ykAarSpMKQQKHh0Q+N2eui8VGjPTzqM6zCJq3S1JG0iACdSSiQW7V4VI6TiMhBSm0 oknw== X-Gm-Message-State: AOAM533NSEQRWOJuPflHcCNZYDbPEQ+GdWD5TDFcfvuk1JB9HNpJiQ/o OIEbI9OBDi+ziBaLUatqDhKBIqcy1m4h8Q== X-Google-Smtp-Source: ABdhPJwcdwD4pLEYz5YdleKkU3m+W600YE9Pvwm6r2jJH278OyfBz0w5ZW4ebwDFj2aA8HFrvI1kwg== X-Received: by 2002:a62:20e:: with SMTP id 14mr3655pfc.207.1597388266775; Thu, 13 Aug 2020 23:57:46 -0700 (PDT) Received: from localhost (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id il13sm7498744pjb.0.2020.08.13.23.57.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:57:45 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 01/31][SRU][OEM-5.6] drm/i915: Move more cdclk state handling into the cdclk code Date: Fri, 14 Aug 2020 14:57:10 +0800 Message-Id: <20200814065740.276039-2-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.215.195; envelope-from=vicamo@gmail.com; helo=mail-pg1-f195.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Ville Syrjälä BugLink: https://bugs.launchpad.net/bugs/1891451 Move the initial setup of state->{cdclk,min_cdclk[],min_voltage_level[]} into intel_modeset_calc_cdclk(), and we'll move the counterparts into intel_cdclk_swap_state(). This encapsulates the cdclk state much better. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200120174728.21095-5-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza (cherry picked from commit 54f09d2342b0516ce73ec02657db8d28fcfa637e) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/display/intel_cdclk.c | 26 +++++++++++++++----- drivers/gpu/drm/i915/display/intel_display.c | 11 --------- 2 files changed, 20 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index fd24f10060b6..b2c8a027b442 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1831,6 +1831,14 @@ void intel_cdclk_swap_state(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); + /* FIXME maybe swap() these too */ + memcpy(dev_priv->min_cdclk, state->min_cdclk, + sizeof(state->min_cdclk)); + memcpy(dev_priv->min_voltage_level, state->min_voltage_level, + sizeof(state->min_voltage_level)); + + dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk; + swap(state->cdclk.logical, dev_priv->cdclk.logical); swap(state->cdclk.actual, dev_priv->cdclk.actual); } @@ -2045,9 +2053,6 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state) int min_cdclk, i; enum pipe pipe; - memcpy(state->min_cdclk, dev_priv->min_cdclk, - sizeof(state->min_cdclk)); - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { int ret; @@ -2094,9 +2099,6 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) int i; enum pipe pipe; - memcpy(state->min_voltage_level, dev_priv->min_voltage_level, - sizeof(state->min_voltage_level)); - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { int ret; @@ -2351,6 +2353,18 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) enum pipe pipe; int ret; + memcpy(state->min_cdclk, dev_priv->min_cdclk, + sizeof(state->min_cdclk)); + memcpy(state->min_voltage_level, dev_priv->min_voltage_level, + sizeof(state->min_voltage_level)); + + /* keep the current setting */ + if (!state->cdclk.force_min_cdclk_changed) + state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk; + + state->cdclk.logical = dev_priv->cdclk.logical; + state->cdclk.actual = dev_priv->cdclk.actual; + ret = dev_priv->display.modeset_calc_cdclk(state); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index eb6942604801..11f93d11079f 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -14376,14 +14376,8 @@ static int intel_modeset_checks(struct intel_atomic_state *state) struct intel_crtc *crtc; int ret, i; - /* keep the current setting */ - if (!state->cdclk.force_min_cdclk_changed) - state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk; - state->modeset = true; state->active_pipes = dev_priv->active_pipes; - state->cdclk.logical = dev_priv->cdclk.logical; - state->cdclk.actual = dev_priv->cdclk.actual; for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { @@ -15717,12 +15711,7 @@ static int intel_atomic_commit(struct drm_device *dev, if (state->global_state_changed) { assert_global_state_locked(dev_priv); - memcpy(dev_priv->min_cdclk, state->min_cdclk, - sizeof(state->min_cdclk)); - memcpy(dev_priv->min_voltage_level, state->min_voltage_level, - sizeof(state->min_voltage_level)); dev_priv->active_pipes = state->active_pipes; - dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk; intel_cdclk_swap_state(state); } From patchwork Fri Aug 14 06:57:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344657 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; 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[61.220.137.37]) by smtp.gmail.com with ESMTPSA id p1sm7215155pjp.10.2020.08.13.23.57.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:57:48 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 02/31][SRU][OEM-5.6] drm/i915: Collect more cdclk state under the same roof Date: Fri, 14 Aug 2020 14:57:11 +0800 Message-Id: <20200814065740.276039-3-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.216.67; envelope-from=vicamo@gmail.com; helo=mail-pj1-f67.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Ville Syrjälä BugLink: https://bugs.launchpad.net/bugs/1891451 Move the min_cdclk[] and min_voltage_level[] arrays under the rest of the cdclk state. And while at it provide a simple helper (intel_cdclk_clear_state()) to clear the state during the ww_mutex backoff dance. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200120174728.21095-6-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza (cherry picked from commit b4db3a8c689ba5f5ced764ab1377ad6411003b0b) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/display/intel_atomic.c | 9 ++--- drivers/gpu/drm/i915/display/intel_cdclk.c | 40 ++++++++++++------- drivers/gpu/drm/i915/display/intel_cdclk.h | 1 + drivers/gpu/drm/i915/display/intel_display.c | 8 ++-- .../drm/i915/display/intel_display_types.h | 10 +++-- drivers/gpu/drm/i915/i915_drv.h | 9 +++-- 6 files changed, 46 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c index c362eecdd414..1269f63ea006 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.c +++ b/drivers/gpu/drm/i915/display/intel_atomic.c @@ -35,6 +35,7 @@ #include #include "intel_atomic.h" +#include "intel_cdclk.h" #include "intel_display_types.h" #include "intel_hdcp.h" #include "intel_psr.h" @@ -497,15 +498,13 @@ intel_atomic_state_alloc(struct drm_device *dev) void intel_atomic_state_clear(struct drm_atomic_state *s) { struct intel_atomic_state *state = to_intel_atomic_state(s); + drm_atomic_state_default_clear(&state->base); + state->dpll_set = state->modeset = false; state->global_state_changed = false; state->active_pipes = 0; - memset(&state->min_cdclk, 0, sizeof(state->min_cdclk)); - memset(&state->min_voltage_level, 0, sizeof(state->min_voltage_level)); - memset(&state->cdclk.logical, 0, sizeof(state->cdclk.logical)); - memset(&state->cdclk.actual, 0, sizeof(state->cdclk.actual)); - state->cdclk.pipe = INVALID_PIPE; + intel_cdclk_clear_state(state); } struct intel_crtc_state * diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index b2c8a027b442..ca0510e74516 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1815,6 +1815,18 @@ static bool intel_cdclk_changed(const struct intel_cdclk_state *a, a->voltage_level != b->voltage_level; } +/** + * intel_cdclk_clear_state - clear the cdclk state + * @state: atomic state + * + * Clear the cdclk state for ww_mutex backoff. + */ +void intel_cdclk_clear_state(struct intel_atomic_state *state) +{ + memset(&state->cdclk, 0, sizeof(state->cdclk)); + state->cdclk.pipe = INVALID_PIPE; +} + /** * intel_cdclk_swap_state - make atomic CDCLK configuration effective * @state: atomic state @@ -1832,10 +1844,10 @@ void intel_cdclk_swap_state(struct intel_atomic_state *state) struct drm_i915_private *dev_priv = to_i915(state->base.dev); /* FIXME maybe swap() these too */ - memcpy(dev_priv->min_cdclk, state->min_cdclk, - sizeof(state->min_cdclk)); - memcpy(dev_priv->min_voltage_level, state->min_voltage_level, - sizeof(state->min_voltage_level)); + memcpy(dev_priv->cdclk.min_cdclk, state->cdclk.min_cdclk, + sizeof(state->cdclk.min_cdclk)); + memcpy(dev_priv->cdclk.min_voltage_level, state->cdclk.min_voltage_level, + sizeof(state->cdclk.min_voltage_level)); dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk; @@ -2060,10 +2072,10 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state) if (min_cdclk < 0) return min_cdclk; - if (state->min_cdclk[i] == min_cdclk) + if (state->cdclk.min_cdclk[i] == min_cdclk) continue; - state->min_cdclk[i] = min_cdclk; + state->cdclk.min_cdclk[i] = min_cdclk; ret = intel_atomic_lock_global_state(state); if (ret) @@ -2072,7 +2084,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state) min_cdclk = state->cdclk.force_min_cdclk; for_each_pipe(dev_priv, pipe) - min_cdclk = max(state->min_cdclk[pipe], min_cdclk); + min_cdclk = max(state->cdclk.min_cdclk[pipe], min_cdclk); return min_cdclk; } @@ -2107,10 +2119,10 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) else min_voltage_level = 0; - if (state->min_voltage_level[i] == min_voltage_level) + if (state->cdclk.min_voltage_level[i] == min_voltage_level) continue; - state->min_voltage_level[i] = min_voltage_level; + state->cdclk.min_voltage_level[i] = min_voltage_level; ret = intel_atomic_lock_global_state(state); if (ret) @@ -2119,7 +2131,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) min_voltage_level = 0; for_each_pipe(dev_priv, pipe) - min_voltage_level = max(state->min_voltage_level[pipe], + min_voltage_level = max(state->cdclk.min_voltage_level[pipe], min_voltage_level); return min_voltage_level; @@ -2353,10 +2365,10 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) enum pipe pipe; int ret; - memcpy(state->min_cdclk, dev_priv->min_cdclk, - sizeof(state->min_cdclk)); - memcpy(state->min_voltage_level, dev_priv->min_voltage_level, - sizeof(state->min_voltage_level)); + memcpy(state->cdclk.min_cdclk, dev_priv->cdclk.min_cdclk, + sizeof(state->cdclk.min_cdclk)); + memcpy(state->cdclk.min_voltage_level, dev_priv->cdclk.min_voltage_level, + sizeof(state->cdclk.min_voltage_level)); /* keep the current setting */ if (!state->cdclk.force_min_cdclk_changed) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index cf71394cc79c..3f3773c582ae 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -31,6 +31,7 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv); void intel_update_rawclk(struct drm_i915_private *dev_priv); bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a, const struct intel_cdclk_state *b); +void intel_cdclk_clear_state(struct intel_atomic_state *state); void intel_cdclk_swap_state(struct intel_atomic_state *state); void intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 11f93d11079f..f405f9c1512d 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7565,8 +7565,8 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, crtc->enabled_power_domains = 0; dev_priv->active_pipes &= ~BIT(pipe); - dev_priv->min_cdclk[pipe] = 0; - dev_priv->min_voltage_level[pipe] = 0; + dev_priv->cdclk.min_cdclk[pipe] = 0; + dev_priv->cdclk.min_voltage_level[pipe] = 0; bw_state->data_rate[pipe] = 0; bw_state->num_active_planes[pipe] = 0; @@ -18313,8 +18313,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) min_cdclk = 0; } - dev_priv->min_cdclk[crtc->pipe] = min_cdclk; - dev_priv->min_voltage_level[crtc->pipe] = + dev_priv->cdclk.min_cdclk[crtc->pipe] = min_cdclk; + dev_priv->cdclk.min_voltage_level[crtc->pipe] = crtc_state->min_voltage_level; intel_bw_crtc_update(bw_state, crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 7000adce712d..d7a5f2e5fd14 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -479,6 +479,12 @@ struct intel_atomic_state { int force_min_cdclk; bool force_min_cdclk_changed; + + /* minimum acceptable cdclk for each pipe */ + int min_cdclk[I915_MAX_PIPES]; + /* minimum acceptable voltage level for each pipe */ + u8 min_voltage_level[I915_MAX_PIPES]; + /* pipe to which cd2x update is synchronized */ enum pipe pipe; } cdclk; @@ -496,10 +502,6 @@ struct intel_atomic_state { u8 active_pipe_changes; u8 active_pipes; - /* minimum acceptable cdclk for each pipe */ - int min_cdclk[I915_MAX_PIPES]; - /* minimum acceptable voltage level for each pipe */ - u8 min_voltage_level[I915_MAX_PIPES]; struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 55252e1b26f1..ef75a913f05b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1019,6 +1019,11 @@ struct drm_i915_private { const struct intel_cdclk_vals *table; int force_min_cdclk; + + /* minimum acceptable cdclk for each pipe */ + int min_cdclk[I915_MAX_PIPES]; + /* minimum acceptable voltage level for each pipe */ + u8 min_voltage_level[I915_MAX_PIPES]; } cdclk; /** @@ -1079,10 +1084,6 @@ struct drm_i915_private { * any crtc lock is sufficient, for writing must hold all of them. */ u8 active_pipes; - /* minimum acceptable cdclk for each pipe */ - int min_cdclk[I915_MAX_PIPES]; - /* minimum acceptable voltage level for each pipe */ - u8 min_voltage_level[I915_MAX_PIPES]; int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; From patchwork Fri Aug 14 06:57:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344658 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[61.220.137.37]) by smtp.gmail.com with ESMTPSA id y135sm8406938pfg.148.2020.08.13.23.57.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:57:51 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 03/31][SRU][OEM-5.6] drm/i915: s/need_cd2x_updare/can_cd2x_update/ Date: Fri, 14 Aug 2020 14:57:12 +0800 Message-Id: <20200814065740.276039-4-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.216.65; envelope-from=vicamo@gmail.com; helo=mail-pj1-f65.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Ville Syrjälä BugLink: https://bugs.launchpad.net/bugs/1891451 intel_cdclk_needs_cd2x_update() is named rather confusingly. We don't have to do a cd2x update, rather we are allowed to do one (as opposed to a full PLL reprogramming with its heavy handed modeset). So let's rename the function to intel_cdclk_can_cd2x_update(). Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200120174728.21095-7-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak (cherry picked from commit 65c88a866d705589e898d288af25f6a3b7dfd829) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/display/intel_cdclk.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index ca0510e74516..37345ec04218 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1779,7 +1779,7 @@ bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a, } /** - * intel_cdclk_needs_cd2x_update - Determine if two CDCLK states require a cd2x divider update + * intel_cdclk_can_cd2x_update - Determine if two CDCLK states need a cd2x divider update * @dev_priv: Not a CDCLK state, it's the drm_i915_private! * @a: first CDCLK state * @b: second CDCLK state @@ -1787,9 +1787,9 @@ bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a, * Returns: * True if the CDCLK states require just a cd2x divider update, false if not. */ -static bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *a, - const struct intel_cdclk_state *b) +static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, + const struct intel_cdclk_state *a, + const struct intel_cdclk_state *b) { /* Older hw doesn't have the capability */ if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv)) @@ -2405,9 +2405,9 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) } if (is_power_of_2(state->active_pipes) && - intel_cdclk_needs_cd2x_update(dev_priv, - &dev_priv->cdclk.actual, - &state->cdclk.actual)) { + intel_cdclk_can_cd2x_update(dev_priv, + &dev_priv->cdclk.actual, + &state->cdclk.actual)) { struct intel_crtc *crtc; struct intel_crtc_state *crtc_state; From patchwork Fri Aug 14 06:57:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344659 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ5V4l4Dz9sPB; Fri, 14 Aug 2020 16:58:06 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1k6Tf9-0007b3-97; Fri, 14 Aug 2020 06:58:03 +0000 Received: from mail-pl1-f173.google.com ([209.85.214.173]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1k6Tf4-0007X5-0B for kernel-team@lists.ubuntu.com; Fri, 14 Aug 2020 06:57:58 +0000 Received: by mail-pl1-f173.google.com with SMTP id bh1so3745634plb.12 for ; Thu, 13 Aug 2020 23:57:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RLI6KDF/GhNG1/euvuohrpuLEX9PvZg3RiT/J/Hhfs0=; b=TJC8FSDdk3+uG9utiv3TKrLRPL0XfGk9vJp31nBgcdSbP3COK1oAWrOSRXyhuApUOv pkiDnIx6/l99++Vx31sWs7GOyfeTQr/mK5rl4g+W5Q/xiBW7nbROZQHSoAqXt3s1SEto hQOA3bWZgzoKpHGRLNunHXBlyzOCn3P63nQZDAc9fNCdRvvItcflpdvu6Z9DbatmsAyR Z8MWpoGTU2T8DS0Um++B9o1UgqTY7TP0oTLTBNicsLzC7C2V5x57OeHxUSbEz2sTZd0D FyDbeGkQ3iFrk1gw5FOdpnJans9Nrgj9PxaZEwxsrnck6s609xbiw17kSNSv+xu8O8u5 mD9A== X-Gm-Message-State: AOAM532wR7/T7LJG9isuGCiCGb8gLeT1dLibb1eQTtwkM9yWsjvH4oyj rWUElQ1eSo467w2bPnINtCkY3UNaYblJNg== X-Google-Smtp-Source: ABdhPJxs76b06kr8xwXTcP2f20pIx7VnXU3e/UdDJ8ZJv514i3zuZtTPsK70CBA46iMTqg8pM7Ru/Q== X-Received: by 2002:a17:902:968a:: with SMTP id n10mr1086489plp.67.1597388275018; Thu, 13 Aug 2020 23:57:55 -0700 (PDT) Received: from localhost (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id x127sm8074405pfd.86.2020.08.13.23.57.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:57:54 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 04/31][SRU][OEM-5.6] drm/i915: s/cdclk_state/cdclk_config/ Date: Fri, 14 Aug 2020 14:57:13 +0800 Message-Id: <20200814065740.276039-5-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.173; envelope-from=vicamo@gmail.com; helo=mail-pl1-f173.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Ville Syrjälä BugLink: https://bugs.launchpad.net/bugs/1891451 I want to have a higher level cdclk state object so let's rename the current lower level thing to cdclk_config (because I lack imagination). Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200120174728.21095-8-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza (backported from commit 0bb94e03834eaa9d5925b259ea140e53fdf68cfb fix conflicts due to DRM_ERROR and I915_READ macros) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/display/intel_cdclk.c | 426 +++++++++--------- drivers/gpu/drm/i915/display/intel_cdclk.h | 18 +- drivers/gpu/drm/i915/display/intel_display.c | 2 +- .../drm/i915/display/intel_display_power.c | 8 +- .../drm/i915/display/intel_display_types.h | 14 +- drivers/gpu/drm/i915/i915_drv.h | 20 +- 6 files changed, 246 insertions(+), 242 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 37345ec04218..100b09c93488 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -55,43 +55,43 @@ */ static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { - cdclk_state->cdclk = 133333; + cdclk_config->cdclk = 133333; } static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { - cdclk_state->cdclk = 200000; + cdclk_config->cdclk = 200000; } static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { - cdclk_state->cdclk = 266667; + cdclk_config->cdclk = 266667; } static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { - cdclk_state->cdclk = 333333; + cdclk_config->cdclk = 333333; } static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { - cdclk_state->cdclk = 400000; + cdclk_config->cdclk = 400000; } static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { - cdclk_state->cdclk = 450000; + cdclk_config->cdclk = 450000; } static void i85x_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { struct pci_dev *pdev = dev_priv->drm.pdev; u16 hpllcc = 0; @@ -102,7 +102,7 @@ static void i85x_get_cdclk(struct drm_i915_private *dev_priv, * FIXME is this the right way to detect 852GM/852GMV? */ if (pdev->revision == 0x1) { - cdclk_state->cdclk = 133333; + cdclk_config->cdclk = 133333; return; } @@ -116,24 +116,24 @@ static void i85x_get_cdclk(struct drm_i915_private *dev_priv, case GC_CLOCK_133_200: case GC_CLOCK_133_200_2: case GC_CLOCK_100_200: - cdclk_state->cdclk = 200000; + cdclk_config->cdclk = 200000; break; case GC_CLOCK_166_250: - cdclk_state->cdclk = 250000; + cdclk_config->cdclk = 250000; break; case GC_CLOCK_100_133: - cdclk_state->cdclk = 133333; + cdclk_config->cdclk = 133333; break; case GC_CLOCK_133_266: case GC_CLOCK_133_266_2: case GC_CLOCK_166_266: - cdclk_state->cdclk = 266667; + cdclk_config->cdclk = 266667; break; } } static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { struct pci_dev *pdev = dev_priv->drm.pdev; u16 gcfgc = 0; @@ -141,23 +141,23 @@ static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, pci_read_config_word(pdev, GCFGC, &gcfgc); if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { - cdclk_state->cdclk = 133333; + cdclk_config->cdclk = 133333; return; } switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { case GC_DISPLAY_CLOCK_333_320_MHZ: - cdclk_state->cdclk = 333333; + cdclk_config->cdclk = 333333; break; default: case GC_DISPLAY_CLOCK_190_200_MHZ: - cdclk_state->cdclk = 190000; + cdclk_config->cdclk = 190000; break; } } static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { struct pci_dev *pdev = dev_priv->drm.pdev; u16 gcfgc = 0; @@ -165,17 +165,17 @@ static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, pci_read_config_word(pdev, GCFGC, &gcfgc); if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { - cdclk_state->cdclk = 133333; + cdclk_config->cdclk = 133333; return; } switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { case GC_DISPLAY_CLOCK_333_320_MHZ: - cdclk_state->cdclk = 320000; + cdclk_config->cdclk = 320000; break; default: case GC_DISPLAY_CLOCK_190_200_MHZ: - cdclk_state->cdclk = 200000; + cdclk_config->cdclk = 200000; break; } } @@ -250,7 +250,7 @@ static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) } static void g33_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { struct pci_dev *pdev = dev_priv->drm.pdev; static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; @@ -261,7 +261,7 @@ static void g33_get_cdclk(struct drm_i915_private *dev_priv, unsigned int cdclk_sel; u16 tmp = 0; - cdclk_state->vco = intel_hpll_vco(dev_priv); + cdclk_config->vco = intel_hpll_vco(dev_priv); pci_read_config_word(pdev, GCFGC, &tmp); @@ -270,7 +270,7 @@ static void g33_get_cdclk(struct drm_i915_private *dev_priv, if (cdclk_sel >= ARRAY_SIZE(div_3200)) goto fail; - switch (cdclk_state->vco) { + switch (cdclk_config->vco) { case 3200000: div_table = div_3200; break; @@ -287,18 +287,18 @@ static void g33_get_cdclk(struct drm_i915_private *dev_priv, goto fail; } - cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, - div_table[cdclk_sel]); + cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, + div_table[cdclk_sel]); return; fail: DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", - cdclk_state->vco, tmp); - cdclk_state->cdclk = 190476; + cdclk_config->vco, tmp); + cdclk_config->cdclk = 190476; } static void pnv_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { struct pci_dev *pdev = dev_priv->drm.pdev; u16 gcfgc = 0; @@ -307,31 +307,31 @@ static void pnv_get_cdclk(struct drm_i915_private *dev_priv, switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { case GC_DISPLAY_CLOCK_267_MHZ_PNV: - cdclk_state->cdclk = 266667; + cdclk_config->cdclk = 266667; break; case GC_DISPLAY_CLOCK_333_MHZ_PNV: - cdclk_state->cdclk = 333333; + cdclk_config->cdclk = 333333; break; case GC_DISPLAY_CLOCK_444_MHZ_PNV: - cdclk_state->cdclk = 444444; + cdclk_config->cdclk = 444444; break; case GC_DISPLAY_CLOCK_200_MHZ_PNV: - cdclk_state->cdclk = 200000; + cdclk_config->cdclk = 200000; break; default: DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); /* fall through */ case GC_DISPLAY_CLOCK_133_MHZ_PNV: - cdclk_state->cdclk = 133333; + cdclk_config->cdclk = 133333; break; case GC_DISPLAY_CLOCK_167_MHZ_PNV: - cdclk_state->cdclk = 166667; + cdclk_config->cdclk = 166667; break; } } static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { struct pci_dev *pdev = dev_priv->drm.pdev; static const u8 div_3200[] = { 16, 10, 8 }; @@ -341,7 +341,7 @@ static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, unsigned int cdclk_sel; u16 tmp = 0; - cdclk_state->vco = intel_hpll_vco(dev_priv); + cdclk_config->vco = intel_hpll_vco(dev_priv); pci_read_config_word(pdev, GCFGC, &tmp); @@ -350,7 +350,7 @@ static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, if (cdclk_sel >= ARRAY_SIZE(div_3200)) goto fail; - switch (cdclk_state->vco) { + switch (cdclk_config->vco) { case 3200000: div_table = div_3200; break; @@ -364,62 +364,62 @@ static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, goto fail; } - cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, - div_table[cdclk_sel]); + cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, + div_table[cdclk_sel]); return; fail: DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", - cdclk_state->vco, tmp); - cdclk_state->cdclk = 200000; + cdclk_config->vco, tmp); + cdclk_config->cdclk = 200000; } static void gm45_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { struct pci_dev *pdev = dev_priv->drm.pdev; unsigned int cdclk_sel; u16 tmp = 0; - cdclk_state->vco = intel_hpll_vco(dev_priv); + cdclk_config->vco = intel_hpll_vco(dev_priv); pci_read_config_word(pdev, GCFGC, &tmp); cdclk_sel = (tmp >> 12) & 0x1; - switch (cdclk_state->vco) { + switch (cdclk_config->vco) { case 2666667: case 4000000: case 5333333: - cdclk_state->cdclk = cdclk_sel ? 333333 : 222222; + cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; break; case 3200000: - cdclk_state->cdclk = cdclk_sel ? 320000 : 228571; + cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; break; default: DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", - cdclk_state->vco, tmp); - cdclk_state->cdclk = 222222; + cdclk_config->vco, tmp); + cdclk_config->cdclk = 222222; break; } } static void hsw_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { u32 lcpll = I915_READ(LCPLL_CTL); u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; if (lcpll & LCPLL_CD_SOURCE_FCLK) - cdclk_state->cdclk = 800000; + cdclk_config->cdclk = 800000; else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) - cdclk_state->cdclk = 450000; + cdclk_config->cdclk = 450000; else if (freq == LCPLL_CLK_FREQ_450) - cdclk_state->cdclk = 450000; + cdclk_config->cdclk = 450000; else if (IS_HSW_ULT(dev_priv)) - cdclk_state->cdclk = 337500; + cdclk_config->cdclk = 337500; else - cdclk_state->cdclk = 540000; + cdclk_config->cdclk = 540000; } static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) @@ -462,17 +462,17 @@ static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) } static void vlv_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { u32 val; vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); - cdclk_state->vco = vlv_get_hpll_vco(dev_priv); - cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", - CCK_DISPLAY_CLOCK_CONTROL, - cdclk_state->vco); + cdclk_config->vco = vlv_get_hpll_vco(dev_priv); + cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", + CCK_DISPLAY_CLOCK_CONTROL, + cdclk_config->vco); val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); @@ -480,10 +480,10 @@ static void vlv_get_cdclk(struct drm_i915_private *dev_priv, BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); if (IS_VALLEYVIEW(dev_priv)) - cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK) >> + cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> DSPFREQGUAR_SHIFT; else - cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> + cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> DSPFREQGUAR_SHIFT_CHV; } @@ -524,11 +524,11 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) } static void vlv_set_cdclk(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *cdclk_state, + const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { - int cdclk = cdclk_state->cdclk; - u32 val, cmd = cdclk_state->voltage_level; + int cdclk = cdclk_config->cdclk; + u32 val, cmd = cdclk_config->voltage_level; intel_wakeref_t wakeref; switch (cdclk) { @@ -611,11 +611,11 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv, } static void chv_set_cdclk(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *cdclk_state, + const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { - int cdclk = cdclk_state->cdclk; - u32 val, cmd = cdclk_state->voltage_level; + int cdclk = cdclk_config->cdclk; + u32 val, cmd = cdclk_config->voltage_level; intel_wakeref_t wakeref; switch (cdclk) { @@ -685,37 +685,37 @@ static u8 bdw_calc_voltage_level(int cdclk) } static void bdw_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { u32 lcpll = I915_READ(LCPLL_CTL); u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; if (lcpll & LCPLL_CD_SOURCE_FCLK) - cdclk_state->cdclk = 800000; + cdclk_config->cdclk = 800000; else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) - cdclk_state->cdclk = 450000; + cdclk_config->cdclk = 450000; else if (freq == LCPLL_CLK_FREQ_450) - cdclk_state->cdclk = 450000; + cdclk_config->cdclk = 450000; else if (freq == LCPLL_CLK_FREQ_54O_BDW) - cdclk_state->cdclk = 540000; + cdclk_config->cdclk = 540000; else if (freq == LCPLL_CLK_FREQ_337_5_BDW) - cdclk_state->cdclk = 337500; + cdclk_config->cdclk = 337500; else - cdclk_state->cdclk = 675000; + cdclk_config->cdclk = 675000; /* * Can't read this out :( Let's assume it's * at least what the CDCLK frequency requires. */ - cdclk_state->voltage_level = - bdw_calc_voltage_level(cdclk_state->cdclk); + cdclk_config->voltage_level = + bdw_calc_voltage_level(cdclk_config->cdclk); } static void bdw_set_cdclk(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *cdclk_state, + const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { - int cdclk = cdclk_state->cdclk; + int cdclk = cdclk_config->cdclk; u32 val; int ret; @@ -778,7 +778,7 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv, DRM_ERROR("Switching back to LCPLL failed\n"); sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, - cdclk_state->voltage_level); + cdclk_config->voltage_level); I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); @@ -821,12 +821,12 @@ static u8 skl_calc_voltage_level(int cdclk) } static void skl_dpll0_update(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { u32 val; - cdclk_state->ref = 24000; - cdclk_state->vco = 0; + cdclk_config->ref = 24000; + cdclk_config->vco = 0; val = I915_READ(LCPLL1_CTL); if ((val & LCPLL_PLL_ENABLE) == 0) @@ -848,11 +848,11 @@ static void skl_dpll0_update(struct drm_i915_private *dev_priv, case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): - cdclk_state->vco = 8100000; + cdclk_config->vco = 8100000; break; case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): - cdclk_state->vco = 8640000; + cdclk_config->vco = 8640000; break; default: MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); @@ -861,32 +861,32 @@ static void skl_dpll0_update(struct drm_i915_private *dev_priv, } static void skl_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { u32 cdctl; - skl_dpll0_update(dev_priv, cdclk_state); + skl_dpll0_update(dev_priv, cdclk_config); - cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref; + cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; - if (cdclk_state->vco == 0) + if (cdclk_config->vco == 0) goto out; cdctl = I915_READ(CDCLK_CTL); - if (cdclk_state->vco == 8640000) { + if (cdclk_config->vco == 8640000) { switch (cdctl & CDCLK_FREQ_SEL_MASK) { case CDCLK_FREQ_450_432: - cdclk_state->cdclk = 432000; + cdclk_config->cdclk = 432000; break; case CDCLK_FREQ_337_308: - cdclk_state->cdclk = 308571; + cdclk_config->cdclk = 308571; break; case CDCLK_FREQ_540: - cdclk_state->cdclk = 540000; + cdclk_config->cdclk = 540000; break; case CDCLK_FREQ_675_617: - cdclk_state->cdclk = 617143; + cdclk_config->cdclk = 617143; break; default: MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); @@ -895,16 +895,16 @@ static void skl_get_cdclk(struct drm_i915_private *dev_priv, } else { switch (cdctl & CDCLK_FREQ_SEL_MASK) { case CDCLK_FREQ_450_432: - cdclk_state->cdclk = 450000; + cdclk_config->cdclk = 450000; break; case CDCLK_FREQ_337_308: - cdclk_state->cdclk = 337500; + cdclk_config->cdclk = 337500; break; case CDCLK_FREQ_540: - cdclk_state->cdclk = 540000; + cdclk_config->cdclk = 540000; break; case CDCLK_FREQ_675_617: - cdclk_state->cdclk = 675000; + cdclk_config->cdclk = 675000; break; default: MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); @@ -917,8 +917,8 @@ static void skl_get_cdclk(struct drm_i915_private *dev_priv, * Can't read this out :( Let's assume it's * at least what the CDCLK frequency requires. */ - cdclk_state->voltage_level = - skl_calc_voltage_level(cdclk_state->cdclk); + cdclk_config->voltage_level = + skl_calc_voltage_level(cdclk_config->cdclk); } /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ @@ -989,11 +989,11 @@ static void skl_dpll0_disable(struct drm_i915_private *dev_priv) } static void skl_set_cdclk(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *cdclk_state, + const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { - int cdclk = cdclk_state->cdclk; - int vco = cdclk_state->vco; + int cdclk = cdclk_config->cdclk; + int vco = cdclk_config->vco; u32 freq_select, cdclk_ctl; int ret; @@ -1075,7 +1075,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, /* inform PCU of the change */ sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, - cdclk_state->voltage_level); + cdclk_config->voltage_level); intel_update_cdclk(dev_priv); } @@ -1093,7 +1093,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) goto sanitize; intel_update_cdclk(dev_priv); - intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); + intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK"); /* Is PLL enabled and locked ? */ if (dev_priv->cdclk.hw.vco == 0 || @@ -1124,7 +1124,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) static void skl_init_cdclk(struct drm_i915_private *dev_priv) { - struct intel_cdclk_state cdclk_state; + struct intel_cdclk_config cdclk_config; skl_sanitize_cdclk(dev_priv); @@ -1140,26 +1140,26 @@ static void skl_init_cdclk(struct drm_i915_private *dev_priv) return; } - cdclk_state = dev_priv->cdclk.hw; + cdclk_config = dev_priv->cdclk.hw; - cdclk_state.vco = dev_priv->skl_preferred_vco_freq; - if (cdclk_state.vco == 0) - cdclk_state.vco = 8100000; - cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco); - cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk); + cdclk_config.vco = dev_priv->skl_preferred_vco_freq; + if (cdclk_config.vco == 0) + cdclk_config.vco = 8100000; + cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); + cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); - skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); + skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); } static void skl_uninit_cdclk(struct drm_i915_private *dev_priv) { - struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; + struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw; - cdclk_state.cdclk = cdclk_state.bypass; - cdclk_state.vco = 0; - cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk); + cdclk_config.cdclk = cdclk_config.bypass; + cdclk_config.vco = 0; + cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); - skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); + skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); } static const struct intel_cdclk_vals bxt_cdclk_table[] = { @@ -1296,16 +1296,16 @@ static u8 tgl_calc_voltage_level(int cdclk) } static void cnl_readout_refclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz) - cdclk_state->ref = 24000; + cdclk_config->ref = 24000; else - cdclk_state->ref = 19200; + cdclk_config->ref = 19200; } static void icl_readout_refclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { u32 dssm = I915_READ(SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; @@ -1314,28 +1314,28 @@ static void icl_readout_refclk(struct drm_i915_private *dev_priv, MISSING_CASE(dssm); /* fall through */ case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: - cdclk_state->ref = 24000; + cdclk_config->ref = 24000; break; case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: - cdclk_state->ref = 19200; + cdclk_config->ref = 19200; break; case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: - cdclk_state->ref = 38400; + cdclk_config->ref = 38400; break; } } static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { u32 val, ratio; if (INTEL_GEN(dev_priv) >= 11) - icl_readout_refclk(dev_priv, cdclk_state); + icl_readout_refclk(dev_priv, cdclk_config); else if (IS_CANNONLAKE(dev_priv)) - cnl_readout_refclk(dev_priv, cdclk_state); + cnl_readout_refclk(dev_priv, cdclk_config); else - cdclk_state->ref = 19200; + cdclk_config->ref = 19200; val = I915_READ(BXT_DE_PLL_ENABLE); if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || @@ -1344,7 +1344,7 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but * setting it to zero is a way to signal that. */ - cdclk_state->vco = 0; + cdclk_config->vco = 0; return; } @@ -1357,26 +1357,26 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, else ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; - cdclk_state->vco = ratio * cdclk_state->ref; + cdclk_config->vco = ratio * cdclk_config->ref; } static void bxt_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { u32 divider; int div; - bxt_de_pll_readout(dev_priv, cdclk_state); + bxt_de_pll_readout(dev_priv, cdclk_config); if (INTEL_GEN(dev_priv) >= 12) - cdclk_state->bypass = cdclk_state->ref / 2; + cdclk_config->bypass = cdclk_config->ref / 2; else if (INTEL_GEN(dev_priv) >= 11) - cdclk_state->bypass = 50000; + cdclk_config->bypass = 50000; else - cdclk_state->bypass = cdclk_state->ref; + cdclk_config->bypass = cdclk_config->ref; - if (cdclk_state->vco == 0) { - cdclk_state->cdclk = cdclk_state->bypass; + if (cdclk_config->vco == 0) { + cdclk_config->cdclk = cdclk_config->bypass; goto out; } @@ -1403,15 +1403,15 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, return; } - cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div); + cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); out: /* * Can't read this out :( Let's assume it's * at least what the CDCLK frequency requires. */ - cdclk_state->voltage_level = - dev_priv->display.calc_voltage_level(cdclk_state->cdclk); + cdclk_config->voltage_level = + dev_priv->display.calc_voltage_level(cdclk_config->cdclk); } static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) @@ -1500,11 +1500,11 @@ static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe } static void bxt_set_cdclk(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *cdclk_state, + const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { - int cdclk = cdclk_state->cdclk; - int vco = cdclk_state->vco; + int cdclk = cdclk_config->cdclk; + int vco = cdclk_config->vco; u32 val, divider; int ret; @@ -1585,7 +1585,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, if (INTEL_GEN(dev_priv) >= 10) { ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, - cdclk_state->voltage_level); + cdclk_config->voltage_level); } else { /* * The timeout isn't specified, the 2ms used here is based on @@ -1595,7 +1595,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, */ ret = sandybridge_pcode_write_timeout(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, - cdclk_state->voltage_level, + cdclk_config->voltage_level, 150, 2); } @@ -1612,7 +1612,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, * Can't read out the voltage level :( * Let's just assume everything is as expected. */ - dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level; + dev_priv->cdclk.hw.voltage_level = cdclk_config->voltage_level; } static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) @@ -1621,7 +1621,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) int cdclk, vco; intel_update_cdclk(dev_priv); - intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); + intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK"); if (dev_priv->cdclk.hw.vco == 0 || dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) @@ -1695,7 +1695,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) static void bxt_init_cdclk(struct drm_i915_private *dev_priv) { - struct intel_cdclk_state cdclk_state; + struct intel_cdclk_config cdclk_config; bxt_sanitize_cdclk(dev_priv); @@ -1703,31 +1703,31 @@ static void bxt_init_cdclk(struct drm_i915_private *dev_priv) dev_priv->cdclk.hw.vco != 0) return; - cdclk_state = dev_priv->cdclk.hw; + cdclk_config = dev_priv->cdclk.hw; /* * FIXME: * - The initial CDCLK needs to be read from VBT. * Need to make this change after VBT has changes for BXT. */ - cdclk_state.cdclk = bxt_calc_cdclk(dev_priv, 0); - cdclk_state.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk); - cdclk_state.voltage_level = - dev_priv->display.calc_voltage_level(cdclk_state.cdclk); + cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0); + cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); + cdclk_config.voltage_level = + dev_priv->display.calc_voltage_level(cdclk_config.cdclk); - bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); + bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); } static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) { - struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; + struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw; - cdclk_state.cdclk = cdclk_state.bypass; - cdclk_state.vco = 0; - cdclk_state.voltage_level = - dev_priv->display.calc_voltage_level(cdclk_state.cdclk); + cdclk_config.cdclk = cdclk_config.bypass; + cdclk_config.vco = 0; + cdclk_config.voltage_level = + dev_priv->display.calc_voltage_level(cdclk_config.cdclk); - bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); + bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); } /** @@ -1763,15 +1763,17 @@ void intel_cdclk_uninit(struct drm_i915_private *i915) } /** - * intel_cdclk_needs_modeset - Determine if two CDCLK states require a modeset on all pipes - * @a: first CDCLK state - * @b: second CDCLK state + * intel_cdclk_needs_modeset - Determine if changong between the CDCLK + * configurations requires a modeset on all pipes + * @a: first CDCLK configuration + * @b: second CDCLK configuration * * Returns: - * True if the CDCLK states require pipes to be off during reprogramming, false if not. + * True if changing between the two CDCLK configurations + * requires all pipes to be off, false if not. */ -bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a, - const struct intel_cdclk_state *b) +bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, + const struct intel_cdclk_config *b) { return a->cdclk != b->cdclk || a->vco != b->vco || @@ -1779,17 +1781,19 @@ bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a, } /** - * intel_cdclk_can_cd2x_update - Determine if two CDCLK states need a cd2x divider update - * @dev_priv: Not a CDCLK state, it's the drm_i915_private! - * @a: first CDCLK state - * @b: second CDCLK state + * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK + * configurations requires only a cd2x divider update + * @dev_priv: i915 device + * @a: first CDCLK configuration + * @b: second CDCLK configuration * * Returns: - * True if the CDCLK states require just a cd2x divider update, false if not. + * True if changing between the two CDCLK configurations + * can be done with just a cd2x divider update, false if not. */ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *a, - const struct intel_cdclk_state *b) + const struct intel_cdclk_config *a, + const struct intel_cdclk_config *b) { /* Older hw doesn't have the capability */ if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv)) @@ -1801,15 +1805,15 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, } /** - * intel_cdclk_changed - Determine if two CDCLK states are different - * @a: first CDCLK state - * @b: second CDCLK state + * intel_cdclk_changed - Determine if two CDCLK configurations are different + * @a: first CDCLK configuration + * @b: second CDCLK configuration * * Returns: - * True if the CDCLK states don't match, false if they do. + * True if the CDCLK configurations don't match, false if they do. */ -static bool intel_cdclk_changed(const struct intel_cdclk_state *a, - const struct intel_cdclk_state *b) +static bool intel_cdclk_changed(const struct intel_cdclk_config *a, + const struct intel_cdclk_config *b) { return intel_cdclk_needs_modeset(a, b) || a->voltage_level != b->voltage_level; @@ -1855,59 +1859,59 @@ void intel_cdclk_swap_state(struct intel_atomic_state *state) swap(state->cdclk.actual, dev_priv->cdclk.actual); } -void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state, - const char *context) +void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config, + const char *context) { DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", - context, cdclk_state->cdclk, cdclk_state->vco, - cdclk_state->ref, cdclk_state->bypass, - cdclk_state->voltage_level); + context, cdclk_config->cdclk, cdclk_config->vco, + cdclk_config->ref, cdclk_config->bypass, + cdclk_config->voltage_level); } /** - * intel_set_cdclk - Push the CDCLK state to the hardware + * intel_set_cdclk - Push the CDCLK configuration to the hardware * @dev_priv: i915 device - * @cdclk_state: new CDCLK state + * @cdclk_config: new CDCLK configuration * @pipe: pipe with which to synchronize the update * * Program the hardware based on the passed in CDCLK state, * if necessary. */ static void intel_set_cdclk(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *cdclk_state, + const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { - if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state)) + if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config)) return; if (WARN_ON_ONCE(!dev_priv->display.set_cdclk)) return; - intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to"); + intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to"); - dev_priv->display.set_cdclk(dev_priv, cdclk_state, pipe); + dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe); - if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state), + if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config), "cdclk state doesn't match!\n")) { - intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]"); - intel_dump_cdclk_state(cdclk_state, "[sw state]"); + intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]"); + intel_dump_cdclk_config(cdclk_config, "[sw state]"); } } /** - * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware + * intel_set_cdclk_pre_plane_update - Push the CDCLK configuration to the hardware * @dev_priv: i915 device - * @old_state: old CDCLK state - * @new_state: new CDCLK state + * @old_state: old CDCLK configuration + * @new_state: new CDCLK configuration * @pipe: pipe with which to synchronize the update * * Program the hardware before updating the HW plane state based on the passed - * in CDCLK state, if necessary. + * in CDCLK configuration, if necessary. */ void intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *old_state, - const struct intel_cdclk_state *new_state, + const struct intel_cdclk_config *old_state, + const struct intel_cdclk_config *new_state, enum pipe pipe) { if (pipe == INVALID_PIPE || old_state->cdclk <= new_state->cdclk) @@ -1915,19 +1919,19 @@ intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv, } /** - * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware + * intel_set_cdclk_post_plane_update - Push the CDCLK configuration to the hardware * @dev_priv: i915 device - * @old_state: old CDCLK state - * @new_state: new CDCLK state + * @old_state: old CDCLK configuration + * @new_state: new CDCLK configuration * @pipe: pipe with which to synchronize the update * * Program the hardware after updating the HW plane state based on the passed - * in CDCLK state, if necessary. + * in CDCLK configuration, if necessary. */ void intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *old_state, - const struct intel_cdclk_state *new_state, + const struct intel_cdclk_config *old_state, + const struct intel_cdclk_config *new_state, enum pipe pipe) { if (pipe != INVALID_PIPE && old_state->cdclk > new_state->cdclk) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index 3f3773c582ae..712cdaea4fef 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -12,7 +12,7 @@ struct drm_i915_private; struct intel_atomic_state; -struct intel_cdclk_state; +struct intel_cdclk_config; struct intel_crtc_state; struct intel_cdclk_vals { @@ -29,22 +29,22 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv); void intel_update_max_cdclk(struct drm_i915_private *dev_priv); void intel_update_cdclk(struct drm_i915_private *dev_priv); void intel_update_rawclk(struct drm_i915_private *dev_priv); -bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a, - const struct intel_cdclk_state *b); +bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, + const struct intel_cdclk_config *b); void intel_cdclk_clear_state(struct intel_atomic_state *state); void intel_cdclk_swap_state(struct intel_atomic_state *state); void intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *old_state, - const struct intel_cdclk_state *new_state, + const struct intel_cdclk_config *old_state, + const struct intel_cdclk_config *new_state, enum pipe pipe); void intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *old_state, - const struct intel_cdclk_state *new_state, + const struct intel_cdclk_config *old_state, + const struct intel_cdclk_config *new_state, enum pipe pipe); -void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state, - const char *context); +void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config, + const char *context); int intel_modeset_calc_cdclk(struct intel_atomic_state *state); #endif /* __INTEL_CDCLK_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f405f9c1512d..91eb687c98ef 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -17403,7 +17403,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) void intel_modeset_init_hw(struct drm_i915_private *i915) { intel_update_cdclk(i915); - intel_dump_cdclk_state(&i915->cdclk.hw, "Current CDCLK"); + intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK"); i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw; } diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 9a4ede33a851..dec2c94ee51b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1161,7 +1161,7 @@ static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) static void gen9_disable_dc_states(struct drm_i915_private *dev_priv) { - struct intel_cdclk_state cdclk_state = {}; + struct intel_cdclk_config cdclk_config = {}; if (dev_priv->csr.target_dc_state == DC_STATE_EN_DC3CO) { tgl_disable_dc3co(dev_priv); @@ -1170,9 +1170,9 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv) gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); - dev_priv->display.get_cdclk(dev_priv, &cdclk_state); + dev_priv->display.get_cdclk(dev_priv, &cdclk_config); /* Can't read out voltage_level so can't use intel_cdclk_changed() */ - WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state)); + WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_config)); gen9_assert_dbuf_enabled(dev_priv); @@ -4723,7 +4723,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); intel_update_cdclk(dev_priv); - intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); + intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK"); } /* diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index d7a5f2e5fd14..e2ed7b4d6b41 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -465,17 +465,17 @@ struct intel_atomic_state { struct { /* - * Logical state of cdclk (used for all scaling, watermark, - * etc. calculations and checks). This is computed as if all - * enabled crtcs were active. + * Logical configuration of cdclk (used for all scaling, + * watermark, etc. calculations and checks). This is + * computed as if all enabled crtcs were active. */ - struct intel_cdclk_state logical; + struct intel_cdclk_config logical; /* - * Actual state of cdclk, can be different from the logical - * state only when all crtc's are DPMS off. + * Actual configuration of cdclk, can be different from the + * logical configuration only when all crtc's are DPMS off. */ - struct intel_cdclk_state actual; + struct intel_cdclk_config actual; int force_min_cdclk; bool force_min_cdclk_changed; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ef75a913f05b..17b4a6355fa2 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -255,18 +255,18 @@ struct sdvo_device_mapping { struct intel_connector; struct intel_encoder; struct intel_atomic_state; +struct intel_cdclk_config; struct intel_crtc_state; struct intel_initial_plane_config; struct intel_crtc; struct intel_limit; struct dpll; -struct intel_cdclk_state; struct drm_i915_display_funcs { void (*get_cdclk)(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state); + struct intel_cdclk_config *cdclk_config); void (*set_cdclk)(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *cdclk_state, + const struct intel_cdclk_config *cdclk_config, enum pipe pipe); int (*get_fifo_size)(struct drm_i915_private *dev_priv, enum i9xx_plane_id i9xx_plane); @@ -872,7 +872,7 @@ struct intel_wm_config { bool sprites_scaled; }; -struct intel_cdclk_state { +struct intel_cdclk_config { unsigned int cdclk, vco, ref, bypass; u8 voltage_level; }; @@ -1003,17 +1003,17 @@ struct drm_i915_private { */ struct { /* - * The current logical cdclk state. + * The current logical cdclk configuration. * See intel_atomic_state.cdclk.logical */ - struct intel_cdclk_state logical; + struct intel_cdclk_config logical; /* - * The current actual cdclk state. + * The current actual cdclk configuration. * See intel_atomic_state.cdclk.actual */ - struct intel_cdclk_state actual; - /* The current hardware cdclk state */ - struct intel_cdclk_state hw; + struct intel_cdclk_config actual; + /* The current hardware cdclk configuration */ + struct intel_cdclk_config hw; /* cdclk, divider, and ratio table from bspec */ const struct intel_cdclk_vals *table; From patchwork Fri Aug 14 06:57:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344660 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ5X0bJbz9sTN; Fri, 14 Aug 2020 16:58:08 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1k6TfA-0007cE-RQ; Fri, 14 Aug 2020 06:58:04 +0000 Received: from mail-pj1-f49.google.com ([209.85.216.49]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1k6Tf6-0007YH-UK for kernel-team@lists.ubuntu.com; Fri, 14 Aug 2020 06:58:01 +0000 Received: by mail-pj1-f49.google.com with SMTP id c6so3972546pje.1 for ; Thu, 13 Aug 2020 23:57:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sgRILGCymQQF1AJ8T2gkTDgiAVdO6HY44ol3HA9brr8=; b=oeg5bOymsPSZFHUAATliZsDVlnnjryNB6Xu28AuoeVnvlqyyy+PmTynOi1RF8n0Ht2 Fc+rBApnVXS74yVszH3jghDHiP0yOercw5euCzE9Zm0XwAdFsKDCEewZuDmAlpmE0xXz ofDsMidz8a0ytyJuX35/3xrgxAQhTsI3O97Xg3iF6WdkrzvAY0XKU1cCvSPnFz9/TWzp kFet9qg0HKaf2qqcSF3vrOZ6lIXOTQGk5wPy3EJX4uGuyhwviOAxvrzlT1v5oFWvG4p9 GGjgMu1iZO/SnGFbXL/ujcbdBwxY3/HRPhZ1OH+1YeoeZWXG8sJV26p5yWOrMuJU2tJX WqRw== X-Gm-Message-State: AOAM533rgKHYuPr1+1YUS8CPqVl1b820p6SfcqtgQmL3AEkeoSIqDxnz uIjf/EPy8xuIHNISKLcbmER7fizrr0BKRQ== X-Google-Smtp-Source: ABdhPJzqN3hWDHXOauYvRUin1+Ldy3uv1SCENpP8oKTx/dqqULjZcYPBqAooDOihrmn21KDU3IAj+Q== X-Received: by 2002:a17:90b:c90:: with SMTP id o16mr1091632pjz.79.1597388277495; Thu, 13 Aug 2020 23:57:57 -0700 (PDT) Received: from localhost (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id y135sm8407266pfg.148.2020.08.13.23.57.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:57:56 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 05/31][SRU][OEM-5.6] drm/i915: Simplify intel_set_cdclk_{pre, post}_plane_update() calling convention Date: Fri, 14 Aug 2020 14:57:14 +0800 Message-Id: <20200814065740.276039-6-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.216.49; envelope-from=vicamo@gmail.com; helo=mail-pj1-f49.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Ville Syrjälä BugLink: https://bugs.launchpad.net/bugs/1891451 Move all the old vs. new state shenanigans into intel_set_cdclk_{pre,post}_plane_update() so that the caller doesn't need to know any of it. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200120174728.21095-9-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza (cherry picked from commit 5604e9ceaed59956c5027832c9f09d48ab3126cb) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/display/intel_cdclk.c | 44 ++++++++++---------- drivers/gpu/drm/i915/display/intel_cdclk.h | 12 +----- drivers/gpu/drm/i915/display/intel_display.c | 10 +---- 3 files changed, 26 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 100b09c93488..410dce69e48e 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1899,41 +1899,41 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv, } /** - * intel_set_cdclk_pre_plane_update - Push the CDCLK configuration to the hardware - * @dev_priv: i915 device - * @old_state: old CDCLK configuration - * @new_state: new CDCLK configuration - * @pipe: pipe with which to synchronize the update + * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware + * @state: intel atomic state * - * Program the hardware before updating the HW plane state based on the passed - * in CDCLK configuration, if necessary. + * Program the hardware before updating the HW plane state based on the + * new CDCLK state, if necessary. */ void -intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv, - const struct intel_cdclk_config *old_state, - const struct intel_cdclk_config *new_state, - enum pipe pipe) +intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) { + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + /* called after intel_cdclk_swap_state()! */ + const struct intel_cdclk_config *old_state = &state->cdclk.actual; + const struct intel_cdclk_config *new_state = &dev_priv->cdclk.actual; + enum pipe pipe = state->cdclk.pipe; + if (pipe == INVALID_PIPE || old_state->cdclk <= new_state->cdclk) intel_set_cdclk(dev_priv, new_state, pipe); } /** - * intel_set_cdclk_post_plane_update - Push the CDCLK configuration to the hardware - * @dev_priv: i915 device - * @old_state: old CDCLK configuration - * @new_state: new CDCLK configuration - * @pipe: pipe with which to synchronize the update + * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware + * @state: intel atomic state * - * Program the hardware after updating the HW plane state based on the passed - * in CDCLK configuration, if necessary. + * Program the hardware before updating the HW plane state based on the + * new CDCLK state, if necessary. */ void -intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv, - const struct intel_cdclk_config *old_state, - const struct intel_cdclk_config *new_state, - enum pipe pipe) +intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) { + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + /* called after intel_cdclk_swap_state()! */ + const struct intel_cdclk_config *old_state = &state->cdclk.actual; + const struct intel_cdclk_config *new_state = &dev_priv->cdclk.actual; + enum pipe pipe = state->cdclk.pipe; + if (pipe != INVALID_PIPE && old_state->cdclk > new_state->cdclk) intel_set_cdclk(dev_priv, new_state, pipe); } diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index 712cdaea4fef..a3fb7b8e8d31 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -33,16 +33,8 @@ bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, const struct intel_cdclk_config *b); void intel_cdclk_clear_state(struct intel_atomic_state *state); void intel_cdclk_swap_state(struct intel_atomic_state *state); -void -intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv, - const struct intel_cdclk_config *old_state, - const struct intel_cdclk_config *new_state, - enum pipe pipe); -void -intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv, - const struct intel_cdclk_config *old_state, - const struct intel_cdclk_config *new_state, - enum pipe pipe); +void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state); +void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state); void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config, const char *context); int intel_modeset_calc_cdclk(struct intel_atomic_state *state); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 91eb687c98ef..93fbfd21f3bf 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15447,10 +15447,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) if (state->modeset) { drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); - intel_set_cdclk_pre_plane_update(dev_priv, - &state->cdclk.actual, - &dev_priv->cdclk.actual, - state->cdclk.pipe); + intel_set_cdclk_pre_plane_update(state); /* * SKL workaround: bspec recommends we disable the SAGV when we @@ -15490,10 +15487,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) if (state->modeset) { intel_encoders_update_complete(state); - intel_set_cdclk_post_plane_update(dev_priv, - &state->cdclk.actual, - &dev_priv->cdclk.actual, - state->cdclk.pipe); + intel_set_cdclk_post_plane_update(state); } /* FIXME: We should call drm_atomic_helper_commit_hw_done() here From patchwork Fri Aug 14 06:57:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344661 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ5d3BsLz9sTM; Fri, 14 Aug 2020 16:58:13 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1k6TfE-0007ez-SL; Fri, 14 Aug 2020 06:58:08 +0000 Received: from mail-pl1-f176.google.com ([209.85.214.176]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1k6TfA-0007ar-7A for kernel-team@lists.ubuntu.com; Fri, 14 Aug 2020 06:58:04 +0000 Received: by mail-pl1-f176.google.com with SMTP id t11so3762641plr.5 for ; Thu, 13 Aug 2020 23:58:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RXAQZg/g247sduWw//8RC1bDwO+8b0E+kUHqFpdUG/0=; b=fPaqwFltngiHrtvxfrRC+D+B1GBrvCmg5ktRLIAzenR6hhqIYvAvXxMrX8DU1PLjBA 0nJGegWLCpMHbmV5OvWrR++BaFByyMBnjQ8ydgW/nv/faSR13Lwg77EFwhhac5J1CjFR TPYc7pmuw6mIFr/g+P5mPzJShpNPzyFVWo2WiT3zdqMm6wE0aOJtebIcnd+uIbZSXNAH wkcwRoaIsYQrQhdPslRDitVMQAloY9h81AMtZRBZz5+1UpjtSn2d99aYSXU+RkDxXkO4 NciVf0UHewLvX0CERNgb227zHr76oiuJysaNodD5BjZIJxfFJJiXRyKjKq5wl9uRtnhU 9efQ== X-Gm-Message-State: AOAM531+2t9KrjbyQ12SzNQBVTXbT8IjaDGdAdPsT3i2pR8lOXlEancw PyZ6FjxWKy7hoawPTYzCYobJqNMxs2nw5A== X-Google-Smtp-Source: ABdhPJy/nwlySQvOS2DhTd+orj26kTEyvF+EjU+6IxqFfVIXTkjRMIlgHdYnHUSKhgP4tsaRFP0dsg== X-Received: by 2002:a17:902:8210:: with SMTP id x16mr1129148pln.166.1597388280452; Thu, 13 Aug 2020 23:58:00 -0700 (PDT) Received: from localhost (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id p9sm7526173pjm.1.2020.08.13.23.57.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:57:59 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 06/31][SRU][OEM-5.6] drm/i915: Extract intel_cdclk_state Date: Fri, 14 Aug 2020 14:57:15 +0800 Message-Id: <20200814065740.276039-7-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.176; envelope-from=vicamo@gmail.com; helo=mail-pl1-f176.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Ville Syrjälä BugLink: https://bugs.launchpad.net/bugs/1891451 Use the same structure to store the cdclk state in both intel_atomic_state and dev_priv. First step towards proper old vs. new cdclk states. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200120174728.21095-10-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza (backported from commit 1965de63a93aecd788874e921f074b52fbea81a8 fix conflicts due to DRM_DEBUG_KMS) Signed-off-by: You-Sheng Yang --- .../gpu/drm/i915/display/intel_atomic_plane.c | 6 +- drivers/gpu/drm/i915/display/intel_audio.c | 4 +- drivers/gpu/drm/i915/display/intel_cdclk.c | 168 ++++++++++-------- drivers/gpu/drm/i915/display/intel_display.c | 29 ++- .../drm/i915/display/intel_display_types.h | 30 +--- drivers/gpu/drm/i915/i915_drv.h | 51 ++++-- 6 files changed, 151 insertions(+), 137 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 3e97af682b1b..563caec1d201 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -159,6 +159,8 @@ bool intel_plane_calc_min_cdclk(struct intel_atomic_state *state, struct intel_plane *plane) { struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + const struct intel_cdclk_state *cdclk_state = + &dev_priv->cdclk_state; const struct intel_plane_state *plane_state = intel_atomic_get_new_plane_state(state, plane); struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc); @@ -182,11 +184,11 @@ bool intel_plane_calc_min_cdclk(struct intel_atomic_state *state, * safe as long we hold at least one crtc mutex (which * must be true since we have crtc_state). */ - if (crtc_state->min_cdclk[plane->id] > dev_priv->cdclk.logical.cdclk) { + if (crtc_state->min_cdclk[plane->id] > cdclk_state->logical.cdclk) { DRM_DEBUG_KMS("[PLANE:%d:%s] min_cdclk (%d kHz) > logical cdclk (%d kHz)\n", plane->base.base.id, plane->base.name, crtc_state->min_cdclk[plane->id], - dev_priv->cdclk.logical.cdclk); + cdclk_state->logical.cdclk); return true; } diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index a228b291df99..c16ec35a90d4 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -823,8 +823,8 @@ static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv, state->acquire_ctx = &ctx; retry: - to_intel_atomic_state(state)->cdclk.force_min_cdclk_changed = true; - to_intel_atomic_state(state)->cdclk.force_min_cdclk = + to_intel_atomic_state(state)->cdclk_state.force_min_cdclk_changed = true; + to_intel_atomic_state(state)->cdclk_state.force_min_cdclk = enable ? 2 * 96000 : 0; /* Protects dev_priv->cdclk.force_min_cdclk */ diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 410dce69e48e..e219b2fb986c 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1827,8 +1827,8 @@ static bool intel_cdclk_changed(const struct intel_cdclk_config *a, */ void intel_cdclk_clear_state(struct intel_atomic_state *state) { - memset(&state->cdclk, 0, sizeof(state->cdclk)); - state->cdclk.pipe = INVALID_PIPE; + memset(&state->cdclk_state, 0, sizeof(state->cdclk_state)); + state->cdclk_state.pipe = INVALID_PIPE; } /** @@ -1848,15 +1848,18 @@ void intel_cdclk_swap_state(struct intel_atomic_state *state) struct drm_i915_private *dev_priv = to_i915(state->base.dev); /* FIXME maybe swap() these too */ - memcpy(dev_priv->cdclk.min_cdclk, state->cdclk.min_cdclk, - sizeof(state->cdclk.min_cdclk)); - memcpy(dev_priv->cdclk.min_voltage_level, state->cdclk.min_voltage_level, - sizeof(state->cdclk.min_voltage_level)); + memcpy(dev_priv->cdclk_state.min_cdclk, + state->cdclk_state.min_cdclk, + sizeof(state->cdclk_state.min_cdclk)); + memcpy(dev_priv->cdclk_state.min_voltage_level, + state->cdclk_state.min_voltage_level, + sizeof(state->cdclk_state.min_voltage_level)); - dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk; + dev_priv->cdclk_state.force_min_cdclk = + state->cdclk_state.force_min_cdclk; - swap(state->cdclk.logical, dev_priv->cdclk.logical); - swap(state->cdclk.actual, dev_priv->cdclk.actual); + swap(state->cdclk_state.logical, dev_priv->cdclk_state.logical); + swap(state->cdclk_state.actual, dev_priv->cdclk_state.actual); } void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config, @@ -1910,12 +1913,13 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); /* called after intel_cdclk_swap_state()! */ - const struct intel_cdclk_config *old_state = &state->cdclk.actual; - const struct intel_cdclk_config *new_state = &dev_priv->cdclk.actual; - enum pipe pipe = state->cdclk.pipe; + const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state; + const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state; + enum pipe pipe = old_cdclk_state->pipe; /* not swapped */ - if (pipe == INVALID_PIPE || old_state->cdclk <= new_state->cdclk) - intel_set_cdclk(dev_priv, new_state, pipe); + if (pipe == INVALID_PIPE || + old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) + intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); } /** @@ -1930,12 +1934,13 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); /* called after intel_cdclk_swap_state()! */ - const struct intel_cdclk_config *old_state = &state->cdclk.actual; - const struct intel_cdclk_config *new_state = &dev_priv->cdclk.actual; - enum pipe pipe = state->cdclk.pipe; + const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state; + const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state; + enum pipe pipe = old_cdclk_state->pipe; /* not swapped */ - if (pipe != INVALID_PIPE && old_state->cdclk > new_state->cdclk) - intel_set_cdclk(dev_priv, new_state, pipe); + if (pipe != INVALID_PIPE && + old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) + intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); } static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) @@ -2064,6 +2069,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) static int intel_compute_min_cdclk(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_cdclk_state *cdclk_state = &state->cdclk_state; struct intel_crtc *crtc; struct intel_crtc_state *crtc_state; int min_cdclk, i; @@ -2076,19 +2082,19 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state) if (min_cdclk < 0) return min_cdclk; - if (state->cdclk.min_cdclk[i] == min_cdclk) + if (cdclk_state->min_cdclk[i] == min_cdclk) continue; - state->cdclk.min_cdclk[i] = min_cdclk; + cdclk_state->min_cdclk[i] = min_cdclk; ret = intel_atomic_lock_global_state(state); if (ret) return ret; } - min_cdclk = state->cdclk.force_min_cdclk; + min_cdclk = cdclk_state->force_min_cdclk; for_each_pipe(dev_priv, pipe) - min_cdclk = max(state->cdclk.min_cdclk[pipe], min_cdclk); + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); return min_cdclk; } @@ -2109,6 +2115,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state) static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_cdclk_state *cdclk_state = &state->cdclk_state; struct intel_crtc *crtc; struct intel_crtc_state *crtc_state; u8 min_voltage_level; @@ -2123,10 +2130,10 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) else min_voltage_level = 0; - if (state->cdclk.min_voltage_level[i] == min_voltage_level) + if (cdclk_state->min_voltage_level[i] == min_voltage_level) continue; - state->cdclk.min_voltage_level[i] = min_voltage_level; + cdclk_state->min_voltage_level[i] = min_voltage_level; ret = intel_atomic_lock_global_state(state); if (ret) @@ -2135,7 +2142,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) min_voltage_level = 0; for_each_pipe(dev_priv, pipe) - min_voltage_level = max(state->cdclk.min_voltage_level[pipe], + min_voltage_level = max(cdclk_state->min_voltage_level[pipe], min_voltage_level); return min_voltage_level; @@ -2144,6 +2151,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_cdclk_state *cdclk_state = &state->cdclk_state; int min_cdclk, cdclk; min_cdclk = intel_compute_min_cdclk(state); @@ -2152,18 +2160,18 @@ static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state) cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); - state->cdclk.logical.cdclk = cdclk; - state->cdclk.logical.voltage_level = + cdclk_state->logical.cdclk = cdclk; + cdclk_state->logical.voltage_level = vlv_calc_voltage_level(dev_priv, cdclk); if (!state->active_pipes) { - cdclk = vlv_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk); + cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); - state->cdclk.actual.cdclk = cdclk; - state->cdclk.actual.voltage_level = + cdclk_state->actual.cdclk = cdclk; + cdclk_state->actual.voltage_level = vlv_calc_voltage_level(dev_priv, cdclk); } else { - state->cdclk.actual = state->cdclk.logical; + cdclk_state->actual = cdclk_state->logical; } return 0; @@ -2171,6 +2179,7 @@ static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state) static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state) { + struct intel_cdclk_state *cdclk_state = &state->cdclk_state; int min_cdclk, cdclk; min_cdclk = intel_compute_min_cdclk(state); @@ -2183,18 +2192,18 @@ static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state) */ cdclk = bdw_calc_cdclk(min_cdclk); - state->cdclk.logical.cdclk = cdclk; - state->cdclk.logical.voltage_level = + cdclk_state->logical.cdclk = cdclk; + cdclk_state->logical.voltage_level = bdw_calc_voltage_level(cdclk); if (!state->active_pipes) { - cdclk = bdw_calc_cdclk(state->cdclk.force_min_cdclk); + cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); - state->cdclk.actual.cdclk = cdclk; - state->cdclk.actual.voltage_level = + cdclk_state->actual.cdclk = cdclk; + cdclk_state->actual.voltage_level = bdw_calc_voltage_level(cdclk); } else { - state->cdclk.actual = state->cdclk.logical; + cdclk_state->actual = cdclk_state->logical; } return 0; @@ -2203,11 +2212,12 @@ static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state) static int skl_dpll0_vco(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_cdclk_state *cdclk_state = &state->cdclk_state; struct intel_crtc *crtc; struct intel_crtc_state *crtc_state; int vco, i; - vco = state->cdclk.logical.vco; + vco = cdclk_state->logical.vco; if (!vco) vco = dev_priv->skl_preferred_vco_freq; @@ -2238,6 +2248,7 @@ static int skl_dpll0_vco(struct intel_atomic_state *state) static int skl_modeset_calc_cdclk(struct intel_atomic_state *state) { + struct intel_cdclk_state *cdclk_state = &state->cdclk_state; int min_cdclk, cdclk, vco; min_cdclk = intel_compute_min_cdclk(state); @@ -2252,20 +2263,20 @@ static int skl_modeset_calc_cdclk(struct intel_atomic_state *state) */ cdclk = skl_calc_cdclk(min_cdclk, vco); - state->cdclk.logical.vco = vco; - state->cdclk.logical.cdclk = cdclk; - state->cdclk.logical.voltage_level = + cdclk_state->logical.vco = vco; + cdclk_state->logical.cdclk = cdclk; + cdclk_state->logical.voltage_level = skl_calc_voltage_level(cdclk); if (!state->active_pipes) { - cdclk = skl_calc_cdclk(state->cdclk.force_min_cdclk, vco); + cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); - state->cdclk.actual.vco = vco; - state->cdclk.actual.cdclk = cdclk; - state->cdclk.actual.voltage_level = + cdclk_state->actual.vco = vco; + cdclk_state->actual.cdclk = cdclk; + cdclk_state->actual.voltage_level = skl_calc_voltage_level(cdclk); } else { - state->cdclk.actual = state->cdclk.logical; + cdclk_state->actual = cdclk_state->logical; } return 0; @@ -2274,6 +2285,7 @@ static int skl_modeset_calc_cdclk(struct intel_atomic_state *state) static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_cdclk_state *cdclk_state = &state->cdclk_state; int min_cdclk, min_voltage_level, cdclk, vco; min_cdclk = intel_compute_min_cdclk(state); @@ -2287,22 +2299,22 @@ static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state) cdclk = bxt_calc_cdclk(dev_priv, min_cdclk); vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); - state->cdclk.logical.vco = vco; - state->cdclk.logical.cdclk = cdclk; - state->cdclk.logical.voltage_level = + cdclk_state->logical.vco = vco; + cdclk_state->logical.cdclk = cdclk; + cdclk_state->logical.voltage_level = max_t(int, min_voltage_level, dev_priv->display.calc_voltage_level(cdclk)); if (!state->active_pipes) { - cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk); + cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); - state->cdclk.actual.vco = vco; - state->cdclk.actual.cdclk = cdclk; - state->cdclk.actual.voltage_level = + cdclk_state->actual.vco = vco; + cdclk_state->actual.cdclk = cdclk; + cdclk_state->actual.voltage_level = dev_priv->display.calc_voltage_level(cdclk); } else { - state->cdclk.actual = state->cdclk.logical; + cdclk_state->actual = cdclk_state->logical; } return 0; @@ -2366,20 +2378,22 @@ static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state) int intel_modeset_calc_cdclk(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); + const struct intel_cdclk_state *old_cdclk_state = &dev_priv->cdclk_state; + struct intel_cdclk_state *new_cdclk_state = &state->cdclk_state; enum pipe pipe; int ret; - memcpy(state->cdclk.min_cdclk, dev_priv->cdclk.min_cdclk, - sizeof(state->cdclk.min_cdclk)); - memcpy(state->cdclk.min_voltage_level, dev_priv->cdclk.min_voltage_level, - sizeof(state->cdclk.min_voltage_level)); + memcpy(new_cdclk_state->min_cdclk, old_cdclk_state->min_cdclk, + sizeof(new_cdclk_state->min_cdclk)); + memcpy(new_cdclk_state->min_voltage_level, old_cdclk_state->min_voltage_level, + sizeof(new_cdclk_state->min_voltage_level)); /* keep the current setting */ - if (!state->cdclk.force_min_cdclk_changed) - state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk; + if (!new_cdclk_state->force_min_cdclk_changed) + new_cdclk_state->force_min_cdclk = old_cdclk_state->force_min_cdclk; - state->cdclk.logical = dev_priv->cdclk.logical; - state->cdclk.actual = dev_priv->cdclk.actual; + new_cdclk_state->logical = old_cdclk_state->logical; + new_cdclk_state->actual = old_cdclk_state->actual; ret = dev_priv->display.modeset_calc_cdclk(state); if (ret) @@ -2390,8 +2404,8 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) * by holding all the crtc mutexes even if we don't end up * touching the hardware */ - if (intel_cdclk_changed(&dev_priv->cdclk.actual, - &state->cdclk.actual)) { + if (intel_cdclk_changed(&old_cdclk_state->actual, + &new_cdclk_state->actual)) { /* * Also serialize commits across all crtcs * if the actual hw needs to be poked. @@ -2399,8 +2413,8 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) ret = intel_atomic_serialize_global_state(state); if (ret) return ret; - } else if (intel_cdclk_changed(&dev_priv->cdclk.logical, - &state->cdclk.logical)) { + } else if (intel_cdclk_changed(&old_cdclk_state->logical, + &new_cdclk_state->logical)) { ret = intel_atomic_lock_global_state(state); if (ret) return ret; @@ -2410,8 +2424,8 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) if (is_power_of_2(state->active_pipes) && intel_cdclk_can_cd2x_update(dev_priv, - &dev_priv->cdclk.actual, - &state->cdclk.actual)) { + &old_cdclk_state->actual, + &new_cdclk_state->actual)) { struct intel_crtc *crtc; struct intel_crtc_state *crtc_state; @@ -2429,28 +2443,28 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) } if (pipe != INVALID_PIPE) { - state->cdclk.pipe = pipe; + new_cdclk_state->pipe = pipe; DRM_DEBUG_KMS("Can change cdclk with pipe %c active\n", pipe_name(pipe)); - } else if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual, - &state->cdclk.actual)) { + } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual, + &new_cdclk_state->actual)) { /* All pipes must be switched off while we change the cdclk. */ ret = intel_modeset_all_pipes(state); if (ret) return ret; - state->cdclk.pipe = INVALID_PIPE; + new_cdclk_state->pipe = INVALID_PIPE; DRM_DEBUG_KMS("Modeset required for cdclk change\n"); } DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n", - state->cdclk.logical.cdclk, - state->cdclk.actual.cdclk); + new_cdclk_state->logical.cdclk, + new_cdclk_state->actual.cdclk); DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n", - state->cdclk.logical.voltage_level, - state->cdclk.actual.voltage_level); + new_cdclk_state->logical.voltage_level, + new_cdclk_state->actual.voltage_level); return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 93fbfd21f3bf..4972d5ef45c2 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7499,6 +7499,8 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_bw_state *bw_state = to_intel_bw_state(dev_priv->bw_obj.state); + struct intel_cdclk_state *cdclk_state = + &dev_priv->cdclk_state; struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); enum intel_display_power_domain domain; @@ -7565,8 +7567,8 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, crtc->enabled_power_domains = 0; dev_priv->active_pipes &= ~BIT(pipe); - dev_priv->cdclk.min_cdclk[pipe] = 0; - dev_priv->cdclk.min_voltage_level[pipe] = 0; + cdclk_state->min_cdclk[pipe] = 0; + cdclk_state->min_voltage_level[pipe] = 0; bw_state->data_rate[pipe] = 0; bw_state->num_active_planes[pipe] = 0; @@ -7802,6 +7804,8 @@ static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state) to_i915(crtc_state->uapi.crtc->dev); struct intel_atomic_state *intel_state = to_intel_atomic_state(crtc_state->uapi.state); + const struct intel_cdclk_state *cdclk_state = + &intel_state->cdclk_state; if (!hsw_crtc_state_ips_capable(crtc_state)) return false; @@ -7821,7 +7825,7 @@ static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state) /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ if (IS_BROADWELL(dev_priv) && - crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100) + crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100) return false; return true; @@ -12566,12 +12570,14 @@ static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state) to_intel_atomic_state(crtc_state->uapi.state); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + const struct intel_cdclk_state *cdclk_state = + &state->cdclk_state; if (!crtc_state->hw.enable) return 0; return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, - state->cdclk.logical.cdclk); + cdclk_state->logical.cdclk); } static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) @@ -14772,7 +14778,7 @@ static int intel_atomic_check(struct drm_device *dev, if (ret) goto fail; - any_ms |= state->cdclk.force_min_cdclk_changed; + any_ms |= state->cdclk_state.force_min_cdclk_changed; ret = intel_atomic_check_planes(state, &any_ms); if (ret) @@ -14783,7 +14789,7 @@ static int intel_atomic_check(struct drm_device *dev, if (ret) goto fail; } else { - state->cdclk.logical = dev_priv->cdclk.logical; + state->cdclk_state.logical = dev_priv->cdclk_state.logical; } ret = intel_atomic_check_crtcs(state); @@ -17396,9 +17402,12 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) void intel_modeset_init_hw(struct drm_i915_private *i915) { + struct intel_cdclk_state *cdclk_state = + &i915->cdclk_state; + intel_update_cdclk(i915); intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK"); - i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw; + cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw; } /* @@ -18239,6 +18248,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) for_each_intel_crtc(dev, crtc) { struct intel_bw_state *bw_state = to_intel_bw_state(dev_priv->bw_obj.state); + struct intel_cdclk_state *cdclk_state = + &dev_priv->cdclk_state; struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); struct intel_plane *plane; @@ -18307,8 +18318,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) min_cdclk = 0; } - dev_priv->cdclk.min_cdclk[crtc->pipe] = min_cdclk; - dev_priv->cdclk.min_voltage_level[crtc->pipe] = + cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; + cdclk_state->min_voltage_level[crtc->pipe] = crtc_state->min_voltage_level; intel_bw_crtc_update(bw_state, crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index e2ed7b4d6b41..63b8ca2deb29 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -463,31 +463,7 @@ struct intel_atomic_state { intel_wakeref_t wakeref; - struct { - /* - * Logical configuration of cdclk (used for all scaling, - * watermark, etc. calculations and checks). This is - * computed as if all enabled crtcs were active. - */ - struct intel_cdclk_config logical; - - /* - * Actual configuration of cdclk, can be different from the - * logical configuration only when all crtc's are DPMS off. - */ - struct intel_cdclk_config actual; - - int force_min_cdclk; - bool force_min_cdclk_changed; - - /* minimum acceptable cdclk for each pipe */ - int min_cdclk[I915_MAX_PIPES]; - /* minimum acceptable voltage level for each pipe */ - u8 min_voltage_level[I915_MAX_PIPES]; - - /* pipe to which cd2x update is synchronized */ - enum pipe pipe; - } cdclk; + struct intel_cdclk_state cdclk_state; bool dpll_set, modeset; @@ -515,9 +491,7 @@ struct intel_atomic_state { /* * active_pipes - * min_cdclk[] - * min_voltage_level[] - * cdclk.* + * cdclk_state */ bool global_state_changed; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 17b4a6355fa2..03130c853bd3 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -65,6 +65,7 @@ #include "i915_utils.h" #include "display/intel_bios.h" +#include "display/intel_cdclk.h" #include "display/intel_display.h" #include "display/intel_display_power.h" #include "display/intel_dpll_mgr.h" @@ -881,6 +882,33 @@ struct i915_selftest_stash { atomic_t counter; }; +struct intel_cdclk_state { + /* + * Logical configuration of cdclk (used for all scaling, + * watermark, etc. calculations and checks). This is + * computed as if all enabled crtcs were active. + */ + struct intel_cdclk_config logical; + + /* + * Actual configuration of cdclk, can be different from the + * logical configuration only when all crtc's are DPMS off. + */ + struct intel_cdclk_config actual; + + /* minimum acceptable cdclk for each pipe */ + int min_cdclk[I915_MAX_PIPES]; + /* minimum acceptable voltage level for each pipe */ + u8 min_voltage_level[I915_MAX_PIPES]; + + /* pipe to which cd2x update is synchronized */ + enum pipe pipe; + + /* forced minimum cdclk for glk+ audio w/a */ + int force_min_cdclk; + bool force_min_cdclk_changed; +}; + struct drm_i915_private { struct drm_device drm; @@ -1001,29 +1029,14 @@ struct drm_i915_private { * For reading holding any crtc lock is sufficient, * for writing must hold all of them. */ + struct intel_cdclk_state cdclk_state; + struct { - /* - * The current logical cdclk configuration. - * See intel_atomic_state.cdclk.logical - */ - struct intel_cdclk_config logical; - /* - * The current actual cdclk configuration. - * See intel_atomic_state.cdclk.actual - */ - struct intel_cdclk_config actual; /* The current hardware cdclk configuration */ struct intel_cdclk_config hw; /* cdclk, divider, and ratio table from bspec */ const struct intel_cdclk_vals *table; - - int force_min_cdclk; - - /* minimum acceptable cdclk for each pipe */ - int min_cdclk[I915_MAX_PIPES]; - /* minimum acceptable voltage level for each pipe */ - u8 min_voltage_level[I915_MAX_PIPES]; } cdclk; /** @@ -1080,8 +1093,8 @@ struct drm_i915_private { struct mutex dpll_lock; /* - * For reading active_pipes, min_cdclk, min_voltage_level holding - * any crtc lock is sufficient, for writing must hold all of them. + * For reading active_pipes, cdclk_state holding any crtc + * lock is sufficient, for writing must hold all of them. */ u8 active_pipes; From patchwork Fri Aug 14 06:57:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344662 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ5g4n62z9sTR; Fri, 14 Aug 2020 16:58:15 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1k6TfG-0007gT-56; Fri, 14 Aug 2020 06:58:10 +0000 Received: from mail-pf1-f196.google.com ([209.85.210.196]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1k6TfD-0007c2-3a for kernel-team@lists.ubuntu.com; Fri, 14 Aug 2020 06:58:07 +0000 Received: by mail-pf1-f196.google.com with SMTP id m71so4115554pfd.1 for ; Thu, 13 Aug 2020 23:58:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gOuWBci6hyZEBEL10FXGdk6gU249n9BR2r9VDKOSQwc=; b=L3ZwiKBwL0HcOToChkzOo26QFSgbZiZPxtE61ORu7zozFLI4c0ajwdMmX+FrARZQ+C nXzMK2ljCE3M/JzoQKkwsYsIUWkeiF2yMNQSXc43eEL5Kn3lE8wVRnx0B24qD+XOcASq wxvUNg6uX91W2d/lwyYGTO+bfGpOdywmUI3grEHlhACdEm0h4nr+peapOKxAPpdfEUMZ MkWPehn+ldUJ8WZWG/2sbZ18YVWnsKW3hwevU7nSFx/UQb3JsJjUwhXyylBFFV0f/Ntt QINTToPq/pp2cdN9OFCT89WmcJZATIzcDfdVGg94vqwSMVE1SdAr35YTXIVFAOI7IS/X Iwcw== X-Gm-Message-State: AOAM533DCPtzCuV/7M44wnHm3+EmIxf6XUn9kQ8Snb6dtAY7b+0Wd8of W8m2NWWDLaX29kCt06UDAndRqHzlECEfEw== X-Google-Smtp-Source: ABdhPJwpaV8zsBPu4XQTkBSuR3rYFLe+A1Ktr2/uaKnWJIjC6fP1aYDUcuR5d7UHdCmBk8h0/72yiw== X-Received: by 2002:a63:d62:: with SMTP id 34mr874609pgn.179.1597388283413; Thu, 13 Aug 2020 23:58:03 -0700 (PDT) Received: from localhost (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id e9sm8297614pfh.151.2020.08.13.23.58.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:02 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 07/31][SRU][OEM-5.6] drm/i915: swap() the entire cdclk state Date: Fri, 14 Aug 2020 14:57:16 +0800 Message-Id: <20200814065740.276039-8-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.210.196; envelope-from=vicamo@gmail.com; helo=mail-pf1-f196.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Ville Syrjälä BugLink: https://bugs.launchpad.net/bugs/1891451 To make life less confusing let's swap() the entire cdclk state rather than swapping some parts, copying other parts, and leaving the rest just as is. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200120174728.21095-11-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak (cherry picked from commit 4c029c499fb446d97b85509c151f8564dfe1dcc3) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/display/intel_cdclk.c | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index e219b2fb986c..2a4540d426fd 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1847,19 +1847,7 @@ void intel_cdclk_swap_state(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); - /* FIXME maybe swap() these too */ - memcpy(dev_priv->cdclk_state.min_cdclk, - state->cdclk_state.min_cdclk, - sizeof(state->cdclk_state.min_cdclk)); - memcpy(dev_priv->cdclk_state.min_voltage_level, - state->cdclk_state.min_voltage_level, - sizeof(state->cdclk_state.min_voltage_level)); - - dev_priv->cdclk_state.force_min_cdclk = - state->cdclk_state.force_min_cdclk; - - swap(state->cdclk_state.logical, dev_priv->cdclk_state.logical); - swap(state->cdclk_state.actual, dev_priv->cdclk_state.actual); + swap(state->cdclk_state, dev_priv->cdclk_state); } void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config, @@ -1915,7 +1903,7 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) /* called after intel_cdclk_swap_state()! */ const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state; const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state; - enum pipe pipe = old_cdclk_state->pipe; /* not swapped */ + enum pipe pipe = new_cdclk_state->pipe; if (pipe == INVALID_PIPE || old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) @@ -1936,7 +1924,7 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) /* called after intel_cdclk_swap_state()! */ const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state; const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state; - enum pipe pipe = old_cdclk_state->pipe; /* not swapped */ + enum pipe pipe = new_cdclk_state->pipe; if (pipe != INVALID_PIPE && old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) From patchwork Fri Aug 14 06:57:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344663 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ5k4j7yz9sTH; Fri, 14 Aug 2020 16:58:18 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1k6TfJ-0007j8-V1; Fri, 14 Aug 2020 06:58:14 +0000 Received: from mail-pg1-f195.google.com ([209.85.215.195]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1k6TfE-0007de-0b for kernel-team@lists.ubuntu.com; Fri, 14 Aug 2020 06:58:08 +0000 Received: by mail-pg1-f195.google.com with SMTP id h12so4082037pgm.7 for ; Thu, 13 Aug 2020 23:58:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CFzlwlxdZeHeA893xkc/StWVGHGSHleEmaWvY7Wvw30=; b=jXR4XHN7Sohni8yyi36AUE6cnqFiKCmkoU/Jke3ue0ammQlrSG+zqCCMrskPCRrEpU rthjQCP3S09chgiwVBfEMjQw/q1sUI6PD57PBcdUQuy+dc0i2R02Z0tCIr79g0xEZOqo YRu3FCZwmeO9GmC/lnbKKlC7pSqAciPD1q0UBxj+Z/dfVls72T6+DCIBfpSfjMQTkeM6 vz+MV2ghVbC7EnsY351Us3F5IoYHHdF0OeS7mPeWyx6OLtwOD7UiNBaHiouLNRKGYiW/ 5Jjscj+kgHgPQ8tC+X7IIYDamtAsqzowwbz4l5DBHfRvGBFjNiAngCNECyBy41kq9dmD LcbA== X-Gm-Message-State: AOAM532UMT6TBDT3INNk1Z6GEKElRkMmib6NpUjGlbe/13CZarvUXTt0 ykByj9/hVID2kxHXATESuZs9wkC1pruyqA== X-Google-Smtp-Source: ABdhPJwQGZhGCxbyyoYGVeZnM/EYon6mMc3OxubK+AOa8bjssL/E5ZvsewHnsFv7WcgMhUUAlXN8DA== X-Received: by 2002:aa7:960f:: with SMTP id q15mr882700pfg.79.1597388285794; Thu, 13 Aug 2020 23:58:05 -0700 (PDT) Received: from localhost (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id b63sm7958990pfg.43.2020.08.13.23.58.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:05 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 08/31][SRU][OEM-5.6] drm/i915: s/init_cdclk/init_cdclk_hw/ Date: Fri, 14 Aug 2020 14:57:17 +0800 Message-Id: <20200814065740.276039-9-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.215.195; envelope-from=vicamo@gmail.com; helo=mail-pg1-f195.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Ville Syrjälä BugLink: https://bugs.launchpad.net/bugs/1891451 Give the cdclk init/uninit functions a _hw suffix to make it clear they are about initializing the actual hardware. I'll be wanting to to add a intel_cdclk_init() which is purely initializing software structures. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200120174728.21095-12-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak (cherry picked from commit ed645eee131c89041fde1b10c76396057588bdbd) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/display/intel_cdclk.c | 24 +++++++++---------- drivers/gpu/drm/i915/display/intel_cdclk.h | 4 ++-- .../drm/i915/display/intel_display_power.c | 16 ++++++------- 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 2a4540d426fd..780721af61a0 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1122,7 +1122,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) dev_priv->cdclk.hw.vco = -1; } -static void skl_init_cdclk(struct drm_i915_private *dev_priv) +static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv) { struct intel_cdclk_config cdclk_config; @@ -1151,7 +1151,7 @@ static void skl_init_cdclk(struct drm_i915_private *dev_priv) skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); } -static void skl_uninit_cdclk(struct drm_i915_private *dev_priv) +static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv) { struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw; @@ -1693,7 +1693,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) dev_priv->cdclk.hw.vco = -1; } -static void bxt_init_cdclk(struct drm_i915_private *dev_priv) +static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv) { struct intel_cdclk_config cdclk_config; @@ -1718,7 +1718,7 @@ static void bxt_init_cdclk(struct drm_i915_private *dev_priv) bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); } -static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) +static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) { struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw; @@ -1731,7 +1731,7 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) } /** - * intel_cdclk_init - Initialize CDCLK + * intel_cdclk_init_hw - Initialize CDCLK hardware * @i915: i915 device * * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and @@ -1739,27 +1739,27 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) * during the display core initialization sequence, after which the DMC will * take care of turning CDCLK off/on as needed. */ -void intel_cdclk_init(struct drm_i915_private *i915) +void intel_cdclk_init_hw(struct drm_i915_private *i915) { if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10) - bxt_init_cdclk(i915); + bxt_cdclk_init_hw(i915); else if (IS_GEN9_BC(i915)) - skl_init_cdclk(i915); + skl_cdclk_init_hw(i915); } /** - * intel_cdclk_uninit - Uninitialize CDCLK + * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware * @i915: i915 device * * Uninitialize CDCLK. This is done only during the display core * uninitialization sequence. */ -void intel_cdclk_uninit(struct drm_i915_private *i915) +void intel_cdclk_uninit_hw(struct drm_i915_private *i915) { if (INTEL_GEN(i915) >= 10 || IS_GEN9_LP(i915)) - bxt_uninit_cdclk(i915); + bxt_cdclk_uninit_hw(i915); else if (IS_GEN9_BC(i915)) - skl_uninit_cdclk(i915); + skl_cdclk_uninit_hw(i915); } /** diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index a3fb7b8e8d31..4b965db07720 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -23,8 +23,8 @@ struct intel_cdclk_vals { }; int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state); -void intel_cdclk_init(struct drm_i915_private *i915); -void intel_cdclk_uninit(struct drm_i915_private *i915); +void intel_cdclk_init_hw(struct drm_i915_private *i915); +void intel_cdclk_uninit_hw(struct drm_i915_private *i915); void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv); void intel_update_max_cdclk(struct drm_i915_private *dev_priv); void intel_update_cdclk(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index dec2c94ee51b..4f79065669d7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4827,7 +4827,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv, mutex_unlock(&power_domains->lock); - intel_cdclk_init(dev_priv); + intel_cdclk_init_hw(dev_priv); gen9_dbuf_enable(dev_priv); @@ -4844,7 +4844,7 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv) gen9_dbuf_disable(dev_priv); - intel_cdclk_uninit(dev_priv); + intel_cdclk_uninit_hw(dev_priv); /* The spec doesn't call for removing the reset handshake flag */ /* disable PG1 and Misc I/O */ @@ -4888,7 +4888,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume mutex_unlock(&power_domains->lock); - intel_cdclk_init(dev_priv); + intel_cdclk_init_hw(dev_priv); gen9_dbuf_enable(dev_priv); @@ -4905,7 +4905,7 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv) gen9_dbuf_disable(dev_priv); - intel_cdclk_uninit(dev_priv); + intel_cdclk_uninit_hw(dev_priv); /* The spec doesn't call for removing the reset handshake flag */ @@ -4947,7 +4947,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume mutex_unlock(&power_domains->lock); /* 5. Enable CD clock */ - intel_cdclk_init(dev_priv); + intel_cdclk_init_hw(dev_priv); /* 6. Enable DBUF */ gen9_dbuf_enable(dev_priv); @@ -4969,7 +4969,7 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) gen9_dbuf_disable(dev_priv); /* 3. Disable CD clock */ - intel_cdclk_uninit(dev_priv); + intel_cdclk_uninit_hw(dev_priv); /* * 4. Disable Power Well 1 (PG1). @@ -5074,7 +5074,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, mutex_unlock(&power_domains->lock); /* 4. Enable CDCLK. */ - intel_cdclk_init(dev_priv); + intel_cdclk_init_hw(dev_priv); /* 5. Enable DBUF. */ icl_dbuf_enable(dev_priv); @@ -5103,7 +5103,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv) icl_dbuf_disable(dev_priv); /* 3. Disable CD clock */ - intel_cdclk_uninit(dev_priv); + intel_cdclk_uninit_hw(dev_priv); /* * 4. Disable Power Well 1 (PG1). From patchwork Fri Aug 14 06:57:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344664 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ5n0h0gz9sPB; Fri, 14 Aug 2020 16:58:21 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1k6TfN-0007mP-HV; Fri, 14 Aug 2020 06:58:17 +0000 Received: from mail-pl1-f182.google.com ([209.85.214.182]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1k6TfJ-0007fV-6h for kernel-team@lists.ubuntu.com; Fri, 14 Aug 2020 06:58:13 +0000 Received: by mail-pl1-f182.google.com with SMTP id y6so3765673plt.3 for ; Thu, 13 Aug 2020 23:58:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PLaX5bPqoBoIQ2yfsrjmIpAWXA0ybN+l6Ujk9fwDuuc=; b=eR6MLUA/NL0PowaSyO09Lm+IvIiWAIhWxwIipAM+XsCZcZs1RoZh52sDvJKuqO42yO MpCOvF+KnMiw+fntec/TQE6eBkg0XK1qjHp2kDcEaUA9z0ygqqPSzhKrUosIeqVOYLSQ x7U3ofPOpFOhYtHEOGaAc9wnsPbIUY/CxU+QEBdRdRV/MuZJu28xau41TuKhPgaSV9O/ oRSwvTKEc9lvVdWzbD8370VsVnSgSGDKlTr7RQb1ZrHmHHdFOC+a9mXKsdpLSt8Ct2if qRORqviSaR42T45pYn79HGlvv7vwoB+y3T9ln+E7hnvkB7A7EzbwsnZPVFWkQGCIBQhk VtBQ== X-Gm-Message-State: AOAM533la7RRuhCD/S3tzckkPUX7MRAUl+gR7P9WKZIXS8JKoA3/MsTs hlkiUAvW/PxIy0cxjO3PeXpdJQ6i22Rr/w== X-Google-Smtp-Source: ABdhPJyC87tJygMQ4bb9cwdAPL1ruNE8XPLFWiFyl0577bvWcX/nV1K7bBGFgY4rYaJKKMgaK+FOsA== X-Received: by 2002:a17:902:9009:: with SMTP id a9mr1027396plp.252.1597388288141; Thu, 13 Aug 2020 23:58:08 -0700 (PDT) Received: from localhost (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id m3sm7096834pjs.22.2020.08.13.23.58.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:07 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 09/31][SRU][OEM-5.6] drm/i915: Move intel_atomic_state_free() into intel_atomic.c Date: Fri, 14 Aug 2020 14:57:18 +0800 Message-Id: <20200814065740.276039-10-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.182; envelope-from=vicamo@gmail.com; helo=mail-pl1-f182.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Ville Syrjälä BugLink: https://bugs.launchpad.net/bugs/1891451 Move intel_atomic_state_free() next to its counterpart. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200120174728.21095-13-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak (cherry picked from commit 5f34299384cb70e7d844d3301be783d437dda97b) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/display/intel_atomic.c | 11 +++++++++++ drivers/gpu/drm/i915/display/intel_atomic.h | 1 + drivers/gpu/drm/i915/display/intel_display.c | 11 ----------- 3 files changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c index 1269f63ea006..1c13423d4945 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.c +++ b/drivers/gpu/drm/i915/display/intel_atomic.c @@ -495,6 +495,17 @@ intel_atomic_state_alloc(struct drm_device *dev) return &state->base; } +void intel_atomic_state_free(struct drm_atomic_state *_state) +{ + struct intel_atomic_state *state = to_intel_atomic_state(_state); + + drm_atomic_state_default_release(&state->base); + + i915_sw_fence_fini(&state->commit_ready); + + kfree(state); +} + void intel_atomic_state_clear(struct drm_atomic_state *s) { struct intel_atomic_state *state = to_intel_atomic_state(s); diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h index 74c749dbfb4f..88133eea0a17 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.h +++ b/drivers/gpu/drm/i915/display/intel_atomic.h @@ -45,6 +45,7 @@ void intel_crtc_destroy_state(struct drm_crtc *crtc, void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state); void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state); struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev); +void intel_atomic_state_free(struct drm_atomic_state *state); void intel_atomic_state_clear(struct drm_atomic_state *state); struct intel_crtc_state * diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 4972d5ef45c2..45940fe951b0 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -17160,17 +17160,6 @@ intel_user_framebuffer_create(struct drm_device *dev, return fb; } -static void intel_atomic_state_free(struct drm_atomic_state *state) -{ - struct intel_atomic_state *intel_state = to_intel_atomic_state(state); - - drm_atomic_state_default_release(state); - - i915_sw_fence_fini(&intel_state->commit_ready); - - kfree(state); -} - static enum drm_mode_status intel_mode_valid(struct drm_device *dev, const struct drm_display_mode *mode) From patchwork Fri Aug 14 06:57:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344665 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ5t2kB5z9sPB; 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[61.220.137.37]) by smtp.gmail.com with ESMTPSA id c207sm7875387pfc.64.2020.08.13.23.58.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:10 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 10/31][SRU][OEM-5.6] drm/i915: Introduce better global state handling Date: Fri, 14 Aug 2020 14:57:19 +0800 Message-Id: <20200814065740.276039-11-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.193; envelope-from=vicamo@gmail.com; helo=mail-pl1-f193.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Ville Syrjälä BugLink: https://bugs.launchpad.net/bugs/1891451 Our current global state handling is pretty ad-hoc. Let's try to make it better by imitating the standard drm core private object approach. The reason why we don't want to directly use the private objects is locking; Each private object has its own lock so if we introduce any global private objects we get serialized by that single lock across all pipes. The global state apporoach instead uses a read/write lock type of approach where each individual crtc lock counts as a read lock, and grabbing all the crtc locks allows one write access. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200120174728.21095-15-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak (cherry picked from commit 0ef1905ecf2e0e9b2ff8903ea3150b4dd2faa6c0) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_atomic.c | 7 +- drivers/gpu/drm/i915/display/intel_atomic.h | 4 +- drivers/gpu/drm/i915/display/intel_audio.c | 2 +- drivers/gpu/drm/i915/display/intel_cdclk.c | 8 +- drivers/gpu/drm/i915/display/intel_display.c | 15 +- .../drm/i915/display/intel_display_types.h | 4 + .../gpu/drm/i915/display/intel_global_state.c | 223 ++++++++++++++++++ .../gpu/drm/i915/display/intel_global_state.h | 87 +++++++ drivers/gpu/drm/i915/i915_drv.h | 3 + 10 files changed, 342 insertions(+), 12 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_global_state.c create mode 100644 drivers/gpu/drm/i915/display/intel_global_state.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index a1f2411aa21b..c645211cb2dc 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -187,6 +187,7 @@ i915-y += \ display/intel_fbc.o \ display/intel_fifo_underrun.o \ display/intel_frontbuffer.o \ + display/intel_global_state.o \ display/intel_hdcp.o \ display/intel_hotplug.o \ display/intel_lpe_audio.o \ diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c index 1c13423d4945..45842ebcdebd 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.c +++ b/drivers/gpu/drm/i915/display/intel_atomic.c @@ -37,6 +37,7 @@ #include "intel_atomic.h" #include "intel_cdclk.h" #include "intel_display_types.h" +#include "intel_global_state.h" #include "intel_hdcp.h" #include "intel_psr.h" #include "intel_sprite.h" @@ -500,6 +501,7 @@ void intel_atomic_state_free(struct drm_atomic_state *_state) struct intel_atomic_state *state = to_intel_atomic_state(_state); drm_atomic_state_default_release(&state->base); + kfree(state->global_objs); i915_sw_fence_fini(&state->commit_ready); @@ -511,6 +513,7 @@ void intel_atomic_state_clear(struct drm_atomic_state *s) struct intel_atomic_state *state = to_intel_atomic_state(s); drm_atomic_state_default_clear(&state->base); + intel_atomic_clear_global_state(state); state->dpll_set = state->modeset = false; state->global_state_changed = false; @@ -530,7 +533,7 @@ intel_atomic_get_crtc_state(struct drm_atomic_state *state, return to_intel_crtc_state(crtc_state); } -int intel_atomic_lock_global_state(struct intel_atomic_state *state) +int _intel_atomic_lock_global_state(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc *crtc; @@ -549,7 +552,7 @@ int intel_atomic_lock_global_state(struct intel_atomic_state *state) return 0; } -int intel_atomic_serialize_global_state(struct intel_atomic_state *state) +int _intel_atomic_serialize_global_state(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc *crtc; diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h index 88133eea0a17..11146292b06f 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.h +++ b/drivers/gpu/drm/i915/display/intel_atomic.h @@ -56,8 +56,8 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state); -int intel_atomic_lock_global_state(struct intel_atomic_state *state); +int _intel_atomic_lock_global_state(struct intel_atomic_state *state); -int intel_atomic_serialize_global_state(struct intel_atomic_state *state); +int _intel_atomic_serialize_global_state(struct intel_atomic_state *state); #endif /* __INTEL_ATOMIC_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index c16ec35a90d4..ff9e5ae44996 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -828,7 +828,7 @@ static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv, enable ? 2 * 96000 : 0; /* Protects dev_priv->cdclk.force_min_cdclk */ - ret = intel_atomic_lock_global_state(to_intel_atomic_state(state)); + ret = _intel_atomic_lock_global_state(to_intel_atomic_state(state)); if (!ret) ret = drm_atomic_commit(state); diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 780721af61a0..744c98f2b501 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2075,7 +2075,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state) cdclk_state->min_cdclk[i] = min_cdclk; - ret = intel_atomic_lock_global_state(state); + ret = _intel_atomic_lock_global_state(state); if (ret) return ret; } @@ -2123,7 +2123,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) cdclk_state->min_voltage_level[i] = min_voltage_level; - ret = intel_atomic_lock_global_state(state); + ret = _intel_atomic_lock_global_state(state); if (ret) return ret; } @@ -2398,12 +2398,12 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) * Also serialize commits across all crtcs * if the actual hw needs to be poked. */ - ret = intel_atomic_serialize_global_state(state); + ret = _intel_atomic_serialize_global_state(state); if (ret) return ret; } else if (intel_cdclk_changed(&old_cdclk_state->logical, &new_cdclk_state->logical)) { - ret = intel_atomic_lock_global_state(state); + ret = _intel_atomic_lock_global_state(state); if (ret) return ret; } else { diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 45940fe951b0..854f68c32ddf 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -14397,7 +14397,7 @@ static int intel_modeset_checks(struct intel_atomic_state *state) } if (state->active_pipe_changes) { - ret = intel_atomic_lock_global_state(state); + ret = _intel_atomic_lock_global_state(state); if (ret) return ret; } @@ -15696,6 +15696,8 @@ static int intel_atomic_commit(struct drm_device *dev, ret = drm_atomic_helper_setup_commit(&state->base, nonblock); if (!ret) ret = drm_atomic_helper_swap_state(&state->base, true); + if (!ret) + intel_atomic_swap_global_state(state); if (ret) { i915_sw_fence_commit(&state->commit_ready); @@ -17580,6 +17582,7 @@ static void intel_mode_config_init(struct drm_i915_private *i915) struct drm_mode_config *mode_config = &i915->drm.mode_config; drm_mode_config_init(&i915->drm); + INIT_LIST_HEAD(&i915->global_obj_list); mode_config->min_width = 0; mode_config->min_height = 0; @@ -17621,6 +17624,12 @@ static void intel_mode_config_init(struct drm_i915_private *i915) } } +static void intel_mode_config_cleanup(struct drm_i915_private *i915) +{ + intel_atomic_global_obj_cleanup(i915); + drm_mode_config_cleanup(&i915->drm); +} + int intel_modeset_init(struct drm_i915_private *i915) { struct drm_device *dev = &i915->drm; @@ -17660,7 +17669,7 @@ int intel_modeset_init(struct drm_i915_private *i915) for_each_pipe(i915, pipe) { ret = intel_crtc_init(i915, pipe); if (ret) { - drm_mode_config_cleanup(dev); + intel_mode_config_cleanup(i915); return ret; } } @@ -18613,7 +18622,7 @@ void intel_modeset_driver_remove(struct drm_i915_private *i915) intel_hdcp_component_fini(i915); - drm_mode_config_cleanup(&i915->drm); + intel_mode_config_cleanup(i915); intel_overlay_cleanup(i915); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 63b8ca2deb29..fa3c29e8a7f5 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -46,6 +46,7 @@ #include "i915_drv.h" struct drm_printer; +struct __intel_global_objs_state; /* * Display related stuff @@ -463,6 +464,9 @@ struct intel_atomic_state { intel_wakeref_t wakeref; + struct __intel_global_objs_state *global_objs; + int num_global_objs; + struct intel_cdclk_state cdclk_state; bool dpll_set, modeset; diff --git a/drivers/gpu/drm/i915/display/intel_global_state.c b/drivers/gpu/drm/i915/display/intel_global_state.c new file mode 100644 index 000000000000..a0cc894c3868 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_global_state.c @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2020 Intel Corporation + */ + +#include + +#include "i915_drv.h" +#include "intel_atomic.h" +#include "intel_display_types.h" +#include "intel_global_state.h" + +void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv, + struct intel_global_obj *obj, + struct intel_global_state *state, + const struct intel_global_state_funcs *funcs) +{ + memset(obj, 0, sizeof(*obj)); + + obj->state = state; + obj->funcs = funcs; + list_add_tail(&obj->head, &dev_priv->global_obj_list); +} + +void intel_atomic_global_obj_cleanup(struct drm_i915_private *dev_priv) +{ + struct intel_global_obj *obj, *next; + + list_for_each_entry_safe(obj, next, &dev_priv->global_obj_list, head) { + list_del(&obj->head); + obj->funcs->atomic_destroy_state(obj, obj->state); + } +} + +static void assert_global_state_write_locked(struct drm_i915_private *dev_priv) +{ + struct intel_crtc *crtc; + + for_each_intel_crtc(&dev_priv->drm, crtc) + drm_modeset_lock_assert_held(&crtc->base.mutex); +} + +static bool modeset_lock_is_held(struct drm_modeset_acquire_ctx *ctx, + struct drm_modeset_lock *lock) +{ + struct drm_modeset_lock *l; + + list_for_each_entry(l, &ctx->locked, head) { + if (lock == l) + return true; + } + + return false; +} + +static void assert_global_state_read_locked(struct intel_atomic_state *state) +{ + struct drm_modeset_acquire_ctx *ctx = state->base.acquire_ctx; + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_crtc *crtc; + + for_each_intel_crtc(&dev_priv->drm, crtc) { + if (modeset_lock_is_held(ctx, &crtc->base.mutex)) + return; + } + + WARN(1, "Global state not read locked\n"); +} + +struct intel_global_state * +intel_atomic_get_global_obj_state(struct intel_atomic_state *state, + struct intel_global_obj *obj) +{ + int index, num_objs, i; + size_t size; + struct __intel_global_objs_state *arr; + struct intel_global_state *obj_state; + + for (i = 0; i < state->num_global_objs; i++) + if (obj == state->global_objs[i].ptr) + return state->global_objs[i].state; + + assert_global_state_read_locked(state); + + num_objs = state->num_global_objs + 1; + size = sizeof(*state->global_objs) * num_objs; + arr = krealloc(state->global_objs, size, GFP_KERNEL); + if (!arr) + return ERR_PTR(-ENOMEM); + + state->global_objs = arr; + index = state->num_global_objs; + memset(&state->global_objs[index], 0, sizeof(*state->global_objs)); + + obj_state = obj->funcs->atomic_duplicate_state(obj); + if (!obj_state) + return ERR_PTR(-ENOMEM); + + obj_state->changed = false; + + state->global_objs[index].state = obj_state; + state->global_objs[index].old_state = obj->state; + state->global_objs[index].new_state = obj_state; + state->global_objs[index].ptr = obj; + obj_state->state = state; + + state->num_global_objs = num_objs; + + DRM_DEBUG_ATOMIC("Added new global object %p state %p to %p\n", + obj, obj_state, state); + + return obj_state; +} + +struct intel_global_state * +intel_atomic_get_old_global_obj_state(struct intel_atomic_state *state, + struct intel_global_obj *obj) +{ + int i; + + for (i = 0; i < state->num_global_objs; i++) + if (obj == state->global_objs[i].ptr) + return state->global_objs[i].old_state; + + return NULL; +} + +struct intel_global_state * +intel_atomic_get_new_global_obj_state(struct intel_atomic_state *state, + struct intel_global_obj *obj) +{ + int i; + + for (i = 0; i < state->num_global_objs; i++) + if (obj == state->global_objs[i].ptr) + return state->global_objs[i].new_state; + + return NULL; +} + +void intel_atomic_swap_global_state(struct intel_atomic_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_global_state *old_obj_state, *new_obj_state; + struct intel_global_obj *obj; + int i; + + for_each_oldnew_global_obj_in_state(state, obj, old_obj_state, + new_obj_state, i) { + WARN_ON(obj->state != old_obj_state); + + /* + * If the new state wasn't modified (and properly + * locked for write access) we throw it away. + */ + if (!new_obj_state->changed) + continue; + + assert_global_state_write_locked(dev_priv); + + old_obj_state->state = state; + new_obj_state->state = NULL; + + state->global_objs[i].state = old_obj_state; + obj->state = new_obj_state; + } +} + +void intel_atomic_clear_global_state(struct intel_atomic_state *state) +{ + int i; + + for (i = 0; i < state->num_global_objs; i++) { + struct intel_global_obj *obj = state->global_objs[i].ptr; + + obj->funcs->atomic_destroy_state(obj, + state->global_objs[i].state); + state->global_objs[i].ptr = NULL; + state->global_objs[i].state = NULL; + state->global_objs[i].old_state = NULL; + state->global_objs[i].new_state = NULL; + } + state->num_global_objs = 0; +} + +int intel_atomic_lock_global_state(struct intel_global_state *obj_state) +{ + struct intel_atomic_state *state = obj_state->state; + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_crtc *crtc; + + for_each_intel_crtc(&dev_priv->drm, crtc) { + int ret; + + ret = drm_modeset_lock(&crtc->base.mutex, + state->base.acquire_ctx); + if (ret) + return ret; + } + + obj_state->changed = true; + + return 0; +} + +int intel_atomic_serialize_global_state(struct intel_global_state *obj_state) +{ + struct intel_atomic_state *state = obj_state->state; + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_crtc *crtc; + + for_each_intel_crtc(&dev_priv->drm, crtc) { + struct intel_crtc_state *crtc_state; + + crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + } + + obj_state->changed = true; + + return 0; +} diff --git a/drivers/gpu/drm/i915/display/intel_global_state.h b/drivers/gpu/drm/i915/display/intel_global_state.h new file mode 100644 index 000000000000..e6163a469029 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_global_state.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2020 Intel Corporation + */ + +#ifndef __INTEL_GLOBAL_STATE_H__ +#define __INTEL_GLOBAL_STATE_H__ + +#include + +struct drm_i915_private; +struct intel_atomic_state; +struct intel_global_obj; +struct intel_global_state; + +struct intel_global_state_funcs { + struct intel_global_state *(*atomic_duplicate_state)(struct intel_global_obj *obj); + void (*atomic_destroy_state)(struct intel_global_obj *obj, + struct intel_global_state *state); +}; + +struct intel_global_obj { + struct list_head head; + struct intel_global_state *state; + const struct intel_global_state_funcs *funcs; +}; + +#define intel_for_each_global_obj(obj, dev_priv) \ + list_for_each_entry(obj, &(dev_priv)->global_obj_list, head) + +#define for_each_new_global_obj_in_state(__state, obj, new_obj_state, __i) \ + for ((__i) = 0; \ + (__i) < (__state)->num_global_objs && \ + ((obj) = (__state)->global_objs[__i].ptr, \ + (new_obj_state) = (__state)->global_objs[__i].new_state, 1); \ + (__i)++) \ + for_each_if(obj) + +#define for_each_old_global_obj_in_state(__state, obj, new_obj_state, __i) \ + for ((__i) = 0; \ + (__i) < (__state)->num_global_objs && \ + ((obj) = (__state)->global_objs[__i].ptr, \ + (new_obj_state) = (__state)->global_objs[__i].old_state, 1); \ + (__i)++) \ + for_each_if(obj) + +#define for_each_oldnew_global_obj_in_state(__state, obj, old_obj_state, new_obj_state, __i) \ + for ((__i) = 0; \ + (__i) < (__state)->num_global_objs && \ + ((obj) = (__state)->global_objs[__i].ptr, \ + (old_obj_state) = (__state)->global_objs[__i].old_state, \ + (new_obj_state) = (__state)->global_objs[__i].new_state, 1); \ + (__i)++) \ + for_each_if(obj) + +struct intel_global_state { + struct intel_atomic_state *state; + bool changed; +}; + +struct __intel_global_objs_state { + struct intel_global_obj *ptr; + struct intel_global_state *state, *old_state, *new_state; +}; + +void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv, + struct intel_global_obj *obj, + struct intel_global_state *state, + const struct intel_global_state_funcs *funcs); +void intel_atomic_global_obj_cleanup(struct drm_i915_private *dev_priv); + +struct intel_global_state * +intel_atomic_get_global_obj_state(struct intel_atomic_state *state, + struct intel_global_obj *obj); +struct intel_global_state * +intel_atomic_get_old_global_obj_state(struct intel_atomic_state *state, + struct intel_global_obj *obj); +struct intel_global_state * +intel_atomic_get_new_global_obj_state(struct intel_atomic_state *state, + struct intel_global_obj *obj); + +void intel_atomic_swap_global_state(struct intel_atomic_state *state); +void intel_atomic_clear_global_state(struct intel_atomic_state *state); +int intel_atomic_lock_global_state(struct intel_global_state *obj_state); +int intel_atomic_serialize_global_state(struct intel_global_state *obj_state); + +#endif diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 03130c853bd3..e2129a740003 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -71,6 +71,7 @@ #include "display/intel_dpll_mgr.h" #include "display/intel_dsb.h" #include "display/intel_frontbuffer.h" +#include "display/intel_global_state.h" #include "display/intel_gmbus.h" #include "display/intel_opregion.h" @@ -1092,6 +1093,8 @@ struct drm_i915_private { */ struct mutex dpll_lock; + struct list_head global_obj_list; + /* * For reading active_pipes, cdclk_state holding any crtc * lock is sufficient, for writing must hold all of them. From patchwork Fri Aug 14 06:57:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344666 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ5w43jmz9sTM; Fri, 14 Aug 2020 16:58:28 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1k6TfU-0007s1-Bw; Fri, 14 Aug 2020 06:58:24 +0000 Received: from mail-pl1-f195.google.com ([209.85.214.195]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1k6TfP-0007jt-Av for kernel-team@lists.ubuntu.com; Fri, 14 Aug 2020 06:58:19 +0000 Received: by mail-pl1-f195.google.com with SMTP id t10so3749313plz.10 for ; Thu, 13 Aug 2020 23:58:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aHjybGltDAFbbbktj6HIsXuqBrOT+BDx6yjLPHaVpbU=; b=H7CLDybalDfj3AZ1SKNtHW7RIXGSGAKcZrD4iUGw7srFgu/dwCr2iO64BgDLENmEo3 C7XDnezOSGUPj37dhc6Pa3Az0FusgsgM7f4kOIHqGT6UOwmW0D8nhH9e3KTEr+zTwwQq 6UHiMyugL4HRk039bhQs1r7xc42Zg4TaKSQcCESVZbF/DWMbYn9YnWa7IUy9/oxDChxW QTCXN5TEebgsiC34QQyUNk/6UMkVwdsubVr9F0+ZFzze1ZmLMMBO1HGiatR4OtpC4Bht cgLADDMHGddDkPq2iRzazHSd5izXK12U/lyrwJzbTukXZQGk/ToqzcLwrHS+pjhPiC/P dshw== X-Gm-Message-State: AOAM531kez/9zKXd28ip384EJgvqdzGkk+KwUhXMMK8ph59YGxrSUXk1 U/7LmWD5Vc1qGZFsaGA65rj3yUM2EE6HCg== X-Google-Smtp-Source: ABdhPJzUoCv/wKcit8GeiWhxQTSQcdPpakyqzwPRuOc2L+DhNpeDeoQv51CwA16XCxPBSCyiks906A== X-Received: by 2002:a17:902:6bc2:: with SMTP id m2mr1062351plt.114.1597388293354; Thu, 13 Aug 2020 23:58:13 -0700 (PDT) Received: from localhost (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id 8sm7320309pjx.14.2020.08.13.23.58.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:12 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 11/31][SRU][OEM-5.6] drm/i915: Convert bandwidth state to global state Date: Fri, 14 Aug 2020 14:57:20 +0800 Message-Id: <20200814065740.276039-12-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.195; envelope-from=vicamo@gmail.com; helo=mail-pl1-f195.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Ville Syrjälä BugLink: https://bugs.launchpad.net/bugs/1891451 Now that we have the more formal global state thing let's use if for memory bandwidth tracking. No real difference to the current private object usage since we already tried to avoid taking the single serializing lock needlessly. But since we're going to roll the global state out to more things probably a good idea to unify the approaches a bit. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200120174728.21095-16-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak (cherry picked from commit fd1a9bba73fa10e1601a43264283fe4696d6f82c) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/display/intel_bw.c | 31 +++++++++----------- drivers/gpu/drm/i915/display/intel_bw.h | 4 +-- drivers/gpu/drm/i915/display/intel_display.c | 2 -- drivers/gpu/drm/i915/i915_drv.h | 2 +- 4 files changed, 17 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index b228671d5a5d..316abcf3e6a2 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -374,10 +374,9 @@ static struct intel_bw_state * intel_atomic_get_bw_state(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); - struct drm_private_state *bw_state; + struct intel_global_state *bw_state; - bw_state = drm_atomic_get_private_obj_state(&state->base, - &dev_priv->bw_obj); + bw_state = intel_atomic_get_global_obj_state(state, &dev_priv->bw_obj); if (IS_ERR(bw_state)) return ERR_CAST(bw_state); @@ -392,7 +391,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state) unsigned int data_rate, max_data_rate; unsigned int num_active_planes; struct intel_crtc *crtc; - int i; + int i, ret; /* FIXME earlier gens need some checks too */ if (INTEL_GEN(dev_priv) < 11) @@ -433,6 +432,10 @@ int intel_bw_atomic_check(struct intel_atomic_state *state) if (!bw_state) return 0; + ret = intel_atomic_lock_global_state(&bw_state->base); + if (ret) + return ret; + data_rate = intel_bw_data_rate(dev_priv, bw_state); num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state); @@ -449,7 +452,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state) return 0; } -static struct drm_private_state *intel_bw_duplicate_state(struct drm_private_obj *obj) +static struct intel_global_state * +intel_bw_duplicate_state(struct intel_global_obj *obj) { struct intel_bw_state *state; @@ -457,18 +461,16 @@ static struct drm_private_state *intel_bw_duplicate_state(struct drm_private_obj if (!state) return NULL; - __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); - return &state->base; } -static void intel_bw_destroy_state(struct drm_private_obj *obj, - struct drm_private_state *state) +static void intel_bw_destroy_state(struct intel_global_obj *obj, + struct intel_global_state *state) { kfree(state); } -static const struct drm_private_state_funcs intel_bw_funcs = { +static const struct intel_global_state_funcs intel_bw_funcs = { .atomic_duplicate_state = intel_bw_duplicate_state, .atomic_destroy_state = intel_bw_destroy_state, }; @@ -481,13 +483,8 @@ int intel_bw_init(struct drm_i915_private *dev_priv) if (!state) return -ENOMEM; - drm_atomic_private_obj_init(&dev_priv->drm, &dev_priv->bw_obj, - &state->base, &intel_bw_funcs); + intel_atomic_global_obj_init(dev_priv, &dev_priv->bw_obj, + &state->base, &intel_bw_funcs); return 0; } - -void intel_bw_cleanup(struct drm_i915_private *dev_priv) -{ - drm_atomic_private_obj_fini(&dev_priv->bw_obj); -} diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h index 20b9ad241802..a8aa7624c5aa 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.h +++ b/drivers/gpu/drm/i915/display/intel_bw.h @@ -9,13 +9,14 @@ #include #include "intel_display.h" +#include "intel_global_state.h" struct drm_i915_private; struct intel_atomic_state; struct intel_crtc_state; struct intel_bw_state { - struct drm_private_state base; + struct intel_global_state base; unsigned int data_rate[I915_MAX_PIPES]; u8 num_active_planes[I915_MAX_PIPES]; @@ -25,7 +26,6 @@ struct intel_bw_state { void intel_bw_init_hw(struct drm_i915_private *dev_priv); int intel_bw_init(struct drm_i915_private *dev_priv); -void intel_bw_cleanup(struct drm_i915_private *dev_priv); int intel_bw_atomic_check(struct intel_atomic_state *state); void intel_bw_crtc_update(struct intel_bw_state *bw_state, const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 854f68c32ddf..8ca2d3f7c99b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -18628,8 +18628,6 @@ void intel_modeset_driver_remove(struct drm_i915_private *i915) intel_gmbus_teardown(i915); - intel_bw_cleanup(i915); - destroy_workqueue(i915->flip_wq); destroy_workqueue(i915->modeset_wq); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e2129a740003..a0556a448083 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1244,7 +1244,7 @@ struct drm_i915_private { u8 num_planes; } max_bw[6]; - struct drm_private_obj bw_obj; + struct intel_global_obj bw_obj; struct intel_runtime_pm runtime_pm; From patchwork Fri Aug 14 06:57:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344667 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; 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[61.220.137.37]) by smtp.gmail.com with ESMTPSA id t25sm8449778pfl.198.2020.08.13.23.58.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:14 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 12/31][SRU][OEM-5.6] drm/i915: Introduce intel_calc_active_pipes() Date: Fri, 14 Aug 2020 14:57:21 +0800 Message-Id: <20200814065740.276039-13-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.215.195; envelope-from=vicamo@gmail.com; helo=mail-pg1-f195.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Ville Syrjälä BugLink: https://bugs.launchpad.net/bugs/1891451 Extract a small helper to compute the active pipes bitmask based on the old bitmask + the crtcs in the atomic state. I want to decouple the cdclk state entirely from the current global state so I want to track the active pipes also inside the (to be introduced) full cdclk state. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200120174728.21095-17-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak (cherry picked from commit aac978718bb480fee1b4a577727c0c06e7ae65db) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/display/intel_display.c | 34 ++++++++++++-------- drivers/gpu/drm/i915/display/intel_display.h | 3 ++ 2 files changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 8ca2d3f7c99b..ebafe88572ba 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -14375,26 +14375,32 @@ static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) return 0; } +u8 intel_calc_active_pipes(struct intel_atomic_state *state, + u8 active_pipes) +{ + const struct intel_crtc_state *crtc_state; + struct intel_crtc *crtc; + int i; + + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { + if (crtc_state->hw.active) + active_pipes |= BIT(crtc->pipe); + else + active_pipes &= ~BIT(crtc->pipe); + } + + return active_pipes; +} + static int intel_modeset_checks(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); - struct intel_crtc_state *old_crtc_state, *new_crtc_state; - struct intel_crtc *crtc; - int ret, i; + int ret; state->modeset = true; - state->active_pipes = dev_priv->active_pipes; + state->active_pipes = intel_calc_active_pipes(state, dev_priv->active_pipes); - for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, - new_crtc_state, i) { - if (new_crtc_state->hw.active) - state->active_pipes |= BIT(crtc->pipe); - else - state->active_pipes &= ~BIT(crtc->pipe); - - if (old_crtc_state->hw.active != new_crtc_state->hw.active) - state->active_pipe_changes |= BIT(crtc->pipe); - } + state->active_pipe_changes = state->active_pipes ^ dev_priv->active_pipes; if (state->active_pipe_changes) { ret = _intel_atomic_lock_global_state(state); diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index dd1215106d4a..1bd7b4cc3227 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -44,6 +44,7 @@ struct drm_modeset_acquire_ctx; struct drm_plane; struct drm_plane_state; struct i915_ggtt_view; +struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; struct intel_digital_port; @@ -469,6 +470,8 @@ enum phy_fia { ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \ (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1)) +u8 intel_calc_active_pipes(struct intel_atomic_state *state, + u8 active_pipes); void intel_link_compute_m_n(u16 bpp, int nlanes, int pixel_clock, int link_clock, struct intel_link_m_n *m_n, From patchwork Fri Aug 14 06:57:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344669 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; 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[61.220.137.37]) by smtp.gmail.com with ESMTPSA id i14sm7094974pjz.25.2020.08.13.23.58.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:17 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 13/31][SRU][OEM-5.6] drm/i915: Don't check uv_wm in skl_plane_wm_equals() Date: Fri, 14 Aug 2020 14:57:22 +0800 Message-Id: <20200814065740.276039-14-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.210.196; envelope-from=vicamo@gmail.com; helo=mail-pf1-f196.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Ville Syrjälä BugLink: https://bugs.launchpad.net/bugs/1891451 The hardware never sees the uv_wm values (apart from uv_wm.min_ddb_alloc affecting the ddb allocation). Thus there is no point in comparing uv_wm to determine if we need to reprogram the watermark registers. So let's check only the rgb/y watermark in skl_plane_wm_equals(). But let's leave a comment behind so that the next person reading this doesn't get as confused as I did when I added this check. If the ddb allocation ends up changing due to uv_wm skl_ddb_add_affected_planes() takes care of adding the plane to the state. TODO: we should perhaps just eliminate uv_wm from the state and simply track the min_ddb_alloc for uv instead. Cc: Matt Roper Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200228203552.30273-1-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza (cherry picked from commit e7f54e6c198159ff593f1d52707d40a82899cfc7) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/intel_pm.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 5eba87c55d54..d25726666177 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5407,8 +5407,12 @@ static bool skl_plane_wm_equals(struct drm_i915_private *dev_priv, int level, max_level = ilk_wm_max_level(dev_priv); for (level = 0; level <= max_level; level++) { - if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level]) || - !skl_wm_level_equals(&wm1->uv_wm[level], &wm2->uv_wm[level])) + /* + * We don't check uv_wm as the hardware doesn't actually + * use it. It only gets used for calculating the required + * ddb allocation. + */ + if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level])) return false; } From patchwork Fri Aug 14 06:57:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344668 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ630ZTnz9sTN; Fri, 14 Aug 2020 16:58:35 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1k6Tfa-0007xh-KH; Fri, 14 Aug 2020 06:58:30 +0000 Received: from mail-pg1-f173.google.com ([209.85.215.173]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1k6TfW-0007qC-5v for kernel-team@lists.ubuntu.com; Fri, 14 Aug 2020 06:58:26 +0000 Received: by mail-pg1-f173.google.com with SMTP id t6so4096067pgq.1 for ; Thu, 13 Aug 2020 23:58:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y8AtkVooBPezhJmlqAj1GncygOGpW/j+ct6cBy5GcHc=; b=eoAWvfY3yytfdsmgr1fS/7uEFyVKOdaml8GJOAeAI356r0obKuZFCGT7k4lyvdaVU0 l1FhQVD++mLS/ldMd0E6qYL59sMHI2LUE83dKa2G38mzhmGqWl2YDCkbiiX5vhFIRInT 18ARfjl5dFpcfY84NtIyqOfRyEtAeeskSXmtylUrOvGDkxx/5rNwQN8oMMRYNtva3brU 1ngQ6/IQLTqDMfo2xRQHt6OkdZCMshUpjv9+UXR286Q666nXYWJj5lUQFqi08tabn7GH znz/LfXaRekJ/UYmZy9Kc6/PK7Zi7xXGf+MccerBwZ8ke2h6JGPHn6F96ErCdufq7hzW r1zQ== X-Gm-Message-State: AOAM532RY3iLtRUORoREFpB9D1nNeWLJrsZzVof9j9bWPAnEprhQXLS4 siOa2Q0wtx+4U24M+USkAOYa4ncWhAyvIA== X-Google-Smtp-Source: ABdhPJzjkVKl7tFJ0BHkfbx4jYV531xp3HWIBWUldhKFBHuOuQ62QxtLwRgCCg7P8d73I25rqFW3Og== X-Received: by 2002:a63:2584:: with SMTP id l126mr876493pgl.126.1597388300836; Thu, 13 Aug 2020 23:58:20 -0700 (PDT) Received: from localhost (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id o10sm7025268pjo.55.2020.08.13.23.58.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:20 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 14/31][SRU][OEM-5.6] drm/i915: Don't check for wm changes until we've compute the wms fully Date: Fri, 14 Aug 2020 14:57:23 +0800 Message-Id: <20200814065740.276039-15-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.215.173; envelope-from=vicamo@gmail.com; helo=mail-pg1-f173.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Ville Syrjälä BugLink: https://bugs.launchpad.net/bugs/1891451 Currently we're comparing the watermarks between the old and new states before we've fully computed the new watermarks. In particular skl_build_pipe_wm() will not account for the amount of ddb space we'll have. That information is only available during skl_compute_ddb() which will proceed to zero out any watermark level exceeding the ddb allocation. If we're short on ddb space this will end up adding the plane to the state due erronously determining that the watermarks have changed. Fix the problem by deferring skl_wm_add_affected_planes() until we have the final watermarks computed. Noticed this when trying enable transition watermarks on glk. We now computed the trans_wm as 28, but we only had 14 blocks of ddb, and thus skl_compute_ddb() ended up disabling the cursor trans_wm every time. Thus we ended up adding the cursor to every commit that didn't actually affect the cursor at all. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200228203552.30273-2-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza (cherry picked from commit 23baedd217effd594bdf4620c1fea4d27febe090) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d25726666177..e5460b470f1f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5769,16 +5769,24 @@ skl_compute_wm(struct intel_atomic_state *state) ret = skl_build_pipe_wm(new_crtc_state); if (ret) return ret; - - ret = skl_wm_add_affected_planes(state, crtc); - if (ret) - return ret; } ret = skl_compute_ddb(state); if (ret) return ret; + /* + * skl_compute_ddb() will have adjusted the final watermarks + * based on how much ddb is available. Now we can actually + * check if the final watermarks changed. + */ + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) { + ret = skl_wm_add_affected_planes(state, crtc); + if (ret) + return ret; + } + skl_print_wm_changes(state); return 0; From patchwork Fri Aug 14 06:57:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344670 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ6C2pLVz9sPB; Fri, 14 Aug 2020 16:58:43 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1k6Tfj-000850-2K; Fri, 14 Aug 2020 06:58:39 +0000 Received: from mail-pf1-f194.google.com ([209.85.210.194]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1k6Tfd-0007st-7f for kernel-team@lists.ubuntu.com; Fri, 14 Aug 2020 06:58:33 +0000 Received: by mail-pf1-f194.google.com with SMTP id a79so4100132pfa.8 for ; Thu, 13 Aug 2020 23:58:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2suK/vY+UUpLXxyeMCYqVvBXBtpEj+RkHDXRKzJI38g=; b=VTPhZHn3JAu8WOf3ctiswZYcPQ6JTIiZd3uPlq/WNHcxTbqYsz6hO4aBpwC+GEsUvR FjgQPP89yTVu5PPqY097wroaUqtoepdjRYRmqEHBzimXfT9CQoRAO2YNphKRswbfIxZZ rETl9lAQpQky+om6zsjxqY8c65Q/44/uRdExBtBkBL0sdOGVhJQChVZRUON34BfWPK3v NiAsgNozjhTv0u7FaqpPOuUj0fIE5tnWs+6MeGtEU46DKbLTauxk3eQaBahZZ3XFtAQC jSrZ2WkKr6AomiaglL7j0oGlAPaw7gEZdtWspFrrkKCTegJ3ibi1qudeDdAi57ozlOZ0 AeQQ== X-Gm-Message-State: AOAM531CV7NCpKhHGHWhMaqDuKAjHwuKrF6fUM/B6NkkjOoFpfET7fvW G56mOOSdjSIVLaUIrAhHSDa/voTfnbFTDg== X-Google-Smtp-Source: ABdhPJx3g2Z0P+iLzBFkuQ1LVlWLt27KAC6UgLbqIycabLb/pS0FOZ5py+XC/yF2jOzU9iPACBjbpA== X-Received: by 2002:a65:538d:: with SMTP id x13mr885727pgq.33.1597388303601; Thu, 13 Aug 2020 23:58:23 -0700 (PDT) Received: from localhost (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id j142sm8306887pfd.100.2020.08.13.23.58.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:22 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 15/31][SRU][OEM-5.6] drm/i915: Enable transition watermarks for glk Date: Fri, 14 Aug 2020 14:57:24 +0800 Message-Id: <20200814065740.276039-16-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.210.194; envelope-from=vicamo@gmail.com; helo=mail-pf1-f194.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Ville Syrjälä BugLink: https://bugs.launchpad.net/bugs/1891451 We are mistakenly skipping transition watermarks on glk. Fix up the condition for glk, and toss in the w/a name from the database. v2: Reorder the ipc enabled vs. platform check to be more sensible Signed-off-by: Ville Syrjälä Reviewed-by: Rodrigo Vivi #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20200228203552.30273-3-ville.syrjala@linux.intel.com (cherry picked from commit a7f1e8e45f21a0c8e966a8678fe0391f4196b178) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/intel_pm.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e5460b470f1f..29137201e20a 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5128,14 +5128,17 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state, const u16 trans_amount = 10; /* This is configurable amount */ u16 wm0_sel_res_b, trans_offset_b, res_blocks; - /* Transition WM are not recommended by HW team for GEN9 */ - if (INTEL_GEN(dev_priv) <= 9) - return; - /* Transition WM don't make any sense if ipc is disabled */ if (!dev_priv->ipc_enabled) return; + /* + * WaDisableTWM:skl,kbl,cfl,bxt + * Transition WM are not recommended by HW team for GEN9 + */ + if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) + return; + trans_min = 14; if (INTEL_GEN(dev_priv) >= 11) trans_min = 4; From patchwork Fri Aug 14 06:57:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344671 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ6G4jQhz9sTH; Fri, 14 Aug 2020 16:58:46 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1k6Tfl-00086o-DJ; Fri, 14 Aug 2020 06:58:41 +0000 Received: from mail-pl1-f195.google.com ([209.85.214.195]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1k6Tfe-0007ug-C0 for kernel-team@lists.ubuntu.com; Fri, 14 Aug 2020 06:58:34 +0000 Received: by mail-pl1-f195.google.com with SMTP id y10so2193886plr.11 for ; Thu, 13 Aug 2020 23:58:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9Tlt8mXMDeiPzbe8pfQmLDLOPLfxcaDzot7OS0/fnWM=; b=oL2DZWaPGB1WG2Fwf6l6MSXlr8r1Upv70V9ltCXzri4OeOnsR3RQs03SVUy7W9UpBG Cxa1+oOpdwnTv1JE4/byCBE19XhvpTCF11JxrJW/IxYeLjnN2QmCHuoA/7ind7+MgIqt J0Xj+cdSPmoyw4RSGbCaURSAOGlvXFOdzfQHKTjmfbQfThT1VbgxcZaGlwpxg3FkF4qw E13mLXlvmBBzW6h1Satn4zm/dfKoMfBwZ3uGuy3QpMj1Lh6QHOu0PPHvNJXfCNCe6hBq 9MMkVYbFZa4AbwQzgCgmSiGgmZJxV5IGM6jO4ZmyprFIGwURoNwuGZAL9Y1wBuUc1BiG uVBA== X-Gm-Message-State: AOAM53055g358LzV+utU7duGpB5zZujjhH4Kajz8+mUibvnusmcXOh3x jWqRzztNWnqVZVJXmUIV/MHs8L3MShA9hg== X-Google-Smtp-Source: ABdhPJxITGbydCLGDax4+FH9MGmDv/2HsmsODifYGRxPlYE/n29y2yHaUHQmOs+jvXlWFqkTkl9fNA== X-Received: by 2002:a17:90a:db18:: with SMTP id g24mr1119900pjv.14.1597388305896; Thu, 13 Aug 2020 23:58:25 -0700 (PDT) Received: from localhost (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id o63sm4115534pfb.190.2020.08.13.23.58.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:25 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 16/31][SRU][OEM-5.6] drm/i915: Implement display w/a 1140 for glk/cnl Date: Fri, 14 Aug 2020 14:57:25 +0800 Message-Id: <20200814065740.276039-17-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.195; envelope-from=vicamo@gmail.com; helo=mail-pl1-f195.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Ville Syrjälä BugLink: https://bugs.launchpad.net/bugs/1891451 Display w/a #1140 tells us we have to program the transition watermark to the minimum value on glk/cnl. Let's do that. Signed-off-by: Ville Syrjälä Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20200228203552.30273-4-ville.syrjala@linux.intel.com (cherry picked from commit c834d03cca61bf88aa8c2f9524360cce484686ac) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/intel_pm.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 29137201e20a..9b9e0780d411 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5124,8 +5124,7 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state, { struct drm_device *dev = crtc_state->uapi.crtc->dev; const struct drm_i915_private *dev_priv = to_i915(dev); - u16 trans_min, trans_y_tile_min; - const u16 trans_amount = 10; /* This is configurable amount */ + u16 trans_min, trans_amount, trans_y_tile_min; u16 wm0_sel_res_b, trans_offset_b, res_blocks; /* Transition WM don't make any sense if ipc is disabled */ @@ -5139,9 +5138,16 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state, if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) return; - trans_min = 14; if (INTEL_GEN(dev_priv) >= 11) trans_min = 4; + else + trans_min = 14; + + /* Display WA #1140: glk,cnl */ + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) + trans_amount = 0; + else + trans_amount = 10; /* This is configurable amount */ trans_offset_b = trans_min + trans_amount; @@ -5168,7 +5174,6 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state, /* WA BUG:1938466 add one block for non y-tile planes */ if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) res_blocks += 1; - } /* From patchwork Fri Aug 14 06:57:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344672 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ6H6bLjz9sTN; Fri, 14 Aug 2020 16:58:47 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1k6Tfn-00088Z-K7; Fri, 14 Aug 2020 06:58:43 +0000 Received: from mail-pg1-f196.google.com ([209.85.215.196]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1k6Tfj-0007wt-1v for kernel-team@lists.ubuntu.com; Fri, 14 Aug 2020 06:58:39 +0000 Received: by mail-pg1-f196.google.com with SMTP id d19so4076734pgl.10 for ; Thu, 13 Aug 2020 23:58:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ONvQXPFoloP5Uevg2E3A0KeaPUSYnSqU9DihHfI8nVU=; b=b8iW0I4VNm+sAg/dSlXquvDqWCn+4qMuPDX+LJr3ZlSFudVLF2JFIiNVUfRWoLtWWd aa7Djf01OjF86I10/5IznJfRP+Iju3maeaukDpYgZws7iv7Ga0e7CqjjT5GaFX7qPQyo DiO42LIdwCvly13L4OFJSB02yLiB3w7H5FFNzqEqzGY62Hyku8f8mOkdjQfsuhtktnbg /esSFg9aJIDC9KDLnoOwP7rOXKVjMzCkA6bkVl9vFeYjbF51txS7Vy4jS11GyEWCJGrJ A1uWXbJRn6AlrTpW7TQaWLD9SM24zd6v/NklYJ1AsKZlYfrmVkVsK5KZixIL0JmfPxus GfIQ== X-Gm-Message-State: AOAM530SHhzOpQFk30DYc5Rxtzqcf/BIssMR4lj3xrFYGGM3iqc12U+s 3KHDQURtyZJLx5nfRDznLvPZRUYxfo9q9A== X-Google-Smtp-Source: ABdhPJyuadaspgM1hw8mG0QipFktNTKjStygYJuj4TucNmHl8+iVHca66BG7q8hI36fytv7K+cS/MA== X-Received: by 2002:aa7:984e:: with SMTP id n14mr862923pfq.272.1597388308407; Thu, 13 Aug 2020 23:58:28 -0700 (PDT) Received: from localhost (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id e23sm7205304pgb.79.2020.08.13.23.58.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:27 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 17/31][SRU][OEM-5.6] drm/i915: Start passing latency as parameter Date: Fri, 14 Aug 2020 14:57:26 +0800 Message-Id: <20200814065740.276039-18-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.215.196; envelope-from=vicamo@gmail.com; helo=mail-pg1-f196.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Stanislav Lisovskiy BugLink: https://bugs.launchpad.net/bugs/1891451 We need to start passing memory latency as a parameter when calculating plane wm levels, as latency can get changed in different circumstances(for example with or without SAGV). So we need to be more flexible on that matter. v2: Changed latency type from u32 to unsigned int(Ville Syrjälä) Reviewed-by: Ville Syrjälä Signed-off-by: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200409154730.18568-2-stanislav.lisovskiy@intel.com (cherry picked from commit 7b994759ad3cc70715a20850416beb54ec0dd53f) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9b9e0780d411..3aaf2dbf4be2 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4002,6 +4002,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state, int color_plane); static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, int level, + unsigned int latency, const struct skl_wm_params *wp, const struct skl_wm_level *result_prev, struct skl_wm_level *result /* out */); @@ -4024,7 +4025,9 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state, WARN_ON(ret); for (level = 0; level <= max_level; level++) { - skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm); + unsigned int latency = dev_priv->wm.skl_latency[level]; + + skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm); if (wm.min_ddb_alloc == U16_MAX) break; @@ -4976,12 +4979,12 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level) static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, int level, + unsigned int latency, const struct skl_wm_params *wp, const struct skl_wm_level *result_prev, struct skl_wm_level *result /* out */) { struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); - u32 latency = dev_priv->wm.skl_latency[level]; uint_fixed_16_16_t method1, method2; uint_fixed_16_16_t selected_result; u32 res_blocks, res_lines, min_ddb_alloc = 0; @@ -5110,9 +5113,10 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state, for (level = 0; level <= max_level; level++) { struct skl_wm_level *result = &levels[level]; + unsigned int latency = dev_priv->wm.skl_latency[level]; - skl_compute_plane_wm(crtc_state, level, wm_params, - result_prev, result); + skl_compute_plane_wm(crtc_state, level, latency, + wm_params, result_prev, result); result_prev = result; } From patchwork Fri Aug 14 06:57:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344673 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ6L4l6wz9sTH; Fri, 14 Aug 2020 16:58:50 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1k6Tfq-0008B5-DI; Fri, 14 Aug 2020 06:58:46 +0000 Received: from mail-pj1-f67.google.com ([209.85.216.67]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1k6Tfl-0007zg-1N for kernel-team@lists.ubuntu.com; Fri, 14 Aug 2020 06:58:41 +0000 Received: by mail-pj1-f67.google.com with SMTP id mt12so3966418pjb.4 for ; Thu, 13 Aug 2020 23:58:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mkw7HCTpv8cqMYaw6ZW2VgiTmQMjxJqB5U9+E0G/xG0=; b=ghjbcuVkTinMXPRrdyzyqKsvVSz4bu33qLNnkGJ9Nj31IJpDlZ8uRUDL8FuRdJhWec a0lsT6I14GP8lyC0wItbd5FI9YMLKKVMlJVnM/X4DwvPOJl07y7IYH2udb+NaTUN4Sjj vBi/qehU6JCt1F7JGD3lG6QzXCXwXRfktUw+G66CPBXSaH3GhXyO1IwLgn68ITX9DENx USRGkfCm3e/YFpwRia/z+ZcePTgtqpyjYz2YKYh27Dd4D27kqMSRA2IhiDjAlO+Fdx5Z aVx91WOZf7TxCgnDHiTQs1aLBN8l18iU8EfvxloToMfh0+avKs9+2Qcw7xHeKlk2IAuc mHuQ== X-Gm-Message-State: AOAM532dWdUCbdLl2HYUNLu96lxPYmyjee/QXRuhjCm7czCn7TDi0tjA +CdLs0vRQKSjTgLcEH7kLIa0SrJk6F6i9Q== X-Google-Smtp-Source: ABdhPJz3j19l6a9fnOyI4qNep9wmKdC8hzW6yXnjjHxrpy2vTVhXdaYWDCsGKWd2qlKXgmzq158RJg== X-Received: by 2002:a17:90b:4a07:: with SMTP id kk7mr1197237pjb.125.1597388310770; Thu, 13 Aug 2020 23:58:30 -0700 (PDT) Received: from localhost (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id h12sm8215193pfr.143.2020.08.13.23.58.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:29 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 18/31][SRU][OEM-5.6] drm/i915: Prepare to extract gen specific functions from intel_can_enable_sagv Date: Fri, 14 Aug 2020 14:57:27 +0800 Message-Id: <20200814065740.276039-19-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.216.67; envelope-from=vicamo@gmail.com; helo=mail-pj1-f67.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Stanislav Lisovskiy BugLink: https://bugs.launchpad.net/bugs/1891451 Addressing one of the comments, recommending to extract platform specific code from intel_can_enable_sagv as a preparation, before we are going to add support for tgl+. v2: - Removed whitespace v3: - Removed premature debug and new cycle introduction(Ville) - Added missing no active pipes check(Ville) v4: - Fixed stupid mistake with plane_state caused by stupid macro change Signed-off-by: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200415145740.28241-1-stanislav.lisovskiy@intel.com (cherry picked from commit a389c49fac556cba82edee7a5724269ec2d28981) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/intel_pm.c | 61 +++++++++++++++++++-------------- 1 file changed, 36 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 3aaf2dbf4be2..9e92f8658b50 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3743,42 +3743,22 @@ intel_disable_sagv(struct drm_i915_private *dev_priv) return 0; } -bool intel_can_enable_sagv(struct intel_atomic_state *state) +static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) { - struct drm_device *dev = state->base.dev; + struct drm_device *dev = crtc_state->uapi.crtc->dev; struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_crtc *crtc; + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct intel_plane *plane; - struct intel_crtc_state *crtc_state; - enum pipe pipe; int level, latency; - if (!intel_has_sagv(dev_priv)) - return false; - - /* - * If there are no active CRTCs, no additional checks need be performed - */ - if (hweight8(state->active_pipes) == 0) + if (!crtc_state->hw.active) return true; - /* - * SKL+ workaround: bspec recommends we disable SAGV when we have - * more then one pipe enabled - */ - if (hweight8(state->active_pipes) > 1) - return false; - - /* Since we're now guaranteed to only have one active CRTC... */ - pipe = ffs(state->active_pipes) - 1; - crtc = intel_get_crtc_for_pipe(dev_priv, pipe); - crtc_state = to_intel_crtc_state(crtc->base.state); - if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) return false; for_each_intel_plane_on_crtc(dev, crtc, plane) { - struct skl_plane_wm *wm = + const struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane->id]; /* Skip this plane if it's not enabled */ @@ -3809,6 +3789,37 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state) return true; } +bool intel_can_enable_sagv(struct intel_atomic_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_crtc *crtc; + const struct intel_crtc_state *crtc_state; + enum pipe pipe; + + if (!intel_has_sagv(dev_priv)) + return false; + + /* + * If there are no active CRTCs, no additional checks need be performed + */ + if (hweight8(state->active_pipes) == 0) + return true; + + /* + * SKL+ workaround: bspec recommends we disable SAGV when we have + * more then one pipe enabled + */ + if (hweight8(state->active_pipes) > 1) + return false; + + /* Since we're now guaranteed to only have one active CRTC... */ + pipe = ffs(state->active_pipes) - 1; + crtc = intel_get_crtc_for_pipe(dev_priv, pipe); + crtc_state = to_intel_crtc_state(crtc->base.state); + + return intel_crtc_can_enable_sagv(crtc_state); +} + /* * Calculate initial DBuf slice offset, based on slice size * and mask(i.e if slice size is 1024 and second slice is enabled From patchwork Fri Aug 14 06:57:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344674 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ6N6Fhrz9sTN; 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[61.220.137.37]) by smtp.gmail.com with ESMTPSA id n17sm7297651pgg.6.2020.08.13.23.58.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:32 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 19/31][SRU][OEM-5.6] drm/i915: Add pre/post plane updates for SAGV Date: Fri, 14 Aug 2020 14:57:28 +0800 Message-Id: <20200814065740.276039-20-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.216.51; envelope-from=vicamo@gmail.com; helo=mail-pj1-f51.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Stanislav Lisovskiy BugLink: https://bugs.launchpad.net/bugs/1891451 Lets have a unified way to handle SAGV changes, espoecially considering the upcoming Gen12 changes. Current "standard" way of doing this in commit_tail is pre/post plane updates, when everything which has to be forbidden and not supported in new config has to be restricted before update and relaxed after plane update. v2: - Removed unneeded returns(Ville) Reviewed-by: Ville Syrjälä Signed-off-by: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200415143911.10244-5-stanislav.lisovskiy@intel.com (cherry picked from commit 680e1af713d92940e39a313a8592b13a6885a14c) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/display/intel_display.c | 13 ++++--------- drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++++++ drivers/gpu/drm/i915/intel_pm.h | 2 ++ 3 files changed, 22 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ebafe88572ba..ab250d7ae628 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15461,12 +15461,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_set_cdclk_pre_plane_update(state); - /* - * SKL workaround: bspec recommends we disable the SAGV when we - * have more then one pipe enabled - */ - if (!intel_can_enable_sagv(state)) - intel_disable_sagv(dev_priv); + intel_sagv_pre_plane_update(state); intel_modeset_verify_disabled(dev_priv, state); } @@ -15563,11 +15558,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_check_cpu_fifo_underruns(dev_priv); intel_check_pch_fifo_underruns(dev_priv); - if (state->modeset) + if (state->modeset) { intel_verify_planes(state); - if (state->modeset && intel_can_enable_sagv(state)) - intel_enable_sagv(dev_priv); + intel_sagv_post_plane_update(state); + } drm_atomic_helper_commit_hw_done(&state->base); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9e92f8658b50..ba1e8cc785d7 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3743,6 +3743,22 @@ intel_disable_sagv(struct drm_i915_private *dev_priv) return 0; } +void intel_sagv_pre_plane_update(struct intel_atomic_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + + if (!intel_can_enable_sagv(state)) + intel_disable_sagv(dev_priv); +} + +void intel_sagv_post_plane_update(struct intel_atomic_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + + if (intel_can_enable_sagv(state)) + intel_enable_sagv(dev_priv); +} + static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) { struct drm_device *dev = crtc_state->uapi.crtc->dev; diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h index d60a85421c5a..9a6036ab0f90 100644 --- a/drivers/gpu/drm/i915/intel_pm.h +++ b/drivers/gpu/drm/i915/intel_pm.h @@ -44,6 +44,8 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv); bool intel_can_enable_sagv(struct intel_atomic_state *state); int intel_enable_sagv(struct drm_i915_private *dev_priv); int intel_disable_sagv(struct drm_i915_private *dev_priv); +void intel_sagv_pre_plane_update(struct intel_atomic_state *state); +void intel_sagv_post_plane_update(struct intel_atomic_state *state); bool skl_wm_level_equals(const struct skl_wm_level *l1, const struct skl_wm_level *l2); bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, From patchwork Fri Aug 14 06:57:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344675 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ6S0KvLz9sTH; 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[61.220.137.37]) by smtp.gmail.com with ESMTPSA id q2sm7377763pgs.90.2020.08.13.23.58.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:35 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 20/31][SRU][OEM-5.6] drm/i915: Add intel_atomic_get_bw_*_state helpers Date: Fri, 14 Aug 2020 14:57:29 +0800 Message-Id: <20200814065740.276039-21-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.216.43; envelope-from=vicamo@gmail.com; helo=mail-pj1-f43.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Stanislav Lisovskiy BugLink: https://bugs.launchpad.net/bugs/1891451 Add correspondent helpers to be able to get old/new bandwidth global state object. v2: - Fixed typo in function call v3: - Changed new functions naming to use convention proposed by Jani Nikula, i.e intel_bw_* in intel_bw.c file. v4: - Change function naming back to intel_atomic* pattern, was decided to rename in a separate patch series. v5: - Fix function naming to match existing practices(Ville) v6: - Removed spurious whitespace v7: - Removed bw_state NULL checks(Ville) Reviewed-by: Ville Syrjälä Signed-off-by: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200415143911.10244-3-stanislav.lisovskiy@intel.com (cherry picked from commit 442e7ee834e8528ec85ea0df3c76bfe6c6742f5a) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/display/intel_bw.c | 24 +++++++++++++++++++++++- drivers/gpu/drm/i915/display/intel_bw.h | 9 +++++++++ 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 316abcf3e6a2..3a9b70d9522c 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -370,7 +370,29 @@ static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv, return data_rate; } -static struct intel_bw_state * +struct intel_bw_state * +intel_atomic_get_old_bw_state(struct intel_atomic_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_global_state *bw_state; + + bw_state = intel_atomic_get_old_global_obj_state(state, &dev_priv->bw_obj); + + return to_intel_bw_state(bw_state); +} + +struct intel_bw_state * +intel_atomic_get_new_bw_state(struct intel_atomic_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_global_state *bw_state; + + bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->bw_obj); + + return to_intel_bw_state(bw_state); +} + +struct intel_bw_state * intel_atomic_get_bw_state(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h index a8aa7624c5aa..ac004d6f4276 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.h +++ b/drivers/gpu/drm/i915/display/intel_bw.h @@ -24,6 +24,15 @@ struct intel_bw_state { #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base) +struct intel_bw_state * +intel_atomic_get_old_bw_state(struct intel_atomic_state *state); + +struct intel_bw_state * +intel_atomic_get_new_bw_state(struct intel_atomic_state *state); + +struct intel_bw_state * +intel_atomic_get_bw_state(struct intel_atomic_state *state); + void intel_bw_init_hw(struct drm_i915_private *dev_priv); int intel_bw_init(struct drm_i915_private *dev_priv); int intel_bw_atomic_check(struct intel_atomic_state *state); From patchwork Fri Aug 14 06:57:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344676 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ6W70l3z9sTH; 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[61.220.137.37]) by smtp.gmail.com with ESMTPSA id q2sm7377931pgs.90.2020.08.13.23.58.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:38 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 21/31][SRU][OEM-5.6] drm/i915: Use bw state for per crtc SAGV evaluation Date: Fri, 14 Aug 2020 14:57:30 +0800 Message-Id: <20200814065740.276039-22-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.215.179; envelope-from=vicamo@gmail.com; helo=mail-pg1-f179.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Stanislav Lisovskiy BugLink: https://bugs.launchpad.net/bugs/1891451 Future platforms require per-crtc SAGV evaluation and serializing global state when those are changed from different commits. v2: - Add has_sagv check to intel_crtc_can_enable_sagv so that it sets bit in reject mask. - Use bw_state in intel_pre/post_plane_enable_sagv instead of atomic state v3: - Fixed rebase conflict, now using intel_atomic_crtc_state_for_each_plane_state in order to call it from atomic check v4: - Use fb modifier from plane state v5: - Make intel_has_sagv static again(Ville) - Removed unnecessary NULL assignments(Ville) - Removed unnecessary SAGV debug(Ville) - Call intel_compute_sagv_mask only for modesets(Ville) - Serialize global state only if sagv results change, but not mask itself(Ville) v6: - use lock global state instead of serialize(Ville) v7: - use both global state lock and serialize depending on if we need to change only global state or access hw (Ville) Signed-off-by: Stanislav Lisovskiy Cc: Ville Syrjälä Cc: James Ausmus Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200430191757.18206-1-stanislav.lisovskiy@intel.com (cherry picked from commit 9728889f42b9ba078f86cd11535a89df29e93b33) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/display/intel_bw.h | 6 ++ drivers/gpu/drm/i915/intel_pm.c | 117 ++++++++++++++++++------ drivers/gpu/drm/i915/intel_pm.h | 3 +- 3 files changed, 97 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h index ac004d6f4276..d6df91058223 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.h +++ b/drivers/gpu/drm/i915/display/intel_bw.h @@ -18,6 +18,12 @@ struct intel_crtc_state; struct intel_bw_state { struct intel_global_state base; + /* + * Contains a bit mask, used to determine, whether correspondent + * pipe allows SAGV or not. + */ + u8 pipe_sagv_reject; + unsigned int data_rate[I915_MAX_PIPES]; u8 num_active_planes[I915_MAX_PIPES]; }; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ba1e8cc785d7..1a192263be55 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -42,6 +42,7 @@ #include "i915_drv.h" #include "i915_irq.h" #include "i915_trace.h" +#include "display/intel_bw.h" #include "intel_pm.h" #include "intel_sideband.h" #include "../../../platform/x86/intel_ips.h" @@ -3746,34 +3747,75 @@ intel_disable_sagv(struct drm_i915_private *dev_priv) void intel_sagv_pre_plane_update(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); + const struct intel_bw_state *new_bw_state; - if (!intel_can_enable_sagv(state)) + /* + * Just return if we can't control SAGV or don't have it. + * This is different from situation when we have SAGV but just can't + * afford it due to DBuf limitation - in case if SAGV is completely + * disabled in a BIOS, we are not even allowed to send a PCode request, + * as it will throw an error. So have to check it here. + */ + if (!intel_has_sagv(dev_priv)) + return; + + new_bw_state = intel_atomic_get_new_bw_state(state); + if (!new_bw_state) + return; + + if (!intel_can_enable_sagv(new_bw_state)) intel_disable_sagv(dev_priv); } void intel_sagv_post_plane_update(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); + const struct intel_bw_state *new_bw_state; + + /* + * Just return if we can't control SAGV or don't have it. + * This is different from situation when we have SAGV but just can't + * afford it due to DBuf limitation - in case if SAGV is completely + * disabled in a BIOS, we are not even allowed to send a PCode request, + * as it will throw an error. So have to check it here. + */ + if (!intel_has_sagv(dev_priv)) + return; - if (intel_can_enable_sagv(state)) + new_bw_state = intel_atomic_get_new_bw_state(state); + if (!new_bw_state) + return; + + if (intel_can_enable_sagv(new_bw_state)) intel_enable_sagv(dev_priv); } static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) { - struct drm_device *dev = crtc_state->uapi.crtc->dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_plane *plane; + const struct intel_plane_state *plane_state; int level, latency; + if (!intel_has_sagv(dev_priv)) + return false; + if (!crtc_state->hw.active) return true; + /* + * SKL+ workaround: bspec recommends we disable SAGV when we have + * more then one pipe enabled + */ + if (hweight8(state->active_pipes) > 1) + return false; + if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) return false; - for_each_intel_plane_on_crtc(dev, crtc, plane) { + intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) { const struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane->id]; @@ -3789,7 +3831,7 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state latency = dev_priv->wm.skl_latency[level]; if (skl_needs_memory_bw_wa(dev_priv) && - plane->base.state->fb->modifier == + plane_state->uapi.fb->modifier == I915_FORMAT_MOD_X_TILED) latency += 15; @@ -3805,35 +3847,48 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state return true; } -bool intel_can_enable_sagv(struct intel_atomic_state *state) +bool intel_can_enable_sagv(const struct intel_bw_state *bw_state) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + return bw_state->pipe_sagv_reject == 0; +} + +static int intel_compute_sagv_mask(struct intel_atomic_state *state) +{ + int ret; struct intel_crtc *crtc; - const struct intel_crtc_state *crtc_state; - enum pipe pipe; + struct intel_crtc_state *new_crtc_state; + struct intel_bw_state *new_bw_state = NULL; + const struct intel_bw_state *old_bw_state = NULL; + int i; - if (!intel_has_sagv(dev_priv)) - return false; + for_each_new_intel_crtc_in_state(state, crtc, + new_crtc_state, i) { + new_bw_state = intel_atomic_get_bw_state(state); + if (IS_ERR(new_bw_state)) + return PTR_ERR(new_bw_state); - /* - * If there are no active CRTCs, no additional checks need be performed - */ - if (hweight8(state->active_pipes) == 0) - return true; + old_bw_state = intel_atomic_get_old_bw_state(state); - /* - * SKL+ workaround: bspec recommends we disable SAGV when we have - * more then one pipe enabled - */ - if (hweight8(state->active_pipes) > 1) - return false; + if (intel_crtc_can_enable_sagv(new_crtc_state)) + new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe); + else + new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe); + } - /* Since we're now guaranteed to only have one active CRTC... */ - pipe = ffs(state->active_pipes) - 1; - crtc = intel_get_crtc_for_pipe(dev_priv, pipe); - crtc_state = to_intel_crtc_state(crtc->base.state); + if (!new_bw_state) + return 0; - return intel_crtc_can_enable_sagv(crtc_state); + if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) { + ret = intel_atomic_serialize_global_state(&new_bw_state->base); + if (ret) + return ret; + } else if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) { + ret = intel_atomic_lock_global_state(&new_bw_state->base); + if (ret) + return ret; + } + + return 0; } /* @@ -5814,6 +5869,12 @@ skl_compute_wm(struct intel_atomic_state *state) if (ret) return ret; + if (state->modeset) { + ret = intel_compute_sagv_mask(state); + if (ret) + return ret; + } + /* * skl_compute_ddb() will have adjusted the final watermarks * based on how much ddb is available. Now we can actually diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h index 9a6036ab0f90..fd1dc422e6c5 100644 --- a/drivers/gpu/drm/i915/intel_pm.h +++ b/drivers/gpu/drm/i915/intel_pm.h @@ -9,6 +9,7 @@ #include #include "i915_reg.h" +#include "display/intel_bw.h" struct drm_device; struct drm_i915_private; @@ -41,7 +42,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, struct skl_pipe_wm *out); void g4x_wm_sanitize(struct drm_i915_private *dev_priv); void vlv_wm_sanitize(struct drm_i915_private *dev_priv); -bool intel_can_enable_sagv(struct intel_atomic_state *state); +bool intel_can_enable_sagv(const struct intel_bw_state *bw_state); int intel_enable_sagv(struct drm_i915_private *dev_priv); int intel_disable_sagv(struct drm_i915_private *dev_priv); void intel_sagv_pre_plane_update(struct intel_atomic_state *state); From patchwork Fri Aug 14 06:57:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344677 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ6b2CpZz9sPB; Fri, 14 Aug 2020 16:59:03 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1k6Tg2-0008Ls-H0; Fri, 14 Aug 2020 06:58:58 +0000 Received: from mail-pj1-f68.google.com ([209.85.216.68]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1k6Tft-00087e-R4 for kernel-team@lists.ubuntu.com; Fri, 14 Aug 2020 06:58:50 +0000 Received: by mail-pj1-f68.google.com with SMTP id d4so3939276pjx.5 for ; Thu, 13 Aug 2020 23:58:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fazPukGnX0MHHl6Qr3VNM9o6pJ+PLshcufv7xDhx9f0=; b=RXDEOQD3kz+HUuC8UmueHU/n9GFGBV4A5CB3pbuzMKMaUp1OhnksIrxcem/tcYqB5q 5oWIdic3tudQjqvcxaBvH9jgnSFUo/5TDjVHRCsGnRKq4+45EivYWIS9fW/SdqmGvVxu znIbIR+x4Ael1twHRruSA/ygaQnpN8qmtsAgdQ+TuKugWnmETU5gogNnLnSUdejMgZSN PGjo33JhsWJ5D6QEmdYfFuzCLWTZVNt3eMbk6F+FwmBE5UJmdpBf5n+IJp0aEhUlBdFO kioq0w23RVkYn3aEt/PFgjpLNJN5BTWiRUQHYmEYVCGVQGyNSSQ+0sVzk0+uq/k29DQR 7GdQ== X-Gm-Message-State: AOAM530KyUbPhQbJ+9dCY+5FURZ8yT6lYskyiPpoeEcEqG0BVu83Chmh 8dm+8iA2EFVC58ZLVrg6N0NdKfeDIOGaaw== X-Google-Smtp-Source: ABdhPJzrTtW3hb9rccmwekZiEGR9zLsRUogFHLV71KXGJHyNvMSaRmG3mHis46e6exDC4cSqsEV90A== X-Received: by 2002:a17:90b:1c06:: with SMTP id oc6mr1105472pjb.182.1597388321094; Thu, 13 Aug 2020 23:58:41 -0700 (PDT) Received: from localhost (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id z2sm8160440pfq.46.2020.08.13.23.58.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:40 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 22/31][SRU][OEM-5.6] drm/i915: Track active_pipes in bw_state Date: Fri, 14 Aug 2020 14:57:31 +0800 Message-Id: <20200814065740.276039-23-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.216.68; envelope-from=vicamo@gmail.com; helo=mail-pj1-f68.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Stanislav Lisovskiy BugLink: https://bugs.launchpad.net/bugs/1891451 We need to calculate SAGV mask also in a non-modeset commit, however currently active_pipes are only calculated for modesets in global atomic state, thus now we will be tracking those also in bw_state in order to be able to properly access global data. v2: - Removed pre/post plane SAGV updates from modeset(Ville) - Now tracking active pipes in intel_can_enable_sagv(Ville) v3: - lock global state if active_pipes change as well(Ville) Signed-off-by: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200430195634.7666-1-stanislav.lisovskiy@intel.com (cherry picked from commit ecab0f3d055d333640bbe2aa5a5141574a65c534) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/display/intel_bw.h | 3 +++ drivers/gpu/drm/i915/display/intel_display.c | 9 +++---- drivers/gpu/drm/i915/intel_pm.c | 27 ++++++++++---------- 3 files changed, 21 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h index d6df91058223..898b4a85ccab 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.h +++ b/drivers/gpu/drm/i915/display/intel_bw.h @@ -26,6 +26,9 @@ struct intel_bw_state { unsigned int data_rate[I915_MAX_PIPES]; u8 num_active_planes[I915_MAX_PIPES]; + + /* bitmask of active pipes */ + u8 active_pipes; }; #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ab250d7ae628..9b00721c0e22 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15461,11 +15461,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_set_cdclk_pre_plane_update(state); - intel_sagv_pre_plane_update(state); - intel_modeset_verify_disabled(dev_priv, state); } + intel_sagv_pre_plane_update(state); + /* Complete the events for pipes that have now been disabled */ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { bool modeset = needs_modeset(new_crtc_state); @@ -15558,11 +15558,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_check_cpu_fifo_underruns(dev_priv); intel_check_pch_fifo_underruns(dev_priv); - if (state->modeset) { + if (state->modeset) intel_verify_planes(state); - intel_sagv_post_plane_update(state); - } + intel_sagv_post_plane_update(state); drm_atomic_helper_commit_hw_done(&state->base); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 1a192263be55..cdc27982a200 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3792,7 +3792,6 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state) static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) { - struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_plane *plane; @@ -3805,13 +3804,6 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state if (!crtc_state->hw.active) return true; - /* - * SKL+ workaround: bspec recommends we disable SAGV when we have - * more then one pipe enabled - */ - if (hweight8(state->active_pipes) > 1) - return false; - if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) return false; @@ -3849,6 +3841,9 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state bool intel_can_enable_sagv(const struct intel_bw_state *bw_state) { + if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes)) + return false; + return bw_state->pipe_sagv_reject == 0; } @@ -3878,6 +3873,14 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state) if (!new_bw_state) return 0; + new_bw_state->active_pipes = + intel_calc_active_pipes(state, old_bw_state->active_pipes); + if (new_bw_state->active_pipes != old_bw_state->active_pipes) { + ret = intel_atomic_lock_global_state(&new_bw_state->base); + if (ret) + return ret; + } + if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) { ret = intel_atomic_serialize_global_state(&new_bw_state->base); if (ret) @@ -5869,11 +5872,9 @@ skl_compute_wm(struct intel_atomic_state *state) if (ret) return ret; - if (state->modeset) { - ret = intel_compute_sagv_mask(state); - if (ret) - return ret; - } + ret = intel_compute_sagv_mask(state); + if (ret) + return ret; /* * skl_compute_ddb() will have adjusted the final watermarks From patchwork Fri Aug 14 06:57:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344678 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ6g4vngz9sTK; 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[61.220.137.37]) by smtp.gmail.com with ESMTPSA id a24sm7983555pfg.113.2020.08.13.23.58.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:42 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 23/31][SRU][OEM-5.6] drm/i915: Rename bw_state to new_bw_state Date: Fri, 14 Aug 2020 14:57:32 +0800 Message-Id: <20200814065740.276039-24-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.215.180; envelope-from=vicamo@gmail.com; helo=mail-pg1-f180.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Stanislav Lisovskiy BugLink: https://bugs.launchpad.net/bugs/1891451 That is a preparation patch before next one where we introduce old_bw_state and a bunch of other changes as well. In a review comment it was suggested to split out at least that renaming into a separate patch, what is done here. v2: Removed spurious space Reviewed-by: Ville Syrjälä Signed-off-by: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200423075902.21892-8-stanislav.lisovskiy@intel.com (backported from commit 9ff79708c54d34a3d4d451b15f8d6e5e042f1d36 fix conflicts due to DRM_DEBUG_KMS) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/display/intel_bw.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 3a9b70d9522c..9407476a936f 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -409,7 +409,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc_state *new_crtc_state, *old_crtc_state; - struct intel_bw_state *bw_state = NULL; + struct intel_bw_state *new_bw_state = NULL; unsigned int data_rate, max_data_rate; unsigned int num_active_planes; struct intel_crtc *crtc; @@ -438,28 +438,28 @@ int intel_bw_atomic_check(struct intel_atomic_state *state) old_active_planes == new_active_planes) continue; - bw_state = intel_atomic_get_bw_state(state); - if (IS_ERR(bw_state)) - return PTR_ERR(bw_state); + new_bw_state = intel_atomic_get_bw_state(state); + if (IS_ERR(new_bw_state)) + return PTR_ERR(new_bw_state); - bw_state->data_rate[crtc->pipe] = new_data_rate; - bw_state->num_active_planes[crtc->pipe] = new_active_planes; + new_bw_state->data_rate[crtc->pipe] = new_data_rate; + new_bw_state->num_active_planes[crtc->pipe] = new_active_planes; DRM_DEBUG_KMS("pipe %c data rate %u num active planes %u\n", pipe_name(crtc->pipe), - bw_state->data_rate[crtc->pipe], - bw_state->num_active_planes[crtc->pipe]); + new_bw_state->data_rate[crtc->pipe], + new_bw_state->num_active_planes[crtc->pipe]); } - if (!bw_state) + if (!new_bw_state) return 0; - ret = intel_atomic_lock_global_state(&bw_state->base); + ret = intel_atomic_lock_global_state(&new_bw_state->base); if (ret) return ret; - data_rate = intel_bw_data_rate(dev_priv, bw_state); - num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state); + data_rate = intel_bw_data_rate(dev_priv, new_bw_state); + num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state); max_data_rate = intel_max_data_rate(dev_priv, num_active_planes); From patchwork Fri Aug 14 06:57:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344679 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; 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[61.220.137.37]) by smtp.gmail.com with ESMTPSA id y1sm7833608pfl.136.2020.08.13.23.58.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:45 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 24/31][SRU][OEM-5.6] drm/i915: Introduce skl_plane_wm_level accessor. Date: Fri, 14 Aug 2020 14:57:33 +0800 Message-Id: <20200814065740.276039-25-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.210.175; envelope-from=vicamo@gmail.com; helo=mail-pf1-f175.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Stanislav Lisovskiy BugLink: https://bugs.launchpad.net/bugs/1891451 For future Gen12 SAGV implementation we need to seemlessly alter wm levels calculated, depending on whether we are allowed to enable SAGV or not. So this accessor will give additional flexibility to do that. Currently this accessor is still simply working as "pass-through" function. This will be changed in next coming patches from this series. v2: - plane_id -> plane->id(Ville Syrjälä) - Moved wm_level var to have more local scope (Ville Syrjälä) - Renamed yuv to color_plane(Ville Syrjälä) in skl_plane_wm_level v3: - plane->id -> plane_id(this time for real, Ville Syrjälä) - Changed colorplane id type from boolean to int as index (Ville Syrjälä) - Moved crtc_state param so that it is first now (Ville Syrjälä) - Moved wm_level declaration to tigher scope in skl_write_plane_wm(Ville Syrjälä) v4: - Started to use enum values for color plane - Do sizeof for a type what we are memset'ing - Zero out wm_uv as well(Ville Syrjälä) v5: - Fixed rebase conflict caused by COLOR_PLANE_* enum removal v6: - Do not use skl_plane_wm_level accessor in skl_allocate_pipe_ddb v7: - Get rid of wm_uv, which is not used in skl_plane_write_wm(Ville) Signed-off-by: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200513093816.11466-2-stanislav.lisovskiy@intel.com (cherry picked from commit d9162348db12487754e61f73497bdcfcea753590) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index cdc27982a200..8b4868462d3f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4633,6 +4633,17 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state, return total_data_rate; } +static const struct skl_wm_level * +skl_plane_wm_level(const struct intel_crtc_state *crtc_state, + enum plane_id plane_id, + int level) +{ + const struct skl_plane_wm *wm = + &crtc_state->wm.skl.optimal.planes[plane_id]; + + return &wm->wm[level]; +} + static int skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state) { @@ -5446,8 +5457,12 @@ void skl_write_plane_wm(struct intel_plane *plane, &crtc_state->wm.skl.plane_ddb_uv[plane_id]; for (level = 0; level <= max_level; level++) { + const struct skl_wm_level *wm_level; + + wm_level = skl_plane_wm_level(crtc_state, plane_id, level); + skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level), - &wm->wm[level]); + wm_level); } skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id), &wm->trans_wm); @@ -5480,8 +5495,12 @@ void skl_write_cursor_wm(struct intel_plane *plane, &crtc_state->wm.skl.plane_ddb_y[plane_id]; for (level = 0; level <= max_level; level++) { + const struct skl_wm_level *wm_level; + + wm_level = skl_plane_wm_level(crtc_state, plane_id, level); + skl_write_wm_level(dev_priv, CUR_WM(pipe, level), - &wm->wm[level]); + wm_level); } skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm); From patchwork Fri Aug 14 06:57:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344681 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ6q1H2Dz9sTT; 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[61.220.137.37]) by smtp.gmail.com with ESMTPSA id s24sm7113659pjp.1.2020.08.13.23.58.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:47 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 25/31][SRU][OEM-5.6] drm/i915: Extract skl SAGV checking Date: Fri, 14 Aug 2020 14:57:34 +0800 Message-Id: <20200814065740.276039-26-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.215.196; envelope-from=vicamo@gmail.com; helo=mail-pg1-f196.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Stanislav Lisovskiy BugLink: https://bugs.launchpad.net/bugs/1891451 Introduce platform dependent SAGV checking in combination with bandwidth state pipe SAGV mask. This is preparation to adding TGL support, which requires different way of SAGV checking. v2, v3, v4, v5, v6: Fix rebase conflict v7: - Nuke icl specific function, use skl for icl as well, gen specific active_pipes check to be added in the next patch(Ville) v8: - Use more generic intel_crtc_can_enable_sagv for checking(Ville) Signed-off-by: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200513093816.11466-3-stanislav.lisovskiy@intel.com (cherry picked from commit 1d0a6c8486aa53f7545e80f5f0293ed99e48ffc0) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 8b4868462d3f..ed0e1cb4c11e 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3790,7 +3790,7 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state) intel_enable_sagv(dev_priv); } -static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) +static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -3839,6 +3839,11 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state return true; } +static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) +{ + return skl_crtc_can_enable_sagv(crtc_state); +} + bool intel_can_enable_sagv(const struct intel_bw_state *bw_state) { if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes)) @@ -3851,7 +3856,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state) { int ret; struct intel_crtc *crtc; - struct intel_crtc_state *new_crtc_state; + const struct intel_crtc_state *new_crtc_state; struct intel_bw_state *new_bw_state = NULL; const struct intel_bw_state *old_bw_state = NULL; int i; @@ -3875,6 +3880,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state) new_bw_state->active_pipes = intel_calc_active_pipes(state, old_bw_state->active_pipes); + if (new_bw_state->active_pipes != old_bw_state->active_pipes) { ret = intel_atomic_lock_global_state(&new_bw_state->base); if (ret) From patchwork Fri Aug 14 06:57:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344680 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ6n2fT6z9sTK; Fri, 14 Aug 2020 16:59:13 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1k6TgB-0008Ua-PJ; Fri, 14 Aug 2020 06:59:07 +0000 Received: from mail-pl1-f172.google.com ([209.85.214.172]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1k6Tg5-0008GM-JL for kernel-team@lists.ubuntu.com; Fri, 14 Aug 2020 06:59:01 +0000 Received: by mail-pl1-f172.google.com with SMTP id k13so3744290plk.13 for ; Thu, 13 Aug 2020 23:58:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XoPDywz4+aBs7oijIicljtafhlI3rT+6xEPyO2Svpww=; b=c7wDM4kVP1g/U38bp0j1vQ/XvG7pCOBG7RYKiJzLvValiwOblPHLmT1mcNJKNEd6N+ v7EFuUeUM9Abd+SiYnORojkkBdb7iVLokvzeDsrMVsZk7eQgdlRkJxcGQ4XRRPzckOZV 3QoOVvval/ePDDYys7bJolPl9yaFj9LFy2hEGCGscPiA9sZL/mBjKcqIuEIw95RkWiag BB6TQbbWTEVdu3s7Dk96AXsl2jogLk0dKOcOOmd/z/A6SL/afDYmZSN9IJ+tTXN7Y3zL i8phCoZaKUKHOFyduVeN6mympjZvNwpB3aLYb5VODdjvFGuW7OFmCBrk08+T30j1gHtd 042g== X-Gm-Message-State: AOAM5313kvCkd4n6epU3VQDV84nZl76SAsddPtzELPb71c4wlBAmdzdP XxsMUkaUaKOljkEqsgOXC280SPU6ayYNxg== X-Google-Smtp-Source: ABdhPJzE8+7wmZE80ZK9D//MU4lkUOvWRcRj0wsM16Kw0z+FrV1X3jY7RtaBNPSNuVkD8zJCDwDMGw== X-Received: by 2002:a17:90a:ff92:: with SMTP id hf18mr1170628pjb.107.1597388330657; Thu, 13 Aug 2020 23:58:50 -0700 (PDT) Received: from localhost (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id na14sm7045445pjb.6.2020.08.13.23.58.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:49 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 26/31][SRU][OEM-5.6] drm/i915: Make active_pipes check skl specific Date: Fri, 14 Aug 2020 14:57:35 +0800 Message-Id: <20200814065740.276039-27-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.172; envelope-from=vicamo@gmail.com; helo=mail-pl1-f172.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Stanislav Lisovskiy BugLink: https://bugs.launchpad.net/bugs/1891451 Seems that only skl needs to have SAGV turned off for multipipe scenarios, so lets do it this way. If anything blows up - we can always revert this patch. v2: Changed if condition to look better (Ville). Signed-off-by: Stanislav Lisovskiy [vsyrjala: wrapped long line to appease checkpatch] Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200513093816.11466-4-stanislav.lisovskiy@intel.com (cherry picked from commit d8d5afe35e3f88f73436f79f974d96a67e879637) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/intel_pm.c | 14 +++++++++----- drivers/gpu/drm/i915/intel_pm.h | 3 ++- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ed0e1cb4c11e..4a12e7731255 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3763,7 +3763,7 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state) if (!new_bw_state) return; - if (!intel_can_enable_sagv(new_bw_state)) + if (!intel_can_enable_sagv(dev_priv, new_bw_state)) intel_disable_sagv(dev_priv); } @@ -3786,7 +3786,7 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state) if (!new_bw_state) return; - if (intel_can_enable_sagv(new_bw_state)) + if (intel_can_enable_sagv(dev_priv, new_bw_state)) intel_enable_sagv(dev_priv); } @@ -3844,9 +3844,11 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state return skl_crtc_can_enable_sagv(crtc_state); } -bool intel_can_enable_sagv(const struct intel_bw_state *bw_state) +bool intel_can_enable_sagv(struct drm_i915_private *dev_priv, + const struct intel_bw_state *bw_state) { - if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes)) + if (INTEL_GEN(dev_priv) < 11 && + bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes)) return false; return bw_state->pipe_sagv_reject == 0; @@ -3854,6 +3856,7 @@ bool intel_can_enable_sagv(const struct intel_bw_state *bw_state) static int intel_compute_sagv_mask(struct intel_atomic_state *state) { + struct drm_i915_private *dev_priv = to_i915(state->base.dev); int ret; struct intel_crtc *crtc; const struct intel_crtc_state *new_crtc_state; @@ -3887,7 +3890,8 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state) return ret; } - if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) { + if (intel_can_enable_sagv(dev_priv, new_bw_state) != + intel_can_enable_sagv(dev_priv, old_bw_state)) { ret = intel_atomic_serialize_global_state(&new_bw_state->base); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h index fd1dc422e6c5..614ac7f8d4cc 100644 --- a/drivers/gpu/drm/i915/intel_pm.h +++ b/drivers/gpu/drm/i915/intel_pm.h @@ -42,7 +42,8 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, struct skl_pipe_wm *out); void g4x_wm_sanitize(struct drm_i915_private *dev_priv); void vlv_wm_sanitize(struct drm_i915_private *dev_priv); -bool intel_can_enable_sagv(const struct intel_bw_state *bw_state); +bool intel_can_enable_sagv(struct drm_i915_private *dev_priv, + const struct intel_bw_state *bw_state); int intel_enable_sagv(struct drm_i915_private *dev_priv); int intel_disable_sagv(struct drm_i915_private *dev_priv); void intel_sagv_pre_plane_update(struct intel_atomic_state *state); From patchwork Fri Aug 14 06:57:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344684 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ6w6P1zz9sV6; Fri, 14 Aug 2020 16:59:20 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1k6TgJ-0000A1-6t; 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[61.220.137.37]) by smtp.gmail.com with ESMTPSA id f17sm7093279pjp.46.2020.08.13.23.58.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:52 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 27/31][SRU][OEM-5.6] drm/i915/gen11: Add additional pcode status values Date: Fri, 14 Aug 2020 14:57:36 +0800 Message-Id: <20200814065740.276039-28-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.179; envelope-from=vicamo@gmail.com; helo=mail-pl1-f179.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Matt Roper BugLink: https://bugs.launchpad.net/bugs/1891451 I don't think we've ever hit these new error codes, but they're documented in the gen11 pcode document, so we might as well add them to the handler. Signed-off-by: Matt Roper Link: https://patchwork.freedesktop.org/patch/msgid/20200111014511.2988923-1-matthew.d.roper@intel.com Reviewed-by: José Roberto de Souza (cherry picked from commit f22fd334890e0e24305aaa7249ff56baba082eca) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_sideband.c | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3386a0fa414b..e1e18049e652 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9097,6 +9097,8 @@ enum { #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF #define GEN7_PCODE_TIMEOUT 0x2 #define GEN7_PCODE_ILLEGAL_DATA 0x3 +#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4 +#define GEN11_PCODE_LOCKED 0x6 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 #define GEN6_PCODE_READ_RC6VIDS 0x5 diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c index cbfb7171d62d..3361fdc41ee1 100644 --- a/drivers/gpu/drm/i915/intel_sideband.c +++ b/drivers/gpu/drm/i915/intel_sideband.c @@ -365,6 +365,10 @@ static inline int gen7_check_mailbox_status(u32 mbox) return -ETIMEDOUT; case GEN7_PCODE_ILLEGAL_DATA: return -EINVAL; + case GEN11_PCODE_ILLEGAL_SUBCOMMAND: + return -ENXIO; + case GEN11_PCODE_LOCKED: + return -EBUSY; case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE: return -EOVERFLOW; default: From patchwork Fri Aug 14 06:57:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344682 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ6s3L2mz9sTv; Fri, 14 Aug 2020 16:59:17 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1k6TgG-00006l-9p; Fri, 14 Aug 2020 06:59:12 +0000 Received: from mail-pl1-f169.google.com ([209.85.214.169]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1k6Tg9-0008Kn-2Z for kernel-team@lists.ubuntu.com; Fri, 14 Aug 2020 06:59:05 +0000 Received: by mail-pl1-f169.google.com with SMTP id y6so3766479plt.3 for ; Thu, 13 Aug 2020 23:58:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1xO7F0J+dwn1EV8Q7rE9QeVNF/Y5yghoSeBwIE5nruU=; b=sgxlAB8XSMBjHXE1nNlTwXtZ4ztdAUSaIXf/zh6w8o0ugAKeb/9kr8JC4+rpQBY8Bk ucNeVZuyrV5TUjM7LPa3IqsSNmoVxnbjcgTalSY/kpUfYZ4thXQqNfRsxIZpuB4E6WZB q+pvSBMlh4xeAsvLV9z8JIlaQp8UbPTdr+jZflDjXZZXh508+XS6HODMJETv3t1gqel5 bFCDbv/+4rfAscshcv3BgtNUT5/ONgdV8HGfacCMv51tmFMefeEDaQoEQ1q5hqteOwJG 0HA7GH1/RGgtEclv+WPAg8p1nwPEOpC3vkpTn1nJfkFUOck3SEEAzn+runRtwAwcg9Rd ShHg== X-Gm-Message-State: AOAM533NlxUqZhDuJBuySx3qn7K99o2Ku+QRgHigOg2SscX+SXyupxxl 6XE+di4xcmDfiLi9/PgrwYwts4QWFfjTtw== X-Google-Smtp-Source: ABdhPJzO2p0fdbBhbO+AcCC1oVlqSxBQA721ZTlEMeYmDwI+LWfNjnwUFOFqOSQD6KZseqcRnXO2Mg== X-Received: by 2002:a17:902:8d94:: with SMTP id v20mr1060352plo.298.1597388335767; Thu, 13 Aug 2020 23:58:55 -0700 (PDT) Received: from localhost (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id na16sm7372355pjb.30.2020.08.13.23.58.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:55 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 28/31][SRU][OEM-5.6] drm/i915: Added required new PCode commands Date: Fri, 14 Aug 2020 14:57:37 +0800 Message-Id: <20200814065740.276039-29-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.169; envelope-from=vicamo@gmail.com; helo=mail-pl1-f169.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Stanislav Lisovskiy BugLink: https://bugs.launchpad.net/bugs/1891451 We need a new PCode request commands and reply codes to be added as a prepartion patch for QGV points restricting for new SAGV support. v2: - Extracted those changes into separate patch (Ville Syrjälä) v3: - Moved new PCode masks to another place from PCode commands(Ville) v4: - Moved new PCode masks to correspondent PCode command, with identation(Ville) - Changed naming to ICL_ instead of GEN11_ to fit more nicely into existing definition style. Signed-off-by: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200505102247.32452-5-stanislav.lisovskiy@intel.com (cherry picked from commit f136c58a0de98e1b56483b7fc8c209dba0a496d9) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ drivers/gpu/drm/i915/intel_sideband.c | 2 ++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e1e18049e652..72623c833b6c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9099,6 +9099,7 @@ enum { #define GEN7_PCODE_ILLEGAL_DATA 0x3 #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4 #define GEN11_PCODE_LOCKED 0x6 +#define GEN11_PCODE_REJECTED 0x11 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 #define GEN6_PCODE_READ_RC6VIDS 0x5 @@ -9120,6 +9121,9 @@ enum { #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8) #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8)) +#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe +#define ICL_PCODE_POINTS_RESTRICTED 0x0 +#define ICL_PCODE_POINTS_RESTRICTED_MASK 0x1 #define GEN6_PCODE_READ_D_COMP 0x10 #define GEN6_PCODE_WRITE_D_COMP 0x11 #define ICL_PCODE_EXIT_TCCOLD 0x12 diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c index 3361fdc41ee1..16f4752e9a3b 100644 --- a/drivers/gpu/drm/i915/intel_sideband.c +++ b/drivers/gpu/drm/i915/intel_sideband.c @@ -369,6 +369,8 @@ static inline int gen7_check_mailbox_status(u32 mbox) return -ENXIO; case GEN11_PCODE_LOCKED: return -EBUSY; + case GEN11_PCODE_REJECTED: + return -EACCES; case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE: return -EOVERFLOW; default: From patchwork Fri Aug 14 06:57:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344685 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ704NBNz9sTK; Fri, 14 Aug 2020 16:59:24 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1k6TgN-0000Ct-9G; Fri, 14 Aug 2020 06:59:19 +0000 Received: from mail-pl1-f179.google.com ([209.85.214.179]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1k6TgF-0008NK-VN for kernel-team@lists.ubuntu.com; Fri, 14 Aug 2020 06:59:12 +0000 Received: by mail-pl1-f179.google.com with SMTP id y6so3766527plt.3 for ; Thu, 13 Aug 2020 23:59:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dBmjluPFuQj2YDaRiHNMHtIty25xV4o/4YTB7QJFWto=; b=p1UxVw0AwNGNeGBXcveOwjI5uKR0MjGR9cxgEMjzVAmpsTH8OLoU8mKB32muS93Rv3 1jRMUZYFE5aYnP1aVWAnO9ZOf+qO3QE0xr+yu4PdP/jHjI6GoFDSTLpX61yRj9l01WYw Rob6jZ+YHraSL816l378o44kMg6xH50w73z1l7YLE3QfCGl07TAG98StLCTZ+DOuQlBi OfqoIYT6mdI/DkMomJb+xbw2u/JlUu8gmoip5Ec+9zwNFhV5Ub8piVU/zXCwhhG3+S+0 baGaLj3VNVlJMiTwOsYcXu8I/WRhF9cQ9Eep1icWHyCKw+6yYQSpF7GGB0NtFO2ghH40 VY3A== X-Gm-Message-State: AOAM530g9p09FQcm6oANjL20BzCq2uVLBWgn3GPfoVPno3xpxhggiQsT cKTGQHJO/Y69tVmwqNW406WihuGDKtl7Fg== X-Google-Smtp-Source: ABdhPJz+j5ROg8AMy+2fTVjijIdLxx77tCFED/fwvD6ojID9HD+kj48Fx7EgFMgfFDKtJzttjmVVZQ== X-Received: by 2002:a17:90a:d081:: with SMTP id k1mr1125693pju.177.1597388338105; Thu, 13 Aug 2020 23:58:58 -0700 (PDT) Received: from localhost (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id s185sm7607748pgc.18.2020.08.13.23.58.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:58:57 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 29/31][SRU][OEM-5.6] drm/i915: Add TGL+ SAGV support Date: Fri, 14 Aug 2020 14:57:38 +0800 Message-Id: <20200814065740.276039-30-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.214.179; envelope-from=vicamo@gmail.com; helo=mail-pl1-f179.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Stanislav Lisovskiy BugLink: https://bugs.launchpad.net/bugs/1891451 Starting from TGL we need to have a separate wm0 values for SAGV and non-SAGV which affects how calculations are done. v2: Remove long lines v3: Removed COLOR_PLANE enum references v4, v5, v6: Fixed rebase conflict v7: - Removed skl_plane_wm_level accessor from skl_allocate_pipe_ddb(Ville) - Removed sagv_uv_wm0(Ville) - can_sagv->use_sagv_wm(Ville) v8: - Moved tgl_crtc_can_enable_sagv function up(Ville) - Changed comment regarding pipe_wm usage(Ville) - Call intel_can_enable_sagv and tgl_compute_sagv_wm only for Gen12(Ville) - Some sagv debugs removed(Ville) - skl_print_wm_changes improvements(Ville) - Do assignment instead of memcpy in skl_pipe_wm_get_hw_state(Ville) v9: - Removed can_sagv variable(Ville) - Removed spurious line(Ville) - Changed u32 to unsigned int as agreed(Ville) - Assign sagv only for gen12 in skl_pipe_wm_get_hw_state(Ville) Signed-off-by: Stanislav Lisovskiy [vsyrjala: Remove the dead 'return false' from intel_crtc_can_enable_sagv()] Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200514074853.9508-2-stanislav.lisovskiy@intel.com (cherry picked from commit 7241c57d3140ad3b613777a8515ffe1f653d4800) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/display/intel_display.c | 8 +- .../drm/i915/display/intel_display_types.h | 2 + drivers/gpu/drm/i915/intel_pm.c | 108 +++++++++++++++--- 3 files changed, 99 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 9b00721c0e22..f719c27c85f4 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13885,7 +13885,9 @@ static void verify_wm_state(struct intel_crtc *crtc, /* Watermarks */ for (level = 0; level <= max_level; level++) { if (skl_wm_level_equals(&hw_plane_wm->wm[level], - &sw_plane_wm->wm[level])) + &sw_plane_wm->wm[level]) || + (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level], + &sw_plane_wm->sagv_wm0))) continue; DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", @@ -13937,7 +13939,9 @@ static void verify_wm_state(struct intel_crtc *crtc, /* Watermarks */ for (level = 0; level <= max_level; level++) { if (skl_wm_level_equals(&hw_plane_wm->wm[level], - &sw_plane_wm->wm[level])) + &sw_plane_wm->wm[level]) || + (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level], + &sw_plane_wm->sagv_wm0))) continue; DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index fa3c29e8a7f5..efd82ecd520b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -654,11 +654,13 @@ struct skl_plane_wm { struct skl_wm_level wm[8]; struct skl_wm_level uv_wm[8]; struct skl_wm_level trans_wm; + struct skl_wm_level sagv_wm0; bool is_planar; }; struct skl_pipe_wm { struct skl_plane_wm planes[I915_MAX_PLANES]; + bool use_sagv_wm; }; enum vlv_wm_level { diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 4a12e7731255..3100f491e9b4 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3839,9 +3839,36 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) return true; } +static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + enum plane_id plane_id; + + if (!crtc_state->hw.active) + return true; + + for_each_plane_id_on_crtc(crtc, plane_id) { + const struct skl_ddb_entry *plane_alloc = + &crtc_state->wm.skl.plane_ddb_y[plane_id]; + const struct skl_plane_wm *wm = + &crtc_state->wm.skl.optimal.planes[plane_id]; + + if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc) + return false; + } + + return true; +} + static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) { - return skl_crtc_can_enable_sagv(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + + if (INTEL_GEN(dev_priv) >= 12) + return tgl_crtc_can_enable_sagv(crtc_state); + else + return skl_crtc_can_enable_sagv(crtc_state); } bool intel_can_enable_sagv(struct drm_i915_private *dev_priv, @@ -3859,7 +3886,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state) struct drm_i915_private *dev_priv = to_i915(state->base.dev); int ret; struct intel_crtc *crtc; - const struct intel_crtc_state *new_crtc_state; + struct intel_crtc_state *new_crtc_state; struct intel_bw_state *new_bw_state = NULL; const struct intel_bw_state *old_bw_state = NULL; int i; @@ -3890,6 +3917,20 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state) return ret; } + for_each_new_intel_crtc_in_state(state, crtc, + new_crtc_state, i) { + struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal; + + /* + * We store use_sagv_wm in the crtc state rather than relying on + * that bw state since we have no convenient way to get at the + * latter from the plane commit hooks (especially in the legacy + * cursor case) + */ + pipe_wm->use_sagv_wm = INTEL_GEN(dev_priv) >= 12 && + intel_can_enable_sagv(dev_priv, new_bw_state); + } + if (intel_can_enable_sagv(dev_priv, new_bw_state) != intel_can_enable_sagv(dev_priv, old_bw_state)) { ret = intel_atomic_serialize_global_state(&new_bw_state->base); @@ -4648,8 +4689,11 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state, enum plane_id plane_id, int level) { - const struct skl_plane_wm *wm = - &crtc_state->wm.skl.optimal.planes[plane_id]; + const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; + const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; + + if (level == 0 && pipe_wm->use_sagv_wm) + return &wm->sagv_wm0; return &wm->wm[level]; } @@ -4695,7 +4739,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state) plane_data_rate, uv_plane_data_rate); - skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state, total_data_rate, alloc, &num_active); alloc_size = skl_ddb_entry_size(alloc); @@ -5228,6 +5271,20 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state, } } +static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state, + const struct skl_wm_params *wm_params, + struct skl_plane_wm *plane_wm) +{ + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct skl_wm_level *sagv_wm = &plane_wm->sagv_wm0; + struct skl_wm_level *levels = plane_wm->wm; + unsigned int latency = dev_priv->wm.skl_latency[0] + dev_priv->sagv_block_time_us; + + skl_compute_plane_wm(crtc_state, 0, latency, + wm_params, &levels[0], + sagv_wm); +} + static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state, const struct skl_wm_params *wp, struct skl_plane_wm *wm) @@ -5299,6 +5356,8 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state, enum plane_id plane_id, int color_plane) { + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; struct skl_wm_params wm_params; int ret; @@ -5309,6 +5368,10 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state, return ret; skl_compute_wm_levels(crtc_state, &wm_params, wm->wm); + + if (INTEL_GEN(dev_priv) >= 12) + tgl_compute_sagv_wm(crtc_state, &wm_params, wm); + skl_compute_transition_wm(crtc_state, &wm_params, wm); return 0; @@ -5674,23 +5737,25 @@ skl_print_wm_changes(struct intel_atomic_state *state) continue; drm_dbg_kms(&dev_priv->drm, - "[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm" - " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm\n", + "[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm" + " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm\n", plane->base.base.id, plane->base.name, enast(old_wm->wm[0].plane_en), enast(old_wm->wm[1].plane_en), enast(old_wm->wm[2].plane_en), enast(old_wm->wm[3].plane_en), enast(old_wm->wm[4].plane_en), enast(old_wm->wm[5].plane_en), enast(old_wm->wm[6].plane_en), enast(old_wm->wm[7].plane_en), enast(old_wm->trans_wm.plane_en), + enast(old_wm->sagv_wm0.plane_en), enast(new_wm->wm[0].plane_en), enast(new_wm->wm[1].plane_en), enast(new_wm->wm[2].plane_en), enast(new_wm->wm[3].plane_en), enast(new_wm->wm[4].plane_en), enast(new_wm->wm[5].plane_en), enast(new_wm->wm[6].plane_en), enast(new_wm->wm[7].plane_en), - enast(new_wm->trans_wm.plane_en)); + enast(new_wm->trans_wm.plane_en), + enast(new_wm->sagv_wm0.plane_en)); drm_dbg_kms(&dev_priv->drm, - "[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d" - " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n", + "[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d" + " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n", plane->base.base.id, plane->base.name, enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l, enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l, @@ -5701,6 +5766,7 @@ skl_print_wm_changes(struct intel_atomic_state *state) enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].plane_res_l, enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l, enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l, + enast(old_wm->sagv_wm0.ignore_lines), old_wm->sagv_wm0.plane_res_l, enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l, enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l, @@ -5710,37 +5776,42 @@ skl_print_wm_changes(struct intel_atomic_state *state) enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].plane_res_l, enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].plane_res_l, enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l, - enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l); + enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l, + enast(new_wm->sagv_wm0.ignore_lines), new_wm->sagv_wm0.plane_res_l); drm_dbg_kms(&dev_priv->drm, - "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d" - " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n", + "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d" + " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n", plane->base.base.id, plane->base.name, old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b, old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b, old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b, old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b, old_wm->trans_wm.plane_res_b, + old_wm->sagv_wm0.plane_res_b, new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b, new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b, new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b, new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b, - new_wm->trans_wm.plane_res_b); + new_wm->trans_wm.plane_res_b, + new_wm->sagv_wm0.plane_res_b); drm_dbg_kms(&dev_priv->drm, - "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d" - " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n", + "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d" + " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n", plane->base.base.id, plane->base.name, old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc, old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc, old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc, old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc, old_wm->trans_wm.min_ddb_alloc, + old_wm->sagv_wm0.min_ddb_alloc, new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc, new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc, new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc, new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc, - new_wm->trans_wm.min_ddb_alloc); + new_wm->trans_wm.min_ddb_alloc, + new_wm->sagv_wm0.min_ddb_alloc); } } } @@ -6034,6 +6105,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, skl_wm_level_from_reg_val(val, &wm->wm[level]); } + if (INTEL_GEN(dev_priv) >= 12) + wm->sagv_wm0 = wm->wm[0]; + if (plane_id != PLANE_CURSOR) val = I915_READ(PLANE_WM_TRANS(pipe, plane_id)); else From patchwork Fri Aug 14 06:57:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344686 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ723qHdz9sTM; Fri, 14 Aug 2020 16:59:26 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1k6TgP-0000F0-EY; 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[61.220.137.37]) by smtp.gmail.com with ESMTPSA id fv23sm7001114pjb.35.2020.08.13.23.58.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:59:00 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 30/31][SRU][OEM-5.6] drm/i915: Restrict qgv points which don't have enough bandwidth. Date: Fri, 14 Aug 2020 14:57:39 +0800 Message-Id: <20200814065740.276039-31-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.215.194; envelope-from=vicamo@gmail.com; helo=mail-pg1-f194.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Stanislav Lisovskiy BugLink: https://bugs.launchpad.net/bugs/1891451 According to BSpec 53998, we should try to restrict qgv points, which can't provide enough bandwidth for desired display configuration. Currently we are just comparing against all of those and take minimum(worst case). v2: Fixed wrong PCode reply mask, removed hardcoded values. v3: Forbid simultaneous legacy SAGV PCode requests and restricting qgv points. Put the actual restriction to commit function, added serialization(thanks to Ville) to prevent commit being applied out of order in case of nonblocking and/or nomodeset commits. v4: - Minor code refactoring, fixed few typos(thanks to James Ausmus) - Change the naming of qgv point masking/unmasking functions(James Ausmus). - Simplify the masking/unmasking operation itself, as we don't need to mask only single point per request(James Ausmus) - Reject and stick to highest bandwidth point if SAGV can't be enabled(BSpec) v5: - Add new mailbox reply codes, which seems to happen during boot time for TGL and indicate that QGV setting is not yet available. v6: - Increase number of supported QGV points to be in sync with BSpec. v7: - Rebased and resolved conflict to fix build failure. - Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus) v8: - Don't report an error if we can't restrict qgv points, as SAGV can be disabled by BIOS, which is completely legal. So don't make CI panic. Instead if we detect that there is only 1 QGV point accessible just analyze if we can fit the required bandwidth requirements, but no need in restricting. v9: - Fix wrong QGV transition if we have 0 planes and no SAGV simultaneously. v10: - Fix CDCLK corruption, because of global state getting serialized without modeset, which caused copying of non-calculated cdclk to be copied to dev_priv(thanks to Ville for the hint). v11: - Remove unneeded headers and spaces(Matthew Roper) - Remove unneeded intel_qgv_info qi struct from bw check and zero out the needed one(Matthew Roper) - Changed QGV error message to have more clear meaning(Matthew Roper) - Use state->modeset_set instead of any_ms(Matthew Roper) - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used - Keep using crtc_state->hw.active instead of .enable(Matthew Roper) - Moved unrelated changes to other patch(using latency as parameter for plane wm calculation, moved to SAGV refactoring patch) v12: - Fix rebase conflict with own temporary SAGV/QGV fix. - Remove unnecessary mask being zero check when unmasking qgv points as this is completely legal(Matt Roper) - Check if we are setting the same mask as already being set in hardware to prevent error from PCode. - Fix error message when restricting/unrestricting qgv points to "mask/unmask" which sounds more accurate(Matt Roper) - Move sagv status setting to icl_get_bw_info from atomic check as this should be calculated only once.(Matt Roper) - Edited comments for the case when we can't enable SAGV and use only 1 QGV point with highest bandwidth to be more understandable.(Matt Roper) v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä) - Changed comment for zero new_mask in qgv points masking function to better reflect reality(Ville Syrjälä) - Simplified bit mask operation in qgv points masking function (Ville Syrjälä) - Moved intel_qgv_points_mask closer to gen11 SAGV disabling, however this still can't be under modeset condition(Ville Syrjälä) - Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask (Ville Syrjälä) - Extracted PCode changes to separate patch.(Ville Syrjälä) - Now treat num_planes 0 same as 1 to avoid confusion and returning max_bw as 0, which would prevent choosing QGV point having max bandwidth in case if SAGV is not allowed, as per BSpec(Ville Syrjälä) - Do the actual qgv_points_mask swap in the same place as all other global state parts like cdclk are swapped. In the next patch, this all will be moved to bw state as global state, once new global state patch series from Ville lands v14: - Now using global state to serialize access to qgv points - Added global state locking back, otherwise we seem to read bw state in a wrong way. v15: - Added TODO comment for near atomic global state locking in bw code. v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed with Jani Nikula. - Take bw_state_changed flag into use. v17: - Moved qgv point related manipulations next to SAGV code, as those are semantically related(Ville Syrjälä) - Renamed those into intel_sagv_(pre)|(post)_plane_update (Ville Syrjälä) v18: - Move sagv related calls from commit tail into intel_sagv_(pre)|(post)_plane_update(Ville Syrjälä) v19: - Use intel_atomic_get_bw_(old)|(new)_state which is intended for commit tail stage. v20: - Return max bandwidth for 0 planes(Ville) - Constify old_bw_state in bw_atomic_check(Ville) - Removed some debugs(Ville) - Added data rate to debug print when no QGV points(Ville) - Removed some comments(Ville) v21, v22, v23: - Fixed rebase conflict v24: - Changed PCode mask to use ICL_ prefix v25: - Resolved rebase conflict v26: - Removed redundant NULL checks(Ville) - Removed redundant error prints(Ville) v27: - Use device specific drm_err(Ville) - Fixed parenthesis ident reported by checkpatch Line over 100 warns to be fixed together with existing code style. Signed-off-by: Stanislav Lisovskiy Cc: Ville Syrjälä Cc: James Ausmus [vsyrjala: Drop duplicate intel_sagv_{pre,post}_plane_update() prototypes and drop unused NUM_SAGV_POINTS define] Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200514074853.9508-3-stanislav.lisovskiy@intel.com (backported from commit 20f505f2253106f695ba6fa0a415159145a8fb2a resolve conflicts due to DRM_DEBUG_KMS) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/display/intel_bw.c | 136 ++++++++++++++++++------ drivers/gpu/drm/i915/display/intel_bw.h | 9 ++ drivers/gpu/drm/i915/intel_pm.c | 53 ++++++++- 3 files changed, 162 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 9407476a936f..9783066ec34b 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -8,6 +8,9 @@ #include "intel_bw.h" #include "intel_display_types.h" #include "intel_sideband.h" +#include "intel_atomic.h" +#include "intel_pm.h" + /* Parameters for Qclk Geyserville (QGV) */ struct intel_qgv_point { @@ -113,6 +116,26 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv, return 0; } +int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv, + u32 points_mask) +{ + int ret; + + /* bspec says to keep retrying for at least 1 ms */ + ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG, + points_mask, + ICL_PCODE_POINTS_RESTRICTED_MASK, + ICL_PCODE_POINTS_RESTRICTED, + 1); + + if (ret < 0) { + drm_err(&dev_priv->drm, "Failed to disable qgv points (%d)\n", ret); + return ret; + } + + return 0; +} + static int icl_get_qgv_points(struct drm_i915_private *dev_priv, struct intel_qgv_info *qi) { @@ -236,6 +259,16 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel break; } + /* + * In case if SAGV is disabled in BIOS, we always get 1 + * SAGV point, but we can't send PCode commands to restrict it + * as it will fail and pointless anyway. + */ + if (qi.num_points == 1) + dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; + else + dev_priv->sagv_status = I915_SAGV_ENABLED; + return 0; } @@ -244,6 +277,11 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv, { int i; + /* + * Let's return max bw for 0 planes + */ + num_planes = max(1, num_planes); + for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) { const struct intel_bw_info *bi = &dev_priv->max_bw[i]; @@ -273,34 +311,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv) icl_get_bw_info(dev_priv, &icl_sa_info); } -static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv, - int num_planes) -{ - if (INTEL_GEN(dev_priv) >= 11) { - /* - * Any bw group has same amount of QGV points - */ - const struct intel_bw_info *bi = - &dev_priv->max_bw[0]; - unsigned int min_bw = UINT_MAX; - int i; - - /* - * FIXME with SAGV disabled maybe we can assume - * point 1 will always be used? Seems to match - * the behaviour observed in the wild. - */ - for (i = 0; i < bi->num_qgv_points; i++) { - unsigned int bw = icl_max_bw(dev_priv, num_planes, i); - - min_bw = min(bw, min_bw); - } - return min_bw; - } else { - return UINT_MAX; - } -} - static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state) { /* @@ -410,10 +420,15 @@ int intel_bw_atomic_check(struct intel_atomic_state *state) struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc_state *new_crtc_state, *old_crtc_state; struct intel_bw_state *new_bw_state = NULL; - unsigned int data_rate, max_data_rate; + const struct intel_bw_state *old_bw_state = NULL; + unsigned int data_rate; unsigned int num_active_planes; struct intel_crtc *crtc; int i, ret; + u32 allowed_points = 0; + unsigned int max_bw_point = 0, max_bw = 0; + unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points; + u32 mask = (1 << num_qgv_points) - 1; /* FIXME earlier gens need some checks too */ if (INTEL_GEN(dev_priv) < 11) @@ -459,18 +474,71 @@ int intel_bw_atomic_check(struct intel_atomic_state *state) return ret; data_rate = intel_bw_data_rate(dev_priv, new_bw_state); + data_rate = DIV_ROUND_UP(data_rate, 1000); + num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state); - max_data_rate = intel_max_data_rate(dev_priv, num_active_planes); + for (i = 0; i < num_qgv_points; i++) { + unsigned int max_data_rate; - data_rate = DIV_ROUND_UP(data_rate, 1000); + max_data_rate = icl_max_bw(dev_priv, num_active_planes, i); + /* + * We need to know which qgv point gives us + * maximum bandwidth in order to disable SAGV + * if we find that we exceed SAGV block time + * with watermarks. By that moment we already + * have those, as it is calculated earlier in + * intel_atomic_check, + */ + if (max_data_rate > max_bw) { + max_bw_point = i; + max_bw = max_data_rate; + } + if (max_data_rate >= data_rate) + allowed_points |= BIT(i); + drm_dbg_kms(&dev_priv->drm, "QGV point %d: max bw %d required %d\n", + i, max_data_rate, data_rate); + } - if (data_rate > max_data_rate) { - DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n", - data_rate, max_data_rate, num_active_planes); + /* + * BSpec states that we always should have at least one allowed point + * left, so if we couldn't - simply reject the configuration for obvious + * reasons. + */ + if (allowed_points == 0) { + drm_dbg_kms(&dev_priv->drm, "No QGV points provide sufficient memory" + " bandwidth %d for display configuration(%d active planes).\n", + data_rate, num_active_planes); return -EINVAL; } + /* + * Leave only single point with highest bandwidth, if + * we can't enable SAGV due to the increased memory latency it may + * cause. + */ + if (!intel_can_enable_sagv(dev_priv, new_bw_state)) { + allowed_points = BIT(max_bw_point); + drm_dbg_kms(&dev_priv->drm, "No SAGV, using single QGV point %d\n", + max_bw_point); + } + /* + * We store the ones which need to be masked as that is what PCode + * actually accepts as a parameter. + */ + new_bw_state->qgv_points_mask = ~allowed_points & mask; + + old_bw_state = intel_atomic_get_old_bw_state(state); + /* + * If the actual mask had changed we need to make sure that + * the commits are serialized(in case this is a nomodeset, nonblocking) + */ + if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) { + ret = intel_atomic_serialize_global_state(&new_bw_state->base); + if (ret) + return ret; + } + return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h index 898b4a85ccab..bbcaaa73ec1b 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.h +++ b/drivers/gpu/drm/i915/display/intel_bw.h @@ -24,6 +24,13 @@ struct intel_bw_state { */ u8 pipe_sagv_reject; + /* + * Current QGV points mask, which restricts + * some particular SAGV states, not to confuse + * with pipe_sagv_mask. + */ + u8 qgv_points_mask; + unsigned int data_rate[I915_MAX_PIPES]; u8 num_active_planes[I915_MAX_PIPES]; @@ -47,5 +54,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv); int intel_bw_atomic_check(struct intel_atomic_state *state); void intel_bw_crtc_update(struct intel_bw_state *bw_state, const struct intel_crtc_state *crtc_state); +int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv, + u32 points_mask); #endif /* __INTEL_BW_H__ */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 3100f491e9b4..055c2f08d80a 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3748,6 +3748,8 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); const struct intel_bw_state *new_bw_state; + const struct intel_bw_state *old_bw_state; + u32 new_mask = 0; /* * Just return if we can't control SAGV or don't have it. @@ -3763,14 +3765,42 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state) if (!new_bw_state) return; - if (!intel_can_enable_sagv(dev_priv, new_bw_state)) + if (INTEL_GEN(dev_priv) < 11 && !intel_can_enable_sagv(dev_priv, new_bw_state)) { intel_disable_sagv(dev_priv); + return; + } + + old_bw_state = intel_atomic_get_old_bw_state(state); + /* + * Nothing to mask + */ + if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask) + return; + + new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask; + + /* + * If new mask is zero - means there is nothing to mask, + * we can only unmask, which should be done in unmask. + */ + if (!new_mask) + return; + + /* + * Restrict required qgv points before updating the configuration. + * According to BSpec we can't mask and unmask qgv points at the same + * time. Also masking should be done before updating the configuration + * and unmasking afterwards. + */ + icl_pcode_restrict_qgv_points(dev_priv, new_mask); } void intel_sagv_post_plane_update(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); const struct intel_bw_state *new_bw_state; + const struct intel_bw_state *old_bw_state; + u32 new_mask = 0; /* * Just return if we can't control SAGV or don't have it. @@ -3786,8 +3816,27 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state) if (!new_bw_state) return; - if (intel_can_enable_sagv(dev_priv, new_bw_state)) + if (INTEL_GEN(dev_priv) < 11 && intel_can_enable_sagv(dev_priv, new_bw_state)) { intel_enable_sagv(dev_priv); + return; + } + + old_bw_state = intel_atomic_get_old_bw_state(state); + /* + * Nothing to unmask + */ + if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask) + return; + + new_mask = new_bw_state->qgv_points_mask; + + /* + * Allow required qgv points after updating the configuration. + * According to BSpec we can't mask and unmask qgv points at the same + * time. Also masking should be done before updating the configuration + * and unmasking afterwards. + */ + icl_pcode_restrict_qgv_points(dev_priv, new_mask); } static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) From patchwork Fri Aug 14 06:57:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: You-Sheng Yang X-Patchwork-Id: 1344687 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BSZ743vFmz9sTR; Fri, 14 Aug 2020 16:59:28 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1k6TgS-0000I7-Bv; Fri, 14 Aug 2020 06:59:24 +0000 Received: from mail-pf1-f194.google.com ([209.85.210.194]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1k6TgI-0008S0-HQ for kernel-team@lists.ubuntu.com; Fri, 14 Aug 2020 06:59:14 +0000 Received: by mail-pf1-f194.google.com with SMTP id d22so4107926pfn.5 for ; Thu, 13 Aug 2020 23:59:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZqPnopknWMYP51K8SSbbOcZ8UTR4Z60zQZ5SHh3e/RY=; b=VRcOPXfwQz4iFTbWIYjURdVLwCeL4/NJYUdK95ItYtvveSxWxuCzCyVYjcTJfojDmB M805wcyMSmvGkigR0Qbsny5FaL48Ub0TS9i8P4oTwIUhUJ+i4kNY5IDI6KpVmFRaWWce Bj94cv/liZfPUhCObZQSoCK5WH36RMTbfYHqewkpcAYi2nOySFGsSqtBdqdvh1AB3vtp LI1KBBH2LKB5KiCX/oUB7a99tMrzDNUZ3GHkcuZEGErNXe4JHV7IJzizRsIJBtLej+Xw EzXp5Aoo3wbq01J0wAMLHY7OOuBeJYFkkYPf6Cuzj4v7whe9xwS4O1N/U7jTl+EH+ciZ 58PQ== X-Gm-Message-State: AOAM533R4q2gRJvHK5vX16DIEHTSmjTOuGfQAlBQBe0bdhOXyaTqfcmQ 4mNlSIi7R/Cemagj2KLMPCmjWjOLWLlS8A== X-Google-Smtp-Source: ABdhPJwsf0VvYjtRdHX8hQqKn7VONZb057sqQ/Xz1U8Rv15IvDYS0fCoV98ih3pEt7NJKdK9808Zzw== X-Received: by 2002:a63:cf03:: with SMTP id j3mr890620pgg.198.1597388343343; Thu, 13 Aug 2020 23:59:03 -0700 (PDT) Received: from localhost (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id q5sm7127496pgv.1.2020.08.13.23.59.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2020 23:59:02 -0700 (PDT) From: You-Sheng Yang To: kernel-team@lists.ubuntu.com Subject: [PATCH 31/31][SRU][OEM-5.6] drm/i915: Enable SAGV support for Gen12 Date: Fri, 14 Aug 2020 14:57:40 +0800 Message-Id: <20200814065740.276039-32-vicamo.yang@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200814065740.276039-1-vicamo.yang@canonical.com> References: <20200814065740.276039-1-vicamo.yang@canonical.com> MIME-Version: 1.0 Received-SPF: pass client-ip=209.85.210.194; envelope-from=vicamo@gmail.com; helo=mail-pf1-f194.google.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Stanislav Lisovskiy BugLink: https://bugs.launchpad.net/bugs/1891451 Flip the switch and enable SAGV support for Gen12 also. Signed-off-by: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20200514074853.9508-4-stanislav.lisovskiy@intel.com (cherry picked from commit 8ca6d0237d1696060cd4f5a3ee93ee001c1a9d5b) Signed-off-by: You-Sheng Yang --- drivers/gpu/drm/i915/intel_pm.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 055c2f08d80a..64bb1ed95755 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3624,10 +3624,6 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv) static bool intel_has_sagv(struct drm_i915_private *dev_priv) { - /* HACK! */ - if (IS_GEN(dev_priv, 12)) - return false; - return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) && dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED; }