From patchwork Fri Aug 7 08:10:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haibo Xu X-Patchwork-Id: 1342130 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=hCzc8Gm9; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BNJ4Y6PXmz9sPB for ; Fri, 7 Aug 2020 18:12:29 +1000 (AEST) Received: from localhost ([::1]:41936 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k3xUJ-0000aN-Ir for incoming@patchwork.ozlabs.org; Fri, 07 Aug 2020 04:12:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45646) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k3xSf-00070N-QL for qemu-devel@nongnu.org; Fri, 07 Aug 2020 04:10:45 -0400 Received: from mail-io1-xd33.google.com ([2607:f8b0:4864:20::d33]:41444) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1k3xSc-0001h6-EG for qemu-devel@nongnu.org; Fri, 07 Aug 2020 04:10:45 -0400 Received: by mail-io1-xd33.google.com with SMTP id g19so1057948ioh.8 for ; Fri, 07 Aug 2020 01:10:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SVvavflqwBHyVfPeo3WkPtz2sD2s7cZLSNZLl+ZfUO0=; b=hCzc8Gm9b7h0j1Hij+WDaaowmrvNimX4GLIJ5eYjCHwjLaascuNQMt4q+J1JY/4Egr uYe8ayQhzwq6LZ0iGU+UFPdVhqcOygM+IVAGdQMAP71UCUtiB6XDeHv0i3ktSYYwr2uP eMtQw6Si0k/wMY5beDVkS8SlIpYS/3B+4WGpvmBdKYa1Cu5fJnsnWSKN9D9L/wedDaq4 QJid3NW4x6U0Cet/0OgnNq78Q0N7ShXFVbK4GKGz+TBuYPbyyTjCFjn+Tse0rA6yDURL jxd3Mk9CohNsdBvLw++zalcMUvml5kuc4NDbB1bSTtQc3eo7a2RxvyUf/CU/h/Glh5Zd 1vfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SVvavflqwBHyVfPeo3WkPtz2sD2s7cZLSNZLl+ZfUO0=; b=PSgN7oeBkaKY3+BZ5WMjAUTEcldEcXip7Wst4WKHsFV59qFQYLPCKQ9Lm2yZAOXEMN BDHiLXRk6E0jjKj/r9RNffGRIARWg2Lf9J6ODEHIt6Ak0fpRFc9v8qoG2ma3WLu1vsYx hjYnRLjPs1qh9aPgpdOevAeWHa7msqEUwaW1Fhh2hIudcD9bjesumyyuaJY4pusEBL6u su6pr2QaWrbYK/mgOYZdyZWP2JMg6K5GYHvtFynfO+DYp6QzvvwKHLhvy+MYzGU0V3/w dckNdxQaFC/NxoXC4CLl8poheFwcShBeIMtPrSV6tpdk8kGxdt0NywXuK98kheHZ5Ajx ZiJQ== X-Gm-Message-State: AOAM53018rkNm5AzX3mSCnOv3iAJq+bzhD9IX03xipNxdD9NGyPlHdnX v8g9tz5GcCOAZBWJ09bRbrFN X-Google-Smtp-Source: ABdhPJxMCDuVYAdFWPKtjS2mFGhjatwW/Vq2uyACdZmA3eYiEiwVWLCuz7TpVRTtj1vWL180HFsHvw== X-Received: by 2002:a6b:8b10:: with SMTP id n16mr3242360iod.11.1596787841141; Fri, 07 Aug 2020 01:10:41 -0700 (PDT) Received: from localhost.localdomain ([147.75.106.138]) by smtp.gmail.com with ESMTPSA id l144sm6233546ill.6.2020.08.07.01.10.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2020 01:10:40 -0700 (PDT) From: Haibo Xu To: peter.maydell@linaro.org Subject: [PATCH 1/7] update Linux headers with new vSPE macros Date: Fri, 7 Aug 2020 08:10:31 +0000 Message-Id: <4da5af14d6f0c0adb112d04eafa0a488ab924439.1596768588.git.haibo.xu@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d33; envelope-from=haibo.xu@linaro.org; helo=mail-io1-xd33.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drjones@redhat.com, qemu-arm@nongnu.org, philmd@redhat.com, qemu-devel@nongnu.org, Haibo Xu Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Haibo Xu --- linux-headers/asm-arm64/kvm.h | 4 ++++ linux-headers/linux/kvm.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h index 9e34f0f875..802319ee02 100644 --- a/linux-headers/asm-arm64/kvm.h +++ b/linux-headers/asm-arm64/kvm.h @@ -106,6 +106,7 @@ struct kvm_regs { #define KVM_ARM_VCPU_SVE 4 /* enable SVE for this CPU */ #define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 /* VCPU uses address authentication */ #define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */ +#define KVM_ARM_VCPU_SPE_V1 7 /* Support guest SPEv1 */ struct kvm_vcpu_init { __u32 target; @@ -334,6 +335,9 @@ struct kvm_vcpu_events { #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 #define KVM_ARM_VCPU_PVTIME_CTRL 2 #define KVM_ARM_VCPU_PVTIME_IPA 0 +#define KVM_ARM_VCPU_SPE_V1_CTRL 3 +#define KVM_ARM_VCPU_SPE_V1_IRQ 0 +#define KVM_ARM_VCPU_SPE_V1_INIT 1 /* KVM_IRQ_LINE irq field index values */ #define KVM_ARM_IRQ_VCPU2_SHIFT 28 diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index a28c366737..35ef0ae842 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -1031,6 +1031,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_PPC_SECURE_GUEST 181 #define KVM_CAP_HALT_POLL 182 #define KVM_CAP_ASYNC_PF_INT 183 +#define KVM_CAP_ARM_SPE_V1 184 #ifdef KVM_CAP_IRQ_ROUTING @@ -1671,6 +1672,7 @@ struct kvm_assigned_msix_entry { #define KVM_ARM_DEV_EL1_VTIMER (1 << 0) #define KVM_ARM_DEV_EL1_PTIMER (1 << 1) #define KVM_ARM_DEV_PMU (1 << 2) +#define KVM_ARM_DEV_SPE (1 << 3) struct kvm_hyperv_eventfd { __u32 conn_id; From patchwork Fri Aug 7 08:10:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haibo Xu X-Patchwork-Id: 1342134 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=VMRerHch; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BNJ686zNTz9sPB for ; Fri, 7 Aug 2020 18:13:52 +1000 (AEST) Received: from localhost ([::1]:50498 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k3xVe-00041w-Lg for incoming@patchwork.ozlabs.org; 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Fri, 07 Aug 2020 01:10:41 -0700 (PDT) From: Haibo Xu To: peter.maydell@linaro.org Subject: [PATCH 2/7] target/arm/kvm: spe: Add helper to detect SPE when using KVM Date: Fri, 7 Aug 2020 08:10:32 +0000 Message-Id: <76aa68f9ec73ced85070b81ef5251771ca27d072.1596768588.git.haibo.xu@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::141; envelope-from=haibo.xu@linaro.org; helo=mail-il1-x141.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drjones@redhat.com, qemu-arm@nongnu.org, philmd@redhat.com, qemu-devel@nongnu.org, Haibo Xu Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Haibo Xu Reviewed-by: Richard Henderson --- target/arm/kvm.c | 5 +++++ target/arm/kvm_arm.h | 13 +++++++++++++ 2 files changed, 18 insertions(+) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 8bb7318378..58f991e890 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -214,6 +214,11 @@ bool kvm_arm_pmu_supported(void) return kvm_check_extension(kvm_state, KVM_CAP_ARM_PMU_V3); } +bool kvm_arm_spe_supported(void) +{ + return kvm_check_extension(kvm_state, KVM_CAP_ARM_SPE_V1); +} + int kvm_arm_get_max_vm_ipa_size(MachineState *ms) { KVMState *s = KVM_STATE(ms->accelerator); diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index adb38514bf..f79655674e 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -283,6 +283,14 @@ bool kvm_arm_aarch32_supported(void); */ bool kvm_arm_pmu_supported(void); +/** + * kvm_arm_spe_supported: + * + * Returns: true if the KVM VCPU can enable its SPE + * and false otherwise. + */ +bool kvm_arm_spe_supported(void); + /** * kvm_arm_sve_supported: * @@ -366,6 +374,11 @@ static inline bool kvm_arm_pmu_supported(void) return false; } +static inline bool kvm_arm_spe_supported(void) +{ + return false; +} + static inline bool kvm_arm_sve_supported(void) { return false; From patchwork Fri Aug 7 08:10:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haibo Xu X-Patchwork-Id: 1342131 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Fri, 07 Aug 2020 01:10:42 -0700 (PDT) From: Haibo Xu To: peter.maydell@linaro.org Subject: [PATCH 3/7] target/arm/cpu: spe: Add an option to turn on/off vSPE support Date: Fri, 7 Aug 2020 08:10:33 +0000 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d43; envelope-from=haibo.xu@linaro.org; helo=mail-io1-xd43.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drjones@redhat.com, qemu-arm@nongnu.org, philmd@redhat.com, qemu-devel@nongnu.org, Haibo Xu Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Adds a spe=[on/off] option to enable/disable vSPE support in guest vCPU. Note this option is only available for "-cpu host" with KVM mode, and default value is on. Signed-off-by: Haibo Xu --- target/arm/cpu.c | 28 ++++++++++++++++++++++++++++ target/arm/cpu.h | 3 +++ 2 files changed, 31 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 111579554f..40768b4d19 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1122,6 +1122,29 @@ static void arm_set_pmu(Object *obj, bool value, Error **errp) cpu->has_pmu = value; } +static bool arm_get_spe(Object *obj, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + + return cpu->has_spe; +} + +static void arm_set_spe(Object *obj, bool value, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + + if (value) { + if (kvm_enabled() && !kvm_arm_spe_supported()) { + error_setg(errp, "'spe' feature not supported by KVM on this host"); + return; + } + set_feature(&cpu->env, ARM_FEATURE_SPE); + } else { + unset_feature(&cpu->env, ARM_FEATURE_SPE); + } + cpu->has_spe = value; +} + unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) { /* @@ -1195,6 +1218,11 @@ void arm_cpu_post_init(Object *obj) object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); } + if (arm_feature(&cpu->env, ARM_FEATURE_SPE)) { + cpu->has_spe = true; + object_property_add_bool(obj, "spe", arm_get_spe, arm_set_spe); + } + /* * Allow user to turn off VFP and Neon support, but only for TCG -- * KVM does not currently allow us to lie to the guest about its diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9e8ed423ea..fe0ac14386 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -822,6 +822,8 @@ struct ARMCPU { bool has_el3; /* CPU has PMU (Performance Monitor Unit) */ bool has_pmu; + /* CPU has SPE (Statistical Profiling Extension) */ + bool has_spe; /* CPU has VFP */ bool has_vfp; /* CPU has Neon */ @@ -1959,6 +1961,7 @@ enum arm_features { ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_M_MAIN, /* M profile Main Extension */ + ARM_FEATURE_SPE, /* has SPE support */ }; static inline int arm_feature(CPUARMState *env, int feature) From patchwork Fri Aug 7 08:10:34 2020 Content-Type: text/plain; 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Fri, 07 Aug 2020 01:10:43 -0700 (PDT) From: Haibo Xu To: peter.maydell@linaro.org Subject: [PATCH 4/7] target/arm/kvm: spe: Unify device attr operatioin helper Date: Fri, 7 Aug 2020 08:10:34 +0000 Message-Id: <3cc31df5191ae6b03e060ccd8e82df74416a3ef5.1596768588.git.haibo.xu@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::142; envelope-from=haibo.xu@linaro.org; helo=mail-il1-x142.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drjones@redhat.com, qemu-arm@nongnu.org, philmd@redhat.com, qemu-devel@nongnu.org, Haibo Xu Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Rename kvm_arm_pmu_set_attr() to kvm_arm_dev_set_attr(), So both the vPMU and vSPE device can share the same API. Signed-off-by: Haibo Xu Reviewed-by: Philippe Mathieu-Daudé --- target/arm/kvm64.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 1169237905..75a417d65c 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -398,7 +398,7 @@ static CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, target_ulong addr) return NULL; } -static bool kvm_arm_pmu_set_attr(CPUState *cs, struct kvm_device_attr *attr) +static bool kvm_arm_dev_set_attr(CPUState *cs, struct kvm_device_attr *attr) { int err; @@ -427,7 +427,7 @@ void kvm_arm_pmu_init(CPUState *cs) if (!ARM_CPU(cs)->has_pmu) { return; } - if (!kvm_arm_pmu_set_attr(cs, &attr)) { + if (!kvm_arm_dev_set_attr(cs, &attr)) { error_report("failed to init PMU"); abort(); } @@ -444,7 +444,7 @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq) if (!ARM_CPU(cs)->has_pmu) { return; } - if (!kvm_arm_pmu_set_attr(cs, &attr)) { + if (!kvm_arm_dev_set_attr(cs, &attr)) { error_report("failed to set irq for PMU"); abort(); } From patchwork Fri Aug 7 08:10:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haibo Xu X-Patchwork-Id: 1342133 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=cJ/kFwfh; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BNJ5V6ZV5z9sTN for ; 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Fri, 07 Aug 2020 01:10:44 -0700 (PDT) Received: from localhost.localdomain ([147.75.106.138]) by smtp.gmail.com with ESMTPSA id l144sm6233546ill.6.2020.08.07.01.10.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2020 01:10:44 -0700 (PDT) From: Haibo Xu To: peter.maydell@linaro.org Subject: [PATCH 5/7] target/arm/kvm: spe: Add device init and set_irq operations Date: Fri, 7 Aug 2020 08:10:35 +0000 Message-Id: <3160507b3f981c92857d3234468d3de1dd352a03.1596768588.git.haibo.xu@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::142; envelope-from=haibo.xu@linaro.org; helo=mail-il1-x142.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drjones@redhat.com, qemu-arm@nongnu.org, philmd@redhat.com, qemu-devel@nongnu.org, Haibo Xu Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Haibo Xu --- target/arm/kvm64.c | 33 +++++++++++++++++++++++++++++++++ target/arm/kvm_arm.h | 5 +++++ 2 files changed, 38 insertions(+) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 75a417d65c..be045ccc5f 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -450,6 +450,39 @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq) } } +void kvm_arm_spe_init(CPUState *cs) +{ + struct kvm_device_attr attr = { + .group = KVM_ARM_VCPU_SPE_V1_CTRL, + .attr = KVM_ARM_VCPU_SPE_V1_INIT, + }; + + if (!ARM_CPU(cs)->has_spe) { + return; + } + if (!kvm_arm_dev_set_attr(cs, &attr)) { + error_report("failed to init SPE"); + abort(); + } +} + +void kvm_arm_spe_set_irq(CPUState *cs, int irq) +{ + struct kvm_device_attr attr = { + .group = KVM_ARM_VCPU_SPE_V1_CTRL, + .addr = (intptr_t)&irq, + .attr = KVM_ARM_VCPU_SPE_V1_IRQ, + }; + + if (!ARM_CPU(cs)->has_spe) { + return; + } + if (!kvm_arm_dev_set_attr(cs, &attr)) { + error_report("failed to set irq for SPE"); + abort(); + } +} + static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) { uint64_t ret; diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index f79655674e..bb155322eb 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -348,6 +348,8 @@ int kvm_arm_vgic_probe(void); void kvm_arm_pmu_set_irq(CPUState *cs, int irq); void kvm_arm_pmu_init(CPUState *cs); +void kvm_arm_spe_set_irq(CPUState *cs, int irq); +void kvm_arm_spe_init(CPUState *cs); int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level); #else @@ -397,6 +399,9 @@ static inline int kvm_arm_vgic_probe(void) static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) {} static inline void kvm_arm_pmu_init(CPUState *cs) {} +static inline void kvm_arm_spe_set_irq(CPUState *cs, int irq) {} +static inline void kvm_arm_spe_init(CPUState *cs) {} + static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) {} static inline void kvm_arm_get_virtual_time(CPUState *cs) {} From patchwork Fri Aug 7 08:10:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haibo Xu X-Patchwork-Id: 1342135 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; 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Fri, 07 Aug 2020 01:10:45 -0700 (PDT) Received: from localhost.localdomain ([147.75.106.138]) by smtp.gmail.com with ESMTPSA id l144sm6233546ill.6.2020.08.07.01.10.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2020 01:10:45 -0700 (PDT) From: Haibo Xu To: peter.maydell@linaro.org Subject: [PATCH 6/7] hw/arm/virt: spe: Add SPE fdt binding for virt machine Date: Fri, 7 Aug 2020 08:10:36 +0000 Message-Id: <1663d06172cffa723e00893837ba04634f061fc8.1596768588.git.haibo.xu@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d41; envelope-from=haibo.xu@linaro.org; helo=mail-io1-xd41.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drjones@redhat.com, qemu-arm@nongnu.org, philmd@redhat.com, qemu-devel@nongnu.org, Haibo Xu Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add a virtual SPE device for virt machine while using PPI 5 for SPE overflow interrupt number. Signed-off-by: Haibo Xu --- hw/arm/virt-acpi-build.c | 3 +++ hw/arm/virt.c | 42 +++++++++++++++++++++++++++++++++++++ include/hw/acpi/acpi-defs.h | 1 + include/hw/arm/virt.h | 1 + target/arm/cpu.c | 2 ++ target/arm/cpu.h | 2 ++ target/arm/kvm.c | 6 ++++++ 7 files changed, 57 insertions(+) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 91f0df7b13..5073ba22a5 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -666,6 +666,9 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ)); } + if (arm_feature(&armcpu->env, ARM_FEATURE_SPE)) { + gicc->spe_interrupt = cpu_to_le32(PPI(VIRTUAL_SPE_IRQ)); + } if (vms->virt) { gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ)); } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ecfee362a1..c40819705d 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -555,6 +555,42 @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms) } } +static void fdt_add_spe_nodes(const VirtMachineState *vms) +{ + CPUState *cpu; + ARMCPU *armcpu; + uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; + + CPU_FOREACH(cpu) { + armcpu = ARM_CPU(cpu); + if (!arm_feature(&armcpu->env, ARM_FEATURE_SPE)) { + return; + } + if (kvm_enabled()) { + if (kvm_irqchip_in_kernel()) { + kvm_arm_spe_set_irq(cpu, PPI(VIRTUAL_SPE_IRQ)); + } + kvm_arm_spe_init(cpu); + } + } + + if (vms->gic_version == VIRT_GIC_VERSION_2) { + irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, + GIC_FDT_IRQ_PPI_CPU_WIDTH, + (1 << vms->smp_cpus) - 1); + } + + armcpu = ARM_CPU(qemu_get_cpu(0)); + qemu_fdt_add_subnode(vms->fdt, "/spe"); + if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { + const char compat[] = "arm,statistical-profiling-extension-v1"; + qemu_fdt_setprop(vms->fdt, "/spe", "compatible", + compat, sizeof(compat)); + qemu_fdt_setprop_cells(vms->fdt, "/spe", "interrupts", + GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_SPE_IRQ, irqflags); + } +} + static inline DeviceState *create_acpi_ged(VirtMachineState *vms) { DeviceState *dev; @@ -727,6 +763,10 @@ static void create_gic(VirtMachineState *vms) qdev_get_gpio_in(vms->gic, ppibase + VIRTUAL_PMU_IRQ)); + qdev_connect_gpio_out_named(cpudev, "spe-interrupt", 0, + qdev_get_gpio_in(vms->gic, ppibase + + VIRTUAL_SPE_IRQ)); + sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); sysbus_connect_irq(gicbusdev, i + smp_cpus, qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); @@ -1915,6 +1955,8 @@ static void machvirt_init(MachineState *machine) fdt_add_pmu_nodes(vms); + fdt_add_spe_nodes(vms); + create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); if (vms->secure) { diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 38a42f409a..56a7f38ae4 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -302,6 +302,7 @@ struct AcpiMadtGenericCpuInterface { uint32_t vgic_interrupt; uint64_t gicr_base_address; uint64_t arm_mpidr; + uint16_t spe_interrupt; /* ACPI 6.3 */ } QEMU_PACKED; typedef struct AcpiMadtGenericCpuInterface AcpiMadtGenericCpuInterface; diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index dff67e1bef..56c83224d2 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -49,6 +49,7 @@ #define ARCH_TIMER_NS_EL1_IRQ 14 #define ARCH_TIMER_NS_EL2_IRQ 10 +#define VIRTUAL_SPE_IRQ 5 #define VIRTUAL_PMU_IRQ 7 #define PPI(irq) ((irq) + 16) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 40768b4d19..67ab0089fd 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1038,6 +1038,8 @@ static void arm_cpu_initfn(Object *obj) "gicv3-maintenance-interrupt", 1); qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, "pmu-interrupt", 1); + qdev_init_gpio_out_named(DEVICE(cpu), &cpu->spe_interrupt, + "spe-interrupt", 1); #endif /* DTB consumers generally don't in fact care what the 'compatible' diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fe0ac14386..4bf8591df8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -790,6 +790,8 @@ struct ARMCPU { qemu_irq gicv3_maintenance_interrupt; /* GPIO output for the PMU interrupt */ qemu_irq pmu_interrupt; + /* GPIO output for the SPE interrupt */ + qemu_irq spe_interrupt; /* MemoryRegion to use for secure physical accesses */ MemoryRegion *secure_memory; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 58f991e890..ecafdda364 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -820,6 +820,12 @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) switched_level &= ~KVM_ARM_DEV_PMU; } + if (switched_level & KVM_ARM_DEV_SPE) { + qemu_set_irq(cpu->spe_interrupt, + !!(run->s.regs.device_irq_level & KVM_ARM_DEV_SPE)); + switched_level &= ~KVM_ARM_DEV_SPE; + } + if (switched_level) { qemu_log_mask(LOG_UNIMP, "%s: unhandled in-kernel device IRQ %x\n", __func__, switched_level); From patchwork Fri Aug 7 08:10:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haibo Xu X-Patchwork-Id: 1342136 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=NnLuiKB3; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BNJ7Y0p3Dz9sPB for ; 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Fri, 07 Aug 2020 01:10:46 -0700 (PDT) Received: from localhost.localdomain ([147.75.106.138]) by smtp.gmail.com with ESMTPSA id l144sm6233546ill.6.2020.08.07.01.10.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2020 01:10:46 -0700 (PDT) From: Haibo Xu To: peter.maydell@linaro.org Subject: [PATCH 7/7] target/arm/cpu: spe: Enable spe to work with host cpu Date: Fri, 7 Aug 2020 08:10:37 +0000 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d44; envelope-from=haibo.xu@linaro.org; helo=mail-io1-xd44.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drjones@redhat.com, qemu-arm@nongnu.org, philmd@redhat.com, qemu-devel@nongnu.org, Haibo Xu Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Turn on the spe cpu property by default when working with host cpu type in KVM mode, i.e. we can now do '-cpu host' to add the vSPE, and '-cpu host,spe=off' to remove it. Signed-off-by: Haibo Xu --- target/arm/cpu.c | 4 ++++ target/arm/kvm64.c | 9 +++++++++ 2 files changed, 13 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 67ab0089fd..42fa99953c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1719,6 +1719,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) cpu->pmceid1 = 0; } + if (!cpu->has_spe || !kvm_enabled()) { + unset_feature(env, ARM_FEATURE_SPE); + } + if (!arm_feature(env, ARM_FEATURE_EL2)) { /* Disable the hypervisor feature bits in the processor feature * registers if we don't have EL2. These are id_pfr1[15:12] and diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index be045ccc5f..4ea58afc1d 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -679,6 +679,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) features |= 1ULL << ARM_FEATURE_AARCH64; features |= 1ULL << ARM_FEATURE_PMU; features |= 1ULL << ARM_FEATURE_GENERIC_TIMER; + features |= 1ULL << ARM_FEATURE_SPE; ahcf->features = features; @@ -826,6 +827,14 @@ int kvm_arch_init_vcpu(CPUState *cs) } else { env->features &= ~(1ULL << ARM_FEATURE_PMU); } + if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_SPE_V1)) { + cpu->has_spe = false; + } + if (cpu->has_spe) { + cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_SPE_V1; + } else { + env->features &= ~(1ULL << ARM_FEATURE_SPE); + } if (cpu_isar_feature(aa64_sve, cpu)) { assert(kvm_arm_sve_supported()); cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_SVE;