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Wed, 5 Aug 2020 19:02:37 +0000 (GMT) Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 46AB078067; Wed, 5 Aug 2020 19:02:37 +0000 (GMT) Received: from [9.65.195.179] (unknown [9.65.195.179]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 5 Aug 2020 19:02:37 +0000 (GMT) To: Segher Boessenkool Subject: [PATCH] rs6000: Don't ICE when spilling an MMA accumulator Message-ID: <6dfd029c-e1f3-cb12-fb2c-7d0c703f43f5@linux.ibm.com> Date: Wed, 5 Aug 2020 14:02:36 -0500 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.14; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-05_14:2020-08-03, 2020-08-05 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 mlxscore=0 suspectscore=0 bulkscore=0 phishscore=0 mlxlogscore=999 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008050145 X-Spam-Status: No, score=-10.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Peter Bergner via Gcc-patches From: Peter Bergner Reply-To: Peter Bergner Cc: GCC Patches Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" The following patch fixes one of the bugs discovered in PR96466, namely when we spill an accumulator that has a known zero value. In that case, LRA would emit a new (set (reg:PXI ...) 0) insn, but it would not use the mma_xxsetaccz pattern to do it. The solution is to move the xxsetaccz instruction into the movpxi pattern and have the xxsetaccz pattern call the move pattern. This patch fixes the ICE and is in the middle of regression testing. Ok for trunk if the testing comes back clean? This is also broken in GCC 10, so ok there after sitting on trunk for a day or two with no fallout? Peter gcc/ PR target/96446 * gcc/config/rs6000/mma.md (*movpxi): Add xxsetaccz generation. Disable split for zero constant source operand. (mma_xxsetaccz): Change to define_expand. Call gen_movpxi. gcc/testsuite/ PR target/96446 * gcc.target/powerpc/pr96446.c: New test. diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md index 15cacfb7fc1..fcca02bfa9f 100644 --- a/gcc/config/rs6000/mma.md +++ b/gcc/config/rs6000/mma.md @@ -328,11 +328,17 @@ [(set (match_operand:PXI 0 "nonimmediate_operand" "=d,m,d,d") (match_operand:PXI 1 "input_operand" "m,d,d,O"))] "TARGET_MMA - && ((gpc_reg_operand (operands[0], PXImode) - && !(CONST_INT_P (operands[1]) && INTVAL (operands[1]) == 0)) + && (gpc_reg_operand (operands[0], PXImode) || gpc_reg_operand (operands[1], PXImode))" - "#" - "&& reload_completed" + "@ + # + # + # + xxsetaccz %A0" + "&& reload_completed + && !(fpr_reg_operand (operands[0], PXImode) + && CONST_INT_P (operands[1]) + && INTVAL (operands[1]) == 0)" [(const_int 0)] { rs6000_split_multireg_move (operands[0], operands[1]); @@ -409,12 +415,14 @@ " %A0" [(set_attr "type" "mma")]) -(define_insn "mma_xxsetaccz" - [(set (match_operand:PXI 0 "fpr_reg_operand" "=d") +(define_expand "mma_xxsetaccz" + [(set (match_operand:PXI 0 "fpr_reg_operand") (const_int 0))] "TARGET_MMA" - "xxsetaccz %A0" - [(set_attr "type" "mma")]) +{ + emit_insn (gen_movpxi (operands[0], const0_rtx)); + DONE; +}) (define_insn "mma_" [(set (match_operand:PXI 0 "fpr_reg_operand" "=&d") diff --git a/gcc/testsuite/gcc.target/powerpc/pr96446.c b/gcc/testsuite/gcc.target/powerpc/pr96446.c new file mode 100644 index 00000000000..2083bf4a76a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr96446.c @@ -0,0 +1,16 @@ +/* PR target/96466 */ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ + +/* Verify we do not ICE on the following. */ + +extern void bar0 (void); +void +foo0 (__vector_quad *dst) +{ + __vector_quad acc; + __builtin_mma_xxsetaccz (&acc); + bar0 (); + *dst = acc; +}