From patchwork Wed Aug 5 03:58:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1341076 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BLyY76VvCz9sPB for ; Wed, 5 Aug 2020 13:59:05 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9692C81269; Wed, 5 Aug 2020 05:58:53 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 4455681B50; Wed, 5 Aug 2020 05:58:52 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id CFAE181260 for ; Wed, 5 Aug 2020 05:58:47 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tien.fong.chee@intel.com IronPort-SDR: duOrYAZ2ezXo+EkP5nUlUOnHiM1G162MxGoz5o0qJc4ThWNJNHHfxVqk8yG2bDo5WlEf2EiOdm /wmQHT1wqbBg== X-IronPort-AV: E=McAfee;i="6000,8403,9703"; a="152429870" X-IronPort-AV: E=Sophos;i="5.75,436,1589266800"; d="scan'208";a="152429870" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2020 20:58:43 -0700 IronPort-SDR: 1sMaSSTD5VwOm/oMTmYI+F3WrTeBgzM/gM0aHUHRalJwZF8uCEL/qd+0Nl2KqBMs4JNbWEWn4V CLnc99wcVOmg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,436,1589266800"; d="scan'208";a="493142002" Received: from sj-iccf0135.altera.com ([10.100.9.116]) by fmsmga005.fm.intel.com with ESMTP; 04 Aug 2020 20:58:43 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Cc: Simon Goldschmidt , Marek Vasut , Chin Liang , Ley Foon , Siew Chin , Chee Hong , Tien Fong Chee Subject: [PATCH] ddr: socfpga: Fix integer overflow that caused DDR size mismatched Date: Tue, 4 Aug 2020 20:58:40 -0700 Message-Id: <20200805035840.22467-1-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.13.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee Convert the constant integer to 'phys_size_t' to avoid overflow when calculating the SDRAM size. Signed-off-by: Tien Fong Chee Reviewed-by: Ley Foon Tan --- drivers/ddr/altera/sdram_soc64.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index 8cb75fe02a..a862ac8092 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -218,13 +218,14 @@ phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat) { u32 dramaddrw = hmc_readl(plat, DRAMADDRW); - phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + - DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) + - DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + - DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + - DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw)); - - size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) & + phys_size_t size = (phys_size_t)1 << + (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw)); + + size *= ((phys_size_t)2 << (hmc_ecc_readl(plat, DDRIOCTRL) & DDR_HMC_DDRIOCTRL_IOSIZE_MSK)); return size;