From patchwork Tue Dec 19 09:31:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 850734 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="XlkSPslo"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3z1CP24xj6z9s82 for ; Tue, 19 Dec 2017 20:32:38 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966790AbdLSJcg (ORCPT ); Tue, 19 Dec 2017 04:32:36 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:15660 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932971AbdLSJc2 (ORCPT ); Tue, 19 Dec 2017 04:32:28 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id vBJ9VoG5030820; Tue, 19 Dec 2017 03:31:50 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1513675910; bh=sxGvI5O1JpQQsebqrxB/n5iwZatgZP2abKeKglZPFR0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=XlkSPslo9OjJXY+w0ExnVDUMPCPIIZdzqxhX2us0FPAeve/f9gXNb3D7fhFg+8lFp tFvHAiMRfsR/JF+gHbQ1Eb4moJMSdNdz6gysDMi9HPbAXpDTeZu0z3tr2w+PY0y+f3 DhIbrY+ZuZwWGLkiT7WaslTm/ENGsb4Xti9Qn3Ak= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ9Vovi015295; Tue, 19 Dec 2017 03:31:50 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 19 Dec 2017 03:31:49 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 19 Dec 2017 03:31:49 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ9VgHu012627; Tue, 19 Dec 2017 03:31:46 -0600 From: Kishon Vijay Abraham I To: Tony Lindgren , CC: Rob Herring , Mark Rutland , Russell King , , , , , , , Subject: [PATCH 1/7] ARM: dts: dra7: Add properties to enable PCIe x2 lane mode Date: Tue, 19 Dec 2017 15:01:27 +0530 Message-ID: <20171219093133.16565-2-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171219093133.16565-1-kishon@ti.com> References: <20171219093133.16565-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org ti,syscon-lane-sel and ti,syscon-lane-conf properties specific to enable PCIe x2 lane mode are added here. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/dra7.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index ac9216293b7c..9966d82dbd7c 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -309,6 +309,8 @@ ti,hwmods = "pcie1"; phys = <&pcie1_phy>; phy-names = "pcie-phy0"; + ti,syscon-lane-conf = <&scm_conf 0x558>; + ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie1_intc 1>, <0 0 0 2 &pcie1_intc 2>, @@ -334,6 +336,8 @@ phys = <&pcie1_phy>; phy-names = "pcie-phy0"; ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; + ti,syscon-lane-conf = <&scm_conf 0x558>; + ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; status = "disabled"; }; }; From patchwork Tue Dec 19 09:31:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 850742 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="joBWbxnD"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3z1CRx67wWz9s72 for ; Tue, 19 Dec 2017 20:35:09 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966805AbdLSJcj (ORCPT ); Tue, 19 Dec 2017 04:32:39 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:15663 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936615AbdLSJc3 (ORCPT ); Tue, 19 Dec 2017 04:32:29 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id vBJ9Vr5r030824; Tue, 19 Dec 2017 03:31:53 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1513675913; bh=wsnH+UC4I5sAayYmmmXexrMc6LVJBIqQ6Bcp9IU+fjk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=joBWbxnDGE3Lyu9FQ9sJIHQNwLFogLmZwK9ycEm5+gumIafmeSc2ZcOCv21dIV6d5 Dp0sfLjz6TAyZIoJUgs6qTGVtwaJq//8iY7yT4l7eaqz2gjYrN7hlQkyrl1v6erEM4 a6tg4XlKuqeii02SZZoyqv0zrMo62KW3zlK17v0o= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ9VrmY015648; Tue, 19 Dec 2017 03:31:53 -0600 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 19 Dec 2017 03:31:53 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 19 Dec 2017 03:31:53 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ9VgHv012627; Tue, 19 Dec 2017 03:31:50 -0600 From: Kishon Vijay Abraham I To: Tony Lindgren , CC: Rob Herring , Mark Rutland , Russell King , , , , , , , Subject: [PATCH 2/7] ARM: dts: DRA74x: Use PCIe compatible specific to dra74 Date: Tue, 19 Dec 2017 15:01:28 +0530 Message-ID: <20171219093133.16565-3-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171219093133.16565-1-kishon@ti.com> References: <20171219093133.16565-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Use dra74 specific compatible string for PCIe while preserving the older compatible. While at that add a new label for the 2nd instance of pcie. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/dra7.dtsi | 2 +- arch/arm/boot/dts/dra74x.dtsi | 12 ++++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 9966d82dbd7c..333f6a634ff9 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -349,7 +349,7 @@ ranges = <0x51800000 0x51800000 0x3000 0x0 0x30000000 0x10000000>; status = "disabled"; - pcie@51800000 { + pcie2_rc: pcie@51800000 { compatible = "ti,dra7-pcie"; reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; reg-names = "rc_dbics", "ti_conf", "config"; diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index 24e6746c5b26..a001eecf3b14 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -124,3 +124,15 @@ status = "disabled"; }; }; + +&pcie1_rc { + compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie"; +}; + +&pcie1_ep { + compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep"; +}; + +&pcie2_rc { + compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie"; +}; From patchwork Tue Dec 19 09:31:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 850736 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="HK7M/Oiq"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3z1CQH4jy7z9s72 for ; Tue, 19 Dec 2017 20:33:43 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936615AbdLSJcw (ORCPT ); Tue, 19 Dec 2017 04:32:52 -0500 Received: from fllnx210.ext.ti.com ([198.47.19.17]:34952 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S938905AbdLSJcb (ORCPT ); Tue, 19 Dec 2017 04:32:31 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id vBJ9VvvF000493; Tue, 19 Dec 2017 03:31:57 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1513675917; bh=kPsOO9BD5gPp9MoyhtztUWXVYP6ohGOdu3zXjuT/cTM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=HK7M/Oiq8LVV814lpWRDd7FYDBtB5aU7Y6fRt1XUxyNTmDkVuInCwKkwNjVeZ1frU u3eEaQeFVU1FtJdy1qeearhB+0eYCHYvfA+tflVYjG2vF81PCaIyx4BoOUYvMUu2Bo GBkkCNO5EbnLsk3THKRkBJnjFywjYMk1l6bIazlE= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ9Vv1Q015700; Tue, 19 Dec 2017 03:31:57 -0600 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 19 Dec 2017 03:31:56 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 19 Dec 2017 03:31:56 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ9VgHw012627; Tue, 19 Dec 2017 03:31:53 -0600 From: Kishon Vijay Abraham I To: Tony Lindgren , CC: Rob Herring , Mark Rutland , Russell King , , , , , , , Subject: [PATCH 3/7] ARM: dts: DRA72x: Use PCIe compatible specific to dra72 Date: Tue, 19 Dec 2017 15:01:29 +0530 Message-ID: <20171219093133.16565-4-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171219093133.16565-1-kishon@ti.com> References: <20171219093133.16565-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Use dra72 specific compatible string for PCIe while preserving the older compatible. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/dra72x.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi index 67107605fb4c..2dafad834d3d 100644 --- a/arch/arm/boot/dts/dra72x.dtsi +++ b/arch/arm/boot/dts/dra72x.dtsi @@ -50,3 +50,15 @@ status = "disabled"; }; }; + +&pcie1_rc { + compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie"; +}; + +&pcie1_ep { + compatible = "ti,dra726-pcie-ep", "ti,dra7-pcie-ep"; +}; + +&pcie2_rc { + compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie"; +}; From patchwork Tue Dec 19 09:31:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 850737 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="S9oMPkzh"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3z1CQZ2mH4z9s82 for ; Tue, 19 Dec 2017 20:33:58 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S938950AbdLSJdz (ORCPT ); Tue, 19 Dec 2017 04:33:55 -0500 Received: from fllnx209.ext.ti.com ([198.47.19.16]:57354 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S938905AbdLSJdx (ORCPT ); Tue, 19 Dec 2017 04:33:53 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id vBJ9W5bk012923; Tue, 19 Dec 2017 03:32:05 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1513675926; bh=Euu2BSfh8tjrQfp8flGHV2W+OdC+6/SRofgdXGJY/y8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=S9oMPkzh2KUtTJhKRRC6zRC/UGUPb/TAQELfZxXC1hyytFxqrNXm+wZNpjTRffh/O 11gAY8g3ssCKeDPYJI7U1ubgCGT57tTUzNdeVUytyiTmVvICxTl9wrcSXHrr9uplfA sz5a1uCs3odVP+v54YFI7nESsWuNCi57wv2abk0k= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ9W07t015740; Tue, 19 Dec 2017 03:32:00 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 19 Dec 2017 03:32:00 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 19 Dec 2017 03:32:00 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ9VgHx012627; Tue, 19 Dec 2017 03:31:57 -0600 From: Kishon Vijay Abraham I To: Tony Lindgren , CC: Rob Herring , Mark Rutland , Russell King , , , , , , , Subject: [PATCH 4/7] ARM: dts: dra76-evm: Enable x2 PCIe lanes Date: Tue, 19 Dec 2017 15:01:30 +0530 Message-ID: <20171219093133.16565-5-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171219093133.16565-1-kishon@ti.com> References: <20171219093133.16565-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org DRA76 EVM has a 4-lane PCIe connector and DRA76 can support x2 lanes. Enable both the PCIe lanes here. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/dra76-evm.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts index b024a65c6e27..244e553f2247 100644 --- a/arch/arm/boot/dts/dra76-evm.dts +++ b/arch/arm/boot/dts/dra76-evm.dts @@ -421,3 +421,19 @@ spi-max-frequency = <96000000>; }; }; + +&pcie2_phy { + status = "okay"; +}; + +&pcie1_rc { + num-lanes = <2>; + phys = <&pcie1_phy>, <&pcie2_phy>; + phy-names = "pcie-phy0", "pcie-phy1"; +}; + +&pcie1_ep { + num-lanes = <2>; + phys = <&pcie1_phy>, <&pcie2_phy>; + phy-names = "pcie-phy0", "pcie-phy1"; +}; From patchwork Tue Dec 19 09:31:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 850735 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="jAmHI67e"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3z1CPF6JtNz9s82 for ; Tue, 19 Dec 2017 20:32:49 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966941AbdLSJcr (ORCPT ); Tue, 19 Dec 2017 04:32:47 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:15665 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S938903AbdLSJca (ORCPT ); Tue, 19 Dec 2017 04:32:30 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id vBJ9W4m4030840; Tue, 19 Dec 2017 03:32:04 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1513675924; bh=DyzIjzbmDXp0Qlfi8lUxH3QwCACf2GqjVbVHZZCR20c=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jAmHI67elYZ6pDPqogL7clQJXu/DgK0osCmuMHtRSv5nhH3cMZk0VJyxL0OX0V7ZJ uKPk5G36iKiQHfq8vyRAZ8fA6yUXUzNoFUwYIPXeJ0pvpte5sQNvyKZcb2LMP0ZxAS k3e1YOFtAQA9w11HmNMnbYQzCp9xfdv8zNoo1UAk= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ9W4Oa015606; Tue, 19 Dec 2017 03:32:04 -0600 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 19 Dec 2017 03:32:04 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 19 Dec 2017 03:32:04 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ9VgI0012627; Tue, 19 Dec 2017 03:32:01 -0600 From: Kishon Vijay Abraham I To: Tony Lindgren , CC: Rob Herring , Mark Rutland , Russell King , , , , , , , Subject: [PATCH 5/7] ARM: dts: dra7: Remove deprecated PCI compatible string Date: Tue, 19 Dec 2017 15:01:31 +0530 Message-ID: <20171219093133.16565-6-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171219093133.16565-1-kishon@ti.com> References: <20171219093133.16565-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Since SoC specific compatible strings are used for PCIe in dra74x.dtsi and dra72x.dtsi, remove the compatible property from dra7.dtsi which uses the deprecated compatible string. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/dra7.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 333f6a634ff9..1efa908c7bce 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -293,7 +293,6 @@ * node and enable pcie1_ep mode. */ pcie1_rc: pcie@51000000 { - compatible = "ti,dra7-pcie"; reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; reg-names = "rc_dbics", "ti_conf", "config"; interrupts = <0 232 0x4>, <0 233 0x4>; @@ -325,7 +324,6 @@ }; pcie1_ep: pcie_ep@51000000 { - compatible = "ti,dra7-pcie-ep"; reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>; reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space"; interrupts = <0 232 0x4>; @@ -350,7 +348,6 @@ 0x0 0x30000000 0x10000000>; status = "disabled"; pcie2_rc: pcie@51800000 { - compatible = "ti,dra7-pcie"; reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; reg-names = "rc_dbics", "ti_conf", "config"; interrupts = <0 355 0x4>, <0 356 0x4>; From patchwork Tue Dec 19 09:31:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 850733 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="zLNEbQaZ"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3z1CNy4mg8z9s72 for ; Tue, 19 Dec 2017 20:32:34 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S938906AbdLSJcc (ORCPT ); Tue, 19 Dec 2017 04:32:32 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:15661 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932998AbdLSJc2 (ORCPT ); Tue, 19 Dec 2017 04:32:28 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id vBJ9W8us030849; Tue, 19 Dec 2017 03:32:08 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1513675928; bh=ffMgXh0vFbhjdKgoqtnyM8PHzyr3806FINH08/axUvQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=zLNEbQaZUK8rc0syaVBj9ChjGXW/7SMcBkQqM+9oULCnBN+c6+CqkovupJWz+HiKY wt8s9xztCyud9igiIJMe285wOqLdbr6hTBecIqYoYj511tP0borNPSLgA7rPqxt8u3 VmbYPZE7pp9cx2hKzuGDwRl5tXGZ1tEY5JJh+YX4= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ9W8AE015704; Tue, 19 Dec 2017 03:32:08 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 19 Dec 2017 03:32:07 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 19 Dec 2017 03:32:07 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ9VgI1012627; Tue, 19 Dec 2017 03:32:04 -0600 From: Kishon Vijay Abraham I To: Tony Lindgren , CC: Rob Herring , Mark Rutland , Russell King , , , , , , , Subject: [PATCH 6/7] ARM: omap2plus_defconfig: Enable CONFIG_PCI_DRA7XX (Host & Device modes) Date: Tue, 19 Dec 2017 15:01:32 +0530 Message-ID: <20171219093133.16565-7-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171219093133.16565-1-kishon@ti.com> References: <20171219093133.16565-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Enable CONFIG_PCI_DRA7XX in order to be able to configure PCIe controller present in dra7 SoCs in both host mode and device mode. Signed-off-by: Kishon Vijay Abraham I --- arch/arm/configs/omap2plus_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 7b97200c1d64..a01871d5aa73 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -48,6 +48,13 @@ CONFIG_SOC_AM43XX=y CONFIG_SOC_DRA7XX=y CONFIG_ARM_THUMBEE=y CONFIG_ARM_ERRATA_411920=y +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_DRA7XX=y +CONFIG_PCI_DRA7XX_EP=y +CONFIG_PCI_ENDPOINT=y +CONFIG_PCI_ENDPOINT_CONFIGFS=y +CONFIG_PCI_EPF_TEST=m CONFIG_SMP=y CONFIG_NR_CPUS=2 CONFIG_CMA=y @@ -137,6 +144,7 @@ CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_SENSORS_TSL2550=m CONFIG_SRAM=y +CONFIG_PCI_ENDPOINT_TEST=m CONFIG_EEPROM_AT24=m CONFIG_BLK_DEV_SD=y CONFIG_SCSI_SCAN_ASYNC=y From patchwork Tue Dec 19 09:31:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 850738 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="O7qYYWuQ"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3z1CRK51H0z9s72 for ; Tue, 19 Dec 2017 20:34:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966944AbdLSJct (ORCPT ); Tue, 19 Dec 2017 04:32:49 -0500 Received: from fllnx210.ext.ti.com ([198.47.19.17]:34953 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S938904AbdLSJcb (ORCPT ); Tue, 19 Dec 2017 04:32:31 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id vBJ9WB0o000530; Tue, 19 Dec 2017 03:32:11 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1513675931; bh=+hsRXLcgiXLBEuX74XvyeIaLTk9ydY076SepF3zjzXI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=O7qYYWuQzDjkuoEKj3HoIyRMXlXjYlgJ3ml/V1obHBrGb34+SySahH//nndrfhZC/ Igo0KMXTbSEF/1w9eX6D8Dcva2GnXsBmR7ryhiqUB1T3uipUj04ZeL1Dk8kohsv/BS 7eJTtDGfTqTe1Wf4fEBAlvFYoMr0yWgG0F/GGaK4= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ9WBln016313; Tue, 19 Dec 2017 03:32:11 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 19 Dec 2017 03:32:11 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 19 Dec 2017 03:32:11 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBJ9VgI2012627; Tue, 19 Dec 2017 03:32:08 -0600 From: Kishon Vijay Abraham I To: Tony Lindgren , CC: Rob Herring , Mark Rutland , Russell King , , , , , , , Subject: [PATCH 7/7] ARM: multi_v7_defconfig: Enable CONFIG_PCI_DRA7XX (Host & Device modes) Date: Tue, 19 Dec 2017 15:01:33 +0530 Message-ID: <20171219093133.16565-8-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171219093133.16565-1-kishon@ti.com> References: <20171219093133.16565-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Enable CONFIG_PCI_DRA7XX in order to be able to configure PCIe controller present in dra7 SoCs in both host mode and device mode. Signed-off-by: Kishon Vijay Abraham I --- arch/arm/configs/multi_v7_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 61509c4b769f..6faecd55ccbd 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -116,6 +116,8 @@ CONFIG_ARCH_ZYNQ=y CONFIG_TRUSTED_FOUNDATIONS=y CONFIG_PCI=y CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCI_DRA7XX=y +CONFIG_PCI_DRA7XX_EP=y CONFIG_PCI_KEYSTONE=y CONFIG_PCI_MSI=y CONFIG_PCI_MVEBU=y @@ -123,6 +125,9 @@ CONFIG_PCI_TEGRA=y CONFIG_PCI_RCAR_GEN2=y CONFIG_PCIE_RCAR=y CONFIG_PCIEPORTBUS=y +CONFIG_PCI_ENDPOINT=y +CONFIG_PCI_ENDPOINT_CONFIGFS=y +CONFIG_PCI_EPF_TEST=m CONFIG_SMP=y CONFIG_NR_CPUS=16 CONFIG_HIGHPTE=y @@ -222,6 +227,7 @@ CONFIG_ATMEL_SSC=m CONFIG_QCOM_COINCELL=m CONFIG_APDS9802ALS=y CONFIG_ISL29003=y +CONFIG_PCI_ENDPOINT_TEST=m CONFIG_EEPROM_AT24=y CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=y