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H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFTY:; SFS:(4636009)(136003)(346002)(376002)(396003)(39860400002)(46966005)(4326008)(8676002)(186003)(36756003)(82310400002)(356005)(54906003)(47076004)(966005)(81166007)(316002)(6666004)(6486002)(83380400001)(82740400003)(36906005)(8936002)(2616005)(956004)(2906002)(66616009)(70206006)(478600001)(5660300002)(70586007)(336012)(86362001)(6916009)(16526019)(26005)(44832011)(6496006)(53546011)(17423001)(156123004); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Jul 2020 07:38:27.1903 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c22cd8d9-2d41-4f0d-1621-08d83524b6b0 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT054.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0801MB1988 X-Spam-Status: No, score=-15.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, MSGID_FROM_MTA_HEADER, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Earnshaw Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Hi all, I'd like to submit the following patch that adds a missing CC reg clobber for the FJCVTZS instruction [1]. The patch adds an executing testcase that fails without the clobber. Bootstrapped on aarch64-linux-gnu, regression ongoing. Okay for trunk when finished testing? Andrea [1] https://developer.arm.com/docs/ddi0596/latest/simd-and-floating-point-instructions-alphabetic-order/fjcvtzs-floating-point-javascript-convert-to-signed-fixed-point-rounding-toward-zero gcc/ChangeLog 2020-07-30 Andrea Corallo * config/aarch64/aarch64.md (aarch64_fjcvtzs): Add missing clobber. gcc/testsuite/ChangeLog 2020-07-30 Andrea Corallo * gcc.target/aarch64/acle/jcvt_2.c: New testcase. * lib/target-supports.exp (check_effective_target_aarch64_fjcvtzs_hw): Add new check for FJCVTZS hw. From 419436f9717a18545e5e89dff7f28e6958891f4c Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Wed, 29 Jul 2020 19:04:40 +0200 Subject: [PATCH] Add missing clobber for fjcvtzs gcc/ChangeLog 2020-07-30 Andrea Corallo * config/aarch64/aarch64.md (aarch64_fjcvtzs): Add missing clobber. gcc/testsuite/ChangeLog 2020-07-30 Andrea Corallo * gcc.target/aarch64/acle/jcvt_2.c: New testcase. * lib/target-supports.exp (check_effective_target_aarch64_fjcvtzs_hw): Add new check for FJCVTZS hw. --- gcc/config/aarch64/aarch64.md | 3 +- .../gcc.target/aarch64/acle/jcvt_2.c | 33 +++++++++++++++++++ gcc/testsuite/lib/target-supports.exp | 21 ++++++++++++ 3 files changed, 56 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/jcvt_2.c diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index d5ca1898c02e..df780b863707 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -7059,7 +7059,8 @@ (define_insn "aarch64_fjcvtzs" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand:DF 1 "register_operand" "w")] - UNSPEC_FJCVTZS))] + UNSPEC_FJCVTZS)) + (clobber (reg:CC CC_REGNUM))] "TARGET_JSCVT" "fjcvtzs\\t%w0, %d1" [(set_attr "type" "f_cvtf2i")] diff --git a/gcc/testsuite/gcc.target/aarch64/acle/jcvt_2.c b/gcc/testsuite/gcc.target/aarch64/acle/jcvt_2.c new file mode 100644 index 000000000000..ea2dfd14cf29 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/jcvt_2.c @@ -0,0 +1,33 @@ +/* Test the __jcvt ACLE intrinsic. */ +/* { dg-do run } */ +/* { dg-options "-O2 -march=armv8.3-a -save-temps" } */ +/* { dg-require-effective-target aarch64_fjcvtzs_hw } */ + +#include + +extern void abort (void); + +#ifdef __ARM_FEATURE_JCVT +volatile int32_t x; + +int __attribute__((noinline)) +foo (double a, int b, int c) +{ + b = b > c; + x = __jcvt (a); + return b; +} + +int +main (void) +{ + int x = foo (1.1, 2, 3); + if (x) + abort (); + + return 0; +} + +#endif + +/* { dg-final { scan-assembler-times "fjcvtzs\tw\[0-9\]+, d\[0-9\]+\n" 1 } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 57eed3012b94..5973f7edb4b3 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -4848,6 +4848,27 @@ proc check_effective_target_aarch64_bti_hw { } { } "-O2" ] } +# Return 1 if the target supports executing the armv8.3-a FJCVTZS +# instruction. +proc check_effective_target_aarch64_fjcvtzs_hw { } { + if { ![istarget aarch64*-*-*] } { + return 0 + } + return [check_runtime aarch64_fjcvtzs_hw_available { + int + main (void) + { + double in = 25.1; + int out; + asm volatile ("fjcvtzs %w0, %d1" + : "=r" (out) + : "w" (in) + : /* No clobbers. */); + return out == 25; + } + } "-march=armv8.3-a" ] +} + # Return 1 if GCC was configured with --enable-standard-branch-protection proc check_effective_target_default_branch_protection { } { return [check_configured_with "enable-standard-branch-protection"]