From patchwork Thu Jul 23 12:18:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 1334842 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-i2c-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=dqdCbynR; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BCBG73JMSz9sRX for ; Thu, 23 Jul 2020 22:19:11 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726521AbgGWMTH (ORCPT ); Thu, 23 Jul 2020 08:19:07 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:7232 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726109AbgGWMTH (ORCPT ); Thu, 23 Jul 2020 08:19:07 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Jul 2020 05:18:04 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 23 Jul 2020 05:19:06 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 23 Jul 2020 05:19:06 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 23 Jul 2020 12:19:06 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 23 Jul 2020 12:19:06 +0000 Received: from kyarlagadda-linux.nvidia.com (Not Verified[10.19.64.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Jul 2020 05:19:05 -0700 From: Krishna Yarlagadda To: , , CC: , , , , , , Krishna Yarlagadda Subject: [PATCH 1/7] i2c: tegra: remove dead code Date: Thu, 23 Jul 2020 17:48:47 +0530 Message-ID: <1595506733-10307-1-git-send-email-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595506684; bh=fa+P5jAGVjPVirFmB1xYmlo1dz271n97QHWg6liSJZc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: MIME-Version:Content-Type:Content-Transfer-Encoding; b=dqdCbynRWBTP0EBgNI6Jsw3LPfIDlnGpA5wTxo6YBYDADj05qQq6N62gGYPQRvode kSOeqaydNeULiJkUJELwwU1WPYuGGJCRnf8YnDMukhubNRerzk+xxiMuauyBHWqd8a +oJGTQOJnvRt6hBMFBEj4TJHpncqJihryRdX372SWX1D4R72sDTqm7nn3Srbh0rcok ecu+okg5mzW5BVQHyTGLzL1LRnz+3DMP4EiKp5KQDbj7RfB7jst0Afcsc9zetFkx63 Dq3A+ZPomsk3pLgRYff5tSxyGaBr3QtJVwD497rROpCjj2/BuG1t06fr2dRVLwNNVs pCQLncIXiqPGw== Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Shardar Shariff Md When I2C_HEADER_CONT_ON_NAK bit in IO header is set then “No ACK from slave” error is not reported (NACK is considered as ACK and transfer is continued). So if I2C_ERR_NO_ACK is set, it would imply I2C_M_IGNORE_NAK is not set and hence this code will never execute. When I2C_HEADER_CONT_ON_NAK bit in IO header is set then “No ACK from slave” error is not reported. Condition (msg->flags & I2C_M_IGNORE_NAK) will never be hit Signed-off-by: Shardar Shariff Md Signed-off-by: Krishna Yarlagadda --- drivers/i2c/busses/i2c-tegra.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 1577296..c6c870c 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -1336,11 +1336,8 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, return -EAGAIN; } - if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { - if (msg->flags & I2C_M_IGNORE_NAK) - return 0; + if (i2c_dev->msg_err == I2C_ERR_NO_ACK) return -EREMOTEIO; - } return -EIO; } From patchwork Thu Jul 23 12:18:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 1334843 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-i2c-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=i5H4s+qv; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BCBG84LxJz9sRK for ; Thu, 23 Jul 2020 22:19:12 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728560AbgGWMTL (ORCPT ); Thu, 23 Jul 2020 08:19:11 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:19162 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726109AbgGWMTK (ORCPT ); Thu, 23 Jul 2020 08:19:10 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Jul 2020 05:17:08 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 23 Jul 2020 05:19:10 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 23 Jul 2020 05:19:10 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 23 Jul 2020 12:19:09 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 23 Jul 2020 12:19:09 +0000 Received: from kyarlagadda-linux.nvidia.com (Not Verified[10.19.64.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Jul 2020 05:19:09 -0700 From: Krishna Yarlagadda To: , , CC: , , , , , , Krishna Yarlagadda Subject: [PATCH 2/7] i2c: tegra: Fix setting of controller ID Date: Thu, 23 Jul 2020 17:48:48 +0530 Message-ID: <1595506733-10307-2-git-send-email-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595506733-10307-1-git-send-email-kyarlagadda@nvidia.com> References: <1595506733-10307-1-git-send-email-kyarlagadda@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595506628; bh=dsjnuZOTtQt5TvQcOndJuqUXWxDoWmm74K7vWSQWQx0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Type; b=i5H4s+qvPEYh8/QWROqjl8QOSLkP6Gqz7k8JpCZ8E6DziSbMGY3pHC4cSlmanpk3E RdHQ7reA2vv02xY7N6k9t/HjnOHB7qrKgB5wtR0hYHO1tmGjUX68oYGl98fWELGtCt w7ROlpaiOotZYcSEr6UzMdSswK9NIp1c3JKlkwnlCa03IrDqmxJpHzOnQ/0krY/MlQ K1Uxfn2rqtCjXwSLsS+fun7XK0HceIEr1eamXaT61L4O1807tTg94Teiauz6PfbBXn 0xYUtgX24wtLl/CMJ84Nv9k1MgaC8Kw4CV8SaazUukCgtPyI6yA1Y1DkvqxIIf1jhI PvscGed9V1XDg== Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Shardar Shariff Md Assign controller id with adapter number as it (cont_id) is passed through DT(through alias). Mask with controller id mask to avoid overflow other fields when single device is present and id is -1. Signed-off-by: Shardar Shariff Md Signed-off-by: Krishna Yarlagadda --- drivers/i2c/busses/i2c-tegra.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index c6c870c..a841d6c 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -83,6 +83,7 @@ #define PACKET_HEADER0_CONT_ID GENMASK(15, 12) #define PACKET_HEADER0_PROTOCOL GENMASK(7, 4) #define PACKET_HEADER0_PROTOCOL_I2C 1 +#define PACKET_HEADER0_CONT_ID_MASK 0xF #define I2C_HEADER_CONT_ON_NAK BIT(21) #define I2C_HEADER_READ BIT(19) @@ -1669,7 +1670,6 @@ static int tegra_i2c_probe(struct platform_device *pdev) i2c_dev->adapter.retries = 1; i2c_dev->adapter.timeout = 6 * HZ; i2c_dev->irq = irq; - i2c_dev->cont_id = pdev->id; i2c_dev->dev = &pdev->dev; i2c_dev->rst = devm_reset_control_get_exclusive(&pdev->dev, "i2c"); @@ -1807,6 +1807,7 @@ static int tegra_i2c_probe(struct platform_device *pdev) if (ret) goto release_dma; + i2c_dev->cont_id = i2c_dev->adapter.nr & PACKET_HEADER0_CONT_ID_MASK; pm_runtime_put(&pdev->dev); return 0; From patchwork Thu Jul 23 12:18:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 1334846 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-i2c-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=C4Y420Xm; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BCBGF0Zgxz9sRX for ; Thu, 23 Jul 2020 22:19:17 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728650AbgGWMTP (ORCPT ); Thu, 23 Jul 2020 08:19:15 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:19167 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726109AbgGWMTN (ORCPT ); Thu, 23 Jul 2020 08:19:13 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 23 Jul 2020 05:17:11 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 23 Jul 2020 05:19:13 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 23 Jul 2020 05:19:13 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 23 Jul 2020 12:19:13 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 23 Jul 2020 12:19:13 +0000 Received: from kyarlagadda-linux.nvidia.com (Not Verified[10.19.64.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Jul 2020 05:19:12 -0700 From: Krishna Yarlagadda To: , , CC: , , , , , , Krishna Yarlagadda Subject: [PATCH 3/7] i2c: tegra: add flag for register write buffering Date: Thu, 23 Jul 2020 17:48:49 +0530 Message-ID: <1595506733-10307-3-git-send-email-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595506733-10307-1-git-send-email-kyarlagadda@nvidia.com> References: <1595506733-10307-1-git-send-email-kyarlagadda@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595506631; bh=Bllwqib3qCXycyC1UJOhNAs0mt5jHnNS0tHTaZbyTLE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Type; b=C4Y420XmHvLxPEt3DoLJF7qmZvhx0w2clomZFwSZmw4YxNx5TwXHvkjI4Z9SvDvDN hJhi9kOq4HVQuu6m1ML+pz9WYpfs5/gNyCeDQ2Vi3zTSFzTBJc7eDStLxy8AdZetEG F4MwtRqY66f26bNqY3nRm3feFzTyU18fFphrlvphRwcvkNpBok/8Oe9hAE4QdS8gKN vb9E6Xdcb4ExJdZey4NPxzcuojr4O3fzGoYTTTjsNVb6eYtSlKwCNZjEy7jh6FztbE SO1KBUxQb5YOAkA/ilrZlaZuLni75+hKvgjFRFBNXAM+e4onMVXfB6OLN5SYEcqLyV +z6+ko4Jk0gUg== Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org In chips earlier to Tegra186, register write gets buffered. So to make sure register writes are completed, there is need to readback the register. Adding flag to disable this readback for Tegra186 and later chips. Signed-off-by: Krishna Yarlagadda --- drivers/i2c/busses/i2c-tegra.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index a841d6c..bdbbca0 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -220,6 +220,7 @@ struct tegra_i2c_hw_feature { bool has_mst_fifo; const struct i2c_adapter_quirks *quirks; bool supports_bus_clear; + bool has_reg_write_buffering; bool has_apb_dma; u8 tlow_std_mode; u8 thigh_std_mode; @@ -325,8 +326,11 @@ static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); /* Read back register to make sure that register writes completed */ - if (reg != I2C_TX_FIFO) - readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); + if (i2c_dev->hw->has_reg_write_buffering) { + if (reg != I2C_TX_FIFO) + readl_relaxed(i2c_dev->base + + tegra_i2c_reg_addr(i2c_dev, reg)); + } } static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) @@ -1450,6 +1454,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { .has_mst_fifo = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = false, + .has_reg_write_buffering = true, .has_apb_dma = true, .tlow_std_mode = 0x4, .thigh_std_mode = 0x2, @@ -1475,6 +1480,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { .has_mst_fifo = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = false, + .has_reg_write_buffering = true, .has_apb_dma = true, .tlow_std_mode = 0x4, .thigh_std_mode = 0x2, @@ -1500,6 +1506,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { .has_mst_fifo = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, + .has_reg_write_buffering = true, .has_apb_dma = true, .tlow_std_mode = 0x4, .thigh_std_mode = 0x2, @@ -1525,6 +1532,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { .has_mst_fifo = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, + .has_reg_write_buffering = true, .has_apb_dma = true, .tlow_std_mode = 0x4, .thigh_std_mode = 0x2, @@ -1550,6 +1558,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { .has_mst_fifo = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, + .has_reg_write_buffering = true, .has_apb_dma = true, .tlow_std_mode = 0x4, .thigh_std_mode = 0x2, @@ -1575,6 +1584,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { .has_mst_fifo = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, + .has_reg_write_buffering = false, .has_apb_dma = false, .tlow_std_mode = 0x4, .thigh_std_mode = 0x3, @@ -1600,6 +1610,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { .has_mst_fifo = true, .quirks = &tegra194_i2c_quirks, .supports_bus_clear = true, + .has_reg_write_buffering = false, .has_apb_dma = false, .tlow_std_mode = 0x8, .thigh_std_mode = 0x7, From patchwork Thu Jul 23 12:18:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 1334847 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-i2c-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=ZWuP9tEX; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BCBGJ486jz9sRX for ; Thu, 23 Jul 2020 22:19:20 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728763AbgGWMTS (ORCPT ); Thu, 23 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Received: from kyarlagadda-linux.nvidia.com (Not Verified[10.19.64.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Jul 2020 05:19:15 -0700 From: Krishna Yarlagadda To: , , CC: , , , , , , Krishna Yarlagadda Subject: [PATCH 4/7] i2c: tegra: add high speed mode support Date: Thu, 23 Jul 2020 17:48:50 +0530 Message-ID: <1595506733-10307-4-git-send-email-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595506733-10307-1-git-send-email-kyarlagadda@nvidia.com> References: <1595506733-10307-1-git-send-email-kyarlagadda@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595506744; bh=MidEY3z1fFgcerAQ5XajHtgp1ERmHHIlbwKkyuQc4F4=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Type; b=ZWuP9tEX0LJdgmnLAUNwaWG2cioBSr8J/OJRIhzdk5uZeUB+2XY5Vov5sePJ9qvdX L1plICtdqyE4dTHj58ZRhpVyzHQAjIh7gRoX+2kS7Fu8S57R0Sniann2E26MmSq26Q yuDP9YklMmSEkzBy+/CiTi29jTfne0oSIt5GWtOtMST1NpkY5DkrBdjUGV/xPmeVVS YAHMKVTivZKognYyYxKSL5WT4qdP7C9PgQiOC5IDq04D4gO43wCxrOLQiKJ3AhaDN8 cUQy8QXNFv7ZeFIPWxy5XaAj9XhfkpU8MhvOFG5s7QnKa4ip24Erd7/a4tSireT1/e QMdDW5oF1Gt8w== Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Shardar Shariff Md Add high speed mode support Signed-off-by: Shardar Shariff Md Signed-off-by: Laxman Dewangan Signed-off-by: Krishna Yarlagadda --- drivers/i2c/busses/i2c-tegra.c | 64 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 56 insertions(+), 8 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index bdbbca0..2f654ed 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -85,12 +85,14 @@ #define PACKET_HEADER0_PROTOCOL_I2C 1 #define PACKET_HEADER0_CONT_ID_MASK 0xF +#define I2C_HEADER_HIGHSPEED_MODE BIT(22) #define I2C_HEADER_CONT_ON_NAK BIT(21) #define I2C_HEADER_READ BIT(19) #define I2C_HEADER_10BIT_ADDR BIT(18) #define I2C_HEADER_IE_ENABLE BIT(17) #define I2C_HEADER_REPEAT_START BIT(16) #define I2C_HEADER_CONTINUE_XFER BIT(15) +#define I2C_HEADER_MASTER_ADDR_SHIFT 12 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 #define I2C_BUS_CLEAR_CNFG 0x084 @@ -136,6 +138,7 @@ /* configuration load timeout in microseconds */ #define I2C_CONFIG_LOAD_TIMEOUT 1000000 +#define I2C_HS_MODE 3500000 /* Packet header size in bytes */ #define I2C_PACKET_HEADER_SIZE 12 @@ -215,12 +218,14 @@ struct tegra_i2c_hw_feature { int clk_divisor_std_mode; int clk_divisor_fast_mode; u16 clk_divisor_fast_plus_mode; + int clk_multiplier_hs_mode; bool has_multi_master_mode; bool has_slcg_override_reg; bool has_mst_fifo; const struct i2c_adapter_quirks *quirks; bool supports_bus_clear; bool has_reg_write_buffering; + bool has_hs_mode_support; bool has_apb_dma; u8 tlow_std_mode; u8 thigh_std_mode; @@ -293,6 +298,7 @@ struct tegra_i2c_dev { bool is_curr_dma_xfer; struct completion dma_complete; bool is_curr_atomic_xfer; + int clk_divisor_hs_mode; }; static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, @@ -778,8 +784,9 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev, bool clk_reinit) if (i2c_dev->is_dvc) tegra_dvc_init(i2c_dev); - val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | - FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT, 2); + val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN; + if (i2c_dev->bus_clk_rate != I2C_HS_MODE) + val |= FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT, 0x2); if (i2c_dev->hw->has_multi_master_mode) val |= I2C_CNFG_MULTI_MASTER_MODE; @@ -791,6 +798,13 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev, bool clk_reinit) tegra_i2c_vi_init(i2c_dev); /* Make sure clock divisor programmed correctly */ + if (i2c_dev->bus_clk_rate == I2C_HS_MODE) { + i2c_dev->clk_divisor_hs_mode = i2c_dev->hw->clk_divisor_hs_mode; + } else { + val = i2c_readl(i2c_dev, I2C_CLK_DIVISOR); + i2c_dev->clk_divisor_hs_mode = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE, val); + } + clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE, i2c_dev->hw->clk_divisor_hs_mode) | FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, @@ -822,8 +836,13 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev, bool clk_reinit) i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); if (!clk_reinit) { - clk_multiplier = (tlow + thigh + 2); - clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1); + if (i2c_dev->bus_clk_rate == I2C_HS_MODE) { + clk_multiplier = i2c_dev->hw->clk_multiplier_hs_mode; + clk_multiplier *= (i2c_dev->clk_divisor_hs_mode + 1); + } else { + clk_multiplier = (tlow + thigh + 2); + clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1); + } err = clk_set_rate(i2c_dev->div_clk, i2c_dev->bus_clk_rate * clk_multiplier); if (err) { @@ -1244,6 +1263,8 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, packet_header |= I2C_HEADER_CONT_ON_NAK; if (msg->flags & I2C_M_RD) packet_header |= I2C_HEADER_READ; + if (i2c_dev->bus_clk_rate == I2C_HS_MODE) + packet_header |= I2C_HEADER_HIGHSPEED_MODE; if (dma && !i2c_dev->msg_read) *buffer++ = packet_header; else @@ -1448,6 +1469,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { .clk_divisor_std_mode = 0, .clk_divisor_fast_mode = 0, .clk_divisor_fast_plus_mode = 0, + .clk_multiplier_hs_mode = 12, .has_config_load_reg = false, .has_multi_master_mode = false, .has_slcg_override_reg = false, @@ -1455,6 +1477,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { .quirks = &tegra_i2c_quirks, .supports_bus_clear = false, .has_reg_write_buffering = true, + .has_hs_mode_support = false, .has_apb_dma = true, .tlow_std_mode = 0x4, .thigh_std_mode = 0x2, @@ -1474,6 +1497,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { .clk_divisor_std_mode = 0, .clk_divisor_fast_mode = 0, .clk_divisor_fast_plus_mode = 0, + .clk_multiplier_hs_mode = 12, .has_config_load_reg = false, .has_multi_master_mode = false, .has_slcg_override_reg = false, @@ -1481,6 +1505,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { .quirks = &tegra_i2c_quirks, .supports_bus_clear = false, .has_reg_write_buffering = true, + .has_hs_mode_support = false, .has_apb_dma = true, .tlow_std_mode = 0x4, .thigh_std_mode = 0x2, @@ -1500,6 +1525,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { .clk_divisor_std_mode = 0x19, .clk_divisor_fast_mode = 0x19, .clk_divisor_fast_plus_mode = 0x10, + .clk_multiplier_hs_mode = 3, .has_config_load_reg = false, .has_multi_master_mode = false, .has_slcg_override_reg = false, @@ -1507,6 +1533,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, .has_reg_write_buffering = true, + .has_hs_mode_support = false, .has_apb_dma = true, .tlow_std_mode = 0x4, .thigh_std_mode = 0x2, @@ -1522,10 +1549,11 @@ static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { .has_continue_xfer_support = true, .has_per_pkt_xfer_complete_irq = true, .has_single_clk_source = true, - .clk_divisor_hs_mode = 1, + .clk_divisor_hs_mode = 2, .clk_divisor_std_mode = 0x19, .clk_divisor_fast_mode = 0x19, .clk_divisor_fast_plus_mode = 0x10, + .clk_multiplier_hs_mode = 13, .has_config_load_reg = true, .has_multi_master_mode = false, .has_slcg_override_reg = true, @@ -1533,6 +1561,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, .has_reg_write_buffering = true, + .has_hs_mode_support = false, .has_apb_dma = true, .tlow_std_mode = 0x4, .thigh_std_mode = 0x2, @@ -1548,10 +1577,11 @@ static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { .has_continue_xfer_support = true, .has_per_pkt_xfer_complete_irq = true, .has_single_clk_source = true, - .clk_divisor_hs_mode = 1, + .clk_divisor_hs_mode = 2, .clk_divisor_std_mode = 0x19, .clk_divisor_fast_mode = 0x19, .clk_divisor_fast_plus_mode = 0x10, + .clk_multiplier_hs_mode = 13, .has_config_load_reg = true, .has_multi_master_mode = false, .has_slcg_override_reg = true, @@ -1559,6 +1589,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, .has_reg_write_buffering = true, + .has_hs_mode_support = false, .has_apb_dma = true, .tlow_std_mode = 0x4, .thigh_std_mode = 0x2, @@ -1574,10 +1605,11 @@ static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { .has_continue_xfer_support = true, .has_per_pkt_xfer_complete_irq = true, .has_single_clk_source = true, - .clk_divisor_hs_mode = 1, + .clk_divisor_hs_mode = 2, .clk_divisor_std_mode = 0x16, .clk_divisor_fast_mode = 0x19, .clk_divisor_fast_plus_mode = 0x10, + .clk_multiplier_hs_mode = 13, .has_config_load_reg = true, .has_multi_master_mode = false, .has_slcg_override_reg = true, @@ -1585,6 +1617,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, .has_reg_write_buffering = false, + .has_hs_mode_support = false, .has_apb_dma = false, .tlow_std_mode = 0x4, .thigh_std_mode = 0x3, @@ -1600,10 +1633,11 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { .has_continue_xfer_support = true, .has_per_pkt_xfer_complete_irq = true, .has_single_clk_source = true, - .clk_divisor_hs_mode = 1, + .clk_divisor_hs_mode = 2, .clk_divisor_std_mode = 0x4f, .clk_divisor_fast_mode = 0x3c, .clk_divisor_fast_plus_mode = 0x16, + .clk_multiplier_hs_mode = 13, .has_config_load_reg = true, .has_multi_master_mode = true, .has_slcg_override_reg = true, @@ -1611,6 +1645,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { .quirks = &tegra194_i2c_quirks, .supports_bus_clear = true, .has_reg_write_buffering = false, + .has_hs_mode_support = true, .has_apb_dma = false, .tlow_std_mode = 0x8, .thigh_std_mode = 0x7, @@ -1694,8 +1729,21 @@ static int tegra_i2c_probe(struct platform_device *pdev) i2c_dev->hw = of_device_get_match_data(&pdev->dev); i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node, "nvidia,tegra20-i2c-dvc"); + + i2c_dev->hw = of_device_get_match_data(&pdev->dev); i2c_dev->is_vi = of_device_is_compatible(dev->of_node, "nvidia,tegra210-i2c-vi"); + if (i2c_dev->bus_clk_rate == I2C_HS_MODE && + !i2c_dev->hw->has_hs_mode_support) { + dev_info(i2c_dev->dev, "HS mode not supported\n"); + i2c_dev->bus_clk_rate = 100000; /* default clock rate */ + } + + if (i2c_dev->is_multimaster_mode && + !i2c_dev->hw->has_multi_master_mode) { + dev_info(i2c_dev->dev, "multi-master mode not supported\n"); + i2c_dev->is_multimaster_mode = false; + } i2c_dev->adapter.quirks = i2c_dev->hw->quirks; i2c_dev->dma_buf_size = i2c_dev->adapter.quirks->max_write_len + I2C_PACKET_HEADER_SIZE; From patchwork Thu Jul 23 12:18:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 1334853 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org 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[PATCH 5/7] i2c: tegra: enable second level clock gating Date: Thu, 23 Jul 2020 17:48:51 +0530 Message-ID: <1595506733-10307-5-git-send-email-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595506733-10307-1-git-send-email-kyarlagadda@nvidia.com> References: <1595506733-10307-1-git-send-email-kyarlagadda@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595506747; bh=YtW5ONuxQcaNg5+GvR7yBueoYCGlYcr9525vggzlM5Q=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Type; b=eseKmqrlY/enO0KSXaanUL2AKHEuZ1u3zDUrTCD7w5U4VmCNMXxDLdKnKHC7BRqz0 SMCn1OldRpl4TsmNXASWOcwS5rxsb4MBEv4BhcqtJaGgxr6JgAOjShVHA4tfxtwQAe fsarR6S2zMoMchKoubouT5QaoKc92ld4Rfb32xTK+5jx44M/eanIdrBF7uHeZTFWcB Pxsf0eaU7P5KMT2wPUQzr5UxMnIbY8rfBi1vIVbfZiNH2mf0wCdXs0LYu+aypESjGu qNMJWVcl7dR9hoRnO67OxcFxk+d+9pp7j+0t+wSdD2Yk+KbC87g6cQj/wFdoeYQLm6 XAd2YBbRnuXXA== Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Enable Second Level Clock Gating feature for supported chips. With SLCG enabled, software need not control clocks anymore and leave clocks enabled always on. Signed-off-by: Shardar Shariff Md Signed-off-by: Laxman Dewangan Signed-off-by: Krishna Yarlagadda --- drivers/i2c/busses/i2c-tegra.c | 32 ++++++++++++++++++++++++++++---- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 2f654ed..8ab968e 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -235,6 +235,7 @@ struct tegra_i2c_hw_feature { u32 setup_hold_time_fast_fast_plus_mode; u32 setup_hold_time_hs_mode; bool has_interface_timing_reg; + bool has_slcg_support; }; /** @@ -299,6 +300,7 @@ struct tegra_i2c_dev { struct completion dma_complete; bool is_curr_atomic_xfer; int clk_divisor_hs_mode; + bool is_clkon_always; }; static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, @@ -1478,6 +1480,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { .supports_bus_clear = false, .has_reg_write_buffering = true, .has_hs_mode_support = false, + .has_slcg_support = false, .has_apb_dma = true, .tlow_std_mode = 0x4, .thigh_std_mode = 0x2, @@ -1506,6 +1509,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { .supports_bus_clear = false, .has_reg_write_buffering = true, .has_hs_mode_support = false, + .has_slcg_support = false, .has_apb_dma = true, .tlow_std_mode = 0x4, .thigh_std_mode = 0x2, @@ -1534,6 +1538,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { .supports_bus_clear = true, .has_reg_write_buffering = true, .has_hs_mode_support = false, + .has_slcg_support = false, .has_apb_dma = true, .tlow_std_mode = 0x4, .thigh_std_mode = 0x2, @@ -1562,6 +1567,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { .supports_bus_clear = true, .has_reg_write_buffering = true, .has_hs_mode_support = false, + .has_slcg_support = false, .has_apb_dma = true, .tlow_std_mode = 0x4, .thigh_std_mode = 0x2, @@ -1590,6 +1596,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { .supports_bus_clear = true, .has_reg_write_buffering = true, .has_hs_mode_support = false, + .has_slcg_support = false, .has_apb_dma = true, .tlow_std_mode = 0x4, .thigh_std_mode = 0x2, @@ -1618,6 +1625,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { .supports_bus_clear = true, .has_reg_write_buffering = false, .has_hs_mode_support = false, + .has_slcg_support = true, .has_apb_dma = false, .tlow_std_mode = 0x4, .thigh_std_mode = 0x3, @@ -1646,6 +1654,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { .supports_bus_clear = true, .has_reg_write_buffering = false, .has_hs_mode_support = true, + .has_slcg_support = true, .has_apb_dma = false, .tlow_std_mode = 0x8, .thigh_std_mode = 0x7, @@ -1822,7 +1831,12 @@ static int tegra_i2c_probe(struct platform_device *pdev) } } - if (i2c_dev->is_multimaster_mode) { + if (i2c_dev->is_multimaster_mode || i2c_dev->hw->has_slcg_support) + i2c_dev->is_clkon_always = true; + else + i2c_dev->is_clkon_always = false; + + if (i2c_dev->is_clkon_always) { ret = clk_enable(i2c_dev->div_clk); if (ret < 0) { dev_err(i2c_dev->dev, "div_clk enable failed %d\n", @@ -1875,7 +1889,7 @@ static int tegra_i2c_probe(struct platform_device *pdev) tegra_i2c_release_dma(i2c_dev); disable_div_clk: - if (i2c_dev->is_multimaster_mode) + if (i2c_dev->is_clkon_always) clk_disable(i2c_dev->div_clk); put_rpm: @@ -1908,7 +1922,7 @@ static int tegra_i2c_remove(struct platform_device *pdev) i2c_del_adapter(&i2c_dev->adapter); - if (i2c_dev->is_multimaster_mode) + if (i2c_dev->is_clkon_always) clk_disable(i2c_dev->div_clk); pm_runtime_disable(&pdev->dev); @@ -1932,7 +1946,8 @@ static int __maybe_unused tegra_i2c_suspend(struct device *dev) struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); int err = 0; - i2c_mark_adapter_suspended(&i2c_dev->adapter); + if (i2c_dev->is_clkon_always) + clk_disable(i2c_dev->div_clk); if (!pm_runtime_status_suspended(dev)) err = tegra_i2c_runtime_suspend(dev); @@ -1968,6 +1983,15 @@ static int __maybe_unused tegra_i2c_resume(struct device *dev) return err; } + if (i2c_dev->is_clkon_always) { + err = clk_enable(i2c_dev->div_clk); + if (err < 0) { + dev_err(i2c_dev->dev, "clock enable failed %d\n", + err); + return err; + } + } + i2c_mark_adapter_resumed(&i2c_dev->adapter); return 0; From patchwork Thu Jul 23 12:18:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 1334848 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-i2c-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=XXcRiwmS; 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Thu, 23 Jul 2020 12:19:23 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 23 Jul 2020 12:19:22 +0000 Received: from kyarlagadda-linux.nvidia.com (Not Verified[10.19.64.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Jul 2020 05:19:22 -0700 From: Krishna Yarlagadda To: , , CC: , , , , , , Krishna Yarlagadda Subject: [PATCH 6/7] i2c: tegra: DMA support for t186 and t194 Date: Thu, 23 Jul 2020 17:48:52 +0530 Message-ID: <1595506733-10307-6-git-send-email-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595506733-10307-1-git-send-email-kyarlagadda@nvidia.com> References: <1595506733-10307-1-git-send-email-kyarlagadda@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595506641; bh=lbncHwO3OLR/eiajOIMGJWlwqCWr+tFZpr51JViAPWc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Type; b=XXcRiwmSauA6ff2cOSQpKunHfb2/28oVTWDfPcuWiebyd1kAp7nsalRWH2ugrBk3U ZmkXutLc0gS9w3YWyC6LmKV7WWaXFDiyufiUQHLzetUtbjxBFgV4JD0DBE/atiOLts CsTbaPPS9G6wYGRzWX/UHrC2ILIkrqIV2cpWGHsp+1O7O64d8IcZTsmMXn32Qhy8I8 TCkBxSwtuWBPrcf43j7QqrzCpU7lrW181xjBXbhT0etvMjYpmneG+FcgdlRpOPLFxA mySbe2q1dADrBpOFFJL0VC8+msVsAzCJfWvbQSjFSZbL+qX9xacP3oeZidYHDkcr6R JYb7cIHqQjtpQ== Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Enable GPC DMA support for Tegra186 and Tegra194 Signed-off-by: Rajesh Gumasta Signed-off-by: Krishna Yarlagadda --- drivers/i2c/busses/i2c-tegra.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 8ab968e..77198fc 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -236,6 +236,7 @@ struct tegra_i2c_hw_feature { u32 setup_hold_time_hs_mode; bool has_interface_timing_reg; bool has_slcg_support; + bool has_gpc_dma; }; /** @@ -432,11 +433,18 @@ static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) dma_addr_t dma_phys; int err; - if (!i2c_dev->hw->has_apb_dma) - return 0; - - if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { - dev_dbg(i2c_dev->dev, "Support for APB DMA not enabled!\n"); + if (i2c_dev->hw->has_gpc_dma) { + if (!IS_ENABLED(CONFIG_TEGRA_GPC_DMA)) { + dev_dbg(i2c_dev->dev, "Support for GPC DMA not enabled!\n"); + return 0; + } + } else if (i2c_dev->hw->has_apb_dma) { + if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { + dev_dbg(i2c_dev->dev, "Support for APB DMA not enabled!\n"); + return 0; + } + } else { + dev_dbg(i2c_dev->dev, "DMA is not enabled!\n"); return 0; } @@ -1490,6 +1498,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { .setup_hold_time_fast_fast_plus_mode = 0x0, .setup_hold_time_hs_mode = 0x0, .has_interface_timing_reg = false, + .has_gpc_dma = false, }; static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { @@ -1519,6 +1528,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { .setup_hold_time_fast_fast_plus_mode = 0x0, .setup_hold_time_hs_mode = 0x0, .has_interface_timing_reg = false, + .has_gpc_dma = false, }; static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { @@ -1548,6 +1558,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { .setup_hold_time_fast_fast_plus_mode = 0x0, .setup_hold_time_hs_mode = 0x0, .has_interface_timing_reg = false, + .has_gpc_dma = false, }; static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { @@ -1577,6 +1588,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { .setup_hold_time_fast_fast_plus_mode = 0x0, .setup_hold_time_hs_mode = 0x0, .has_interface_timing_reg = true, + .has_gpc_dma = false, }; static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { @@ -1606,6 +1618,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { .setup_hold_time_fast_fast_plus_mode = 0, .setup_hold_time_hs_mode = 0, .has_interface_timing_reg = true, + .has_gpc_dma = true, }; static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { @@ -1635,6 +1648,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { .setup_hold_time_fast_fast_plus_mode = 0, .setup_hold_time_hs_mode = 0, .has_interface_timing_reg = true, + .has_gpc_dma = true, }; static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { @@ -1664,6 +1678,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { .setup_hold_time_fast_fast_plus_mode = 0x02020202, .setup_hold_time_hs_mode = 0x090909, .has_interface_timing_reg = true, + .has_gpc_dma = true, }; /* Match table for of_platform binding */ From patchwork Thu Jul 23 12:18:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 1334850 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-i2c-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=c5DauvVD; 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Thu, 23 Jul 2020 12:19:26 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 23 Jul 2020 12:19:26 +0000 Received: from kyarlagadda-linux.nvidia.com (Not Verified[10.19.64.169]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 23 Jul 2020 05:19:25 -0700 From: Krishna Yarlagadda To: , , CC: , , , , , , Krishna Yarlagadda Subject: [PATCH 7/7] i2c: tegra: dump I2C registers on timeout Date: Thu, 23 Jul 2020 17:48:53 +0530 Message-ID: <1595506733-10307-7-git-send-email-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595506733-10307-1-git-send-email-kyarlagadda@nvidia.com> References: <1595506733-10307-1-git-send-email-kyarlagadda@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595506644; bh=R11Ga9WFE2Eiv4ttDZrrlRWyR6LeF2U8LlGpsShfusY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Type; b=c5DauvVDYBkxNG6Rd4TruvpOuOmBI8mIup3ch/VzXJrwnYN42hMmTlkhxAAAVI14r H4rj/QBSFxt1N8zSYsr5Z6MiMam+697tDp4rC5I2fIO+y7ZEU8m4ZTDqw3nhRuKFU3 RBRNeAb/DUbSvpMrLRTRwRVRKgmnhgocj9h4kM3zmQN92mOvtKyOpdk0rme32WqM0i um0MCis4U5obZd9e5NP2xBle1rZ7qFheseow3ljjDvAntcATOEjtbZyT+gqm8VtDcb bLLM0azOwzw1PeYq9LE6RrpaRSkMWu1Qzc41sjPfl9tqOu9B3hucLMUSrVnzn3DfA9 uvUQ1qyWjP+oA== Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Rajesh Gumasta Dump I2C regsiters for debug when transfer timeout occurs. Signed-off-by: Rajesh Gumasta Signed-off-by: Krishna Yarlagadda --- drivers/i2c/busses/i2c-tegra.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 77198fc..cdc8664 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -126,6 +126,8 @@ #define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8) #define I2C_HS_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) +#define I2C_MST_PACKET_TRANSFER_CNT_STATUS 0x0b0 + #define I2C_MST_FIFO_CONTROL 0x0b4 #define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0) #define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1) @@ -1178,6 +1180,33 @@ static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap) return -EAGAIN; } +static void tegra_i2c_reg_dump(struct tegra_i2c_dev *i2c_dev) +{ + dev_dbg(i2c_dev->dev, "--- register dump for debugging ----\n"); + dev_dbg(i2c_dev->dev, "I2C_CNFG - 0x%x\n", + i2c_readl(i2c_dev, I2C_CNFG)); + dev_dbg(i2c_dev->dev, "I2C_PACKET_TRANSFER_STATUS - 0x%x\n", + i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS)); + dev_dbg(i2c_dev->dev, "I2C_FIFO_CONTROL - 0x%x\n", + i2c_readl(i2c_dev, I2C_FIFO_CONTROL)); + dev_dbg(i2c_dev->dev, "I2C_FIFO_STATUS - 0x%x\n", + i2c_readl(i2c_dev, I2C_FIFO_STATUS)); + + if (i2c_dev->hw->has_mst_fifo) { + dev_dbg(i2c_dev->dev, "I2C_MST_FIFO_CONTROL - 0x%x\n", + i2c_readl(i2c_dev, I2C_MST_FIFO_CONTROL)); + dev_dbg(i2c_dev->dev, "I2C_MST_FIFO_STATUS - 0x%x\n", + i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS)); + dev_dbg(i2c_dev->dev, "I2C_MST_PACKET_TRANSFER_CNT - 0x%x\n", + i2c_readl(i2c_dev, + I2C_MST_PACKET_TRANSFER_CNT_STATUS)); + } + dev_dbg(i2c_dev->dev, "I2C_INT_MASK - 0x%x\n", + i2c_readl(i2c_dev, I2C_INT_MASK)); + dev_dbg(i2c_dev->dev, "I2C_INT_STATUS - 0x%x\n", + i2c_readl(i2c_dev, I2C_INT_STATUS)); +} + static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, struct i2c_msg *msg, enum msg_end_type end_state) @@ -1331,6 +1360,7 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, if (!time_left && !completion_done(&i2c_dev->dma_complete)) { dev_err(i2c_dev->dev, "DMA transfer timeout\n"); + tegra_i2c_reg_dump(i2c_dev); tegra_i2c_init(i2c_dev, true); return -ETIMEDOUT; } @@ -1352,6 +1382,7 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, if (time_left == 0) { dev_err(i2c_dev->dev, "i2c transfer timed out\n"); + tegra_i2c_reg_dump(i2c_dev); tegra_i2c_init(i2c_dev, true); return -ETIMEDOUT; }