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Wed, 22 Jul 2020 10:24:41 -0700 (PDT) Received: from localhost.localdomain ([188.25.219.134]) by smtp.gmail.com with ESMTPSA id bt26sm311517edb.17.2020.07.22.10.24.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 10:24:40 -0700 (PDT) From: Vladimir Oltean To: robh+dt@kernel.org, shawnguo@kernel.org, mpe@ellerman.id.au, devicetree@vger.kernel.org Subject: [PATCH devicetree 1/4] powerpc: dts: t1040: add bindings for Seville Ethernet switch Date: Wed, 22 Jul 2020 20:24:19 +0300 Message-Id: <20200722172422.2590489-2-olteanv@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200722172422.2590489-1-olteanv@gmail.com> References: <20200722172422.2590489-1-olteanv@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Thu, 23 Jul 2020 08:08:49 +1000 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: madalin.bucur@oss.nxp.com, linux-kernel@vger.kernel.org, radu-andrei.bulie@nxp.com, fido_max@inbox.ru, paulus@samba.org, netdev@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Add the description of the embedded L2 switch inside the SoC dtsi file for NXP T1040. Signed-off-by: Vladimir Oltean --- arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 75 +++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi index 315d0557eefc..4af856dcc6a3 100644 --- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi @@ -628,6 +628,81 @@ mdio@fd000 { status = "disabled"; }; }; + + seville_switch: ethernet-switch@800000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mscc,vsc9953-switch"; + little-endian; + reg = <0x800000 0x290000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + seville_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + seville_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + seville_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + seville_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + seville_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + + seville_port5: port@5 { + reg = <5>; + status = "disabled"; + }; + + seville_port6: port@6 { + reg = <6>; + status = "disabled"; + }; + + seville_port7: port@7 { + reg = <7>; + status = "disabled"; + }; + + seville_port8: port@8 { + reg = <8>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + seville_port9: port@9 { + reg = <9>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + }; + }; }; &qe { From patchwork Wed Jul 22 17:24:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 1334243 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BBqbw4J99z9sPf for ; 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Wed, 22 Jul 2020 10:24:41 -0700 (PDT) From: Vladimir Oltean To: robh+dt@kernel.org, shawnguo@kernel.org, mpe@ellerman.id.au, devicetree@vger.kernel.org Subject: [PATCH devicetree 2/4] powerpc: dts: t1040: label the 2 MDIO controllers Date: Wed, 22 Jul 2020 20:24:20 +0300 Message-Id: <20200722172422.2590489-3-olteanv@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200722172422.2590489-1-olteanv@gmail.com> References: <20200722172422.2590489-1-olteanv@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Thu, 23 Jul 2020 08:08:50 +1000 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: madalin.bucur@oss.nxp.com, linux-kernel@vger.kernel.org, radu-andrei.bulie@nxp.com, fido_max@inbox.ru, paulus@samba.org, netdev@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" In preparation of referencing the MDIO nodes from board DTS files (so that we can add PHY nodes easier), add labels to mdio0 and mdio1. Signed-off-by: Vladimir Oltean --- arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi index 4af856dcc6a3..e1b138b3c714 100644 --- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi @@ -620,11 +620,11 @@ enet3: ethernet@e6000 { enet4: ethernet@e8000 { }; - mdio@fc000 { + mdio0: mdio@fc000 { interrupts = <100 1 0 0>; }; - mdio@fd000 { + mdio1: mdio@fd000 { status = "disabled"; }; }; From patchwork Wed Jul 22 17:24:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 1334241 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BBqZ22sTtz9sPf for ; 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Wed, 22 Jul 2020 10:24:43 -0700 (PDT) From: Vladimir Oltean To: robh+dt@kernel.org, shawnguo@kernel.org, mpe@ellerman.id.au, devicetree@vger.kernel.org Subject: [PATCH devicetree 3/4] powerpc: dts: t1040rdb: put SGMII PHY under &mdio0 label Date: Wed, 22 Jul 2020 20:24:21 +0300 Message-Id: <20200722172422.2590489-4-olteanv@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200722172422.2590489-1-olteanv@gmail.com> References: <20200722172422.2590489-1-olteanv@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Thu, 23 Jul 2020 08:08:49 +1000 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: madalin.bucur@oss.nxp.com, linux-kernel@vger.kernel.org, radu-andrei.bulie@nxp.com, fido_max@inbox.ru, paulus@samba.org, netdev@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" We're going to add 8 more PHYs in a future patch. It is easier to follow the hardware description if we don't need to fish for the path of the MDIO controllers inside the SoC and just use the labels. Signed-off-by: Vladimir Oltean --- arch/powerpc/boot/dts/fsl/t1040rdb.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/boot/dts/fsl/t1040rdb.dts b/arch/powerpc/boot/dts/fsl/t1040rdb.dts index 65ff34c49025..40d7126dbe90 100644 --- a/arch/powerpc/boot/dts/fsl/t1040rdb.dts +++ b/arch/powerpc/boot/dts/fsl/t1040rdb.dts @@ -59,12 +59,6 @@ ethernet@e4000 { phy-handle = <&phy_sgmii_2>; phy-connection-type = "sgmii"; }; - - mdio@fc000 { - phy_sgmii_2: ethernet-phy@3 { - reg = <0x03>; - }; - }; }; }; @@ -76,3 +70,9 @@ cpld@3,0 { }; #include "t1040si-post.dtsi" + +&mdio0 { + phy_sgmii_2: ethernet-phy@3 { + reg = <0x3>; + }; +}; From patchwork Wed Jul 22 17:24:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 1334244 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BBqds728zz9sPf for ; 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Wed, 22 Jul 2020 10:24:44 -0700 (PDT) From: Vladimir Oltean To: robh+dt@kernel.org, shawnguo@kernel.org, mpe@ellerman.id.au, devicetree@vger.kernel.org Subject: [PATCH devicetree 4/4] powerpc: dts: t1040rdb: add ports for Seville Ethernet switch Date: Wed, 22 Jul 2020 20:24:22 +0300 Message-Id: <20200722172422.2590489-5-olteanv@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200722172422.2590489-1-olteanv@gmail.com> References: <20200722172422.2590489-1-olteanv@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Thu, 23 Jul 2020 08:08:50 +1000 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: madalin.bucur@oss.nxp.com, linux-kernel@vger.kernel.org, radu-andrei.bulie@nxp.com, fido_max@inbox.ru, paulus@samba.org, netdev@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Define the network interface names for the switch ports and hook them up to the 2 QSGMII PHYs that are onboard. A conscious decision was taken to go along with the numbers that are written on the front panel of the board and not with the hardware numbers of the switch chip ports. The 2 are shifted by 4. Signed-off-by: Vladimir Oltean --- arch/powerpc/boot/dts/fsl/t1040rdb.dts | 111 +++++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/arch/powerpc/boot/dts/fsl/t1040rdb.dts b/arch/powerpc/boot/dts/fsl/t1040rdb.dts index 40d7126dbe90..28ee06a1706d 100644 --- a/arch/powerpc/boot/dts/fsl/t1040rdb.dts +++ b/arch/powerpc/boot/dts/fsl/t1040rdb.dts @@ -75,4 +75,115 @@ &mdio0 { phy_sgmii_2: ethernet-phy@3 { reg = <0x3>; }; + + /* VSC8514 QSGMII PHY */ + phy_qsgmii_0: ethernet-phy@4 { + reg = <0x4>; + }; + + phy_qsgmii_1: ethernet-phy@5 { + reg = <0x5>; + }; + + phy_qsgmii_2: ethernet-phy@6 { + reg = <0x6>; + }; + + phy_qsgmii_3: ethernet-phy@7 { + reg = <0x7>; + }; + + /* VSC8514 QSGMII PHY */ + phy_qsgmii_4: ethernet-phy@8 { + reg = <0x8>; + }; + + phy_qsgmii_5: ethernet-phy@9 { + reg = <0x9>; + }; + + phy_qsgmii_6: ethernet-phy@a { + reg = <0xa>; + }; + + phy_qsgmii_7: ethernet-phy@b { + reg = <0xb>; + }; +}; + +&seville_port0 { + managed = "in-band-status"; + phy-handle = <&phy_qsgmii_0>; + phy-mode = "qsgmii"; + /* ETH4 written on chassis */ + label = "swp4"; + status = "okay"; +}; + +&seville_port1 { + managed = "in-band-status"; + phy-handle = <&phy_qsgmii_1>; + phy-mode = "qsgmii"; + /* ETH5 written on chassis */ + label = "swp5"; + status = "okay"; +}; + +&seville_port2 { + managed = "in-band-status"; + phy-handle = <&phy_qsgmii_2>; + phy-mode = "qsgmii"; + /* ETH6 written on chassis */ + label = "swp6"; + status = "okay"; +}; + +&seville_port3 { + managed = "in-band-status"; + phy-handle = <&phy_qsgmii_3>; + phy-mode = "qsgmii"; + /* ETH7 written on chassis */ + label = "swp7"; + status = "okay"; +}; + +&seville_port4 { + managed = "in-band-status"; + phy-handle = <&phy_qsgmii_4>; + phy-mode = "qsgmii"; + /* ETH8 written on chassis */ + label = "swp8"; + status = "okay"; +}; + +&seville_port5 { + managed = "in-band-status"; + phy-handle = <&phy_qsgmii_5>; + phy-mode = "qsgmii"; + /* ETH9 written on chassis */ + label = "swp9"; + status = "okay"; +}; + +&seville_port6 { + managed = "in-band-status"; + phy-handle = <&phy_qsgmii_6>; + phy-mode = "qsgmii"; + /* ETH10 written on chassis */ + label = "swp10"; + status = "okay"; +}; + +&seville_port7 { + managed = "in-band-status"; + phy-handle = <&phy_qsgmii_7>; + phy-mode = "qsgmii"; + /* ETH11 written on chassis */ + label = "swp11"; + status = "okay"; +}; + +&seville_port8 { + ethernet = <&enet0>; + status = "okay"; };