From patchwork Mon Jul 20 12:56:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1332359 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=R5y95QPp; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B9MFD2B9Rz9sRf for ; Mon, 20 Jul 2020 22:57:04 +1000 (AEST) Received: from localhost ([::1]:38496 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jxVLp-0002Iy-Lq for incoming@patchwork.ozlabs.org; Mon, 20 Jul 2020 08:57:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55724) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jxVLK-0002HT-4j for qemu-devel@nongnu.org; Mon, 20 Jul 2020 08:56:30 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:39483) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jxVLH-0007Ht-0R for qemu-devel@nongnu.org; Mon, 20 Jul 2020 08:56:29 -0400 Received: by mail-wm1-x32f.google.com with SMTP id w3so25053640wmi.4 for ; Mon, 20 Jul 2020 05:56:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=emW1nc2AzE5wKcpJ7qyQJo3pUf29WqEBvvdvJOV3mSo=; b=R5y95QPpKEVXD4vSCW2b1QDx4CNXB8UEBAGEp+hTEpOXE/Z/w/X3CQPTgu3GP+fWot YJ5fHlAsD3E8vuvYBE8fRftBkrQj7VyjFpiLPg0O9j+fvIgYREcr4Sy/VG+o0UfhOsOs UDO+0sldi6o/RtG7uz9/RLaZNaC5nJb1w7lwjb/jfogM04115Zf7e73gzyElx5SsbG/t Yfp8Mk8fwxhI92cMwpKviHEX6P9edm8OiIoQTSW1f2OaRNnJhPa5Pb9i3/WZfNpwlRzX YNbQqolEUaCOTGXvR1s7dCVzKnhaQmBOPHjj4UjuD69MeZprYP43PxpHtBeDvOgqM5zb 0jHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=emW1nc2AzE5wKcpJ7qyQJo3pUf29WqEBvvdvJOV3mSo=; b=shLgCl0Hq63z3zLLzO3LZMRHZa+LiFbt8TiLDGM2BM/y1HhTQO4xl7XZ2Q5Qk+AcIi OUVmlhAFPSQMNjWk6I5t4GjvWrXdLhzGa/TWxfrPSFU4jsXoB0KqsJu2Ih7vRsRkYu7N roJhNvP7HK/DhdIUv0Mcndjy6t3qWYX5uQI3R3aXpami2krzXZGbKf/I3JaaU/E++I+1 yFVtsLKTZVS9c3G24fZjtErJ+3GbwF4G6piuPxYYtqlH1tVPr3N/n2V0D0mSXskWSLJm XbYPZcKBmyY+3ludfqHHdKG9c5aXzii/DW19dFC44LCbYI72U3v5U1lnt0akQyQyJCa6 +uHQ== X-Gm-Message-State: AOAM533bKLREXJ8NPvyBbj6BZeLW1eUatLeQYchvwzsjqfOaqNlot15J Vrzj7b8B10PWiUs+RLWwPbLHFndS95VAwQ== X-Google-Smtp-Source: ABdhPJzZs6qzdoZJINY3TltC4bz+juMdTkBRWc6TvDRwffOzQLCM7b7d4m5vYtNj7LzrNF+5X8utyQ== X-Received: by 2002:a1c:a7c4:: with SMTP id q187mr21146857wme.0.1595249785149; Mon, 20 Jul 2020 05:56:25 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p29sm34025403wmi.43.2020.07.20.05.56.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2020 05:56:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/12] hw/arm/virt: Enable MTE via a machine property Date: Mon, 20 Jul 2020 13:56:10 +0100 Message-Id: <20200720125621.13460-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200720125621.13460-1-peter.maydell@linaro.org> References: <20200720125621.13460-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Control this cpu feature via a machine property, much as we do with secure=on, since both require specialized support in the machine setup to be functional. Default MTE to off, since this feature implies extra overhead. Signed-off-by: Richard Henderson Message-id: 20200713213341.590275-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/virt.h | 1 + hw/arm/virt.c | 39 ++++++++++++++++++++++++++++++++++----- target/arm/cpu.c | 19 +++++++++++-------- target/arm/cpu64.c | 5 +++-- 4 files changed, 49 insertions(+), 15 deletions(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 54bcf17afd3..dff67e1bef0 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -140,6 +140,7 @@ typedef struct { bool its; bool virt; bool ras; + bool mte; OnOffAuto acpi; VirtGICType gic_version; VirtIOMMUType iommu; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 9005dae356b..5866c4ce202 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1837,12 +1837,19 @@ static void machvirt_init(MachineState *machine) OBJECT(secure_sysmem), &error_abort); } - /* - * The cpu adds the property if and only if MemTag is supported. - * If it is, we must allocate the ram to back that up. - */ - if (object_property_find(cpuobj, "tag-memory", NULL)) { + if (vms->mte) { + /* Create the memory region only once, but link to all cpus. */ if (!tag_sysmem) { + /* + * The property exists only if MemTag is supported. + * If it is, we must allocate the ram to back that up. + */ + if (!object_property_find(cpuobj, "tag-memory", NULL)) { + error_report("MTE requested, but not supported " + "by the guest CPU"); + exit(1); + } + tag_sysmem = g_new(MemoryRegion, 1); memory_region_init(tag_sysmem, OBJECT(machine), "tag-memory", UINT64_MAX / 32); @@ -2061,6 +2068,20 @@ static void virt_set_ras(Object *obj, bool value, Error **errp) vms->ras = value; } +static bool virt_get_mte(Object *obj, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + return vms->mte; +} + +static void virt_set_mte(Object *obj, bool value, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + vms->mte = value; +} + static char *virt_get_gic_version(Object *obj, Error **errp) { VirtMachineState *vms = VIRT_MACHINE(obj); @@ -2481,6 +2502,14 @@ static void virt_instance_init(Object *obj) "Set on/off to enable/disable reporting host memory errors " "to a KVM guest using ACPI and guest external abort exceptions"); + /* MTE is disabled by default. */ + vms->mte = false; + object_property_add_bool(obj, "mte", virt_get_mte, virt_set_mte); + object_property_set_description(obj, "mte", + "Set on/off to enable/disable emulating a " + "guest CPU which implements the ARM " + "Memory Tagging Extension"); + vms->irqmap = a15irqmap; virt_flash_create(vms); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5050e1843a8..111579554fb 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1698,6 +1698,17 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) cpu->id_pfr1 &= ~0xf000; } +#ifndef CONFIG_USER_ONLY + if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { + /* + * Disable the MTE feature bits if we do not have tag-memory + * provided by the machine. + */ + cpu->isar.id_aa64pfr1 = + FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); + } +#endif + /* MPU can be configured out of a PMSA CPU either by setting has-mpu * to false or by setting pmsav7-dregion to 0. */ @@ -1787,14 +1798,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", cpu->secure_tag_memory); } - } else if (cpu_isar_feature(aa64_mte, cpu)) { - /* - * Since there is no tag memory, we can't meaningfully support MTE - * to its fullest. To avoid problems later, when we would come to - * use the tag memory, downgrade support to insns only. - */ - cpu->isar.id_aa64pfr1 = - FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); } cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 15494002d20..dd696183dfb 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -646,8 +646,9 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64pfr1; t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* - * Begin with full support for MTE; will be downgraded to MTE=1 - * during realize if the board provides no tag memory. + * Begin with full support for MTE. This will be downgraded to MTE=0 + * during realize if the board provides no tag memory, much like + * we do for EL2 with the virtualization=on property. */ t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2); cpu->isar.id_aa64pfr1 = t; From patchwork Mon Jul 20 12:56:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1332360 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=ZzigXOT3; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B9MFF3KgJz9sRk for ; Mon, 20 Jul 2020 22:57:05 +1000 (AEST) Received: from localhost ([::1]:38608 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jxVLr-0002Lx-6d for incoming@patchwork.ozlabs.org; Mon, 20 Jul 2020 08:57:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55750) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jxVLL-0002IP-7i for qemu-devel@nongnu.org; Mon, 20 Jul 2020 08:56:31 -0400 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:36143) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jxVLI-0007IA-Cd for qemu-devel@nongnu.org; Mon, 20 Jul 2020 08:56:30 -0400 Received: by mail-wr1-x443.google.com with SMTP id 88so7465830wrh.3 for ; Mon, 20 Jul 2020 05:56:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=2R6yuGy1KqPamHh7Iri9C1nOxQozqj4+DJfYR4M9wzg=; b=ZzigXOT3oCZHxaK5+lz6WdbPqbHF+1m3tPNF8Fcrfsg8c+lDgm3/lxv4sTsnSrq89M vEa36I9pyP8piN1jhHLArJRXCmukGBdVA9wGfysqM72s59r3mHloiCMiUUAg6PxRUNhP 6GNdrBANIUbD0EWxaCnSDTPfB2E5GHUdp7vqLTgGxp6w46/GIvUkp93jt01DKjM/qsr0 kEmp1HGpem9SLaoiyzmQAwteC6Bm+GZbuwHuE/isEfj9u4Gwjk1X5/NSbBMo556SSEVU MTOkiGCAm6EEup3tkreEdXAClPBum/yHvXA+4olMjKxS59lshYGhtmvu7UMryu0qSX19 Ecgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2R6yuGy1KqPamHh7Iri9C1nOxQozqj4+DJfYR4M9wzg=; b=nhb7tiRYVpdvAjgsORxdbuWZJEDfBz2uxyfrfgsDiHeVwgxdNIPRFGMTPDcR2w8tHp EbrMUaRqO+VcOYBHU8jhd269vXPujOFDopPLPeB4a8u7A620ySejolH0HqH91GMEzH6T n225I1wnd/n3ztO1QBJTfoeIDn6JET5r+tbZaOOyAmn0kmRNcG0UhOUgaPWdx5BD0HWQ m9DWFRh0ls0U+Hhkl7d137Ty19L2GMi0VEyRkZOh22w/vV4rDiGKa/W3Os7k5b+ZIKHA SlujEyxgnzaoW2qlo1e1P8ISZLmRE3bOv8o4Ry7MA4j+PSL/V0CNqo8TacKOi6U0LvcA 37sw== X-Gm-Message-State: AOAM531S22JcLlIQsIk1EaPbqC10oawt1pH8FXFLgxbLkuZQyHMizzIW /T04UvTthhEWzSQy/54luW64V9kJ0mjI2Q== X-Google-Smtp-Source: ABdhPJxKjQc86geRQVNg0sIVySMNMw2w2nrX2R3nBy0+ecPDuWl2Nnc8mWGqriRtYur4fo99zbgxBw== X-Received: by 2002:a5d:6348:: with SMTP id b8mr4820927wrw.362.1595249786432; Mon, 20 Jul 2020 05:56:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p29sm34025403wmi.43.2020.07.20.05.56.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2020 05:56:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/12] hw/arm/virt: Error for MTE enabled with KVM Date: Mon, 20 Jul 2020 13:56:11 +0100 Message-Id: <20200720125621.13460-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200720125621.13460-1-peter.maydell@linaro.org> References: <20200720125621.13460-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson While we expect KVM to support MTE at some future point, it certainly won't be ready in time for qemu 5.1. Signed-off-by: Richard Henderson Message-id: 20200713213341.590275-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/virt.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 5866c4ce202..a7f3d442db3 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1773,6 +1773,12 @@ static void machvirt_init(MachineState *machine) exit(1); } + if (vms->mte && kvm_enabled()) { + error_report("mach-virt: KVM does not support providing " + "MTE to the guest CPU"); + exit(1); + } + create_fdt(vms); possible_cpus = mc->possible_cpu_arch_ids(machine); From patchwork Mon Jul 20 12:56:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1332362 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=R7sQeBkB; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B9MH31zYCz9sRW for ; Mon, 20 Jul 2020 22:58:39 +1000 (AEST) Received: from localhost ([::1]:46672 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jxVNM-0005ck-Tj for incoming@patchwork.ozlabs.org; Mon, 20 Jul 2020 08:58:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55746) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jxVLK-0002I9-W3 for qemu-devel@nongnu.org; Mon, 20 Jul 2020 08:56:31 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:46724) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jxVLJ-0007IM-BY for qemu-devel@nongnu.org; Mon, 20 Jul 2020 08:56:30 -0400 Received: by mail-wr1-x444.google.com with SMTP id r12so17645931wrj.13 for ; Mon, 20 Jul 2020 05:56:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=UtZqvEbX3cxeC7NPk3wMM6IqqBBRLSdFGXelit5rqZ4=; b=R7sQeBkB4v7fJwN+D9EW7ZFwHRDfIeEkd+AMoWDwU4hiahRueL1VdHb0V3dMpeBLNR cNeD2tQt3iONyzdRyHlnS/ncALh2o0SuFsRTwzH2CqvLr6OKf/U4iML2t1rM/z2amhm2 HwGFEPWU5rrqc4hGVDnMLdXWKlXZ05LaK/dV4rPXWEZ/xjagGAe+Oy/7ZZenMIZo8gWw h2a85FhHcWLodHLQVsHYfTt2sWFHmSDEr+/eFEFjaGjPS7bZDnvZ4YGfeiNVaTohaZGw H4CM27tm2KGC1l0I69jBdpPRRal5P1L/NyN46//P7405rD0LLdo+zI14hzVq6+aQRbzg t0Cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UtZqvEbX3cxeC7NPk3wMM6IqqBBRLSdFGXelit5rqZ4=; b=LAt5jpUYvAdq++ViOGD5BJAE9kszAjZ8Ne0uAlsgncma8gKuyp8xP31GBiZZo6D1T+ FPELxg4too31mThW79Td9qDKv6cZKlVS250WytbCYMKVeKtWgmGnObPsbHtNiXR6GroH eGBhbmPHOsbhVoNQI2BVlCHahFRN1nGbP9+5a2cxpfbyTEvu2a9vFxhIxHVkhzF6NKaP TiG80vUmsEhSIMatX4BFOGsYMnKrJK41dLfYqfB/BDZP9XyOBkaLQpOdBWQr8lnLVrzi OIwFof/5Ivo7bBvI4O1qky0npa59JEpKgd5OQ+jBPi0yz7Qsr6Hqws/PxwQn2DLlkrIo gJ3w== X-Gm-Message-State: AOAM5323YylZTOBTBh/aiKOlBoR5vJ/pVJadk25n4uTx3I+p76sha7bD F7bBOwF3udU2XLuQw/xrVKCKT0cFa3gREw== X-Google-Smtp-Source: ABdhPJyLpz9kOwfw+cL4JkKDOX6uJzETp4PRwUBWam5DwAB8L+B6Pj9YpWsaSVXxuJXg5o4dcYGzvQ== X-Received: by 2002:adf:e690:: with SMTP id r16mr22802wrm.249.1595249787528; Mon, 20 Jul 2020 05:56:27 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p29sm34025403wmi.43.2020.07.20.05.56.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2020 05:56:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/12] hw/arm/virt: Disable memory hotplug when MTE is enabled Date: Mon, 20 Jul 2020 13:56:12 +0100 Message-Id: <20200720125621.13460-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200720125621.13460-1-peter.maydell@linaro.org> References: <20200720125621.13460-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson When MTE is enabled, tag memory must exist for all RAM. It might be possible to simultaneously hot plug tag memory alongside the corresponding normal memory, but for now just disable hotplug. Signed-off-by: Richard Henderson Message-id: 20200713213341.590275-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/virt.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index a7f3d442db3..ecfee362a18 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2194,6 +2194,11 @@ static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, return; } + if (vms->mte) { + error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); + return; + } + if (is_nvdimm && !ms->nvdimms_state->is_enabled) { error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); return; From patchwork Mon Jul 20 12:56:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1332361 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=hWSP1wPq; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B9MFG1qNhz9sSJ for ; Mon, 20 Jul 2020 22:57:06 +1000 (AEST) Received: from localhost ([::1]:38658 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jxVLr-0002NT-UY for incoming@patchwork.ozlabs.org; Mon, 20 Jul 2020 08:57:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55754) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jxVLL-0002JG-Sh for qemu-devel@nongnu.org; Mon, 20 Jul 2020 08:56:31 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:51897) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jxVLK-0007IV-Aq for qemu-devel@nongnu.org; Mon, 20 Jul 2020 08:56:31 -0400 Received: by mail-wm1-x336.google.com with SMTP id 22so22179888wmg.1 for ; Mon, 20 Jul 2020 05:56:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8DHK7n8boT1yEvYZmR1ZTOA6F3ocx/EmfVnNFwz0uCw=; b=hWSP1wPqdV3014Z/4f5laDJKphYuW23U3s4067+XuJSIwTRpyxT7rUVOJ5SezDdb3H 4w6go3U6NR9xnsu/g/tw0pY0uKA34ByzYnRWv0c13e8knDLApX/eJypZHJB4fz6P/GOM stmVIzEp5j/tvkXokP73YuABhMe2hB+yCOi/eBqCdsfc4Eqi1hbFQvhFmv0wA4r+aP76 jpoDUoqBEke+YbQTeyAWuZm50R6RDfaMSAWpfMyV8cMjlKSbSyQTtE4ZLNmfXKCpQJGY 2BfFXM0avZ84PuU2DGVYAX/ZjujB3qsuc2m6HP6Qfj+C5uEl/5cJfhrKOayFydJiHuIn w9ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8DHK7n8boT1yEvYZmR1ZTOA6F3ocx/EmfVnNFwz0uCw=; b=K6fI968Fq5CfPSq9NMmKNXsFrCc8H2H6gBxezJcpGtl6ydL2u3K5/FaCW9ERynTLqf 0FAnmdxXWo9ackdySd869T/eFZvSg978+2SP3+7BiZQwFKtclB2JW3liIpZmRsv5KQON 8k/ERnHMu2FjFGW9LAf6mZWti7gLbBetffmvhkiTxVIwdDv/TvuMWKDxCzklpwJxk2Fc Kie7P1ohTNpucz6STi6Vo3Gistc6tRls9UctpLHZbS/KufkPzA552+2epSlChiGOo8fd r6adP0iVs3kwDB+PDLUF20S+uPpTT57A7KMB3OdwwNgqqkmay74WHPCPL6EabHU0CYQf qNew== X-Gm-Message-State: AOAM531ffeJfIDASApYMD2TvhyucN87iZRS6IytqWCKTv7ApFp8xW9si uzv6ddxoWs4gEh8muX4QDzKPdCVlEjFy6g== X-Google-Smtp-Source: ABdhPJzaOhWfY+IvSFWXftVWy1QAGmvLopASHEfxtS2KczVjZiIZO+eXJIrLIOWaQZji8/YzCPE0fQ== X-Received: by 2002:a1c:2392:: with SMTP id j140mr21081532wmj.6.1595249788625; Mon, 20 Jul 2020 05:56:28 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p29sm34025403wmi.43.2020.07.20.05.56.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2020 05:56:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/12] util: Implement qemu_get_thread_id() for OpenBSD Date: Mon, 20 Jul 2020 13:56:13 +0100 Message-Id: <20200720125621.13460-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200720125621.13460-1-peter.maydell@linaro.org> References: <20200720125621.13460-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: David CARLIER Implement qemu_get_thread_id() for OpenBSD hosts, using getthrid(). Signed-off-by: David Carlier Reviewed-by: Brad Smith Message-id: CA+XhMqxD6gQDBaj8tX0CMEj3si7qYKsM8u1km47e_-U7MC37Pg@mail.gmail.com Reviewed-by: Peter Maydell [PMM: tidied up commit message] Signed-off-by: Peter Maydell --- util/oslib-posix.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/util/oslib-posix.c b/util/oslib-posix.c index 36bf8593f8c..d9236746248 100644 --- a/util/oslib-posix.c +++ b/util/oslib-posix.c @@ -100,6 +100,8 @@ int qemu_get_thread_id(void) return (int)tid; #elif defined(__NetBSD__) return _lwp_self(); +#elif defined(__OpenBSD__) + return getthrid(); #else return getpid(); #endif From patchwork Mon Jul 20 12:56:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1332363 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=AGKqMuhw; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B9MH658QSz9sRf for ; Mon, 20 Jul 2020 22:58:42 +1000 (AEST) Received: from localhost ([::1]:47100 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jxVNQ-0005ma-DE for incoming@patchwork.ozlabs.org; Mon, 20 Jul 2020 08:58:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55780) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jxVLN-0002Mf-R9 for qemu-devel@nongnu.org; Mon, 20 Jul 2020 08:56:33 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:51888) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jxVLL-0007Il-QC for qemu-devel@nongnu.org; Mon, 20 Jul 2020 08:56:33 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 22so22179954wmg.1 for ; Mon, 20 Jul 2020 05:56:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hv/hRwDof3drBWJIx+Z5EldftQ4h6Grha3K0MkRlGTk=; b=AGKqMuhw3m4d33q0mUK6W2+UJSssuf59IF9pKdyRQM53j5AFtUNFitVrLz1m54h9th pjTiqml6mJWKvFkGLfj0ReJcLiPhR38NJ56AVkNOQzMpheB0iQR6zHuvvD5lYjfu5U8u k7UytPz0CDTsXEsvdcZnkaa5VnIZa719RsUwuh6aRRJZWKMZhwQah9jiftvpqE+xGOSK FAqU33mwXEHXgKjX40hWtKuC0ZqIFM/Y/JGBkcrNSKagBhSO9zOPHUDzKWwrtqh5QPUF ZMOdtfbQsXPAVJjDxToKwNqq7WhN8rNHGcVkDJAbGFmKvLRTrY7H6MwCHEra19s9bFDG 7dxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hv/hRwDof3drBWJIx+Z5EldftQ4h6Grha3K0MkRlGTk=; b=d5viOS07EBMdn3PlRJsGlATD6S4mS4LpxRvWbeWKeDKYh9d5GyuUkR6PaNiM4WW4CI 9wo//Ef4d5ftxRr2MIm+/tmMNPEzKmcX8hX0O/2rxHB0JvRzHuqDM6qBP6kp/Zi7dJgc uLrSPlfBFwLt8G0QzmD0lChpQIliMvHKYzPvpmzAp5M83A0hQsLqqo2jIOJI6lki5PNs 7K9I/MsBkiK6FMTCr4X0Bcz1kY9suCdzNU0Zc2ND99V0Ax4/HCkkYL9EFsqWYM/8mYta Zn0/qxSS9giE8UoKaEohh5j1yMbfJJAfP3N7MSFStGsYtmhtnCuabZwDfo4Y8Dj4p+xQ v0Jw== X-Gm-Message-State: AOAM532aB8Q3SSp2+pqFzhIED0XHVC6RGGHK0LHrjeJyDJ30DDFKX+Js vSGKlm0yq2xA4BxTQoHd6wvPNTl8GiBNRA== X-Google-Smtp-Source: ABdhPJyKPFLjYztcEuk3wCsrdcxbP15F40aeOwOh81wAPXZWc1VXGoLXFklbsoyMaAf2baPJ5bLefg== X-Received: by 2002:a1c:d8:: with SMTP id 207mr20722005wma.81.1595249789868; Mon, 20 Jul 2020 05:56:29 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p29sm34025403wmi.43.2020.07.20.05.56.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2020 05:56:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/12] qdev: Move doc comments from qdev.c to qdev-core.h Date: Mon, 20 Jul 2020 13:56:14 +0100 Message-Id: <20200720125621.13460-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200720125621.13460-1-peter.maydell@linaro.org> References: <20200720125621.13460-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The doc-comments which document the qdev API are split between the header file and the C source files, because as a project we haven't been consistent about where we put them. Move all the doc-comments in qdev.c to the header files, so that users of the APIs don't have to look at the implementation files for this information. In the process, unify them into our doc-comment format and expand on them in some cases to clarify expected use cases. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200711142425.16283-2-peter.maydell@linaro.org --- include/hw/qdev-core.h | 57 ++++++++++++++++++++++++++++++++++++ include/hw/qdev-properties.h | 13 ++++++++ hw/core/qdev.c | 33 --------------------- 3 files changed, 70 insertions(+), 33 deletions(-) diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index fe78073c708..2d441d1fb2e 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -320,9 +320,66 @@ compat_props_add(GPtrArray *arr, /*** Board API. This should go away once we have a machine config file. ***/ +/** + * qdev_new: Create a device on the heap + * @name: device type to create (we assert() that this type exists) + * + * This only allocates the memory and initializes the device state + * structure, ready for the caller to set properties if they wish. + * The device still needs to be realized. + * The returned object has a reference count of 1. + */ DeviceState *qdev_new(const char *name); +/** + * qdev_try_new: Try to create a device on the heap + * @name: device type to create + * + * This is like qdev_new(), except it returns %NULL when type @name + * does not exist, rather than asserting. + */ DeviceState *qdev_try_new(const char *name); +/** + * qdev_realize: Realize @dev. + * @dev: device to realize + * @bus: bus to plug it into (may be NULL) + * @errp: pointer to error object + * + * "Realize" the device, i.e. perform the second phase of device + * initialization. + * @dev must not be plugged into a bus already. + * If @bus, plug @dev into @bus. This takes a reference to @dev. + * If @dev has no QOM parent, make one up, taking another reference. + * On success, return true. + * On failure, store an error through @errp and return false. + * + * If you created @dev using qdev_new(), you probably want to use + * qdev_realize_and_unref() instead. + */ bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp); +/** + * qdev_realize_and_unref: Realize @dev and drop a reference + * @dev: device to realize + * @bus: bus to plug it into (may be NULL) + * @errp: pointer to error object + * + * Realize @dev and drop a reference. + * This is like qdev_realize(), except the caller must hold a + * (private) reference, which is dropped on return regardless of + * success or failure. Intended use:: + * + * dev = qdev_new(); + * [...] + * qdev_realize_and_unref(dev, bus, errp); + * + * Now @dev can go away without further ado. + * + * If you are embedding the device into some other QOM device and + * initialized it via some variant on object_initialize_child() then + * do not use this function, because that family of functions arrange + * for the only reference to the child device to be held by the parent + * via the child<> property, and so the reference-count-drop done here + * would be incorrect. For that use case you want qdev_realize(). + */ bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp); void qdev_unrealize(DeviceState *dev); void qdev_set_legacy_instance_id(DeviceState *dev, int alias_id, diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h index 587e5b7d317..8f3a98cba69 100644 --- a/include/hw/qdev-properties.h +++ b/include/hw/qdev-properties.h @@ -282,6 +282,19 @@ void error_set_from_qdev_prop_error(Error **errp, int ret, DeviceState *dev, */ void qdev_property_add_static(DeviceState *dev, Property *prop); +/** + * qdev_alias_all_properties: Create aliases on source for all target properties + * @target: Device which has properties to be aliased + * @source: Object to add alias properties to + * + * Add alias properties to the @source object for all qdev properties on + * the @target DeviceState. + * + * This is useful when @target is an internal implementation object + * owned by @source, and you want to expose all the properties of that + * implementation object as properties on the @source object so that users + * of @source can set them. + */ void qdev_alias_all_properties(DeviceState *target, Object *source); /** diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 01796823b41..96772a15bd5 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -128,13 +128,6 @@ void qdev_set_parent_bus(DeviceState *dev, BusState *bus) } } -/* - * Create a device on the heap. - * A type @name must exist. - * This only initializes the device state structure and allows - * properties to be set. The device still needs to be realized. See - * qdev-core.h. - */ DeviceState *qdev_new(const char *name) { if (!object_class_by_name(name)) { @@ -143,11 +136,6 @@ DeviceState *qdev_new(const char *name) return DEVICE(object_new(name)); } -/* - * Try to create a device on the heap. - * This is like qdev_new(), except it returns %NULL when type @name - * does not exist. - */ DeviceState *qdev_try_new(const char *name) { if (!module_object_class_by_name(name)) { @@ -378,14 +366,6 @@ void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev, qdev_unrealize(dev); } -/* - * Realize @dev. - * @dev must not be plugged into a bus. - * If @bus, plug @dev into @bus. This takes a reference to @dev. - * If @dev has no QOM parent, make one up, taking another reference. - * On success, return true. - * On failure, store an error through @errp and return false. - */ bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp) { assert(!dev->realized && !dev->parent_bus); @@ -399,16 +379,6 @@ bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp) return object_property_set_bool(OBJECT(dev), "realized", true, errp); } -/* - * Realize @dev and drop a reference. - * This is like qdev_realize(), except the caller must hold a - * (private) reference, which is dropped on return regardless of - * success or failure. Intended use: - * dev = qdev_new(); - * [...] - * qdev_realize_and_unref(dev, bus, errp); - * Now @dev can go away without further ado. - */ bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp) { bool ret; @@ -814,9 +784,6 @@ static void qdev_class_add_property(DeviceClass *klass, Property *prop) prop->info->description); } -/* @qdev_alias_all_properties - Add alias properties to the source object for - * all qdev properties on the target DeviceState. - */ void qdev_alias_all_properties(DeviceState *target, Object *source) { ObjectClass *class; From patchwork Mon Jul 20 12:56:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1332368 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=qBsI2Ra4; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B9MKT5Yl0z9sSd for ; Mon, 20 Jul 2020 23:00:45 +1000 (AEST) Received: from localhost ([::1]:55816 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jxVPP-0000pK-AL for incoming@patchwork.ozlabs.org; Mon, 20 Jul 2020 09:00:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55798) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jxVLO-0002P6-MU for qemu-devel@nongnu.org; Mon, 20 Jul 2020 08:56:34 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:53617) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jxVLM-0007JD-Tp for qemu-devel@nongnu.org; Mon, 20 Jul 2020 08:56:34 -0400 Received: by mail-wm1-x333.google.com with SMTP id j18so22172187wmi.3 for ; Mon, 20 Jul 2020 05:56:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=10LO/QCoMpR7jIRc6OlNm9WJ8aeWJRb66wCBW65n2ZM=; b=qBsI2Ra42VlwXp7Kl2gFxtX2bIeSOIuL0xgUxvSkhbKPu9BjvUUAp1JYL2yIGO6ys5 sjQlpiPSJZp03F/LoViTNm5gToBlaK8P8zWqaZ9RiW7kVBSIJon7AIdthIC81DAL8L8u 0x4gNzEwuSkYEx1bVgE0vxLdwFWDGpCmIYdl/zUqIaeu9GazyvLPh3I9WZh8Q3ZTndJ5 aiU4Kdr8kG3xpVkotYfW8tJdz2OTexWA3VP9Cb06Fq2mBWjppH7QW3VNcnRm6aUV6VJ4 jTkQlSrO+z2f95VQQmp3D3V4oA0jcXjPdYvSltatfJwI4lKU4dtMMVvrDSBe/pBQl2rm blUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=10LO/QCoMpR7jIRc6OlNm9WJ8aeWJRb66wCBW65n2ZM=; b=fv7Axyg6ZU322gBzqqTlkxxsKtzs7EIksvD/bmjPsLJyu+ckO530S1fHc/rZxAcwyl x3MRum5CmS2FoJAhe0pO1Jy3hpr/1WeIcboHH23DhCjnvvCfFvE4nxOQeRVzU9Rahr9b AtTeQcs3gmdl1p4hEIawc8VyCGH/GMFkjn0TUaAH5wl20ysDyj2LUN009+Qd6luUAhhS aUoyjILci5oB2t2U0k83fRyCY6GAmLjTPQCDIZwk0Z5w2vxO6nEhQZ+okEdtn87b13W9 ZKw/Pb6QAYMd3LcFqQW0hawh9NFEcNwOuAma/dXIqF+UFjo5SwxNcB2StdoS6wDwksiJ 2DTQ== X-Gm-Message-State: AOAM531S2O3pqhe2OQxsx4lt0cs4D2k3BQkFf2NU58QNq0Kt0h5ax6D5 y4uZrTrSH+GlKCCjiPrnFB4mP/xe49mywg== X-Google-Smtp-Source: ABdhPJx4sxD/jRp3i20+IEuQAsXn7R4814Nuv1qyi9DFsMlaaZJ1IjEkMzhir6pFooD7b9V/qUd4DQ== X-Received: by 2002:a05:600c:249:: with SMTP id 9mr20186415wmj.80.1595249791240; Mon, 20 Jul 2020 05:56:31 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p29sm34025403wmi.43.2020.07.20.05.56.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2020 05:56:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/12] qdev: Document qdev_unrealize() Date: Mon, 20 Jul 2020 13:56:15 +0100 Message-Id: <20200720125621.13460-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200720125621.13460-1-peter.maydell@linaro.org> References: <20200720125621.13460-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add a doc comment for qdev_unrealize(), to go with the new documentation for the realize part of the qdev lifecycle. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200711142425.16283-3-peter.maydell@linaro.org --- include/hw/qdev-core.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 2d441d1fb2e..1d2bf5f37da 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -381,6 +381,25 @@ bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp); * would be incorrect. For that use case you want qdev_realize(). */ bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp); +/** + * qdev_unrealize: Unrealize a device + * @dev: device to unrealize + * + * This function will "unrealize" a device, which is the first phase + * of correctly destroying a device that has been realized. It will: + * + * - unrealize any child buses by calling qbus_unrealize() + * (this will recursively unrealize any devices on those buses) + * - call the the unrealize method of @dev + * + * The device can then be freed by causing its reference count to go + * to zero. + * + * Warning: most devices in QEMU do not expect to be unrealized. Only + * devices which are hot-unpluggable should be unrealized (as part of + * the unplugging process); all other devices are expected to last for + * the life of the simulation and should not be unrealized and freed. + */ void qdev_unrealize(DeviceState *dev); void qdev_set_legacy_instance_id(DeviceState *dev, int alias_id, int required_for_version); From patchwork Mon Jul 20 12:56:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1332364 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=oXC2moot; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B9MH64ZrMz9sRW for ; Mon, 20 Jul 2020 22:58:42 +1000 (AEST) Received: from localhost ([::1]:47078 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jxVNQ-0005mH-Al for incoming@patchwork.ozlabs.org; Mon, 20 Jul 2020 08:58:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55826) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jxVLQ-0002UE-QG for qemu-devel@nongnu.org; Mon, 20 Jul 2020 08:56:36 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:45052) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jxVLO-0007JP-GM for qemu-devel@nongnu.org; Mon, 20 Jul 2020 08:56:36 -0400 Received: by mail-wr1-x444.google.com with SMTP id b6so17720509wrs.11 for ; Mon, 20 Jul 2020 05:56:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8Xd7zpZsEJU+pgATz/q/VYH7gIksBbBcCoaaOptcJd8=; b=oXC2mootWDU1OQHId5gg2jDRKsySzPMcq0gHHiGHOCCKv20Be5SImcwOTdTD7i0lxM nB8a+U2pOa+RifTyvA1HXGKfELRARM3A8ijDaGy3zLmSKMMyzDjYZGNHhyihIxbJafeF 6H/suCBcKEJmD+Ebm2p3clF9+V5NQkf9MLxMtBuZ3L194eLZg7fSPzqUjzy6271Kgab6 edC++aoAN2OBaqNH7EgyGcO5Th9yHnRUJ8MUbp3/zNi+ItmYhTlrqyySYE0AvqatZmR1 lsABLTQl1KtcckTACCDHfKGVyBq/yJbAwvqt9SNmjJllaWOPEv119/FoOapa3Aucl75k AOXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8Xd7zpZsEJU+pgATz/q/VYH7gIksBbBcCoaaOptcJd8=; b=qoh4jrRj8ISiXsy5OEv298nI9MlLSdokegFK4sPe1vqVucAv8kU2ClTzqQJFKHjlUt kCZkV7a0QKsdvm647aprxwmKc/x+CNANotqkDLFP56dq1LhwIibzOplB84tj9BMVamLz Z/qKhdK6kQK+sjVSXxkJWF2W9axEfj08GQVK0XQdCwDywZ1L0ML35dRUgrHNbeQ/fDLp z2x25IwQYjU8O0SIeayvQQ6WfGTkCc4icFCpif2Eu305TTuTM8bLYuosJkT/Kmk/4NdA KJfZvrxKf3AxWxYAa441u+q5XodTAlDDK3qfzzat+fjmvzgu/OnMlu5LPtQzTqoA3klB 4Vbg== X-Gm-Message-State: AOAM531x0TPpEU8KWpPApNboDwyXUZZ5xu7f8qNHvFuwMGAZh+k9zLU1 Q3FRM7rZLEwJtW6zClrsKF+VdS7SBoDhSQ== X-Google-Smtp-Source: ABdhPJxN4NCn4xzhpVHUdHgj9StvI9x+mNqFpizcv1uqlKzCMiSkHzGXO2w4PPXnxgF55PA6o3YUYg== X-Received: by 2002:adf:fc06:: with SMTP id i6mr3910964wrr.79.1595249792445; Mon, 20 Jul 2020 05:56:32 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p29sm34025403wmi.43.2020.07.20.05.56.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2020 05:56:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/12] qdev: Document GPIO related functions Date: Mon, 20 Jul 2020 13:56:16 +0100 Message-Id: <20200720125621.13460-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200720125621.13460-1-peter.maydell@linaro.org> References: <20200720125621.13460-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add documentation comments for the various qdev functions related to creating and connecting GPIO lines. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200711142425.16283-4-peter.maydell@linaro.org --- include/hw/qdev-core.h | 191 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 189 insertions(+), 2 deletions(-) diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 1d2bf5f37da..ea3f73a282d 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -424,13 +424,132 @@ void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev, void qdev_machine_creation_done(void); bool qdev_machine_modified(void); +/** + * qdev_get_gpio_in: Get one of a device's anonymous input GPIO lines + * @dev: Device whose GPIO we want + * @n: Number of the anonymous GPIO line (which must be in range) + * + * Returns the qemu_irq corresponding to an anonymous input GPIO line + * (which the device has set up with qdev_init_gpio_in()). The index + * @n of the GPIO line must be valid (i.e. be at least 0 and less than + * the total number of anonymous input GPIOs the device has); this + * function will assert() if passed an invalid index. + * + * This function is intended to be used by board code or SoC "container" + * device models to wire up the GPIO lines; usually the return value + * will be passed to qdev_connect_gpio_out() or a similar function to + * connect another device's output GPIO line to this input. + * + * For named input GPIO lines, use qdev_get_gpio_in_named(). + */ qemu_irq qdev_get_gpio_in(DeviceState *dev, int n); +/** + * qdev_get_gpio_in_named: Get one of a device's named input GPIO lines + * @dev: Device whose GPIO we want + * @name: Name of the input GPIO array + * @n: Number of the GPIO line in that array (which must be in range) + * + * Returns the qemu_irq corresponding to a named input GPIO line + * (which the device has set up with qdev_init_gpio_in_named()). + * The @name string must correspond to an input GPIO array which exists on + * the device, and the index @n of the GPIO line must be valid (i.e. + * be at least 0 and less than the total number of input GPIOs in that + * array); this function will assert() if passed an invalid name or index. + * + * For anonymous input GPIO lines, use qdev_get_gpio_in(). + */ qemu_irq qdev_get_gpio_in_named(DeviceState *dev, const char *name, int n); +/** + * qdev_connect_gpio_out: Connect one of a device's anonymous output GPIO lines + * @dev: Device whose GPIO to connect + * @n: Number of the anonymous output GPIO line (which must be in range) + * @pin: qemu_irq to connect the output line to + * + * This function connects an anonymous output GPIO line on a device + * up to an arbitrary qemu_irq, so that when the device asserts that + * output GPIO line, the qemu_irq's callback is invoked. + * The index @n of the GPIO line must be valid (i.e. be at least 0 and + * less than the total number of anonymous output GPIOs the device has + * created with qdev_init_gpio_out()); otherwise this function will assert(). + * + * Outbound GPIO lines can be connected to any qemu_irq, but the common + * case is connecting them to another device's inbound GPIO line, using + * the qemu_irq returned by qdev_get_gpio_in() or qdev_get_gpio_in_named(). + * + * It is not valid to try to connect one outbound GPIO to multiple + * qemu_irqs at once, or to connect multiple outbound GPIOs to the + * same qemu_irq. (Warning: there is no assertion or other guard to + * catch this error: the model will just not do the right thing.) + * Instead, for fan-out you can use the TYPE_IRQ_SPLIT device: connect + * a device's outbound GPIO to the splitter's input, and connect each + * of the splitter's outputs to a different device. For fan-in you + * can use the TYPE_OR_IRQ device, which is a model of a logical OR + * gate with multiple inputs and one output. + * + * For named output GPIO lines, use qdev_connect_gpio_out_named(). + */ void qdev_connect_gpio_out(DeviceState *dev, int n, qemu_irq pin); +/** + * qdev_connect_gpio_out: Connect one of a device's anonymous output GPIO lines + * @dev: Device whose GPIO to connect + * @name: Name of the output GPIO array + * @n: Number of the anonymous output GPIO line (which must be in range) + * @pin: qemu_irq to connect the output line to + * + * This function connects an anonymous output GPIO line on a device + * up to an arbitrary qemu_irq, so that when the device asserts that + * output GPIO line, the qemu_irq's callback is invoked. + * The @name string must correspond to an output GPIO array which exists on + * the device, and the index @n of the GPIO line must be valid (i.e. + * be at least 0 and less than the total number of input GPIOs in that + * array); this function will assert() if passed an invalid name or index. + * + * Outbound GPIO lines can be connected to any qemu_irq, but the common + * case is connecting them to another device's inbound GPIO line, using + * the qemu_irq returned by qdev_get_gpio_in() or qdev_get_gpio_in_named(). + * + * It is not valid to try to connect one outbound GPIO to multiple + * qemu_irqs at once, or to connect multiple outbound GPIOs to the + * same qemu_irq; see qdev_connect_gpio_out() for details. + * + * For named output GPIO lines, use qdev_connect_gpio_out_named(). + */ void qdev_connect_gpio_out_named(DeviceState *dev, const char *name, int n, qemu_irq pin); +/** + * qdev_get_gpio_out_connector: Get the qemu_irq connected to an output GPIO + * @dev: Device whose output GPIO we are interested in + * @name: Name of the output GPIO array + * @n: Number of the output GPIO line within that array + * + * Returns whatever qemu_irq is currently connected to the specified + * output GPIO line of @dev. This will be NULL if the output GPIO line + * has never been wired up to the anything. Note that the qemu_irq + * returned does not belong to @dev -- it will be the input GPIO or + * IRQ of whichever device the board code has connected up to @dev's + * output GPIO. + * + * You probably don't need to use this function -- it is used only + * by the platform-bus subsystem. + */ qemu_irq qdev_get_gpio_out_connector(DeviceState *dev, const char *name, int n); +/** + * qdev_intercept_gpio_out: Intercept an existing GPIO connection + * @dev: Device to intercept the outbound GPIO line from + * @icpt: New qemu_irq to connect instead + * @name: Name of the output GPIO array + * @n: Number of the GPIO line in the array + * + * This function is provided only for use by the qtest testing framework + * and is not suitable for use in non-testing parts of QEMU. + * + * This function breaks an existing connection of an outbound GPIO + * line from @dev, and replaces it with the new qemu_irq @icpt, as if + * ``qdev_connect_gpio_out_named(dev, icpt, name, n)`` had been called. + * The previously connected qemu_irq is returned, so it can be restored + * by a second call to qdev_intercept_gpio_out() if desired. + */ qemu_irq qdev_intercept_gpio_out(DeviceState *dev, qemu_irq icpt, const char *name, int n); @@ -438,10 +557,59 @@ BusState *qdev_get_child_bus(DeviceState *dev, const char *name); /*** Device API. ***/ -/* Register device properties. */ -/* GPIO inputs also double as IRQ sinks. */ +/** + * qdev_init_gpio_in: create an array of anonymous input GPIO lines + * @dev: Device to create input GPIOs for + * @handler: Function to call when GPIO line value is set + * @n: Number of GPIO lines to create + * + * Devices should use functions in the qdev_init_gpio_in* family in + * their instance_init or realize methods to create any input GPIO + * lines they need. There is no functional difference between + * anonymous and named GPIO lines. Stylistically, named GPIOs are + * preferable (easier to understand at callsites) unless a device + * has exactly one uniform kind of GPIO input whose purpose is obvious. + * Note that input GPIO lines can serve as 'sinks' for IRQ lines. + * + * See qdev_get_gpio_in() for how code that uses such a device can get + * hold of an input GPIO line to manipulate it. + */ void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n); +/** + * qdev_init_gpio_out: create an array of anonymous output GPIO lines + * @dev: Device to create output GPIOs for + * @pins: Pointer to qemu_irq or qemu_irq array for the GPIO lines + * @n: Number of GPIO lines to create + * + * Devices should use functions in the qdev_init_gpio_out* family + * in their instance_init or realize methods to create any output + * GPIO lines they need. There is no functional difference between + * anonymous and named GPIO lines. Stylistically, named GPIOs are + * preferable (easier to understand at callsites) unless a device + * has exactly one uniform kind of GPIO output whose purpose is obvious. + * + * The @pins argument should be a pointer to either a "qemu_irq" + * (if @n == 1) or a "qemu_irq []" array (if @n > 1) in the device's + * state structure. The device implementation can then raise and + * lower the GPIO line by calling qemu_set_irq(). (If anything is + * connected to the other end of the GPIO this will cause the handler + * function for that input GPIO to be called.) + * + * See qdev_connect_gpio_out() for how code that uses such a device + * can connect to one of its output GPIO lines. + */ void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n); +/** + * qdev_init_gpio_out: create an array of named output GPIO lines + * @dev: Device to create output GPIOs for + * @pins: Pointer to qemu_irq or qemu_irq array for the GPIO lines + * @name: Name to give this array of GPIO lines + * @n: Number of GPIO lines to create + * + * Like qdev_init_gpio_out(), but creates an array of GPIO output lines + * with a name. Code using the device can then connect these GPIO lines + * using qdev_connect_gpio_out_named(). + */ void qdev_init_gpio_out_named(DeviceState *dev, qemu_irq *pins, const char *name, int n); /** @@ -473,6 +641,25 @@ static inline void qdev_init_gpio_in_named(DeviceState *dev, qdev_init_gpio_in_named_with_opaque(dev, handler, dev, name, n); } +/** + * qdev_pass_gpios: create GPIO lines on container which pass through to device + * @dev: Device which has GPIO lines + * @container: Container device which needs to expose them + * @name: Name of GPIO array to pass through (NULL for the anonymous GPIO array) + * + * In QEMU, complicated devices like SoCs are often modelled with a + * "container" QOM device which itself contains other QOM devices and + * which wires them up appropriately. This function allows the container + * to create GPIO arrays on itself which simply pass through to a GPIO + * array of one of its internal devices. + * + * If @dev has both input and output GPIOs named @name then both will + * be passed through. It is not possible to pass a subset of the array + * with this function. + * + * To users of the container device, the GPIO array created on @container + * behaves exactly like any other. + */ void qdev_pass_gpios(DeviceState *dev, DeviceState *container, const char *name); From patchwork Mon Jul 20 12:56:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1332367 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=o3pQ4A21; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B9MKR1bv4z9sRW for ; Mon, 20 Jul 2020 23:00:43 +1000 (AEST) Received: from localhost ([::1]:55600 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jxVPM-0000jv-R6 for incoming@patchwork.ozlabs.org; Mon, 20 Jul 2020 09:00:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55830) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jxVLR-0002Vh-BU for qemu-devel@nongnu.org; Mon, 20 Jul 2020 08:56:37 -0400 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:37398) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jxVLP-0007Ja-IQ for qemu-devel@nongnu.org; Mon, 20 Jul 2020 08:56:36 -0400 Received: by mail-wr1-x443.google.com with SMTP id y3so394680wrl.4 for ; Mon, 20 Jul 2020 05:56:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9ouB9vz4LaWxmz+dvR+lSvNVqxELEdCuBWptGBdnlTg=; b=o3pQ4A214mdcI8Ba5WWaseQ+K10E/TyRHTdYQ5ysZNiPbBesWzlJIE4YTPJGvpivO4 ZB9vWsExxtuBRocDFhZ35CkvfDH78gtFSoiP4EdUdqlPveoy+d4SyRSktrJSgqcfV27r 0Ygw4WNj5/kAqeTh+fF14kQS3o7UTqgUqtoBJ/bbS8H8Eqks/OsHAcnEwRJu08vLvVAm vXs4kwGpNsIUMFQOcO5DpTKQ7dD7GcMWOdpTqrEutBf/UD6CeY5Fnf5RcDFQ8adadMCF W71vRAHrNFJCFlhAv5zdlASDUkemC3i84V+H8bDLARzZ/0p4+fNAvdA6vq+kerxoTOJL ezbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9ouB9vz4LaWxmz+dvR+lSvNVqxELEdCuBWptGBdnlTg=; b=S3FZ02ynsvKhk0ObGDsjB77IXDxTTPS0W/I4r1jIC2hmVXUGyal0l4+6gK2c19hImg kCUsp7K2ZDEVhHv6FgvM6qP9tRX6MSbLVa6wDGZgljzdZV3wohFtJzN3APIesoTBmnAo wX7got/bpIYMkGNhjuktPUcz0CNKcHPvd5Wpy790ckUVpUk0LVxvnYsS+fKUxhSUpNl+ MWCeYDjETi7Ljhp4bUXyvCllbzqpMgFm/xh5tsH0fRjbQv6dtLNh89wN6Kw/8gnqmytH BFlh/wvKcR0wtgYdK6QctpN8Ci0ncx+/lU2w+U2OAy8VBX+KkSTBp5ptXYyUPiCYqjy6 qHVw== X-Gm-Message-State: AOAM533/NDqAj1o++EsnFtFbdR9cNRycgn7j2lYXgnumKZPToS0iyM5f 5ENjZQKH27Y7pZpQB25bURuP3w+K9iradg== X-Google-Smtp-Source: ABdhPJxHREDEMRdlzd6iI+H8T/fUhtrx6dC744qog7K9NaXmAG1tvjXO4lTk2ZY25dk5swlyXF/cxg== X-Received: by 2002:a5d:51c3:: with SMTP id n3mr12767261wrv.104.1595249793940; Mon, 20 Jul 2020 05:56:33 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p29sm34025403wmi.43.2020.07.20.05.56.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2020 05:56:32 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/12] hw/arm/armsse: Assert info->num_cpus is in-bounds in armsse_realize() Date: Mon, 20 Jul 2020 13:56:17 +0100 Message-Id: <20200720125621.13460-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200720125621.13460-1-peter.maydell@linaro.org> References: <20200720125621.13460-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" In armsse_realize() we have a loop over [0, info->num_cpus), which indexes into various fixed-size arrays in the ARMSSE struct. This confuses Coverity, which warns that we might overrun those arrays (CID 1430326, 1430337, 1430371, 1430414, 1430430). This can't actually happen, because the info struct is always one of the entries in the armsse_variants[] array and num_cpus is either 1 or 2; we also already assert in armsse_init() that num_cpus is not too large. However, adding an assert to armsse_realize() like the one in armsse_init() should help Coverity figure out that these code paths aren't possible. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20200713143716.9881-1-peter.maydell@linaro.org --- hw/arm/armsse.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 64fcab895f7..dcbff9bd8f4 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -452,6 +452,8 @@ static void armsse_realize(DeviceState *dev, Error **errp) return; } + assert(info->num_cpus <= SSE_MAX_CPUS); + /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */ assert(is_power_of_2(info->sram_banks)); addr_width_max = 24 - ctz32(info->sram_banks); From patchwork Mon Jul 20 12:56:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1332371 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=y5GZAcoH; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B9MN32Blbz9sRf for ; Mon, 20 Jul 2020 23:02:58 +1000 (AEST) Received: from localhost ([::1]:35418 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jxVRX-00047p-CX for incoming@patchwork.ozlabs.org; Mon, 20 Jul 2020 09:02:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55850) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jxVLS-0002Ya-KA for qemu-devel@nongnu.org; Mon, 20 Jul 2020 08:56:38 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:45470) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jxVLQ-0007Jj-Jl for qemu-devel@nongnu.org; Mon, 20 Jul 2020 08:56:38 -0400 Received: by mail-wr1-x42d.google.com with SMTP id s10so17690948wrw.12 for ; Mon, 20 Jul 2020 05:56:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=P4gnsXwsGRcRiwGn2A5K5QHmrCzJUCvt2/Zcs5cjl3E=; b=y5GZAcoH9WrQmtqsoxmcJfVed8YL6npKSRyb+TheylAO9gPAMvVsV7cdNZokPaUlr1 zg1zKvkmSJ2VbeMbNLAsXy2j6RUFHZs7ma3Uw4QdbcVUpHJaLk2CBonvxUvAOrLqCt5e XX+78Md4wLzDSGTPNyNZYZuBNwaEpxv7yugZ9mMaeyFvhQ7s78sOIWZHMlI9Y9wGDgyM JRyPSzv75AoYalZeHzwy81AtFDFh801PKCpNrN2THfyyWTPpRcxPGJS2JZ8aivSy9etd Ki9uBHBIC42TOD14+w5kgTB5vmmLBF2GImwuDrlrIsWD0bSIIb57EP8/TAgxiHtHhZhr Iu8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P4gnsXwsGRcRiwGn2A5K5QHmrCzJUCvt2/Zcs5cjl3E=; b=Jg0D3BoBvVzX0pe0jX0Qbbd7lb0rM0e+vLf7NGYsLfIdL83SwHh4KbXHTflODeqiTT 3/biD6In6JgOHnh5JTwlNvFq5qzb1eDc66cFbeOX6yadwpCpHV8mV+soTn2L1A6nZ0Sx 8N8b8+eRZfP0tpARK80CygvePxvOgch2FrUJ5wQ0P6mSlbVOgH87sR5CU34fY1Pihdjm nO6XV7rTbe4NiKOdob1iw2gEOeO2zblVekjSH/9m3DSvBBbAviQ1dB9vsfN7YNrzogAg tpfON0t2Cl4s1/AFlnkY8wICKWsO4AKw4UQO0xYi7iROroyHCVwC1IqEa8JlLl/Mdx0k rhLw== X-Gm-Message-State: AOAM530m0QFt51cQA82thm0HsPwguhqzKPF3d1OKlKdQad/h9CurtuXh 5TLjxvyz3v0KA35vMewHRUNoSe9Wcswr5g== X-Google-Smtp-Source: ABdhPJyeYNaCLPgLC+6x2xaL/bwYyH3rq354upXx1O1KQ7pa17YNhpEL55mZQXU0du2JhuhbYPWr5g== X-Received: by 2002:a5d:69c8:: with SMTP id s8mr21757642wrw.405.1595249794899; Mon, 20 Jul 2020 05:56:34 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p29sm34025403wmi.43.2020.07.20.05.56.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2020 05:56:34 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/12] docs/system: Briefly document canon-a1100 board Date: Mon, 20 Jul 2020 13:56:18 +0100 Message-Id: <20200720125621.13460-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200720125621.13460-1-peter.maydell@linaro.org> References: <20200720125621.13460-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add skeletal documentation of the canon-a1100 board. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Message-id: 20200713175746.5936-2-peter.maydell@linaro.org --- docs/system/arm/digic.rst | 11 +++++++++++ docs/system/target-arm.rst | 1 + MAINTAINERS | 1 + 3 files changed, 13 insertions(+) create mode 100644 docs/system/arm/digic.rst diff --git a/docs/system/arm/digic.rst b/docs/system/arm/digic.rst new file mode 100644 index 00000000000..2b3520ff5e1 --- /dev/null +++ b/docs/system/arm/digic.rst @@ -0,0 +1,11 @@ +Canon A1100 (``canon-a1100``) +============================= + +This machine is a model of the Canon PowerShot A1100 camera, which +uses the DIGIC SoC. This model is based on reverse engineering efforts +by the contributors to the `CHDK `_ and +`Magic Lantern `_ projects. + +The emulation is incomplete. In particular it can't be used +to run the original camera firmware, but it can successfully run +an experimental version of the `barebox bootloader `_. diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index 1bd477a2936..8fa51a22817 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -82,6 +82,7 @@ undocumented; you can get a complete list by running arm/versatile arm/vexpress arm/aspeed + arm/digic arm/musicpal arm/nseries arm/orangepi diff --git a/MAINTAINERS b/MAINTAINERS index 5d9c56e441d..9ed36dcf736 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -636,6 +636,7 @@ F: include/hw/arm/digic.h F: hw/*/digic* F: include/hw/*/digic* F: tests/acceptance/machine_arm_canona1100.py +F: docs/system/arm/digic.rst Goldfish RTC M: Anup Patel From patchwork Mon Jul 20 12:56:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1332372 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=jIrMUgcN; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B9MPp2mxgz9sRf for ; Mon, 20 Jul 2020 23:04:29 +1000 (AEST) Received: from localhost ([::1]:38182 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jxVT1-0005I5-2m for incoming@patchwork.ozlabs.org; Mon, 20 Jul 2020 09:04:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55860) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jxVLT-0002aR-EQ for qemu-devel@nongnu.org; Mon, 20 Jul 2020 08:56:39 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:41266) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jxVLR-0007Jr-M7 for qemu-devel@nongnu.org; Mon, 20 Jul 2020 08:56:39 -0400 Received: by mail-wr1-x42a.google.com with SMTP id z15so17720268wrl.8 for ; Mon, 20 Jul 2020 05:56:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/CYzeU7y3oLD60p/I26mnIKvepekcuC7eHDRGOCqlio=; b=jIrMUgcNk/3xzZpc8wqn+AZC2FIbCRomhHHdr4yY2EtVWwVvyB672+aYe9apaaAYIr XS3fbPiErib3cN5Vq2+GEDsAXhxmW4vWOnsX3/Zc0HwaFxBZYgLZcxeXvrWoSfO5+9DC wSq5pUkY0KGaW1OzGzFqp/i9y3St2LXzfGuV8jv2ESjanxAT+Ecv0dlE4MPo0V9rYCAu oZIM++7v8SYtKKfKPXCOwdBlUqu4Zzvo5nbEGBo4PoY6b1h80gTI0fIICs3XFjIEVGXc /HqTPoIsgVA1zlICzLSSCZuKEBDtwa3n9Ldb49BKAPrL3aZDGixLmgOtxwjS/XVJLB+M g4AA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/CYzeU7y3oLD60p/I26mnIKvepekcuC7eHDRGOCqlio=; b=uHoyW+5J5g//f8V4SOzHzLtyQYfK8L0+Np/AYmU4j3359oDtojC4OXFVhaxjjsZeqr X2CD0BorSPS/0hb38fAuezCdKy/U86jGY7XmuqYvnj9NOFS7ib4u/nejq+qqOEnzSr9j 8hPbwgi4owW7fHHhQHslexqCKsCCRF1UOK2YtvrnLpLDL899q392ygZitVJor/uqfun7 yvA3MKYUNnGKNOZCzB5HwIXlLKLrQ0sX6orPq+tWZbzJhCXP4RnqtFyM0ulWwXdWqE+U oDWK6JIaJNyTRrsgh9FTd5TQMrMw0Q5XpzC5yz6RHub4yxJzzVAHilWV34+hPVyHBEqg K7Cw== X-Gm-Message-State: AOAM533Sx3kelFIE7J+nBZ0I6PDNw9iOAg9ao6sBoIxzd8DATTxjbEk8 BXdm6vFvJjRdkZpVcDsL1hyReFy0gVYWbA== X-Google-Smtp-Source: ABdhPJy7lGoUnHHS2gXv+AkKpWXHvNySYYZv9RfLzYHfAn9DdJbo8JlgRQ5e89sowBCCse15BABidg== X-Received: by 2002:a5d:4991:: with SMTP id r17mr22004601wrq.1.1595249795937; Mon, 20 Jul 2020 05:56:35 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p29sm34025403wmi.43.2020.07.20.05.56.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2020 05:56:35 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/12] docs/system: Briefly document collie board Date: Mon, 20 Jul 2020 13:56:19 +0100 Message-Id: <20200720125621.13460-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200720125621.13460-1-peter.maydell@linaro.org> References: <20200720125621.13460-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add skeletal documentation of the collie board. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Message-id: 20200713175746.5936-3-peter.maydell@linaro.org --- docs/system/arm/collie.rst | 16 ++++++++++++++++ docs/system/target-arm.rst | 1 + MAINTAINERS | 1 + 3 files changed, 18 insertions(+) create mode 100644 docs/system/arm/collie.rst diff --git a/docs/system/arm/collie.rst b/docs/system/arm/collie.rst new file mode 100644 index 00000000000..5cc67b6d1b5 --- /dev/null +++ b/docs/system/arm/collie.rst @@ -0,0 +1,16 @@ +Sharp Zaurus SL-5500 (``collie``) +================================= + +This machine is a model of the Sharp Zaurus SL-5500, which was +a 1990s PDA based on the StrongARM SA1110. + +Implemented devices: + + * NOR flash + * Interrupt controller + * Timer + * RTC + * GPIO + * Peripheral Pin Controller (PPC) + * UARTs + * Synchronous Serial Ports (SSP) diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index 8fa51a22817..376c18f0b17 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -88,6 +88,7 @@ undocumented; you can get a complete list by running arm/orangepi arm/palm arm/xscale + arm/collie arm/sx1 arm/stellaris diff --git a/MAINTAINERS b/MAINTAINERS index 9ed36dcf736..6973b68975b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -847,6 +847,7 @@ L: qemu-arm@nongnu.org S: Odd Fixes F: hw/arm/collie.c F: hw/arm/strongarm* +F: docs/system/arm/collie.rst Stellaris M: Peter Maydell From patchwork Mon Jul 20 12:56:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1332366 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=pqFF4y8r; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B9MKG0VJLz9sRf for ; Mon, 20 Jul 2020 23:00:34 +1000 (AEST) Received: from localhost ([::1]:55072 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jxVPD-0000WP-Aj for incoming@patchwork.ozlabs.org; Mon, 20 Jul 2020 09:00:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55870) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jxVLU-0002d9-IY for qemu-devel@nongnu.org; Mon, 20 Jul 2020 08:56:40 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:35430) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jxVLS-0007K1-No for qemu-devel@nongnu.org; Mon, 20 Jul 2020 08:56:40 -0400 Received: by mail-wm1-x32e.google.com with SMTP id l2so25113136wmf.0 for ; Mon, 20 Jul 2020 05:56:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/Qnf6IlQrDPLH/pkVSmr5xzm83LBS6FFFF/CTFBek8g=; b=pqFF4y8rG5Vq+nRbEG55pG7cz0N1nbAlVwto+6yIx7670BaJJctppqRFI2zZQDp+pq IjlvIE/cuaymq3rBYiI18EwDSoJWgnjFeQLVwaK+I1vTI8CZXNehp+ZUYd2rvC0i+xG7 ZtCKF6sCKM5IkSHn2jVuMXR+gjjf1eKImpCdUZTlg7t2Yx4yWB0hLmRM4E2vRKdrQsrS WK6VOjR97xaYPxget+rlYPj/IUg+6jlwtRJ/TvnWWdTqPQIiJ5LdbXlEkJbib9AhpzQc Yi77g43Rc1LIW9yLN8VXpwcYO0T1CTFZSGynowk58fTkdFbeLK1tChYGnDt+E6VB5EIM qbKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/Qnf6IlQrDPLH/pkVSmr5xzm83LBS6FFFF/CTFBek8g=; b=hn65XCDmVnBKb6jXp6ZEbkFWB3/mC1/0bgSX2tvw/YsezCeG+3p1+7KpjrYPE14rl2 uWMo2RYZzSba6Dn+/k91/M2diRPR0ZSXP2jkB7Ir2ei+JoMWpDgBFlRnRJVVETWr9G0u frtzHuJHcoJarfWMzOykgGIUWCvJ3ebmLvUKiMFcovaaJZffnc2c/WFlUgzmCChWHkeQ 8je6M0DwCWPRfrsql+ysFhD0s5Fb3+9nNeTg0D1MZyPrS5pvimfWQCIGQDiemAKlvD7E sUNQ+wGfxkFo0Jm2KLShyhPC6cJxDhQBLoJD5qwivmTHEUeM48vH9ROafUsLTqqzDVCm nUJw== X-Gm-Message-State: AOAM530mWM35euuKFuvRKUS657WbVAy+lMNLY9/F50E9L8pEK+bin33c bg15rge0M8oPtZEIWwOqx6SnBJFiiEhVNg== X-Google-Smtp-Source: ABdhPJxwcLLRjT8x64EQZNWucbVPDiljf64/9AEws0McFI8cEuTeQ1XZuI4aNnz73uVWAPIgTNSIew== X-Received: by 2002:a1c:6308:: with SMTP id x8mr22325336wmb.92.1595249797086; Mon, 20 Jul 2020 05:56:37 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p29sm34025403wmi.43.2020.07.20.05.56.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2020 05:56:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/12] docs/system: Briefly document gumstix boards Date: Mon, 20 Jul 2020 13:56:20 +0100 Message-Id: <20200720125621.13460-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200720125621.13460-1-peter.maydell@linaro.org> References: <20200720125621.13460-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add skeletal documentation of the gumstix boards ('connex' and 'verdex'). Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Message-id: 20200713175746.5936-4-peter.maydell@linaro.org --- docs/system/arm/gumstix.rst | 21 +++++++++++++++++++++ docs/system/target-arm.rst | 1 + MAINTAINERS | 1 + 3 files changed, 23 insertions(+) create mode 100644 docs/system/arm/gumstix.rst diff --git a/docs/system/arm/gumstix.rst b/docs/system/arm/gumstix.rst new file mode 100644 index 00000000000..cb373139dcb --- /dev/null +++ b/docs/system/arm/gumstix.rst @@ -0,0 +1,21 @@ +Gumstix Connex and Verdex (``connex``, ``verdex``) +================================================== + +These machines model the Gumstix Connex and Verdex boards. +The Connex has a PXA255 CPU and the Verdex has a PXA270. + +Implemented devices: + + * NOR flash + * SMC91C111 ethernet + * Interrupt controller + * DMA + * Timer + * GPIO + * MMC/SD card + * Fast infra-red communications port (FIR) + * LCD controller + * Synchronous serial ports (SPI) + * PCMCIA interface + * I2C + * I2S diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index 376c18f0b17..163ab915592 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -84,6 +84,7 @@ undocumented; you can get a complete list by running arm/aspeed arm/digic arm/musicpal + arm/gumstix arm/nseries arm/orangepi arm/palm diff --git a/MAINTAINERS b/MAINTAINERS index 6973b68975b..935ccb3ab31 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -652,6 +652,7 @@ R: Philippe Mathieu-Daudé L: qemu-arm@nongnu.org S: Odd Fixes F: hw/arm/gumstix.c +F: docs/system/arm/gumstix.rst i.MX25 PDK M: Peter Maydell From patchwork Mon Jul 20 12:56:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1332375 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p29sm34025403wmi.43.2020.07.20.05.56.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2020 05:56:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/12] docs/system: Document the arm virt board Date: Mon, 20 Jul 2020 13:56:21 +0100 Message-Id: <20200720125621.13460-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200720125621.13460-1-peter.maydell@linaro.org> References: <20200720125621.13460-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Document the arm 'virt' board, which has been undocumented for far too long given that it is the main recommended board type for arm guests. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Message-id: 20200713175746.5936-5-peter.maydell@linaro.org --- docs/system/arm/virt.rst | 161 +++++++++++++++++++++++++++++++++++++ docs/system/target-arm.rst | 1 + MAINTAINERS | 1 + 3 files changed, 163 insertions(+) create mode 100644 docs/system/arm/virt.rst diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst new file mode 100644 index 00000000000..6621ab7205d --- /dev/null +++ b/docs/system/arm/virt.rst @@ -0,0 +1,161 @@ +'virt' generic virtual platform (``virt``) +========================================== + +The `virt` board is a platform which does not correspond to any +real hardware; it is designed for use in virtual machines. +It is the recommended board type if you simply want to run +a guest such as Linux and do not care about reproducing the +idiosyncrasies and limitations of a particular bit of real-world +hardware. + +This is a "versioned" board model, so as well as the ``virt`` machine +type itself (which may have improvements, bugfixes and other minor +changes between QEMU versions) a version is provided that guarantees +to have the same behaviour as that of previous QEMU releases, so +that VM migration will work between QEMU versions. For instance the +``virt-5.0`` machine type will behave like the ``virt`` machine from +the QEMU 5.0 release, and migration should work between ``virt-5.0`` +of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration +is not guaranteed to work between different QEMU releases for +the non-versioned ``virt`` machine type. + +Supported devices +""""""""""""""""" + +The virt board supports: + +- PCI/PCIe devices +- Flash memory +- One PL011 UART +- An RTC +- The fw_cfg device that allows a guest to obtain data from QEMU +- A PL061 GPIO controller +- An optional SMMUv3 IOMMU +- hotpluggable DIMMs +- hotpluggable NVDIMMs +- An MSI controller (GICv2M or ITS). GICv2M is selected by default along + with GICv2. ITS is selected by default with GICv3 (>= virt-2.7). Note + that ITS is not modeled in TCG mode. +- 32 virtio-mmio transport devices +- running guests using the KVM accelerator on aarch64 hardware +- large amounts of RAM (at least 255GB, and more if using highmem) +- many CPUs (up to 512 if using a GICv3 and highmem) +- Secure-World-only devices if the CPU has TrustZone: + + - A second PL011 UART + - A secure flash memory + - 16MB of secure RAM + +Supported guest CPU types: + +- ``cortex-a7`` (32-bit) +- ``cortex-a15`` (32-bit; the default) +- ``cortex-a53`` (64-bit) +- ``cortex-a57`` (64-bit) +- ``cortex-a72`` (64-bit) +- ``host`` (with KVM only) +- ``max`` (same as ``host`` for KVM; best possible emulation with TCG) + +Note that the default is ``cortex-a15``, so for an AArch64 guest you must +specify a CPU type. + +Graphics output is available, but unlike the x86 PC machine types +there is no default display device enabled: you should select one from +the Display devices section of "-device help". The recommended option +is ``virtio-gpu-pci``; this is the only one which will work correctly +with KVM. You may also need to ensure your guest kernel is configured +with support for this; see below. + +Machine-specific options +"""""""""""""""""""""""" + +The following machine-specific options are supported: + +secure + Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the + Arm Security Extensions (TrustZone). The default is ``off``. + +virtualization + Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the + Arm Virtualization Extensions. The default is ``off``. + +highmem + Set ``on``/``off`` to enable/disable placing devices and RAM in physical + address space above 32 bits. The default is ``on`` for machine types + later than ``virt-2.12``. + +gic-version + Specify the version of the Generic Interrupt Controller (GIC) to provide. + Valid values are: + + ``2`` + GICv2 + ``3`` + GICv3 + ``host`` + Use the same GIC version the host provides, when using KVM + ``max`` + Use the best GIC version possible (same as host when using KVM; + currently same as ``3``` for TCG, but this may change in future) + +its + Set ``on``/``off`` to enable/disable ITS instantiation. The default is ``on`` + for machine types later than ``virt-2.7``. + +iommu + Set the IOMMU type to create for the guest. Valid values are: + + ``none`` + Don't create an IOMMU (the default) + ``smmuv3`` + Create an SMMUv3 + +ras + Set ``on``/``off`` to enable/disable reporting host memory errors to a guest + using ACPI and guest external abort exceptions. The default is off. + +Linux guest kernel configuration +"""""""""""""""""""""""""""""""" + +The 'defconfig' for Linux arm and arm64 kernels should include the +right device drivers for virtio and the PCI controller; however some older +kernel versions, especially for 32-bit Arm, did not have everything +enabled by default. If you're not seeing PCI devices that you expect, +then check that your guest config has:: + + CONFIG_PCI=y + CONFIG_VIRTIO_PCI=y + CONFIG_PCI_HOST_GENERIC=y + +If you want to use the ``virtio-gpu-pci`` graphics device you will also +need:: + + CONFIG_DRM=y + CONFIG_DRM_VIRTIO_GPU=y + +Hardware configuration information for bare-metal programming +""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" + +The ``virt`` board automatically generates a device tree blob ("dtb") +which it passes to the guest. This provides information about the +addresses, interrupt lines and other configuration of the various devices +in the system. Guest code can rely on and hard-code the following +addresses: + +- Flash memory starts at address 0x0000_0000 + +- RAM starts at 0x4000_0000 + +All other information about device locations may change between +QEMU versions, so guest code must look in the DTB. + +QEMU supports two types of guest image boot for ``virt``, and +the way for the guest code to locate the dtb binary differs: + +- For guests using the Linux kernel boot protocol (this means any + non-ELF file passed to the QEMU ``-kernel`` option) the address + of the DTB is passed in a register (``r2`` for 32-bit guests, + or ``x0`` for 64-bit guests) + +- For guests booting as "bare-metal" (any other kind of boot), + the DTB is at the start of RAM (0x4000_0000) diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index 163ab915592..4c5b0e4aab8 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -92,6 +92,7 @@ undocumented; you can get a complete list by running arm/collie arm/sx1 arm/stellaris + arm/virt Arm CPU features ================ diff --git a/MAINTAINERS b/MAINTAINERS index 935ccb3ab31..5e8616821a5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -880,6 +880,7 @@ L: qemu-arm@nongnu.org S: Maintained F: hw/arm/virt* F: include/hw/arm/virt.h +F: docs/system/arm/virt.rst Xilinx Zynq M: Edgar E. Iglesias