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[73.14.175.90]) by smtp.gmail.com with ESMTPSA id 28sm3790693ilv.17.2020.07.16.20.22.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2020 20:22:50 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Wolfgang Wallner , Bin Meng , Andy Shevchenko , Simon Glass Subject: [PATCH v3 01/10] x86: apl: Fix save/restore of ITSS priorities Date: Thu, 16 Jul 2020 21:22:30 -0600 Message-Id: <20200716212232.v3.1.I47b041ba995bc87537c2b8b03e5c5dbee96ad725@changeid> X-Mailer: git-send-email 2.28.0.rc0.105.gf9edc3c819-goog In-Reply-To: <20200717032239.197695-1-sjg@chromium.org> References: <20200717032239.197695-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean The FSP-S changes the ITSS priorities. The code that tries to save it before running FSP-S and restore it afterwards does not work as U-Boot relocates in between the save and restore. This means that the driver data saved before relocation is lost and the new driver just sees zeroes. Fix this by allocating space in the relocated memory for the ITSS data. Save it there and access it from the driver after relocation. This fixes interrupt handling on coral. Also drop the log_msg_ret() in irq_first_device_type() since this function can be called speculatively in places where we are not sure if there is an interrupt controller of that type. The resulting log errors are confusing when there is no error. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Reviewed-by: Wolfgang Wallner --- (no changes since v2) Changes in v2: - Add mention of why log_msg_ret() is dropped arch/x86/cpu/apollolake/fsp_s.c | 11 +++++------ arch/x86/cpu/cpu.c | 18 +++++++++++++++--- arch/x86/cpu/intel_common/itss.c | 25 +++++++++++++++++++++++-- arch/x86/include/asm/global_data.h | 1 + arch/x86/include/asm/itss.h | 2 +- drivers/misc/irq-uclass.c | 2 +- 6 files changed, 46 insertions(+), 13 deletions(-) diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c index 3a54297a28..e54b0ac104 100644 --- a/arch/x86/cpu/apollolake/fsp_s.c +++ b/arch/x86/cpu/apollolake/fsp_s.c @@ -160,11 +160,6 @@ int arch_fsps_preinit(void) ret = irq_first_device_type(X86_IRQT_ITSS, &itss); if (ret) return log_msg_ret("no itss", ret); - /* - * Snapshot the current GPIO IRQ polarities. FSP is setting a default - * policy that doesn't honour boards' requirements - */ - irq_snapshot_polarities(itss); /* * Clear the GPI interrupt status and enable registers. These @@ -203,7 +198,11 @@ int arch_fsp_init_r(void) ret = irq_first_device_type(X86_IRQT_ITSS, &itss); if (ret) return log_msg_ret("no itss", ret); - /* Restore GPIO IRQ polarities back to previous settings */ + + /* + * Restore GPIO IRQ polarities back to previous settings. This was + * stored in reserve_arch() - see X86_IRQT_ITSS + */ irq_restore_polarities(itss); /* soc_init() */ diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 23a4d633d2..9ef797b41b 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -269,9 +270,11 @@ int cpu_init_r(void) #ifndef CONFIG_EFI_STUB int reserve_arch(void) { -#ifdef CONFIG_ENABLE_MRC_CACHE - mrccache_reserve(); -#endif + struct udevice *itss; + int ret; + + if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) + mrccache_reserve(); #ifdef CONFIG_SEABIOS high_table_reserve(); @@ -288,6 +291,15 @@ int reserve_arch(void) fsp_save_s3_stack(); } } + ret = irq_first_device_type(X86_IRQT_ITSS, &itss); + if (!ret) { + /* + * Snapshot the current GPIO IRQ polarities. FSP-S is about to + * run and will set a default policy that doesn't honour boards' + * requirements + */ + irq_snapshot_polarities(itss); + } return 0; } diff --git a/arch/x86/cpu/intel_common/itss.c b/arch/x86/cpu/intel_common/itss.c index 963afa8f5b..fe84ebe29f 100644 --- a/arch/x86/cpu/intel_common/itss.c +++ b/arch/x86/cpu/intel_common/itss.c @@ -65,14 +65,23 @@ static int snapshot_polarities(struct udevice *dev) int i; reg_start = start / IRQS_PER_IPC; - reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC; + reg_end = DIV_ROUND_UP(end, IRQS_PER_IPC); + log_info("ITSS IRQ Polarities snapshot %p\n", priv->irq_snapshot); for (i = reg_start; i < reg_end; i++) { uint reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i; priv->irq_snapshot[i] = pcr_read32(dev, reg); + log_debug(" - %d, reg %x: irq_snapshot[i] %x\n", i, reg, + priv->irq_snapshot[i]); } + /* Save the snapshot for use after relocation */ + gd->start_addr_sp -= sizeof(*priv); + gd->start_addr_sp &= ~0xf; + gd->arch.itss_priv = (void *)gd->start_addr_sp; + memcpy(gd->arch.itss_priv, priv, sizeof(*priv)); + return 0; } @@ -91,16 +100,26 @@ static void show_polarities(struct udevice *dev, const char *msg) static int restore_polarities(struct udevice *dev) { struct itss_priv *priv = dev_get_priv(dev); + struct itss_priv *old_priv; const int start = GPIO_IRQ_START; const int end = GPIO_IRQ_END; int reg_start; int reg_end; int i; + /* Get the snapshot which was stored by the pre-reloc device */ + old_priv = gd->arch.itss_priv; + if (!old_priv) + return log_msg_ret("priv", -EFAULT); + memcpy(priv->irq_snapshot, old_priv->irq_snapshot, + sizeof(priv->irq_snapshot)); + show_polarities(dev, "Before"); + log_info("priv->irq_snapshot %p\n", priv->irq_snapshot); reg_start = start / IRQS_PER_IPC; - reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC; + reg_end = DIV_ROUND_UP(end, IRQS_PER_IPC); + for (i = reg_start; i < reg_end; i++) { u32 mask; @@ -125,6 +144,8 @@ static int restore_polarities(struct udevice *dev) mask &= ~((1U << irq_start) - 1); reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i; + log_debug(" - %d, reg %x: mask %x, irq_snapshot[i] %x\n", + i, reg, mask, priv->irq_snapshot[i]); pcr_clrsetbits32(dev, reg, mask, mask & priv->irq_snapshot[i]); } diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 0e64c8a46d..5bc251c0dd 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -121,6 +121,7 @@ struct arch_global_data { #ifdef CONFIG_FSP_VERSION2 struct fsp_header *fsp_s_hdr; /* Pointer to FSP-S header */ #endif + void *itss_priv; /* Private ITSS data pointer */ ulong acpi_start; /* Start address of ACPI tables */ }; diff --git a/arch/x86/include/asm/itss.h b/arch/x86/include/asm/itss.h index c75d8fe8c2..f7d3240384 100644 --- a/arch/x86/include/asm/itss.h +++ b/arch/x86/include/asm/itss.h @@ -16,7 +16,7 @@ #define ITSS_MAX_IRQ 119 #define IRQS_PER_IPC 32 -#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1) / IRQS_PER_IPC) +#define NUM_IPC_REGS DIV_ROUND_UP(ITSS_MAX_IRQ, IRQS_PER_IPC) /* Max PXRC registers in ITSS */ #define MAX_PXRC_CONFIG (PCR_ITSS_PIRQH_ROUT - PCR_ITSS_PIRQA_ROUT + 1) diff --git a/drivers/misc/irq-uclass.c b/drivers/misc/irq-uclass.c index 8727a33dd9..94fa233f19 100644 --- a/drivers/misc/irq-uclass.c +++ b/drivers/misc/irq-uclass.c @@ -168,7 +168,7 @@ int irq_first_device_type(enum irq_dev_t type, struct udevice **devp) ret = uclass_first_device_drvdata(UCLASS_IRQ, type, devp); if (ret) - return log_msg_ret("find", ret); + return ret; return 0; } From patchwork Fri Jul 17 03:22:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1330691 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=mK4Ex/gZ; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B7Gfg371vz9sRN for ; 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[73.14.175.90]) by smtp.gmail.com with ESMTPSA id 28sm3790693ilv.17.2020.07.16.20.22.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2020 20:22:51 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Wolfgang Wallner , Bin Meng , Andy Shevchenko , Simon Glass Subject: [PATCH v3 02/10] x86: Add debugging to table writing Date: Thu, 16 Jul 2020 21:22:31 -0600 Message-Id: <20200716212232.v3.2.I7759eca88ecdfe2cab1769ab2c28828f5b026012@changeid> X-Mailer: git-send-email 2.28.0.rc0.105.gf9edc3c819-goog In-Reply-To: <20200717032239.197695-1-sjg@chromium.org> References: <20200717032239.197695-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Writing tables is currently pretty opaque. Add a bit of debugging to the process so we can see what tables are written and where they start/end in memory. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Reviewed-by: Wolfgang Wallner --- (no changes since v1) arch/x86/lib/tables.c | 38 ++++++++++++++++++++++++++++---------- 1 file changed, 28 insertions(+), 10 deletions(-) diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index 574d331d76..7bad5dd303 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -20,21 +21,32 @@ */ typedef ulong (*table_write)(ulong addr); -static table_write table_write_funcs[] = { +/** + * struct table_info - Information about each table to write + * + * @name: Name of table (for debugging) + * @write: Function to call to write this table + */ +struct table_info { + const char *name; + table_write write; +}; + +static struct table_info table_list[] = { #ifdef CONFIG_GENERATE_PIRQ_TABLE - write_pirq_routing_table, + { "pirq", write_pirq_routing_table }, #endif #ifdef CONFIG_GENERATE_SFI_TABLE - write_sfi_table, + { "sfi", write_sfi_table, }, #endif #ifdef CONFIG_GENERATE_MP_TABLE - write_mp_table, + { "mp", write_mp_table, }, #endif #ifdef CONFIG_GENERATE_ACPI_TABLE - write_acpi_tables, + { "acpi", write_acpi_tables, }, #endif #ifdef CONFIG_GENERATE_SMBIOS_TABLE - write_smbios_table, + { "smbios", write_smbios_table, }, #endif }; @@ -58,19 +70,22 @@ void write_tables(void) u32 rom_table_end; #ifdef CONFIG_SEABIOS u32 high_table, table_size; - struct memory_area cfg_tables[ARRAY_SIZE(table_write_funcs) + 1]; + struct memory_area cfg_tables[ARRAY_SIZE(table_list) + 1]; #endif int i; - for (i = 0; i < ARRAY_SIZE(table_write_funcs); i++) { - rom_table_end = table_write_funcs[i](rom_table_start); + debug("Writing tables to %x:\n", rom_table_start); + for (i = 0; i < ARRAY_SIZE(table_list); i++) { + const struct table_info *table = &table_list[i]; + + rom_table_end = table->write(rom_table_start); rom_table_end = ALIGN(rom_table_end, ROM_TABLE_ALIGN); #ifdef CONFIG_SEABIOS table_size = rom_table_end - rom_table_start; high_table = (u32)high_table_malloc(table_size); if (high_table) { - table_write_funcs[i](high_table); + table->write(high_table); cfg_tables[i].start = high_table; cfg_tables[i].size = table_size; @@ -79,6 +94,8 @@ void write_tables(void) } #endif + debug("- wrote '%s' to %x, end %x\n", table->name, + rom_table_start, rom_table_end); rom_table_start = rom_table_end; } @@ -87,4 +104,5 @@ void write_tables(void) cfg_tables[i].size = 0; write_coreboot_table(CB_TABLE_ADDR, cfg_tables); #endif + debug("- done writing tables\n"); } From patchwork Fri Jul 17 03:22:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1330692 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=BrCtt3iH; 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[73.14.175.90]) by smtp.gmail.com with ESMTPSA id 28sm3790693ilv.17.2020.07.16.20.22.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2020 20:22:52 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Wolfgang Wallner , Bin Meng , Andy Shevchenko , Simon Glass Subject: [PATCH v3 03/10] x86: apl: Set the correct boot mode in the FSP-M code Date: Thu, 16 Jul 2020 21:22:32 -0600 Message-Id: <20200717032239.197695-2-sjg@chromium.org> X-Mailer: git-send-email 2.28.0.rc0.105.gf9edc3c819-goog In-Reply-To: <20200717032239.197695-1-sjg@chromium.org> References: <20200717032239.197695-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean If there is MRC information we should run FSP-M with a different boot_mode flag since it is supposed to do a 'fast path' through the memory init. Fix this. Signed-off-by: Simon Glass Reviewed-by: Wolfgang Wallner Reviewed-by: Bin Meng --- (no changes since v2) Changes in v2: - Add a new commit to handle the boot_mode fix arch/x86/cpu/apollolake/fsp_m.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c index 65461d85b8..e19a2b0826 100644 --- a/arch/x86/cpu/apollolake/fsp_m.c +++ b/arch/x86/cpu/apollolake/fsp_m.c @@ -26,7 +26,8 @@ int fspm_update_config(struct udevice *dev, struct fspm_upd *upd) return log_msg_ret("mrc", cache_ret); arch->stack_base = (void *)0xfef96000; arch->boot_loader_tolum_size = 0; - arch->boot_mode = FSP_BOOT_WITH_FULL_CONFIGURATION; + arch->boot_mode = cache_ret ? FSP_BOOT_WITH_FULL_CONFIGURATION : + FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; node = dev_ofnode(dev); if (!ofnode_valid(node)) From patchwork Fri Jul 17 03:22:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1330693 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=MiY6V9hW; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B7Gg43kFmz9sRN for ; Fri, 17 Jul 2020 13:23:44 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 293D681C24; Fri, 17 Jul 2020 05:23:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="MiY6V9hW"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 55BF781C18; Fri, 17 Jul 2020 05:22:58 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-io1-xd41.google.com (mail-io1-xd41.google.com [IPv6:2607:f8b0:4864:20::d41]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A822081BF7 for ; Fri, 17 Jul 2020 05:22:54 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-io1-xd41.google.com with SMTP id l1so8937252ioh.5 for ; Thu, 16 Jul 2020 20:22:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ukfiz0r9Wd3Lt/36EUICjKZlD4BYa2RMLofpqVngGHg=; b=MiY6V9hW2Jq7/nwt+XYwjntbVs7OQ2dlz1KK7lDYydT1oEAy+1CZToyZMkS/O4vqpl +mE1whhctpwafww5CFFctDdG+6WoxSYI7+6yPiW92X3/MJDaX7uCMWkpverV/2iJRdc7 i6OSfhxXGW7uKpy7pUZCYzZWAw65hAgz9ewts= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ukfiz0r9Wd3Lt/36EUICjKZlD4BYa2RMLofpqVngGHg=; b=skfOU9qslyTdKseL5fIwv4y7C1m4O15FAiQe0EfyIW7GlF8+VUuWUtSUZ01sbKmOQC 45SJ4uFvU/7RBq4E8AeaIlhM3Q+9SmZHFk7fjI661DTn/qwk8Y8CRp3bySS/lRvEdhvu +i9uctXUS74YNzYLSi+2zm/UUVk7kXbCebeANH3rTAsVTt574keHajmFYKnK56aiemBE 8F8jcj/slolt6ZorctNMJadQTNk3FKhOjKGe8DE3n7xUU/JhUN6Qenog6F5HcXUWuWQt VUwP/oquk9qpAfmnJKvwXBVQOM0evng8wNfmPxiozk13Y5khMsOjd9q+2OItUQagdSZ6 hfDg== X-Gm-Message-State: AOAM530TBJwB5ywsBWXH95BopOey8G9YAnGQDzYnAWmYf6Ty1cVp8pcw QE/tR5zXVbgfIws2aLjJHpINnF0yHFd0KQ== X-Google-Smtp-Source: ABdhPJyy62uBR0IAe89Cx/GGEqFLXX1MpMAkV5wGvKJGKSeQQZtybJSBZHfhxzo6+JoEsOzVUBnJcg== X-Received: by 2002:a05:6602:1611:: with SMTP id x17mr848465iow.32.1594956173461; Thu, 16 Jul 2020 20:22:53 -0700 (PDT) Received: from localhost.localdomain (c-73-14-175-90.hsd1.co.comcast.net. [73.14.175.90]) by smtp.gmail.com with ESMTPSA id 28sm3790693ilv.17.2020.07.16.20.22.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2020 20:22:53 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Wolfgang Wallner , Bin Meng , Andy Shevchenko , Simon Glass Subject: [PATCH v3 04/10] x86: apl: Adjust FSP-M code to avoid hard-coded address Date: Thu, 16 Jul 2020 21:22:33 -0600 Message-Id: <20200717032239.197695-3-sjg@chromium.org> X-Mailer: git-send-email 2.28.0.rc0.105.gf9edc3c819-goog In-Reply-To: <20200717032239.197695-1-sjg@chromium.org> References: <20200717032239.197695-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Update this code to calculate the address to use, rather than hard-coding it. Obtain the requested stack size from the FSP. Signed-off-by: Simon Glass Reviewed-by: Wolfgang Wallner Reviewed-by: Bin Meng --- (no changes since v2) Changes in v2: - Split out the boot_mode change into a separate patch arch/x86/cpu/apollolake/fsp_m.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c index e19a2b0826..cef937573b 100644 --- a/arch/x86/cpu/apollolake/fsp_m.c +++ b/arch/x86/cpu/apollolake/fsp_m.c @@ -24,7 +24,8 @@ int fspm_update_config(struct udevice *dev, struct fspm_upd *upd) cache_ret = prepare_mrc_cache(upd); if (cache_ret && cache_ret != -ENOENT) return log_msg_ret("mrc", cache_ret); - arch->stack_base = (void *)0xfef96000; + arch->stack_base = (void *)(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - + arch->stack_size); arch->boot_loader_tolum_size = 0; arch->boot_mode = cache_ret ? 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[73.14.175.90]) by smtp.gmail.com with ESMTPSA id 28sm3790693ilv.17.2020.07.16.20.22.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2020 20:22:53 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Wolfgang Wallner , Bin Meng , Andy Shevchenko , Simon Glass Subject: [PATCH v3 05/10] x86: Store the coreboot table address in global_data Date: Thu, 16 Jul 2020 21:22:34 -0600 Message-Id: <20200717032239.197695-4-sjg@chromium.org> X-Mailer: git-send-email 2.28.0.rc0.105.gf9edc3c819-goog In-Reply-To: <20200717032239.197695-1-sjg@chromium.org> References: <20200717032239.197695-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean At present this information is used to locate and parse the tables but is not stored. Store it so that we can display it to the user, e.g. with the 'bdinfo' command. Note that now the GD_FLG_SKIP_LL_INIT flag is set in get_coreboot_info(), so it is always set when booting from coreboot. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Reviewed-by: Wolfgang Wallner --- Changes in v3: - Update the commit message with an explanation of GD_FLG_SKIP_LL_INIT arch/x86/cpu/coreboot/tables.c | 8 +++++++- arch/x86/cpu/i386/cpu.c | 7 ++++++- arch/x86/include/asm/global_data.h | 1 + 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c index a5d31d1dea..1594b4a8b2 100644 --- a/arch/x86/cpu/coreboot/tables.c +++ b/arch/x86/cpu/coreboot/tables.c @@ -10,6 +10,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + /* * This needs to be in the .data section so that it's copied over during * relocation. By default it's put in the .bss section which is simply filled @@ -243,6 +245,10 @@ int get_coreboot_info(struct sysinfo_t *info) if (addr < 0) return addr; ret = cb_parse_header((void *)addr, 0x1000, info); + if (!ret) + return -ENOENT; + gd->arch.coreboot_table = addr; + gd->flags |= GD_FLG_SKIP_LL_INIT; - return ret == 1 ? 0 : -ENOENT; + return 0; } diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index d27324cb4e..a6a6afec8c 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -455,10 +455,15 @@ int x86_cpu_init_f(void) int x86_cpu_reinit_f(void) { + long addr; + setup_identity(); setup_pci_ram_top(); - if (locate_coreboot_table() >= 0) + addr = locate_coreboot_table(); + if (addr >= 0) { + gd->arch.coreboot_table = addr; gd->flags |= GD_FLG_SKIP_LL_INIT; + } return 0; } diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 5bc251c0dd..3e4044593c 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -123,6 +123,7 @@ struct arch_global_data { #endif void *itss_priv; /* Private ITSS data pointer */ ulong acpi_start; /* Start address of ACPI tables */ + ulong coreboot_table; /* Address of coreboot table */ }; #endif From patchwork Fri Jul 17 03:22:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1330695 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=a53PM1Zj; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B7Ggb3kW5z9sRN for ; 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[73.14.175.90]) by smtp.gmail.com with ESMTPSA id 28sm3790693ilv.17.2020.07.16.20.22.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2020 20:22:54 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Wolfgang Wallner , Bin Meng , Andy Shevchenko , Simon Glass Subject: [PATCH v3 06/10] x86: Update the comment about booting for FSP2 Date: Thu, 16 Jul 2020 21:22:35 -0600 Message-Id: <20200717032239.197695-5-sjg@chromium.org> X-Mailer: git-send-email 2.28.0.rc0.105.gf9edc3c819-goog In-Reply-To: <20200717032239.197695-1-sjg@chromium.org> References: <20200717032239.197695-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean The comment here applies only to FSP1, so update it. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Reviewed-by: Wolfgang Wallner --- (no changes since v1) arch/x86/cpu/start.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 01524635e9..4ad515ce08 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -124,6 +124,7 @@ car_init_ret: #endif #else /* + * Instructions for FSP1, but not FSP2: * U-Boot enters here twice. For the first time it comes from * car_init_done() with esp points to a temporary stack and esi * set to zero. For the second time it comes from fsp_init_done() From patchwork Fri Jul 17 03:22:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1330696 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=EdLFc3Ru; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B7Ggp2zjVz9sRN for ; Fri, 17 Jul 2020 13:24:22 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D01BE81D71; Fri, 17 Jul 2020 05:23:23 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="EdLFc3Ru"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 01A5881C26; Fri, 17 Jul 2020 05:23:01 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-io1-xd44.google.com (mail-io1-xd44.google.com [IPv6:2607:f8b0:4864:20::d44]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 797A881BFD for ; Fri, 17 Jul 2020 05:22:57 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-io1-xd44.google.com with SMTP id f23so8931920iof.6 for ; Thu, 16 Jul 2020 20:22:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Deo3mKe+fblRaRrSSV+aY0H81EtdYlW7qdixpFHd10c=; b=EdLFc3Ru7wFcooA+J90NFbu/04EU3GCON8aA112MFRrI2zEXCWHPDpn4r7Ooh9LXr9 2D2L/0jJZtx1+LjW0pWEUIUtu3YLMx6CYCB4kTzsZgNxypbmMYR1QVrbPfdcpupiIcWd DrkB//H0fhvE8hR2tiCLSnciwfgSuvMJ2vw3U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Deo3mKe+fblRaRrSSV+aY0H81EtdYlW7qdixpFHd10c=; b=H+hNog5zjwYe8u5TFurt1BiHyoTtoAh8RIdkJ+it8IzjZSYwvwGVRUhOxp/nsZAyMm 5H+es78+g5QImgNYe7HDdNs4b61IHCMRQbj8j1BWl38SvJ69srfKPfYOYTnnMOi2q8EL RsNcud78MVe5ACphR418vQIGwClcOzSnzLG5RfsDKSDMlUYQ308JrnoB4MkDVooqt5sa BwKplJ289JYhksBD3UUew7HXp3QyH/VbVzK/fyYVVpv/UQkJz/yCNkF/Ir4WxcVyztLC +chaM7//yZ+JaJJDSe4/SFtyNDXTJZaQ0kLermBowtsEMyNCxG6anhfcH11CXp6suTgF WOKA== X-Gm-Message-State: AOAM533jLHfy90WO9xLf8UXCICjLronDOPxm/pvwrIx2B2MBdW5g5547 ZC9VYPzw8ORJ08Es3/tolLNdUvwLMqG0bA== X-Google-Smtp-Source: ABdhPJwlOluSSEBPJVZ8wCKIzIUwA1BnZERlN/ixgaLchX1+C6DCbvnRrrs18IKIOmSYD326Enujzw== X-Received: by 2002:a92:8451:: with SMTP id l78mr7839217ild.234.1594956176207; Thu, 16 Jul 2020 20:22:56 -0700 (PDT) Received: from localhost.localdomain (c-73-14-175-90.hsd1.co.comcast.net. [73.14.175.90]) by smtp.gmail.com with ESMTPSA id 28sm3790693ilv.17.2020.07.16.20.22.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2020 20:22:55 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Wolfgang Wallner , Bin Meng , Andy Shevchenko , Simon Glass Subject: [PATCH v3 07/10] x86: Drop setup_pcat_compatibility() Date: Thu, 16 Jul 2020 21:22:36 -0600 Message-Id: <20200717032239.197695-6-sjg@chromium.org> X-Mailer: git-send-email 2.28.0.rc0.105.gf9edc3c819-goog In-Reply-To: <20200717032239.197695-1-sjg@chromium.org> References: <20200717032239.197695-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean This function does not exist anymore. Drop it from the header file. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- (no changes since v2) Changes in v2: - Remove the function from zimage.c also arch/x86/include/asm/u-boot-x86.h | 2 -- arch/x86/lib/zimage.c | 10 ---------- 2 files changed, 12 deletions(-) diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index bd3f44014c..d732661f6d 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -83,8 +83,6 @@ int default_print_cpuinfo(void); /* Set up a UART which can be used with printch(), printhex8(), etc. */ int setup_internal_uart(int enable); -void setup_pcat_compatibility(void); - void isa_unmap_rom(u32 addr); u32 isa_map_rom(u32 bus_addr, int size); diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 64d14e8911..d2b6002008 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -304,13 +304,6 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, return 0; } -void setup_pcat_compatibility(void) - __attribute__((weak, alias("__setup_pcat_compatibility"))); - -void __setup_pcat_compatibility(void) -{ -} - int do_zboot(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { struct boot_params *base_ptr; @@ -323,9 +316,6 @@ int do_zboot(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) disable_interrupts(); - /* Setup board for maximum PC/AT Compatibility */ - setup_pcat_compatibility(); - if (argc >= 2) { /* argv[1] holds the address of the bzImage */ s = argv[1]; From patchwork Fri Jul 17 03:22:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1330698 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; 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[73.14.175.90]) by smtp.gmail.com with ESMTPSA id 28sm3790693ilv.17.2020.07.16.20.22.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2020 20:22:56 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Wolfgang Wallner , Bin Meng , Andy Shevchenko , Simon Glass Subject: [PATCH v3 08/10] x86: acpi: Correct the version of the MADT Date: Thu, 16 Jul 2020 21:22:37 -0600 Message-Id: <20200717032239.197695-7-sjg@chromium.org> X-Mailer: git-send-email 2.28.0.rc0.105.gf9edc3c819-goog In-Reply-To: <20200717032239.197695-1-sjg@chromium.org> References: <20200717032239.197695-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Currently U-Boot implements version 2 but reports version 4. Correct it. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Reviewed-by: Wolfgang Wallner --- (no changes since v2) Changes in v2: - Use ACPI_MADT_REV_ACPI_3_0 instead of the open-coded value arch/x86/lib/acpi_table.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index d2bc3386eb..3a93fedfc3 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -155,7 +155,7 @@ static void acpi_create_madt(struct acpi_madt *madt) /* Fill out header fields */ acpi_fill_header(header, "APIC"); header->length = sizeof(struct acpi_madt); - header->revision = 4; + header->revision = ACPI_MADT_REV_ACPI_3_0; madt->lapic_addr = LAPIC_DEFAULT_BASE; madt->flags = ACPI_MADT_PCAT_COMPAT; From patchwork Fri Jul 17 03:22:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1330704 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=GRffPIcz; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B7GhP1JBZz9sRN for ; Fri, 17 Jul 2020 13:24:53 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id DC5FA81EF5; Fri, 17 Jul 2020 05:23:29 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="GRffPIcz"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 903D981C2A; Fri, 17 Jul 2020 05:23:05 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-io1-xd44.google.com (mail-io1-xd44.google.com [IPv6:2607:f8b0:4864:20::d44]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 5FF7C81C00 for ; Fri, 17 Jul 2020 05:22:59 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-io1-xd44.google.com with SMTP id l17so8928009iok.7 for ; Thu, 16 Jul 2020 20:22:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KB/GAWNb6z4lsXfOpFSoOayRkbEMmREjYxwBXD7tv5w=; b=GRffPIczhWtbwOcyP8tw1uG8e5MDSGpArYp2drZquq1oSOWqnPn5hdY41UGuS+Fl3R 7D736cxDdhDa6CO6v/OjSqu16xdi20MojHNwuhQkL1SKMV8msaLg11m6tHdLuACn09uy KyjdIEj2ykzQkrz3NLNBJ5welupqaLGEH2M1U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KB/GAWNb6z4lsXfOpFSoOayRkbEMmREjYxwBXD7tv5w=; b=nJniznwplV64EaAZVAXBo35W7mdtcV/xKiroTd/5vJvZTJb4qeqvDZJU7kDmwkc1Pt +f7II32jagKhoSrVe0HbhxG6gtVf3PnxRNEuGThiLx07Qtb35XD/ukOY+xZ55CwJ729I sicYrTf7rnL1SiK83z5fpLmw0u4CitvQH9nWxO07zQ+xE5WvmQh7PDzOgXcA59OBGlff L6ZMvdEhn0+JQH5wTD0obr9AxmCGBDmUhUHjUrHAVsjRbNnn5t/8JyGxWx0FprpcpXOa Yim5kmcG6mcVhKsxxCs3RW0DHjlxNYhaWWh25WouEl4O9EXvPrRl7s2bVrFQAL8nzmZC oqwA== X-Gm-Message-State: AOAM531iWCxMK5GliksJcX7w2hcr82UXt7JlED42rywwm/1HHNVBkcI7 k8jKBlv4JGOf+DMu+1X+i0YrmWuhsxAIVw== X-Google-Smtp-Source: ABdhPJxgLQsr6sj6jQlNrvKZHBf01Ys7+LImwuS+hJAkumg4v96uJfhIyS3CUEyh9hnTEPLqX4cGNQ== X-Received: by 2002:a05:6602:1c7:: with SMTP id w7mr7414031iot.185.1594956177931; Thu, 16 Jul 2020 20:22:57 -0700 (PDT) Received: from localhost.localdomain (c-73-14-175-90.hsd1.co.comcast.net. [73.14.175.90]) by smtp.gmail.com with ESMTPSA id 28sm3790693ilv.17.2020.07.16.20.22.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2020 20:22:57 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Wolfgang Wallner , Bin Meng , Andy Shevchenko , Simon Glass Subject: [PATCH v3 09/10] x86: Rename board_final_cleanup() to board_final_init() Date: Thu, 16 Jul 2020 21:22:38 -0600 Message-Id: <20200716212232.v3.9.I2762a08266cb540453f944c69ce0031ad0fe7c05@changeid> X-Mailer: git-send-email 2.28.0.rc0.105.gf9edc3c819-goog In-Reply-To: <20200717032239.197695-1-sjg@chromium.org> References: <20200717032239.197695-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean This function sounds like something that is called when U-Boot is about to jump to Linux. In fact it is an init function. Rename it to reduce confusion. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Reviewed-by: Wolfgang Wallner --- (no changes since v1) arch/x86/cpu/coreboot/coreboot.c | 4 ++-- arch/x86/cpu/cpu.c | 8 ++++---- arch/x86/cpu/efi/app.c | 2 +- arch/x86/cpu/quark/quark.c | 2 +- arch/x86/lib/fsp/fsp_common.c | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index d44db1347b..22a93254a9 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -42,7 +42,7 @@ int print_cpuinfo(void) return default_print_cpuinfo(); } -static void board_final_cleanup(void) +static void board_final_init(void) { /* * Un-cache the ROM so the kernel has one @@ -80,7 +80,7 @@ int last_stage_init(void) if (CONFIG_IS_ENABLED(USB_KEYBOARD)) usb_init(); - board_final_cleanup(); + board_final_init(); return 0; } diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 9ef797b41b..98ed66e67d 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -179,10 +179,10 @@ void show_boot_progress(int val) #if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB) /* - * Implement a weak default function for boards that optionally - * need to clean up the system before jumping to the kernel. + * Implement a weak default function for boards that need to do some final init + * before the system is ready. */ -__weak void board_final_cleanup(void) +__weak void board_final_init(void) { } @@ -190,7 +190,7 @@ int last_stage_init(void) { struct acpi_fadt __maybe_unused *fadt; - board_final_cleanup(); + board_final_init(); if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { fadt = acpi_find_fadt(); diff --git a/arch/x86/cpu/efi/app.c b/arch/x86/cpu/efi/app.c index 10677ecbc2..f754489784 100644 --- a/arch/x86/cpu/efi/app.c +++ b/arch/x86/cpu/efi/app.c @@ -24,7 +24,7 @@ int print_cpuinfo(void) return default_print_cpuinfo(); } -void board_final_cleanup(void) +void board_final_init(void) { } diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index ddad02e375..30b4711b9a 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -363,7 +363,7 @@ int arch_misc_init(void) return 0; } -void board_final_cleanup(void) +void board_final_init(void) { struct quark_rcba *rcba; u32 base, val; diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 8e3082d4c8..ea52954725 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -47,7 +47,7 @@ int fsp_init_phase_pci(void) return status ? -EPERM : 0; } -void board_final_cleanup(void) +void board_final_init(void) { u32 status; From patchwork Fri Jul 17 03:22:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1330703 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=mqy92Syv; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B7GhB2vVdz9sSt for ; Fri, 17 Jul 2020 13:24:42 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 396E381D39; Fri, 17 Jul 2020 05:23:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="mqy92Syv"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 468C281C26; Fri, 17 Jul 2020 05:23:04 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-io1-xd44.google.com (mail-io1-xd44.google.com [IPv6:2607:f8b0:4864:20::d44]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4E60D81C18 for ; Fri, 17 Jul 2020 05:23:00 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-io1-xd44.google.com with SMTP id p205so8934854iod.8 for ; Thu, 16 Jul 2020 20:23:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6Ck2YiKmzcEd/P8QozPA0hyShUAD3FqqhQfNY/I4h80=; b=mqy92SyvoDNhsb2yeslpXxb3/pigIcQ2bOooWjWHzZq1wt8duYSmAsF7ztsXObJRAN sWiltmDaDRv3Q1umoi8mkWeAqzckHv/8n8i+sGrZ4FgiRMaMi5ZdLO6K+956AMOHzqPa ed1phfmI8tau37oKBEfsTakE83CPsCg2r0z/Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6Ck2YiKmzcEd/P8QozPA0hyShUAD3FqqhQfNY/I4h80=; b=cawofPNXL+T74Kld96+Arg/Uzvjmifr3jxztrNB0b1l2tMO8xQjR1HWwwBG4CWIWiV Lf3IGcXt8t+BWqCqAyPoEnsFUg3sTPS+DLvX31xSfEz3utPOxU1eTpJWbEwmI7sjpPjT 3HJMmokDWFmlXj37kXWvE6KVHLVWdKfu/nmSeyAidKoPozXt8BtxDWvib5DvUpJnwhQl iwDtA+uvYARSrAUwF8cz13txlKVPqSAiwqrBwVV9DEJ0NARlxYcJl7PadfqUNZsyquAd z+61Io3771vjUfpnG5P9m63GTFyBqpoJ3mU7+mWkj2nJ+5vR1wTzaHShOSN0P+0NlOtO BHsg== X-Gm-Message-State: AOAM530h3n21XFAEfm7lMwDhuxd+S1HI7QhzP9dVa3F+CIl0pooGiFPL /FtA0iBqv8S305aZxkQcrk+toJ27u89OJQ== X-Google-Smtp-Source: ABdhPJyXEc5/cvl5yHQMFjlkrrCrggL/4Rfc7411mfnL3CfMQcI1RUtPtOfVkPyM6JSH15guy1XpXA== X-Received: by 2002:a05:6e02:48e:: with SMTP id b14mr7474514ils.143.1594956178796; Thu, 16 Jul 2020 20:22:58 -0700 (PDT) Received: from localhost.localdomain (c-73-14-175-90.hsd1.co.comcast.net. [73.14.175.90]) by smtp.gmail.com with ESMTPSA id 28sm3790693ilv.17.2020.07.16.20.22.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2020 20:22:58 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Wolfgang Wallner , Bin Meng , Andy Shevchenko , Simon Glass Subject: [PATCH v3 10/10] acpi: Enable ACPI table generation by default on x86 Date: Thu, 16 Jul 2020 21:22:39 -0600 Message-Id: <20200716212232.v3.10.I4c0c2ab2332368225244b54e2762d8acd78b4982@changeid> X-Mailer: git-send-email 2.28.0.rc0.105.gf9edc3c819-goog In-Reply-To: <20200717032239.197695-1-sjg@chromium.org> References: <20200717032239.197695-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean This should ideally be used by all x86 boards in U-Boot. Enable it by default. If some boards don't use it, the cost is small. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v3: - Rebase to x86/master Changes in v2: - Don't enable this for qemu arch/Kconfig | 1 + drivers/core/Kconfig | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/Kconfig b/arch/Kconfig index a11f872938..9be02d1319 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -190,6 +190,7 @@ config X86 imply PCH imply RTC_MC146818 imply IRQ + imply ACPIGEN if !QEMU # Thing to enable for when SPL/TPL are enabled: SPL imply SPL_DM diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index a594899f37..00d1d80dc3 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -270,7 +270,7 @@ config DM_DEV_READ_INLINE config ACPIGEN bool "Support ACPI table generation in driver model" - default y if SANDBOX || GENERATE_ACPI_TABLE + default y if SANDBOX || (GENERATE_ACPI_TABLE && !QEMU) help This option enables generation of ACPI tables using driver-model devices. It adds a new operation struct to each driver, to support