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Thu, 16 Jul 2020 06:16:27 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E15DE42042; Thu, 16 Jul 2020 06:16:22 +0000 (GMT) Received: from localhost.localdomain.com (unknown [9.79.215.148]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 16 Jul 2020 06:16:22 +0000 (GMT) From: Balamuruhan S To: mpe@ellerman.id.au Subject: [PATCH v2 1/4] powerpc/sstep: support new VSX vector paired storage access instructions Date: Thu, 16 Jul 2020 11:45:55 +0530 Message-Id: <20200716061558.1532199-2-bala24@linux.ibm.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200716061558.1532199-1-bala24@linux.ibm.com> References: <20200716061558.1532199-1-bala24@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-15_12:2020-07-15, 2020-07-15 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=999 bulkscore=0 clxscore=1015 spamscore=0 adultscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=1 malwarescore=0 impostorscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2007160042 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ravi.bangoria@linux.ibm.com, jniethe5@gmail.com, Balamuruhan S , paulus@samba.org, sandipan@linux.ibm.com, naveen.n.rao@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" VSX Vector Paired instructions loads/stores an octword (32 bytes) from/to storage into two sequential VSRs. Add `analyse_instr()` support to these new instructions, * Load VSX Vector Paired (lxvp) * Load VSX Vector Paired Indexed (lxvpx) * Prefixed Load VSX Vector Paired (plxvp) * Store VSX Vector Paired (stxvp) * Store VSX Vector Paired Indexed (stxvpx) * Prefixed Store VSX Vector Paired (pstxvp) Signed-off-by: Balamuruhan S --- arch/powerpc/lib/sstep.c | 52 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c index 5abe98216dc2..1af8c1920b36 100644 --- a/arch/powerpc/lib/sstep.c +++ b/arch/powerpc/lib/sstep.c @@ -31,6 +31,10 @@ extern char system_call_common[]; #define XER_OV32 0x00080000U #define XER_CA32 0x00040000U +#ifdef CONFIG_VSX +#define VSX_REGISTER_XTP(rd) ((((rd) & 1) << 5) | ((rd) & 0xfe)) +#endif + #ifdef CONFIG_PPC_FPU /* * Functions in ldstfp.S @@ -2382,6 +2386,15 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, op->vsx_flags = VSX_SPLAT; break; + case 333: /* lxvpx */ + if (!cpu_has_feature(CPU_FTR_ARCH_31)) + return -1; + op->reg = VSX_REGISTER_XTP(rd); + op->type = MKOP(LOAD_VSX, 0, 32); + op->element_size = 32; + op->vsx_flags = VSX_CHECK_VEC; + break; + case 364: /* lxvwsx */ op->reg = rd | ((word & 1) << 5); op->type = MKOP(LOAD_VSX, 0, 4); @@ -2410,6 +2423,14 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, VSX_CHECK_VEC; break; } + case 461: /* stxvpx */ + if (!cpu_has_feature(CPU_FTR_ARCH_31)) + return -1; + op->reg = VSX_REGISTER_XTP(rd); + op->type = MKOP(STORE_VSX, 0, 32); + op->element_size = 32; + op->vsx_flags = VSX_CHECK_VEC; + break; case 524: /* lxsspx */ op->reg = rd | ((word & 1) << 5); op->type = MKOP(LOAD_VSX, 0, 4); @@ -2651,6 +2672,23 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, #endif #ifdef CONFIG_VSX + case 6: + if (!cpu_has_feature(CPU_FTR_ARCH_31)) + return -1; + op->ea = dqform_ea(word, regs); + op->reg = VSX_REGISTER_XTP(rd); + op->element_size = 32; + op->vsx_flags = VSX_CHECK_VEC; + switch (word & 0xf) { + case 0: /* lxvp */ + op->type = MKOP(LOAD_VSX, 0, 32); + break; + case 1: /* stxvp */ + op->type = MKOP(STORE_VSX, 0, 32); + break; + } + break; + case 61: /* stfdp, lxv, stxsd, stxssp, stxv */ switch (word & 7) { case 0: /* stfdp with LSB of DS field = 0 */ @@ -2715,6 +2753,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, } break; case 1: /* Prefixed instructions */ + if (!cpu_has_feature(CPU_FTR_ARCH_31)) + return -1; prefix_r = word & (1ul << 20); ra = (suffix >> 16) & 0x1f; op->update_reg = ra; @@ -2779,12 +2819,24 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, case 57: /* pld */ op->type = MKOP(LOAD, PREFIXED, 8); break; + case 58: /* plxvp */ + op->reg = VSX_REGISTER_XTP(rd); + op->type = MKOP(LOAD_VSX, PREFIXED, 32); + op->element_size = 32; + op->vsx_flags = VSX_CHECK_VEC; + break; case 60: /* stq */ op->type = MKOP(STORE, PREFIXED, 16); break; case 61: /* pstd */ op->type = MKOP(STORE, PREFIXED, 8); break; + case 62: /* pstxvp */ + op->reg = VSX_REGISTER_XTP(rd); + op->type = MKOP(STORE_VSX, PREFIXED, 32); + op->element_size = 32; + op->vsx_flags = VSX_CHECK_VEC; + break; } break; case 1: /* Type 01 Eight-Byte Register-to-Register */ From patchwork Thu Jul 16 06:15:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Balamuruhan S X-Patchwork-Id: 1330027 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B6kgG73K1z9sRK for ; Thu, 16 Jul 2020 16:22:02 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4B6kgG2gcVzDqg5 for ; Thu, 16 Jul 2020 16:22:02 +1000 (AEST) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; 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Thu, 16 Jul 2020 06:16:31 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5D40142042; Thu, 16 Jul 2020 06:16:27 +0000 (GMT) Received: from localhost.localdomain.com (unknown [9.79.215.148]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 16 Jul 2020 06:16:27 +0000 (GMT) From: Balamuruhan S To: mpe@ellerman.id.au Subject: [PATCH v2 2/4] powerpc/sstep: support emulation for vsx vector paired storage access instructions Date: Thu, 16 Jul 2020 11:45:56 +0530 Message-Id: <20200716061558.1532199-3-bala24@linux.ibm.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200716061558.1532199-1-bala24@linux.ibm.com> References: <20200716061558.1532199-1-bala24@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-15_12:2020-07-15, 2020-07-15 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 malwarescore=0 suspectscore=1 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2007160042 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ravi.bangoria@linux.ibm.com, jniethe5@gmail.com, Balamuruhan S , paulus@samba.org, sandipan@linux.ibm.com, naveen.n.rao@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" add emulate_step() changes to support vsx vector paired storage access instructions that provides octword operands loads/stores between storage and set of 2 Vector Scalar Registers (VSRs). Signed-off-by: Balamuruhan S --- arch/powerpc/include/asm/sstep.h | 2 +- arch/powerpc/lib/sstep.c | 58 +++++++++++++++++++++++++++----- 2 files changed, 50 insertions(+), 10 deletions(-) diff --git a/arch/powerpc/include/asm/sstep.h b/arch/powerpc/include/asm/sstep.h index 3b01c69a44aa..a6c0b299bcc9 100644 --- a/arch/powerpc/include/asm/sstep.h +++ b/arch/powerpc/include/asm/sstep.h @@ -126,7 +126,7 @@ union vsx_reg { unsigned long d[2]; float fp[4]; double dp[2]; - __vector128 v; + __vector128 v[2]; }; /* diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c index 1af8c1920b36..010ce81aeffb 100644 --- a/arch/powerpc/lib/sstep.c +++ b/arch/powerpc/lib/sstep.c @@ -279,6 +279,19 @@ static nokprobe_inline void do_byte_reverse(void *ptr, int nb) up[1] = tmp; break; } + case 32: { + unsigned long *up = (unsigned long *)ptr; + unsigned long tmp; + + tmp = byterev_8(up[0]); + up[0] = byterev_8(up[3]); + up[3] = tmp; + tmp = byterev_8(up[2]); + up[2] = byterev_8(up[1]); + up[1] = tmp; + break; + } + #endif default: WARN_ON_ONCE(1); @@ -709,6 +722,8 @@ void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg, reg->d[0] = reg->d[1] = 0; switch (op->element_size) { + case 32: + /* [p]lxvp[x] or [p]stxvp[x] */ case 16: /* whole vector; lxv[x] or lxvl[l] */ if (size == 0) @@ -717,7 +732,7 @@ void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg, if (IS_LE && (op->vsx_flags & VSX_LDLEFT)) rev = !rev; if (rev) - do_byte_reverse(reg, 16); + do_byte_reverse(reg, size); break; case 8: /* scalar loads, lxvd2x, lxvdsx */ @@ -793,6 +808,22 @@ void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg, size = GETSIZE(op->type); switch (op->element_size) { + case 32: + /* [p]lxvp[x] or [p]stxvp[x] */ + if (size == 0) + break; + if (IS_LE && (op->vsx_flags & VSX_LDLEFT)) + rev = !rev; + if (rev) { + /* reverse 32 bytes */ + buf.d[0] = byterev_8(reg->d[3]); + buf.d[1] = byterev_8(reg->d[2]); + buf.d[2] = byterev_8(reg->d[1]); + buf.d[3] = byterev_8(reg->d[0]); + reg = &buf; + } + memcpy(mem, reg, size); + break; case 16: /* stxv, stxvx, stxvl, stxvll */ if (size == 0) @@ -861,28 +892,33 @@ static nokprobe_inline int do_vsx_load(struct instruction_op *op, bool cross_endian) { int reg = op->reg; - u8 mem[16]; + int i, nr_vsx_regs; + u8 mem[32]; union vsx_reg buf; int size = GETSIZE(op->type); if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs)) return -EFAULT; + nr_vsx_regs = size / sizeof(__vector128); emulate_vsx_load(op, &buf, mem, cross_endian); preempt_disable(); if (reg < 32) { /* FP regs + extensions */ if (regs->msr & MSR_FP) { - load_vsrn(reg, &buf); + for (i = 0; i < nr_vsx_regs; i++) + load_vsrn(reg + i, &buf.v[i]); } else { current->thread.fp_state.fpr[reg][0] = buf.d[0]; current->thread.fp_state.fpr[reg][1] = buf.d[1]; } } else { if (regs->msr & MSR_VEC) - load_vsrn(reg, &buf); + for (i = 0; i < nr_vsx_regs; i++) + load_vsrn(reg + i, &buf.v[i]); + else - current->thread.vr_state.vr[reg - 32] = buf.v; + current->thread.vr_state.vr[reg - 32] = buf.v[0]; } preempt_enable(); return 0; @@ -893,27 +929,31 @@ static nokprobe_inline int do_vsx_store(struct instruction_op *op, bool cross_endian) { int reg = op->reg; - u8 mem[16]; + int i, nr_vsx_regs; + u8 mem[32]; union vsx_reg buf; int size = GETSIZE(op->type); if (!address_ok(regs, ea, size)) return -EFAULT; + nr_vsx_regs = size / sizeof(__vector128); preempt_disable(); if (reg < 32) { /* FP regs + extensions */ if (regs->msr & MSR_FP) { - store_vsrn(reg, &buf); + for (i = 0; i < nr_vsx_regs; i++) + store_vsrn(reg + i, &buf.v[i]); } else { buf.d[0] = current->thread.fp_state.fpr[reg][0]; buf.d[1] = current->thread.fp_state.fpr[reg][1]; } } else { if (regs->msr & MSR_VEC) - store_vsrn(reg, &buf); + for (i = 0; i < nr_vsx_regs; i++) + store_vsrn(reg + i, &buf.v[i]); else - buf.v = current->thread.vr_state.vr[reg - 32]; + buf.v[0] = current->thread.vr_state.vr[reg - 32]; } preempt_enable(); emulate_vsx_store(op, &buf, mem, cross_endian); From patchwork Thu Jul 16 06:15:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Balamuruhan S X-Patchwork-Id: 1330028 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B6kj74zm0z9sQt for ; Thu, 16 Jul 2020 16:23:39 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4B6kj71PJyzDqXT for ; Thu, 16 Jul 2020 16:23:39 +1000 (AEST) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; 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Thu, 16 Jul 2020 06:16:31 +0000 (GMT) Received: from localhost.localdomain.com (unknown [9.79.215.148]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 16 Jul 2020 06:16:31 +0000 (GMT) From: Balamuruhan S To: mpe@ellerman.id.au Subject: [PATCH v2 3/4] powerpc ppc-opcode: add opcodes for vsx vector paired instructions Date: Thu, 16 Jul 2020 11:45:57 +0530 Message-Id: <20200716061558.1532199-4-bala24@linux.ibm.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200716061558.1532199-1-bala24@linux.ibm.com> References: <20200716061558.1532199-1-bala24@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-15_12:2020-07-15, 2020-07-15 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=890 bulkscore=0 clxscore=1015 spamscore=0 adultscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=1 malwarescore=0 impostorscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2007160042 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ravi.bangoria@linux.ibm.com, jniethe5@gmail.com, Balamuruhan S , paulus@samba.org, sandipan@linux.ibm.com, naveen.n.rao@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" add instruction opcodes for new vsx vector paired instructions, * Load VSX Vector Paired (lxvp) * Load VSX Vector Paired Indexed (lxvpx) * Store VSX Vector Paired (stxvp) * Store VSX Vector Paired Indexed (stxvpx) Signed-off-by: Balamuruhan S --- arch/powerpc/include/asm/ppc-opcode.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index 777d5056a71c..f7ffbe11624e 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -210,6 +210,10 @@ #define PPC_INST_ISEL 0x7c00001e #define PPC_INST_ISEL_MASK 0xfc00003e #define PPC_INST_LDARX 0x7c0000a8 +#define PPC_INST_LXVP 0x18000000 +#define PPC_INST_LXVPX 0x7c00029a +#define PPC_INST_STXVP 0x18000001 +#define PPC_INST_STXVPX 0x7c00039a #define PPC_INST_STDCX 0x7c0001ad #define PPC_INST_LQARX 0x7c000228 #define PPC_INST_STQCX 0x7c00016d From patchwork Thu Jul 16 06:15:58 2020 Content-Type: text/plain; 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Thu, 16 Jul 2020 06:16:36 +0000 (GMT) From: Balamuruhan S To: mpe@ellerman.id.au Subject: [PATCH v2 4/4] powerpc sstep: add testcases for vsx load/store instructions Date: Thu, 16 Jul 2020 11:45:58 +0530 Message-Id: <20200716061558.1532199-5-bala24@linux.ibm.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200716061558.1532199-1-bala24@linux.ibm.com> References: <20200716061558.1532199-1-bala24@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-15_12:2020-07-15, 2020-07-15 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 spamscore=0 phishscore=0 adultscore=0 suspectscore=1 mlxlogscore=920 clxscore=1015 lowpriorityscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2007160042 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ravi.bangoria@linux.ibm.com, jniethe5@gmail.com, Balamuruhan S , paulus@samba.org, sandipan@linux.ibm.com, naveen.n.rao@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" add testcases for vsx load/store vector paired instructions, * Load VSX Vector Paired (lxvp) * Load VSX Vector Paired Indexed (lxvpx) * Prefixed Load VSX Vector Paired (plxvp) * Store VSX Vector Paired (stxvp) * Store VSX Vector Paired Indexed (stxvpx) * Prefixed Store VSX Vector Paired (pstxvp) Signed-off-by: Balamuruhan S --- arch/powerpc/include/asm/ppc-opcode.h | 7 + arch/powerpc/lib/test_emulate_step.c | 273 ++++++++++++++++++++++++++ 2 files changed, 280 insertions(+) diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index f7ffbe11624e..aa688d13981a 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -389,6 +389,10 @@ #define PPC_INST_VCMPEQUD 0x100000c7 #define PPC_INST_VCMPEQUB 0x10000006 +/* Prefixes */ +#define PPC_PREFIX_MLS 0x06000000 +#define PPC_PREFIX_8LS 0x04000000 + /* macros to insert fields into opcodes */ #define ___PPC_RA(a) (((a) & 0x1f) << 16) #define ___PPC_RB(b) (((b) & 0x1f) << 11) @@ -420,6 +424,9 @@ #define __PPC_CT(t) (((t) & 0x0f) << 21) #define __PPC_SPR(r) ((((r) & 0x1f) << 16) | ((((r) >> 5) & 0x1f) << 11)) #define __PPC_RC21 (0x1 << 10) +#define __PPC_PRFX_R(r) (((r) & 0x1) << 20) +#define __PPC_TP(tp) (((tp) & 0xf) << 22) +#define __PPC_TX(tx) (((tx) & 0x1) << 21) /* * Both low and high 16 bits are added as SIGNED additions, so if low 16 bits diff --git a/arch/powerpc/lib/test_emulate_step.c b/arch/powerpc/lib/test_emulate_step.c index 46af80279ebc..98ecbc66bef8 100644 --- a/arch/powerpc/lib/test_emulate_step.c +++ b/arch/powerpc/lib/test_emulate_step.c @@ -14,7 +14,13 @@ #include #define IMM_L(i) ((uintptr_t)(i) & 0xffff) +#define IMM_H(i) (((uintptr_t)(i) >> 16) & 0x3ffff) #define IMM_DS(i) ((uintptr_t)(i) & 0xfffc) +#define IMM_DQ(i) (((uintptr_t)(i) & 0xfff) << 4) + +#define PLXVP_EX_OP 0xe8000000 +#define PSTXVP_EX_OP 0xf8000000 + /* * Defined with TEST_ prefix so it does not conflict with other @@ -47,6 +53,21 @@ ___PPC_RA(a) | ___PPC_RB(b)) #define TEST_LXVD2X(s, a, b) ppc_inst(PPC_INST_LXVD2X | VSX_XX1((s), R##a, R##b)) #define TEST_STXVD2X(s, a, b) ppc_inst(PPC_INST_STXVD2X | VSX_XX1((s), R##a, R##b)) +#define TEST_LXVP(tp, tx, a, i) \ + (PPC_INST_LXVP | __PPC_TP(tp) | __PPC_TX(tx) | ___PPC_RA(a) | IMM_DQ(i)) +#define TEST_STXVP(sp, sx, a, i) \ + (PPC_INST_STXVP | __PPC_TP(sp) | __PPC_TX(sx) | ___PPC_RA(a) | IMM_DQ(i) | 0x1) +#define TEST_LXVPX(tp, tx, a, b) \ + (PPC_INST_LXVPX | __PPC_TP(tp) | __PPC_TX(tx) | ___PPC_RA(a) | ___PPC_RB(b)) +#define TEST_STXVPX(sp, sx, a, b) \ + (PPC_INST_STXVPX | __PPC_TP(sp) | __PPC_TX(sx) | ___PPC_RA(a) | ___PPC_RB(b)) +#define TEST_PLXVP(a, i, pr, tp, tx) \ + ((PPC_PREFIX_8LS | __PPC_PRFX_R(pr) | IMM_H(i)) << 32 | \ + (PLXVP_EX_OP | __PPC_TP(tp) | __PPC_TX(tx) | ___PPC_RA(a) | IMM_L(i))) +#define TEST_PSTXVP(a, i, pr, sp, sx) \ + ((PPC_PREFIX_8LS | __PPC_PRFX_R(pr) | IMM_H(i)) << 32 | \ + (PSTXVP_EX_OP | __PPC_TP(sp) | __PPC_TX(sx) | ___PPC_RA(a) | IMM_L(i))) + #define TEST_ADD(t, a, b) ppc_inst(PPC_INST_ADD | ___PPC_RT(t) | \ ___PPC_RA(a) | ___PPC_RB(b)) #define TEST_ADD_DOT(t, a, b) ppc_inst(PPC_INST_ADD | ___PPC_RT(t) | \ @@ -444,6 +465,255 @@ static void __init test_lxvd2x_stxvd2x(void) } #endif /* CONFIG_VSX */ +#ifdef CONFIG_VSX +static void __init test_lxvp_stxvp(void) +{ + struct pt_regs regs; + union { + vector128 a[2]; + u32 b[8]; + } c; + u32 cached_b[8]; + int stepped = -1; + + init_pt_regs(®s); + + /*** lxvp ***/ + + cached_b[0] = c.b[0] = 18233; + cached_b[1] = c.b[1] = 34863571; + cached_b[2] = c.b[2] = 834; + cached_b[3] = c.b[3] = 6138911; + cached_b[4] = c.b[4] = 1234; + cached_b[5] = c.b[5] = 5678; + cached_b[6] = c.b[6] = 91011; + cached_b[7] = c.b[7] = 121314; + + regs.gpr[4] = (unsigned long)&c.a; + + /* + * lxvp XTp,DQ(RA) + * XTp = 32×TX + 2×Tp + * let TX=1 Tp=1 RA=4 DQ=0 + */ + stepped = emulate_step(®s, ppc_inst(TEST_LXVP(1, 1, 4, 0))); + + if (stepped == 1 && cpu_has_feature(CPU_FTR_VSX)) { + show_result("lxvp", "PASS"); + } else { + if (!cpu_has_feature(CPU_FTR_VSX)) + show_result("lxvp", "PASS (!CPU_FTR_VSX)"); + else + show_result("lxvp", "FAIL"); + } + + /*** stxvp ***/ + + c.b[0] = 21379463; + c.b[1] = 87; + c.b[2] = 374234; + c.b[3] = 4; + c.b[4] = 90; + c.b[5] = 122; + c.b[6] = 555; + c.b[7] = 32144; + + /* + * stxvp XSp,DQ(RA) + * XSp = 32×SX + 2×Sp + * let SX=1 Sp=1 RA=4 DQ=0 + */ + stepped = emulate_step(®s, ppc_inst(TEST_STXVP(1, 1, 4, 0))); + + if (stepped == 1 && cached_b[0] == c.b[0] && cached_b[1] == c.b[1] && + cached_b[2] == c.b[2] && cached_b[3] == c.b[3] && + cached_b[4] == c.b[4] && cached_b[5] == c.b[5] && + cached_b[6] == c.b[6] && cached_b[7] == c.b[7] && + cpu_has_feature(CPU_FTR_VSX)) { + show_result("stxvp", "PASS"); + } else { + if (!cpu_has_feature(CPU_FTR_VSX)) + show_result("stxvp", "PASS (!CPU_FTR_VSX)"); + else + show_result("stxvp", "FAIL"); + } +} +#else +static void __init test_lxvp_stxvp(void) +{ + show_result("lxvp", "SKIP (CONFIG_VSX is not set)"); + show_result("stxvp", "SKIP (CONFIG_VSX is not set)"); +} +#endif /* CONFIG_VSX */ + +#ifdef CONFIG_VSX +static void __init test_lxvpx_stxvpx(void) +{ + struct pt_regs regs; + union { + vector128 a[2]; + u32 b[8]; + } c; + u32 cached_b[8]; + int stepped = -1; + + init_pt_regs(®s); + + /*** lxvpx ***/ + + cached_b[0] = c.b[0] = 18233; + cached_b[1] = c.b[1] = 34863571; + cached_b[2] = c.b[2] = 834; + cached_b[3] = c.b[3] = 6138911; + cached_b[4] = c.b[4] = 1234; + cached_b[5] = c.b[5] = 5678; + cached_b[6] = c.b[6] = 91011; + cached_b[7] = c.b[7] = 121314; + + regs.gpr[3] = (unsigned long)&c.a; + regs.gpr[4] = 0; + + /* + * lxvpx XTp,RA,RB + * XTp = 32×TX + 2×Tp + * let TX=1 Tp=1 RA=3 RB=4 + */ + stepped = emulate_step(®s, ppc_inst(TEST_LXVPX(1, 1, 3, 4))); + + if (stepped == 1 && cpu_has_feature(CPU_FTR_VSX)) { + show_result("lxvpx", "PASS"); + } else { + if (!cpu_has_feature(CPU_FTR_VSX)) + show_result("lxvpx", "PASS (!CPU_FTR_VSX)"); + else + show_result("lxvpx", "FAIL"); + } + + /*** stxvpx ***/ + + c.b[0] = 21379463; + c.b[1] = 87; + c.b[2] = 374234; + c.b[3] = 4; + c.b[4] = 90; + c.b[5] = 122; + c.b[6] = 555; + c.b[7] = 32144; + + /* + * stxvpx XSp,RA,RB + * XSp = 32×SX + 2×Sp + * let SX=1 Sp=1 RA=3 RB=4 + */ + stepped = emulate_step(®s, ppc_inst(TEST_STXVPX(1, 1, 3, 4))); + + if (stepped == 1 && cached_b[0] == c.b[0] && cached_b[1] == c.b[1] && + cached_b[2] == c.b[2] && cached_b[3] == c.b[3] && + cached_b[4] == c.b[4] && cached_b[5] == c.b[5] && + cached_b[6] == c.b[6] && cached_b[7] == c.b[7] && + cpu_has_feature(CPU_FTR_VSX)) { + show_result("stxvpx", "PASS"); + } else { + if (!cpu_has_feature(CPU_FTR_VSX)) + show_result("stxvpx", "PASS (!CPU_FTR_VSX)"); + else + show_result("stxvpx", "FAIL"); + } +} +#else +static void __init test_lxvpx_stxvpx(void) +{ + show_result("lxvpx", "SKIP (CONFIG_VSX is not set)"); + show_result("stxvpx", "SKIP (CONFIG_VSX is not set)"); +} +#endif /* CONFIG_VSX */ + +#ifdef CONFIG_VSX +static void __init test_plxvp_pstxvp(void) +{ + struct ppc_inst instr; + struct pt_regs regs; + union { + vector128 a[2]; + u32 b[8]; + } c; + u32 cached_b[8]; + int stepped = -1; + + /* + * plxvp XTp,D(RA),R + * XSp = 32×SX + 2×Sp + * let RA=3 R=0 D=d0||d1=0 R=0 Sp=1 SX=1 + */ + instr = ppc_inst_prefix(TEST_PLXVP(3, 0, 0, 1, 1) >> 32, + TEST_PLXVP(3, 0, 0, 1, 1) & 0xffffffff); + + /*** plxvpx ***/ + + cached_b[0] = c.b[0] = 18233; + cached_b[1] = c.b[1] = 34863571; + cached_b[2] = c.b[2] = 834; + cached_b[3] = c.b[3] = 6138911; + cached_b[4] = c.b[4] = 1234; + cached_b[5] = c.b[5] = 5678; + cached_b[6] = c.b[6] = 91011; + cached_b[7] = c.b[7] = 121314; + + init_pt_regs(®s); + regs.gpr[3] = (unsigned long)&c.a; + + stepped = emulate_step(®s, instr); + if (stepped == 1 && cpu_has_feature(CPU_FTR_VSX)) { + show_result("plxvpx", "PASS"); + } else { + if (!cpu_has_feature(CPU_FTR_VSX)) + show_result("plxvpx", "PASS (!CPU_FTR_VSX)"); + else + show_result("plxvpx", "FAIL"); + } + + /*** pstxvpx ***/ + + c.b[0] = 21379463; + c.b[1] = 87; + c.b[2] = 374234; + c.b[3] = 4; + c.b[4] = 90; + c.b[5] = 122; + c.b[6] = 555; + c.b[7] = 32144; + + /* + * pstxvpx XTp,D(RA),R + * XSp = 32×SX + 2×Sp + * let RA=3 D=d0||d1=0 R=0 Sp=1 SX=1 + */ + instr = ppc_inst_prefix(TEST_PSTXVP(3, 0, 0, 1, 1) >> 32, + TEST_PSTXVP(3, 0, 0, 1, 1) & 0xffffffff); + + stepped = emulate_step(®s, instr); + + if (stepped == 1 && cached_b[0] == c.b[0] && cached_b[1] == c.b[1] && + cached_b[2] == c.b[2] && cached_b[3] == c.b[3] && + cached_b[4] == c.b[4] && cached_b[5] == c.b[5] && + cached_b[6] == c.b[6] && cached_b[7] == c.b[7] && + cpu_has_feature(CPU_FTR_VSX)) { + show_result("pstxvpx", "PASS"); + } else { + if (!cpu_has_feature(CPU_FTR_VSX)) + show_result("pstxvpx", "PASS (!CPU_FTR_VSX)"); + else + show_result("pstxvpx", "FAIL"); + } +} +#else +static void __init test_plxvp_pstxvp(void) +{ + show_result("plxvpx", "SKIP (CONFIG_VSX is not set)"); + show_result("pstxvpx", "SKIP (CONFIG_VSX is not set)"); +} +#endif /* CONFIG_VSX */ + static void __init run_tests_load_store(void) { test_ld(); @@ -455,6 +725,9 @@ static void __init run_tests_load_store(void) test_lfdx_stfdx(); test_lvx_stvx(); test_lxvd2x_stxvd2x(); + test_lxvp_stxvp(); + test_lxvpx_stxvpx(); + test_plxvp_pstxvp(); } struct compute_test {