From patchwork Sun Jul 12 10:06:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 1327474 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=HqmEWCRm; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4B4Mrc1t14z9sR4 for ; Sun, 12 Jul 2020 20:06:56 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728690AbgGLKGz (ORCPT ); Sun, 12 Jul 2020 06:06:55 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:5760 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728675AbgGLKGy (ORCPT ); Sun, 12 Jul 2020 06:06:54 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 12 Jul 2020 03:05:03 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sun, 12 Jul 2020 03:06:54 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sun, 12 Jul 2020 03:06:54 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 12 Jul 2020 10:06:53 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 12 Jul 2020 10:06:54 +0000 Received: from moonraker.nvidia.com (Not Verified[10.26.75.246]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Sun, 12 Jul 2020 03:06:53 -0700 From: Jon Hunter To: Thierry Reding CC: "Rafael J . Wysocki" , Viresh Kumar , , , Jon Hunter Subject: [PATCH 1/2] cpufreq: tegra186: Fix initial frequency Date: Sun, 12 Jul 2020 11:06:44 +0100 Message-ID: <20200712100645.13927-1-jonathanh@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594548303; bh=efSfznaHRVOLPOniFGgvlT8Fr3h/o5mTkr8QrJEVayo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=HqmEWCRmNF6QaGG4iBINeBvBO7pjoiu4upmffuxhYh9vCgKecx95JbhuArhBIQSB8 FUujT2hTtPVPoPsNShBlI/O4E3mHVljRHXmK70nMVDi0ivnBqlRweO2ZmqBZJHYDSQ gz78o2MpSpFgL8HsurGCd0PidH1tGzE9apZmDV/S3Kbf1ZRPiV9PJouXNs5qPI1wnA YmpLkBoNfhfRvQQ3krPn1ZCuNIi8S5OxhQs8gw7VAN8oMcnBFhSMGZiJw6wRK9/c15 K6BJybO3FSvhSoCraWu1qXJcz+LwWdFfAUb0S7Y48WlP/UCsfVwUBNBjbKN2v8+Xk1 vQGJp1NqfHpbA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Commit 6cc3d0e9a097 ("cpufreq: tegra186: add CPUFREQ_NEED_INITIAL_FREQ_CHECK flag") fixed CPUFREQ support for Tegra186 but as a consequence the following warnings are now seen on boot ... cpufreq: cpufreq_online: CPU0: Running at unlisted freq: 0 KHz cpufreq: cpufreq_online: CPU0: Unlisted initial frequency changed to: 2035200 KHz cpufreq: cpufreq_online: CPU1: Running at unlisted freq: 0 KHz cpufreq: cpufreq_online: CPU1: Unlisted initial frequency changed to: 2035200 KHz cpufreq: cpufreq_online: CPU2: Running at unlisted freq: 0 KHz cpufreq: cpufreq_online: CPU2: Unlisted initial frequency changed to: 2035200 KHz cpufreq: cpufreq_online: CPU3: Running at unlisted freq: 0 KHz cpufreq: cpufreq_online: CPU3: Unlisted initial frequency changed to: 2035200 KHz cpufreq: cpufreq_online: CPU4: Running at unlisted freq: 0 KHz cpufreq: cpufreq_online: CPU4: Unlisted initial frequency changed to: 2035200 KHz cpufreq: cpufreq_online: CPU5: Running at unlisted freq: 0 KHz cpufreq: cpufreq_online: CPU5: Unlisted initial frequency changed to: 2035200 KHz Although we could fix this by adding a 'get' operator for the Tegra186 CPUFREQ driver, there is really little point because the CPUFREQ on Tegra186 is set by writing a value stored in the frequency table to a register and we just need to set the initial frequency. So for Tegra186 the simplest way to fix this is read the register that sets the frequency for each CPU and set the initial frequency when initialising the CPUFREQ driver. Signed-off-by: Jon Hunter --- drivers/cpufreq/tegra186-cpufreq.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/cpufreq/tegra186-cpufreq.c b/drivers/cpufreq/tegra186-cpufreq.c index 3d2f143748ef..c44190ce3f03 100644 --- a/drivers/cpufreq/tegra186-cpufreq.c +++ b/drivers/cpufreq/tegra186-cpufreq.c @@ -59,6 +59,7 @@ static int tegra186_cpufreq_init(struct cpufreq_policy *policy) struct tegra186_cpufreq_cluster *cluster = &data->clusters[i]; const struct tegra186_cpufreq_cluster_info *info = cluster->info; + u32 edvd_val; int core; for (core = 0; core < ARRAY_SIZE(info->cpus); core++) { @@ -71,6 +72,13 @@ static int tegra186_cpufreq_init(struct cpufreq_policy *policy) policy->driver_data = data->regs + info->offset + EDVD_CORE_VOLT_FREQ(core); policy->freq_table = cluster->table; + + edvd_val = readl(policy->driver_data); + + for (i = 0; cluster->table[i].frequency != CPUFREQ_TABLE_END; i++) { + if (cluster->table[i].driver_data == edvd_val) + policy->cur = cluster->table[i].frequency; + } break; } From patchwork Sun Jul 12 10:06:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 1327475 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=BRI7EJNb; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4B4Mrk0Bf8z9s1x for ; Sun, 12 Jul 2020 20:07:02 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728354AbgGLKG6 (ORCPT ); Sun, 12 Jul 2020 06:06:58 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:6374 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727777AbgGLKG5 (ORCPT ); Sun, 12 Jul 2020 06:06:57 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 12 Jul 2020 03:06:01 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 12 Jul 2020 03:06:57 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 12 Jul 2020 03:06:57 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 12 Jul 2020 10:06:55 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 12 Jul 2020 10:06:55 +0000 Received: from moonraker.nvidia.com (Not Verified[10.26.75.246]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Sun, 12 Jul 2020 03:06:55 -0700 From: Jon Hunter To: Thierry Reding CC: "Rafael J . Wysocki" , Viresh Kumar , , , Jon Hunter Subject: [PATCH 2/2] cpufreq: tegra186: Simplify probe return path Date: Sun, 12 Jul 2020 11:06:45 +0100 Message-ID: <20200712100645.13927-2-jonathanh@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200712100645.13927-1-jonathanh@nvidia.com> References: <20200712100645.13927-1-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594548361; bh=nz3cJSjF3NMjq5LmbqTUriy0lkrKQK3j38oB5/xDGQU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=BRI7EJNbWMEaprvOwmA+ve/vgPKNWxdyeWYk921IJPDQTqaXCLiEEGqju8ls8fza8 uwBsUQEtQBEd6eufardF4yEE1vAOWvdTzYgpDYt+Vd2rM6TweEVVhMMdgQAUm4j4XZ 6QyDIc2nWnRyjXoKchlsKcyzT7FzzC1XaEeVrhur0fQ4yrSRi5BeDdTY97Esco0bWG qsjFWeNMScNu64vSO0nmFNYg9qlOSxJ3qWD5N4X1gay53iQM54W74nT7ahpaaKZRVA wWYw7+jrUokoXrUfb+B5/kWBI3a/jKqp318yW0IeNRcvSJ1uIEL708x160n1F+J6f1 RYliZWjay2bxQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org We always put the reference to BPMP device on exit of the Tegra186 CPUFREQ driver and so there is no need to have separate exit paths for success and failure. Therefore, simplify the probe return path in the Tegra186 CPUFREQ driver by combining the success and failure paths. Signed-off-by: Jon Hunter --- drivers/cpufreq/tegra186-cpufreq.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/cpufreq/tegra186-cpufreq.c b/drivers/cpufreq/tegra186-cpufreq.c index c44190ce3f03..bf8cab357277 100644 --- a/drivers/cpufreq/tegra186-cpufreq.c +++ b/drivers/cpufreq/tegra186-cpufreq.c @@ -231,15 +231,9 @@ static int tegra186_cpufreq_probe(struct platform_device *pdev) } } - tegra_bpmp_put(bpmp); - tegra186_cpufreq_driver.driver_data = data; err = cpufreq_register_driver(&tegra186_cpufreq_driver); - if (err) - return err; - - return 0; put_bpmp: tegra_bpmp_put(bpmp);