From patchwork Thu Jul 9 21:35:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 1326223 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=walle.cc header.i=@walle.cc header.a=rsa-sha256 header.s=mail2016061301 header.b=snagahQu; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4B2qH03YJlz9sRW for ; Fri, 10 Jul 2020 07:35:56 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726801AbgGIVft (ORCPT ); Thu, 9 Jul 2020 17:35:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726510AbgGIVfq (ORCPT ); Thu, 9 Jul 2020 17:35:46 -0400 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75206C08C5DC; Thu, 9 Jul 2020 14:35:44 -0700 (PDT) Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 5FD9F22FF5; Thu, 9 Jul 2020 23:35:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1594330538; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=84ne4nXHSEC8l7CIFcYailprO/l8iEq22QSMWXO6DMc=; b=snagahQubulHTf4XE317rVThdYFrKtcPeNuRSHwkNQ6sxYQ2FTzXWmyGhiXokFzCmCC3eW AJ6RvGloO4qYhspacPjLqOE4tVFZmwm9CgeqBFWV0CaKOHAyvxgtCFwljzwjwplSEHTSzm 8mG2OZxFa+edhzryX3NEh7k2JugG1rc= From: Michael Walle To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: "David S . Miller" , Jakub Kicinski , Andrew Lunn , Michael Walle , Vladimir Oltean , Alex Marginean , Claudiu Manoil , Heiko Thiery , Russell King - ARM Linux admin , Ioana Ciornei , Microchip Linux Driver Support Subject: [PATCH net-next v6 1/4] net: phy: add USXGMII link partner ability constants Date: Thu, 9 Jul 2020 23:35:23 +0200 Message-Id: <20200709213526.21972-2-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200709213526.21972-1-michael@walle.cc> References: <20200709213526.21972-1-michael@walle.cc> MIME-Version: 1.0 X-Spam: Yes Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The constants are taken from the USXGMII Singleport Copper Interface specification. The naming are based on the SGMII ones, but with an MDIO_ prefix. Signed-off-by: Michael Walle Reviewed-by: Russell King --- include/uapi/linux/mdio.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h index 4bcb41c71b8c..784723072578 100644 --- a/include/uapi/linux/mdio.h +++ b/include/uapi/linux/mdio.h @@ -324,4 +324,30 @@ static inline __u16 mdio_phy_id_c45(int prtad, int devad) return MDIO_PHY_ID_C45 | (prtad << 5) | devad; } +/* UsxgmiiChannelInfo[15:0] for USXGMII in-band auto-negotiation.*/ +#define MDIO_LPA_USXGMII_EEE_CLK_STP 0x0080 /* EEE clock stop supported */ +#define MDIO_LPA_USXGMII_EEE 0x0100 /* EEE supported */ +#define MDIO_LPA_USXGMII_SPD_MASK 0x0e00 /* USXGMII speed mask */ +#define MDIO_LPA_USXGMII_FULL_DUPLEX 0x1000 /* USXGMII full duplex */ +#define MDIO_LPA_USXGMII_DPX_SPD_MASK 0x1e00 /* USXGMII duplex and speed bits */ +#define MDIO_LPA_USXGMII_10 0x0000 /* 10Mbps */ +#define MDIO_LPA_USXGMII_10HALF 0x0000 /* 10Mbps half-duplex */ +#define MDIO_LPA_USXGMII_10FULL 0x1000 /* 10Mbps full-duplex */ +#define MDIO_LPA_USXGMII_100 0x0200 /* 100Mbps */ +#define MDIO_LPA_USXGMII_100HALF 0x0200 /* 100Mbps half-duplex */ +#define MDIO_LPA_USXGMII_100FULL 0x1200 /* 100Mbps full-duplex */ +#define MDIO_LPA_USXGMII_1000 0x0400 /* 1000Mbps */ +#define MDIO_LPA_USXGMII_1000HALF 0x0400 /* 1000Mbps half-duplex */ +#define MDIO_LPA_USXGMII_1000FULL 0x1400 /* 1000Mbps full-duplex */ +#define MDIO_LPA_USXGMII_10G 0x0600 /* 10Gbps */ +#define MDIO_LPA_USXGMII_10GHALF 0x0600 /* 10Gbps half-duplex */ +#define MDIO_LPA_USXGMII_10GFULL 0x1600 /* 10Gbps full-duplex */ +#define MDIO_LPA_USXGMII_2500 0x0800 /* 2500Mbps */ +#define MDIO_LPA_USXGMII_2500HALF 0x0800 /* 2500Mbps half-duplex */ +#define MDIO_LPA_USXGMII_2500FULL 0x1800 /* 2500Mbps full-duplex */ +#define MDIO_LPA_USXGMII_5000 0x0a00 /* 5000Mbps */ +#define MDIO_LPA_USXGMII_5000HALF 0x0a00 /* 5000Mbps half-duplex */ +#define MDIO_LPA_USXGMII_5000FULL 0x1a00 /* 5000Mbps full-duplex */ +#define MDIO_LPA_USXGMII_LINK 0x8000 /* PHY link with copper-side partner */ + #endif /* _UAPI__LINUX_MDIO_H__ */ From patchwork Thu Jul 9 21:35:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 1326225 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=walle.cc header.i=@walle.cc header.a=rsa-sha256 header.s=mail2016061301 header.b=GPJe2eNH; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4B2qHB4rkWz9sSd for ; Fri, 10 Jul 2020 07:36:06 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726875AbgGIVgD (ORCPT ); Thu, 9 Jul 2020 17:36:03 -0400 Received: from ssl.serverraum.org ([176.9.125.105]:43105 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726196AbgGIVfo (ORCPT ); Thu, 9 Jul 2020 17:35:44 -0400 Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id E849B2304C; Thu, 9 Jul 2020 23:35:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1594330541; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iVptw4aoJ+3oNrDHOoxXfWtJ9FG20ce1D/+p/lagA6g=; b=GPJe2eNH3iIytVPN3zsGJmjFypI2Pq4KommhcMhZNGNuzDnjQ5Y3v12yzgLxZj9zlL8nsj pEFWj8GswPFf8q5jEb2Yluq/cSFSxFHmDQoYdqP0okHyHvfRSpPuL5RfHaTKJIbnTJMF1M rehNXYm7leJTC/dKedgJMhy9DUsbrYM= From: Michael Walle To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: "David S . Miller" , Jakub Kicinski , Andrew Lunn , Michael Walle , Vladimir Oltean , Alex Marginean , Claudiu Manoil , Heiko Thiery , Russell King - ARM Linux admin , Ioana Ciornei , Microchip Linux Driver Support Subject: [PATCH net-next v6 2/4] net: dsa: felix: (re)use already existing constants Date: Thu, 9 Jul 2020 23:35:24 +0200 Message-Id: <20200709213526.21972-3-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200709213526.21972-1-michael@walle.cc> References: <20200709213526.21972-1-michael@walle.cc> MIME-Version: 1.0 X-Spam: Yes Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Now that there are USXGMII constants available, drop the old definitions and reuse the generic ones. Signed-off-by: Michael Walle Tested-by: Vladimir Oltean --- drivers/net/dsa/ocelot/felix_vsc9959.c | 45 +++++++------------------- 1 file changed, 12 insertions(+), 33 deletions(-) diff --git a/drivers/net/dsa/ocelot/felix_vsc9959.c b/drivers/net/dsa/ocelot/felix_vsc9959.c index 19614537b1ba..a3ddb1394540 100644 --- a/drivers/net/dsa/ocelot/felix_vsc9959.c +++ b/drivers/net/dsa/ocelot/felix_vsc9959.c @@ -10,35 +10,15 @@ #include #include #include +#include #include #include "felix.h" #define VSC9959_VCAP_IS2_CNT 1024 #define VSC9959_VCAP_IS2_ENTRY_WIDTH 376 #define VSC9959_VCAP_PORT_CNT 6 - -/* TODO: should find a better place for these */ -#define USXGMII_BMCR_RESET BIT(15) -#define USXGMII_BMCR_AN_EN BIT(12) -#define USXGMII_BMCR_RST_AN BIT(9) -#define USXGMII_BMSR_LNKS(status) (((status) & GENMASK(2, 2)) >> 2) -#define USXGMII_BMSR_AN_CMPL(status) (((status) & GENMASK(5, 5)) >> 5) -#define USXGMII_ADVERTISE_LNKS(x) (((x) << 15) & BIT(15)) -#define USXGMII_ADVERTISE_FDX BIT(12) -#define USXGMII_ADVERTISE_SPEED(x) (((x) << 9) & GENMASK(11, 9)) -#define USXGMII_LPA_LNKS(lpa) ((lpa) >> 15) -#define USXGMII_LPA_DUPLEX(lpa) (((lpa) & GENMASK(12, 12)) >> 12) -#define USXGMII_LPA_SPEED(lpa) (((lpa) & GENMASK(11, 9)) >> 9) - #define VSC9959_TAS_GCL_ENTRY_MAX 63 -enum usxgmii_speed { - USXGMII_SPEED_10 = 0, - USXGMII_SPEED_100 = 1, - USXGMII_SPEED_1000 = 2, - USXGMII_SPEED_2500 = 4, -}; - static const u32 vsc9959_ana_regmap[] = { REG(ANA_ADVLEARN, 0x0089a0), REG(ANA_VLANMASK, 0x0089a4), @@ -787,11 +767,10 @@ static void vsc9959_pcs_config_usxgmii(struct phy_device *pcs, { /* Configure device ability for the USXGMII Replicator */ phy_write_mmd(pcs, MDIO_MMD_VEND2, MII_ADVERTISE, - USXGMII_ADVERTISE_SPEED(USXGMII_SPEED_2500) | - USXGMII_ADVERTISE_LNKS(1) | + MDIO_LPA_USXGMII_2500FULL | + MDIO_LPA_USXGMII_LINK | ADVERTISE_SGMII | - ADVERTISE_LPACK | - USXGMII_ADVERTISE_FDX); + ADVERTISE_LPACK); } static void vsc9959_pcs_config(struct ocelot *ocelot, int port, @@ -1005,8 +984,8 @@ static void vsc9959_pcs_link_state_usxgmii(struct phy_device *pcs, return; pcs->autoneg = true; - pcs->autoneg_complete = USXGMII_BMSR_AN_CMPL(status); - pcs->link = USXGMII_BMSR_LNKS(status); + pcs->autoneg_complete = !!(status & BMSR_ANEGCOMPLETE); + pcs->link = !!(status & BMSR_LSTATUS); if (!pcs->link || !pcs->autoneg_complete) return; @@ -1015,24 +994,24 @@ static void vsc9959_pcs_link_state_usxgmii(struct phy_device *pcs, if (lpa < 0) return; - switch (USXGMII_LPA_SPEED(lpa)) { - case USXGMII_SPEED_10: + switch (lpa & MDIO_LPA_USXGMII_SPD_MASK) { + case MDIO_LPA_USXGMII_10: pcs->speed = SPEED_10; break; - case USXGMII_SPEED_100: + case MDIO_LPA_USXGMII_100: pcs->speed = SPEED_100; break; - case USXGMII_SPEED_1000: + case MDIO_LPA_USXGMII_1000: pcs->speed = SPEED_1000; break; - case USXGMII_SPEED_2500: + case MDIO_LPA_USXGMII_2500: pcs->speed = SPEED_2500; break; default: break; } - if (USXGMII_LPA_DUPLEX(lpa)) + if (lpa & MDIO_LPA_USXGMII_FULL_DUPLEX) pcs->duplex = DUPLEX_FULL; else pcs->duplex = DUPLEX_HALF; From patchwork Thu Jul 9 21:35:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 1326224 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=walle.cc header.i=@walle.cc header.a=rsa-sha256 header.s=mail2016061301 header.b=mPtFZJVa; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4B2qH52z7Fz9sSd for ; Fri, 10 Jul 2020 07:36:01 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726645AbgGIVfq (ORCPT ); Thu, 9 Jul 2020 17:35:46 -0400 Received: from ssl.serverraum.org ([176.9.125.105]:33811 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726367AbgGIVfn (ORCPT ); Thu, 9 Jul 2020 17:35:43 -0400 Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 5747123076; Thu, 9 Jul 2020 23:35:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1594330541; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2JbonOSJZttJ4wvWtSTnr7bMQWIJnMbJ7R1kG/eiBVM=; b=mPtFZJVaZNsRs1lLSnE77zPS2MI5KGURlPlPZGl7bKmgxqbxXXpkrLQvpS12S6T2WQUfbG NjTkJIU3ovSxYF0LYhHphzbpOinN4riXSTRYjaRb3MGNd1M9KX8SrPUkvwLu5O9oCLg6e+ eQyerLH+jjO5dAKeE+HB9sMM4llfH7s= From: Michael Walle To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: "David S . Miller" , Jakub Kicinski , Andrew Lunn , Michael Walle , Vladimir Oltean , Alex Marginean , Claudiu Manoil , Heiko Thiery , Russell King - ARM Linux admin , Ioana Ciornei , Microchip Linux Driver Support Subject: [PATCH net-next v6 3/4] net: enetc: Initialize SerDes for SGMII and USXGMII protocols Date: Thu, 9 Jul 2020 23:35:25 +0200 Message-Id: <20200709213526.21972-4-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200709213526.21972-1-michael@walle.cc> References: <20200709213526.21972-1-michael@walle.cc> MIME-Version: 1.0 X-Spam: Yes Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org ENETC has ethernet MACs capable of SGMII, 2500BaseX and USXGMII. But in order to use these protocols some SerDes configurations need to be performed. The SerDes is configurable via an internal PCS PHY which is connected to an internal MDIO bus at address 0. This patch basically removes the dependency on bootloader regarding SerDes initialization. Signed-off-by: Michael Walle Reviewed-by: Claudiu Manoil Tested-by: Vladimir Oltean --- .../net/ethernet/freescale/enetc/enetc_hw.h | 3 + .../net/ethernet/freescale/enetc/enetc_pf.c | 135 ++++++++++++++++++ .../net/ethernet/freescale/enetc/enetc_pf.h | 2 + 3 files changed, 140 insertions(+) diff --git a/drivers/net/ethernet/freescale/enetc/enetc_hw.h b/drivers/net/ethernet/freescale/enetc/enetc_hw.h index fc357bc56835..135bf46354ea 100644 --- a/drivers/net/ethernet/freescale/enetc/enetc_hw.h +++ b/drivers/net/ethernet/freescale/enetc/enetc_hw.h @@ -224,6 +224,9 @@ enum enetc_bdr_type {TX, RX}; #define ENETC_PM0_MAXFRM 0x8014 #define ENETC_SET_TX_MTU(val) ((val) << 16) #define ENETC_SET_MAXFRM(val) ((val) & 0xffff) + +#define ENETC_PM_IMDIO_BASE 0x8030 + #define ENETC_PM0_IF_MODE 0x8300 #define ENETC_PMO_IFM_RG BIT(2) #define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11)) diff --git a/drivers/net/ethernet/freescale/enetc/enetc_pf.c b/drivers/net/ethernet/freescale/enetc/enetc_pf.c index 4fac57dbb3c8..662740874841 100644 --- a/drivers/net/ethernet/freescale/enetc/enetc_pf.c +++ b/drivers/net/ethernet/freescale/enetc/enetc_pf.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* Copyright 2017-2019 NXP */ +#include #include #include #include @@ -833,6 +834,135 @@ static void enetc_of_put_phy(struct enetc_ndev_priv *priv) of_node_put(priv->phy_node); } +static int enetc_imdio_init(struct enetc_pf *pf, bool is_c45) +{ + struct device *dev = &pf->si->pdev->dev; + struct enetc_mdio_priv *mdio_priv; + struct phy_device *pcs; + struct mii_bus *bus; + int err; + + bus = mdiobus_alloc_size(sizeof(*mdio_priv)); + if (!bus) + return -ENOMEM; + + bus->name = "Freescale ENETC internal MDIO Bus"; + bus->read = enetc_mdio_read; + bus->write = enetc_mdio_write; + bus->parent = dev; + bus->phy_mask = ~0; + mdio_priv = bus->priv; + mdio_priv->hw = &pf->si->hw; + mdio_priv->mdio_base = ENETC_PM_IMDIO_BASE; + snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); + + err = mdiobus_register(bus); + if (err) { + dev_err(dev, "cannot register internal MDIO bus (%d)\n", err); + goto free_mdio_bus; + } + + pcs = get_phy_device(bus, 0, is_c45); + if (IS_ERR(pcs)) { + err = PTR_ERR(pcs); + dev_err(dev, "cannot get internal PCS PHY (%d)\n", err); + goto unregister_mdiobus; + } + + pf->imdio = bus; + pf->pcs = pcs; + + return 0; + +unregister_mdiobus: + mdiobus_unregister(bus); +free_mdio_bus: + mdiobus_free(bus); + return err; +} + +static void enetc_imdio_remove(struct enetc_pf *pf) +{ + if (pf->pcs) + put_device(&pf->pcs->mdio.dev); + if (pf->imdio) { + mdiobus_unregister(pf->imdio); + mdiobus_free(pf->imdio); + } +} + +static void enetc_configure_sgmii(struct phy_device *pcs) +{ + /* SGMII spec requires tx_config_Reg[15:0] to be exactly 0x4001 + * for the MAC PCS in order to acknowledge the AN. + */ + phy_write(pcs, MII_ADVERTISE, ADVERTISE_SGMII | ADVERTISE_LPACK); + + phy_write(pcs, ENETC_PCS_IF_MODE, + ENETC_PCS_IF_MODE_SGMII_EN | + ENETC_PCS_IF_MODE_USE_SGMII_AN); + + /* Adjust link timer for SGMII */ + phy_write(pcs, ENETC_PCS_LINK_TIMER1, ENETC_PCS_LINK_TIMER1_VAL); + phy_write(pcs, ENETC_PCS_LINK_TIMER2, ENETC_PCS_LINK_TIMER2_VAL); + + phy_write(pcs, MII_BMCR, BMCR_ANRESTART | BMCR_ANENABLE); +} + +static void enetc_configure_2500basex(struct phy_device *pcs) +{ + phy_write(pcs, ENETC_PCS_IF_MODE, + ENETC_PCS_IF_MODE_SGMII_EN | + ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_2500)); + + phy_write(pcs, MII_BMCR, BMCR_SPEED1000 | BMCR_FULLDPLX | BMCR_RESET); +} + +static void enetc_configure_usxgmii(struct phy_device *pcs) +{ + /* Configure device ability for the USXGMII Replicator */ + phy_write_mmd(pcs, MDIO_MMD_VEND2, MII_ADVERTISE, + ADVERTISE_SGMII | ADVERTISE_LPACK | + MDIO_LPA_USXGMII_FULL_DUPLEX); + + /* Restart PCS AN */ + phy_write_mmd(pcs, MDIO_MMD_VEND2, MII_BMCR, + BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART); +} + +static int enetc_configure_serdes(struct enetc_ndev_priv *priv) +{ + bool is_c45 = priv->if_mode == PHY_INTERFACE_MODE_USXGMII; + struct enetc_pf *pf = enetc_si_priv(priv->si); + int err; + + if (priv->if_mode != PHY_INTERFACE_MODE_SGMII && + priv->if_mode != PHY_INTERFACE_MODE_2500BASEX && + priv->if_mode != PHY_INTERFACE_MODE_USXGMII) + return 0; + + err = enetc_imdio_init(pf, is_c45); + if (err) + return err; + + switch (priv->if_mode) { + case PHY_INTERFACE_MODE_SGMII: + enetc_configure_sgmii(pf->pcs); + break; + case PHY_INTERFACE_MODE_2500BASEX: + enetc_configure_2500basex(pf->pcs); + break; + case PHY_INTERFACE_MODE_USXGMII: + enetc_configure_usxgmii(pf->pcs); + break; + default: + dev_err(&pf->si->pdev->dev, "Unsupported link mode %s\n", + phy_modes(priv->if_mode)); + } + + return 0; +} + static int enetc_pf_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { @@ -897,6 +1027,10 @@ static int enetc_pf_probe(struct pci_dev *pdev, if (err) dev_warn(&pdev->dev, "Fallback to PHY-less operation\n"); + err = enetc_configure_serdes(priv); + if (err) + dev_warn(&pdev->dev, "Attempted SerDes config but failed\n"); + err = register_netdev(ndev); if (err) goto err_reg_netdev; @@ -932,6 +1066,7 @@ static void enetc_pf_remove(struct pci_dev *pdev) priv = netdev_priv(si->ndev); unregister_netdev(si->ndev); + enetc_imdio_remove(pf); enetc_mdio_remove(pf); enetc_of_put_phy(priv); diff --git a/drivers/net/ethernet/freescale/enetc/enetc_pf.h b/drivers/net/ethernet/freescale/enetc/enetc_pf.h index 59e65a6f6c3e..2cb922b59f46 100644 --- a/drivers/net/ethernet/freescale/enetc/enetc_pf.h +++ b/drivers/net/ethernet/freescale/enetc/enetc_pf.h @@ -44,6 +44,8 @@ struct enetc_pf { DECLARE_BITMAP(active_vlans, VLAN_N_VID); struct mii_bus *mdio; /* saved for cleanup */ + struct mii_bus *imdio; + struct phy_device *pcs; }; int enetc_msg_psi_init(struct enetc_pf *pf); From patchwork Thu Jul 9 21:35:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 1326222 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=walle.cc header.i=@walle.cc header.a=rsa-sha256 header.s=mail2016061301 header.b=MXj6SXDN; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4B2qGr5KFSz9sRf for ; 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d=walle.cc; s=mail2016061301; t=1594330542; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CjY7on8agRG6TdUsMLxGYdjF6d2M4lGZIm/tWq8gksw=; b=MXj6SXDNPyVS2tikRYEtefMv/QXRgWqHdgvIO3nVPzuBuBCmlHldsx2Roqw0thnVdr7YG1 VkUYggpylu38phbsBIvtd2ksjIrwkHtmhZiPmaHTyWryszDC5ut9bUoz+B7lVmTA+hxWZA fJyzdwYGqQ7HVyX4YvAQJx2bfCPtFUc= From: Michael Walle To: netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: "David S . Miller" , Jakub Kicinski , Andrew Lunn , Michael Walle , Vladimir Oltean , Alex Marginean , Claudiu Manoil , Heiko Thiery , Russell King - ARM Linux admin , Ioana Ciornei , Microchip Linux Driver Support Subject: [PATCH net-next v6 4/4] net: enetc: Use DT protocol information to set up the ports Date: Thu, 9 Jul 2020 23:35:26 +0200 Message-Id: <20200709213526.21972-5-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200709213526.21972-1-michael@walle.cc> References: <20200709213526.21972-1-michael@walle.cc> MIME-Version: 1.0 X-Spam: Yes Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Alex Marginean Use DT information rather than in-band information from bootloader to set up MAC for XGMII. For RGMII use the DT indication in addition to RGMII defaults in hardware. However, this implies that PHY connection information needs to be extracted before netdevice creation, when the ENETC Port MAC is being configured. Signed-off-by: Alex Marginean Signed-off-by: Claudiu Manoil Signed-off-by: Michael Walle Tested-by: Vladimir Oltean --- .../net/ethernet/freescale/enetc/enetc_pf.c | 57 ++++++++++--------- .../net/ethernet/freescale/enetc/enetc_pf.h | 3 + 2 files changed, 34 insertions(+), 26 deletions(-) diff --git a/drivers/net/ethernet/freescale/enetc/enetc_pf.c b/drivers/net/ethernet/freescale/enetc/enetc_pf.c index 662740874841..dfc3acc841df 100644 --- a/drivers/net/ethernet/freescale/enetc/enetc_pf.c +++ b/drivers/net/ethernet/freescale/enetc/enetc_pf.c @@ -482,7 +482,8 @@ static void enetc_port_si_configure(struct enetc_si *si) enetc_port_wr(hw, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS); } -static void enetc_configure_port_mac(struct enetc_hw *hw) +static void enetc_configure_port_mac(struct enetc_hw *hw, + phy_interface_t phy_mode) { enetc_port_wr(hw, ENETC_PM0_MAXFRM, ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE)); @@ -498,9 +499,11 @@ static void enetc_configure_port_mac(struct enetc_hw *hw) ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC | ENETC_PM0_TX_EN | ENETC_PM0_RX_EN); /* set auto-speed for RGMII */ - if (enetc_port_rd(hw, ENETC_PM0_IF_MODE) & ENETC_PMO_IFM_RG) + if (enetc_port_rd(hw, ENETC_PM0_IF_MODE) & ENETC_PMO_IFM_RG || + phy_interface_mode_is_rgmii(phy_mode)) enetc_port_wr(hw, ENETC_PM0_IF_MODE, ENETC_PM0_IFM_RGAUTO); - if (enetc_global_rd(hw, ENETC_G_EPFBLPR(1)) == ENETC_G_EPFBLPR1_XGMII) + + if (phy_mode == PHY_INTERFACE_MODE_USXGMII) enetc_port_wr(hw, ENETC_PM0_IF_MODE, ENETC_PM0_IFM_XGMII); } @@ -524,7 +527,7 @@ static void enetc_configure_port(struct enetc_pf *pf) enetc_configure_port_pmac(hw); - enetc_configure_port_mac(hw); + enetc_configure_port_mac(hw, pf->if_mode); enetc_port_si_configure(pf->si); @@ -776,27 +779,27 @@ static void enetc_mdio_remove(struct enetc_pf *pf) mdiobus_unregister(pf->mdio); } -static int enetc_of_get_phy(struct enetc_ndev_priv *priv) +static int enetc_of_get_phy(struct enetc_pf *pf) { - struct enetc_pf *pf = enetc_si_priv(priv->si); - struct device_node *np = priv->dev->of_node; + struct device *dev = &pf->si->pdev->dev; + struct device_node *np = dev->of_node; struct device_node *mdio_np; int err; - priv->phy_node = of_parse_phandle(np, "phy-handle", 0); - if (!priv->phy_node) { + pf->phy_node = of_parse_phandle(np, "phy-handle", 0); + if (!pf->phy_node) { if (!of_phy_is_fixed_link(np)) { - dev_err(priv->dev, "PHY not specified\n"); + dev_err(dev, "PHY not specified\n"); return -ENODEV; } err = of_phy_register_fixed_link(np); if (err < 0) { - dev_err(priv->dev, "fixed link registration failed\n"); + dev_err(dev, "fixed link registration failed\n"); return err; } - priv->phy_node = of_node_get(np); + pf->phy_node = of_node_get(np); } mdio_np = of_get_child_by_name(np, "mdio"); @@ -804,15 +807,15 @@ static int enetc_of_get_phy(struct enetc_ndev_priv *priv) of_node_put(mdio_np); err = enetc_mdio_probe(pf); if (err) { - of_node_put(priv->phy_node); + of_node_put(pf->phy_node); return err; } } - err = of_get_phy_mode(np, &priv->if_mode); + err = of_get_phy_mode(np, &pf->if_mode); if (err) { - dev_err(priv->dev, "missing phy type\n"); - of_node_put(priv->phy_node); + dev_err(dev, "missing phy type\n"); + of_node_put(pf->phy_node); if (of_phy_is_fixed_link(np)) of_phy_deregister_fixed_link(np); else @@ -824,14 +827,14 @@ static int enetc_of_get_phy(struct enetc_ndev_priv *priv) return 0; } -static void enetc_of_put_phy(struct enetc_ndev_priv *priv) +static void enetc_of_put_phy(struct enetc_pf *pf) { - struct device_node *np = priv->dev->of_node; + struct device_node *np = pf->si->pdev->dev.of_node; if (np && of_phy_is_fixed_link(np)) of_phy_deregister_fixed_link(np); - if (priv->phy_node) - of_node_put(priv->phy_node); + if (pf->phy_node) + of_node_put(pf->phy_node); } static int enetc_imdio_init(struct enetc_pf *pf, bool is_c45) @@ -994,6 +997,10 @@ static int enetc_pf_probe(struct pci_dev *pdev, pf->si = si; pf->total_vfs = pci_sriov_get_totalvfs(pdev); + err = enetc_of_get_phy(pf); + if (err) + dev_warn(&pdev->dev, "Fallback to PHY-less operation\n"); + enetc_configure_port(pf); enetc_get_si_caps(si); @@ -1008,6 +1015,8 @@ static int enetc_pf_probe(struct pci_dev *pdev, enetc_pf_netdev_setup(si, ndev, &enetc_ndev_ops); priv = netdev_priv(ndev); + priv->phy_node = pf->phy_node; + priv->if_mode = pf->if_mode; enetc_init_si_rings_params(priv); @@ -1023,10 +1032,6 @@ static int enetc_pf_probe(struct pci_dev *pdev, goto err_alloc_msix; } - err = enetc_of_get_phy(priv); - if (err) - dev_warn(&pdev->dev, "Fallback to PHY-less operation\n"); - err = enetc_configure_serdes(priv); if (err) dev_warn(&pdev->dev, "Attempted SerDes config but failed\n"); @@ -1040,7 +1045,6 @@ static int enetc_pf_probe(struct pci_dev *pdev, return 0; err_reg_netdev: - enetc_of_put_phy(priv); enetc_free_msix(priv); err_alloc_msix: enetc_free_si_resources(priv); @@ -1048,6 +1052,7 @@ static int enetc_pf_probe(struct pci_dev *pdev, si->ndev = NULL; free_netdev(ndev); err_alloc_netdev: + enetc_of_put_phy(pf); err_map_pf_space: enetc_pci_remove(pdev); @@ -1068,7 +1073,7 @@ static void enetc_pf_remove(struct pci_dev *pdev) enetc_imdio_remove(pf); enetc_mdio_remove(pf); - enetc_of_put_phy(priv); + enetc_of_put_phy(pf); enetc_free_msix(priv); diff --git a/drivers/net/ethernet/freescale/enetc/enetc_pf.h b/drivers/net/ethernet/freescale/enetc/enetc_pf.h index 2cb922b59f46..0d0ee91282a5 100644 --- a/drivers/net/ethernet/freescale/enetc/enetc_pf.h +++ b/drivers/net/ethernet/freescale/enetc/enetc_pf.h @@ -46,6 +46,9 @@ struct enetc_pf { struct mii_bus *mdio; /* saved for cleanup */ struct mii_bus *imdio; struct phy_device *pcs; + + struct device_node *phy_node; + phy_interface_t if_mode; }; int enetc_msg_psi_init(struct enetc_pf *pf);