From patchwork Mon Jul 6 09:31:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 1323507 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=cg2exXge; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4B0hhZ4F3zz9sSn for ; Mon, 6 Jul 2020 20:32:14 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728926AbgGFKb4 (ORCPT ); Mon, 6 Jul 2020 06:31:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728733AbgGFKbz (ORCPT ); Mon, 6 Jul 2020 06:31:55 -0400 Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F3E4EC061794; Mon, 6 Jul 2020 03:31:54 -0700 (PDT) Received: by mail-wr1-x444.google.com with SMTP id f18so32169051wrs.0; Mon, 06 Jul 2020 03:31:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zIc+ryXbVspn9u+GSLsSwM5Cff3RjamOLjlQZyxFr+U=; b=cg2exXge4dbjo5XG0pFDqzL4EhbxVye2Y2SrCQv/P2Dg2tU+/5QN+wUT5XfILrK669 StfO6eeTUTyg3zJq2I3CJ+rZAEjFi03MOLGodp2ZjGdKraqFoyDCCQLbp+stXcS0rSGk EeJxe8rvAE8Tbp6sce9+rVFKzDBtgvB3d6wCyI5HatgTE2+x3QE6ooHDcRIP0cPGFQp7 z1A+03J1XT8xTyK3YOYa4o61qT3mqZBb5lSTgp0LNkck2wLm8qRcpiFspO81+BGlBc4Z yus+TgOMZRecaarzNx1To3/r7LBqROPWCwgsUF0Y4B8XTureThhh1unrmpXQuys2tGqC ihZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zIc+ryXbVspn9u+GSLsSwM5Cff3RjamOLjlQZyxFr+U=; b=fDYAUgQ6ARu476ErYISfWRE9bO5Ctz1A7qS9/2wDUmgJrSCW6T+qsDzjrbVd1hQcwj g1bUFUX8EXnK3FDb1VE3iupTGrD2VKI9tm6Vc3fT80aTZfRaMGr5zJx0Tgb5g7xKKJui El4OO7TU3w1Cuen37zosDyLLRqM/VyUu4R/g9yLy8npTKpIC5EoNESq6F6ueCjIj/Aco ky+UQ5DCUHoaQhfvHRaIaR2TUXTB0fSmnAE7k9aw1e1tk75SZQYrWgXje+CMgMkoetrG Dmk67fmyFjnLwuY2E8DCHf/3TpzU+7Cab8d74+27WlAJ/8n0bZMQuPCI3tU58+oQcND1 HZRg== X-Gm-Message-State: AOAM531UeooH/NVi1BJ5WMtaiW7uN8XfreXJ0xqsrfmZ+t/MHXSG2m9v A2j0wReKdOeZw5oCnZo8bY+sbt1eGybM4Q== X-Google-Smtp-Source: ABdhPJxCtqWPmnt50I/FTSU/wExRSzDqqvPU1j31/xL1NsH+jBfN84hjLCyjVT7+LEc9gP3gIrxkeA== X-Received: by 2002:adf:91e1:: with SMTP id 88mr41365811wri.89.1594031513765; Mon, 06 Jul 2020 03:31:53 -0700 (PDT) Received: from net.saheed (51B7C2DF.dsl.pool.telekom.hu. [81.183.194.223]) by smtp.gmail.com with ESMTPSA id 22sm24216859wmb.11.2020.07.06.03.31.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 03:31:53 -0700 (PDT) From: Saheed Olayemi Bolarinwa To: helgaas@kernel.org Cc: Bolarinwa Olayemi Saheed , bjorn@helgaas.com, Lukas Wunner , skhan@linuxfoundation.org, linux-pci@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/11 RFC] PCI: pciehp: Validate with the return value of pcie_capability_read_*() Date: Mon, 6 Jul 2020 11:31:13 +0200 Message-Id: <20200706093121.9731-4-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20200706093121.9731-1-refactormyself@gmail.com> References: <20200706093121.9731-1-refactormyself@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bolarinwa Olayemi Saheed On any failure pcie_capability_read_word() sets it's last parameter, *val to 0. If pci_config_read_word() fails the *val is reset to 0. Any function which check only for a frabricated ~0 which fail in this case. Include a check on the return value of pcie_capability_read_dword() to confirm success or failure. Suggested-by: Bjorn Helgaas Signed-off-by: Bolarinwa Olayemi Saheed --- drivers/pci/hotplug/pciehp_hpc.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 53433b37e181..5af281d97d4f 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -86,10 +86,11 @@ static int pcie_poll_cmd(struct controller *ctrl, int timeout) { struct pci_dev *pdev = ctrl_dev(ctrl); u16 slot_status; + int ret; do { - pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); - if (slot_status == (u16) ~0) { + ret = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); + if (ret || (slot_status == (u16) ~0)) { ctrl_info(ctrl, "%s: no response from device\n", __func__); return 0; @@ -156,6 +157,7 @@ static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd, { struct pci_dev *pdev = ctrl_dev(ctrl); u16 slot_ctrl_orig, slot_ctrl; + int ret; mutex_lock(&ctrl->ctrl_lock); @@ -164,8 +166,8 @@ static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd, */ pcie_wait_cmd(ctrl); - pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); - if (slot_ctrl == (u16) ~0) { + ret = pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); + if (ret || (slot_ctrl == (u16) ~0)) { ctrl_info(ctrl, "%s: no response from device\n", __func__); goto out; } @@ -430,7 +432,7 @@ void pciehp_get_latch_status(struct controller *ctrl, u8 *status) * removed immediately after the check so the caller may need to take * this into account. * - * It the hotplug controller itself is not available anymore returns + * If the hotplug controller itself is not available anymore returns * %-ENODEV. */ int pciehp_card_present(struct controller *ctrl) @@ -591,8 +593,8 @@ static irqreturn_t pciehp_isr(int irq, void *dev_id) } read_status: - pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status); - if (status == (u16) ~0) { + ret = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status); + if (ret || (status == (u16) ~0)) { ctrl_info(ctrl, "%s: no response from device\n", __func__); if (parent) pm_runtime_put(parent); From patchwork Mon Jul 6 09:31:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 1323508 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=TG4pzGRb; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4B0hhf49Byz9sSn for ; Mon, 6 Jul 2020 20:32:18 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728968AbgGFKcO (ORCPT ); Mon, 6 Jul 2020 06:32:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728929AbgGFKb4 (ORCPT ); Mon, 6 Jul 2020 06:31:56 -0400 Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27E09C061794; Mon, 6 Jul 2020 03:31:56 -0700 (PDT) Received: by mail-wm1-x341.google.com with SMTP id q15so38663092wmj.2; Mon, 06 Jul 2020 03:31:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RPTa/b9ulSr2LIoV7+9N5nhgam/KG2MWD7MpfjJwUI4=; b=TG4pzGRbEwH/BSJarGEyRYf1QP7euiq3ZvuQTcexU3ZoYSD+b8fqCNHTZEOCWFGXWf FfSoXFkDiMaB+pSiKoOy6gl2ISBkzY6SenyTzPtviHoLi+PZSSC3+dbUqBIv64wSLyzm l0L815djwPABf2iKVNWgUMkhl0Yu6//iDVLTkxJiy+M9FZQAt+fa9aGp4nPF3j0dptnL TAmviTKz/G7eCqJ686+bgEzJGbI15po6Pwlk1VRKHHCjT+539hC3LuaA0aynuNXG41u8 I/O6EoGxYhVaVdls2XfiIzdklTWKIwJmOhKz9wYHDk5JmkqCw7WUMtJUFLSmRwxrf6su qjog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RPTa/b9ulSr2LIoV7+9N5nhgam/KG2MWD7MpfjJwUI4=; b=n+KjJPvbR3Y9HUPlnadPYwlW5CAdm/JGYqFprFJF06vDny/lmxDXlVEJa1q1Fqm8Xy TKQGItJTnoOW5dnsctah9RKchLz85SddToTVIKHkpLSuPsfZxIpQq1uZAOG97jClWDvL O6ktBo5ZOQ1urBeOpAoIQ6nyHi9d6zqCfxlXj3b9ixyE0ROl44cx3/nG1WZLo2wX8ZI1 1AaUCInB1BwoAAzuIjSQZlDfaKETZmtuOjGV/L4nQoy4Z7MJF7Sb5EAq8upJBWQ8lcnc Uw0wtIh0jKXuBYj+kP1vvreZZXe1H7A1yPebbuh3zM9+K43UBnVsy0Bst7QO4PubFphl YU2Q== X-Gm-Message-State: AOAM531wmeWobjY296S3Y3r6v9oQ2rasceK6jRIaBD2sumYRpB1XE5Xm f+W4ePgdtDJWTYZQ4YGJ+IA= X-Google-Smtp-Source: ABdhPJywhsCbkbFGmRLpYBAbKoNOxH4X7OJZCSZcE5Hy9HRvf3pC50XF2xqZYYR9LVEyfSHQgxlr7A== X-Received: by 2002:a1c:9911:: with SMTP id b17mr44258657wme.135.1594031514919; Mon, 06 Jul 2020 03:31:54 -0700 (PDT) Received: from net.saheed (51B7C2DF.dsl.pool.telekom.hu. [81.183.194.223]) by smtp.gmail.com with ESMTPSA id 22sm24216859wmb.11.2020.07.06.03.31.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 03:31:54 -0700 (PDT) From: Saheed Olayemi Bolarinwa To: helgaas@kernel.org Cc: Bolarinwa Olayemi Saheed , bjorn@helgaas.com, skhan@linuxfoundation.org, linux-pci@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/11 RFC] PCI: pciehp: Validate with the return value of pcie_capability_read_*() Date: Mon, 6 Jul 2020 11:31:14 +0200 Message-Id: <20200706093121.9731-5-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20200706093121.9731-1-refactormyself@gmail.com> References: <20200706093121.9731-1-refactormyself@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bolarinwa Olayemi Saheed On failure pcie_capability_read_dword() sets it's last parameter, val to 0. However, with Patch 11/11, it is possible that val is set to ~0 on failure. This would introduce a bug because (x & x) == (~0 & x). This bug can be avoided if the return value of pcie_capability_read_dword is checked to confirm success. Check the return value of pcie_capability_read_dword() to ensure success. Return a value that indicate the result of pcie_capability_read_dword(). Suggested-by: Bjorn Helgaas Signed-off-by: Bolarinwa Olayemi Saheed --- drivers/pci/hotplug/pciehp_hpc.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 5af281d97d4f..0b691e37fd04 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -277,10 +277,11 @@ static void pcie_wait_for_presence(struct pci_dev *pdev) { int timeout = 1250; u16 slot_status; + int ret; do { - pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); - if (slot_status & PCI_EXP_SLTSTA_PDS) + ret = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); + if (!ret && (slot_status & PCI_EXP_SLTSTA_PDS)) return; msleep(10); timeout -= 10; @@ -354,12 +355,13 @@ int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot, struct controller *ctrl = to_ctrl(hotplug_slot); struct pci_dev *pdev = ctrl_dev(ctrl); u16 slot_ctrl; + int ret; pci_config_pm_runtime_get(pdev); - pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); + ret = pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); pci_config_pm_runtime_put(pdev); *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6; - return 0; + return pcibios_err_to_errno(ret); } int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status) @@ -367,9 +369,10 @@ int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status) struct controller *ctrl = to_ctrl(hotplug_slot); struct pci_dev *pdev = ctrl_dev(ctrl); u16 slot_ctrl; + int ret; pci_config_pm_runtime_get(pdev); - pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); + ret = pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); pci_config_pm_runtime_put(pdev); ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); @@ -389,7 +392,7 @@ int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status) break; } - return 0; + return pcibios_err_to_errno(ret); } void pciehp_get_power_status(struct controller *ctrl, u8 *status) From patchwork Mon Jul 6 09:31:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 1323506 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=PNS1AOdh; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4B0hhY2WLjz9sTQ for ; Mon, 6 Jul 2020 20:32:13 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728938AbgGFKb6 (ORCPT ); Mon, 6 Jul 2020 06:31:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728733AbgGFKb5 (ORCPT ); Mon, 6 Jul 2020 06:31:57 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 43176C061794; Mon, 6 Jul 2020 03:31:57 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id q15so38663139wmj.2; Mon, 06 Jul 2020 03:31:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gLOVpKwfnzdqPjeF9FisBhEgOhhTDNWgNNsho9uiBK8=; b=PNS1AOdhKTtQLZQyI5JQWqsfSKn6StXnzQ9fS+uIkFKt/eYOI3XsDToqjFRZ8Uquu0 5aEvnYw7rdO3qku9pKGyrBh4S8b8PdsY48PxlH1g2BODDaHYIdbqj+ZQYHbgRbV9Xfr7 dVqET9v2e1LhxYB9b6sUSd2yvSB4NGKussrpxDxU84gw5SCZT3xIljO6U7jpLF+C+oZ6 uQmGF7YTWB7i7ulAKINHdEhfOMstQHpk0/8mjw3IRY9/EiJ/nvuekRLXAL4BFgaxRBEH MqLuCoFx4859jBxZP4AqdeBycYg5TURUtuTIkGoiPh1jPxJCIlUdU1gR1+DsQYrhttpK Gr8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gLOVpKwfnzdqPjeF9FisBhEgOhhTDNWgNNsho9uiBK8=; b=GyYz5RlT3lZtE96tpmw0WXsj3+q6ETxGpMzCdG5MR3c/pdPrnsBBn5YkcA01SYzBne 0OXzTs1kx/oxzPuRuWD3vjKs2y1R09Pgy8jBVT/kkxwXCowPKcrDsfJf9F185AOpfjaa 8eb+FcgXhyxmhvkB78+Fzv0+Xtuh0dk+O+vntJBVn24RdkTxWyPmOJs/yf62WY1+UGwF 6VzjxdkQUrhzUj94lEUOmNY+ZbgNWgNu5phbEAP8Kxa2eNW6StO2JzHy6o4PCBB+1rDE InMBshcBIsUNhrLrQLy2/ESzC6JHb0NPlWh0G6qEDTmAQeEE0XxTapC20tRIcpV6JrBI RaCA== X-Gm-Message-State: AOAM531ze1Kjh6JzjI8uBLl/F9upLNOMl77FLtchzh/wha5CDs1UnCV4 6QbvTljeQQpKaMcID4nBz1Q= X-Google-Smtp-Source: ABdhPJxwFsuaA1UtVrdWVLhkh7v8Bjopk63guA9Az8X8ssMRTKHtPQSA15Wy/yavGlrGm3dAMS6F+Q== X-Received: by 2002:a1c:28a:: with SMTP id 132mr19176296wmc.109.1594031515995; Mon, 06 Jul 2020 03:31:55 -0700 (PDT) Received: from net.saheed (51B7C2DF.dsl.pool.telekom.hu. [81.183.194.223]) by smtp.gmail.com with ESMTPSA id 22sm24216859wmb.11.2020.07.06.03.31.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 03:31:55 -0700 (PDT) From: Saheed Olayemi Bolarinwa To: helgaas@kernel.org Cc: Bolarinwa Olayemi Saheed , bjorn@helgaas.com, skhan@linuxfoundation.org, linux-pci@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/11 RFC] PCI: pciehp: Make "Power On" the default Date: Mon, 6 Jul 2020 11:31:15 +0200 Message-Id: <20200706093121.9731-6-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20200706093121.9731-1-refactormyself@gmail.com> References: <20200706093121.9731-1-refactormyself@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bolarinwa Olayemi Saheed The default case of the switch statement is redundant since PCI_EXP_SLTCTL_PCC is only a single bit. pcie_capability_read_word() currently causes "On" value to be set if it fails. Patch 11/11 changes the behaviour of pcie_capability_read_word() so on falure the "Off" value will be set. Make the function set status to "Power On" by default and only set to Set "Power Off" only if pcie_capability_read_word() is successful and (slot_ctrl & PCI_EXP_SLTCTL_PCC) == PCI_EXP_SLTCTL_PWR_OFF. Suggested-by: Bjorn Helgaas Signed-off-by: Bolarinwa Olayemi Saheed --- drivers/pci/hotplug/pciehp_hpc.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 0b691e37fd04..78f806a9c6f1 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -399,22 +399,16 @@ void pciehp_get_power_status(struct controller *ctrl, u8 *status) { struct pci_dev *pdev = ctrl_dev(ctrl); u16 slot_ctrl; + int ret; - pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); + *status = 1; /* On */ + ret = pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); - switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) { - case PCI_EXP_SLTCTL_PWR_ON: - *status = 1; /* On */ - break; - case PCI_EXP_SLTCTL_PWR_OFF: + if (!ret && + ((slot_ctrl & PCI_EXP_SLTCTL_PCC) == PCI_EXP_SLTCTL_PWR_OFF)) *status = 0; /* Off */ - break; - default: - *status = 0xFF; - break; - } } void pciehp_get_latch_status(struct controller *ctrl, u8 *status) From patchwork Mon Jul 6 09:31:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 1323505 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=hcaH530k; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4B0hhX4Sh2z9sTH for ; Mon, 6 Jul 2020 20:32:12 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728956AbgGFKcA (ORCPT ); Mon, 6 Jul 2020 06:32:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728950AbgGFKb7 (ORCPT ); Mon, 6 Jul 2020 06:31:59 -0400 Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 70744C061794; Mon, 6 Jul 2020 03:31:59 -0700 (PDT) Received: by mail-wr1-x443.google.com with SMTP id j4so37813161wrp.10; Mon, 06 Jul 2020 03:31:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=h+kDFiIJUTsKW3n99UHZzrHB6kCAOHxPSRHyJei2C70=; b=hcaH530k48yc7s44pzmTgEgAKe9ym1JiRcDUKaoV18znhk84JN+6UTSautPPpn/KG5 nfAWKFT49ue3SEQWExx2mPrSI3lwqdISJCA+tAfHLR9qo0ANtg9CjpYqWlfgTzDLrtL/ 6wuwGn0C/Q+amjCZ7I1KJdizN+8zBIkb6vzagJnHabiLCafVUDdKFjoWM0MSZoFiPA7H b5uPNVJrMStmy/Q3pf1Jvf+GOLEBum7VlB+0LXnPuZG6UX34bJD4/XKXzwREw/7jM2wW Su5BSnTS7RGuSww61CwHesVyp4m81v1ME537f62iMgNl8wH/qWgMH9R1YgBFKSwnwEoV 0W5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=h+kDFiIJUTsKW3n99UHZzrHB6kCAOHxPSRHyJei2C70=; b=PEnemhDXC8mfwWTJYwn+/ly8AAGxYeIhmB9LqxoMk4aAzqBIWRPgeASO+7qmZRMPKz TUeCUKMHlW2lM96Hff0L9X3v3FrcJsuYzHFAfzpuaTb1SqB0Iy0rarlMUNE7RMTR8Bz2 BKaMlrXDilOUyLWBRwcSsyrj5os3IsPcrVmfUyS0IIWjl4Ps/6u1xPga1qCyrHYt1f2O ioYTKwB3/a0dzujQZg5QTCoyK8BQf2EudZ50RIz1eIpq29BsV4qk4hHjVACibmh8tbRX e7zPEszhq/ZKlGfQ6YTNPVulDVCmlqVWApnKJVeJPN0rzUp4wcZfe/4aTIh8tIucLKZ6 lTKw== X-Gm-Message-State: AOAM531ZrskBZ9Mn23SsR2KGlDu/RZ4OZ1nOT9xcJtf5SfRM6EuWyv0z Af+JDdaJo1C1AjmGTU19W70= X-Google-Smtp-Source: ABdhPJwVg1BymNode15ugRIv8aKKBbIQzIjGgGl2HqCXAiJO/2zF3/GZe/M/NE/k4imThhnK3ydmwQ== X-Received: by 2002:adf:e5d0:: with SMTP id a16mr45907268wrn.48.1594031518242; Mon, 06 Jul 2020 03:31:58 -0700 (PDT) Received: from net.saheed (51B7C2DF.dsl.pool.telekom.hu. [81.183.194.223]) by smtp.gmail.com with ESMTPSA id 22sm24216859wmb.11.2020.07.06.03.31.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 03:31:57 -0700 (PDT) From: Saheed Olayemi Bolarinwa To: helgaas@kernel.org Cc: Bolarinwa Olayemi Saheed , bjorn@helgaas.com, skhan@linuxfoundation.org, linux-pci@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/11 RFC] PCI: Validate with the return value of pcie_capability_read_*() Date: Mon, 6 Jul 2020 11:31:17 +0200 Message-Id: <20200706093121.9731-8-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20200706093121.9731-1-refactormyself@gmail.com> References: <20200706093121.9731-1-refactormyself@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bolarinwa Olayemi Saheed On failure pcie_capability_read_dword() sets it's last parameter, val to 0. However, with Patch 11/11, it is possible that val is set to ~0 on failure. This would introduce a bug because (x & x) == (~0 & x). This bug can be avoided if the return value of pcie_capability_read_dword is checked to confirm success. Check the return value of pcie_capability_read_dword() to ensure success. Suggested-by: Bjorn Helgaas Signed-off-by: Bolarinwa Olayemi Saheed --- drivers/pci/probe.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 2f66988cea25..3c87a8a1d4b5 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1121,10 +1121,11 @@ EXPORT_SYMBOL(pci_add_new_bus); static void pci_enable_crs(struct pci_dev *pdev) { u16 root_cap = 0; + int ret; /* Enable CRS Software Visibility if supported */ - pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); - if (root_cap & PCI_EXP_RTCAP_CRSVIS) + ret = pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); + if (!ret && (root_cap & PCI_EXP_RTCAP_CRSVIS)) pcie_capability_set_word(pdev, PCI_EXP_RTCTL, PCI_EXP_RTCTL_CRSSVE); } @@ -1519,9 +1520,10 @@ void set_pcie_port_type(struct pci_dev *pdev) void set_pcie_hotplug_bridge(struct pci_dev *pdev) { u32 reg32; + int ret; - pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); - if (reg32 & PCI_EXP_SLTCAP_HPC) + ret = pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); + if (!ret && (reg32 & PCI_EXP_SLTCAP_HPC)) pdev->is_hotplug_bridge = 1; } @@ -2057,10 +2059,11 @@ int pci_configure_extended_tags(struct pci_dev *dev, void *ign) bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) { u16 v; + int ret; - pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); + ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); - return !!(v & PCI_EXP_DEVCTL_RELAX_EN); + return (!ret && !!(v & PCI_EXP_DEVCTL_RELAX_EN)); } EXPORT_SYMBOL(pcie_relaxed_ordering_enabled); @@ -2096,16 +2099,17 @@ static void pci_configure_ltr(struct pci_dev *dev) struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); struct pci_dev *bridge; u32 cap, ctl; + int ret; if (!pci_is_pcie(dev)) return; - pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); - if (!(cap & PCI_EXP_DEVCAP2_LTR)) + ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); + if (ret || !(cap & PCI_EXP_DEVCAP2_LTR)) return; - pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl); - if (ctl & PCI_EXP_DEVCTL2_LTR_EN) { + ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl); + if (!ret && (ctl & PCI_EXP_DEVCTL2_LTR_EN)) { if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { dev->ltr_path = 1; return; @@ -2142,12 +2146,13 @@ static void pci_configure_eetlp_prefix(struct pci_dev *dev) struct pci_dev *bridge; int pcie_type; u32 cap; + int ret; if (!pci_is_pcie(dev)) return; - pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); - if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) + ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); + if (ret || !(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) return; pcie_type = pci_pcie_type(dev); From patchwork Mon Jul 6 09:31:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 1323504 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=r5XcN9Oq; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4B0hhW6CBbz9sTF for ; Mon, 6 Jul 2020 20:32:11 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728950AbgGFKcC (ORCPT ); Mon, 6 Jul 2020 06:32:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47170 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728960AbgGFKcB (ORCPT ); Mon, 6 Jul 2020 06:32:01 -0400 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A0AEDC061794; Mon, 6 Jul 2020 03:32:00 -0700 (PDT) Received: by mail-wm1-x344.google.com with SMTP id q15so38663288wmj.2; Mon, 06 Jul 2020 03:32:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=t6GU51on/sjAi6p+kLT9PGikn6ea3QP4rvjpiDaqtyQ=; b=r5XcN9OqOkS0fFKzvOC+DqsZw3O1pmDYS3v9XcE9r6dq5TDKngHKKcBC1bm8x4m6x1 jiiQxPMHJezkuGHMalDZJE6TZjXVuubFQQLwCdS0odUeQh42P2gSuwlulB8MT7fOJ+gN 071Hfr0bxfDdjCPC87n4OW3FqgfVxgyZJ7wBOXN2l4TsuNFEXsqNTUGyNk68OTuyutF5 6hScBQAHYBV7GXzixO9133/UvmXgd32Sip+SFkIIfOc85Hh7iD76MBYUafKsnKqabWYr YNdwMfvZrBzi7nkSQjbLYgg4W65Md9E6RfHi49VoQfkCj0zNBV5AL+NZ7wpDeFArLWwx 0oug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=t6GU51on/sjAi6p+kLT9PGikn6ea3QP4rvjpiDaqtyQ=; b=exPiYSwgN1NRoWeSzJC58gTFMyks5aXjTvAGzejk9B0a+OLHkBcOHubK3+IOV1hx89 gEBoq35AjIKkd1ovZLgu32w1CEskkhyRn+OYcT70ejtl7gqGk3lSKG+0gn47kEEfu87V Q50KZUr+72bVenj4XsZklGH4njUu0j6mxM+5eYZFGyU92od9w9SmvWl+j2JzeNcZmbYt sdUPrE5lxE9sDaZTfa2RG/csUcaA78EquTZdmxFzn9Kaknxqm1YxTXZXAgXUIHJy8qX/ g1uIHxYl46SCFPmPIQ8TLCfpUH3wmBfveG7Ud/Jog/znl6w6vQDZ62OoPHMEAxOtbP1i MVug== X-Gm-Message-State: AOAM532PXl1T0RxYvzbu1ur3GiEn5PTZQjGRf3usBxZm6g3wT1YvfqBK 6e7vbue+oVQSuW6mnc0GRsw= X-Google-Smtp-Source: ABdhPJyjotNeFrSLhXBXdNTY9AWQbsB9ir2KScfaQcnzXL4qoO9Wo945aZ7sxjmUiMKkvBPv4hfp7A== X-Received: by 2002:a1c:8117:: with SMTP id c23mr46495692wmd.157.1594031519334; Mon, 06 Jul 2020 03:31:59 -0700 (PDT) Received: from net.saheed (51B7C2DF.dsl.pool.telekom.hu. [81.183.194.223]) by smtp.gmail.com with ESMTPSA id 22sm24216859wmb.11.2020.07.06.03.31.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 03:31:58 -0700 (PDT) From: Saheed Olayemi Bolarinwa To: helgaas@kernel.org Cc: Bolarinwa Olayemi Saheed , bjorn@helgaas.com, skhan@linuxfoundation.org, linux-pci@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-kernel@vger.kernel.org Subject: [PATCH 8/11 RFC] PCI/PM: Use error return value from pcie_capability_read_*() Date: Mon, 6 Jul 2020 11:31:18 +0200 Message-Id: <20200706093121.9731-9-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20200706093121.9731-1-refactormyself@gmail.com> References: <20200706093121.9731-1-refactormyself@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bolarinwa Olayemi Saheed On failure pcie_capability_read_dword() sets it's last parameter, val to 0. However, with Patch 11/11, it is possible that val is set to ~0 on failure. This would introduce a bug because (x & x) == (~0 & x). This bug can be avoided if the return value of pcie_capability_read_dword is checked to confirm success. Check the return value of pcie_capability_read_dword() to ensure success. Suggested-by: Bjorn Helgaas Signed-off-by: Bolarinwa Olayemi Saheed --- drivers/pci/pci.c | 52 ++++++++++++++++++++++++++++++----------------- 1 file changed, 33 insertions(+), 19 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index ce096272f52b..9f18ffbf7bd4 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3207,6 +3207,7 @@ void pci_configure_ari(struct pci_dev *dev) { u32 cap; struct pci_dev *bridge; + int ret; if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) return; @@ -3215,8 +3216,8 @@ void pci_configure_ari(struct pci_dev *dev) if (!bridge) return; - pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); - if (!(cap & PCI_EXP_DEVCAP2_ARI)) + ret = pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); + if (ret || !(cap & PCI_EXP_DEVCAP2_ARI)) return; if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { @@ -3606,6 +3607,7 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) struct pci_bus *bus = dev->bus; struct pci_dev *bridge; u32 cap, ctl2; + int ret; if (!pci_is_pcie(dev)) return -EINVAL; @@ -3629,28 +3631,29 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) while (bus->parent) { bridge = bus->self; - pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); + ret = pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, + &cap); switch (pci_pcie_type(bridge)) { /* Ensure switch ports support AtomicOp routing */ case PCI_EXP_TYPE_UPSTREAM: case PCI_EXP_TYPE_DOWNSTREAM: - if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) + if (ret || !(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) return -EINVAL; break; /* Ensure root port supports all the sizes we care about */ case PCI_EXP_TYPE_ROOT_PORT: - if ((cap & cap_mask) != cap_mask) + if (ret || ((cap & cap_mask) != cap_mask)) return -EINVAL; break; } /* Ensure upstream ports don't block AtomicOps on egress */ if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) { - pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, - &ctl2); - if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK) + ret = pcie_capability_read_dword(bridge, + PCI_EXP_DEVCTL2, &ctl2); + if (!ret && (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK) return -EINVAL; } @@ -4507,12 +4510,13 @@ EXPORT_SYMBOL(pci_wait_for_pending_transaction); bool pcie_has_flr(struct pci_dev *dev) { u32 cap; + int ret; if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) return false; - pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); - return cap & PCI_EXP_DEVCAP_FLR; + ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); + return (!ret && !!(cap & PCI_EXP_DEVCAP_FLR)); } EXPORT_SYMBOL_GPL(pcie_has_flr); @@ -4672,7 +4676,7 @@ static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active, msleep(20); for (;;) { pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); - ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); + ret = !!(!ret && (lnk_status & PCI_EXP_LNKSTA_DLLLA)); if (ret == active) break; if (timeout <= 0) @@ -5774,6 +5778,7 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, enum pci_bus_speed next_speed; enum pcie_link_width next_width; u32 bw, next_bw; + int ret; if (speed) *speed = PCI_SPEED_UNKNOWN; @@ -5783,7 +5788,12 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, bw = 0; while (dev) { - pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); + ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); + + if (ret) { + dev = pci_upstream_bridge(dev); + continue; + } next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> @@ -5820,6 +5830,7 @@ EXPORT_SYMBOL(pcie_bandwidth_available); enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) { u32 lnkcap2, lnkcap; + int ret; /* * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The @@ -5830,16 +5841,18 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) * should use the Supported Link Speeds field in Link Capabilities, * where only 2.5 GT/s and 5.0 GT/s speeds were defined. */ - pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); + ret = pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); /* PCIe r3.0-compliant */ - if (lnkcap2) + if (!ret && lnkcap2) return PCIE_LNKCAP2_SLS2SPEED(lnkcap2); - pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); - if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB) + ret = pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); + if (!ret && + ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)) return PCIE_SPEED_5_0GT; - else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB) + else if (!ret && + ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)) return PCIE_SPEED_2_5GT; return PCI_SPEED_UNKNOWN; @@ -5856,9 +5869,10 @@ EXPORT_SYMBOL(pcie_get_speed_cap); enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev) { u32 lnkcap; + int ret; - pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); - if (lnkcap) + ret = pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); + if (!ret && lnkcap) return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4; return PCIE_LNK_WIDTH_UNKNOWN; From patchwork Mon Jul 6 09:31:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 1323503 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=co+Hhf/s; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4B0hhV2RLgz9sTC for ; Mon, 6 Jul 2020 20:32:10 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728977AbgGFKcG (ORCPT ); Mon, 6 Jul 2020 06:32:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728968AbgGFKcD (ORCPT ); Mon, 6 Jul 2020 06:32:03 -0400 Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6CF6C061794; Mon, 6 Jul 2020 03:32:02 -0700 (PDT) Received: by mail-wr1-x441.google.com with SMTP id b6so40211865wrs.11; Mon, 06 Jul 2020 03:32:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Xt1YnhbKy4/5TpAyL6iPPAj3fa0SaikOZX3SkNC5/cs=; b=co+Hhf/sWoMzEYqwa5Ain3cY7e4KSSiUOmEfwJQb1NeVGFEzn0PQP/JcP5+0va9H50 xiF1w/ly0NlcJGGE3DckK6xOfj8hhy0xZdK4G1XNW9Fe9qgUtiLuhpc5QZZOxgFVtFi+ z3IM42d42k5ldCAyVBNNp5Tj4DHavz2lQvTMkCWoqWneqaCGWGJbmOb7FggzrK7NjP8W sUDLZ8z5QWsW2Z/pTMGTrrXQ0OtVo12+cgsw6P3ychg1111TvH39V2dom/vdq+VJvfum DY+UgOBfPimdsbCrjhkEe36HGDvr+GsxvJIzDxiYkSWNmc8YPr7lwHSXOk5JKFN3uJg0 R3OA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Xt1YnhbKy4/5TpAyL6iPPAj3fa0SaikOZX3SkNC5/cs=; b=HKtlXsfD6YU84EWVc3DwUPH0pJHSH8bokYWq2JiHj4udNQT07tTa5Vi8dW8u1DrwIB EPNqLFWE0KwVfU7Hm7fI3U0NtAvG3foDbZOEzGhcXkFm147VSwPsorBi+mo6tNsxtXX5 LmppvGQ2avXbBqnVyeVpJw38xhmOi/XntDEeYDO47DOQl3mA2+I17xLhyy9svlklTVIf 1+6GKHmGJ5cbXp8l25S0tQokj6XLxXcJPgamNj+rpULgRFC2ZERLrXut/V14lRKyNK2m AJoyUSqiYaUTepHQ4Xzdrj19WEouYjjWgtRnptHQ9ewvRLU09oFhAAqfLQM42TXprswO O6YA== X-Gm-Message-State: AOAM531PQd3nX/V/ZpAq/Me0OunARJN2eXnD2gh7l4+RFxob4bmn4xxY I4Ff6DGrFkT+6PrM3duKu70nL/taR4QAHw== X-Google-Smtp-Source: ABdhPJx2eDLSW97bkw4iz1NfiA0Clo5Lgra2iobZdw5mwX70eKnoycMIu5+PnOcB1hjLfGz3+dHG/g== X-Received: by 2002:adf:f34e:: with SMTP id e14mr47656427wrp.299.1594031521641; Mon, 06 Jul 2020 03:32:01 -0700 (PDT) Received: from net.saheed (51B7C2DF.dsl.pool.telekom.hu. [81.183.194.223]) by smtp.gmail.com with ESMTPSA id 22sm24216859wmb.11.2020.07.06.03.32.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 03:32:01 -0700 (PDT) From: Saheed Olayemi Bolarinwa To: helgaas@kernel.org Cc: Bolarinwa Olayemi Saheed , bjorn@helgaas.com, skhan@linuxfoundation.org, linux-pci@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/11 RFC] PCI/ASPM: Use error return value from pcie_capability_read_*() Date: Mon, 6 Jul 2020 11:31:20 +0200 Message-Id: <20200706093121.9731-11-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20200706093121.9731-1-refactormyself@gmail.com> References: <20200706093121.9731-1-refactormyself@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bolarinwa Olayemi Saheed On failure pcie_capability_read_dword() sets it's last parameter, val to 0. However, with Patch 11/11, it is possible that val is set to ~0 on failure. This would introduce a bug because (x & x) == (~0 & x). This bug can be avoided if the return value of pcie_capability_read_dword is checked to confirm success. Check the return value of pcie_capability_read_dword() to ensure success. Suggested-by: Bjorn Helgaas Signed-off-by: Bolarinwa Olayemi Saheed --- drivers/pci/pcie/aspm.c | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index b17e5ffd31b1..32aa9d57672a 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -176,7 +176,7 @@ static void pcie_set_clkpm(struct pcie_link_state *link, int enable) static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) { - int capable = 1, enabled = 1; + int ret, capable = 1, enabled = 1; u32 reg32; u16 reg16; struct pci_dev *child; @@ -184,14 +184,14 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) /* All functions should have the same cap and state, take the worst */ list_for_each_entry(child, &linkbus->devices, bus_list) { - pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32); - if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { + ret = pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32); + if (ret || !(reg32 & PCI_EXP_LNKCAP_CLKPM)) { capable = 0; enabled = 0; break; } - pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); - if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN)) + ret = pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); + if (ret || !(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN)) enabled = 0; } link->clkpm_enabled = enabled; @@ -205,6 +205,7 @@ static bool pcie_retrain_link(struct pcie_link_state *link) struct pci_dev *parent = link->pdev; unsigned long end_jiffies; u16 reg16; + int ret; pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); reg16 |= PCI_EXP_LNKCTL_RL; @@ -222,8 +223,8 @@ static bool pcie_retrain_link(struct pcie_link_state *link) /* Wait for link training end. Break out after waiting for timeout */ end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT; do { - pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); - if (!(reg16 & PCI_EXP_LNKSTA_LT)) + ret = pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); + if (ret || !(reg16 & PCI_EXP_LNKSTA_LT)) break; msleep(1); } while (time_before(jiffies, end_jiffies)); @@ -237,7 +238,7 @@ static bool pcie_retrain_link(struct pcie_link_state *link) */ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) { - int same_clock = 1; + int ret, same_clock = 1; u16 reg16, parent_reg, child_reg[8]; struct pci_dev *child, *parent = link->pdev; struct pci_bus *linkbus = parent->subordinate; @@ -249,24 +250,24 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) BUG_ON(!pci_is_pcie(child)); /* Check downstream component if bit Slot Clock Configuration is 1 */ - pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16); - if (!(reg16 & PCI_EXP_LNKSTA_SLC)) + ret = pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16); + if (ret || !(reg16 & PCI_EXP_LNKSTA_SLC)) same_clock = 0; /* Check upstream component if bit Slot Clock Configuration is 1 */ - pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); - if (!(reg16 & PCI_EXP_LNKSTA_SLC)) + ret = pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); + if (ret || !(reg16 & PCI_EXP_LNKSTA_SLC)) same_clock = 0; /* Port might be already in common clock mode */ - pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); - if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) { + ret = pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); + if (!ret && same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) { bool consistent = true; list_for_each_entry(child, &linkbus->devices, bus_list) { - pcie_capability_read_word(child, PCI_EXP_LNKCTL, + ret = pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); - if (!(reg16 & PCI_EXP_LNKCTL_CCC)) { + if (ret || !(reg16 & PCI_EXP_LNKCTL_CCC)) { consistent = false; break; }