From patchwork Fri Dec 15 14:33:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 849195 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=monstr-eu.20150623.gappssmtp.com header.i=@monstr-eu.20150623.gappssmtp.com header.b="ubvdLKYL"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yytGk17Gcz9s7m for ; Sat, 16 Dec 2017 01:34:04 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id A77ABC21F41; Fri, 15 Dec 2017 14:33:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id ECAB9C21E31; Fri, 15 Dec 2017 14:33:53 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B2B0DC21D9F; Fri, 15 Dec 2017 14:33:52 +0000 (UTC) Received: from mail-wm0-f67.google.com (mail-wm0-f67.google.com [74.125.82.67]) by lists.denx.de (Postfix) with ESMTPS id A85B5C21E0E for ; Fri, 15 Dec 2017 14:33:50 +0000 (UTC) Received: by mail-wm0-f67.google.com with SMTP id n138so17843767wmg.2 for ; Fri, 15 Dec 2017 06:33:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monstr-eu.20150623.gappssmtp.com; s=20150623; h=reply-to:to:cc:from:subject:message-id:date:user-agent:mime-version; bh=+0q2kZysDa1Y1ImjLZf6FxVCNs2+1Kr6wGf2/z//cxQ=; b=ubvdLKYLdeS3O4JxCXJZGPark/QKufet53mAzRMPMiZVmRecTGsWU2B5HlKnULN2Hm wqUC2lINQM2yOxxTkcW7tS1JpmoPQAxdRpJsojASdiTP9DNuTfxYN0HlE55P12YqNARD Lxb7uPuBEs8MviO4paaFbz6j19kdvxEIBwqRlf+w/dOZ9EnMrbn/v+BZ5xCu7mBL6nlx 6HPYHsEgT+HWwysZcMQRUfl5dVwYwkZ9Qpup99/B0MHr1IpYUkDdwDwdcRc34/3dt2Ow QZQCXIiVDnlg9zMk+STktFnaqZ3/fI63Myy4V8WFc6A1BPwUUAVt+n8uaP+WaYUZ7Rfo VXfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:reply-to:to:cc:from:subject:message-id:date :user-agent:mime-version; bh=+0q2kZysDa1Y1ImjLZf6FxVCNs2+1Kr6wGf2/z//cxQ=; b=ZZ3eVpIYotBq0CpHHg5o+lyifBcTxzuMZUOOhaFZALK6aJxPhZV1BGKb5yDzovbjbd 9f91qg310bEDrTQm/NTifZwzxFhlPAiXkkRvI3xmrmw0Vrm4Fc/cUycv051AcdzNvAh1 SuxEXl+C+VZfVxJ2MrI8tcCsMib6jJOVNmNt5N+R69120WO0w5j15PyqX8wDOnV7OATh NxV1ApDEJfFwya8ibvKTo6BYyZBcdfHkogvDcPhXNm8uN9Td0Hav9Jm4veZLjapQYrPq K1Xyw5YjTV1fLCBrT8nQN7xyo1qvhHykpgNH4HrrBMEjU8ZwYQlG2rHFmpPKqlgAmjyh u6YA== X-Gm-Message-State: AKGB3mKp2dMcsiTxoeAH2tArPcar1BY/oVIdzwfZvmtHDYdrKvjvgB6Y uwtR8RQOlND44+UNori+3j6L/A== X-Google-Smtp-Source: ACJfBovjjAn3UMHk58XpRNmqGUM3rWY/tP59LZ73MhZN66En2YB/R1ioTMkv3Y3Q4UdnRtbMOsNVAw== X-Received: by 10.80.164.144 with SMTP id w16mr16830591edb.130.1513348430165; Fri, 15 Dec 2017 06:33:50 -0800 (PST) Received: from [74.125.140.108] ([149.199.62.254]) by smtp.gmail.com with ESMTPSA id l50sm5332224eda.85.2017.12.15.06.33.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 15 Dec 2017 06:33:49 -0800 (PST) To: Tom Rini From: Michal Simek Message-ID: <75a181eb-c26d-1711-9f7a-59895058ee5d@monstr.eu> Date: Fri, 15 Dec 2017 15:33:44 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.18 Cc: "u-boot@lists.denx.de" , Stephen Warren Subject: [U-Boot] [GIT PULL] Xilinx fixes for v2018.01-rc2 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: monstr@monstr.eu Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Hi Tom, +Stephen please pull these changes to your tree. Travis is not showing any issue. https://travis-ci.org/michalsimek-test/u-boot/builds/316577925 Buildman was also fine over all patches and tests on board looks good too. I have included one patch from Stephen which we discussed for fixing zynq_cse_qspi configuration which doesn't use HUSH. Thanks, Michal The following changes since commit 659208da4703de50826a469cbb38bf6afb938978: README: update the kernel coding style reference (2017-12-12 21:34:10 -0500) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git tags/xilinx-for-v2018.01-rc2 for you to fetch changes up to 956a1340c8677e96f9eb364fb0070c152d591a4a: test/py: Setup variables based on HUSH selection (2017-12-14 20:09:04 +0100) ---------------------------------------------------------------- Xilinx changes for v2018.01-rc2 fpga: - Enable loading bitstream via fit image for !xilinx platforms zynq: - Fix SPL SD boot mode zynqmp: - Not not reset in panic - Do not use simple allocator because of fat changes - Various dt chagnes - modeboot variable setup - Fix fpga loading on automotive devices - Fix coverity issues test: - Fix env test for !hush case - Stephen's patch ---------------------------------------------------------------- Goldschmidt Simon (1): fpga: allow programming fpga from FIT image for all FPGA drivers Javier Martinez Canillas (1): arm64: zynqmp: Add generic compatible string for I2C EEPROM Michal Simek (19): arm: zynq: Fix SPL SD boot mode arm64: zynqmp: Do not perform reset in case of panic arm64: zynqmp: Do not use SPL_SYS_MALLOC_SIMPLE allocator arm64: zynqmp: Add reference to pmu firmware node arm64: zynqmp: Add support for generic QSPI boot arm64: zynqmp: Enable SPL_CLK when SPL is enabled arm64: zynqmp: Setup modeboot variable based on bootmode arm64: zynqmp: Enable phys for zcu102 arm64: zynqmp: Enable clock command for all boards arm64: zynqmp: Remove undocumented dma properties arm64: zynqmp: Use only earlycon bootargs instead of full one arm64: zynqmp: Add missing zynq_board_read_rom_ethaddr() prototype arm64: zynqmp: Add support for zynqmp automotive silicons arm64: zynqmp: Enable misc devices arm64: zynqmp: Enable SPL ram support arm64: zynqmp: Enable fpga bitstream loading arm64: zynqmp: Enable AES command arm64: zynqmp: Enable spi flashes tools: zynqmpimage: Check return values from file functions Siva Durga Prasad Paladugu (3): arm64: zynqmp: Read boot mode register using zynqmp_mmio_read arm64: zynqmp: Dont use 4K sector erase by default for spi-flashes arm64: zynqmp: Access timestamp_ref_ctrl register only if running in el3 Stephen Warren (1): test/py: Setup variables based on HUSH selection arch/arm/Kconfig | 2 +- arch/arm/dts/zynqmp-ep108.dts | 4 ++-- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 9 --------- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 9 --------- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 9 --------- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 11 +---------- arch/arm/dts/zynqmp-zcu102-revA.dts | 20 +++++++++++--------- arch/arm/dts/zynqmp.dtsi | 3 ++- arch/arm/include/asm/arch-zynqmp/sys_proto.h | 1 + board/xilinx/zynqmp/zynqmp.c | 23 +++++++++++++++++++---- common/bootm.c | 2 +- common/image.c | 6 ++---- configs/syzygy_hub_defconfig | 2 ++ configs/topic_miami_defconfig | 2 ++ configs/topic_miamilite_defconfig | 2 ++ configs/topic_miamiplus_defconfig | 2 ++ configs/xilinx_zynqmp_ep_defconfig | 7 ++++++- configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 10 +++++++++- configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 8 +++++++- configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 15 ++++++++++++++- configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 8 +++++++- configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 10 +++++++++- configs/xilinx_zynqmp_zcu102_revA_defconfig | 10 +++++++++- configs/xilinx_zynqmp_zcu102_revB_defconfig | 10 +++++++++- configs/zynq_cc108_defconfig | 2 ++ configs/zynq_cse_qspi_defconfig | 2 ++ configs/zynq_microzed_defconfig | 2 ++ configs/zynq_picozed_defconfig | 2 ++ configs/zynq_z_turn_defconfig | 2 ++ configs/zynq_zc702_defconfig | 2 ++ configs/zynq_zc706_defconfig | 2 ++ configs/zynq_zc770_xm010_defconfig | 2 ++ configs/zynq_zc770_xm011_defconfig | 2 ++ configs/zynq_zc770_xm012_defconfig | 2 ++ configs/zynq_zc770_xm013_defconfig | 2 ++ configs/zynq_zed_defconfig | 2 ++ configs/zynq_zybo_defconfig | 2 ++ drivers/fpga/fpga.c | 9 +++++++++ drivers/fpga/xilinx.c | 13 +++++++++++++ include/configs/xilinx_zynqmp.h | 16 +++++++++++++--- include/configs/zynq-common.h | 7 ++----- include/fpga.h | 1 + test/py/tests/test_env.py | 11 ++++++++++- tools/zynqmpimage.c | 32 +++++++++++++++++++++++++++----- 44 files changed, 219 insertions(+), 81 deletions(-)