From patchwork Fri Jul 3 10:10:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Hsuan-Yu Lin X-Patchwork-Id: 1322302 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49yrMF1k88z9sQt; Fri, 3 Jul 2020 20:10:49 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1jrIeY-0003gB-UE; Fri, 03 Jul 2020 10:10:42 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1jrIeT-0003fM-MJ for kernel-team@lists.ubuntu.com; Fri, 03 Jul 2020 10:10:37 +0000 Received: from mail-pj1-f71.google.com ([209.85.216.71]) by youngberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1jrIeT-0002vO-A3 for kernel-team@lists.ubuntu.com; Fri, 03 Jul 2020 10:10:37 +0000 Received: by mail-pj1-f71.google.com with SMTP id 6so15036297pjh.1 for ; Fri, 03 Jul 2020 03:10:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DrobtoTLCbEnratIHAF81Z62XPbmIDmHWzsTUM+YP6k=; b=PCx6a0tUbtnhgvwtfNaZo1CoQd3d+A/el0++1h+4b/ui8n09s+TsdaqiqzFie+3Nwa XoRt15tyTH7UTrv6Wa8KxGxjJrloK32M4Iw+nyH8Pqtl1GWKXKXp0N22oHHDc6CE0O/p Fih83xVhmH17itotaDp09LLezgy11NYyBjaETYLZpRkf/rOkx6hD6xDC4FfI5i4TeVBW SDEsIpg/vrxdwELptz0DSdWvvZydthNF23YkxE5bUH2NK54+M0R4+pYzu1Jv4RhzQYCg 1ixbz00b0zBFdLIhyxTnQErnzp+CFQyPv/p/IXT+nvCS5+LP27N4lx88I0RJE6rfgxq+ 9X7w== X-Gm-Message-State: AOAM530xhk3U93Xgr32UJ3hr1CscKGD2MDDuL5049dM804JmnK5J0rWy LOHm8hp/Qwt77XIkQhiZnLv/jKaWjb4jwvDBBotef7oBUBDS/J7A6Wpv2wKy7Wys4h0easeUAA4 9mTMa6BwW8nlHWevSsgVAVxQqi0zv54XiwuMl/Fw3iQ== X-Received: by 2002:a17:90a:148:: with SMTP id z8mr15131858pje.197.1593771035753; Fri, 03 Jul 2020 03:10:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxBiOyMzQ3H6kswuC1chEylzjzba0PIleewpAnf9EeUCdsIvSqFVY8t5QhxOOwwccPMA10COw== X-Received: by 2002:a17:90a:148:: with SMTP id z8mr15131835pje.197.1593771035488; Fri, 03 Jul 2020 03:10:35 -0700 (PDT) Received: from dell.taipei.internal (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id d9sm11648908pgv.45.2020.07.03.03.10.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 03:10:35 -0700 (PDT) From: Hsuan-Yu Lin To: kernel-team@lists.ubuntu.com Subject: [PATCH 1/7][SRU][OEM-5.6] drm/i915/tgl: Update TC DP vswing table Date: Fri, 3 Jul 2020 18:10:25 +0800 Message-Id: <20200703101031.99125-2-shane.lin@canonical.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200703101031.99125-1-shane.lin@canonical.com> References: <20200703101031.99125-1-shane.lin@canonical.com> MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: José Roberto de Souza BugLink: https://bugs.launchpad.net/bugs/1886165 Small updates in dkl_de_emphasis_control field. BSpec: 49292 Signed-off-by: José Roberto de Souza Reviewed-by: Khaled Almahallawy Link: https://patchwork.freedesktop.org/patch/msgid/20200529232757.37832-1-jose.souza@intel.com (cherry picked from commit 250a353cd85f2d0b06ca73bd20accbe58bea8d82 drm-tip) Signed-off-by: Hsuan-Yu Lin --- drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index e7675cd5c104..8384472f42ae 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -625,11 +625,11 @@ struct tgl_dkl_phy_ddi_buf_trans { static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = { /* VS pre-emp Non-trans mV Pre-emph dB */ { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ - { 0x5, 0x0, 0x03 }, /* 0 1 400mV 3.5 dB */ - { 0x2, 0x0, 0x0b }, /* 0 2 400mV 6 dB */ + { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */ + { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */ { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ - { 0x2, 0x0, 0x03 }, /* 1 1 600mV 3.5 dB */ + { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ From patchwork Fri Jul 3 10:10:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hsuan-Yu Lin X-Patchwork-Id: 1322301 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49yrMC2fw5z9sSJ; Fri, 3 Jul 2020 20:10:47 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1jrIeZ-0003gN-58; Fri, 03 Jul 2020 10:10:43 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1jrIeV-0003fS-5Z for kernel-team@lists.ubuntu.com; Fri, 03 Jul 2020 10:10:39 +0000 Received: from mail-pl1-f200.google.com ([209.85.214.200]) by youngberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1jrIeU-0002vW-PL for kernel-team@lists.ubuntu.com; Fri, 03 Jul 2020 10:10:38 +0000 Received: by mail-pl1-f200.google.com with SMTP id r11so11554601plo.13 for ; Fri, 03 Jul 2020 03:10:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WYgsOlC0F339eBFHskAfiqdyJd1b7ANTQQsLBpxWGwk=; b=HaAjJ5xYOmH+8tT6UFIFzMDQzHKNBxOrCGF9f/DJPSLSKbkFheBgHCj5hTuFWwKL5H FRo9Ptv8cXQwdz1d6XZjWEmugwJMrFCM4DmbyW0WLgBY19KvkBFr+1V/hN/ZRtxHw/T5 QNdf84J3rIbrpFzqdeWuiTD24E4BJS+OXz8QFUzrGQKCvmmszEsGcR5vv+SYImjblA7n nK/6yRXIW6ljZ1IouZ/UAi71SV9uSWabkqtzEJFB06ZfsnA1tnQYQXPtq1XlM+l1wr65 C8ppFAkEz45anxmKhBwvTc6jMHwsIZLsuNqOftH6bTHVwb0kGVth31sxTlHYxz6N71KR tnJA== X-Gm-Message-State: AOAM533vj228pc9AoVOq1iv4xuk4Hnigc2RDizJtAx8Y/DuTUnYYICVW qcWZ8vFDS1yM8I0awMLAaVOmvwkePpw/taHpoZXkfFNxtCofOqFheDeGqQzev5fB7PAA+vSKMNy q54aQ26GWEx+4RMGu+faolf6029U/sOvXTFOH2SGirg== X-Received: by 2002:a17:902:8d90:: with SMTP id v16mr31475656plo.189.1593771037077; Fri, 03 Jul 2020 03:10:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyh8qliEDo9EnIqneRRiUtyd26miu9fd2Npjjn5T1qtdEXzQTf0Q5sLx3B1FT6UrbilC/aZDA== X-Received: by 2002:a17:902:8d90:: with SMTP id v16mr31475635plo.189.1593771036747; Fri, 03 Jul 2020 03:10:36 -0700 (PDT) Received: from dell.taipei.internal (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id d9sm11648908pgv.45.2020.07.03.03.10.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 03:10:36 -0700 (PDT) From: Hsuan-Yu Lin To: kernel-team@lists.ubuntu.com Subject: [PATCH 2/7][SRU][OEM-5.6] drm/i915/tgl: Implement WA_16011163337 Date: Fri, 3 Jul 2020 18:10:26 +0800 Message-Id: <20200703101031.99125-3-shane.lin@canonical.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200703101031.99125-1-shane.lin@canonical.com> References: <20200703101031.99125-1-shane.lin@canonical.com> MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Clint Taylor BugLink: https://bugs.launchpad.net/bugs/1886165 Set GS Timer to 224. Combine with Wa_1604555607 due to register FF_MODE2 not being able to be read. V2: Math issue fixed Cc: Chris Wilson Cc: Caz Yokoyama Cc: Matt Atwood Signed-off-by: Clint Taylor Acked-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20200603221150.14745-1-clinton.a.taylor@intel.com (cherry picked from commit 84f9cbf335809412704f99b5fb9b737ef7cb8e89 drm-tip) Signed-off-by: Hsuan-Yu Lin --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 +++++++---- drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 576d1299347c..1514962cb7d1 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -591,11 +591,14 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, * Wa_1604555607:gen12 and Wa_1608008084:gen12 * FF_MODE2 register will return the wrong value when read. The default * value for this register is zero for all fields and there are no bit - * masks. So instead of doing a RMW we should just write the TDS timer - * value for Wa_1604555607. + * masks. So instead of doing a RMW we should just write the GS Timer + * and TDS timer values for Wa_1604555607 and Wa_16011163337. */ - wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, - FF_MODE2_TDS_TIMER_128, 0); + wa_add(wal, + FF_MODE2, + FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK, + FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128, + 0); /* WaDisableGPGPUMidThreadPreemption:tgl */ WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8874780456db..3386a0fa414b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8027,6 +8027,8 @@ enum { #define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) #define FF_MODE2 _MMIO(0x6604) +#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24) +#define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224) #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16) #define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4) From patchwork Fri Jul 3 10:10:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Hsuan-Yu Lin X-Patchwork-Id: 1322303 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49yrMG0QGbz9sRW; Fri, 3 Jul 2020 20:10:50 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1jrIea-0003hM-Bs; Fri, 03 Jul 2020 10:10:44 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1jrIeW-0003fl-Hn for kernel-team@lists.ubuntu.com; Fri, 03 Jul 2020 10:10:40 +0000 Received: from mail-pl1-f197.google.com ([209.85.214.197]) by youngberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1jrIeW-0002vm-5M for kernel-team@lists.ubuntu.com; Fri, 03 Jul 2020 10:10:40 +0000 Received: by mail-pl1-f197.google.com with SMTP id w13so6348825plp.8 for ; Fri, 03 Jul 2020 03:10:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vzVLfSLXAnpXiz8VLu+z66ZV+Nfqcdqve7eztW/htrs=; b=V0pSQhTjcwE+BhgWkbqHH39J2+eUsAqCe/X2kYkAznTkHHNNwnaQnVhV2X3cLgMrjm wem7oyyChz1in0nAq3MuyIgNpQWWNUXNa9ZVbVZGd5AVgV49JfmC0zqYP7qpfPYEAsvq r7lLXvIiOAjep0KuynCc+inmGTFTIqoTotXrEYCWnB99lXoLe4g4c9E5tuP7QaQCMRy3 rD/odslwyWo4Gvb/g7V8fVnn9YIVMACDpwyg3m0efNZ4NdnamaD2zR2rivsU7Kom5rka +NRQDBjrr1D0IXn/lPNJmDbHFDebfhtSjtNsQC40Coec4eZAPyyPEbAnLeu6bJxkr+A1 2Jfw== X-Gm-Message-State: AOAM5326jH7co7sjI85ifmQR2Fp1L8p7MaG1yLNxNZK/rrvFAJa7S2MN pjxCnEyYzR94p84IFChndMIu9c+y/PDWBJe7ltkubWS5riI7c9Zvo+GYHBqC09N4mMIzq3Ft346 /q6Am5o52kqUaWd4GpJz24uMop4eqz+XmPm3G1ERYrg== X-Received: by 2002:a63:c603:: with SMTP id w3mr28053363pgg.284.1593771038627; Fri, 03 Jul 2020 03:10:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw38Z+gy3edwOzEKlSxtUZtnVjvUlRVHAqGxEWHurPgOYchFP6QFq5PvJF4UHObGJT4QinPdQ== X-Received: by 2002:a63:c603:: with SMTP id w3mr28053342pgg.284.1593771038253; Fri, 03 Jul 2020 03:10:38 -0700 (PDT) Received: from dell.taipei.internal (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id d9sm11648908pgv.45.2020.07.03.03.10.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 03:10:37 -0700 (PDT) From: Hsuan-Yu Lin To: kernel-team@lists.ubuntu.com Subject: [PATCH 3/7][SRU][OEM-5.6] UBUNTU: SAUCE: drm/i915/bios: add intel_bios_hdmi_level_shift() Date: Fri, 3 Jul 2020 18:10:27 +0800 Message-Id: <20200703101031.99125-4-shane.lin@canonical.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200703101031.99125-1-shane.lin@canonical.com> References: <20200703101031.99125-1-shane.lin@canonical.com> MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Jani Nikula BugLink: https://bugs.launchpad.net/bugs/1886165 Don't access i915->vbt.ddi_port_info[] directly. Reviewed-by: Ville Syrjälä Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/da8ca144020fe165af33992661568d0586a2fdeb.1579270868.git.jani.nikula@intel.com (cherry picked from commit 0aed3bdede66ae5febfb4d8ab52990e370ce6567 drm-tip) Signed-off-by: Hsuan-Yu Lin --- drivers/gpu/drm/i915/display/intel_bios.c | 16 ++++++++++++++++ drivers/gpu/drm/i915/display/intel_bios.h | 2 ++ drivers/gpu/drm/i915/display/intel_ddi.c | 14 ++++++-------- 3 files changed, 24 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index aea49ef20661..ca0b851405aa 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -2583,3 +2583,19 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, return aux_ch; } + +int intel_bios_max_tmds_clock(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + + return i915->vbt.ddi_port_info[encoder->port].max_tmds_clock; +} + +int intel_bios_hdmi_level_shift(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + const struct ddi_vbt_port_info *info = + &i915->vbt.ddi_port_info[encoder->port]; + + return info->hdmi_level_shift_set ? info->hdmi_level_shift : -1; +} diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h index d6a0c29d37ac..c6cc413bf8ec 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.h +++ b/drivers/gpu/drm/i915/display/intel_bios.h @@ -247,5 +247,7 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, enum port bool intel_bios_get_dsc_params(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, int dsc_max_bpc); +int intel_bios_max_tmds_clock(struct intel_encoder *encoder); +int intel_bios_hdmi_level_shift(struct intel_encoder *encoder); #endif /* _INTEL_BIOS_H_ */ diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 8384472f42ae..1e8a145188d9 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -988,11 +988,11 @@ tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, return tgl_combo_phy_ddi_translations_dp_hbr; } -static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) +static int intel_ddi_hdmi_level(struct intel_encoder *encoder) { - struct ddi_vbt_port_info *port_info = &dev_priv->vbt.ddi_port_info[port]; + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); int n_entries, level, default_entry; - enum phy phy = intel_port_to_phy(dev_priv, port); + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); if (INTEL_GEN(dev_priv) >= 12) { if (intel_phy_is_combo(dev_priv, phy)) @@ -1032,9 +1032,8 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por if (WARN_ON_ONCE(n_entries == 0)) return 0; - if (port_info->hdmi_level_shift_set) - level = port_info->hdmi_level_shift; - else + level = intel_bios_hdmi_level_shift(encoder); + if (level < 0) level = default_entry; if (WARN_ON_ONCE(level >= n_entries)) @@ -3721,8 +3720,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum port port = encoder->port; - int level = intel_ddi_hdmi_level(dev_priv, port); + int level = intel_ddi_hdmi_level(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); From patchwork Fri Jul 3 10:10:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Hsuan-Yu Lin X-Patchwork-Id: 1322306 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49yrMK4tbKz9sSy; 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[61.220.137.37]) by smtp.gmail.com with ESMTPSA id d9sm11648908pgv.45.2020.07.03.03.10.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 03:10:39 -0700 (PDT) From: Hsuan-Yu Lin To: kernel-team@lists.ubuntu.com Subject: [PATCH 4/7][SRU][OEM-5.6] drm/i915/tgl: Add HBR and HBR2+ voltage swing table Date: Fri, 3 Jul 2020 18:10:28 +0800 Message-Id: <20200703101031.99125-5-shane.lin@canonical.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200703101031.99125-1-shane.lin@canonical.com> References: <20200703101031.99125-1-shane.lin@canonical.com> MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: José Roberto de Souza BugLink: https://bugs.launchpad.net/bugs/1886165 As latest update we have now 2 voltage swing tables for DP over DKL PHY with only one difference in Level 0 pre-emphasis 3. So with 2 tables for DP is time to have one single function to return all DKL voltage swing tables. BSpec: 49292 Cc: Khaled Almahallawy Signed-off-by: José Roberto de Souza Tested-by: Khaled Almahallawy Reviewed-by: Khaled Almahallawy Link: https://patchwork.freedesktop.org/patch/msgid/20200602205424.138143-1-jose.souza@intel.com (cherry picked from commit 9fa6769952ee14250bb7107a2ec66062d2ccae1e drm-tip) Signed-off-by: Hsuan-Yu Lin --- drivers/gpu/drm/i915/display/intel_ddi.c | 50 ++++++++++++++++++++---- 1 file changed, 42 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 1e8a145188d9..8284e600ea98 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -627,6 +627,20 @@ static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = { { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */ { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ + { 0x0, 0x0, 0x18 }, /* 0 3 400mV 9.5 dB */ + { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ + { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ + { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ + { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ + { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ + { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ +}; + +static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans_hbr2[] = { + /* VS pre-emp Non-trans mV Pre-emph dB */ + { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ + { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */ + { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */ { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ @@ -988,6 +1002,22 @@ tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, return tgl_combo_phy_ddi_translations_dp_hbr; } +static const struct tgl_dkl_phy_ddi_buf_trans * +tgl_get_dkl_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, + int *n_entries) +{ + if (type == INTEL_OUTPUT_HDMI) { + *n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); + return tgl_dkl_phy_hdmi_ddi_trans; + } else if (rate > 270000) { + *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2); + return tgl_dkl_phy_dp_ddi_trans_hbr2; + } + + *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); + return tgl_dkl_phy_dp_ddi_trans; +} + static int intel_ddi_hdmi_level(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -999,7 +1029,8 @@ static int intel_ddi_hdmi_level(struct intel_encoder *encoder) tgl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0, &n_entries); else - n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); + tgl_get_dkl_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0, + &n_entries); default_entry = n_entries - 1; } else if (INTEL_GEN(dev_priv) == 11) { if (intel_phy_is_combo(dev_priv, phy)) @@ -2468,7 +2499,8 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) tgl_get_combo_buf_trans(dev_priv, encoder->type, intel_dp->link_rate, &n_entries); else - n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); + tgl_get_dkl_buf_trans(dev_priv, encoder->type, + intel_dp->link_rate, &n_entries); } else if (INTEL_GEN(dev_priv) == 11) { if (intel_phy_is_combo(dev_priv, phy)) icl_get_combo_buf_trans(dev_priv, encoder->type, @@ -2931,15 +2963,17 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock, enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations; u32 n_entries, val, ln, dpcnt_mask, dpcnt_val; + int rate = 0; - if (encoder->type == INTEL_OUTPUT_HDMI) { - n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); - ddi_translations = tgl_dkl_phy_hdmi_ddi_trans; - } else { - n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); - ddi_translations = tgl_dkl_phy_dp_ddi_trans; + if (encoder->type != INTEL_OUTPUT_HDMI) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + rate = intel_dp->link_rate; } + ddi_translations = tgl_get_dkl_buf_trans(dev_priv, encoder->type, rate, + &n_entries); + if (level >= n_entries) level = n_entries - 1; From patchwork Fri Jul 3 10:10:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Hsuan-Yu Lin X-Patchwork-Id: 1322304 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; 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[61.220.137.37]) by smtp.gmail.com with ESMTPSA id d9sm11648908pgv.45.2020.07.03.03.10.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 03:10:40 -0700 (PDT) From: Hsuan-Yu Lin To: kernel-team@lists.ubuntu.com Subject: [PATCH 5/7][SRU][OEM-5.6] drm/i915/dc3co: Avoid full modeset when EXITLINE needs to be changed Date: Fri, 3 Jul 2020 18:10:29 +0800 Message-Id: <20200703101031.99125-6-shane.lin@canonical.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200703101031.99125-1-shane.lin@canonical.com> References: <20200703101031.99125-1-shane.lin@canonical.com> MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: José Roberto de Souza BugLink: https://bugs.launchpad.net/bugs/1886165 A recent change in BSpec allow us to change EXTLINE while transcoder is enabled so this allow us to change it even when doing the first fastset after taking over previous hardware state set by BIOS. BIOS don't enable PSR, so if sink supports PSR it will be enabled on the first fastset, so moving the EXTLINE compute and set to PSR flows allow us to simplfy a bunch of code. This will save a lot of time in all the IGT tests that uses CRC, as when PSR2 is enabled CRCs are not generated, so we switch to PSR1, so the previous code would compute dc3co_exitline=0 causing a full modeset that would shutdown pipe, enable and train link. v2: only programming EXTLINE when DC3CO is enabled BSpec: 49196 Cc: Imre Deak Cc: Anshuman Gupta Reviewed-by: Anshuman Gupta Signed-off-by: José Roberto de Souza Link: https://patchwork.freedesktop.org/patch/msgid/20200122182617.18597-2-jose.souza@intel.com (cherry picked from commit c5c772cf8d7cb68701b1c7fb9956857e646ae4b1 drm-tip) Signed-off-by: Hsuan-Yu Lin --- drivers/gpu/drm/i915/display/intel_ddi.c | 86 -------------------- drivers/gpu/drm/i915/display/intel_display.c | 1 - drivers/gpu/drm/i915/display/intel_psr.c | 45 ++++++++++ 3 files changed, 45 insertions(+), 87 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 8284e600ea98..23d39f15632b 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3439,86 +3439,6 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, POSTING_READ(intel_dp->regs.dp_tp_ctl); } -static void -tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state *cstate) -{ - struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev); - u32 val; - - if (!cstate->dc3co_exitline) - return; - - val = I915_READ(EXITLINE(cstate->cpu_transcoder)); - val &= ~(EXITLINE_MASK | EXITLINE_ENABLE); - I915_WRITE(EXITLINE(cstate->cpu_transcoder), val); -} - -static void -tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state *cstate) -{ - u32 val, exit_scanlines; - struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev); - - if (!cstate->dc3co_exitline) - return; - - exit_scanlines = cstate->dc3co_exitline; - exit_scanlines <<= EXITLINE_SHIFT; - val = I915_READ(EXITLINE(cstate->cpu_transcoder)); - val &= ~(EXITLINE_MASK | EXITLINE_ENABLE); - val |= exit_scanlines; - val |= EXITLINE_ENABLE; - I915_WRITE(EXITLINE(cstate->cpu_transcoder), val); -} - -static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder, - struct intel_crtc_state *cstate) -{ - u32 exit_scanlines; - struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev); - u32 crtc_vdisplay = cstate->hw.adjusted_mode.crtc_vdisplay; - - cstate->dc3co_exitline = 0; - - if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)) - return; - - /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/ - if (to_intel_crtc(cstate->uapi.crtc)->pipe != PIPE_A || - encoder->port != PORT_A) - return; - - if (!cstate->has_psr2 || !cstate->hw.active) - return; - - /* - * DC3CO Exit time 200us B.Spec 49196 - * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 - */ - exit_scanlines = - intel_usecs_to_scanlines(&cstate->hw.adjusted_mode, 200) + 1; - - if (WARN_ON(exit_scanlines > crtc_vdisplay)) - return; - - cstate->dc3co_exitline = crtc_vdisplay - exit_scanlines; - DRM_DEBUG_KMS("DC3CO exit scanlines %d\n", cstate->dc3co_exitline); -} - -static void tgl_dc3co_exitline_get_config(struct intel_crtc_state *crtc_state) -{ - u32 val; - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); - - if (INTEL_GEN(dev_priv) < 12) - return; - - val = I915_READ(EXITLINE(crtc_state->cpu_transcoder)); - - if (val & EXITLINE_ENABLE) - crtc_state->dc3co_exitline = val & EXITLINE_MASK; -} - static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) @@ -3531,7 +3451,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder, int level = intel_ddi_dp_level(intel_dp); enum transcoder transcoder = crtc_state->cpu_transcoder; - tgl_set_psr2_transcoder_exitline(crtc_state); intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count, is_mst); @@ -3915,7 +3834,6 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, dig_port->ddi_io_power_domain); intel_ddi_clk_disable(encoder); - tgl_clear_psr2_transcoder_exitline(old_crtc_state); } static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder, @@ -4509,9 +4427,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder, break; } - if (encoder->type == INTEL_OUTPUT_EDP) - tgl_dc3co_exitline_get_config(pipe_config); - pipe_config->has_audio = intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); @@ -4593,7 +4508,6 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder, ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); } else { ret = intel_dp_compute_config(encoder, pipe_config, conn_state); - tgl_dc3co_exitline_compute_config(encoder, pipe_config); } if (ret) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a540056d93e9..eb6942604801 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13674,7 +13674,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(pixel_multiplier); PIPE_CONF_CHECK_I(output_format); - PIPE_CONF_CHECK_I(dc3co_exitline); PIPE_CONF_CHECK_BOOL(has_hdmi_sink); if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index fb9eb777a0c6..8f50b249175d 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -604,6 +604,36 @@ static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv) tgl_psr2_disable_dc3co(dev_priv); } +static void +tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state) +{ + const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + u32 exit_scanlines; + + if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)) + return; + + /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/ + if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A || + dig_port->base.port != PORT_A) + return; + + /* + * DC3CO Exit time 200us B.Spec 49196 + * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 + */ + exit_scanlines = + intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; + + if (WARN_ON(exit_scanlines > crtc_vdisplay)) + return; + + crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; +} + static bool intel_psr2_config_valid(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state) { @@ -675,6 +705,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } + tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); return true; } @@ -792,6 +823,20 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, I915_WRITE(EDP_PSR_DEBUG(dev_priv->psr.transcoder), mask); psr_irq_control(dev_priv); + + if (crtc_state->dc3co_exitline) { + u32 val; + + /* + * TODO: if future platforms supports DC3CO in more than one + * transcoder, EXITLINE will need to be unset when disabling PSR + */ + val = I915_READ(EXITLINE(cpu_transcoder)); + val &= ~EXITLINE_MASK; + val |= crtc_state->dc3co_exitline << EXITLINE_SHIFT; + val |= EXITLINE_ENABLE; + I915_WRITE(EXITLINE(cpu_transcoder), val); + } } static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, From patchwork Fri Jul 3 10:10:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Hsuan-Yu Lin X-Patchwork-Id: 1322307 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[61.220.137.37]) by smtp.gmail.com with ESMTPSA id d9sm11648908pgv.45.2020.07.03.03.10.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 03:10:41 -0700 (PDT) From: Hsuan-Yu Lin To: kernel-team@lists.ubuntu.com Subject: [PATCH 6/7][SRU][OEM-5.6] drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders Date: Fri, 3 Jul 2020 18:10:30 +0800 Message-Id: <20200703101031.99125-7-shane.lin@canonical.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200703101031.99125-1-shane.lin@canonical.com> References: <20200703101031.99125-1-shane.lin@canonical.com> MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Imre Deak BugLink: https://bugs.launchpad.net/bugs/1886165 MST encoders must use the master MST transcoder's DP_TP_STATUS and DP_TP_CONTROL registers. Atm, during the HW readout of an MST encoder connected to a slave transcoder we reset these register addresses in intel_dp::regs.dp_tp_* to the slave transcoder's DP_TP_* register addresses incorrectly; fix this. One example where the above overwite happens is the encoder HW state validation after enabling multiple streams; see intel_dp_mst_enc_get_config(). After that during disabling any stream we'll get a 'Timed out waiting for ACT sent when disabling' error, due to reading from the incorrect DP_TP_STATUS register. This change replaces https://patchwork.freedesktop.org/patch/369577/?series=78193&rev=1 which just papered over the problem. v2: - Correct the failure scenario in the commit log. (José) Cc: Ville Syrjälä Cc: José Roberto de Souza Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä Reviewed-by: José Roberto de Souza Link: https://patchwork.freedesktop.org/patch/msgid/20200616211146.23027-1-imre.deak@intel.com (cherry picked from commit f153478de4b259afb0a383de83e817b4c237401b drm-tip) Signed-off-by: Hsuan-Yu Lin --- drivers/gpu/drm/i915/display/intel_ddi.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 23d39f15632b..bd79dff36526 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4328,11 +4328,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder, if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) return; - if (INTEL_GEN(dev_priv) >= 12) { - intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(cpu_transcoder); - intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(cpu_transcoder); - } - intel_dsc_get_config(encoder, pipe_config); temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); @@ -4427,6 +4422,16 @@ void intel_ddi_get_config(struct intel_encoder *encoder, break; } + if (INTEL_GEN(dev_priv) >= 12) { + enum transcoder transcoder = + intel_dp_mst_is_slave_trans(pipe_config) ? + pipe_config->mst_master_transcoder : + pipe_config->cpu_transcoder; + + intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); + intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); + } + pipe_config->has_audio = intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); From patchwork Fri Jul 3 10:10:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hsuan-Yu Lin X-Patchwork-Id: 1322308 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49yrMP0hCBz9sTR; Fri, 3 Jul 2020 20:10:56 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1jrIeh-0003n9-N9; Fri, 03 Jul 2020 10:10:51 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1jrIeb-0003iU-RA for kernel-team@lists.ubuntu.com; Fri, 03 Jul 2020 10:10:45 +0000 Received: from mail-pj1-f72.google.com ([209.85.216.72]) by youngberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1jrIeb-0002wO-Du for kernel-team@lists.ubuntu.com; Fri, 03 Jul 2020 10:10:45 +0000 Received: by mail-pj1-f72.google.com with SMTP id a6so11880174pjd.4 for ; Fri, 03 Jul 2020 03:10:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qS5kFmoERJpo09LVaKlJVtDVgxHitpe52RuHvq/Mhbo=; b=gLA5IUhW7+O916OQ6NJsFhBK6P4JudGGXhVvCBltd614tA8K9gDtb/uH3WP2YJrzAJ dpmrR3PKHTvEFr1pDQ+/QGOj1W8cTIcb9vvkttES27nKkHwUnBV/+ZkMgl5kB2yxCyic YIQD13LrN8NDYRtyJBybqt+RnfsTu3Vxd+2820oUeq8bMjJs/7U9uHUjhuRCNK1wB9qi FXLWmIP+hyXfXWEhrp/Melv80I4WzxryhGCMpfacjP/C4Vg9KjTYwliuNggdT2fvRlCT M2189DouZH0vCRlc/7xj6s5vOXC5gr6ns/WSSwUUeS5H0oLQkpManmohIyX2Rn5BNuCu VgpA== X-Gm-Message-State: AOAM530j1SL8rbE3yAXrhFzBkackCrPnuthAJ2fNu0YRyBRRs5PRbnBG adW1YkPvA6kODwAWaK15MWWZvuOqodH5Rl445cYX8mqqdqWB9TGZOMtm/j/FgxjDtRF9TkFn49p cYDgu8g8L6UPay/gwAUHeUisQD4RbYRl794rYaG56Ew== X-Received: by 2002:a63:1f09:: with SMTP id f9mr27817299pgf.324.1593771043890; Fri, 03 Jul 2020 03:10:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw9c6ItZqVGN+Mc+WFKv63krIbtv2m0heZ/sDm3K3RXuzcZTdIp8eHTai7rNg6opJR/ik64aQ== X-Received: by 2002:a63:1f09:: with SMTP id f9mr27817276pgf.324.1593771043502; Fri, 03 Jul 2020 03:10:43 -0700 (PDT) Received: from dell.taipei.internal (61-220-137-37.HINET-IP.hinet.net. [61.220.137.37]) by smtp.gmail.com with ESMTPSA id d9sm11648908pgv.45.2020.07.03.03.10.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 03:10:43 -0700 (PDT) From: Hsuan-Yu Lin To: kernel-team@lists.ubuntu.com Subject: [PATCH 7/7][SRU][OEM-5.6] drm/i915/tgl+: Fix TBT DPLL fractional divider for 38.4MHz ref clock Date: Fri, 3 Jul 2020 18:10:31 +0800 Message-Id: <20200703101031.99125-8-shane.lin@canonical.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200703101031.99125-1-shane.lin@canonical.com> References: <20200703101031.99125-1-shane.lin@canonical.com> MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Imre Deak BugLink: https://bugs.launchpad.net/bugs/1886165 When the reference clock is 38.4MHz, using the current TBT PLL fractional divider value results in a slightly off TBT link frequency. This causes an endless loop of link training success followed by a bad link signaling and retraining at least on a Dell WD19TB TBT dock. The workaround provided by the HW team is to divide the fractional divider value by two. This fixed the link training problem on the ThinkPad dock. The same workaround is needed on some EHL platforms and for combo PHY PLLs, these will be addressed in a follow-up. Bspec: 49204 References: HSDES#22010772725 References: HSDES#14011861142 Reported-and-tested-by: Khaled Almahallawy Signed-off-by: Imre Deak Reviewed-by: Khaled Almahallawy Link: https://patchwork.freedesktop.org/patch/msgid/20200629185848.20550-1-imre.deak@intel.com (cherry picked from commit 09eac8277262bea10a52159f90dcb55beffe0714 drm-tip) Signed-off-by: Hsuan-Yu Lin --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index c75e34d87111..6e336513d874 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -2547,6 +2547,15 @@ static const struct skl_wrpll_params tgl_tbt_pll_19_2MHz_values = { static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = { .dco_integer = 0x43, .dco_fraction = 0x4000, /* the following params are unused */ +}; + +/* + * Display WA #22010492432: tgl + * Divide the nominal .dco_fraction value by 2. + */ +static const struct skl_wrpll_params tgl_tbt_pll_38_4MHz_values = { + .dco_integer = 0x54, .dco_fraction = 0x1800, + /* the following params are unused */ .pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0, }; @@ -2583,12 +2592,14 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state, MISSING_CASE(dev_priv->cdclk.hw.ref); /* fall-through */ case 19200: - case 38400: *pll_params = tgl_tbt_pll_19_2MHz_values; break; case 24000: *pll_params = tgl_tbt_pll_24MHz_values; break; + case 38400: + *pll_params = tgl_tbt_pll_38_4MHz_values; + break; } } else { switch (dev_priv->cdclk.hw.ref) {