From patchwork Thu Jul 2 10:13:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 1321224 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=07oSXWMf; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49yDWG3wMWz9sTN for ; Thu, 2 Jul 2020 20:15:38 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728448AbgGBKPc (ORCPT ); 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d="scan'208";a="85979770" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 02 Jul 2020 03:14:35 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 2 Jul 2020 03:14:35 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 2 Jul 2020 03:14:12 -0700 From: Lars Povlsen To: Mark Brown , Peter Rosin , "Rob Herring" CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Serge Semin , Serge Semin Subject: [PATCH v3 5/8] dt-bindings: snps,dw-apb-ssi: Add sparx5 support, plus snps,rx-sample-delay-ns property Date: Thu, 2 Jul 2020 12:13:28 +0200 Message-ID: <20200702101331.26375-6-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200702101331.26375-1-lars.povlsen@microchip.com> References: <20200702101331.26375-1-lars.povlsen@microchip.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This has the following changes for the snps,dw-apb-ss DT bindings: - Add "microchip,sparx5-spi" as the compatible for the Sparx5 SoC controller - Add the property "mux-controls" for the above compatible string - Add the property "snps,rx-sample-delay-ns" for SPI slaves Signed-off-by: Lars Povlsen --- .../bindings/spi/snps,dw-apb-ssi.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) -- 2.27.0 diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index c62cbe79f00dd..9d9208391fae3 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -36,6 +36,8 @@ properties: - mscc,ocelot-spi - mscc,jaguar2-spi - const: snps,dw-apb-ssi + - description: Microchip Sparx5 SoC SPI Controller + const: microchip,sparx5-spi - description: Amazon Alpine SPI Controller const: amazon,alpine-dw-apb-ssi - description: Renesas RZ/N1 SPI Controller @@ -93,6 +95,19 @@ properties: - const: tx - const: rx +if: + properties: + compatible: + contains: + const: microchip,sparx5-spi + +then: + properties: + mux-controls: + description: A mux controller node for selecting SPI bus interface. + maxItems: 1 + $ref: '/schemas/types.yaml#/definitions/phandle' + patternProperties: "^.*@[0-9a-f]+$": type: object @@ -107,6 +122,14 @@ patternProperties: spi-tx-bus-width: const: 1 + snps,rx-sample-delay-ns: + description: SPI Rx sample delay offset, unit is nanoseconds. + The delay from the default sample time before the actual + sample of the rxd input signal occurs. The "rx_sample_delay" + is an optional feature of the designware controller, and the + upper limit is also subject to controller configuration. + $ref: /schemas/types.yaml#/definitions/uint32 + unevaluatedProperties: false required: @@ -129,5 +152,10 @@ examples: num-cs = <2>; cs-gpios = <&gpio0 13 0>, <&gpio0 14 0>; + spi-flash@1 { + compatible = "spi-nand"; + reg = <1>; + snps,rx-sample-delay-ns = <7>; + }; }; ... From patchwork Thu Jul 2 10:13:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 1321222 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=eibkzKtQ; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49yDVX63B6z9sDX for ; Thu, 2 Jul 2020 20:15:00 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728235AbgGBKOy (ORCPT ); Thu, 2 Jul 2020 06:14:54 -0400 Received: from esa1.microchip.iphmx.com ([68.232.147.91]:55429 "EHLO esa1.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728404AbgGBKOl (ORCPT ); Thu, 2 Jul 2020 06:14:41 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1593684881; x=1625220881; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=p8ti72N/kPmTe//KJjZaDbS1jxKg9TXG3r5s9TRcE6E=; b=eibkzKtQYY/B3FBSX4vWv0yieY1wikVNhjjUQ503v9cfL0LxZ4nX+zKh mMoC22O+eqp+i+JecvFcPdBxF8nmUEBxNqKDmnJkCPzMQ0SPicdIRyWdq RO6C2+mM7tlTwQhxmjQjN1WXzheQ6g0biEfqPS07RuezNChy0AGTv9mk3 BptWyFhXcb3HDJIKXPoko1VKk7iHYsZS4VSRdYfsyvte7CJB9Xb3MmbJV 3Fv63I5guiQTmVzyjFW91GjtSornzkZx3/pQvs4gM6OGveZM9zmbRGjdh yAD0BF9CVY7Rk7ce6qkyeR6P03/BESC/kbMecFAAUNkN1TPbrkDRvs/iQ w==; IronPort-SDR: FCIeI9nI6414nJ7ksSRxJS2d4awbwnDfmW5mcNChBuvks4bbmqF2IsOPpo6eXjXRwdRRxjSmaR KAoH4M0zfg3ll5n7w3zPaD7UkhezRadn/zdwKLcZrkUF9WPBU7R8GAeXu42Eq7B4uTJjQ16/F1 IMXoeQNi7vqXj69PGAHVeMMibjwiw2sBBJ6bYWEs4+lfWVUjszomyASpWoSXACRi3nlu/a8zkb 2lGs0UoRbWk8LIZ3cxRuzrKyo7uFG3+VJmiA5YeeVRQc9x16EJAbrRqaoPyF4auOXyJwg2/RpM 2zY= X-IronPort-AV: E=Sophos;i="5.75,304,1589266800"; d="scan'208";a="85979780" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 02 Jul 2020 03:14:40 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 2 Jul 2020 03:14:40 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 2 Jul 2020 03:14:17 -0700 From: Lars Povlsen To: Mark Brown , Peter Rosin , "Rob Herring" CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Serge Semin , Serge Semin Subject: [PATCH v3 6/8] dt-bindings: microchip,sparx5-spi-mux: Add Sparx5 SPI mux driver bindings Date: Thu, 2 Jul 2020 12:13:29 +0200 Message-ID: <20200702101331.26375-7-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200702101331.26375-1-lars.povlsen@microchip.com> References: <20200702101331.26375-1-lars.povlsen@microchip.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Microchip Sparx5 SPI controller has two bus segments, and use this mux to control the bus interface mapping for any chip selects. This decribes the bindings used to configure the mux driver. Signed-off-by: Lars Povlsen --- .../mux/microchip,sparx5-spi-mux.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/mux/microchip,sparx5-spi-mux.yaml -- 2.27.0 diff --git a/Documentation/devicetree/bindings/mux/microchip,sparx5-spi-mux.yaml b/Documentation/devicetree/bindings/mux/microchip,sparx5-spi-mux.yaml new file mode 100644 index 0000000000000..b0ce3b15a69e5 --- /dev/null +++ b/Documentation/devicetree/bindings/mux/microchip,sparx5-spi-mux.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mux/microchip,sparx5-spi-mux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Sparx5 SPI mux + +maintainers: + - Lars Povlsen + +description: | + The Microchip Sparx5 SPI controller has two bus segments. In order + to switch between the appropriate bus for any given SPI slave + (defined by a chip select), this mux driver is used. The device tree + node for the mux will define the bus mapping for any chip + selects. The default bus mapping for any chip select is "0", such + that only non-default mappings need to be explicitly defined. + +properties: + compatible: + enum: + - microchip,sparx5-spi-mux + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#mux-control-cells': + const: 0 + +required: + - compatible + +additionalProperties: false + +patternProperties: + "^mux@[0-9a-f]$": + type: object + + properties: + reg: + description: + Chip select to define bus mapping for. + minimum: 0 + maximum: 15 + + microchip,bus-interface: + description: + The bus interface to use for this chip select. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + required: + - reg + - microchip,bus-interface + +examples: + - | + mux: mux-controller { + compatible = "microchip,sparx5-spi-mux"; + #address-cells = <1>; + #size-cells = <0>; + #mux-control-cells = <0>; + mux@e { + reg = <14>; + microchip,bus-interface = <1>; + }; + };