From patchwork Sat Jun 27 20:00:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dennis Gilmore X-Patchwork-Id: 1318428 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256 header.s=mimecast20190719 header.b=UUrtem30; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49vPkd2lCRz9sRW for ; Sun, 28 Jun 2020 06:00:39 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0ED3A819F3; Sat, 27 Jun 2020 22:00:33 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.b="UUrtem30"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 33F0B81260; Sat, 27 Jun 2020 22:00:31 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from us-smtp-delivery-1.mimecast.com (us-smtp-2.mimecast.com [205.139.110.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id DD4E781260 for ; Sat, 27 Jun 2020 22:00:27 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dgilmore@redhat.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1593288026; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=J13AFTlngnrFg3CkxA/tXZ0T/fWMEtJKbNVeNcNHK9Y=; b=UUrtem30C+zkuDDJCHy7LNv7luTr9AbxSnjhEVNx2Cfb1+vER5qxlaQ9JE2d4DU3IzBELZ Z7YpiuZwpDTRWJBC/uDcq7crL/ns0iwij0rDycCa8AP/aPaRZWfEJP8FaqvMUWiM0Dt/N7 PA0+boWdg9vFiSPN1YCnjgh+d5zMcr0= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-224-FD4GkgRTOrapwAcp4eRGdA-1; Sat, 27 Jun 2020 16:00:22 -0400 X-MC-Unique: FD4GkgRTOrapwAcp4eRGdA-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 7AF37464; Sat, 27 Jun 2020 20:00:21 +0000 (UTC) Received: from anubis.ausil.us.com (ovpn-112-153.rdu2.redhat.com [10.10.112.153]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 6F23910016E8; Sat, 27 Jun 2020 20:00:19 +0000 (UTC) From: dgilmore@redhat.com To: u-boot@lists.denx.de Cc: aditya@kobol.io, trini@konsulko.com, sjg@chromium.org, baruch@tkos.co.il, Dennis Gilmore Subject: [PATCH] sync helios4 config to clearfog and dts to kernel Date: Sat, 27 Jun 2020 15:00:16 -0500 Message-Id: <20200627200016.24789-1-dgilmore@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean From: Dennis Gilmore The helios4 is built on the same microsom as the clearfog, by syncing the config we enable the same featureset that exists in the som on the helios4. The current config does not boot as some of the clearfog changes needed to be made on the helios4 also, generally speaking most changes for the clearfog should also be made on the helios4. Signed-off-by: Dennis Gilmore Reviewed-by: Stefan Roese --- arch/arm/dts/armada-388-helios4-u-boot.dtsi | 15 ++++ arch/arm/dts/armada-388-helios4.dts | 16 ++-- configs/helios4_defconfig | 20 +++-- include/configs/helios4.h | 95 ++++++++++++--------- 4 files changed, 93 insertions(+), 53 deletions(-) diff --git a/arch/arm/dts/armada-388-helios4-u-boot.dtsi b/arch/arm/dts/armada-388-helios4-u-boot.dtsi index f0da9f42de..0753889854 100644 --- a/arch/arm/dts/armada-388-helios4-u-boot.dtsi +++ b/arch/arm/dts/armada-388-helios4-u-boot.dtsi @@ -14,6 +14,9 @@ &spi1 { u-boot,dm-spl; + spi-flash@0 { + u-boot,dm-spl; + }; }; &w25q32 { @@ -21,6 +24,18 @@ u-boot,dm-spl; }; +&gpio0 { + u-boot,dm-spl; +}; + +&ahci0 { + u-boot,dm-spl; +}; + +&ahci1 { + u-boot,dm-spl; +}; + &sdhci { u-boot,dm-spl; }; diff --git a/arch/arm/dts/armada-388-helios4.dts b/arch/arm/dts/armada-388-helios4.dts index a154e0f4f4..fb49df2a3b 100644 --- a/arch/arm/dts/armada-388-helios4.dts +++ b/arch/arm/dts/armada-388-helios4.dts @@ -140,11 +140,6 @@ soc { internal-regs { i2c@11000 { - clock-frequency = <400000>; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - status = "okay"; - /* * PCA9655 GPIO expander, up to 1MHz clock. * 0-Board Revision bit 0 # @@ -187,8 +182,7 @@ gpio-hog; gpios = <5 GPIO_ACTIVE_HIGH>; input; - line-name = - "usb-overcurrent-status"; + line-name = "usb-overcurrent-status"; }; }; @@ -248,7 +242,7 @@ bus-width = <4>; cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; no-1-8-v; - pinctrl-0 = <µsom_sdhci_pins + pinctrl-0 = <&helios_sdhci_pins &helios_sdhci_cd_pins>; pinctrl-names = "default"; status = "okay"; @@ -286,6 +280,12 @@ marvell,pins = "mpp20"; marvell,function = "gpio"; }; + helios_sdhci_pins: helios-sdhci-pins { + marvell,pins = "mpp21", "mpp28", + "mpp37", "mpp38", + "mpp39", "mpp40"; + marvell,function = "sd0"; + }; helios_led_pins: helios-led-pins { marvell,pins = "mpp24", "mpp25", "mpp49", "mpp50", diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig index e15f10cdd5..9cc87fd96a 100644 --- a/configs/helios4_defconfig +++ b/configs/helios4_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_CPU_INIT=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 CONFIG_SPL_LIBCOMMON_SUPPORT=y @@ -24,40 +25,47 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x141 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET=0x1 +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_CMD_TLV_EEPROM=y +CONFIG_SPL_CMD_TLV_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y +CONFIG_CMD_MVEBU_BUBT=y # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_DEFAULT_DEVICE_TREE="armada-388-helios4" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_OF_TRANSLATE=y -CONFIG_SCSI_AHCI=y +CONFIG_AHCI_MVEBU=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1 CONFIG_SYS_I2C_MVTWSI=y +CONFIG_I2C_EEPROM=y +CONFIG_SPL_I2C_EEPROM=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_MV=y CONFIG_MTD=y CONFIG_SF_DEFAULT_BUS=1 -CONFIG_SF_DEFAULT_SPEED=104000000 CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y CONFIG_MII=y +CONFIG_PCI=y +CONFIG_PCI_MVEBU=y CONFIG_SCSI=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y diff --git a/include/configs/helios4.h b/include/configs/helios4.h index 31e2e78b62..2f4b67025c 100644 --- a/include/configs/helios4.h +++ b/include/configs/helios4.h @@ -6,7 +6,6 @@ #ifndef _CONFIG_HELIOS4_H #define _CONFIG_HELIOS4_H -#include #include /* @@ -30,26 +29,30 @@ #define CONFIG_ENV_MIN_ENTRIES 128 +/* Environment in MMC */ +#define CONFIG_SYS_MMC_ENV_DEV 0 /* - * SATA/SCSI/AHCI configuration + * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC + * boot image starts @ LBA-0. + * As result in MMC/eMMC case it will be a 1 sector gap between u-boot + * image and environment */ -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 -#define CONFIG_SYS_SCSI_MAX_LUN 2 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) -#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI -/* Environment in SPI NOR flash */ -#endif +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC -/* Environment in MMC */ -#define CONFIG_SYS_MMC_ENV_DEV 0 -/* stay within first 1M */ +/* PCIe support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PCI_SCAN_SHOW #endif -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ +/* SATA support */ +#ifdef CONFIG_SCSI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#endif /* Keep device tree and initrd in lower memory so the kernel can access them */ #define RELOCATION_LIMITS_ENV_SETTINGS \ @@ -57,22 +60,6 @@ "initrd_high=0x10000000\0" /* SPL */ -/* - * Select the boot device here - * - * Currently supported are: - * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash - * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) - */ -#define SPL_BOOT_SPI_NOR_FLASH 1 -#define SPL_BOOT_SDIO_MMC_CARD 2 - -#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI -#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH -#endif -#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC -#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SDIO_MMC_CARD -#endif /* Defines for SPL */ #define CONFIG_SPL_SIZE (140 << 10) @@ -88,11 +75,10 @@ #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) -#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH +#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI) +/* SPL related SPI defines */ #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS -#endif - -#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD +#elif defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA) /* SPL related MMC defines */ #define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS @@ -100,6 +86,7 @@ #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ #endif #endif + /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros @@ -121,16 +108,46 @@ #define BOOT_TARGET_DEVICES_USB(func) #endif -#ifdef CONFIG_SATA -#define BOOT_TARGET_DEVICES_SATA(func) func(SATA, sata, 0) +#ifndef CONFIG_SCSI +#define BOOT_TARGET_DEVICES_SCSI_BUS0(func) +#define BOOT_TARGET_DEVICES_SCSI_BUS1(func) +#define BOOT_TARGET_DEVICES_SCSI_BUS2(func) +#else +/* + * With SCSI enabled, M.2 SATA is always located on bus 0 + */ +#define BOOT_TARGET_DEVICES_SCSI_BUS0(func) func(SCSI, scsi, 0) + +/* + * Either one or both mPCIe slots may be configured as mSATA interfaces. The + * SCSI bus ids are assigned based on sequence of hardware present, not always + * tied to hardware slot ids. As such, use second SCSI bus if either slot is + * set for SATA, and only use third SCSI bus if both slots are SATA enabled. + */ +#if defined (CONFIG_HELIOS4_CON2_SATA) || defined (CONFIG_HELIOS4_CON3_SATA) +#define BOOT_TARGET_DEVICES_SCSI_BUS1(func) func(SCSI, scsi, 1) +#else +#define BOOT_TARGET_DEVICES_SCSI_BUS1(func) +#endif + +#if defined (CONFIG_HELIOS4_CON2_SATA) && defined (CONFIG_HELIOS4_CON3_SATA) +#define BOOT_TARGET_DEVICES_SCSI_BUS2(func) func(SCSI, scsi, 2) #else -#define BOOT_TARGET_DEVICES_SATA(func) +#define BOOT_TARGET_DEVICES_SCSI_BUS2(func) #endif +#endif /* CONFIG_SCSI */ + +/* + * The SCSI buses are attempted in increasing bus order, there is no current + * mechanism to alter the default bus priority order for booting. + */ #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_MMC(func) \ BOOT_TARGET_DEVICES_USB(func) \ - BOOT_TARGET_DEVICES_SATA(func) \ + BOOT_TARGET_DEVICES_SCSI_BUS0(func) \ + BOOT_TARGET_DEVICES_SCSI_BUS1(func) \ + BOOT_TARGET_DEVICES_SCSI_BUS2(func) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na)