From patchwork Sat Jun 27 15:25:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Beata Michalska X-Patchwork-Id: 1318385 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=SiLDQW9d; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49vHfl21V0z9sQt for ; Sun, 28 Jun 2020 01:26:55 +1000 (AEST) Received: from localhost ([::1]:44074 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jpCjF-0004VP-1i for incoming@patchwork.ozlabs.org; Sat, 27 Jun 2020 11:26:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45576) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jpCin-0004Cw-Pn for qemu-devel@nongnu.org; Sat, 27 Jun 2020 11:26:25 -0400 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:37253) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jpCim-0007Sr-6h for qemu-devel@nongnu.org; Sat, 27 Jun 2020 11:26:25 -0400 Received: by mail-wr1-x443.google.com with SMTP id a6so12285690wrm.4 for ; Sat, 27 Jun 2020 08:26:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sywPQP4YPO8LGxojbcR8IAxntZAWNms0b4i/i1pRSn4=; b=SiLDQW9dcgpRB6D+KHc4ARCZLzJcBv9wbmBl4Y3XnNwMMNDquQ8xAkUMQEk4NEqz3I US+u4+pR37pYZkW+V+ev0Q7MSo0Zn64BTrOlt06UXkFpBxQmdAkYWi6hyCIp6IX7qecu LM1cZqdjmiechPF2m2IKTwf+V2pkZYu/o16dP68nrFoL/AAkEk1GF7aN5QJ4YxHr+6aL ZWzsmV26h+uK0gijybQkuWz1WZ6mRGFPLnjXuztj4iiJ5+jQGSfw4cuvAx1sr5tqo9VB KrcQljcWTBykuVNj1ecLPGi7tR1Pj+AcDivbiYcOnehl1cb6ABsHZJ9HTlVJWg3nGSKC DXqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sywPQP4YPO8LGxojbcR8IAxntZAWNms0b4i/i1pRSn4=; b=scoCswDhkZ/c6Qt+CMVVPh0EJWRN/FPpihpotO8A9Qxl3s0PXXdxKogvKQA4NPv+H1 5WcMWGeqhHIPixE9DfeJBlgiXiyF4IkFfE0sEg9armlqClQOti7GY9MplMvju0NgjVhB GL0Fm5V8/hAv2+e4euaFqhPS9SHLjW1GLGn0vzW5+qD8Leh+dj7Gn4hVQTYYiguVkXPq dEHVCHiZClECN3vAvHIDx4h3e0AzhpdHVq6FI0M00OQoZ3fvKkBpjNJKiSbbgsNKib/7 AluVrdxtXYoV8DNejS/qIMuLdHqpxN9YH7sfYTM2n9aXQ2fBPUnwLFu1dG7Emr/R+amK ZZvg== X-Gm-Message-State: AOAM531+4fW8K4oU7Abi0ICPy7xuieMBQJNS3PSJ8cWSfdKwl5IFOWz9 UiUGSzLuSxJi4mC8bUrRqKzjk/FNOASKvA== X-Google-Smtp-Source: ABdhPJxkoUM9UcCa/lpe3+bR7cO6H5cyDGmpNECjgEgD+ajwHt0wfs6AcwU6Nii6I2V10pX1h16kXQ== X-Received: by 2002:adf:f388:: with SMTP id m8mr9219258wro.338.1593271582640; Sat, 27 Jun 2020 08:26:22 -0700 (PDT) Received: from moi-limbo-9350.home (host-92-18-20-3.as13285.net. [92.18.20.3]) by smtp.gmail.com with ESMTPSA id c6sm20965438wma.15.2020.06.27.08.26.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jun 2020 08:26:22 -0700 (PDT) From: Beata Michalska To: qemu-devel@nongnu.org Subject: [PATCH v7 1/2] target/arm: kvm: Handle DABT with no valid ISS Date: Sat, 27 Jun 2020 16:25:55 +0100 Message-Id: <20200627152556.7391-2-beata.michalska@linaro.org> In-Reply-To: <20200627152556.7391-1-beata.michalska@linaro.org> References: <20200627152556.7391-1-beata.michalska@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=beata.michalska@linaro.org; helo=mail-wr1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, Christoffer.Dall@arm.com, qemu-arm@nongnu.org, pbonzini@redhat.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" On ARMv7 & ARMv8 some load/store instructions might trigger a data abort exception with no valid ISS info to be decoded. The lack of decode info makes it at least tricky to emulate those instruction which is one of the (many) reasons why KVM will not even try to do so. Add support for handling those by requesting KVM to inject external dabt into the quest. Signed-off-by: Beata Michalska --- target/arm/kvm.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 57 insertions(+), 1 deletion(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index eef3bbd..3ea6f9a 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -39,6 +39,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = { static bool cap_has_mp_state; static bool cap_has_inject_serror_esr; +static bool cap_has_inject_ext_dabt; static ARMHostCPUFeatures arm_host_cpu_features; @@ -245,6 +246,16 @@ int kvm_arch_init(MachineState *ms, KVMState *s) ret = -EINVAL; } + if (kvm_check_extension(s, KVM_CAP_ARM_NISV_TO_USER)) { + if (kvm_vm_enable_cap(s, KVM_CAP_ARM_NISV_TO_USER, 0)) { + error_report("Failed to enable KVM_CAP_ARM_NISV_TO_USER cap"); + } else { + /* Set status for supporting the external dabt injection */ + cap_has_inject_ext_dabt = kvm_check_extension(s, + KVM_CAP_ARM_INJECT_EXT_DABT); + } + } + return ret; } @@ -810,6 +821,46 @@ void kvm_arm_vm_state_change(void *opaque, int running, RunState state) } } +/** + * kvm_arm_handle_dabt_nisv: + * @cs: CPUState + * @esr_iss: ISS encoding (limited) for the exception from Data Abort + * ISV bit set to '0b0' -> no valid instruction syndrome + * @fault_ipa: faulting address for the synchronous data abort + * + * Returns: 0 if the exception has been handled, < 0 otherwise + */ +static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss, + uint64_t fault_ipa) +{ + /* + * Request KVM to inject the external data abort into the guest + */ + if (cap_has_inject_ext_dabt) { + /* + * KVM_CAP_ARM_INJECT_EXT_DABT support implies one for + * KVM_CAP_VCPU_EVENTS + */ + struct kvm_vcpu_events events = { }; + /* + * The external data abort event will be handled immediately by KVM + * using the address fault that triggered the exit on given VCPU. + * Requesting injection of the external data abort does not rely + * on any other VCPU state. Therefore, in this particular case, the VCPU + * synchronization can be exceptionally skipped. + */ + events.exception.ext_dabt_pending = 1; + + return kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events); + } else { + error_report("Data abort exception triggered by guest memory access " + "at physical address: 0x" TARGET_FMT_lx, + (target_ulong)fault_ipa); + error_printf("KVM unable to emulate faulting instruction.\n"); + } + return -1; +} + int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) { int ret = 0; @@ -820,7 +871,12 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) ret = EXCP_DEBUG; } /* otherwise return to guest */ break; - default: + case KVM_EXIT_ARM_NISV: + /* External DABT with no valid iss to decode */ + ret = kvm_arm_handle_dabt_nisv(cs, run->arm_nisv.esr_iss, + run->arm_nisv.fault_ipa); + break; + default: qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", __func__, run->exit_reason); break; From patchwork Sat Jun 27 15:25:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Beata Michalska X-Patchwork-Id: 1318386 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=g+lTXTe5; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49vHgy6B2tz9sQt for ; Sun, 28 Jun 2020 01:27:58 +1000 (AEST) Received: from localhost ([::1]:48312 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jpCkG-0006Cg-K5 for incoming@patchwork.ozlabs.org; Sat, 27 Jun 2020 11:27:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45626) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jpCis-0004Jl-S3 for qemu-devel@nongnu.org; Sat, 27 Jun 2020 11:26:30 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:35492) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jpCiq-0007TO-CD for qemu-devel@nongnu.org; Sat, 27 Jun 2020 11:26:30 -0400 Received: by mail-wr1-x442.google.com with SMTP id g18so12306896wrm.2 for ; Sat, 27 Jun 2020 08:26:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=n/6jUch7mGHyEeK3tacOaSSb1YHko1j6EhQD5+qAa6A=; b=g+lTXTe5bhAAe4vDb1NZ7db+wwa2/yz2oQ8pEwuqKjtmq1B8+GU71Ku9eBNDWwS8CF eWKRe5ew5tR2Ug0G1mtMRFJjVhDzNGNDqUAMC/j+PI9HWdCFvzLNz2Zaw7Pb6O9pbeMK f2adRDciNW9aSFXPM2LP0r28vxNJZTQBn8LhqlU0JzBCozD25ugt6NDyF5fsTGQKG1i1 FKIJiF1FAG4F5/7dmhp9ST81S3AUV3dkcl19+Gm6hpYLI6ZTbBrFvYqz6BnLU6cpkzuu reIZX4y7MDEXSjASYQpxT/Qb33+x8urCxJVw3s3cUcEIMk2yKU5q8W83sg9V/OW//ZMx iZoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=n/6jUch7mGHyEeK3tacOaSSb1YHko1j6EhQD5+qAa6A=; b=uT48lzv+WuZ8cJadA7OWsZOLs6iI+PlmnY/tZcr0+ehpvjHa8F8xGnhAzXf7lnJiB4 zP/DtrxYEt4NaOCcu2pKPT3Cd4XDUPHp6riW7ZR3Ly9YZ8/g2MHMAPTIth/8f1qFfBX4 gUo8UR4bG+Glg/tyKg0RkWe2sYHzQWw7c50cBhA3E1LtJRQDUd3vXzBY/Zlh7xLrbYf7 MSo5rVN9TrD7VRr+pfIUnXFyzF0k8Sey2Bb6vx/yFjItPZmw7Pye6LFhwvq0nmioY4Wg sQa1ZQFje/Ac59Eotf7vOu7i7MxoAmIVWmDy6p+lyFpI8iR0MCTK3wI0bEnf4xco/5hE 78WA== X-Gm-Message-State: AOAM532eOn1Fne+PCJ1eMP5hgZBjeQrOL25J5cq2i2TI+nKANBwf682Q 73TL9Pl0zMn9ite8T6M3l+4Az2EYAesUpw== X-Google-Smtp-Source: ABdhPJytR/59J4R5jKDmAp1NzkrV1ArjXZp773q1vu5Pr+Yy7tZLW3O7uFXyDBsu0bNeu3Bqjx2kGg== X-Received: by 2002:a05:6000:cf:: with SMTP id q15mr9144736wrx.203.1593271586577; Sat, 27 Jun 2020 08:26:26 -0700 (PDT) Received: from moi-limbo-9350.home (host-92-18-20-3.as13285.net. [92.18.20.3]) by smtp.gmail.com with ESMTPSA id c6sm20965438wma.15.2020.06.27.08.26.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jun 2020 08:26:26 -0700 (PDT) From: Beata Michalska To: qemu-devel@nongnu.org Subject: [PATCH v7 2/2] target/arm: kvm: Handle misconfigured dabt injection Date: Sat, 27 Jun 2020 16:25:56 +0100 Message-Id: <20200627152556.7391-3-beata.michalska@linaro.org> In-Reply-To: <20200627152556.7391-1-beata.michalska@linaro.org> References: <20200627152556.7391-1-beata.michalska@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=beata.michalska@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, Christoffer.Dall@arm.com, qemu-arm@nongnu.org, pbonzini@redhat.com, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Injecting external data abort through KVM might trigger an issue on kernels that do not get updated to include the KVM fix. For those and aarch32 guests, the injected abort gets misconfigured to be an implementation defined exception. This leads to the guest repeatedly re-running the faulting instruction. Add support for handling that case. [ Fixed-by: 018f22f95e8a ('KVM: arm: Fix DFSR setting for non-LPAE aarch32 guests') Fixed-by: 21aecdbd7f3a ('KVM: arm: Make inject_abt32() inject an external abort instead') ] Signed-off-by: Beata Michalska --- target/arm/cpu.h | 2 ++ target/arm/kvm.c | 30 +++++++++++++++++++++++++++++- target/arm/kvm32.c | 34 ++++++++++++++++++++++++++++++++++ target/arm/kvm64.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ target/arm/kvm_arm.h | 10 ++++++++++ 5 files changed, 124 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 677584e..ed0ff09 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -570,6 +570,8 @@ typedef struct CPUARMState { uint64_t esr; } serror; + uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ + /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ uint32_t irq_line_state; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 3ea6f9a..66d5ee5 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -749,6 +749,29 @@ int kvm_get_vcpu_events(ARMCPU *cpu) void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + + if (unlikely(env->ext_dabt_raised)) { + /* + * Verifying that the ext DABT has been properly injected, + * otherwise risking indefinitely re-running the faulting instruction + * Covering a very narrow case for kernels 5.5..5.5.4 + * when injected abort was misconfigured to be + * an IMPLEMENTATION DEFINED exception (for 32-bit EL1) + */ + if (!arm_feature(env, ARM_FEATURE_AARCH64) && + unlikely(!kvm_arm_verify_ext_dabt_pending(cs))) { + + error_report("Data abort exception with no valid ISS generated by " + "guest memory access. KVM unable to emulate faulting " + "instruction. Failed to inject an external data abort " + "into the guest."); + abort(); + } + /* Clear the status */ + env->ext_dabt_raised = 0; + } } MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) @@ -833,6 +856,8 @@ void kvm_arm_vm_state_change(void *opaque, int running, RunState state) static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss, uint64_t fault_ipa) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; /* * Request KVM to inject the external data abort into the guest */ @@ -851,7 +876,10 @@ static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss, */ events.exception.ext_dabt_pending = 1; - return kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events); + if (!kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events)) { + env->ext_dabt_raised = 1; + return 0; + } } else { error_report("Data abort exception triggered by guest memory access " "at physical address: 0x" TARGET_FMT_lx, diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 7b3a19e..0af46b4 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -559,3 +559,37 @@ void kvm_arm_pmu_init(CPUState *cs) { qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__); } + +#define ARM_REG_DFSR ARM_CP15_REG32(0, 5, 0, 0) +#define ARM_REG_TTBCR ARM_CP15_REG32(0, 2, 0, 2) +/* + *DFSR: + * TTBCR.EAE == 0 + * FS[4] - DFSR[10] + * FS[3:0] - DFSR[3:0] + * TTBCR.EAE == 1 + * FS, bits [5:0] + */ +#define DFSR_FSC(lpae, v) \ + ((lpae) ? ((v) & 0x3F) : (((v) >> 6) | ((v) & 0x1F))) + +#define DFSC_EXTABT(lpae) ((lpae) ? 0x10 : 0x08) + +bool kvm_arm_verify_ext_dabt_pending(CPUState *cs) +{ + uint32_t dfsr_val; + + if (!kvm_get_one_reg(cs, ARM_REG_DFSR, &dfsr_val)) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + uint32_t ttbcr; + int lpae = 0; + + if (!kvm_get_one_reg(cs, ARM_REG_TTBCR, &ttbcr)) { + lpae = arm_feature(env, ARM_FEATURE_LPAE) && (ttbcr & TTBCR_EAE); + } + /* The verification is based on FS filed of the DFSR reg only*/ + return (DFSR_FSC(lpae, dfsr_val) == DFSC_EXTABT(lpae)); + } + return false; +} diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index f09ed9f..88cf10c 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -1497,3 +1497,52 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit) return false; } + +#define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0) +#define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2) + +/* + * ESR_EL1 + * ISS encoding + * AARCH64: DFSC, bits [5:0] + * AARCH32: + * TTBCR.EAE == 0 + * FS[4] - DFSR[10] + * FS[3:0] - DFSR[3:0] + * TTBCR.EAE == 1 + * FS, bits [5:0] + */ +#define ESR_DFSC(aarch64, lpae, v) \ + ((aarch64 || (lpae)) ? ((v) & 0x3F) \ + : (((v) >> 6) | ((v) & 0x1F))) + +#define ESR_DFSC_EXTABT(aarch64, lpae) \ + ((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8) + +bool kvm_arm_verify_ext_dabt_pending(CPUState *cs) +{ + uint64_t dfsr_val; + + if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + int aarch64_mode = arm_feature(env, ARM_FEATURE_AARCH64); + int lpae = 0; + + if (!aarch64_mode) { + uint64_t ttbcr; + + if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) { + lpae = arm_feature(env, ARM_FEATURE_LPAE) + && (ttbcr & TTBCR_EAE); + } + } + /* + * The verification here is based on the DFSC bits + * of the ESR_EL1 reg only + */ + return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) == + ESR_DFSC_EXTABT(aarch64_mode, lpae)); + } + return false; +} diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 48bf5e1..471ddd1 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -453,6 +453,16 @@ struct kvm_guest_debug_arch; void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr); /** + * kvm_arm_verify_ext_dabt_pending: + * @cs: CPUState + * + * Verify the fault status code wrt the Ext DABT injection + * + * Returns: true if the fault status code is as expected, false otherwise + */ +bool kvm_arm_verify_ext_dabt_pending(CPUState *cs); + +/** * its_class_name: * * Return the ITS class name to use depending on whether KVM acceleration