From patchwork Wed Jun 24 02:30:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 1315820 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49s6pv61kgz9sRR for ; Wed, 24 Jun 2020 12:41:25 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5E52A81EC6; Wed, 24 Jun 2020 04:41:16 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id A551881F8F; Wed, 24 Jun 2020 04:41:10 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from ATCSQR.andestech.com (atcsqr.andestech.com [60.248.187.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A4B7481EC4 for ; Wed, 24 Jun 2020 04:41:02 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=uboot@andestech.com Received: from mail.andestech.com (atcpcs12.andestech.com [10.0.1.220]) by ATCSQR.andestech.com with ESMTP id 05O2Xh7h071784; Wed, 24 Jun 2020 10:33:43 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from [127.0.1.1] (10.0.15.117) by ATCPCS12.andestech.com (10.0.1.220) with Microsoft SMTP Server id 14.3.123.3; Wed, 24 Jun 2020 10:40:33 +0800 MIME-Version: 1.0 Subject: [U-Boot] Pull request: u-boot-riscv/master From: To: , , , Date: Wed, 24 Jun 2020 10:30:24 +0800 Message-ID: <8dc6332c-5b99-4b9c-a1c1-48068b71e474@ATCPCS12.andestech.com> X-Originating-IP: [10.0.15.117] X-DNSRBL: X-MAIL: ATCSQR.andestech.com 05O2Xh7h071784 X-Content-Filtered-By: Mailman/MimeDel 2.1.30rc1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Hi Tom, Please pull some riscv updates: - fu540: dts: Correct reg size of otp and dmc nodes - sbi: Add newline to error message - sifive/fu540: Enable SPI-NOR support Thanks Rick https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/701223929 The following changes since commit 4ff63383e3497389e66cf70943a83bdb1810462a: Merge tag 'u-boot-imx-20200623' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2020-06-23 08:20:55 -0400) are available in the Git repository at: git@gitlab.denx.de:u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 2148d9c76ef5efbf5b98ca3d3fcbaad465115e70: riscv: fu540: dts: Correct reg size of otp and dmc nodes (2020-06-24 09:59:30 +0800) ---------------------------------------------------------------- Bin Meng (2): riscv: fu540: dts: Remove the unnecessary space in the cpu2_intc node riscv: fu540: dts: Correct reg size of otp and dmc nodes Jagan Teki (6): sifive: fu540: Add runtime boot mode detection sifive: fu540: Add Booting from SPI env: Enable SPI flash env for SiFive FU540 sifive: fu540: Mark the default env as SPI flash sifive: fu540: Add boot flash script offset, size sifive: fu540: Enable SF distro bootcmd Sean Anderson (1): riscv: sbi: Add newline to error message arch/riscv/cpu/fu540/Kconfig | 15 +++++++++++++++ arch/riscv/dts/fu540-c000-u-boot.dtsi | 6 +++--- arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 12 ++++++++++++ board/sifive/fu540/Kconfig | 1 + board/sifive/fu540/fu540.c | 25 +++++++++++++++++++------ common/spl/spl_opensbi.c | 2 +- configs/sifive_fu540_defconfig | 4 ++++ doc/board/sifive/fu540.rst | 41 +++++++++++++++++++++++++++++++++++++++++ include/configs/sifive-fu540.h | 7 ++++++- 9 files changed, 102 insertions(+), 11 deletions(-)