From patchwork Thu Jun 18 08:38:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 1311938 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=socionext.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49nb1j2CmZz9sTL for ; Thu, 18 Jun 2020 18:38:33 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728841AbgFRIib (ORCPT ); Thu, 18 Jun 2020 04:38:31 -0400 Received: from mx.socionext.com ([202.248.49.38]:19342 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727839AbgFRIi0 (ORCPT ); Thu, 18 Jun 2020 04:38:26 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 18 Jun 2020 17:38:24 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 528D6180B51; Thu, 18 Jun 2020 17:38:24 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Thu, 18 Jun 2020 17:38:24 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id D09501A12AD; Thu, 18 Jun 2020 17:38:23 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Rob Herring , Masahiro Yamada , Marc Zyngier Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v5 1/6] PCI: dwc: Add msi_host_isr() callback Date: Thu, 18 Jun 2020 17:38:08 +0900 Message-Id: <1592469493-1549-2-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1592469493-1549-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1592469493-1549-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This adds msi_host_isr() callback function support to describe SoC-dependent service triggered by MSI. For example, when AER interrupt is triggered by MSI, the callback function reads SoC-dependent registers and detects that the interrupt is from AER, and invoke AER interrupts related to MSI. Cc: Marc Zyngier Cc: Jingoo Han Cc: Gustavo Pimentel Signed-off-by: Kunihiko Hayashi Acked-by: Gustavo Pimentel --- drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 0a4a5aa..026edb1 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -83,6 +83,9 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) u32 status, num_ctrls; irqreturn_t ret = IRQ_NONE; + if (pp->ops->msi_host_isr) + pp->ops->msi_host_isr(pp); + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; for (i = 0; i < num_ctrls; i++) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 656e00f..e741967 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -170,6 +170,7 @@ struct dw_pcie_host_ops { void (*scan_bus)(struct pcie_port *pp); void (*set_num_vectors)(struct pcie_port *pp); int (*msi_host_init)(struct pcie_port *pp); + void (*msi_host_isr)(struct pcie_port *pp); }; struct pcie_port { From patchwork Thu Jun 18 08:38:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 1311942 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=socionext.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49nb2D3T94z9sTD for ; Thu, 18 Jun 2020 18:39:00 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728846AbgFRIic (ORCPT ); Thu, 18 Jun 2020 04:38:32 -0400 Received: from mx.socionext.com ([202.248.49.38]:19349 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728820AbgFRIi1 (ORCPT ); Thu, 18 Jun 2020 04:38:27 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 18 Jun 2020 17:38:25 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 5BC97180B51; Thu, 18 Jun 2020 17:38:25 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Thu, 18 Jun 2020 17:38:25 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id CB0D41A12AD; Thu, 18 Jun 2020 17:38:24 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Rob Herring , Masahiro Yamada , Marc Zyngier Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v5 2/6] PCI: uniphier: Add misc interrupt handler to invoke PME and AER Date: Thu, 18 Jun 2020 17:38:09 +0900 Message-Id: <1592469493-1549-3-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1592469493-1549-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1592469493-1549-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The misc interrupts consisting of PME, AER, and Link event, is handled by INTx handler, however, these interrupts should be also handled by MSI handler. This adds the function uniphier_pcie_misc_isr() that handles misc interrupts, which is called from both INTx and MSI handlers. This function detects PME and AER interrupts with the status register, and invoke PME and AER drivers related to MSI. And this sets the mask for misc interrupts from INTx if MSI is enabled and sets the mask for misc interrupts from MSI if MSI is disabled. Cc: Marc Zyngier Cc: Jingoo Han Cc: Gustavo Pimentel Signed-off-by: Kunihiko Hayashi --- drivers/pci/controller/dwc/pcie-uniphier.c | 57 ++++++++++++++++++++++++------ 1 file changed, 46 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c index a5401a0..5ce2479 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier.c +++ b/drivers/pci/controller/dwc/pcie-uniphier.c @@ -44,7 +44,9 @@ #define PCL_SYS_AUX_PWR_DET BIT(8) #define PCL_RCV_INT 0x8108 +#define PCL_RCV_INT_ALL_INT_MASK GENMASK(28, 25) #define PCL_RCV_INT_ALL_ENABLE GENMASK(20, 17) +#define PCL_RCV_INT_ALL_MSI_MASK GENMASK(12, 9) #define PCL_CFG_BW_MGT_STATUS BIT(4) #define PCL_CFG_LINK_AUTO_BW_STATUS BIT(3) #define PCL_CFG_AER_RC_ERR_MSI_STATUS BIT(2) @@ -167,7 +169,15 @@ static void uniphier_pcie_stop_link(struct dw_pcie *pci) static void uniphier_pcie_irq_enable(struct uniphier_pcie_priv *priv) { - writel(PCL_RCV_INT_ALL_ENABLE, priv->base + PCL_RCV_INT); + u32 val; + + val = PCL_RCV_INT_ALL_ENABLE; + if (pci_msi_enabled()) + val |= PCL_RCV_INT_ALL_INT_MASK; + else + val |= PCL_RCV_INT_ALL_MSI_MASK; + + writel(val, priv->base + PCL_RCV_INT); writel(PCL_RCV_INTX_ALL_ENABLE, priv->base + PCL_RCV_INTX); } @@ -231,32 +241,56 @@ static const struct irq_domain_ops uniphier_intx_domain_ops = { .map = uniphier_pcie_intx_map, }; -static void uniphier_pcie_irq_handler(struct irq_desc *desc) +static void uniphier_pcie_misc_isr(struct pcie_port *pp, bool is_msi) { - struct pcie_port *pp = irq_desc_get_handler_data(desc); struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); - struct irq_chip *chip = irq_desc_get_chip(desc); - unsigned long reg; - u32 val, bit, virq; + u32 val, virq; - /* INT for debug */ val = readl(priv->base + PCL_RCV_INT); if (val & PCL_CFG_BW_MGT_STATUS) dev_dbg(pci->dev, "Link Bandwidth Management Event\n"); + if (val & PCL_CFG_LINK_AUTO_BW_STATUS) dev_dbg(pci->dev, "Link Autonomous Bandwidth Event\n"); - if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS) - dev_dbg(pci->dev, "Root Error\n"); - if (val & PCL_CFG_PME_MSI_STATUS) - dev_dbg(pci->dev, "PME Interrupt\n"); + + if (is_msi) { + if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS) + dev_dbg(pci->dev, "Root Error Status\n"); + + if (val & PCL_CFG_PME_MSI_STATUS) + dev_dbg(pci->dev, "PME Interrupt\n"); + + if (val & (PCL_CFG_AER_RC_ERR_MSI_STATUS | + PCL_CFG_PME_MSI_STATUS)) { + virq = irq_linear_revmap(pp->irq_domain, 0); + generic_handle_irq(virq); + } + } writel(val, priv->base + PCL_RCV_INT); +} + +static void uniphier_pcie_msi_host_isr(struct pcie_port *pp) +{ + uniphier_pcie_misc_isr(pp, true); +} + +static void uniphier_pcie_irq_handler(struct irq_desc *desc) +{ + struct pcie_port *pp = irq_desc_get_handler_data(desc); + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned long reg; + u32 val, bit, virq; /* INTx */ chained_irq_enter(chip, desc); + uniphier_pcie_misc_isr(pp, false); + val = readl(priv->base + PCL_RCV_INTX); reg = FIELD_GET(PCL_RCV_INTX_ALL_STATUS, val); @@ -330,6 +364,7 @@ static int uniphier_pcie_host_init(struct pcie_port *pp) static const struct dw_pcie_host_ops uniphier_pcie_host_ops = { .host_init = uniphier_pcie_host_init, + .msi_host_isr = uniphier_pcie_msi_host_isr, }; static int uniphier_add_pcie_port(struct uniphier_pcie_priv *priv, From patchwork Thu Jun 18 08:38:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 1311947 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=socionext.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49nb2g2xwGz9sTD for ; Thu, 18 Jun 2020 18:39:23 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728909AbgFRIjV (ORCPT ); Thu, 18 Jun 2020 04:39:21 -0400 Received: from mx.socionext.com ([202.248.49.38]:19356 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728823AbgFRIi1 (ORCPT ); Thu, 18 Jun 2020 04:38:27 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 18 Jun 2020 17:38:26 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 6B432180B51; Thu, 18 Jun 2020 17:38:26 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Thu, 18 Jun 2020 17:38:26 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 9911D1A12AD; Thu, 18 Jun 2020 17:38:25 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Rob Herring , Masahiro Yamada , Marc Zyngier Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v5 3/6] dt-bindings: PCI: uniphier: Add iATU register description Date: Thu, 18 Jun 2020 17:38:10 +0900 Message-Id: <1592469493-1549-4-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1592469493-1549-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1592469493-1549-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org In the dt-bindings, "atu" reg-names is required to get the register space for iATU in Synopsys DWC version 4.80 or later. Signed-off-by: Kunihiko Hayashi Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/uniphier-pcie.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt index 1fa2c59..c4b7381 100644 --- a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt +++ b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt @@ -16,6 +16,7 @@ Required properties: "dbi" - controller configuration registers "link" - SoC-specific glue layer registers "config" - PCIe configuration space + "atu" - iATU registers for DWC version 4.80 or later - clocks: A phandle to the clock gate for PCIe glue layer including the host controller. - resets: A phandle to the reset line for PCIe glue layer including From patchwork Thu Jun 18 08:38:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 1311941 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=socionext.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49nb2C3RwDz9sSd for ; Thu, 18 Jun 2020 18:38:59 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728851AbgFRIic (ORCPT ); Thu, 18 Jun 2020 04:38:32 -0400 Received: from mx.socionext.com ([202.248.49.38]:19364 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728824AbgFRIi2 (ORCPT ); Thu, 18 Jun 2020 04:38:28 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 18 Jun 2020 17:38:26 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id E406C60057; Thu, 18 Jun 2020 17:38:26 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Thu, 18 Jun 2020 17:38:26 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 5E0AB1A12AD; Thu, 18 Jun 2020 17:38:26 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Rob Herring , Masahiro Yamada , Marc Zyngier Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v5 4/6] PCI: uniphier: Add iATU register support Date: Thu, 18 Jun 2020 17:38:11 +0900 Message-Id: <1592469493-1549-5-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1592469493-1549-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1592469493-1549-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This gets iATU register area from reg property. In Synopsys DWC version 4.80 or later, since iATU register area is separated from core register area, this area is necessary to get from DT independently. Signed-off-by: Kunihiko Hayashi --- drivers/pci/controller/dwc/pcie-uniphier.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c index 5ce2479..c37a968 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier.c +++ b/drivers/pci/controller/dwc/pcie-uniphier.c @@ -451,6 +451,11 @@ static int uniphier_pcie_probe(struct platform_device *pdev) if (IS_ERR(priv->pci.dbi_base)) return PTR_ERR(priv->pci.dbi_base); + priv->pci.atu_base = + devm_platform_ioremap_resource_byname(pdev, "atu"); + if (IS_ERR(priv->pci.atu_base)) + priv->pci.atu_base = NULL; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "link"); priv->base = devm_ioremap_resource(dev, res); if (IS_ERR(priv->base)) From patchwork Thu Jun 18 08:38:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 1311944 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=socionext.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49nb2K60P8z9sRh for ; Thu, 18 Jun 2020 18:39:05 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728891AbgFRIjC (ORCPT ); Thu, 18 Jun 2020 04:39:02 -0400 Received: from mx.socionext.com ([202.248.49.38]:19368 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728825AbgFRIi2 (ORCPT ); Thu, 18 Jun 2020 04:38:28 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 18 Jun 2020 17:38:27 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 75A22180B51; Thu, 18 Jun 2020 17:38:27 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Thu, 18 Jun 2020 17:38:27 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 1A10B1A12AD; Thu, 18 Jun 2020 17:38:27 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Rob Herring , Masahiro Yamada , Marc Zyngier Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v5 5/6] PCI: uniphier: Add error message when failed to get phy Date: Thu, 18 Jun 2020 17:38:12 +0900 Message-Id: <1592469493-1549-6-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1592469493-1549-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1592469493-1549-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Even if phy driver doesn't probe, the error message can't be distinguished from other errors. This displays error message caused by the phy driver explicitly. Signed-off-by: Kunihiko Hayashi --- drivers/pci/controller/dwc/pcie-uniphier.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c index c37a968..8356dd3 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier.c +++ b/drivers/pci/controller/dwc/pcie-uniphier.c @@ -470,8 +470,12 @@ static int uniphier_pcie_probe(struct platform_device *pdev) return PTR_ERR(priv->rst); priv->phy = devm_phy_optional_get(dev, "pcie-phy"); - if (IS_ERR(priv->phy)) - return PTR_ERR(priv->phy); + if (IS_ERR(priv->phy)) { + ret = PTR_ERR(priv->phy); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get phy (%d)\n", ret); + return ret; + } platform_set_drvdata(pdev, priv); From patchwork Thu Jun 18 08:38:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 1311945 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=socionext.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49nb2d0gm3z9sRh for ; Thu, 18 Jun 2020 18:39:21 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728824AbgFRIjB (ORCPT ); Thu, 18 Jun 2020 04:39:01 -0400 Received: from mx.socionext.com ([202.248.49.38]:19334 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728826AbgFRIi3 (ORCPT ); Thu, 18 Jun 2020 04:38:29 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 18 Jun 2020 17:38:28 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 7559760057; Thu, 18 Jun 2020 17:38:28 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Thu, 18 Jun 2020 17:38:28 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id D055C1A12AD; Thu, 18 Jun 2020 17:38:27 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Rob Herring , Masahiro Yamada , Marc Zyngier Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v5 6/6] PCI: uniphier: Use devm_platform_ioremap_resource_byname() Date: Thu, 18 Jun 2020 17:38:13 +0900 Message-Id: <1592469493-1549-7-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1592469493-1549-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1592469493-1549-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Use devm_platform_ioremap_resource_byname() to simplify the code a bit. Signed-off-by: Kunihiko Hayashi --- drivers/pci/controller/dwc/pcie-uniphier.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c index 8356dd3..233d624 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier.c +++ b/drivers/pci/controller/dwc/pcie-uniphier.c @@ -456,8 +456,7 @@ static int uniphier_pcie_probe(struct platform_device *pdev) if (IS_ERR(priv->pci.atu_base)) priv->pci.atu_base = NULL; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "link"); - priv->base = devm_ioremap_resource(dev, res); + priv->base = devm_platform_ioremap_resource_byname(pdev, "link"); if (IS_ERR(priv->base)) return PTR_ERR(priv->base);