From patchwork Tue Jun 16 13:51:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310348 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=owc+3xnI; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV5M0N5Pz9sSS for ; Tue, 16 Jun 2020 23:52:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728869AbgFPNwu (ORCPT ); Tue, 16 Jun 2020 09:52:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728740AbgFPNws (ORCPT ); Tue, 16 Jun 2020 09:52:48 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4688C06174E for ; Tue, 16 Jun 2020 06:52:47 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id l26so2965206wme.3 for ; Tue, 16 Jun 2020 06:52:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=e+aQRcr8g2L1XKOdnqIhl3Y/lE37D1u6kdXp0AB8z5I=; b=owc+3xnIp7+UxkS37n+s30rY/dEHLz54ugoJQyM3x7GXnY7LE12lTuv5JisMFRDytV moVOllI0lNionN251TnXUQu4+Fh4dUaWDxosglDGNVVtZCOIM1j9Ng0MKIZRv+Cqw+IF ZJxYatrl7IJvBmwOkGNrjXJ0k7ftb3D/yI8NvPDYBVCQaiwZ1oM318jsUc5RygzH9kYx zcB29tYTJdL7kGzH+pU8GSAMpm7wx0+BMLJh1BwABonik7y5QkcJkGVWHreqVJCY5kmG A8NGC3Ot8FIkaPRG0EH4O8s9I795Ye0Y8jV3MfB0O7l49WMWftyQM2uHkOt/Mb8+k2Pe 9djg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=e+aQRcr8g2L1XKOdnqIhl3Y/lE37D1u6kdXp0AB8z5I=; b=j08yioO1Ua884ouKW/4WMZHiV6k2c0i8kb9Z3p7/9GAXR7XcRZeovHNAytwA00EB4a qaIZZ0bDieGk3Ruk4mEsdj9eVbP4YP5N+vDdog9UOrTcK/XbHnLkUONVQ2nWACbLWSVJ duS7ricpK2q2KSHlmdV+bxFqgXi5xQZ5bPEMVFDRxVlCS3aXoAAUvTHieYHe35dJsTwF NF+J92CzkLqiDjsTNcj0uCGKSO2lTTl8lhMRxFAwzkLIolk0Vg02X9CtricCHZrj+oE1 /GZsZpEZifDUSHYZITsJxBxl5IHCP31HlRS8Hg+I7VmJ2a17o5ES1gmr1iY/6WZAWHzI AQqA== X-Gm-Message-State: AOAM530qFPIzsqHRcaM5F/5PjHho3MU6mO8aDdeVT9vcRnShfvv4JLUh aBs6LdUZvVWU3AE2OS4H7jQ= X-Google-Smtp-Source: ABdhPJzaobN8VHO0iY9PKxgxYV6t9Vyj5L3IcgcwIYyFVUackFYExX4ODtN2vuG7CWtmYqpWvXmSew== X-Received: by 2002:a05:600c:287:: with SMTP id 7mr3535658wmk.91.1592315566443; Tue, 16 Jun 2020 06:52:46 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id f11sm27766410wrm.13.2020.06.16.06.52.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:52:45 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 01/73] ARM: tegra: Add missing clock-names for SDHCI on Tegra114 Date: Tue, 16 Jun 2020 15:51:26 +0200 Message-Id: <20200616135238.3001888-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The Tegra SDHCI controller bindings state that the clock-names property is required, so add the missing properties on Tegra114. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 450a1f1b12a0..01a81d380f1f 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -649,6 +649,7 @@ sdhci@78000000 { reg = <0x78000000 0x200>; interrupts = ; clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; + clock-names = "sdhci"; resets = <&tegra_car 14>; reset-names = "sdhci"; status = "disabled"; @@ -659,6 +660,7 @@ sdhci@78000200 { reg = <0x78000200 0x200>; interrupts = ; clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; + clock-names = "sdhci"; resets = <&tegra_car 9>; reset-names = "sdhci"; status = "disabled"; @@ -669,6 +671,7 @@ sdhci@78000400 { reg = <0x78000400 0x200>; interrupts = ; clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; + clock-names = "sdhci"; resets = <&tegra_car 69>; reset-names = "sdhci"; status = "disabled"; @@ -679,6 +682,7 @@ sdhci@78000600 { reg = <0x78000600 0x200>; interrupts = ; clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; + clock-names = "sdhci"; resets = <&tegra_car 15>; reset-names = "sdhci"; status = "disabled"; From patchwork Tue Jun 16 13:51:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310349 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=s93KSWIY; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV5M33PNz9sSg for ; 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Tue, 16 Jun 2020 06:52:47 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 02/73] ARM: tegra: Remove simple clocks bus Date: Tue, 16 Jun 2020 15:51:27 +0200 Message-Id: <20200616135238.3001888-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The standard way to do this is to list out the clocks at the top-level. Adopt the standard way to fix validation. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-dalmore.dts | 15 ++++----------- arch/arm/boot/dts/tegra114-roth.dts | 15 ++++----------- arch/arm/boot/dts/tegra114-tn7.dts | 15 ++++----------- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 15 ++++----------- arch/arm/boot/dts/tegra124-nyan.dtsi | 15 ++++----------- arch/arm/boot/dts/tegra124-venice2.dts | 15 ++++----------- arch/arm/boot/dts/tegra20-harmony.dts | 15 ++++----------- arch/arm/boot/dts/tegra20-paz00.dts | 15 ++++----------- arch/arm/boot/dts/tegra20-seaboard.dts | 15 ++++----------- arch/arm/boot/dts/tegra20-trimslice.dts | 19 ++++++------------- arch/arm/boot/dts/tegra20-ventana.dts | 15 ++++----------- arch/arm/boot/dts/tegra30-beaver.dts | 15 ++++----------- arch/arm/boot/dts/tegra30-cardhu.dtsi | 15 ++++----------- 13 files changed, 54 insertions(+), 145 deletions(-) diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 08be733ee2cd..04adfcb30cd7 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1152,17 +1152,10 @@ backlight: backlight { default-brightness-level = <6>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; gpio-keys { diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index 3d3835591cd2..73b83d51b59b 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -1016,17 +1016,10 @@ backlight: backlight { enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; gpio-keys { diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts index bfdd1bf61816..94e801b7986e 100644 --- a/arch/arm/boot/dts/tegra114-tn7.dts +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -273,17 +273,10 @@ backlight: backlight { power-supply = <&lcd_bl_en>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; gpio-keys { diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 3bce7a1b288a..51b217a6507d 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1855,17 +1855,10 @@ usb-phy@7d008000 { vbus-supply = <&vdd_usb3_vbus>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; cpus { diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 9cb5921bb1fa..4555d01094b5 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -575,17 +575,10 @@ backlight: backlight { 256>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; cpus { diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 710a68c5d4c7..6a7a31c831c5 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -1057,17 +1057,10 @@ backlight: backlight { default-brightness-level = <6>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; gpio-keys { diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 02cd67ea2503..bdfbe26fa26a 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -640,17 +640,10 @@ backlight: backlight { default-brightness-level = <6>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; gpio-keys { diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index cce3a3fb82ed..bfc9625a6c72 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -569,17 +569,10 @@ backlight: backlight { backlight-boot-off; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; gpio-keys { diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 376ecb6435f4..28dcff3b7d7e 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -792,17 +792,10 @@ backlight: backlight { default-brightness-level = <6>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; gpio-keys { diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 8debd3d3c20d..5b26482a55b7 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -366,30 +366,23 @@ usb-phy@c5008000 { status = "okay"; }; - sdhci@c8000000 { + mmc@c8000000 { status = "okay"; broken-cd; bus-width = <4>; }; - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; bus-width = <4>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; gpio-keys { diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 022649119821..59998d3708a1 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -586,17 +586,10 @@ backlight: backlight { default-brightness-level = <6>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; gpio-keys { diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 6b6fd8a8058f..ef3ea08f8d19 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1965,17 +1965,10 @@ usb-phy@7d008000 { status = "okay"; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; gpio-leds { diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 5ee5d141bd81..c166967b6c3f 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -418,17 +418,10 @@ backlight: backlight { default-brightness-level = <6>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; panel: panel { From patchwork Tue Jun 16 13:51:28 2020 Content-Type: text/plain; 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Tue, 16 Jun 2020 06:52:50 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 03/73] ARM: tegra: Remove simple regulators bus Date: Tue, 16 Jun 2020 15:51:28 +0200 Message-Id: <20200616135238.3001888-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The standard way to do this is to list out the regulators at the top level. Adopt the standard way to fix validation. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-dalmore.dts | 129 +++++------ arch/arm/boot/dts/tegra114-roth.dts | 120 +++++----- arch/arm/boot/dts/tegra114-tn7.dts | 65 +++--- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 238 +++++++++---------- arch/arm/boot/dts/tegra124-nyan.dtsi | 259 ++++++++++----------- arch/arm/boot/dts/tegra124-venice2.dts | 265 ++++++++++------------ arch/arm/boot/dts/tegra20-harmony.dts | 121 +++++----- arch/arm/boot/dts/tegra20-medcom-wide.dts | 66 +++--- arch/arm/boot/dts/tegra20-paz00.dts | 38 ++-- arch/arm/boot/dts/tegra20-plutux.dts | 66 +++--- arch/arm/boot/dts/tegra20-seaboard.dts | 125 +++++----- arch/arm/boot/dts/tegra20-tamonten.dtsi | 39 +--- arch/arm/boot/dts/tegra20-tec.dts | 66 +++--- arch/arm/boot/dts/tegra20-trimslice.dts | 85 +++---- arch/arm/boot/dts/tegra20-ventana.dts | 85 +++---- arch/arm/boot/dts/tegra30-beaver.dts | 193 ++++++++-------- arch/arm/boot/dts/tegra30-cardhu-a02.dts | 128 +++++------ arch/arm/boot/dts/tegra30-cardhu-a04.dts | 149 ++++++------ arch/arm/boot/dts/tegra30-cardhu.dtsi | 261 ++++++++++----------- 19 files changed, 1130 insertions(+), 1368 deletions(-) diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 04adfcb30cd7..1dfff574e371 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1187,83 +1187,70 @@ volume_up { }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_ac_bat_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_ac_bat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + vdd_ac_bat_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_ac_bat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - dvdd_ts_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "dvdd_ts"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; - }; + dvdd_ts_reg: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "dvdd_ts"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; + }; - usb1_vbus_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&tps65090_dcdc1_reg>; - }; + usb1_vbus_reg: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&tps65090_dcdc1_reg>; + }; - usb3_vbus_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "usb2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&tps65090_dcdc1_reg>; - }; + usb3_vbus_reg: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "usb2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&tps65090_dcdc1_reg>; + }; - vdd_hdmi_reg: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "vdd_hdmi_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&tps65090_dcdc1_reg>; - }; + vdd_hdmi_reg: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "vdd_hdmi_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&tps65090_dcdc1_reg>; + }; - vdd_cam_1v8_reg: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "vdd_cam_1v8_reg"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&palmas_gpio 6 0>; - }; + vdd_cam_1v8_reg: regulator@6 { + compatible = "regulator-fixed"; + regulator-name = "vdd_cam_1v8_reg"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&palmas_gpio 6 0>; + }; - vdd_5v0_hdmi: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "VDD_5V0_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&tps65090_dcdc1_reg>; - }; + vdd_5v0_hdmi: regulator@7 { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V0_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&tps65090_dcdc1_reg>; }; sound { diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index 73b83d51b59b..5249afdca577 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -1045,76 +1045,64 @@ power { }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - lcd_bl_en: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "lcd_bl_en"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; + lcd_bl_en: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "lcd_bl_en"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; - vdd_lcd: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vdd_lcd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vdd_1v8>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; + vdd_lcd: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vdd_lcd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vdd_1v8>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vdd_1v8_ts"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_LOW>; - regulator-boot-on; - }; + regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_ts"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_LOW>; + regulator-boot-on; + }; - regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vdd_3v3_ts"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; + regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_ts"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; - regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "vdd_1v8_com"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vdd_1v8>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; + regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_com"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vdd_1v8>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; - regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "vdd_3v3_com"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_sys>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; - regulator-always-on; - regulator-boot-on; - }; + regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_com"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_sys>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; }; }; diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts index 94e801b7986e..90935db591a5 100644 --- a/arch/arm/boot/dts/tegra114-tn7.dts +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -302,44 +302,35 @@ volume_up { }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - /* FIXME: output of BQ24192 */ - vs_sys: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "VS_SYS"; - regulator-min-microvolt = <4200000>; - regulator-max-microvolt = <4200000>; - regulator-always-on; - regulator-boot-on; - }; + /* FIXME: output of BQ24192 */ + vs_sys: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "VS_SYS"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + regulator-boot-on; + }; - lcd_bl_en: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "VDD_LCD_BL"; - regulator-min-microvolt = <16500000>; - regulator-max-microvolt = <16500000>; - gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vs_sys>; - regulator-boot-on; - }; + lcd_bl_en: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VDD_LCD_BL"; + regulator-min-microvolt = <16500000>; + regulator-max-microvolt = <16500000>; + gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vs_sys>; + regulator-boot-on; + }; - vdd_lcd: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "VD_LCD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_1v8>; - regulator-boot-on; - }; + vdd_lcd: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "VD_LCD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_1v8>; + regulator-boot-on; }; }; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 51b217a6507d..e97943871fd8 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1879,145 +1879,127 @@ power { }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_mux: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "+VDD_MUX"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; + vdd_mux: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "+VDD_MUX"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "+5V_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; + vdd_5v0_sys: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "+5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; - vdd_3v3_sys: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "+3.3V_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; + vdd_3v3_sys: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; - vdd_3v3_run: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "+3.3V_RUN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; + vdd_3v3_run: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_RUN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; - vdd_3v3_hdmi: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_run>; - }; + vdd_3v3_hdmi: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_run>; + }; - vdd_usb1_vbus: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "+USB0_VBUS_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_usb1_vbus: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "+USB0_VBUS_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; - vdd_usb3_vbus: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "+5V_USB_HS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_usb3_vbus: regulator@6 { + compatible = "regulator-fixed"; + regulator-name = "+5V_USB_HS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; - vdd_3v3_lp0: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "+3.3V_LP0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; + vdd_3v3_lp0: regulator@7 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_LP0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; - vdd_hdmi_pll: regulator@11 { - compatible = "regulator-fixed"; - reg = <11>; - regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05_run>; - }; + vdd_hdmi_pll: regulator@8 { + compatible = "regulator-fixed"; + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05_run>; + }; - vdd_5v0_hdmi: regulator@12 { - compatible = "regulator-fixed"; - reg = <12>; - regulator-name = "+5V_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_5v0_hdmi: regulator@9 { + compatible = "regulator-fixed"; + regulator-name = "+5V_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; - /* Molex power connector */ - vdd_5v0_sata: regulator@13 { - compatible = "regulator-fixed"; - reg = <13>; - regulator-name = "+5V_SATA"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; + /* Molex power connector */ + vdd_5v0_sata: regulator@10 { + compatible = "regulator-fixed"; + regulator-name = "+5V_SATA"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; - vdd_12v0_sata: regulator@14 { - compatible = "regulator-fixed"; - reg = <14>; - regulator-name = "+12V_SATA"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_mux>; - }; + vdd_12v0_sata: regulator@11 { + compatible = "regulator-fixed"; + regulator-name = "+12V_SATA"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_mux>; }; sound { diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 4555d01094b5..b3b5c12cbda9 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -608,157 +608,138 @@ power { }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_mux: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "+VDD_MUX"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; + vdd_mux: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "+VDD_MUX"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "+5V_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; + vdd_5v0_sys: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "+5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; - vdd_3v3_sys: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "+3.3V_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; + vdd_3v3_sys: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; - vdd_3v3_run: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "+3.3V_RUN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; + vdd_3v3_run: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_RUN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; - vdd_3v3_hdmi: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_run>; - }; + vdd_3v3_hdmi: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_run>; + }; - vdd_led: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "+VDD_LED"; - gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_mux>; - }; + vdd_led: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "+VDD_LED"; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_mux>; + }; - vdd_5v0_ts: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "+5V_VDD_TS_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_5v0_ts: regulator@6 { + compatible = "regulator-fixed"; + regulator-name = "+5V_VDD_TS_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; - vdd_usb1_vbus: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "+5V_USB_HS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_usb1_vbus: regulator@7 { + compatible = "regulator-fixed"; + regulator-name = "+5V_USB_HS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; - vdd_usb3_vbus: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "+5V_USB_SS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_usb3_vbus: regulator@8 { + compatible = "regulator-fixed"; + regulator-name = "+5V_USB_SS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; - vdd_3v3_panel: regulator@9 { - compatible = "regulator-fixed"; - reg = <9>; - regulator-name = "+3.3V_PANEL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_run>; - }; + vdd_3v3_panel: regulator@9 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_PANEL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_run>; + }; - vdd_3v3_lp0: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "+3.3V_LP0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* - * TODO: find a way to wire this up with the USB EHCI - * controllers so that it can be enabled on demand. - */ - regulator-always-on; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; + vdd_3v3_lp0: regulator@10 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_LP0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* + * TODO: find a way to wire this up with the USB EHCI + * controllers so that it can be enabled on demand. + */ + regulator-always-on; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; - vdd_hdmi_pll: regulator@11 { - compatible = "regulator-fixed"; - reg = <11>; - regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05_run>; - }; + vdd_hdmi_pll: regulator@11 { + compatible = "regulator-fixed"; + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05_run>; + }; - vdd_5v0_hdmi: regulator@12 { - compatible = "regulator-fixed"; - reg = <12>; - regulator-name = "+5V_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_5v0_hdmi: regulator@12 { + compatible = "regulator-fixed"; + regulator-name = "+5V_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; }; sound { diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 6a7a31c831c5..effdb303c7f7 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -1077,164 +1077,145 @@ power { panel: panel { compatible = "lg,lp129qe"; - + power-supply = <&vdd_3v3_panel>; backlight = <&backlight>; ddc-i2c-bus = <&dpaux>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_mux: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "+VDD_MUX"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; + vdd_mux: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "+VDD_MUX"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "+5V_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; + vdd_5v0_sys: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "+5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; - vdd_3v3_sys: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "+3.3V_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; + vdd_3v3_sys: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; - vdd_3v3_run: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "+3.3V_RUN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; + vdd_3v3_run: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_RUN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; - vdd_3v3_hdmi: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_run>; - }; + vdd_3v3_hdmi: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_run>; + }; - vdd_led: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "+VDD_LED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_mux>; - }; + vdd_led: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "+VDD_LED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_mux>; + }; - vdd_5v0_ts: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "+5V_VDD_TS_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_5v0_ts: regulator@6 { + compatible = "regulator-fixed"; + regulator-name = "+5V_VDD_TS_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; - vdd_usb1_vbus: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "+5V_USB_HS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_usb1_vbus: regulator@7 { + compatible = "regulator-fixed"; + regulator-name = "+5V_USB_HS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; - vdd_usb3_vbus: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "+5V_USB_SS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_usb3_vbus: regulator@8 { + compatible = "regulator-fixed"; + regulator-name = "+5V_USB_SS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; - vdd_3v3_panel: regulator@9 { - compatible = "regulator-fixed"; - reg = <9>; - regulator-name = "+3.3V_PANEL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_run>; - }; + vdd_3v3_panel: regulator@9 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_PANEL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_run>; + }; - vdd_3v3_lp0: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "+3.3V_LP0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* - * TODO: find a way to wire this up with the USB EHCI - * controllers so that it can be enabled on demand. - */ - regulator-always-on; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; + vdd_3v3_lp0: regulator@10 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_LP0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* + * TODO: find a way to wire this up with the USB EHCI + * controllers so that it can be enabled on demand. + */ + regulator-always-on; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; - vdd_hdmi_pll: regulator@11 { - compatible = "regulator-fixed"; - reg = <11>; - regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05_run>; - }; + vdd_hdmi_pll: regulator@11 { + compatible = "regulator-fixed"; + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05_run>; + }; - vdd_5v0_hdmi: regulator@12 { - compatible = "regulator-fixed"; - reg = <12>; - regulator-name = "+5V_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_5v0_hdmi: regulator@12 { + compatible = "regulator-fixed"; + regulator-name = "+5V_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; }; sound { diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index bdfbe26fa26a..b051d75d4642 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -666,79 +666,66 @@ panel: panel { backlight = <&backlight>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_5v0_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + vdd_5v0_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vdd_1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; + regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - pci_vdd_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vdd_1v05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + pci_vdd_reg: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vdd_pnl_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "vdd_pnl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + vdd_pnl_reg: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vdd_bl_reg: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + vdd_bl_reg: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vdd_5v0_hdmi: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "VDDIO_HDMI"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_reg>; - }; + vdd_5v0_hdmi: regulator@6 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_HDMI"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_reg>; }; sound { diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index c73510cd501c..049181421a86 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -92,44 +92,38 @@ sound { clock-names = "pll_a", "pll_a_out0", "mclk"; }; - regulators { - vcc_24v_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "vcc_24v"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - regulator-always-on; - }; + vcc_24v_reg: regulator@100 { + compatible = "regulator-fixed"; + regulator-name = "vcc_24v"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + regulator-always-on; + }; - vdd_5v0_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "vdd_5v0"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + vdd_5v0_reg: regulator@101 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - vdd_3v3_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "vdd_3v3"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + vdd_3v3_reg: regulator@102 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - vdd_1v8_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "vdd_1v8"; - vin-supply = <&vdd_3v3_reg>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; + vdd_1v8_reg: regulator@103 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8"; + vin-supply = <&vdd_3v3_reg>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; }; }; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index bfc9625a6c72..2a0e5754f50f 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -606,30 +606,22 @@ panel: panel { backlight = <&backlight>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - p5valw_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "+5valw"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + p5valw_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "+5valw"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - vdd_pnl_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "+3VS,vdd_pnl"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + vdd_pnl_reg: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "+3VS,vdd_pnl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; }; sound { diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts index 429e4605fbdb..378f23b2958b 100644 --- a/arch/arm/boot/dts/tegra20-plutux.dts +++ b/arch/arm/boot/dts/tegra20-plutux.dts @@ -60,44 +60,38 @@ sound { clock-names = "pll_a", "pll_a_out0", "mclk"; }; - regulators { - vcc_24v_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "vcc_24v"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - regulator-always-on; - }; + vcc_24v_reg: regulator@100 { + compatible = "regulator-fixed"; + regulator-name = "vcc_24v"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + regulator-always-on; + }; - vdd_5v0_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "vdd_5v0"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + vdd_5v0_reg: regulator@101 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - vdd_3v3_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "vdd_3v3"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + vdd_3v3_reg: regulator@102 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - vdd_1v8_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "vdd_1v8"; - vin-supply = <&vdd_3v3_reg>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; + vdd_1v8_reg: regulator@103 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8"; + vin-supply = <&vdd_3v3_reg>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; }; }; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 28dcff3b7d7e..9a1ab4bd43e0 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -828,81 +828,68 @@ panel: panel { ddc-i2c-bus = <&lvds_ddc>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_5v0_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + vdd_5v0_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vdd_1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; + regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vbus_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vdd_vbus_wup1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 0) 0>; - regulator-always-on; - regulator-boot-on; - }; + vbus_reg: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_vbus_wup1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 0) 0>; + regulator-always-on; + regulator-boot-on; + }; - vdd_pnl_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "vdd_pnl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + vdd_pnl_reg: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vdd_bl_reg: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + vdd_bl_reg: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vdd_hdmi: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "VDDIO_HDMI"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_reg>; - }; + vdd_hdmi: regulator@6 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_HDMI"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_reg>; }; sound { diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 20137fc578b1..95e6bccdb4f6 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -495,40 +495,25 @@ usb-phy@c5008000 { status = "okay"; }; - sdhci@c8000600 { + mmc@c8000600 { cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; bus-width = <4>; status = "okay"; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; - regulators { - compatible = "simple-bus"; - - #address-cells = <1>; - #size-cells = <0>; - - pci_vdd_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vdd_1v05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&pmic 2 0>; - enable-active-high; - }; + pci_vdd_reg: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&pmic 2 0>; + enable-active-high; }; }; diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts index 4dec27737238..44ced60315de 100644 --- a/arch/arm/boot/dts/tegra20-tec.dts +++ b/arch/arm/boot/dts/tegra20-tec.dts @@ -69,44 +69,38 @@ sound { clock-names = "pll_a", "pll_a_out0", "mclk"; }; - regulators { - vcc_24v_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "vcc_24v"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - regulator-always-on; - }; + vcc_24v_reg: regulator@100 { + compatible = "regulator-fixed"; + regulator-name = "vcc_24v"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + regulator-always-on; + }; - vdd_5v0_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "vdd_5v0"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + vdd_5v0_reg: regulator@101 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - vdd_3v3_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "vdd_3v3"; - vin-supply = <&vcc_24v_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + vdd_3v3_reg: regulator@102 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + vin-supply = <&vcc_24v_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - vdd_1v8_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "vdd_1v8"; - vin-supply = <&vdd_3v3_reg>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; + vdd_1v8_reg: regulator@103 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8"; + vin-supply = <&vdd_3v3_reg>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; }; }; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 5b26482a55b7..4bc87bc0c2a4 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -401,58 +401,47 @@ poweroff { gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - hdmi_vdd_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "avdd_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + hdmi_vdd_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - hdmi_pll_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; + hdmi_pll_reg: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; - vbus_reg: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(V, 2) 0>; - regulator-always-on; - regulator-boot-on; - }; + vbus_reg: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(V, 2) 0>; + regulator-always-on; + regulator-boot-on; + }; - pci_clk_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "pci_clk"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + pci_clk_reg: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "pci_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - pci_vdd_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "pci_vdd"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; + pci_vdd_reg: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "pci_vdd"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; }; sound { diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 59998d3708a1..ccc24674be03 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -613,58 +613,47 @@ panel: panel { ddc-i2c-bus = <&lvds_ddc>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_5v0_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + vdd_5v0_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vdd_1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; + regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vdd_pnl_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vdd_pnl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + vdd_pnl_reg: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vdd_bl_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + vdd_bl_reg: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; }; sound { diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index ef3ea08f8d19..3211c61f956c 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1984,118 +1984,103 @@ gpled2 { }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_5v_in_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_5v_in"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + vdd_5v_in_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v_in"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - chargepump_5v_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "chargepump_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - enable-active-high; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; + chargepump_5v_reg: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "chargepump_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; - ddr_reg: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v_in_reg>; - }; + ddr_reg: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v_in_reg>; + }; - vdd_5v_sata_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vdd_5v_sata"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v_in_reg>; - }; + vdd_5v_sata_reg: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v_sata"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v_in_reg>; + }; - usb1_vbus_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v_in_reg>; - }; + usb1_vbus_reg: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v_in_reg>; + }; - usb3_vbus_reg: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "usb3_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v_in_reg>; - }; + usb3_vbus_reg: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v_in_reg>; + }; - sys_3v3_reg: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "sys_3v3,vdd_3v3_alw"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v_in_reg>; - }; + sys_3v3_reg: regulator@6 { + compatible = "regulator-fixed"; + regulator-name = "sys_3v3,vdd_3v3_alw"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v_in_reg>; + }; - sys_3v3_pexs_reg: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "sys_3v3_pexs"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; + sys_3v3_pexs_reg: regulator@7 { + compatible = "regulator-fixed"; + regulator-name = "sys_3v3_pexs"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; - vdd_5v0_hdmi: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "+VDD_5V_HDMI"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&sys_3v3_reg>; - }; + vdd_5v0_hdmi: regulator@8 { + compatible = "regulator-fixed"; + regulator-name = "+VDD_5V_HDMI"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&sys_3v3_reg>; }; sound { diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts index a02ec5082287..4899e05a0d9c 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts @@ -9,87 +9,75 @@ / { model = "NVIDIA Tegra30 Cardhu A02 evaluation board"; compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30"; - sdhci@78000400 { + mmc@78000400 { status = "okay"; power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; bus-width = <4>; keep-power-in-suspend; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - ddr_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - }; + ddr_reg: regulator@100 { + compatible = "regulator-fixed"; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + }; - sys_3v3_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "sys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; - }; + sys_3v3_reg: regulator@101 { + compatible = "regulator-fixed"; + regulator-name = "sys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + }; - usb1_vbus_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; + usb1_vbus_reg: regulator@102 { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; - usb3_vbus_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "usb3_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; + usb3_vbus_reg: regulator@103 { + compatible = "regulator-fixed"; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; - vdd_5v0_reg: regulator@104 { - compatible = "regulator-fixed"; - reg = <104>; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - }; + vdd_5v0_reg: regulator@104 { + compatible = "regulator-fixed"; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + }; - vdd_bl_reg: regulator@105 { - compatible = "regulator-fixed"; - reg = <105>; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>; - }; + vdd_bl_reg: regulator@105 { + compatible = "regulator-fixed"; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts index 9234988624ec..c1c0ca628af1 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts @@ -11,99 +11,86 @@ / { model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board"; compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30"; - sdhci@78000400 { + mmc@78000400 { status = "okay"; power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>; bus-width = <4>; keep-power-in-suspend; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - ddr_reg: regulator@100 { - compatible = "regulator-fixed"; - regulator-name = "ddr"; - reg = <100>; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; - }; + ddr_reg: regulator@100 { + compatible = "regulator-fixed"; + regulator-name = "ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + }; - sys_3v3_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "sys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - }; + sys_3v3_reg: regulator@101 { + compatible = "regulator-fixed"; + regulator-name = "sys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + }; - usb1_vbus_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; + usb1_vbus_reg: regulator@102 { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; - usb3_vbus_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "usb3_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; + usb3_vbus_reg: regulator@103 { + compatible = "regulator-fixed"; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; + }; - vdd_5v0_reg: regulator@104 { - compatible = "regulator-fixed"; - reg = <104>; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pmic 8 GPIO_ACTIVE_HIGH>; - }; + vdd_5v0_reg: regulator@104 { + compatible = "regulator-fixed"; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pmic 8 GPIO_ACTIVE_HIGH>; + }; - vdd_bl_reg: regulator@105 { - compatible = "regulator-fixed"; - reg = <105>; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; - }; + vdd_bl_reg: regulator@105 { + compatible = "regulator-fixed"; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; + }; - vdd_bl2_reg: regulator@106 { - compatible = "regulator-fixed"; - reg = <106>; - regulator-name = "vdd_bl2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; - }; + vdd_bl2_reg: regulator@106 { + compatible = "regulator-fixed"; + regulator-name = "vdd_bl2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; }; i2c@7000d000 { diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index c166967b6c3f..c8dc3b6ab2f6 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -434,158 +434,139 @@ panel: panel { backlight = <&backlight>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_ac_bat_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_ac_bat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + vdd_ac_bat_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_ac_bat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - cam_1v8_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "cam_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; - vin-supply = <&vio_reg>; - }; + cam_1v8_reg: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "cam_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; + vin-supply = <&vio_reg>; + }; - cp_5v_reg: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "cp_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - enable-active-high; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; + cp_5v_reg: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "cp_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; - emmc_3v3_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "emmc_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; + emmc_3v3_reg: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "emmc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; - modem_3v3_reg: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "modem_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; - }; + modem_3v3_reg: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "modem_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; + }; - pex_hvdd_3v3_reg: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "pex_hvdd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; + pex_hvdd_3v3_reg: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "pex_hvdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; - vdd_cam1_ldo_reg: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "vdd_cam1_ldo"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; + vdd_cam1_ldo_reg: regulator@6 { + compatible = "regulator-fixed"; + regulator-name = "vdd_cam1_ldo"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; - vdd_cam2_ldo_reg: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "vdd_cam2_ldo"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; + vdd_cam2_ldo_reg: regulator@7 { + compatible = "regulator-fixed"; + regulator-name = "vdd_cam2_ldo"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; - vdd_cam3_ldo_reg: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "vdd_cam3_ldo"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; + vdd_cam3_ldo_reg: regulator@8 { + compatible = "regulator-fixed"; + regulator-name = "vdd_cam3_ldo"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; - vdd_com_reg: regulator@9 { - compatible = "regulator-fixed"; - reg = <9>; - regulator-name = "vdd_com"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; + vdd_com_reg: regulator@9 { + compatible = "regulator-fixed"; + regulator-name = "vdd_com"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; - vdd_fuse_3v3_reg: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "vdd_fuse_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; + vdd_fuse_3v3_reg: regulator@10 { + compatible = "regulator-fixed"; + regulator-name = "vdd_fuse_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; - vdd_pnl1_reg: regulator@11 { - compatible = "regulator-fixed"; - reg = <11>; - regulator-name = "vdd_pnl1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; + vdd_pnl1_reg: regulator@11 { + compatible = "regulator-fixed"; + regulator-name = "vdd_pnl1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; - vdd_vid_reg: regulator@12 { - compatible = "regulator-fixed"; - reg = <12>; - regulator-name = "vddio_vid"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; - gpio-open-drain; - vin-supply = <&vdd_5v0_reg>; - }; + vdd_vid_reg: regulator@12 { + compatible = "regulator-fixed"; + regulator-name = "vddio_vid"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + vin-supply = <&vdd_5v0_reg>; }; sound { From patchwork Tue Jun 16 13:51:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310350 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=vV9mIgIk; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV5Q0Dnxz9sRK for ; Tue, 16 Jun 2020 23:52:58 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728931AbgFPNw5 (ORCPT ); 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Tue, 16 Jun 2020 06:52:52 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 04/73] ARM: tegra: Remove battery-name property Date: Tue, 16 Jun 2020 15:51:29 +0200 Message-Id: <20200616135238.3001888-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding This property is not documented and will cause a validation failure. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-dalmore.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 1dfff574e371..584db54cd750 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -769,7 +769,6 @@ i2c@7000c000 { battery: smart-battery@b { compatible = "ti,bq20z45", "sbs,sbs-battery"; reg = <0xb>; - battery-name = "battery"; sbs,i2c-retry-count = <2>; sbs,poll-retry-count = <100>; power-supplies = <&charger>; From patchwork Tue Jun 16 13:51:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310352 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=GcI+noiG; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV5T6VZwz9sRK for ; Tue, 16 Jun 2020 23:53:01 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728917AbgFPNxB (ORCPT ); Tue, 16 Jun 2020 09:53:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728908AbgFPNxA (ORCPT ); Tue, 16 Jun 2020 09:53:00 -0400 Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD25FC061573 for ; Tue, 16 Jun 2020 06:52:59 -0700 (PDT) Received: by mail-wm1-x341.google.com with SMTP id d128so3173835wmc.1 for ; Tue, 16 Jun 2020 06:52:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZXEbv/x0T8NRWftaB6bwURGcBWmiOgCAbqfov9/KHNQ=; b=GcI+noiGq+iar/iB9yA/a6G+lmoNmtz702DbZ4kkXaeiOq0uu4/ohsCgQ9khUokXDX RAtBWdx0+DBSnNEn7PtwQyCUDTarkzbE2WwaRX7EGPXkopOPJ3R6yED6xCU4Kyi1Y4ys A2Xp3dWVyIQmC6gyr9LuNhguQ2LToFMcqHXuYzneXQeg16sZ3GgZYGmfW+JH8xJsUaU/ di6Vz5y2+RfQqMmWFtVUomfLiDZckEO8ycgzwIWT44HAC0HKD2x4fQXRV4jl0gxQsYUw Bc5Y1I5z5MMyxTMUN7XJUgFDiCqVJ830Fn5nACeMHD9V8r1dQ1ju+nEuNu0KShIQdME2 vGTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZXEbv/x0T8NRWftaB6bwURGcBWmiOgCAbqfov9/KHNQ=; b=IpCClyYW/fAYo7fkbE6cIKBKayr0zNpTRFeClUFNmn2RQ1tTszmQU9DcGK4HRVnlgy VOKbt9YoIM2ZvejGrO28Qj7oYGkLcVtfLikbq+gP7h4itOah98/2nVxXEnxyKzLBgBXo 7BZRFdUnBxjUE9TmsgE9NG2uLm95A/BLCT2sabqIPROP2XKj8GZNs4UafDkl2H9S2DaF rlAYCcl6rnCLx2EaAhv1O4bIS7SjcMAq4bVMWgFc3iiw/PeTGEBSnS+g8zRLlI/1Qd48 jBs4A27WfCJjbL9di/gEkozOpLuktca3GTmBibYdgyaFAIMBfpGL/7HRMvC5iOpc76be S6Xw== X-Gm-Message-State: AOAM531oAlPqnPkrT46S3vfuQlIkB7746AyLO27Nx7ite22ehKjeRZWU AiykNyd4hzti7XxY3y8eDS8= X-Google-Smtp-Source: ABdhPJwKRsi2fWVS01SU1sG57FGp8wzYiVSftb5oP8Yg8f8uc9tXrRvwipsqf5xc1OFluycle2Exyg== X-Received: by 2002:a05:600c:2218:: with SMTP id z24mr3269785wml.24.1592315578629; Tue, 16 Jun 2020 06:52:58 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id o15sm4079926wmm.31.2020.06.16.06.52.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:52:55 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 05/73] ARM: tegra: roth: Use the correct DSI/CSI supply Date: Tue, 16 Jun 2020 15:51:30 +0200 Message-Id: <20200616135238.3001888-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The correct DSI/CSI supply property is called vdd-dsi-csi-supply, so use that instead of the wrong vdd-supply property. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-roth.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index 5249afdca577..7378b5d6f2fa 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -37,7 +37,7 @@ host1x@50000000 { dsi@54300000 { status = "okay"; - vdd-supply = <&vdd_1v2_ap>; + avdd-dsi-csi-supply = <&vdd_1v2_ap>; panel@0 { compatible = "lg,lh500wx1-sd03"; From patchwork Tue Jun 16 13:51:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310353 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=dradM+XT; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV5X06j6z9sRN for ; Tue, 16 Jun 2020 23:53:04 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728928AbgFPNxD (ORCPT ); Tue, 16 Jun 2020 09:53:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728908AbgFPNxD (ORCPT ); Tue, 16 Jun 2020 09:53:03 -0400 Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9BFFC061573 for ; Tue, 16 Jun 2020 06:53:02 -0700 (PDT) Received: by mail-wm1-x341.google.com with SMTP id t194so3159112wmt.4 for ; Tue, 16 Jun 2020 06:53:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NcQyUR9ZMCNSxD7yzbRR2V9chBQB5uCLO5RENeG6ZPg=; b=dradM+XTFqtfIk1wbaLcrDc3FqQghNUwqkBA23/Q+SDlv1IEGaxnp5M7Yt+kPAymjT A3huBfelTXnU0x9tSR0GOtIeh4TRwlqQCYJZP+5mouXGtTkHqkVJ0EO2Abf8gwlx+Ibp TIcb1FhefLyWpB34AJsIeL0n5pi5GUITuQ5iwGZ57jgbohaXvHQjWjpr5a3L0Xk5/BPD IkwTxCFCNXjtUhkOAaM2QDnEALieTLEXXisoqMfgFOWQYhljpDsX1GAZeQd5JXm0t7Un wdT/6KQSvlw5pItHR6mVeUUdabTU7Ai3obwpKT45J26/64dqjzje52JaGw18xKNlTnYD rMLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NcQyUR9ZMCNSxD7yzbRR2V9chBQB5uCLO5RENeG6ZPg=; b=cGtfr93zbxuFZdYQ7k1J2VXTLTeUrg5UeOO/qaWD1cteTJVKgg7mtLVha6rFtu35Ai Hc5kP6YwNGac+q0+a3SjNUhFc8Rff/RAPZPRnngEK6xmfpuxZhZQQc8pw6B5T4+0lBm5 b3FpC2NqO5yI5PdeIXhQhHP9o9CkLwSvZq000bGgRv4s1nBJLW5/3nZhMg+REH/HVU3t 67cvOrDY0Dxqn8B7khwCf4EpVJ/2PsxdZrztCP8xSiTfJTMLAt6eCDXeZdfbDqrT6yNb 2x3SeIaA2nRceFHcjKR4Yon3L/y7HtGlbCY/R9IhWQFhbmDXZ3w0rF8nPv8ypz4SQW6W IV/A== X-Gm-Message-State: AOAM530YH0uAHmUJZclqIMBf9rZOTeIVCa7wtuIIoUu3cxle2vzEy0MH qNTuLnnwjEz2NzVVYrKSv4k= X-Google-Smtp-Source: ABdhPJw+XVbp6SdHrlPiQJidsycshiRYm0yP/7i8nx2fCykybpVhxL6NfQXcic+eGUBXuvoy4iA/KA== X-Received: by 2002:a05:600c:21c2:: with SMTP id x2mr3392321wmj.33.1592315581703; Tue, 16 Jun 2020 06:53:01 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id v19sm4088915wml.26.2020.06.16.06.52.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:53:00 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 06/73] ARM: tegra: tn7: Use the correct DSI/CSI supply Date: Tue, 16 Jun 2020 15:51:31 +0200 Message-Id: <20200616135238.3001888-7-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The correct DSI/CSI supply property is called vdd-dsi-csi-supply, so use that instead of the wrong vdd-supply property. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-tn7.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts index 90935db591a5..0e520ae1109d 100644 --- a/arch/arm/boot/dts/tegra114-tn7.dts +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -37,7 +37,7 @@ host1x@50000000 { dsi@54300000 { status = "okay"; - vdd-supply = <&vdd_1v2_ap>; + avdd-dsi-csi-supply = <&vdd_1v2_ap>; panel@0 { compatible = "lg,ld070wx3-sl01"; From patchwork Tue Jun 16 13:51:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310354 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=J9TB5th1; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV5h3vphz9sRK for ; Tue, 16 Jun 2020 23:53:12 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728934AbgFPNxL (ORCPT ); Tue, 16 Jun 2020 09:53:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728908AbgFPNxH (ORCPT ); Tue, 16 Jun 2020 09:53:07 -0400 Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8579C061573 for ; Tue, 16 Jun 2020 06:53:05 -0700 (PDT) Received: by mail-wm1-x341.google.com with SMTP id b82so2977775wmb.1 for ; Tue, 16 Jun 2020 06:53:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MwlkI0IF0P2g4pEYmpV2rRTm6Y2o1Uayf0Va5pno/2M=; b=J9TB5th1Gvl7xbRfuSYK8wj2IyJHVBzwQ32+CeTMfbHGWvHoiA7D1+qizOO0175fm3 POSdd0rNZf9USPTuAMyyIQqP/UBSwPL3VCXt5zY1XZr+M1tKVtq9ILEaVDLj1asIEAfU wxBgn5448hHF3RQbXs46V4yBpTGEgjJfXT191IkPcJ9jVWZeJclK6mPRn7r8iezfgquZ C+DKpwQdlIwtHJK35KwCQQLTf1V/alr0ocTwBZBDV3t3R6ufjf3alJcXf6rMt+3aTT8J Czk+qt1538blssJItJqexK9unH18t5y3jLC9JIEDCIyetevm9cmjU4MiCXpjlFpC1K81 B9iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MwlkI0IF0P2g4pEYmpV2rRTm6Y2o1Uayf0Va5pno/2M=; b=GcSctqawCp6mG5X4SgnhXQ1iq9ihu0eArwjC9iiqcyMG5MzAn0QyMx5bc3QIfqCnR7 KjOk7MbQPZiZu1LQtg/N3oc5NndQH/ZpvbkkSA6zZFT9jfhzDGh0fHsnA1xiFDw6lk/l qHLH5PnzJtxQy5R4PhWvG2tUo5l8autP1kTWo0d1K/ORbcTdra0WYomG0GRph6BD6iSF SS7KgH6tb/pLjyGYTWirpF5xuw/YdoUUXSFbaWCAsUABPKvCW/1lyqmaJrduD6+h71dI 0lELVPXJDq9bQmJVDJ8IjfHkSiFDtgyGrqmFvicBagyEX6OkPv6xZPAoQANEhnxuqcT4 PaHg== X-Gm-Message-State: AOAM532DV1DsYiOE8Azgn5Cx/X/E5LTp6bOLOPXrIus3AF+FFELP1UFL x2MwjtyqmdNgVZPXKWiDoCM= X-Google-Smtp-Source: ABdhPJzfU4Y+cwFeWdou8smoaFJ5Bv8iXBsqj0PmFxhSgk6NpofZY/8ZKcUEXC38V3ewrqU8aOSunw== X-Received: by 2002:a1c:9ec4:: with SMTP id h187mr3314361wme.27.1592315584601; Tue, 16 Jun 2020 06:53:04 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id a3sm28145691wrp.91.2020.06.16.06.53.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:53:03 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 07/73] ARM: tegra: Do not mark host1x as simple bus Date: Tue, 16 Jun 2020 15:51:32 +0200 Message-Id: <20200616135238.3001888-8-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The host1x is not a simple bus, so drop the corresponding compatible string. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 2 +- arch/arm/boot/dts/tegra124.dtsi | 2 +- arch/arm/boot/dts/tegra20.dtsi | 2 +- arch/arm/boot/dts/tegra30.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 01a81d380f1f..be048aa553ee 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -18,7 +18,7 @@ memory@80000000 { }; host1x@50000000 { - compatible = "nvidia,tegra114-host1x", "simple-bus"; + compatible = "nvidia,tegra114-host1x"; reg = <0x50000000 0x00028000>; interrupts = , /* syncpt */ ; /* general */ diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 94cac13d3e50..fc124343658e 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -85,7 +85,7 @@ pci@2,0 { }; host1x@50000000 { - compatible = "nvidia,tegra124-host1x", "simple-bus"; + compatible = "nvidia,tegra124-host1x"; reg = <0x0 0x50000000 0x0 0x00034000>; interrupts = , /* syncpt */ ; /* general */ diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index c3b8ad53b967..7319df2fcd3e 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -31,7 +31,7 @@ vde_pool: vde@400 { }; host1x@50000000 { - compatible = "nvidia,tegra20-host1x", "simple-bus"; + compatible = "nvidia,tegra20-host1x"; reg = <0x50000000 0x00024000>; interrupts = , /* syncpt */ ; /* general */ diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index d2d05f1da274..0b58863e570e 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -111,7 +111,7 @@ vde_pool: vde@400 { }; host1x@50000000 { - compatible = "nvidia,tegra30-host1x", "simple-bus"; + compatible = "nvidia,tegra30-host1x"; reg = <0x50000000 0x00024000>; interrupts = , /* syncpt */ ; /* general */ From patchwork Tue Jun 16 13:51:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310355 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Tue, 16 Jun 2020 06:53:06 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id 138sm4353784wma.23.2020.06.16.06.53.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:53:05 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 08/73] ARM: tegra: Add missing host1x properties Date: Tue, 16 Jun 2020 15:51:33 +0200 Message-Id: <20200616135238.3001888-9-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The host1x device tree bindings require the clock- and interrupt-names properties to be present, so add them where missing. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 2 ++ arch/arm/boot/dts/tegra124.dtsi | 2 ++ arch/arm/boot/dts/tegra20.dtsi | 2 ++ arch/arm/boot/dts/tegra30.dtsi | 2 ++ 4 files changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index be048aa553ee..a0ac9ea9ec9d 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -22,7 +22,9 @@ host1x@50000000 { reg = <0x50000000 0x00028000>; interrupts = , /* syncpt */ ; /* general */ + interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA114_CLK_HOST1X>; + clock-names = "host1x"; resets = <&tegra_car 28>; reset-names = "host1x"; iommus = <&mc TEGRA_SWGROUP_HC>; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index fc124343658e..1afed8496c95 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -89,7 +89,9 @@ host1x@50000000 { reg = <0x0 0x50000000 0x0 0x00034000>; interrupts = , /* syncpt */ ; /* general */ + interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA124_CLK_HOST1X>; + clock-names = "host1x"; resets = <&tegra_car 28>; reset-names = "host1x"; iommus = <&mc TEGRA_SWGROUP_HC>; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 7319df2fcd3e..f0a172c61b26 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -35,7 +35,9 @@ host1x@50000000 { reg = <0x50000000 0x00024000>; interrupts = , /* syncpt */ ; /* general */ + interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA20_CLK_HOST1X>; + clock-names = "host1x"; resets = <&tegra_car 28>; reset-names = "host1x"; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 0b58863e570e..27000f0ba35b 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -115,7 +115,9 @@ host1x@50000000 { reg = <0x50000000 0x00024000>; interrupts = , /* syncpt */ ; /* general */ + interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA30_CLK_HOST1X>; + clock-names = "host1x"; resets = <&tegra_car 28>; reset-names = "host1x"; iommus = <&mc TEGRA_SWGROUP_HC>; From patchwork Tue Jun 16 13:51:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310356 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=VTca1UDW; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV5j5kQpz9sSg for ; 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Tue, 16 Jun 2020 06:53:07 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 09/73] ARM: tegra: gr2d is not backwards-compatible Date: Tue, 16 Jun 2020 15:51:34 +0200 Message-Id: <20200616135238.3001888-10-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The instantiation of gr2d in Tegra114 is not backwards-compatible with the version found on earlier chips. Remove the misleading compatible string. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index a0ac9ea9ec9d..d583dfba688f 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -35,7 +35,7 @@ host1x@50000000 { ranges = <0x54000000 0x54000000 0x01000000>; gr2d@54140000 { - compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d"; + compatible = "nvidia,tegra114-gr2d"; reg = <0x54140000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA114_CLK_GR2D>; From patchwork Tue Jun 16 13:51:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310357 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=C6nNcEvD; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV5k1Vmwz9sRK for ; Tue, 16 Jun 2020 23:53:14 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728947AbgFPNxN (ORCPT ); Tue, 16 Jun 2020 09:53:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728869AbgFPNxN (ORCPT ); Tue, 16 Jun 2020 09:53:13 -0400 Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6EEAC06174E for ; Tue, 16 Jun 2020 06:53:11 -0700 (PDT) Received: by mail-wm1-x341.google.com with SMTP id l26so2966441wme.3 for ; Tue, 16 Jun 2020 06:53:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CsJOLSAV7jrFDpiST38oXr0om9CoIKPDCCZXQlS9m+Q=; b=C6nNcEvDBdDRoblLxhN8crE9V0SWAqmjp8IXfNd70fYoZSj08a+KNMXYpm2Ep0mkGs 04ztt55i2rIDsg9NqBibK7gjtsS1RsgWepHq96duxmdHx/BqXi8yjtlTKea7tETXxnBd TP2mOSmfu8UbeN+b9tinPBznIPZbFp2rgCRwTErfeBhm8pcP1lVdlMMVO051Bx3Y6YUq JMiWnei717U/W4qh1myEpoaEeNHN1gBa8eJ1gE1k6HBwxSeewyADUMg/b9/OX6zqWKzC YI5yy9NuKEP22YheElSCpdqbuyiw3AFV29GaD/rfl66C4/o6VF8JGcO3IrvBK1PCJ5En ajMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CsJOLSAV7jrFDpiST38oXr0om9CoIKPDCCZXQlS9m+Q=; b=cR3LnR59GPtD2gObOZMXG/mHNHdLDR6H2pVBs0VKOD6YjshMX6iWlnFqRR7qOlvnrZ wtoD+fJd6fzRxxb2VHeHkmhha0tnzQG7h+n2uCdUSlgsVCKfGzZk9JUGlLzst7yF8k+x E4I4U5z249nYItvJOq+yt/7jKoexm2Lozvy8BGNsTOnHYnO/8+IeghGplT6anyvA4qTY BC70Yvf+gssBiROZGbf0r+bCLeUfpxcb8n9RYQ5IWzwQavLFSXQyarY+pH4mtqfZ2SDI WYrfa49uppdGH/2a4IrVb+DTVjm/KupmeldIqbIvEceuekRlxYp2jebgHvhcgYFLz5pR +c2w== X-Gm-Message-State: AOAM530SfnTbPHeIiY43QWvZmoLh0tNfuqKmBB1wSi73wniw7jnI/etX n+K9p6U/v6EtIMUyJiO8ONs= X-Google-Smtp-Source: ABdhPJzjqNfVbW94/FWweHsM1LMjOQFMMEaox+XR5ER4LbkHjLbu5AdkLhtiA+njLuz+SS46g3QF/g== X-Received: by 2002:a7b:c1d4:: with SMTP id a20mr3238882wmj.153.1592315590607; Tue, 16 Jun 2020 06:53:10 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id r7sm3881747wmh.46.2020.06.16.06.53.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:53:09 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 10/73] ARM: tegra: gr3d is not backwards-compatible Date: Tue, 16 Jun 2020 15:51:35 +0200 Message-Id: <20200616135238.3001888-11-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The instantiation of gr3d in Tegra114 is not backwards-compatible with the version found on earlier chips. Remove the misleading compatible string. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index d583dfba688f..392f06107b32 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -46,7 +46,7 @@ gr2d@54140000 { }; gr3d@54180000 { - compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d"; + compatible = "nvidia,tegra114-gr3d"; reg = <0x54180000 0x00040000>; clocks = <&tegra_car TEGRA114_CLK_GR3D>; resets = <&tegra_car 24>; From patchwork Tue Jun 16 13:51:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310358 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=bSZJDYwI; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV5n1M2Lz9sRK for ; Tue, 16 Jun 2020 23:53:17 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728899AbgFPNxP (ORCPT ); Tue, 16 Jun 2020 09:53:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728869AbgFPNxP (ORCPT ); Tue, 16 Jun 2020 09:53:15 -0400 Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD23BC061573 for ; Tue, 16 Jun 2020 06:53:13 -0700 (PDT) Received: by mail-wr1-x443.google.com with SMTP id r7so20893035wro.1 for ; Tue, 16 Jun 2020 06:53:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FT2XLpfBDjhksZtGFD0bEBzgpWT5Qpglrh+vmdOd/oo=; b=bSZJDYwIxLNahacewvcxphbOsAC+HSNSBsJRptZpwLITEgOkA4y2rzTTQqqYhx19H5 ExAYqLTb0vgPpv8EwOVx5eVZ57iVTa6OaQo7awaM3WWiI78WbQ7lsO709u8HrGxj5hLB 2Xvgy6dKKcYai63He7ezWodaclgfNYlocbgNPYpvH3bwxvI00J4eiu5wK4HZTqbHOft9 1rlHorDTTMDmwS8CeRuYi+7C9EieSEdDoyYY4dUFdF+HJrkiWsu7yhA7DXWK03cBWRbK xUw7+LecocwcllFSp5EFKb9PjuOJ2c8q+X6D4jYxRi3FEO8wigot4yO4YNvZgFjVYQDY RmKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FT2XLpfBDjhksZtGFD0bEBzgpWT5Qpglrh+vmdOd/oo=; b=gnekKAci05wBKx42dmcVVSkEyC3Rk1dEzqbQqmwYBo9vgpNgjFbdwe85YXADWLez4k C4IzIAKHyyMoCzckcAgEkDEtmJH6J+bXpHhQjU+OkTV9aT5IL4lVRlodnQZ/GpMa4zGp RRTLYT/xOUlzpthxosud0+F7Uqhch9YfOIkfROFCzDqhcr4sudReY67f0aEemTO4p6Ee 9RYnvat9KtsHHbKQ7E37Y44vF0E+LQEQ1BiOOV8Rjac52pUm++fqDSW6mPkdsLVvCone QqLQ30FZu97WTPI3Lt8drB+22vibSFbRt66L8PAB36FLR+KZAbEo900bDpSJDCmwLNyE 9m5A== X-Gm-Message-State: AOAM531R6Xv5JQvwbgu4F3loCSuDsHypMeHgouFo24awHORRSQ5ofq/V UXd0ymx7duW2Z8PY1vytunLUSJHH X-Google-Smtp-Source: ABdhPJxbMvXDt5cbMxmncdZsxboagCBEEqp5k2CMTYXn6m3dztuFwDsTjCU4ppfvevzOAUYUtcvI/Q== X-Received: by 2002:adf:c385:: with SMTP id p5mr3239900wrf.409.1592315592683; Tue, 16 Jun 2020 06:53:12 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id c81sm4199809wmd.42.2020.06.16.06.53.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:53:11 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 11/73] ARM: tegra: The Tegra114 DC is not backwards-compatible Date: Tue, 16 Jun 2020 15:51:36 +0200 Message-Id: <20200616135238.3001888-12-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The display controller on Tegra114 is in fact not backwards-compatible with the instantiation found on earlier SoCs. Drop the misleading compatible string. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 392f06107b32..a06b88b01ef3 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -56,7 +56,7 @@ gr3d@54180000 { }; dc@54200000 { - compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; + compatible = "nvidia,tegra114-dc"; reg = <0x54200000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA114_CLK_DISP1>, @@ -75,7 +75,7 @@ rgb { }; dc@54240000 { - compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; + compatible = "nvidia,tegra114-dc"; reg = <0x54240000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA114_CLK_DISP2>, From patchwork Tue Jun 16 13:51:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310359 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=ryLdf2LX; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV5v4L9jz9sRK for ; Tue, 16 Jun 2020 23:53:23 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728928AbgFPNxV (ORCPT ); Tue, 16 Jun 2020 09:53:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728869AbgFPNxR (ORCPT ); Tue, 16 Jun 2020 09:53:17 -0400 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03132C061573 for ; Tue, 16 Jun 2020 06:53:16 -0700 (PDT) Received: by mail-wm1-x344.google.com with SMTP id r15so3155523wmh.5 for ; Tue, 16 Jun 2020 06:53:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tpIq7vACm4SRxkjFZliC+FSY9hil6puRxlsauHDzKe8=; b=ryLdf2LXTxwgiV7DZWr7/VLXC2xIGtU0POGsbmLk+xrVeTszRvGXuy3BDIzboqpXE+ r1KRxGTBTTxRGoFe9ZZ1i2s4hPEejXZ6LO6nvh0OKrkN351IVql1yUhXR0MQbdEnytup x1Lx16+Vm27p4+qolpdSosQcDD1eBOWhvh6Q63I8A9r3/iX+SK8UsC1qB3pIEkS8+TBL DxnXEv9F5tWTc+yTXvG2g6vTuhP5fvW+YvHj2syCLd3UNvpt8sn2i24KEftZsKpiNquz niogcl9am/UShqHR9vgd1Tr+y5FkmUiXjy7TIAJKDbDIvQQKpyh5FG8iVhKIY8CrTq21 3gMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tpIq7vACm4SRxkjFZliC+FSY9hil6puRxlsauHDzKe8=; b=nxOLamtva2U18bMTbVOVxW6/bCdSr7bR87Xw1TviNQ2WYT9pfY1R4UQ7uNXJ+NijRN EYfVpQJ0m3qwjuKbsB4j8s06I6PjmCaahxPgqfT5NVqlvCCdgBRKCMMTEWxdwXkKm3jl ukRwHlF4zv9u5DX1VXGjGcHZ6XHS+Ek51UamTs+iELVp5ZwhcFExV+f6G/10qlRAURyy Mws/8gK/YdBcAToRnslRfMgnvCY1nX93F0WVObWylXFrNTyGfg8dnfaBtoSEJAU0DzDC 9CM47+d88OeHprf45xYG9sCKX3E+Jf2H5JbzKiXN3tUmZCT0YeisQ7dP6LvUZzU3JKoT SyHw== X-Gm-Message-State: AOAM5339ieLlR+CiGUOkQj6bHHzrN8jRIiYTtHQvipUXz8MdJY0y2hR7 mGSxrB5r0XoLPyiiSbf/ncLbhrvc X-Google-Smtp-Source: ABdhPJzipveQTxSMnAX+CCSmUY/8CMrXker9nYOnhziBKgxrErWzwb0f+Alxp/k8cVnTn0Fsbmy3/g== X-Received: by 2002:a1c:c302:: with SMTP id t2mr3273849wmf.72.1592315594678; Tue, 16 Jun 2020 06:53:14 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id o9sm3983949wmh.37.2020.06.16.06.53.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:53:13 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 12/73] ARM: tegra: Drop display controller parent clocks on Tegra114 Date: Tue, 16 Jun 2020 15:51:37 +0200 Message-Id: <20200616135238.3001888-13-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The parent clocks are determined by the output that will be used, not by the display controller that drives the output. Drop the parent clocks from the display controller device tree nodes. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 10 ++++------ arch/arm/boot/dts/tegra124.dtsi | 10 ++++------ arch/arm/boot/dts/tegra20.dtsi | 10 ++++------ arch/arm/boot/dts/tegra30.dtsi | 10 ++++------ 4 files changed, 16 insertions(+), 24 deletions(-) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index a06b88b01ef3..23df7a5f37d3 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -59,9 +59,8 @@ dc@54200000 { compatible = "nvidia,tegra114-dc"; reg = <0x54200000 0x00040000>; interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_DISP1>, - <&tegra_car TEGRA114_CLK_PLL_P>; - clock-names = "dc", "parent"; + clocks = <&tegra_car TEGRA114_CLK_DISP1>; + clock-names = "dc"; resets = <&tegra_car 27>; reset-names = "dc"; @@ -78,9 +77,8 @@ dc@54240000 { compatible = "nvidia,tegra114-dc"; reg = <0x54240000 0x00040000>; interrupts = ; - clocks = <&tegra_car TEGRA114_CLK_DISP2>, - <&tegra_car TEGRA114_CLK_PLL_P>; - clock-names = "dc", "parent"; + clocks = <&tegra_car TEGRA114_CLK_DISP2>; + clock-names = "dc"; resets = <&tegra_car 26>; reset-names = "dc"; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 1afed8496c95..2c992e8e3594 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -105,9 +105,8 @@ dc@54200000 { compatible = "nvidia,tegra124-dc"; reg = <0x0 0x54200000 0x0 0x00040000>; interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DISP1>, - <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "dc", "parent"; + clocks = <&tegra_car TEGRA124_CLK_DISP1>; + clock-names = "dc"; resets = <&tegra_car 27>; reset-names = "dc"; @@ -120,9 +119,8 @@ dc@54240000 { compatible = "nvidia,tegra124-dc"; reg = <0x0 0x54240000 0x0 0x00040000>; interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DISP2>, - <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "dc", "parent"; + clocks = <&tegra_car TEGRA124_CLK_DISP2>; + clock-names = "dc"; resets = <&tegra_car 26>; reset-names = "dc"; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index f0a172c61b26..8b6909839f59 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -103,9 +103,8 @@ dc@54200000 { compatible = "nvidia,tegra20-dc"; reg = <0x54200000 0x00040000>; interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_DISP1>, - <&tegra_car TEGRA20_CLK_PLL_P>; - clock-names = "dc", "parent"; + clocks = <&tegra_car TEGRA20_CLK_DISP1>; + clock-names = "dc"; resets = <&tegra_car 27>; reset-names = "dc"; @@ -120,9 +119,8 @@ dc@54240000 { compatible = "nvidia,tegra20-dc"; reg = <0x54240000 0x00040000>; interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_DISP2>, - <&tegra_car TEGRA20_CLK_PLL_P>; - clock-names = "dc", "parent"; + clocks = <&tegra_car TEGRA20_CLK_DISP2>; + clock-names = "dc"; resets = <&tegra_car 26>; reset-names = "dc"; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 27000f0ba35b..23fedb76e5ae 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -200,9 +200,8 @@ dc@54200000 { compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc"; reg = <0x54200000 0x00040000>; interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_DISP1>, - <&tegra_car TEGRA30_CLK_PLL_P>; - clock-names = "dc", "parent"; + clocks = <&tegra_car TEGRA30_CLK_DISP1>; + clock-names = "dc"; resets = <&tegra_car 27>; reset-names = "dc"; @@ -219,9 +218,8 @@ dc@54240000 { compatible = "nvidia,tegra30-dc"; reg = <0x54240000 0x00040000>; interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_DISP2>, - <&tegra_car TEGRA30_CLK_PLL_P>; - clock-names = "dc", "parent"; + clocks = <&tegra_car TEGRA30_CLK_DISP2>; + clock-names = "dc"; resets = <&tegra_car 26>; reset-names = "dc"; From patchwork Tue Jun 16 13:51:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310360 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; 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Tue, 16 Jun 2020 06:53:16 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id v19sm4090072wml.26.2020.06.16.06.53.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:53:15 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcel Ziswiler , Philippe Schenker Subject: [PATCH 13/73] ARM: tegra: Rename sdhci nodes to mmc Date: Tue, 16 Jun 2020 15:51:38 +0200 Message-Id: <20200616135238.3001888-14-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The new json-schema based validation tools require SD/MMC controller nodes to be named mmc. Rename all references to them. Cc: Marcel Ziswiler Cc: Philippe Schenker Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-dalmore.dts | 4 ++-- arch/arm/boot/dts/tegra114-roth.dts | 4 ++-- arch/arm/boot/dts/tegra114-tn7.dts | 2 +- arch/arm/boot/dts/tegra114.dtsi | 8 ++++---- arch/arm/boot/dts/tegra124-apalis-eval.dts | 4 ++-- arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts | 4 ++-- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 2 +- arch/arm/boot/dts/tegra124-apalis.dtsi | 2 +- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 4 ++-- arch/arm/boot/dts/tegra124-nyan-big.dts | 2 +- arch/arm/boot/dts/tegra124-nyan.dtsi | 6 +++--- arch/arm/boot/dts/tegra124-venice2.dts | 4 ++-- arch/arm/boot/dts/tegra124.dtsi | 8 ++++---- arch/arm/boot/dts/tegra20-colibri-eval-v3.dts | 2 +- arch/arm/boot/dts/tegra20-colibri-iris.dts | 2 +- arch/arm/boot/dts/tegra20-harmony.dts | 4 ++-- arch/arm/boot/dts/tegra20-paz00.dts | 4 ++-- arch/arm/boot/dts/tegra20-seaboard.dts | 6 +++--- arch/arm/boot/dts/tegra20-ventana.dts | 6 +++--- arch/arm/boot/dts/tegra20.dtsi | 8 ++++---- arch/arm/boot/dts/tegra30-apalis-eval.dts | 4 ++-- arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts | 4 ++-- arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | 2 +- arch/arm/boot/dts/tegra30-apalis.dtsi | 2 +- arch/arm/boot/dts/tegra30-beaver.dts | 4 ++-- arch/arm/boot/dts/tegra30-cardhu.dtsi | 4 ++-- arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 2 +- arch/arm/boot/dts/tegra30-colibri.dtsi | 2 +- arch/arm/boot/dts/tegra30.dtsi | 8 ++++---- 29 files changed, 59 insertions(+), 59 deletions(-) diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 584db54cd750..c04162ddec3c 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1108,14 +1108,14 @@ i2s@70080400 { }; }; - sdhci@78000400 { + mmc@78000400 { cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; bus-width = <4>; status = "okay"; }; - sdhci@78000600 { + mmc@78000600 { bus-width = <8>; status = "okay"; non-removable; diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index 7378b5d6f2fa..07960171fabe 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -962,7 +962,7 @@ pmc@7000e400 { }; /* SD card */ - sdhci@78000400 { + mmc@78000400 { status = "okay"; bus-width = <4>; vqmmc-supply = <&vddio_sdmmc3>; @@ -971,7 +971,7 @@ sdhci@78000400 { }; /* eMMC */ - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts index 0e520ae1109d..745d234b105b 100644 --- a/arch/arm/boot/dts/tegra114-tn7.dts +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -242,7 +242,7 @@ pmc@7000e400 { }; /* eMMC */ - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 23df7a5f37d3..69e0e3eeffb4 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -644,7 +644,7 @@ mipi: mipi@700e3000 { #nvidia,mipi-calibrate-cells = <1>; }; - sdhci@78000000 { + mmc@78000000 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000000 0x200>; interrupts = ; @@ -655,7 +655,7 @@ sdhci@78000000 { status = "disabled"; }; - sdhci@78000200 { + mmc@78000200 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000200 0x200>; interrupts = ; @@ -666,7 +666,7 @@ sdhci@78000200 { status = "disabled"; }; - sdhci@78000400 { + mmc@78000400 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000400 0x200>; interrupts = ; @@ -677,7 +677,7 @@ sdhci@78000400 { status = "disabled"; }; - sdhci@78000600 { + mmc@78000600 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000600 0x200>; interrupts = ; diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts index ceb3f6388c7d..28c29b6813a7 100644 --- a/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts @@ -130,7 +130,7 @@ usb@70090000 { }; /* Apalis MMC1 */ - sdhci@700b0000 { + mmc@700b0000 { status = "okay"; bus-width = <4>; /* MMC1_CD# */ @@ -139,7 +139,7 @@ sdhci@700b0000 { }; /* Apalis SD1 */ - sdhci@700b0400 { + mmc@700b0400 { status = "okay"; bus-width = <4>; /* SD1_CD# */ diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts index 826b776fbe6f..f3afde410615 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts @@ -132,7 +132,7 @@ usb@70090000 { }; /* Apalis MMC1 */ - sdhci@700b0000 { + mmc@700b0000 { status = "okay"; bus-width = <4>; /* MMC1_CD# */ @@ -141,7 +141,7 @@ sdhci@700b0000 { }; /* Apalis SD1 */ - sdhci@700b0400 { + mmc@700b0400 { status = "okay"; bus-width = <4>; /* SD1_CD# */ diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 1cc080fd062e..3fdc6ff32b0c 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -1909,7 +1909,7 @@ usb3-1 { }; /* eMMC */ - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index f2b243d98c7c..29ceeba1e7b1 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -1901,7 +1901,7 @@ usb3-1 { }; /* eMMC */ - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index e97943871fd8..289bf6e99041 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1797,7 +1797,7 @@ usb3-0 { }; /* SD card */ - sdhci@700b0400 { + mmc@700b0400 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; @@ -1807,7 +1807,7 @@ sdhci@700b0400 { }; /* eMMC */ - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts index d97791b98958..4d14dec21af6 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big.dts +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts @@ -20,7 +20,7 @@ panel: panel { ddc-i2c-bus = <&dpaux>; }; - sdhci@700b0400 { /* SD Card on this bus */ + mmc@700b0400 { /* SD Card on this bus */ wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index b3b5c12cbda9..41a3db6649c5 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -491,7 +491,7 @@ sdhci0_pwrseq: sdhci0_pwrseq { reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; }; - sdhci@700b0000 { /* WiFi/BT on this bus */ + mmc@700b0000 { /* WiFi/BT on this bus */ status = "okay"; bus-width = <4>; no-1-8-v; @@ -502,7 +502,7 @@ sdhci@700b0000 { /* WiFi/BT on this bus */ keep-power-in-suspend; }; - sdhci@700b0400 { /* SD Card on this bus */ + mmc@700b0400 { /* SD Card on this bus */ status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; @@ -511,7 +511,7 @@ sdhci@700b0400 { /* SD Card on this bus */ vqmmc-supply = <&vddio_sdmmc3>; }; - sdhci@700b0600 { /* eMMC on this bus */ + mmc@700b0600 { /* eMMC on this bus */ status = "okay"; bus-width = <8>; no-1-8-v; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index effdb303c7f7..584a3b2125cd 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -998,7 +998,7 @@ usb3-1 { }; }; - sdhci@700b0400 { + mmc@700b0400 { cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; @@ -1007,7 +1007,7 @@ sdhci@700b0400 { vqmmc-supply = <&vddio_sdmmc3>; }; - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 2c992e8e3594..76c1ef923213 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -833,7 +833,7 @@ usb3-1 { }; }; - sdhci@700b0000 { + mmc@700b0000 { compatible = "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0000 0x0 0x200>; interrupts = ; @@ -843,7 +843,7 @@ sdhci@700b0000 { status = "disabled"; }; - sdhci@700b0200 { + mmc@700b0200 { compatible = "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0200 0x0 0x200>; interrupts = ; @@ -853,7 +853,7 @@ sdhci@700b0200 { status = "disabled"; }; - sdhci@700b0400 { + mmc@700b0400 { compatible = "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0400 0x0 0x200>; interrupts = ; @@ -863,7 +863,7 @@ sdhci@700b0400 { status = "disabled"; }; - sdhci@700b0600 { + mmc@700b0600 { compatible = "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0600 0x0 0x200>; interrupts = ; diff --git a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts index 37ad508b61d9..a05fb3853da8 100644 --- a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts @@ -183,7 +183,7 @@ can@0 { }; /* SD/MMC */ - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; bus-width = <4>; cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index af4740847769..425494b9ed54 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -171,7 +171,7 @@ spi@7000da00 { }; /* SD/MMC */ - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; bus-width = <4>; cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index b051d75d4642..86494cb4d5a1 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -613,7 +613,7 @@ usb-phy@c5008000 { status = "okay"; }; - sdhci@c8000200 { + mmc@c8000200 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; @@ -621,7 +621,7 @@ sdhci@c8000200 { bus-width = <4>; }; - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 2a0e5754f50f..91b6bb82e960 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -543,7 +543,7 @@ usb-phy@c5008000 { status = "okay"; }; - sdhci@c8000000 { + mmc@c8000000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; @@ -551,7 +551,7 @@ sdhci@c8000000 { bus-width = <4>; }; - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 9a1ab4bd43e0..f1baf16c5010 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -760,14 +760,14 @@ usb-phy@c5008000 { status = "okay"; }; - sdhci@c8000000 { + mmc@c8000000 { status = "okay"; power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; bus-width = <4>; keep-power-in-suspend; }; - sdhci@c8000400 { + mmc@c8000400 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; @@ -775,7 +775,7 @@ sdhci@c8000400 { bus-width = <4>; }; - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index ccc24674be03..b158771ac0b7 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -554,14 +554,14 @@ usb-phy@c5008000 { status = "okay"; }; - sdhci@c8000000 { + mmc@c8000000 { status = "okay"; power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; bus-width = <4>; keep-power-in-suspend; }; - sdhci@c8000400 { + mmc@c8000400 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; @@ -569,7 +569,7 @@ sdhci@c8000400 { bus-width = <4>; }; - sdhci@c8000600 { + mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 8b6909839f59..9e71ed84bf28 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -805,7 +805,7 @@ phy3: usb-phy@c5008000 { status = "disabled"; }; - sdhci@c8000000 { + mmc@c8000000 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000000 0x200>; interrupts = ; @@ -815,7 +815,7 @@ sdhci@c8000000 { status = "disabled"; }; - sdhci@c8000200 { + mmc@c8000200 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000200 0x200>; interrupts = ; @@ -825,7 +825,7 @@ sdhci@c8000200 { status = "disabled"; }; - sdhci@c8000400 { + mmc@c8000400 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000400 0x200>; interrupts = ; @@ -835,7 +835,7 @@ sdhci@c8000400 { status = "disabled"; }; - sdhci@c8000600 { + mmc@c8000600 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000600 0x200>; interrupts = ; diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index b39c26806bf2..9f653ef41da4 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -120,7 +120,7 @@ spi@7000dc00 { }; /* Apalis SD1 */ - sdhci@78000000 { + mmc@78000000 { status = "okay"; bus-width = <4>; /* SD1_CD# */ @@ -129,7 +129,7 @@ sdhci@78000000 { }; /* Apalis MMC1 */ - sdhci@78000400 { + mmc@78000400 { status = "okay"; bus-width = <8>; /* MMC1_CD# */ diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts index e29dca92ba0a..dc633e529822 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts @@ -121,7 +121,7 @@ spi@7000dc00 { }; /* Apalis SD1 */ - sdhci@78000000 { + mmc@78000000 { status = "okay"; bus-width = <4>; /* SD1_CD# */ @@ -130,7 +130,7 @@ sdhci@78000000 { }; /* Apalis MMC1 */ - sdhci@78000400 { + mmc@78000400 { status = "okay"; bus-width = <8>; /* MMC1_CD# */ diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi index 387b17458e22..9421063cd86c 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi @@ -1112,7 +1112,7 @@ i2s@70080500 { }; /* eMMC */ - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 6648506f3aa4..d13f6b0c7c0c 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -1094,7 +1094,7 @@ i2s@70080500 { }; /* eMMC */ - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 3211c61f956c..e0624b74fb50 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1922,7 +1922,7 @@ i2s@70080400 { }; }; - sdhci@78000000 { + mmc@78000000 { status = "okay"; vqmmc-supply = <&ldo5_reg>; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; @@ -1931,7 +1931,7 @@ sdhci@78000000 { bus-width = <4>; }; - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index c8dc3b6ab2f6..dab9989fa760 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -384,7 +384,7 @@ i2s@70080400 { }; }; - sdhci@78000000 { + mmc@78000000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; @@ -392,7 +392,7 @@ sdhci@78000000 { bus-width = <4>; }; - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index 8e106e784dce..7d4a6ca4936a 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -98,7 +98,7 @@ can@0 { }; /* SD/MMC */ - sdhci@78000200 { + mmc@78000200 { status = "okay"; bus-width = <4>; cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index adba554381c7..a7bfe26f038d 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -933,7 +933,7 @@ i2s@70080500 { }; /* eMMC */ - sdhci@78000600 { + mmc@78000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 23fedb76e5ae..536cc5629440 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -851,7 +851,7 @@ tegra_i2s4: i2s@70080700 { }; }; - sdhci@78000000 { + mmc@78000000 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000000 0x200>; interrupts = ; @@ -861,7 +861,7 @@ sdhci@78000000 { status = "disabled"; }; - sdhci@78000200 { + mmc@78000200 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000200 0x200>; interrupts = ; @@ -871,7 +871,7 @@ sdhci@78000200 { status = "disabled"; }; - sdhci@78000400 { + mmc@78000400 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000400 0x200>; interrupts = ; @@ -881,7 +881,7 @@ sdhci@78000400 { status = "disabled"; }; - sdhci@78000600 { + mmc@78000600 { compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; reg = <0x78000600 0x200>; interrupts = ; From patchwork Tue Jun 16 13:51:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310361 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; 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Tue, 16 Jun 2020 06:53:18 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id w17sm30538823wra.71.2020.06.16.06.53.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:53:17 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 14/73] ARM: tegra: Tegra114 SDHCI is not backwards-compatible Date: Tue, 16 Jun 2020 15:51:39 +0200 Message-Id: <20200616135238.3001888-15-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The SDHCI controller instantiated on Tegra114 is not backwards- compatible with the version on Tegra30, so remove the corresponding compatible string. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 69e0e3eeffb4..88632d8d0bde 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -645,7 +645,7 @@ mipi: mipi@700e3000 { }; mmc@78000000 { - compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; + compatible = "nvidia,tegra114-sdhci"; reg = <0x78000000 0x200>; interrupts = ; clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; @@ -656,7 +656,7 @@ mmc@78000000 { }; mmc@78000200 { - compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; + compatible = "nvidia,tegra114-sdhci"; reg = <0x78000200 0x200>; interrupts = ; clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; @@ -667,7 +667,7 @@ mmc@78000200 { }; mmc@78000400 { - compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; + compatible = "nvidia,tegra114-sdhci"; reg = <0x78000400 0x200>; interrupts = ; clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; @@ -678,7 +678,7 @@ mmc@78000400 { }; mmc@78000600 { - compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; + compatible = "nvidia,tegra114-sdhci"; reg = <0x78000600 0x200>; interrupts = ; clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; From patchwork Tue Jun 16 13:51:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310362 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=IQm8uHie; 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Tue, 16 Jun 2020 06:53:20 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id d5sm31603455wrb.14.2020.06.16.06.53.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:53:19 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 15/73] ARM: tegra: Add missing #phy-cells property to USB PHYs Date: Tue, 16 Jun 2020 15:51:40 +0200 Message-Id: <20200616135238.3001888-16-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding USB PHYs must have a #phy-cells property, so add one to the Tegra USB PHYs which don't have one. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 2 ++ arch/arm/boot/dts/tegra124.dtsi | 3 +++ arch/arm/boot/dts/tegra20.dtsi | 3 +++ arch/arm/boot/dts/tegra30.dtsi | 3 +++ 4 files changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 88632d8d0bde..d28d35dc3f5c 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -710,6 +710,7 @@ phy1: usb-phy@7d000000 { clock-names = "reg", "pll_u", "utmi-pads"; resets = <&tegra_car 22>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <0>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; @@ -746,6 +747,7 @@ phy3: usb-phy@7d008000 { clock-names = "reg", "pll_u", "utmi-pads"; resets = <&tegra_car 59>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <0>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 76c1ef923213..f00e962c8f55 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -1056,6 +1056,7 @@ phy1: usb-phy@7d000000 { clock-names = "reg", "pll_u", "utmi-pads"; resets = <&tegra_car 22>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <0>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; @@ -1093,6 +1094,7 @@ phy2: usb-phy@7d004000 { clock-names = "reg", "pll_u", "utmi-pads"; resets = <&tegra_car 58>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <0>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; @@ -1129,6 +1131,7 @@ phy3: usb-phy@7d008000 { clock-names = "reg", "pll_u", "utmi-pads"; resets = <&tegra_car 59>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <0>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 9e71ed84bf28..77f6b3ee8418 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -735,6 +735,7 @@ phy1: usb-phy@c5000000 { clock-names = "reg", "pll_u", "timer", "utmi-pads"; resets = <&tegra_car 22>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,has-legacy-mode; nvidia,hssync-start-delay = <9>; nvidia,idle-wait-delay = <17>; @@ -769,6 +770,7 @@ phy2: usb-phy@c5004000 { clock-names = "reg", "pll_u", "ulpi-link"; resets = <&tegra_car 58>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; status = "disabled"; }; @@ -795,6 +797,7 @@ phy3: usb-phy@c5008000 { clock-names = "reg", "pll_u", "timer", "utmi-pads"; resets = <&tegra_car 59>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <9>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 536cc5629440..3d0515f6db51 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -914,6 +914,7 @@ phy1: usb-phy@7d000000 { clock-names = "reg", "pll_u", "utmi-pads"; resets = <&tegra_car 22>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <9>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; @@ -951,6 +952,7 @@ phy2: usb-phy@7d004000 { clock-names = "reg", "pll_u", "utmi-pads"; resets = <&tegra_car 58>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <9>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; @@ -987,6 +989,7 @@ phy3: usb-phy@7d008000 { clock-names = "reg", "pll_u", "utmi-pads"; resets = <&tegra_car 59>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <0>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; From patchwork Tue Jun 16 13:51:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310363 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Tue, 16 Jun 2020 06:53:23 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id d5sm31603598wrb.14.2020.06.16.06.53.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:53:22 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcel Ziswiler , Philippe Schenker Subject: [PATCH 16/73] ARM: tegra: Add missing #sound-dai-cells property to codecs Date: Tue, 16 Jun 2020 15:51:41 +0200 Message-Id: <20200616135238.3001888-17-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Audio codecs need a #sound-dai-cells property, so add one to the audio codecs on various Tegra-based boards that don't have one. Cc: Marcel Ziswiler Cc: Philippe Schenker Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 1 + arch/arm/boot/dts/tegra124-apalis.dtsi | 1 + arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | 1 + arch/arm/boot/dts/tegra30-apalis.dtsi | 1 + arch/arm/boot/dts/tegra30-colibri.dtsi | 1 + 5 files changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 3fdc6ff32b0c..0d6890af457e 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -1559,6 +1559,7 @@ i2c@7000d000 { sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; VDDA-supply = <®_module_3v3_audio>; VDDD-supply = <®_1v8_vddio>; VDDIO-supply = <®_1v8_vddio>; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 29ceeba1e7b1..8857a11332c2 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -1552,6 +1552,7 @@ i2c@7000d000 { sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; VDDA-supply = <®_module_3v3_audio>; VDDD-supply = <®_1v8_vddio>; VDDIO-supply = <®_1v8_vddio>; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi index 9421063cd86c..fdd3e4e3522b 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi @@ -855,6 +855,7 @@ i2c@7000d000 { sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; VDDA-supply = <®_module_3v3_audio>; VDDD-supply = <®_1v8_vio>; VDDIO-supply = <®_module_3v3>; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index d13f6b0c7c0c..90694d1a3b0c 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -846,6 +846,7 @@ i2c@7000d000 { sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; VDDA-supply = <®_module_3v3_audio>; VDDD-supply = <®_1v8_vio>; VDDIO-supply = <®_module_3v3>; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index a7bfe26f038d..933087ee45a8 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -723,6 +723,7 @@ i2c@7000d000 { sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; VDDA-supply = <®_module_3v3_audio>; VDDD-supply = <®_1v8_vio>; VDDIO-supply = <®_module_3v3>; From patchwork Tue Jun 16 13:51:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310364 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; 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Tue, 16 Jun 2020 06:53:25 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id l2sm28735784wru.58.2020.06.16.06.53.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:53:24 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcel Ziswiler , Philippe Schenker Subject: [PATCH 17/73] ARM: tegra: Name GPIO hog nodes consistently Date: Tue, 16 Jun 2020 15:51:42 +0200 Message-Id: <20200616135238.3001888-18-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Use the common gpios- prefix for GPIO hog node names to make it clear that they are all hogs. This helps with json-schema based validation. Cc: Marcel Ziswiler Cc: Philippe Schenker Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-eval.dts | 2 +- arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts | 2 +- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 4 ++-- arch/arm/boot/dts/tegra124-apalis.dtsi | 4 ++-- arch/arm/boot/dts/tegra20-colibri.dtsi | 6 +++--- arch/arm/boot/dts/tegra30-apalis-eval.dts | 2 +- arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts | 2 +- arch/arm/boot/dts/tegra30-colibri.dtsi | 2 +- 8 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts index 28c29b6813a7..89fafa39aa2a 100644 --- a/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts @@ -246,7 +246,7 @@ reg_usbh_vbus: regulator-usbh-vbus { &gpio { /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n { + gpios-pex-perst-n { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts index f3afde410615..441a244ef6c1 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts @@ -248,7 +248,7 @@ reg_usbh_vbus: regulator-usbh-vbus { &gpio { /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n { + gpios-pex-perst-n { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 0d6890af457e..eb5f4ad0fe71 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -2048,7 +2048,7 @@ gpu-shutdown-trip { &gpio { /* I210 Gigabit Ethernet Controller Reset */ - lan-reset-n { + gpios-lan-reset-n { gpio-hog; gpios = ; output-high; @@ -2056,7 +2056,7 @@ lan-reset-n { }; /* Control MXM3 pin 26 Reset Module Output Carrier Input */ - reset-moci-ctrl { + gpios-reset-moci-ctrl { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 8857a11332c2..64a18b525378 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -2040,7 +2040,7 @@ gpu-shutdown-trip { &gpio { /* I210 Gigabit Ethernet Controller Reset */ - lan-reset-n { + gpios-lan-reset-n { gpio-hog; gpios = ; output-high; @@ -2048,7 +2048,7 @@ lan-reset-n { }; /* Control MXM3 pin 26 Reset Module Output Carrier Input */ - reset-moci-ctrl { + gpios-reset-moci-ctrl { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 6162d193e12c..90f317117298 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -743,7 +743,7 @@ sound { }; &gpio { - lan-reset-n { + gpios-lan-reset-n { gpio-hog; gpios = ; output-high; @@ -751,7 +751,7 @@ lan-reset-n { }; /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */ - npwe { + gpios-npwe { gpio-hog; gpios = ; output-high; @@ -759,7 +759,7 @@ npwe { }; /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */ - rdnwr { + gpios-rdnwr { gpio-hog; gpios = ; output-low; diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 9f653ef41da4..01b2a9db77c8 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -239,7 +239,7 @@ reg_usbh_vbus: regulator-usbh-vbus { &gpio { /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n { + gpios-pex-perst-n { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts index dc633e529822..d5a244351137 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts @@ -257,7 +257,7 @@ reg_vddio_sdmmc3: regulator-vddio-sdmmc3 { &gpio { /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n { + gpios-pex-perst-n { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 933087ee45a8..c209020e13fd 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -1043,7 +1043,7 @@ sound { }; &gpio { - lan-reset-n { + gpios-lan-reset-n { gpio-hog; gpios = ; output-high; From patchwork Tue Jun 16 13:51:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310365 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Tue, 16 Jun 2020 06:53:27 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id 89sm2412029wrg.56.2020.06.16.06.53.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:53:26 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcel Ziswiler , Philippe Schenker Subject: [PATCH 18/73] ARM: tegra: Use standard name for Ethernet devices Date: Tue, 16 Jun 2020 15:51:43 +0200 Message-Id: <20200616135238.3001888-19-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Ethernet device should be named "ethernet@". Cc: Marcel Ziswiler Cc: Philippe Schenker Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 2 +- arch/arm/boot/dts/tegra124-apalis.dtsi | 2 +- arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | 2 +- arch/arm/boot/dts/tegra30-apalis.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index eb5f4ad0fe71..8f4c11f918b4 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -37,7 +37,7 @@ pci@2,0 { phy-names = "pcie-0"; status = "okay"; - pcie@0 { + ethernet@0,0 { reg = <0 0 0 0 0>; local-mac-address = [00 00 00 00 00 00]; }; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 64a18b525378..39a5744dbcb4 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -36,7 +36,7 @@ pci@2,0 { phy-names = "pcie-0"; status = "okay"; - pcie@0 { + ethernet@0,0 { reg = <0 0 0 0 0>; local-mac-address = [00 00 00 00 00 00]; }; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi index fdd3e4e3522b..6a3a72f81c44 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi @@ -37,7 +37,7 @@ pci@3,0 { status = "okay"; nvidia,num-lanes = <1>; - pcie@0 { + ethernet@0,0 { reg = <0 0 0 0 0>; local-mac-address = [00 00 00 00 00 00]; }; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 90694d1a3b0c..6544ce70b46f 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -36,7 +36,7 @@ pci@3,0 { status = "okay"; nvidia,num-lanes = <1>; - pcie@0 { + ethernet@0,0 { reg = <0 0 0 0 0>; local-mac-address = [00 00 00 00 00 00]; }; From patchwork Tue Jun 16 13:51:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310366 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Tue, 16 Jun 2020 06:53:29 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id g187sm4442985wma.17.2020.06.16.06.53.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:53:28 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcel Ziswiler , Philippe Schenker Subject: [PATCH 19/73] ARM: tegra: Use proper tuple notation Date: Tue, 16 Jun 2020 15:51:44 +0200 Message-Id: <20200616135238.3001888-20-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Tuple boundaries should be marked by < and > to make it clear which cells are part of the same tuple. This also helps the json-schema based validation tooling to properly parse this data. While at it, also remove the "immovable" bit from PCI addresses. All of these addresses are in fact "movable". Cc: Marcel Ziswiler Cc: Philippe Schenker Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 16 +++++----- arch/arm/boot/dts/tegra20.dtsi | 24 +++++++-------- .../arm/boot/dts/tegra30-apalis-v1.1-eval.dts | 4 +-- arch/arm/boot/dts/tegra30.dtsi | 30 +++++++++---------- 4 files changed, 37 insertions(+), 37 deletions(-) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index f00e962c8f55..6d34742b56b9 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -22,9 +22,9 @@ memory@80000000 { pcie@1003000 { compatible = "nvidia,tegra124-pcie"; device_type = "pci"; - reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ - 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ - 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ + reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ + <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ + <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ reg-names = "pads", "afi", "cs"; interrupts = , /* controller interrupt */ ; /* MSI interrupt */ @@ -38,11 +38,11 @@ pcie@1003000 { #address-cells = <3>; #size-cells = <2>; - ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ - 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ - 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ - 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ - 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ + ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ + <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ + <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ + <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ + <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ clocks = <&tegra_car TEGRA124_CLK_PCIE>, <&tegra_car TEGRA124_CLK_AFI>, diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 77f6b3ee8418..90393d8f5ebc 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -172,8 +172,8 @@ timer@50040600 { intc: interrupt-controller@50041000 { compatible = "arm,cortex-a9-gic"; - reg = <0x50041000 0x1000 - 0x50040100 0x0100>; + reg = <0x50041000 0x1000>, + <0x50040100 0x0100>; interrupt-controller; #interrupt-cells = <3>; interrupt-parent = <&intc>; @@ -649,12 +649,12 @@ fuse@7000f800 { pcie@80003000 { compatible = "nvidia,tegra20-pcie"; device_type = "pci"; - reg = <0x80003000 0x00000800 /* PADS registers */ - 0x80003800 0x00000200 /* AFI registers */ - 0x90000000 0x10000000>; /* configuration space */ + reg = <0x80003000 0x00000800>, /* PADS registers */ + <0x80003800 0x00000200>, /* AFI registers */ + <0x90000000 0x10000000>; /* configuration space */ reg-names = "pads", "afi", "cs"; - interrupts = ; /* MSI interrupt */ + interrupts = , /* controller interrupt */ + ; /* MSI interrupt */ interrupt-names = "intr", "msi"; #interrupt-cells = <1>; @@ -665,11 +665,11 @@ pcie@80003000 { #address-cells = <3>; #size-cells = <2>; - ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ - 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ - 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */ - 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ + ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */ + <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */ + <0x01000000 0 0 0x82000000 0 0x00010000>, /* downstream I/O */ + <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */ + <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ clocks = <&tegra_car TEGRA20_CLK_PEX>, <&tegra_car TEGRA20_CLK_AFI>, diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts index d5a244351137..1fa440d02e83 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts @@ -248,8 +248,8 @@ reg_vddio_sdmmc3: regulator-vddio-sdmmc3 { regulator-max-microvolt = <3300000>; regulator-type = "voltage"; gpios = <&gpio TEGRA_GPIO(J, 5) GPIO_ACTIVE_HIGH>; - states = <1800000 0x0 - 3300000 0x1>; + states = <1800000 0x0>, + <3300000 0x1>; startup-delay-us = <100000>; vin-supply = <&vddio_sdmmc_1v8_reg>; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 3d0515f6db51..9a8c07ccbb30 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -20,12 +20,12 @@ memory@80000000 { pcie@3000 { compatible = "nvidia,tegra30-pcie"; device_type = "pci"; - reg = <0x00003000 0x00000800 /* PADS registers */ - 0x00003800 0x00000200 /* AFI registers */ - 0x10000000 0x10000000>; /* configuration space */ + reg = <0x00003000 0x00000800>, /* PADS registers */ + <0x00003800 0x00000200>, /* AFI registers */ + <0x10000000 0x10000000>; /* configuration space */ reg-names = "pads", "afi", "cs"; - interrupts = ; /* MSI interrupt */ + interrupts = , /* controller interrupt */ + ; /* MSI interrupt */ interrupt-names = "intr", "msi"; #interrupt-cells = <1>; @@ -36,12 +36,12 @@ pcie@3000 { #address-cells = <3>; #size-cells = <2>; - ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ - 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ - 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ - 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */ - 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ + ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */ + <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */ + <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */ + <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */ + <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */ + <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ clocks = <&tegra_car TEGRA30_CLK_PCIE>, <&tegra_car TEGRA30_CLK_AFI>, @@ -185,8 +185,8 @@ gr2d@54140000 { gr3d@54180000 { compatible = "nvidia,tegra30-gr3d"; reg = <0x54180000 0x00040000>; - clocks = <&tegra_car TEGRA30_CLK_GR3D - &tegra_car TEGRA30_CLK_GR3D2>; + clocks = <&tegra_car TEGRA30_CLK_GR3D>, + <&tegra_car TEGRA30_CLK_GR3D2>; clock-names = "3d", "3d2"; resets = <&tegra_car 24>, <&tegra_car 98>; @@ -273,8 +273,8 @@ timer@50040600 { intc: interrupt-controller@50041000 { compatible = "arm,cortex-a9-gic"; - reg = <0x50041000 0x1000 - 0x50040100 0x0100>; + reg = <0x50041000 0x1000>, + <0x50040100 0x0100>; interrupt-controller; #interrupt-cells = <3>; interrupt-parent = <&intc>; From patchwork Tue Jun 16 13:51:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310367 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Tue, 16 Jun 2020 06:53:32 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id a7sm4344861wmh.14.2020.06.16.06.53.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:53:31 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 20/73] ARM: tegra: Add micro-USB A/B port on Jetson TK1 Date: Tue, 16 Jun 2020 15:51:45 +0200 Message-Id: <20200616135238.3001888-21-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Run the micro-USB A/B port on Jetson TK1 in host mode by default. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 289bf6e99041..6eaa39646221 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1775,6 +1775,12 @@ sata-0 { }; ports { + /* Micro A/B */ + usb2-0 { + status = "okay"; + mode = "host"; + }; + /* Mini PCIe */ usb2-1 { status = "okay"; From patchwork Tue Jun 16 13:51:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310368 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=Gzss4fSM; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV6900MZz9sRK for ; Tue, 16 Jun 2020 23:53:36 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728917AbgFPNxg (ORCPT ); Tue, 16 Jun 2020 09:53:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57008 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726306AbgFPNxf (ORCPT ); Tue, 16 Jun 2020 09:53:35 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 673DFC061573 for ; Tue, 16 Jun 2020 06:53:35 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id x13so20855838wrv.4 for ; Tue, 16 Jun 2020 06:53:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iXboMnPmHQIHtE6HM9vw2yFF9ZSbpIwzP+DcxPet0tM=; b=Gzss4fSM87UaJzKPYU1n97qDJ/Lt4naG7zj/ylaKOxQcfvgQwlOVEPEJVfJK5HwM1g cjls36HJTPepPLCgXPKKpyp2TQgU+EwueaQMze1ymSMXJSK1shpEAZXlG8rzy++Sn2Mq mh90+tN3dXKLYTR8DpTZhG4xLQtsdLcUojWAR6e61jOqSt+yLqn7V7tNftayIolSudFG PdnRju7Yx0u8evzXHo61udcbBSjq2Ct/AXv2s2ze/HB33F64IwJVB5nQN2of81qtphjJ xs1qfXCbvqOrkdjT/XoB1c+BgqiWpOgDQ8QFX/Rs+CMtLo59O7+77vSABlNIri8MMjUT 9Alw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iXboMnPmHQIHtE6HM9vw2yFF9ZSbpIwzP+DcxPet0tM=; b=HpatDkY9oiESTC1+FPns2v2NFj3HbP/yMw90NJ11IVPzrSpvk7tKIq4b3cBCZ/cUug VXRueaUR8RBAhlJJDOTPppsPPrNBUt7oir8nHc9E+SkKVskhwy9bKce6ihyY4l3NP/bs SuNFEtcDmkX/buOPHVSd4mWNTqSkoXimqOGANo9q31raF+GPvJ8Sx77dTGB5Br7cYimD Ihlm7vKThnf0x61w6BqE7IGVxNnW/FU8MicIYsilgMZKevC2ntke+nSX4BMqoCpl/iIK TdgzzSqgXvDGqGdCVsUxYT09q6IML4Wslumjkylu9NyyS/f130BK0+LgJGtdama4UTHE G1DQ== X-Gm-Message-State: AOAM532I+MIOwNIf2wsuieltPouoU5ehYv+ak27kpGNrqN8SRaBVVGYP zpi+4hjNl3/zSIyrDcBWGFs= X-Google-Smtp-Source: ABdhPJwAabq2qictYV0u1lT6v7v69dvOMKqGISfWlUh+49ofOGrc8/Ekt+ENvEQoYlPLglQJr4Dw1w== X-Received: by 2002:adf:f003:: with SMTP id j3mr3224077wro.228.1592315614149; Tue, 16 Jun 2020 06:53:34 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id n204sm4389946wma.5.2020.06.16.06.53.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:53:33 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 21/73] ARM: tegra: Add missing panel power supplies on Nyan Date: Tue, 16 Jun 2020 15:51:46 +0200 Message-Id: <20200616135238.3001888-22-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Both Nyan boards are missing panel power supplies. Add them. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-nyan-big.dts | 1 + arch/arm/boot/dts/tegra124-nyan-blaze.dts | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts index 4d14dec21af6..1d2aac2cb6d0 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big.dts +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts @@ -16,6 +16,7 @@ / { panel: panel { compatible = "auo,b133xtn01"; + power-supply = <&vdd_3v3_panel>; backlight = <&backlight>; ddc-i2c-bus = <&dpaux>; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/tegra124-nyan-blaze.dts index 2a029ee86dd7..677babde6460 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze.dts +++ b/arch/arm/boot/dts/tegra124-nyan-blaze.dts @@ -18,6 +18,7 @@ / { panel: panel { compatible = "samsung,ltn140at29-301"; + power-supply = <&vdd_3v3_panel>; backlight = <&backlight>; ddc-i2c-bus = <&dpaux>; }; From patchwork Tue Jun 16 13:51:47 2020 Content-Type: text/plain; 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Tue, 16 Jun 2020 06:53:35 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 22/73] ARM: tegra: Add #reset-cells to Tegra124 memory controller Date: Tue, 16 Jun 2020 15:51:47 +0200 Message-Id: <20200616135238.3001888-23-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The memory controller exposes a set of memory client resets and needs to specify the #reset-cells property in order to advertise the number of cells needed to describe each of the resets. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 6d34742b56b9..98cd7962a559 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -622,6 +622,7 @@ mc: memory-controller@70019000 { interrupts = ; #iommu-cells = <1>; + #reset-cells = <1>; }; emc: external-memory-controller@7001b000 { From patchwork Tue Jun 16 13:51:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310370 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=BBE6diyY; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV6Q4kYHz9sRN for ; Tue, 16 Jun 2020 23:53:50 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729003AbgFPNxp (ORCPT ); Tue, 16 Jun 2020 09:53:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726306AbgFPNxp (ORCPT ); Tue, 16 Jun 2020 09:53:45 -0400 Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5EF12C061573 for ; Tue, 16 Jun 2020 06:53:43 -0700 (PDT) Received: by mail-wr1-x444.google.com with SMTP id x14so20879958wrp.2 for ; Tue, 16 Jun 2020 06:53:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1hzh7RbaArgZesWRTqDN/FeTVQzKBLSZlz7exAjOze0=; b=BBE6diyY98Clf7rBWb0sGxUZG+94G+k5yBejFWt18I8AqePPpW3KvTCx90cGKglNJU fic1UEDuhg75rs1f5P96aRW1OS12e2O73f/A3LogF3Fgcvb605UpmVK29YRQHWjZqZkA Yc7yJP3TBAvq9UfZ/HgOB/ganbZAyo7zWC8zGPuO18Ailw/0zjG7YSn9jNl+ozBH1DNy dl+IzfpoKGhL0SpyqVBLplZkDQfNDtKJM5YJATb9cOo4o5gm7Brq/lRvXiubVQH6px+U 1cHH2SWgCpsGPb3KFzmAeycOUiaYkciFKMuKgCG8V2hqYS3F92imlwGRTJMIbqR8R9ej uMoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1hzh7RbaArgZesWRTqDN/FeTVQzKBLSZlz7exAjOze0=; b=QmP4m6sfsTiIzF8bm2kAodNGnajNYR/qRf/qXWaVdda+QYpb9xxXkGge07GSvaq171 I2+YgVA0i6izbjvkUQ3KlBsmUgpi25iunGi6OE7d9t2U67agIfqLOd5sDHJdt1fC5yIF zjv1B57Ao0/pq4fvU+5A9jvQg4oZqWlSYE77U98P2RMGKpLPHejrCEe7SRi4NxpZEJT9 yYYzPI+XEv7mdwoZev/h3QfXgm9Ll0U2g4rTzZO89RnN57/QAq1uXGgZ8wjtP/cX/l8o jfRwNWnxG+PbD1neiv/Ki8drHmriH/zoSWwcqDHgD3IzcZ5g/0WHmClHFChyZWNNGdhS Q2cg== X-Gm-Message-State: AOAM530/OI4YQlPNAGA9CjbWXjPJAbDIEh7fdx9fUHJS53xhoUDgC2Kz MuJEXh+Zzx/BbfP3H8dtd3Q= X-Google-Smtp-Source: ABdhPJzMz/BaDg4ZelBnXNDvNp1+Uhdm3/Sxq/uv/BGMXs2RJkskuDLu1IVdwz34s+jI8dVzp+W8+Q== X-Received: by 2002:adf:ff8a:: with SMTP id j10mr3131917wrr.405.1592315622168; Tue, 16 Jun 2020 06:53:42 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id a3sm4064332wmb.7.2020.06.16.06.53.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:53:37 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 23/73] ARM: tegra: Fix order of XUSB controller clocks Date: Tue, 16 Jun 2020 15:51:48 +0200 Message-Id: <20200616135238.3001888-24-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding This is purely to make the json-schema validation tools happy because they cannot deal with string arrays that may be in arbitrary order. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 98cd7962a559..3840019ed5c6 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -680,8 +680,8 @@ usb@70090000 { <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, <&tegra_car TEGRA124_CLK_XUSB_SS>, - <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, <&tegra_car TEGRA124_CLK_PLL_U_480M>, @@ -689,7 +689,7 @@ usb@70090000 { <&tegra_car TEGRA124_CLK_PLL_E>; clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src", "xusb_ss", - "xusb_ss_div2", "xusb_ss_src", + "xusb_ss_src", "xusb_ss_div2", "xusb_hs_src", "xusb_fs_src", "pll_u_480m", "clk_m", "pll_e"; resets = <&tegra_car 89>, <&tegra_car 156>, From patchwork Tue Jun 16 13:51:49 2020 Content-Type: text/plain; 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Tue, 16 Jun 2020 06:53:43 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 24/73] ARM: tegra: Add missing clock-names for SDHCI controllers Date: Tue, 16 Jun 2020 15:51:49 +0200 Message-Id: <20200616135238.3001888-25-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The Tegra SDHCI controllers need to have a clock-names property according to the bindings. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 4 ++++ arch/arm/boot/dts/tegra20.dtsi | 4 ++++ arch/arm/boot/dts/tegra30.dtsi | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 3840019ed5c6..175d0bcd7a2b 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -839,6 +839,7 @@ mmc@700b0000 { reg = <0x0 0x700b0000 0x0 0x200>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; + clock-names = "sdhci"; resets = <&tegra_car 14>; reset-names = "sdhci"; status = "disabled"; @@ -849,6 +850,7 @@ mmc@700b0200 { reg = <0x0 0x700b0200 0x0 0x200>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; + clock-names = "sdhci"; resets = <&tegra_car 9>; reset-names = "sdhci"; status = "disabled"; @@ -859,6 +861,7 @@ mmc@700b0400 { reg = <0x0 0x700b0400 0x0 0x200>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; + clock-names = "sdhci"; resets = <&tegra_car 69>; reset-names = "sdhci"; status = "disabled"; @@ -869,6 +872,7 @@ mmc@700b0600 { reg = <0x0 0x700b0600 0x0 0x200>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; + clock-names = "sdhci"; resets = <&tegra_car 15>; reset-names = "sdhci"; status = "disabled"; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 90393d8f5ebc..ccd2995aef83 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -813,6 +813,7 @@ mmc@c8000000 { reg = <0xc8000000 0x200>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; + clock-names = "sdhci"; resets = <&tegra_car 14>; reset-names = "sdhci"; status = "disabled"; @@ -823,6 +824,7 @@ mmc@c8000200 { reg = <0xc8000200 0x200>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; + clock-names = "sdhci"; resets = <&tegra_car 9>; reset-names = "sdhci"; status = "disabled"; @@ -833,6 +835,7 @@ mmc@c8000400 { reg = <0xc8000400 0x200>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; + clock-names = "sdhci"; resets = <&tegra_car 69>; reset-names = "sdhci"; status = "disabled"; @@ -843,6 +846,7 @@ mmc@c8000600 { reg = <0xc8000600 0x200>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; + clock-names = "sdhci"; resets = <&tegra_car 15>; reset-names = "sdhci"; status = "disabled"; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 9a8c07ccbb30..f838e4775cf6 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -856,6 +856,7 @@ mmc@78000000 { reg = <0x78000000 0x200>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; + clock-names = "sdhci"; resets = <&tegra_car 14>; reset-names = "sdhci"; status = "disabled"; @@ -866,6 +867,7 @@ mmc@78000200 { reg = <0x78000200 0x200>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; + clock-names = "sdhci"; resets = <&tegra_car 9>; reset-names = "sdhci"; status = "disabled"; @@ -876,6 +878,7 @@ mmc@78000400 { reg = <0x78000400 0x200>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + clock-names = "sdhci"; resets = <&tegra_car 69>; reset-names = "sdhci"; status = "disabled"; @@ -886,6 +889,7 @@ mmc@78000600 { reg = <0x78000600 0x200>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; + clock-names = "sdhci"; resets = <&tegra_car 15>; reset-names = "sdhci"; status = "disabled"; From patchwork Tue Jun 16 13:51:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310371 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; 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Tue, 16 Jun 2020 06:53:46 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id n23sm4012124wmc.0.2020.06.16.06.53.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:53:45 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 25/73] ARM: tegra: Use proper unit-addresses for OPPs Date: Tue, 16 Jun 2020 15:51:50 +0200 Message-Id: <20200616135238.3001888-26-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Use commas rather than underscores to separate the various parts of the unit-address in CPU OPPs to make them properly validate under the json- schema bindings. Signed-off-by: Thierry Reding --- .../boot/dts/tegra20-cpu-opp-microvolt.dtsi | 98 ++--- arch/arm/boot/dts/tegra20-cpu-opp.dtsi | 98 ++--- .../boot/dts/tegra30-cpu-opp-microvolt.dtsi | 398 +++++++++--------- arch/arm/boot/dts/tegra30-cpu-opp.dtsi | 398 +++++++++--------- 4 files changed, 496 insertions(+), 496 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi b/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi index e85ffdbef876..dce85d39480d 100644 --- a/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi +++ b/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi @@ -2,199 +2,199 @@ / { cpu0_opp_table: cpu_opp_table0 { - opp@216000000_750 { + opp@216000000,750 { opp-microvolt = <750000 750000 1125000>; }; - opp@216000000_800 { + opp@216000000,800 { opp-microvolt = <800000 800000 1125000>; }; - opp@312000000_750 { + opp@312000000,750 { opp-microvolt = <750000 750000 1125000>; }; - opp@312000000_800 { + opp@312000000,800 { opp-microvolt = <800000 800000 1125000>; }; - opp@456000000_750 { + opp@456000000,750 { opp-microvolt = <750000 750000 1125000>; }; - opp@456000000_800 { + opp@456000000,800 { opp-microvolt = <800000 800000 1125000>; }; - opp@456000000_800_2_2 { + opp@456000000,800,2,2 { opp-microvolt = <800000 800000 1125000>; }; - opp@456000000_800_3_2 { + opp@456000000,800,3,2 { opp-microvolt = <800000 800000 1125000>; }; - opp@456000000_825 { + opp@456000000,825 { opp-microvolt = <825000 825000 1125000>; }; - opp@608000000_750 { + opp@608000000,750 { opp-microvolt = <750000 750000 1125000>; }; - opp@608000000_800 { + opp@608000000,800 { opp-microvolt = <800000 800000 1125000>; }; - opp@608000000_800_3_2 { + opp@608000000,800,3,2 { opp-microvolt = <800000 800000 1125000>; }; - opp@608000000_825 { + opp@608000000,825 { opp-microvolt = <825000 825000 1125000>; }; - opp@608000000_850 { + opp@608000000,850 { opp-microvolt = <850000 850000 1125000>; }; - opp@608000000_900 { + opp@608000000,900 { opp-microvolt = <900000 900000 1125000>; }; - opp@760000000_775 { + opp@760000000,775 { opp-microvolt = <775000 775000 1125000>; }; - opp@760000000_800 { + opp@760000000,800 { opp-microvolt = <800000 800000 1125000>; }; - opp@760000000_850 { + opp@760000000,850 { opp-microvolt = <850000 850000 1125000>; }; - opp@760000000_875 { + opp@760000000,875 { opp-microvolt = <875000 875000 1125000>; }; - opp@760000000_875_1_1 { + opp@760000000,875,1,1 { opp-microvolt = <875000 875000 1125000>; }; - opp@760000000_875_0_2 { + opp@760000000,875,0,2 { opp-microvolt = <875000 875000 1125000>; }; - opp@760000000_875_1_2 { + opp@760000000,875,1,2 { opp-microvolt = <875000 875000 1125000>; }; - opp@760000000_900 { + opp@760000000,900 { opp-microvolt = <900000 900000 1125000>; }; - opp@760000000_975 { + opp@760000000,975 { opp-microvolt = <975000 975000 1125000>; }; - opp@816000000_800 { + opp@816000000,800 { opp-microvolt = <800000 800000 1125000>; }; - opp@816000000_850 { + opp@816000000,850 { opp-microvolt = <850000 850000 1125000>; }; - opp@816000000_875 { + opp@816000000,875 { opp-microvolt = <875000 875000 1125000>; }; - opp@816000000_950 { + opp@816000000,950 { opp-microvolt = <950000 950000 1125000>; }; - opp@816000000_1000 { + opp@816000000,1000 { opp-microvolt = <1000000 1000000 1125000>; }; - opp@912000000_850 { + opp@912000000,850 { opp-microvolt = <850000 850000 1125000>; }; - opp@912000000_900 { + opp@912000000,900 { opp-microvolt = <900000 900000 1125000>; }; - opp@912000000_925 { + opp@912000000,925 { opp-microvolt = <925000 925000 1125000>; }; - opp@912000000_950 { + opp@912000000,950 { opp-microvolt = <950000 950000 1125000>; }; - opp@912000000_950_0_2 { + opp@912000000,950,0,2 { opp-microvolt = <950000 950000 1125000>; }; - opp@912000000_950_2_2 { + opp@912000000,950,2,2 { opp-microvolt = <950000 950000 1125000>; }; - opp@912000000_1000 { + opp@912000000,1000 { opp-microvolt = <1000000 1000000 1125000>; }; - opp@912000000_1050 { + opp@912000000,1050 { opp-microvolt = <1050000 1050000 1125000>; }; - opp@1000000000_875 { + opp@1000000000,875 { opp-microvolt = <875000 875000 1125000>; }; - opp@1000000000_900 { + opp@1000000000,900 { opp-microvolt = <900000 900000 1125000>; }; - opp@1000000000_950 { + opp@1000000000,950 { opp-microvolt = <950000 950000 1125000>; }; - opp@1000000000_975 { + opp@1000000000,975 { opp-microvolt = <975000 975000 1125000>; }; - opp@1000000000_1000 { + opp@1000000000,1000 { opp-microvolt = <1000000 1000000 1125000>; }; - opp@1000000000_1000_0_2 { + opp@1000000000,1000,0,2 { opp-microvolt = <1000000 1000000 1125000>; }; - opp@1000000000_1025 { + opp@1000000000,1025 { opp-microvolt = <1025000 1025000 1125000>; }; - opp@1000000000_1100 { + opp@1000000000,1100 { opp-microvolt = <1100000 1100000 1125000>; }; - opp@1200000000_1000 { + opp@1200000000,1000 { opp-microvolt = <1000000 1000000 1125000>; }; - opp@1200000000_1050 { + opp@1200000000,1050 { opp-microvolt = <1050000 1050000 1125000>; }; - opp@1200000000_1100 { + opp@1200000000,1100 { opp-microvolt = <1100000 1100000 1125000>; }; - opp@1200000000_1125 { + opp@1200000000,1125 { opp-microvolt = <1125000 1125000 1125000>; }; }; diff --git a/arch/arm/boot/dts/tegra20-cpu-opp.dtsi b/arch/arm/boot/dts/tegra20-cpu-opp.dtsi index c878f4231791..9b8fedb57a1b 100644 --- a/arch/arm/boot/dts/tegra20-cpu-opp.dtsi +++ b/arch/arm/boot/dts/tegra20-cpu-opp.dtsi @@ -5,295 +5,295 @@ cpu0_opp_table: cpu_opp_table0 { compatible = "operating-points-v2"; opp-shared; - opp@216000000_750 { + opp@216000000,750 { clock-latency-ns = <400000>; opp-supported-hw = <0x0F 0x0003>; opp-hz = /bits/ 64 <216000000>; }; - opp@216000000_800 { + opp@216000000,800 { clock-latency-ns = <400000>; opp-supported-hw = <0x0F 0x0004>; opp-hz = /bits/ 64 <216000000>; }; - opp@312000000_750 { + opp@312000000,750 { clock-latency-ns = <400000>; opp-supported-hw = <0x0F 0x0003>; opp-hz = /bits/ 64 <312000000>; }; - opp@312000000_800 { + opp@312000000,800 { clock-latency-ns = <400000>; opp-supported-hw = <0x0F 0x0004>; opp-hz = /bits/ 64 <312000000>; }; - opp@456000000_750 { + opp@456000000,750 { clock-latency-ns = <400000>; opp-supported-hw = <0x0C 0x0003>; opp-hz = /bits/ 64 <456000000>; }; - opp@456000000_800 { + opp@456000000,800 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0006>; opp-hz = /bits/ 64 <456000000>; }; - opp@456000000_800_2_2 { + opp@456000000,800,2,2 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <456000000>; }; - opp@456000000_800_3_2 { + opp@456000000,800,3,2 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <456000000>; }; - opp@456000000_825 { + opp@456000000,825 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <456000000>; }; - opp@608000000_750 { + opp@608000000,750 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0003>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000_800 { + opp@608000000,800 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0006>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000_800_3_2 { + opp@608000000,800,3,2 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000_825 { + opp@608000000,825 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0001>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000_850 { + opp@608000000,850 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0006>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000_900 { + opp@608000000,900 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <608000000>; }; - opp@760000000_775 { + opp@760000000,775 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0003>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_800 { + opp@760000000,800 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_850 { + opp@760000000,850 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0006>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_875 { + opp@760000000,875 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0001>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_875_1_1 { + opp@760000000,875,1,1 { clock-latency-ns = <400000>; opp-supported-hw = <0x02 0x0002>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_875_0_2 { + opp@760000000,875,0,2 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0004>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_875_1_2 { + opp@760000000,875,1,2 { clock-latency-ns = <400000>; opp-supported-hw = <0x02 0x0004>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900 { + opp@760000000,900 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0002>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_975 { + opp@760000000,975 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <760000000>; }; - opp@816000000_800 { + opp@816000000,800 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0007>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000_850 { + opp@816000000,850 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000_875 { + opp@816000000,875 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0005>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000_950 { + opp@816000000,950 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0006>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000_1000 { + opp@816000000,1000 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <816000000>; }; - opp@912000000_850 { + opp@912000000,850 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0007>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000_900 { + opp@912000000,900 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000_925 { + opp@912000000,925 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0001>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000_950 { + opp@912000000,950 { clock-latency-ns = <400000>; opp-supported-hw = <0x02 0x0006>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000_950_0_2 { + opp@912000000,950,0,2 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0004>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000_950_2_2 { + opp@912000000,950,2,2 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000_1000 { + opp@912000000,1000 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0002>; opp-hz = /bits/ 64 <912000000>; }; - opp@912000000_1050 { + opp@912000000,1050 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <912000000>; }; - opp@1000000000_875 { + opp@1000000000,875 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0007>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_900 { + opp@1000000000,900 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_950 { + opp@1000000000,950 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975 { + opp@1000000000,975 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0001>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_1000 { + opp@1000000000,1000 { clock-latency-ns = <400000>; opp-supported-hw = <0x02 0x0006>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_1000_0_2 { + opp@1000000000,1000,0,2 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0004>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_1025 { + opp@1000000000,1025 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0002>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_1100 { + opp@1000000000,1100 { clock-latency-ns = <400000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1200000000_1000 { + opp@1200000000,1000 { clock-latency-ns = <400000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1050 { + opp@1200000000,1050 { clock-latency-ns = <400000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1100 { + opp@1200000000,1100 { clock-latency-ns = <400000>; opp-supported-hw = <0x02 0x0004>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1125 { + opp@1200000000,1125 { clock-latency-ns = <400000>; opp-supported-hw = <0x01 0x0004>; opp-hz = /bits/ 64 <1200000000>; diff --git a/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi b/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi index 5c40ef49894f..d682f7437146 100644 --- a/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi +++ b/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi @@ -2,799 +2,799 @@ / { cpu0_opp_table: cpu_opp_table0 { - opp@51000000_800 { + opp@51000000,800 { opp-microvolt = <800000 800000 1250000>; }; - opp@51000000_850 { + opp@51000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@51000000_912 { + opp@51000000,912 { opp-microvolt = <912000 912000 1250000>; }; - opp@102000000_800 { + opp@102000000,800 { opp-microvolt = <800000 800000 1250000>; }; - opp@102000000_850 { + opp@102000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@102000000_912 { + opp@102000000,912 { opp-microvolt = <912000 912000 1250000>; }; - opp@204000000_800 { + opp@204000000,800 { opp-microvolt = <800000 800000 1250000>; }; - opp@204000000_850 { + opp@204000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@204000000_912 { + opp@204000000,912 { opp-microvolt = <912000 912000 1250000>; }; - opp@312000000_850 { + opp@312000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@312000000_912 { + opp@312000000,912 { opp-microvolt = <912000 912000 1250000>; }; - opp@340000000_800 { + opp@340000000,800 { opp-microvolt = <800000 800000 1250000>; }; - opp@340000000_850 { + opp@340000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@370000000_800 { + opp@370000000,800 { opp-microvolt = <800000 800000 1250000>; }; - opp@456000000_850 { + opp@456000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@456000000_912 { + opp@456000000,912 { opp-microvolt = <912000 912000 1250000>; }; - opp@475000000_800 { + opp@475000000,800 { opp-microvolt = <800000 800000 1250000>; }; - opp@475000000_850 { + opp@475000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@475000000_850_0_1 { + opp@475000000,850,0,1 { opp-microvolt = <850000 850000 1250000>; }; - opp@475000000_850_0_4 { + opp@475000000,850,0,4 { opp-microvolt = <850000 850000 1250000>; }; - opp@475000000_850_0_7 { + opp@475000000,850,0,7 { opp-microvolt = <850000 850000 1250000>; }; - opp@475000000_850_0_8 { + opp@475000000,850,0,8 { opp-microvolt = <850000 850000 1250000>; }; - opp@608000000_850 { + opp@608000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@608000000_912 { + opp@608000000,912 { opp-microvolt = <912000 912000 1250000>; }; - opp@620000000_850 { + opp@620000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850 { + opp@640000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_1_1 { + opp@640000000,850,1,1 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_2_1 { + opp@640000000,850,2,1 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_3_1 { + opp@640000000,850,3,1 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_1_4 { + opp@640000000,850,1,4 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_2_4 { + opp@640000000,850,2,4 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_3_4 { + opp@640000000,850,3,4 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_1_7 { + opp@640000000,850,1,7 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_2_7 { + opp@640000000,850,2,7 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_3_7 { + opp@640000000,850,3,7 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_4_7 { + opp@640000000,850,4,7 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_1_8 { + opp@640000000,850,1,8 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_2_8 { + opp@640000000,850,2,8 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_3_8 { + opp@640000000,850,3,8 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_850_4_8 { + opp@640000000,850,4,8 { opp-microvolt = <850000 850000 1250000>; }; - opp@640000000_900 { + opp@640000000,900 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_850 { + opp@760000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@760000000_850_3_1 { + opp@760000000,850,3,1 { opp-microvolt = <850000 850000 1250000>; }; - opp@760000000_850_3_2 { + opp@760000000,850,3,2 { opp-microvolt = <850000 850000 1250000>; }; - opp@760000000_850_3_3 { + opp@760000000,850,3,3 { opp-microvolt = <850000 850000 1250000>; }; - opp@760000000_850_3_4 { + opp@760000000,850,3,4 { opp-microvolt = <850000 850000 1250000>; }; - opp@760000000_850_3_7 { + opp@760000000,850,3,7 { opp-microvolt = <850000 850000 1250000>; }; - opp@760000000_850_4_7 { + opp@760000000,850,4,7 { opp-microvolt = <850000 850000 1250000>; }; - opp@760000000_850_3_8 { + opp@760000000,850,3,8 { opp-microvolt = <850000 850000 1250000>; }; - opp@760000000_850_4_8 { + opp@760000000,850,4,8 { opp-microvolt = <850000 850000 1250000>; }; - opp@760000000_850_0_10 { + opp@760000000,850,0,10 { opp-microvolt = <850000 850000 1250000>; }; - opp@760000000_900 { + opp@760000000,900 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_1_1 { + opp@760000000,900,1,1 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_2_1 { + opp@760000000,900,2,1 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_1_2 { + opp@760000000,900,1,2 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_2_2 { + opp@760000000,900,2,2 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_1_3 { + opp@760000000,900,1,3 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_2_3 { + opp@760000000,900,2,3 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_1_4 { + opp@760000000,900,1,4 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_2_4 { + opp@760000000,900,2,4 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_1_7 { + opp@760000000,900,1,7 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_2_7 { + opp@760000000,900,2,7 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_1_8 { + opp@760000000,900,1,8 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_900_2_8 { + opp@760000000,900,2,8 { opp-microvolt = <900000 900000 1250000>; }; - opp@760000000_912 { + opp@760000000,912 { opp-microvolt = <912000 912000 1250000>; }; - opp@760000000_975 { + opp@760000000,975 { opp-microvolt = <975000 975000 1250000>; }; - opp@816000000_850 { + opp@816000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@816000000_912 { + opp@816000000,912 { opp-microvolt = <912000 912000 1250000>; }; - opp@860000000_850 { + opp@860000000,850 { opp-microvolt = <850000 850000 1250000>; }; - opp@860000000_900 { + opp@860000000,900 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_2_1 { + opp@860000000,900,2,1 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_3_1 { + opp@860000000,900,3,1 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_2_2 { + opp@860000000,900,2,2 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_3_2 { + opp@860000000,900,3,2 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_2_3 { + opp@860000000,900,2,3 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_3_3 { + opp@860000000,900,3,3 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_2_4 { + opp@860000000,900,2,4 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_3_4 { + opp@860000000,900,3,4 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_2_7 { + opp@860000000,900,2,7 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_3_7 { + opp@860000000,900,3,7 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_4_7 { + opp@860000000,900,4,7 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_2_8 { + opp@860000000,900,2,8 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_3_8 { + opp@860000000,900,3,8 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_900_4_8 { + opp@860000000,900,4,8 { opp-microvolt = <900000 900000 1250000>; }; - opp@860000000_975 { + opp@860000000,975 { opp-microvolt = <975000 975000 1250000>; }; - opp@860000000_975_1_1 { + opp@860000000,975,1,1 { opp-microvolt = <975000 975000 1250000>; }; - opp@860000000_975_1_2 { + opp@860000000,975,1,2 { opp-microvolt = <975000 975000 1250000>; }; - opp@860000000_975_1_3 { + opp@860000000,975,1,3 { opp-microvolt = <975000 975000 1250000>; }; - opp@860000000_975_1_4 { + opp@860000000,975,1,4 { opp-microvolt = <975000 975000 1250000>; }; - opp@860000000_975_1_7 { + opp@860000000,975,1,7 { opp-microvolt = <975000 975000 1250000>; }; - opp@860000000_975_1_8 { + opp@860000000,975,1,8 { opp-microvolt = <975000 975000 1250000>; }; - opp@860000000_1000 { + opp@860000000,1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@910000000_900 { + opp@910000000,900 { opp-microvolt = <900000 900000 1250000>; }; - opp@1000000000_900 { + opp@1000000000,900 { opp-microvolt = <900000 900000 1250000>; }; - opp@1000000000_975 { + opp@1000000000,975 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_2_1 { + opp@1000000000,975,2,1 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_3_1 { + opp@1000000000,975,3,1 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_2_2 { + opp@1000000000,975,2,2 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_3_2 { + opp@1000000000,975,3,2 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_2_3 { + opp@1000000000,975,2,3 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_3_3 { + opp@1000000000,975,3,3 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_2_4 { + opp@1000000000,975,2,4 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_3_4 { + opp@1000000000,975,3,4 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_2_7 { + opp@1000000000,975,2,7 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_3_7 { + opp@1000000000,975,3,7 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_4_7 { + opp@1000000000,975,4,7 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_2_8 { + opp@1000000000,975,2,8 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_3_8 { + opp@1000000000,975,3,8 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_975_4_8 { + opp@1000000000,975,4,8 { opp-microvolt = <975000 975000 1250000>; }; - opp@1000000000_1000 { + opp@1000000000,1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1000000000_1025 { + opp@1000000000,1025 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1100000000_900 { + opp@1100000000,900 { opp-microvolt = <900000 900000 1250000>; }; - opp@1100000000_975 { + opp@1100000000,975 { opp-microvolt = <975000 975000 1250000>; }; - opp@1100000000_975_3_1 { + opp@1100000000,975,3,1 { opp-microvolt = <975000 975000 1250000>; }; - opp@1100000000_975_3_2 { + opp@1100000000,975,3,2 { opp-microvolt = <975000 975000 1250000>; }; - opp@1100000000_975_3_3 { + opp@1100000000,975,3,3 { opp-microvolt = <975000 975000 1250000>; }; - opp@1100000000_975_3_4 { + opp@1100000000,975,3,4 { opp-microvolt = <975000 975000 1250000>; }; - opp@1100000000_975_3_7 { + opp@1100000000,975,3,7 { opp-microvolt = <975000 975000 1250000>; }; - opp@1100000000_975_4_7 { + opp@1100000000,975,4,7 { opp-microvolt = <975000 975000 1250000>; }; - opp@1100000000_975_3_8 { + opp@1100000000,975,3,8 { opp-microvolt = <975000 975000 1250000>; }; - opp@1100000000_975_4_8 { + opp@1100000000,975,4,8 { opp-microvolt = <975000 975000 1250000>; }; - opp@1100000000_1000 { + opp@1100000000,1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1100000000_1000_2_1 { + opp@1100000000,1000,2,1 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1100000000_1000_2_2 { + opp@1100000000,1000,2,2 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1100000000_1000_2_3 { + opp@1100000000,1000,2,3 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1100000000_1000_2_4 { + opp@1100000000,1000,2,4 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1100000000_1000_2_7 { + opp@1100000000,1000,2,7 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1100000000_1000_2_8 { + opp@1100000000,1000,2,8 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1100000000_1025 { + opp@1100000000,1025 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1100000000_1075 { + opp@1100000000,1075 { opp-microvolt = <1075000 1075000 1250000>; }; - opp@1150000000_975 { + opp@1150000000,975 { opp-microvolt = <975000 975000 1250000>; }; - opp@1200000000_975 { + opp@1200000000,975 { opp-microvolt = <975000 975000 1250000>; }; - opp@1200000000_1000 { + opp@1200000000,1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1200000000_1000_3_1 { + opp@1200000000,1000,3,1 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1200000000_1000_3_2 { + opp@1200000000,1000,3,2 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1200000000_1000_3_3 { + opp@1200000000,1000,3,3 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1200000000_1000_3_4 { + opp@1200000000,1000,3,4 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1200000000_1000_3_7 { + opp@1200000000,1000,3,7 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1200000000_1000_4_7 { + opp@1200000000,1000,4,7 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1200000000_1000_3_8 { + opp@1200000000,1000,3,8 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1200000000_1000_4_8 { + opp@1200000000,1000,4,8 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1200000000_1025 { + opp@1200000000,1025 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1200000000_1025_2_1 { + opp@1200000000,1025,2,1 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1200000000_1025_2_2 { + opp@1200000000,1025,2,2 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1200000000_1025_2_3 { + opp@1200000000,1025,2,3 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1200000000_1025_2_4 { + opp@1200000000,1025,2,4 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1200000000_1025_2_7 { + opp@1200000000,1025,2,7 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1200000000_1025_2_8 { + opp@1200000000,1025,2,8 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1200000000_1050 { + opp@1200000000,1050 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1200000000_1075 { + opp@1200000000,1075 { opp-microvolt = <1075000 1075000 1250000>; }; - opp@1200000000_1100 { + opp@1200000000,1100 { opp-microvolt = <1100000 1100000 1250000>; }; - opp@1300000000_1000 { + opp@1300000000,1000 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1300000000_1000_4_7 { + opp@1300000000,1000,4,7 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1300000000_1000_4_8 { + opp@1300000000,1000,4,8 { opp-microvolt = <1000000 1000000 1250000>; }; - opp@1300000000_1025 { + opp@1300000000,1025 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1300000000_1025_3_1 { + opp@1300000000,1025,3,1 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1300000000_1025_3_7 { + opp@1300000000,1025,3,7 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1300000000_1025_3_8 { + opp@1300000000,1025,3,8 { opp-microvolt = <1025000 1025000 1250000>; }; - opp@1300000000_1050 { + opp@1300000000,1050 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000_1050_2_1 { + opp@1300000000,1050,2,1 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000_1050_3_2 { + opp@1300000000,1050,3,2 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000_1050_3_3 { + opp@1300000000,1050,3,3 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000_1050_3_4 { + opp@1300000000,1050,3,4 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000_1050_3_5 { + opp@1300000000,1050,3,5 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000_1050_3_6 { + opp@1300000000,1050,3,6 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000_1050_2_7 { + opp@1300000000,1050,2,7 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000_1050_2_8 { + opp@1300000000,1050,2,8 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000_1050_3_12 { + opp@1300000000,1050,3,12 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000_1050_3_13 { + opp@1300000000,1050,3,13 { opp-microvolt = <1050000 1050000 1250000>; }; - opp@1300000000_1075 { + opp@1300000000,1075 { opp-microvolt = <1075000 1075000 1250000>; }; - opp@1300000000_1075_2_2 { + opp@1300000000,1075,2,2 { opp-microvolt = <1075000 1075000 1250000>; }; - opp@1300000000_1075_2_3 { + opp@1300000000,1075,2,3 { opp-microvolt = <1075000 1075000 1250000>; }; - opp@1300000000_1075_2_4 { + opp@1300000000,1075,2,4 { opp-microvolt = <1075000 1075000 1250000>; }; - opp@1300000000_1100 { + opp@1300000000,1100 { opp-microvolt = <1100000 1100000 1250000>; }; - opp@1300000000_1125 { + opp@1300000000,1125 { opp-microvolt = <1125000 1125000 1250000>; }; - opp@1300000000_1150 { + opp@1300000000,1150 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1300000000_1175 { + opp@1300000000,1175 { opp-microvolt = <1175000 1175000 1250000>; }; - opp@1400000000_1100 { + opp@1400000000,1100 { opp-microvolt = <1100000 1100000 1250000>; }; - opp@1400000000_1125 { + opp@1400000000,1125 { opp-microvolt = <1125000 1125000 1250000>; }; - opp@1400000000_1150 { + opp@1400000000,1150 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1400000000_1150_2_4 { + opp@1400000000,1150,2,4 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1400000000_1175 { + opp@1400000000,1175 { opp-microvolt = <1175000 1175000 1250000>; }; - opp@1400000000_1237 { + opp@1400000000,1237 { opp-microvolt = <1237000 1237000 1250000>; }; - opp@1500000000_1125 { + opp@1500000000,1125 { opp-microvolt = <1125000 1125000 1250000>; }; - opp@1500000000_1125_4_5 { + opp@1500000000,1125,4,5 { opp-microvolt = <1125000 1125000 1250000>; }; - opp@1500000000_1125_4_6 { + opp@1500000000,1125,4,6 { opp-microvolt = <1125000 1125000 1250000>; }; - opp@1500000000_1125_4_12 { + opp@1500000000,1125,4,12 { opp-microvolt = <1125000 1125000 1250000>; }; - opp@1500000000_1125_4_13 { + opp@1500000000,1125,4,13 { opp-microvolt = <1125000 1125000 1250000>; }; - opp@1500000000_1150 { + opp@1500000000,1150 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1500000000_1150_3_5 { + opp@1500000000,1150,3,5 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1500000000_1150_3_6 { + opp@1500000000,1150,3,6 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1500000000_1150_3_12 { + opp@1500000000,1150,3,12 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1500000000_1150_3_13 { + opp@1500000000,1150,3,13 { opp-microvolt = <1150000 1150000 1250000>; }; - opp@1500000000_1200 { + opp@1500000000,1200 { opp-microvolt = <1200000 1200000 1250000>; }; - opp@1500000000_1237 { + opp@1500000000,1237 { opp-microvolt = <1237000 1237000 1250000>; }; - opp@1600000000_1212 { + opp@1600000000,1212 { opp-microvolt = <1212000 1212000 1250000>; }; - opp@1600000000_1237 { + opp@1600000000,1237 { opp-microvolt = <1237000 1237000 1250000>; }; - opp@1700000000_1212 { + opp@1700000000,1212 { opp-microvolt = <1212000 1212000 1250000>; }; - opp@1700000000_1237 { + opp@1700000000,1237 { opp-microvolt = <1237000 1237000 1250000>; }; }; diff --git a/arch/arm/boot/dts/tegra30-cpu-opp.dtsi b/arch/arm/boot/dts/tegra30-cpu-opp.dtsi index d64fc262585e..8e434f6713cd 100644 --- a/arch/arm/boot/dts/tegra30-cpu-opp.dtsi +++ b/arch/arm/boot/dts/tegra30-cpu-opp.dtsi @@ -5,1195 +5,1195 @@ cpu0_opp_table: cpu_opp_table0 { compatible = "operating-points-v2"; opp-shared; - opp@51000000_800 { + opp@51000000,800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x31FE>; opp-hz = /bits/ 64 <51000000>; }; - opp@51000000_850 { + opp@51000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C01>; opp-hz = /bits/ 64 <51000000>; }; - opp@51000000_912 { + opp@51000000,912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <51000000>; }; - opp@102000000_800 { + opp@102000000,800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x31FE>; opp-hz = /bits/ 64 <102000000>; }; - opp@102000000_850 { + opp@102000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C01>; opp-hz = /bits/ 64 <102000000>; }; - opp@102000000_912 { + opp@102000000,912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <102000000>; }; - opp@204000000_800 { + opp@204000000,800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x31FE>; opp-hz = /bits/ 64 <204000000>; }; - opp@204000000_850 { + opp@204000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C01>; opp-hz = /bits/ 64 <204000000>; }; - opp@204000000_912 { + opp@204000000,912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <204000000>; }; - opp@312000000_850 { + opp@312000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C00>; opp-hz = /bits/ 64 <312000000>; }; - opp@312000000_912 { + opp@312000000,912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <312000000>; }; - opp@340000000_800 { + opp@340000000,800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0192>; opp-hz = /bits/ 64 <340000000>; }; - opp@340000000_850 { + opp@340000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x0F 0x0001>; opp-hz = /bits/ 64 <340000000>; }; - opp@370000000_800 { + opp@370000000,800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1E 0x306C>; opp-hz = /bits/ 64 <370000000>; }; - opp@456000000_850 { + opp@456000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0C00>; opp-hz = /bits/ 64 <456000000>; }; - opp@456000000_912 { + opp@456000000,912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <456000000>; }; - opp@475000000_800 { + opp@475000000,800 { clock-latency-ns = <100000>; opp-supported-hw = <0x1E 0x31FE>; opp-hz = /bits/ 64 <475000000>; }; - opp@475000000_850 { + opp@475000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x0F 0x0001>; opp-hz = /bits/ 64 <475000000>; }; - opp@475000000_850_0_1 { + opp@475000000,850,0,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0002>; opp-hz = /bits/ 64 <475000000>; }; - opp@475000000_850_0_4 { + opp@475000000,850,0,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0010>; opp-hz = /bits/ 64 <475000000>; }; - opp@475000000_850_0_7 { + opp@475000000,850,0,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0080>; opp-hz = /bits/ 64 <475000000>; }; - opp@475000000_850_0_8 { + opp@475000000,850,0,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0100>; opp-hz = /bits/ 64 <475000000>; }; - opp@608000000_850 { + opp@608000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0400>; opp-hz = /bits/ 64 <608000000>; }; - opp@608000000_912 { + opp@608000000,912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <608000000>; }; - opp@620000000_850 { + opp@620000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1E 0x306C>; opp-hz = /bits/ 64 <620000000>; }; - opp@640000000_850 { + opp@640000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x0F 0x0001>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_1_1 { + opp@640000000,850,1,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0002>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_2_1 { + opp@640000000,850,2,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_3_1 { + opp@640000000,850,3,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0002>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_1_4 { + opp@640000000,850,1,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0010>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_2_4 { + opp@640000000,850,2,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0010>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_3_4 { + opp@640000000,850,3,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0010>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_1_7 { + opp@640000000,850,1,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0080>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_2_7 { + opp@640000000,850,2,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0080>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_3_7 { + opp@640000000,850,3,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0080>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_4_7 { + opp@640000000,850,4,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0080>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_1_8 { + opp@640000000,850,1,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0100>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_2_8 { + opp@640000000,850,2,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0100>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_3_8 { + opp@640000000,850,3,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0100>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_850_4_8 { + opp@640000000,850,4,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0100>; opp-hz = /bits/ 64 <640000000>; }; - opp@640000000_900 { + opp@640000000,900 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <640000000>; }; - opp@760000000_850 { + opp@760000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1E 0x3461>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_850_3_1 { + opp@760000000,850,3,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0002>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_850_3_2 { + opp@760000000,850,3,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_850_3_3 { + opp@760000000,850,3,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0008>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_850_3_4 { + opp@760000000,850,3,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0010>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_850_3_7 { + opp@760000000,850,3,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0080>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_850_4_7 { + opp@760000000,850,4,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0080>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_850_3_8 { + opp@760000000,850,3,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0100>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_850_4_8 { + opp@760000000,850,4,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0100>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_850_0_10 { + opp@760000000,850,0,10 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0400>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900 { + opp@760000000,900 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_1_1 { + opp@760000000,900,1,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0002>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_2_1 { + opp@760000000,900,2,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_1_2 { + opp@760000000,900,1,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0004>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_2_2 { + opp@760000000,900,2,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_1_3 { + opp@760000000,900,1,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0008>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_2_3 { + opp@760000000,900,2,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0008>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_1_4 { + opp@760000000,900,1,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0010>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_2_4 { + opp@760000000,900,2,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0010>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_1_7 { + opp@760000000,900,1,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0080>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_2_7 { + opp@760000000,900,2,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0080>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_1_8 { + opp@760000000,900,1,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0100>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_900_2_8 { + opp@760000000,900,2,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0100>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_912 { + opp@760000000,912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <760000000>; }; - opp@760000000_975 { + opp@760000000,975 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <760000000>; }; - opp@816000000_850 { + opp@816000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0400>; opp-hz = /bits/ 64 <816000000>; }; - opp@816000000_912 { + opp@816000000,912 { clock-latency-ns = <100000>; opp-supported-hw = <0x1F 0x0200>; opp-hz = /bits/ 64 <816000000>; }; - opp@860000000_850 { + opp@860000000,850 { clock-latency-ns = <100000>; opp-supported-hw = <0x0C 0x0001>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900 { + opp@860000000,900 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0001>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_2_1 { + opp@860000000,900,2,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_3_1 { + opp@860000000,900,3,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0002>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_2_2 { + opp@860000000,900,2,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_3_2 { + opp@860000000,900,3,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_2_3 { + opp@860000000,900,2,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0008>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_3_3 { + opp@860000000,900,3,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0008>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_2_4 { + opp@860000000,900,2,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0010>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_3_4 { + opp@860000000,900,3,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0010>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_2_7 { + opp@860000000,900,2,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0080>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_3_7 { + opp@860000000,900,3,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0080>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_4_7 { + opp@860000000,900,4,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0080>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_2_8 { + opp@860000000,900,2,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0100>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_3_8 { + opp@860000000,900,3,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0100>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_900_4_8 { + opp@860000000,900,4,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0100>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_975 { + opp@860000000,975 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_975_1_1 { + opp@860000000,975,1,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0002>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_975_1_2 { + opp@860000000,975,1,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0004>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_975_1_3 { + opp@860000000,975,1,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0008>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_975_1_4 { + opp@860000000,975,1,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0010>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_975_1_7 { + opp@860000000,975,1,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0080>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_975_1_8 { + opp@860000000,975,1,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0100>; opp-hz = /bits/ 64 <860000000>; }; - opp@860000000_1000 { + opp@860000000,1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <860000000>; }; - opp@910000000_900 { + opp@910000000,900 { clock-latency-ns = <100000>; opp-supported-hw = <0x18 0x3060>; opp-hz = /bits/ 64 <910000000>; }; - opp@1000000000_900 { + opp@1000000000,900 { clock-latency-ns = <100000>; opp-supported-hw = <0x0C 0x0001>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975 { + opp@1000000000,975 { clock-latency-ns = <100000>; opp-supported-hw = <0x03 0x0001>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_2_1 { + opp@1000000000,975,2,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_3_1 { + opp@1000000000,975,3,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0002>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_2_2 { + opp@1000000000,975,2,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_3_2 { + opp@1000000000,975,3,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_2_3 { + opp@1000000000,975,2,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0008>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_3_3 { + opp@1000000000,975,3,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0008>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_2_4 { + opp@1000000000,975,2,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0010>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_3_4 { + opp@1000000000,975,3,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0010>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_2_7 { + opp@1000000000,975,2,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0080>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_3_7 { + opp@1000000000,975,3,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0080>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_4_7 { + opp@1000000000,975,4,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0080>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_2_8 { + opp@1000000000,975,2,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0100>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_3_8 { + opp@1000000000,975,3,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0100>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_975_4_8 { + opp@1000000000,975,4,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0100>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_1000 { + opp@1000000000,1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x019E>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1000000000_1025 { + opp@1000000000,1025 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <1000000000>; }; - opp@1100000000_900 { + opp@1100000000,900 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0001>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_975 { + opp@1100000000,975 { clock-latency-ns = <100000>; opp-supported-hw = <0x06 0x0001>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_975_3_1 { + opp@1100000000,975,3,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0002>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_975_3_2 { + opp@1100000000,975,3,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_975_3_3 { + opp@1100000000,975,3,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0008>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_975_3_4 { + opp@1100000000,975,3,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0010>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_975_3_7 { + opp@1100000000,975,3,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0080>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_975_4_7 { + opp@1100000000,975,4,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0080>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_975_3_8 { + opp@1100000000,975,3,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0100>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_975_4_8 { + opp@1100000000,975,4,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0100>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_1000 { + opp@1100000000,1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_1000_2_1 { + opp@1100000000,1000,2,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_1000_2_2 { + opp@1100000000,1000,2,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_1000_2_3 { + opp@1100000000,1000,2,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0008>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_1000_2_4 { + opp@1100000000,1000,2,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0010>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_1000_2_7 { + opp@1100000000,1000,2,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0080>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_1000_2_8 { + opp@1100000000,1000,2,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0100>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_1025 { + opp@1100000000,1025 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x019E>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1100000000_1075 { + opp@1100000000,1075 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <1100000000>; }; - opp@1150000000_975 { + opp@1150000000,975 { clock-latency-ns = <100000>; opp-supported-hw = <0x18 0x3060>; opp-hz = /bits/ 64 <1150000000>; }; - opp@1200000000_975 { + opp@1200000000,975 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0001>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1000 { + opp@1200000000,1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0001>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1000_3_1 { + opp@1200000000,1000,3,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0002>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1000_3_2 { + opp@1200000000,1000,3,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1000_3_3 { + opp@1200000000,1000,3,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0008>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1000_3_4 { + opp@1200000000,1000,3,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0010>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1000_3_7 { + opp@1200000000,1000,3,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0080>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1000_4_7 { + opp@1200000000,1000,4,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0080>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1000_3_8 { + opp@1200000000,1000,3,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0100>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1000_4_8 { + opp@1200000000,1000,4,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0100>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1025 { + opp@1200000000,1025 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0001>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1025_2_1 { + opp@1200000000,1025,2,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1025_2_2 { + opp@1200000000,1025,2,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1025_2_3 { + opp@1200000000,1025,2,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0008>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1025_2_4 { + opp@1200000000,1025,2,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0010>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1025_2_7 { + opp@1200000000,1025,2,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0080>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1025_2_8 { + opp@1200000000,1025,2,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0100>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1050 { + opp@1200000000,1050 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x019E>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1075 { + opp@1200000000,1075 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1200000000_1100 { + opp@1200000000,1100 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0192>; opp-hz = /bits/ 64 <1200000000>; }; - opp@1300000000_1000 { + opp@1300000000,1000 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0001>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1000_4_7 { + opp@1300000000,1000,4,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0080>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1000_4_8 { + opp@1300000000,1000,4,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0100>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1025 { + opp@1300000000,1025 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0001>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1025_3_1 { + opp@1300000000,1025,3,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0002>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1025_3_7 { + opp@1300000000,1025,3,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0080>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1025_3_8 { + opp@1300000000,1025,3,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0100>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1050 { + opp@1300000000,1050 { clock-latency-ns = <100000>; opp-supported-hw = <0x12 0x3061>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1050_2_1 { + opp@1300000000,1050,2,1 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0002>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1050_3_2 { + opp@1300000000,1050,3,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0004>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1050_3_3 { + opp@1300000000,1050,3,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0008>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1050_3_4 { + opp@1300000000,1050,3,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0010>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1050_3_5 { + opp@1300000000,1050,3,5 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0020>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1050_3_6 { + opp@1300000000,1050,3,6 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0040>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1050_2_7 { + opp@1300000000,1050,2,7 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0080>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1050_2_8 { + opp@1300000000,1050,2,8 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0100>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1050_3_12 { + opp@1300000000,1050,3,12 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x1000>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1050_3_13 { + opp@1300000000,1050,3,13 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x2000>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1075 { + opp@1300000000,1075 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0182>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1075_2_2 { + opp@1300000000,1075,2,2 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0004>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1075_2_3 { + opp@1300000000,1075,2,3 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0008>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1075_2_4 { + opp@1300000000,1075,2,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0010>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1100 { + opp@1300000000,1100 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x001C>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1125 { + opp@1300000000,1125 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0001>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1150 { + opp@1300000000,1150 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0182>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1300000000_1175 { + opp@1300000000,1175 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0010>; opp-hz = /bits/ 64 <1300000000>; }; - opp@1400000000_1100 { + opp@1400000000,1100 { clock-latency-ns = <100000>; opp-supported-hw = <0x18 0x307C>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1400000000_1125 { + opp@1400000000,1125 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x000C>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1400000000_1150 { + opp@1400000000,1150 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x000C>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1400000000_1150_2_4 { + opp@1400000000,1150,2,4 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0010>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1400000000_1175 { + opp@1400000000,1175 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0010>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1400000000_1237 { + opp@1400000000,1237 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0010>; opp-hz = /bits/ 64 <1400000000>; }; - opp@1500000000_1125 { + opp@1500000000,1125 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0010>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000_1125_4_5 { + opp@1500000000,1125,4,5 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0020>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000_1125_4_6 { + opp@1500000000,1125,4,6 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x0040>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000_1125_4_12 { + opp@1500000000,1125,4,12 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x1000>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000_1125_4_13 { + opp@1500000000,1125,4,13 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x2000>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000_1150 { + opp@1500000000,1150 { clock-latency-ns = <100000>; opp-supported-hw = <0x04 0x0010>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000_1150_3_5 { + opp@1500000000,1150,3,5 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0020>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000_1150_3_6 { + opp@1500000000,1150,3,6 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x0040>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000_1150_3_12 { + opp@1500000000,1150,3,12 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x1000>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000_1150_3_13 { + opp@1500000000,1150,3,13 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x2000>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000_1200 { + opp@1500000000,1200 { clock-latency-ns = <100000>; opp-supported-hw = <0x02 0x0010>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1500000000_1237 { + opp@1500000000,1237 { clock-latency-ns = <100000>; opp-supported-hw = <0x01 0x0010>; opp-hz = /bits/ 64 <1500000000>; }; - opp@1600000000_1212 { + opp@1600000000,1212 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x3060>; opp-hz = /bits/ 64 <1600000000>; }; - opp@1600000000_1237 { + opp@1600000000,1237 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x3060>; opp-hz = /bits/ 64 <1600000000>; }; - opp@1700000000_1212 { + opp@1700000000,1212 { clock-latency-ns = <100000>; opp-supported-hw = <0x10 0x3060>; opp-hz = /bits/ 64 <1700000000>; }; - opp@1700000000_1237 { + opp@1700000000,1237 { clock-latency-ns = <100000>; opp-supported-hw = <0x08 0x3060>; opp-hz = /bits/ 64 <1700000000>; From patchwork Tue Jun 16 13:51:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310374 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; 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Tue, 16 Jun 2020 06:53:53 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id r12sm30951520wrc.22.2020.06.16.06.53.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:53:48 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 26/73] ARM: tegra: medcom-wide: Remove extra panel power supply Date: Tue, 16 Jun 2020 15:51:51 +0200 Message-Id: <20200616135238.3001888-27-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Simple panels can only have a single power supply. The second listed supply is not needed because it is also the input supply of the first supply and therefore will always be on at the same time. In retrospect the panel probably doesn't qualify as simple since it apparently does need both of these supplies, even if in the case of the Medcom Wide it isn't necessary to explicitly hook them up. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-medcom-wide.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index 049181421a86..a348ca30e522 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -59,7 +59,7 @@ backlight: backlight { panel: panel { compatible = "innolux,n156bge-l21"; - power-supply = <&vdd_1v8_reg>, <&vdd_3v3_reg>; + power-supply = <&vdd_1v8_reg>; // <&vdd_3v3_reg>; enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; backlight = <&backlight>; From patchwork Tue Jun 16 13:51:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310376 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=WWyDyBs5; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV6Z4mV1z9sRN for ; Tue, 16 Jun 2020 23:53:58 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728908AbgFPNx6 (ORCPT ); Tue, 16 Jun 2020 09:53:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728899AbgFPNx5 (ORCPT ); Tue, 16 Jun 2020 09:53:57 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 626F6C061573 for ; Tue, 16 Jun 2020 06:53:57 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id t194so3162443wmt.4 for ; Tue, 16 Jun 2020 06:53:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M3L/vhQHjDE+C9l0qudwi26/w+psczXMcfOt270RlEk=; b=WWyDyBs5/lglLdztMlKeP3eCq3IT9zB+pSBDzV9On7VRvPoGZ1onDmxKvlIMUrflCA DnBR2rYBuhKNuxgqb0YNj/i+ahf5DQJMe3n+MDHHao8lnCuiTyZ1Q/T2NH9RTqBDufET 2WAN93v80t/wOu8ts5CYozmiqXUc9rYrkHy6KG0vZlohFvGWYzwO0A+keYAaFmDZLegV COMXdLz1S7ilS9BWHHZZssaVViCxzgmnDaArUxuYBP8begs2RtG3+IRthhMFP5njP0qW 64urTl/UfKAZM63kk6Mfy+KJXzVwFgs1aYlxQoZjpMUbLxp6fRiZr0njqrQY6dkBT5Xw s1bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M3L/vhQHjDE+C9l0qudwi26/w+psczXMcfOt270RlEk=; b=f9odwD7N6QibnGMIimzoRdiUHqHIHtbzRhIyc8rUsk1l5nZHkqS3cE2ODFHtB2zDUe IbcXQHQJDQkQ6H4KALi3+nTF+Gwc6725TWEWo9alhDjZnO7lB7HCxsIMC+tMCHBusELj ly9TKJgAJEjNN8Ab9pCUlFxqPD5M1sT9M2VZbtOUvF09yHxwSxD+ffvGjV0Rj5wybECD AeuQcNBPfZmirfHEKUiOkADI95qCQBSirf38/BMNO71Fr29DfoOt9lSZuo2WPXWP14Ip 3cmI1nEVFVZIdSCXYpegdjLeAYFIr8AuACj1cgx96RAeD5Xkt84Aluj6+99Wf/IQdyBW 7FRQ== X-Gm-Message-State: AOAM53217iKzkIgbYcuE7eaIXRsgXaC1StioJdLNSELYi5/6tNIVFNQe 3X7MHVDAIFW3/kpS5fF+1nU= X-Google-Smtp-Source: ABdhPJzGk/jl8TeiUrND4uefnaHAqsSQ6+a99XBpUrP6SsfayTbaa6VwGdJdqbB2VWl0LieJIkYi2w== X-Received: by 2002:a7b:c842:: with SMTP id c2mr3404588wml.58.1592315636193; Tue, 16 Jun 2020 06:53:56 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id b143sm4139276wme.20.2020.06.16.06.53.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:53:54 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 27/73] ARM: tegra: Use numeric unit-addresses Date: Tue, 16 Jun 2020 15:51:52 +0200 Message-Id: <20200616135238.3001888-28-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Unit-addresses should be numeric. This fixes a validation failure seen using the json-schema tooling. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-paz00.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 91b6bb82e960..f6aa783b0f02 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -314,7 +314,7 @@ nvec@7000c500 { memory-controller@7000f400 { nvidia,use-ram-code; - emc-tables@hynix { + emc-tables@0 { nvidia,ram-code = <0x0>; #address-cells = <1>; #size-cells = <0>; From patchwork Tue Jun 16 13:51:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310380 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=WPl1istJ; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV6h5T2kz9sRN for ; Tue, 16 Jun 2020 23:54:04 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728917AbgFPNyD (ORCPT ); Tue, 16 Jun 2020 09:54:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728815AbgFPNyB (ORCPT ); Tue, 16 Jun 2020 09:54:01 -0400 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D66F0C061573 for ; Tue, 16 Jun 2020 06:53:59 -0700 (PDT) Received: by mail-wm1-x344.google.com with SMTP id r15so3158217wmh.5 for ; Tue, 16 Jun 2020 06:53:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CgHFXQGZCBEeJb+voRiLKHYUP+aolWvzm4Cf5SWvL0s=; b=WPl1istJDy6REda+MLJhcwq9sIrmI+2C7/zhWoTkvFxPVBO3D4w22LYcdMDihJ8UGa GVLD6TTwc9MTjhmvj4jxmqtnG0/istl+j0WTZMLQ1vSdfZN9oSfKWBf+dc93kArSZbCa 7VIQye4Q+5k+gji319QsIt+NQy9Ur83anQkUK4EQu5cIeZacrwPTnAE9nyMXUS4gtAug uB9Ryx8FndCP4daSd/46hZEw/Q1uViKpOTFuk2mZzAvcqjuzjtURz00VT8vaiQUKCVou JZa+pr3bVASW0L+KGmyOTz9u+P0NVI/Gh40GfeektaX9HyUv46P+ASGTDeL2qCHh/hHg j3oA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CgHFXQGZCBEeJb+voRiLKHYUP+aolWvzm4Cf5SWvL0s=; b=AAtaq/gVysTGyowm/agPYlXpIpocsRojHqIu2oBldF1siBHOpbK4NTnbxXlDl6ZXZe J3IBjPtnMMVkawIUw1mx5U5WFsPzkmXmWZ6JntoNs8LZUywKZ8TYg1DCYK1YZIGAKKIj 9e8LQTGmtNrnPIwZIZpNOPxRXROyN0thrNTTzjAt53ECYd3cT9ErtBfzQL1SBU4eiPdw 152l28USIi/oYS7QyMLI5C/Qm3rrMv28W7tcYmGWpdoT+XihpmpRD7B+IjxmQj9TPz/c Mv9skZvNE6uqtQ6y4vm51MlmR3N6TtF3XevsZIAHrpa4CRh2UIGRUnGpFthsaslUGdHi pbLQ== X-Gm-Message-State: AOAM530X1qJjKmCsY5bK8oFZ+uCGPLebMiq6yAkrCPKRspflU3xgc4BA 46QF2dRR1d40Vl+8lIQTVmE= X-Google-Smtp-Source: ABdhPJwA9Vln20BWen/PoW0PG0VaFlSCUK2CNP+GyGm8bz6amWfj+xqV/Tv4EQVld7V/6csj5gt8EA== X-Received: by 2002:a1c:7c0e:: with SMTP id x14mr3226376wmc.1.1592315638658; Tue, 16 Jun 2020 06:53:58 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id z12sm32056041wrg.9.2020.06.16.06.53.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:53:57 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 28/73] ARM: tegra: Use standard names for LED nodes Date: Tue, 16 Jun 2020 15:51:53 +0200 Message-Id: <20200616135238.3001888-29-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding LED nodes should be named led-* to match the bindings. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-paz00.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index f6aa783b0f02..ada2bed8b1b5 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -589,7 +589,7 @@ wakeup { gpio-leds { compatible = "gpio-leds"; - wifi { + led-0 { label = "wifi-led"; gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; linux,default-trigger = "rfkill0"; From patchwork Tue Jun 16 13:51:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310381 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=nlwgsg+o; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV6j406mz9sSg for ; Tue, 16 Jun 2020 23:54:05 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728815AbgFPNyD (ORCPT ); Tue, 16 Jun 2020 09:54:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728899AbgFPNyC (ORCPT ); Tue, 16 Jun 2020 09:54:02 -0400 Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0CC0C06174E for ; Tue, 16 Jun 2020 06:54:01 -0700 (PDT) Received: by mail-wm1-x341.google.com with SMTP id r9so2972938wmh.2 for ; Tue, 16 Jun 2020 06:54:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YuiLIUu/YnML9dFw4hu2Yeqj2POA+ml5uNhb4909fHI=; b=nlwgsg+ofktUw3Aw5uAsr+hgAEjUb5vgy4T/TfjNeRjK07MwLGNKm1rEBOkWy2jvjF WoKqKnwPQaRaa6LMAbTmnHJw7GPwdegAPwQ4U85tLvl3k/xoeQQrRxMml2ekLjVoHdYC h5BdCTnLbQ27lplp8fpBkUZrrwief5qAfWovQZ7mWqvan9sJ99DuFgs0WEEeW9X0jFui koigc9xrioJdheaFyNOYYMr+CeYdXdoOze0CAQjYccpf9F5PnpB3u5L0KOQNmLBL7IRV KyNgzuOkWOQmwnQw5L5PfKl3cUwogbbcSY8Wc/acBNDJ/7kbxsR5N0bwGb/2Pt/R5vKK AN8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YuiLIUu/YnML9dFw4hu2Yeqj2POA+ml5uNhb4909fHI=; b=HCEXDxR+r2TAMsQBFEBYWn741M/aQfvHG03YcoNwb5HPDBPONca1Qhj/ZCKdh+udp6 DPhR6de6wgF3O/WNnoefJiD9zCCyEt/JCZueT1nSHBm4Y5t5BhzYSotR0j2N1x0nHAYn IfHSCQlyq1GGcK/pwDByqNaLJWweQzPfsjWFnuFdfQdvsbhW7kb0zN1wnLbxo4uLMMwM nsNC0M6HFv6+8p1ILF6pJvcA1B7PHADc8rLYzx0VndX5De4uLB5CVEoKKw4DbYX//aEj WD/NcIFW+tUrIbeFcjO18Smk5JwccJFa0CgjRd890dUkSxwYW558TrDAg/NBd7cqs6IK 32MA== X-Gm-Message-State: AOAM530oDRWOa/iy6w7+v9XlMX/KqZ8V6bnmO2d/QqsZwaXRSILfX5jA LESW9dLdrEXesaf876ZoevA= X-Google-Smtp-Source: ABdhPJzLSUEeB11A9gIgfZR8uzltD2LdQNQ9FATlM6iL7NTpC0rwccouKcZkB398Df+o56LB614dSA== X-Received: by 2002:a1c:4b15:: with SMTP id y21mr3402842wma.32.1592315640615; Tue, 16 Jun 2020 06:54:00 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id h15sm27602787wrt.73.2020.06.16.06.53.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:53:59 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 29/73] ARM: tegra: seaboard: Use standard battery bindings Date: Tue, 16 Jun 2020 15:51:54 +0200 Message-Id: <20200616135238.3001888-30-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Seaboard uses a non-existing, possibly obsoleted, binding for the battery. Move to the standard binding which seems to be a super- set of the odl binding. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-seaboard.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index f1baf16c5010..c24d4a37613e 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -394,10 +394,10 @@ lvds_ddc: i2c@1 { #size-cells = <0>; smart-battery@b { - compatible = "ti,bq20z75", "smart-battery-1.1"; + compatible = "ti,bq20z75", "sbs,sbs-battery"; reg = <0xb>; - ti,i2c-retry-count = <2>; - ti,poll-retry-count = <10>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <10>; }; }; }; From patchwork Tue Jun 16 13:51:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310382 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=dpTouy5l; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV6k2NTqz9sT6 for ; Tue, 16 Jun 2020 23:54:06 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728931AbgFPNyE (ORCPT ); Tue, 16 Jun 2020 09:54:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728899AbgFPNyE (ORCPT ); Tue, 16 Jun 2020 09:54:04 -0400 Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E80EFC061573 for ; Tue, 16 Jun 2020 06:54:03 -0700 (PDT) Received: by mail-wm1-x341.google.com with SMTP id l26so2969178wme.3 for ; Tue, 16 Jun 2020 06:54:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tMYaQdji6zR5lZgb0sKLhTaK1Jb/52l/cl/I/Gv3TlY=; b=dpTouy5lnSQNwoKZkllwZ8r+NnHAugELmJre2azRgCaQxs5E5VP/CHt559N+CRRAJc r38la9JiGOAAgaAbB4vgHn+YjfN9gnaC3acHsy1NP8dTezZirBLxLUQpPdHuTPRFqOG6 S/AnbWdTVqfJcTl0VQqCI9NANyHEI28uZL7ZyzAlo2eYP5bqNOgCgU+FKfI+Xnii9Bbg AVDO1YqUWkb5H3vQo780+pJd7AufKtya7nEGgp02RK73QzU5T2LRbs9KalwYtmjpeuVz 12+6gsGppT6hPxq5VrxH0ZUY0Ari+gnw2Uir6EdF8yQ2es93YWReAj1dubVuk0ZAPKZw kNRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tMYaQdji6zR5lZgb0sKLhTaK1Jb/52l/cl/I/Gv3TlY=; b=iluASDekYBQT6DFWMdJmbBhiZmzfq6EtL0XLtxKWclK25WDDweH8GZldiW2p1f+zVa aPryEemPpVo699Z0b06YDjcauZUnkRCLZVJ0nYhhtQtBnhapU3yf1WRtrH4USdjC4cUv 9rRJ1yq3qwdkMmQ3mDhjl1fDxJ2sfhu5XDaM58Wb5ctIaRSU/IOReISrJFvp6j41cq83 t+yGllJMOqS1LhfRayGotw5I4/Xso3JDbMdYvfY464sbr1uIOaMo7vX+QSeEWvYWj+4c +Cxi/XoXesiRgE+VmtlBSL+r2aCmo9PqkjFoNOYg2g42mSq57hq0HEPrBFj6bUMPs6ho YmtQ== X-Gm-Message-State: AOAM531Kwh7ISvKm2CQzRf+O8RKyTH3vacj0TKbSAlbvqgdo768NsgrR V4Bmd0R/DpMaG//e2/8G9Nw= X-Google-Smtp-Source: ABdhPJyqXi3fI4wDpzEil4M7ad15F2TY4dvEOrQvYWH6fnTkBq/azOgr+vucDNV5uc/ts6EfAesU6g== X-Received: by 2002:a7b:cb18:: with SMTP id u24mr3441539wmj.67.1592315642652; Tue, 16 Jun 2020 06:54:02 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id 67sm30302842wrk.49.2020.06.16.06.54.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:54:01 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 30/73] ARM: tegra: Use standard names for SRAM nodes Date: Tue, 16 Jun 2020 15:51:55 +0200 Message-Id: <20200616135238.3001888-31-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding SRAM nodes should be named sram@ to match the bindings. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 4 ++-- arch/arm/boot/dts/tegra30.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index ccd2995aef83..2568236284ad 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -17,14 +17,14 @@ memory@0 { reg = <0 0>; }; - iram@40000000 { + sram@40000000 { compatible = "mmio-sram"; reg = <0x40000000 0x40000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40000000 0x40000>; - vde_pool: vde@400 { + vde_pool: sram@400 { reg = <0x400 0x3fc00>; pool; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index f838e4775cf6..690e1628860f 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -97,14 +97,14 @@ pci@3,0 { }; }; - iram@40000000 { + sram@40000000 { compatible = "mmio-sram"; reg = <0x40000000 0x40000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40000000 0x40000>; - vde_pool: vde@400 { + vde_pool: sram@400 { reg = <0x400 0x3fc00>; pool; }; From patchwork Tue Jun 16 13:51:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310383 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=jttMGiL+; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV6p4WvXz9sSS for ; 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Tue, 16 Jun 2020 06:54:03 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 31/73] ARM: tegra: Add parent clock to DSI output Date: Tue, 16 Jun 2020 15:51:56 +0200 Message-Id: <20200616135238.3001888-32-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The DSI output needs to specify a parent clock that will be used to drive both the output and the display controller. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 4 +++- arch/arm/boot/dts/tegra30.dtsi | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 2568236284ad..19d5d4b8692b 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -154,7 +154,9 @@ tvo@542c0000 { dsi@54300000 { compatible = "nvidia,tegra20-dsi"; reg = <0x54300000 0x00040000>; - clocks = <&tegra_car TEGRA20_CLK_DSI>; + clocks = <&tegra_car TEGRA20_CLK_DSI>, + <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; + clock-names = "dsi", "parent"; resets = <&tegra_car 48>; reset-names = "dsi"; status = "disabled"; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 690e1628860f..d80f9d3d2d18 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -255,7 +255,9 @@ tvo@542c0000 { dsi@54300000 { compatible = "nvidia,tegra30-dsi"; reg = <0x54300000 0x00040000>; - clocks = <&tegra_car TEGRA30_CLK_DSIA>; + clocks = <&tegra_car TEGRA30_CLK_DSIA>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + clock-names = "dsi", "parent"; resets = <&tegra_car 48>; reset-names = "dsi"; status = "disabled"; From patchwork Tue Jun 16 13:51:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310384 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=L5+uZE3I; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV6s6wM5z9sRK for ; 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Tue, 16 Jun 2020 06:54:05 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcel Ziswiler , Philippe Schenker Subject: [PATCH 32/73] ARM: tegra: Remove spurious comma from node name Date: Tue, 16 Jun 2020 15:51:57 +0200 Message-Id: <20200616135238.3001888-33-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding This was probably left there by mistake or perhaps was a typo in the first place. Remove it. Cc: Marcel Ziswiler Cc: Philippe Schenker Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index c209020e13fd..811c06599bfa 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -527,7 +527,7 @@ spi2-cs1-n-pw2 { }; /* Colibri USBH_OC */ - spi2-cs2-n-pw3, { + spi2-cs2-n-pw3 { nvidia,pins = "spi2_cs2_n_pw3"; nvidia,function = "spi2_alt"; nvidia,pull = ; From patchwork Tue Jun 16 13:51:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310385 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=Jv1sFJzp; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV6t4HgTz9sSS for ; Tue, 16 Jun 2020 23:54:14 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728861AbgFPNyN (ORCPT ); Tue, 16 Jun 2020 09:54:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57122 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728934AbgFPNyL (ORCPT ); Tue, 16 Jun 2020 09:54:11 -0400 Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5781DC06174E for ; Tue, 16 Jun 2020 06:54:10 -0700 (PDT) Received: by mail-wr1-x443.google.com with SMTP id q11so20891568wrp.3 for ; Tue, 16 Jun 2020 06:54:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pwE35G81wgEIvaTTAj8x7ONwFHGN+HySTYYEqF0s99Y=; b=Jv1sFJzp58JI28XF+/gu0gljB0qYxU/OqEcP3oSh5BKS1iaklTd4gA410IVLtHQ3f6 +H1LWqsCDVN0aSJJ02TumbWf7ZGMTeKvdoizX8Vyp+tyiOjlzYseMxJQPNO4wkMz0OPz EeLZj5zvZnnGjasW7eOPXmGAkr+0JfND+l5tgQRr/IlGrUB/X02T4hGbhCXADKxyHCjy +hkh6xUSCRV5LeyvgWIFGtjVc9YUp1w6nPcxH9gF5iaTZLFVWa5s2GCsO9ERlM/Cz5tT kaAXZuxWOYsJ9Eo+CCD7Xi5DKakAIT/zcNqIbbKYuJBgYiCCx0PPZ2uS0utLzHUcx7PF CcoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pwE35G81wgEIvaTTAj8x7ONwFHGN+HySTYYEqF0s99Y=; b=ihTjfjCPB+bJMEjIWbYdIsq22YKkXg8RZEcZN+c+qt+YM8HDSWSExtMGnO6EOvhKnH KWuLB8EH53ST66Z507+x4Dnpj1QaLvrpaHClePCXqok8oeLtx4WzCNBSuSo8a/y6LK53 8v+wJZQskFjHdGGZG6oKJmmbUGA53WHXEMupgut8597lq1THQemZvTvtoVSpZQTz6Lbr DYOligHqIFCwrRQnVt60Hgi+PDwrsUh5yJs8kbjh0pU9i/cY7AeRqVUTPbXfJNyudMhC eg7iGSC7sZhC6oQXnOq65mfV8Moj/AWljLQ1ru/i0ZfMpXE7vsuELYqjH8Q8YSe5H0/X 4rPA== X-Gm-Message-State: AOAM533SwjeYvbDLGeOH0BYIEys7GtjcYJ1GwNrfcHiEKIHaCuYoMlOI ttZxDpP/+U7fdz8w0KP1cYI= X-Google-Smtp-Source: ABdhPJw3w75sDLQDhSMDHVawPQsm/dWJbeacSJHf5qyvFJ1g0kkLRv427rHG4Bu1lBl4G8L3bUF52g== X-Received: by 2002:adf:82f4:: with SMTP id 107mr2387804wrc.163.1592315649142; Tue, 16 Jun 2020 06:54:09 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id z16sm29333427wrm.70.2020.06.16.06.54.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:54:08 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 33/73] ARM: tegra: The Tegra30 DC is not backwards-compatible Date: Tue, 16 Jun 2020 15:51:58 +0200 Message-Id: <20200616135238.3001888-34-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The display controller on Tegra30 is in fact not backwards-compatible with the instantiation found on earlier SoCs. Drop the misleading compatible string. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index d80f9d3d2d18..bedab43016c7 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -197,7 +197,7 @@ gr3d@54180000 { }; dc@54200000 { - compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc"; + compatible = "nvidia,tegra30-dc"; reg = <0x54200000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_DISP1>; From patchwork Tue Jun 16 13:51:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310386 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=jGexnNuz; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV6w3lfWz9sRK for ; Tue, 16 Jun 2020 23:54:16 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728908AbgFPNyP (ORCPT ); Tue, 16 Jun 2020 09:54:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57130 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728899AbgFPNyP (ORCPT ); Tue, 16 Jun 2020 09:54:15 -0400 Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8E25C061573 for ; Tue, 16 Jun 2020 06:54:13 -0700 (PDT) Received: by mail-wm1-x341.google.com with SMTP id l17so2987650wmj.0 for ; Tue, 16 Jun 2020 06:54:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iSV77y8AmWb+Wh1piRcAkQT0I7rk2MZqZTm5Fu4vFQA=; b=jGexnNuzhW3pKohokLWtgune9Doo8bb8gmGqdgTvbDkhDMwKYdhPz3/WCqj22H9MIO i0dXeEBirSfyKW80seDcyCd2Bst4RkZB1JtkhgLrpSvw6G9VFNqHH8SoQeJ5LuokoJ1p aNTuHV7IwXqDHLI3WWgIF+I63heoPGbFWZEiaI9iaG69Ob6v0s18rm/N6k+m9U2VpQQD UWaRUjYZBWHbxpdT+z3vfonrchDD0cVDN88fMw+tWwh+RIJnEHMBKXE7e4yIrL1p5hwp uafyjnRl2+LAzAngMLPw69/+EpTRfc+2/JHFUrP45Py2gyJaOI2Uz80mxWmTHYq8m+M7 FDtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iSV77y8AmWb+Wh1piRcAkQT0I7rk2MZqZTm5Fu4vFQA=; b=MCxDT6LwBQ8E9YFUUndLLrx8RfXxIMiTZutf0ijJsUBiU8lIE7AfnPMK7JKB0xjtZD PAPJJrjd6kwrFB6nxHOMnUfgHAargkNipknApnGxGLFkNUkhB/zLxQcfrNVnHytAQ9a3 PX8iwSRXzoVQJEHJ3VIVVrEDvk4C0t31Q8JQWRB27gIMF62kkiEgtW9+kbwUsn365gIJ TnUrM/eZz5thOriOF9Y38kAg7gjODJs9mPK3mOLsej90R0mVlRK09R1GTep6hTrvMcgW 33czPgKUOHCi9QrsNj590GJpLJapD9+cj6v3Ts2L8BvY1p9qkS9JqwaMvhafL36DKszE DeoA== X-Gm-Message-State: AOAM530aZaUYiER3BeylNKDTQudmtFYX1HXsv+5JaYnQTOnAJpmEJFhP 4tNAGVZWwcEotAsr6wpPN3Jjc0aD X-Google-Smtp-Source: ABdhPJwWvCiIh9OzTTLCPHqPjRDt8xPuHQuoHliL9OM1vk6X4Sdjm50lnyyfjGdrH6xZNulYKpnMbQ== X-Received: by 2002:a1c:60d6:: with SMTP id u205mr3548805wmb.163.1592315652471; Tue, 16 Jun 2020 06:54:12 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id o18sm4383482wme.19.2020.06.16.06.54.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:54:11 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 34/73] ARM: tegra: The Tegra30 SDHCI is not backwards-compatible Date: Tue, 16 Jun 2020 15:51:59 +0200 Message-Id: <20200616135238.3001888-35-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The SDHCI on Tegra30 is in fact not backwards-compatible with the instantiation found on earlier SoCs. Drop the misleading compatible string. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index bedab43016c7..3c7ee0b871c0 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -854,7 +854,7 @@ tegra_i2s4: i2s@70080700 { }; mmc@78000000 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + compatible = "nvidia,tegra30-sdhci"; reg = <0x78000000 0x200>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; @@ -865,7 +865,7 @@ mmc@78000000 { }; mmc@78000200 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + compatible = "nvidia,tegra30-sdhci"; reg = <0x78000200 0x200>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; @@ -876,7 +876,7 @@ mmc@78000200 { }; mmc@78000400 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + compatible = "nvidia,tegra30-sdhci"; reg = <0x78000400 0x200>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; @@ -887,7 +887,7 @@ mmc@78000400 { }; mmc@78000600 { - compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; + compatible = "nvidia,tegra30-sdhci"; reg = <0x78000600 0x200>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; From patchwork Tue Jun 16 13:52:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310387 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=jVIlO54+; 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Tue, 16 Jun 2020 06:54:14 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id z8sm28917970wru.33.2020.06.16.06.54.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:54:13 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 35/73] arm64: tegra: Add missing #phy-cells property on Jetson TX2 Date: Tue, 16 Jun 2020 15:52:00 +0200 Message-Id: <20200616135238.3001888-36-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding PHYs need to have a #phy-cells property that defines how many cells are required in their specifier. The standard Ethernet PHY doesn't require a specifier, so set its #phy-cells to 0. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index 2fcaa2e64370..de049d8d458a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -50,6 +50,8 @@ phy: phy@0 { interrupt-parent = <&gpio>; interrupts = ; + + #phy-cells = <0>; }; }; }; From patchwork Tue Jun 16 13:52:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310388 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=uSaIDrOE; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV73189Nz9sRK for ; Tue, 16 Jun 2020 23:54:23 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728885AbgFPNyV (ORCPT ); Tue, 16 Jun 2020 09:54:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728899AbgFPNyU (ORCPT ); Tue, 16 Jun 2020 09:54:20 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1356BC061573 for ; Tue, 16 Jun 2020 06:54:19 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id l10so20842336wrr.10 for ; Tue, 16 Jun 2020 06:54:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EfZn0e2yak8oW3bFOlBf3ybvTJUHnF3nqSzE+El5OpU=; b=uSaIDrOETWkxJkuo7Tq/oV3yWUlMo3tfHlWwcgh04nyYp1ICpyeh20VzvUyCUyqAaQ 3tDXfCPfqVDqEXGLxqraQx+cqjrnbjlljd5/H6mAeXP4Mn2p1gvmA4TcmXYrzictCbsv Nfj3hAFF9oOJaBXpbIYh2upGSXum0DsQdEWgRsHz0/QCbzxvDflW5/rvbEUHD0DP6Mo3 oQhpQ3yptMGg39FZqLOYuTqM15QHoFsi+GQEK9c/i/zub89Dws0uayuJterc2D6iB9WH OJXlSI6Fa81sxo7VO9Y4vQ/n31E4ebp2lbFBgG0Z4hcAVZudFBgDCgFhie2tJOqaLBor RwdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EfZn0e2yak8oW3bFOlBf3ybvTJUHnF3nqSzE+El5OpU=; b=g9CLHz+S8k1MzLMpDgk6bHGboo/Hi0HS/XGdYL7veOQy0rFkYmQmwjcg6WsKryvgvc SXth9XFv20LCqlwz+7zCmAI5U5dZEQ9wX/c5igdgYGgRSRKLoNajmA0lXTVibFaMJ8/2 QurP56rDFcZtZGS0vwgxdIFrPipURXBImtxny8GHmX3eTqRmV35aSr6RtBlwIv8ncxcQ OXciva/c1NhQq8vbtHbpqziIHrQwiyTrggD0ma8Fhvd1mqwd9ceIOGcbGb1L5m0hpERG Z6CGHDLmmnH3uAaPobBsj4XIflW7KrZr0ipzFHKEey7O3hLCdkgJhZJr3aOzZ08joH1C Hchw== X-Gm-Message-State: AOAM530HoCVNPe4Sep+bVCC8IZqiutgKvOHs7swdAK5BQeiuSAdcLUdb GVEIA6tMoXTrKmz9aSE1JXk= X-Google-Smtp-Source: ABdhPJwd7gT9/J7V9dYG9c35OqjoTaO9IQ+WwWcoJwQi8j0Jda4Xu0zzbH/M7ykH2cDgI+o11exrlA== X-Received: by 2002:a5d:604b:: with SMTP id j11mr3158732wrt.193.1592315657762; Tue, 16 Jun 2020 06:54:17 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id q13sm29731927wrn.84.2020.06.16.06.54.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:54:16 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 36/73] arm64: tegra: Add missing #phy-cells property on Jetson AGX Xavier Date: Tue, 16 Jun 2020 15:52:01 +0200 Message-Id: <20200616135238.3001888-37-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding PHYs need to have a #phy-cells property that defines how many cells are required in their specifier. The standard Ethernet PHY doesn't require a specifier, so set its #phy-cells to 0. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index b96eb4e14556..f3781e86f321 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -44,6 +44,7 @@ phy: phy@0 { reg = <0x0>; interrupt-parent = <&gpio>; interrupts = ; + #phy-cells = <0>; }; }; }; From patchwork Tue Jun 16 13:52:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310389 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=F15k2Y0d; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV7401S7z9sRN for ; Tue, 16 Jun 2020 23:54:23 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728803AbgFPNyX (ORCPT ); Tue, 16 Jun 2020 09:54:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728815AbgFPNyV (ORCPT ); Tue, 16 Jun 2020 09:54:21 -0400 Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 333D5C06174E for ; Tue, 16 Jun 2020 06:54:21 -0700 (PDT) Received: by mail-wr1-x444.google.com with SMTP id b6so1729719wrs.11 for ; Tue, 16 Jun 2020 06:54:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Q+qDaBmogzp3rENt1OG4yOphWjq8JVCDpGzP7ggeRUE=; b=F15k2Y0dRr1PfVU0cOR9rJidj02ntjM5osYJpN1Q7522vgCLGYIGRxfbeEwbV0q5GB cjPcGPv4miJk8NnsLhCCmG94vfL18zhaZhCjMCY/vLQsm3W420ihgVWEQilPZOibZ2gA cc/IHIl/t/DHIo0CEJ/9WZf53ogMVgrNsAez4qBfZpN8NuPvoK4p93V0pn5Ne4lIPCw9 9lXy6+p/EupWYWkm93HIWQaif+nb+zH5UeGrdVY7jTe7vKEl+O9iG+C5Ut2aAxYMY69R q3zKH0B3Vknk+jHT1QmNw4fLjtuYXgRy+tRES60GGshE0MAl296P5qamEdVe+8PZRzPm bQwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q+qDaBmogzp3rENt1OG4yOphWjq8JVCDpGzP7ggeRUE=; b=VGGWJ1K73YIXbIeOR7XZniJG5DaING+y3ED4GE0wJalasGKWclqAjgzVN14IBx7Uk2 iP2mi2pCOTuushnLq1zwKcMbHZcFANIQbURkFOmxGkQXCzNNgN6vMGSpZ25asDw0jOPk Bhp9IWrdQTrBbIqHhplIZVbsnzGfIIg2/8LdE9LahSBDVvASDgvOprBTbT5r942WX8sB TWeLFq0pJZv3brt9Ow9QIZ4WqgV3Cu9tLxGZ+lbrT8d8hUgVDnZfRNSgceMAgopIxGGF kI0HEVih7Z0psuzhcJyxzwy/NKKhsVotSXkZ4XvvxIyTqM1WKG3ll+fMiSnSRQYRxGEj 2l3g== X-Gm-Message-State: AOAM530HqZdm76qfbXued3phg1+gO9cU/s+L8awW0osxQsnU2uMWlX78 sxDMJ6HkjS/fF+xglqiUITvg10+P X-Google-Smtp-Source: ABdhPJw85hnj9ARPHTZVDw2ajb6UG35sRgBJqf2472xqfKzPrPrvL70ttg/oUH2a/S5dRw7iS/zsfw== X-Received: by 2002:adf:9b9e:: with SMTP id d30mr3280508wrc.345.1592315659931; Tue, 16 Jun 2020 06:54:19 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id b81sm4430697wmc.5.2020.06.16.06.54.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:54:18 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 37/73] arm64: tegra: Fix #address-cells/#size-cells for SRAM on Tegra186 Date: Tue, 16 Jun 2020 15:52:02 +0200 Message-Id: <20200616135238.3001888-38-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The standard mmio-sram bindings require the #address- and #size-cells properties to be 1. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 58100fb9cd8b..373f575b8678 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1216,20 +1216,20 @@ gpu@17000000 { sysram@30000000 { compatible = "nvidia,tegra186-sysram", "mmio-sram"; reg = <0x0 0x30000000 0x0 0x50000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x30000000 0x50000>; cpu_bpmp_tx: shmem@4e000 { compatible = "nvidia,tegra186-bpmp-shmem"; - reg = <0x0 0x4e000 0x0 0x1000>; + reg = <0x4e000 0x1000>; label = "cpu-bpmp-tx"; pool; }; cpu_bpmp_rx: shmem@4f000 { compatible = "nvidia,tegra186-bpmp-shmem"; - reg = <0x0 0x4f000 0x0 0x1000>; + reg = <0x4f000 0x1000>; label = "cpu-bpmp-rx"; pool; }; From patchwork Tue Jun 16 13:52:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310390 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=jcdi4uwK; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV745gkDz9sRK for ; Tue, 16 Jun 2020 23:54:24 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728553AbgFPNyY (ORCPT ); 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Tue, 16 Jun 2020 06:54:21 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 38/73] arm64: tegra: Use standard notation for interrupts Date: Tue, 16 Jun 2020 15:52:03 +0200 Message-Id: <20200616135238.3001888-39-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding It is customary to use angle brackets around each tuple in the interrupts property. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 373f575b8678..50b56168fc97 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1199,8 +1199,8 @@ gpu@17000000 { compatible = "nvidia,gp10b"; reg = <0x0 0x17000000 0x0 0x1000000>, <0x0 0x18000000 0x0 0x1000000>; - interrupts = ; + interrupts = , + ; interrupt-names = "stall", "nonstall"; clocks = <&bpmp TEGRA186_CLK_GPCCLK>, From patchwork Tue Jun 16 13:52:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310391 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=o/hi0mnh; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV770kkfz9sRK for ; Tue, 16 Jun 2020 23:54:27 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728899AbgFPNy0 (ORCPT ); Tue, 16 Jun 2020 09:54:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57170 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728815AbgFPNy0 (ORCPT ); Tue, 16 Jun 2020 09:54:26 -0400 Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93111C061573 for ; Tue, 16 Jun 2020 06:54:25 -0700 (PDT) Received: by mail-wm1-x343.google.com with SMTP id r9so2974333wmh.2 for ; Tue, 16 Jun 2020 06:54:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kThqcb4cQbBx/uIsel8TVm5M32tgO5gv/gDCIhxkJJA=; b=o/hi0mnh2wpMjd4mgh7FpL98ASw5tSNjvcUQsMZmDL7CaRzCWFSeuAtCWoaRhUUZXn hS5gS/LCLSrTDWGHwZcaT/lr1RQ3IHm8vpgwcQLD5N99QRwLS7eAWrBI0m7zdsZRwRxu /dk6beZXp7QzUWAW94rcDpjx4WtdNIIbPZnYhkbNPyehGuq9Tp2FEHl1x/2ragpYV3ST grA85cCHOXQI/nyfs0m6Z8L/3V9r+yz5RA+vU/DbD8+obw/Z2gIfCBalD5VmQ79OTstK k2vn2+Tom6TvlQk0EVBdlJoZOJyznexZ4YUTO3Jm8QlYN1+gi5T3wYtZy0IeO7LD0B45 MLuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kThqcb4cQbBx/uIsel8TVm5M32tgO5gv/gDCIhxkJJA=; b=AYgh2WdZlKjjAd5rZxSB/8+T0bRe8KYP1ibTim8+Q2AN3++VpKZQafM0YgpBer/fNM 3hqHwFx9sxF8ryE7A+4JRS5MnMc4nJbtpoYU65grf3/sztbdwQx4fgSNuDTkCKNhsJRO LC6hUYyiiGLjlUC6eOSymNpMjzgRjvy3CK1LADjRXVEDrKGY18mWtJ7B5RoiqtJlgx8d 9bI3RvcsplQgRi2kNueoelAhPTpdXH1FMvyunv5q0NFGCbDIlEcu31RThS4aVhN4sB0e lFd1W+t0ZCu2tLACAZFX0pdwQe8ZjiwOGY/WioU/LouH3ompRq0FqjQQPlzr9wIJnEa1 5R6w== X-Gm-Message-State: AOAM532Kx4PEoobgNvxQNqMhW4wcSIbH7Co4BwdSCWnCx+MU5+Yope8p o4bjV5ioU8SXBDtSWMbo4HtfSG1e X-Google-Smtp-Source: ABdhPJwJwKgoBKOrgh9ybWXJW1wfiTzi0G/DnJugS41di6b6KeHJcMacLd5pTXFBo1vjSqxmGbaNEQ== X-Received: by 2002:a1c:154:: with SMTP id 81mr3295877wmb.23.1592315664359; Tue, 16 Jun 2020 06:54:24 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id a124sm4156094wmh.4.2020.06.16.06.54.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:54:23 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 39/73] arm64: tegra: Remove extra compatible for Tegra194 SDHCI Date: Tue, 16 Jun 2020 15:52:04 +0200 Message-Id: <20200616135238.3001888-40-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The SDHCI on Tegra194 is in fact not compatible with the one found on Tegra186. Remove the extra compatible string to reflect that. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 4bc187a4eacd..ae438b2c4dd9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -450,7 +450,7 @@ pwm8: pwm@32f0000 { }; sdmmc1: sdhci@3400000 { - compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; + compatible = "nvidia,tegra194-sdhci"; reg = <0x03400000 0x10000>; interrupts = ; clocks = <&bpmp TEGRA194_CLK_SDMMC1>; @@ -472,7 +472,7 @@ sdmmc1: sdhci@3400000 { }; sdmmc3: sdhci@3440000 { - compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; + compatible = "nvidia,tegra194-sdhci"; reg = <0x03440000 0x10000>; interrupts = ; clocks = <&bpmp TEGRA194_CLK_SDMMC3>; @@ -495,7 +495,7 @@ sdmmc3: sdhci@3440000 { }; sdmmc4: sdhci@3460000 { - compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; + compatible = "nvidia,tegra194-sdhci"; reg = <0x03460000 0x10000>; interrupts = ; clocks = <&bpmp TEGRA194_CLK_SDMMC4>; From patchwork Tue Jun 16 13:52:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310392 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=O9LtF6Hd; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV7C5WhQz9sRK for ; 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Tue, 16 Jun 2020 06:54:25 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 40/73] arm64: tegra: Remove extra compatible for Tegra210 SDHCI Date: Tue, 16 Jun 2020 15:52:05 +0200 Message-Id: <20200616135238.3001888-41-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The SDHCI on Tegra210 is in fact not compatible with the one found on Tegra124. Remove the extra compatible string to reflect that. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 08655081f72d..cbf0d30a2f8b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1177,7 +1177,7 @@ usb3-3 { }; sdhci@700b0000 { - compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; + compatible = "nvidia,tegra210-sdhci"; reg = <0x0 0x700b0000 0x0 0x200>; interrupts = ; clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; @@ -1205,7 +1205,7 @@ sdhci@700b0000 { }; sdhci@700b0200 { - compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; + compatible = "nvidia,tegra210-sdhci"; reg = <0x0 0x700b0200 0x0 0x200>; interrupts = ; clocks = <&tegra_car TEGRA210_CLK_SDMMC2>; @@ -1222,7 +1222,7 @@ sdhci@700b0200 { }; sdhci@700b0400 { - compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; + compatible = "nvidia,tegra210-sdhci"; reg = <0x0 0x700b0400 0x0 0x200>; interrupts = ; clocks = <&tegra_car TEGRA210_CLK_SDMMC3>; @@ -1245,7 +1245,7 @@ sdhci@700b0400 { }; sdhci@700b0600 { - compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci"; + compatible = "nvidia,tegra210-sdhci"; reg = <0x0 0x700b0600 0x0 0x200>; interrupts = ; clocks = <&tegra_car TEGRA210_CLK_SDMMC4>; From patchwork Tue Jun 16 13:52:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310393 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; 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Tue, 16 Jun 2020 06:54:28 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id d5sm31607980wrb.14.2020.06.16.06.54.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:54:27 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 41/73] arm64: tegra: Describe interconnect paths on Tegra186 Date: Tue, 16 Jun 2020 15:52:06 +0200 Message-Id: <20200616135238.3001888-42-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The interface used by clients of the memory controller can be configured in a number of different ways. Describe this path using the interconnect bindings to enable the configuration of these parameters. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 54 ++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 50b56168fc97..decf8de3bbe5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -60,6 +60,9 @@ ethernet@2490000 { clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; resets = <&bpmp TEGRA186_RESET_EQOS>; reset-names = "eqos"; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; + interconnect-names = "dma-mem", "write"; iommus = <&smmu TEGRA186_SID_EQOS>; status = "disabled"; @@ -145,6 +148,7 @@ memory-controller@2c00000 { interrupts = ; status = "disabled"; + #interconnect-cells = <1>; #address-cells = <2>; #size-cells = <2>; @@ -163,6 +167,8 @@ emc: external-memory-controller@2c60000 { clocks = <&bpmp TEGRA186_CLK_EMC>; clock-names = "emc"; + #interconnect-cells = <0>; + nvidia,bpmp = <&bpmp>; }; }; @@ -335,6 +341,9 @@ sdmmc1: sdhci@3400000 { clock-names = "sdhci"; resets = <&bpmp TEGRA186_RESET_SDMMC1>; reset-names = "sdhci"; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, + <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; + interconnect-names = "dma-mem", "write"; iommus = <&smmu TEGRA186_SID_SDMMC1>; pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; pinctrl-0 = <&sdmmc1_3v3>; @@ -361,6 +370,9 @@ sdmmc2: sdhci@3420000 { clock-names = "sdhci"; resets = <&bpmp TEGRA186_RESET_SDMMC2>; reset-names = "sdhci"; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, + <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; + interconnect-names = "dma-mem", "write"; iommus = <&smmu TEGRA186_SID_SDMMC2>; pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; pinctrl-0 = <&sdmmc2_3v3>; @@ -382,6 +394,9 @@ sdmmc3: sdhci@3440000 { clock-names = "sdhci"; resets = <&bpmp TEGRA186_RESET_SDMMC3>; reset-names = "sdhci"; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; + interconnect-names = "dma-mem", "write"; iommus = <&smmu TEGRA186_SID_SDMMC3>; pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; pinctrl-0 = <&sdmmc3_3v3>; @@ -408,6 +423,9 @@ sdmmc4: sdhci@3460000 { assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; resets = <&bpmp TEGRA186_RESET_SDMMC4>; reset-names = "sdhci"; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, + <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; + interconnect-names = "dma-mem", "write"; iommus = <&smmu TEGRA186_SID_SDMMC4>; nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; @@ -436,6 +454,9 @@ hda@3510000 { <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; reset-names = "hda", "hda2hdmi", "hda2codec_2x"; power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; + interconnect-names = "dma-mem", "write"; iommus = <&smmu TEGRA186_SID_HDA>; status = "disabled"; }; @@ -564,6 +585,9 @@ usb@3530000 { power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; power-domain-names = "xusb_host", "xusb_ss"; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; + interconnect-names = "dma-mem", "write"; iommus = <&smmu TEGRA186_SID_XUSB_HOST>; #address-cells = <1>; #size-cells = <0>; @@ -786,6 +810,10 @@ pcie@10003000 { <&bpmp TEGRA186_RESET_PCIEXCLK>; reset-names = "afi", "pex", "pcie_x"; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_AFI>; iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; iommu-map-mask = <0x0>; @@ -921,6 +949,10 @@ host1x@13e00000 { #size-cells = <1>; ranges = <0x15000000 0x0 0x15000000 0x01000000>; + + interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; + interconnect-names = "dma-mem"; + iommus = <&smmu TEGRA186_SID_HOST1X>; dpaux1: dpaux@15040000 { @@ -992,6 +1024,9 @@ display@15200000 { reset-names = "dc"; power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; + interconnect-names = "dma-mem", "read-1"; iommus = <&smmu TEGRA186_SID_NVDISPLAY>; nvidia,outputs = <&dsia &dsib &sor0 &sor1>; @@ -1008,6 +1043,9 @@ display@15210000 { reset-names = "dc"; power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; + interconnect-names = "dma-mem", "read-1"; iommus = <&smmu TEGRA186_SID_NVDISPLAY>; nvidia,outputs = <&dsia &dsib &sor0 &sor1>; @@ -1024,6 +1062,9 @@ display@15220000 { reset-names = "dc"; power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; + interconnect-names = "dma-mem", "read-1"; iommus = <&smmu TEGRA186_SID_NVDISPLAY>; nvidia,outputs = <&sor0 &sor1>; @@ -1056,6 +1097,9 @@ vic@15340000 { reset-names = "vic"; power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, + <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; + interconnect-names = "dma-mem", "write"; iommus = <&smmu TEGRA186_SID_VIC>; }; @@ -1211,6 +1255,11 @@ gpu@17000000 { status = "disabled"; power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, + <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, + <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; + interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; }; sysram@30000000 { @@ -1237,6 +1286,11 @@ cpu_bpmp_rx: shmem@4f000 { bpmp: bpmp { compatible = "nvidia,tegra186-bpmp"; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; + interconnect-names = "read", "write", "dma-mem", "dma-write"; iommus = <&smmu TEGRA186_SID_BPMP>; mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; From patchwork Tue Jun 16 13:52:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310394 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=liOO0ZpV; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV7G6yfhz9sRK for ; Tue, 16 Jun 2020 23:54:34 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728931AbgFPNye (ORCPT ); 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Tue, 16 Jun 2020 06:54:29 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 42/73] arm64: tegra: Describe interconnect paths on Tegra194 Date: Tue, 16 Jun 2020 15:52:07 +0200 Message-Id: <20200616135238.3001888-43-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding On Tegra194, all clients of the memory subsystem can generally address 40 bits of system memory. However, bit 39 has special meaning and will cause the memory controller to reorder sectors for block-linear buffer formats. This is primarily useful for graphics-related devices. Use of bit 39 must be controlled on a case-by-case basis. Buffers that are used with bit 39 set by one device may be used with bit 39 cleared by other devices. Care must be taken to allocate buffers at addresses that do not require bit 39 to be set. This is normally not an issue for system memory since there are no Tegra-based systems with enough RAM to exhaust the 39-bit physical address space. However, when a device is behind an IOMMU, such as the ARM SMMU on Tegra194, the IOMMUs input address space can cause IOVA allocations to happen in this region. This is for example the case when an operating system implements a top-down allocation policy for IO virtual addresses. To account for this, describe the path that memory accesses take through the system. Memory clients will send requests to the memory controller, which forwards bits [38:0] of the address either to the external memory controller or the SMMU, depending on the stream ID of the access. A good way to describe this is using the interconnects bindings, see: Documentation/devicetree/bindings/interconnect/interconnect.txt The standard "dma-mem" path is used to describe the path towards system memory via the memory controller. A dma-ranges property in the memory controller's device tree node limits the range of DMA addresses that the memory clients can use to bits [38:0], ensuring that bit 39 is not used. Signed-off-by: Thierry Reding --- Changes in v4: - add additional entries for interconnect-names to match interconnects - add EMC as destination for interconnect paths Changes in v3: - add missing interconnect properties for VIC Changes in v2: - use memory client IDs instead of stream IDs (Mikko Perttunen) Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 70 ++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index ae438b2c4dd9..a50504a317d7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -59,6 +59,9 @@ ethernet@2490000 { clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; resets = <&bpmp TEGRA194_RESET_EQOS>; reset-names = "eqos"; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, + <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; + interconnect-names = "dma-mem", "write"; status = "disabled"; snps,write-requests = <1>; @@ -176,6 +179,7 @@ mc: memory-controller@2c00000 { reg = <0x02c00000 0x100000>, <0x02b80000 0x040000>, <0x01700000 0x100000>; + #interconnect-cells = <1>; status = "disabled"; #address-cells = <2>; @@ -209,6 +213,8 @@ emc: external-memory-controller@2c60000 { clocks = <&bpmp TEGRA194_CLK_EMC>; clock-names = "emc"; + #interconnect-cells = <0>; + nvidia,bpmp = <&bpmp>; }; }; @@ -457,6 +463,9 @@ sdmmc1: sdhci@3400000 { clock-names = "sdhci"; resets = <&bpmp TEGRA194_RESET_SDMMC1>; reset-names = "sdhci"; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, + <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; + interconnect-names = "dma-mem", "write"; nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; nvidia,pad-autocal-pull-down-offset-3v3-timeout = @@ -479,6 +488,9 @@ sdmmc3: sdhci@3440000 { clock-names = "sdhci"; resets = <&bpmp TEGRA194_RESET_SDMMC3>; reset-names = "sdhci"; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, + <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; + interconnect-names = "dma-mem", "write"; nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; @@ -506,6 +518,9 @@ sdmmc4: sdhci@3460000 { <&bpmp TEGRA194_CLK_PLLC4>; resets = <&bpmp TEGRA194_RESET_SDMMC4>; reset-names = "sdhci"; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, + <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; + interconnect-names = "dma-mem", "write"; nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; @@ -534,6 +549,9 @@ hda@3510000 { <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; reset-names = "hda", "hda2codec_2x", "hda2hdmi"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, + <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; + interconnect-names = "dma-mem", "write"; status = "disabled"; }; @@ -1032,6 +1050,8 @@ host1x@13e00000 { #size-cells = <1>; ranges = <0x15000000 0x15000000 0x01000000>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; + interconnect-names = "dma-mem"; display-hub@15200000 { compatible = "nvidia,tegra194-display", "simple-bus"; @@ -1067,6 +1087,9 @@ display@15200000 { reset-names = "dc"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; + interconnect-names = "dma-mem", "read-1"; nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; nvidia,head = <0>; @@ -1082,6 +1105,9 @@ display@15210000 { reset-names = "dc"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; + interconnect-names = "dma-mem", "read-1"; nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; nvidia,head = <1>; @@ -1097,6 +1123,9 @@ display@15220000 { reset-names = "dc"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; + interconnect-names = "dma-mem", "read-1"; nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; nvidia,head = <2>; @@ -1112,6 +1141,9 @@ display@15230000 { reset-names = "dc"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; + interconnect-names = "dma-mem", "read-1"; nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; nvidia,head = <3>; @@ -1128,6 +1160,9 @@ vic@15340000 { reset-names = "vic"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, + <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; + interconnect-names = "dma-mem", "write"; }; dpaux0: dpaux@155c0000 { @@ -1404,9 +1439,14 @@ pcie@14100000 { nvidia,aspm-l0s-entrance-latency-us = <3>; bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc3000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ + + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; + interconnect-names = "read", "write"; }; pcie@14120000 { @@ -1449,9 +1489,14 @@ pcie@14120000 { nvidia,aspm-l0s-entrance-latency-us = <3>; bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc3000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ + + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; + interconnect-names = "read", "write"; }; pcie@14140000 { @@ -1494,9 +1539,14 @@ pcie@14140000 { nvidia,aspm-l0s-entrance-latency-us = <3>; bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc3000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ + + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; + interconnect-names = "read", "write"; }; pcie@14160000 { @@ -1539,9 +1589,14 @@ pcie@14160000 { nvidia,aspm-l0s-entrance-latency-us = <3>; bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc3000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ + + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; + interconnect-names = "read", "write"; }; pcie@14180000 { @@ -1584,9 +1639,14 @@ pcie@14180000 { nvidia,aspm-l0s-entrance-latency-us = <3>; bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc3000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ + + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; + interconnect-names = "read", "write"; }; pcie@141a0000 { @@ -1633,9 +1693,14 @@ pcie@141a0000 { nvidia,aspm-l0s-entrance-latency-us = <3>; bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc3000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ + + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; + interconnect-names = "read", "write"; }; pcie_ep@14160000 { @@ -1767,6 +1832,11 @@ bpmp: bpmp { #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, + <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, + <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, + <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; + interconnect-names = "read", "write", "dma-mem", "dma-write"; bpmp_i2c: i2c { compatible = "nvidia,tegra186-bpmp-i2c"; From patchwork Tue Jun 16 13:52:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310395 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=TYuAs+ic; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV7N179zz9sRK for ; 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Tue, 16 Jun 2020 06:54:31 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 43/73] arm64: tegra: Add interrupt for Tegra194 memory controller Date: Tue, 16 Jun 2020 15:52:08 +0200 Message-Id: <20200616135238.3001888-44-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding This interrupt can be used for the operating system to be interrupted when certain events occur. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index a50504a317d7..73aba724bf67 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -179,6 +179,7 @@ mc: memory-controller@2c00000 { reg = <0x02c00000 0x100000>, <0x02b80000 0x040000>, <0x01700000 0x100000>; + interrupts = ; #interconnect-cells = <1>; status = "disabled"; From patchwork Tue Jun 16 13:52:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310396 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=rDV9T/RK; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV7P4ZmPz9sSS for ; Tue, 16 Jun 2020 23:54:41 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728815AbgFPNyk (ORCPT ); Tue, 16 Jun 2020 09:54:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728803AbgFPNyh (ORCPT ); Tue, 16 Jun 2020 09:54:37 -0400 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B27AC061573 for ; Tue, 16 Jun 2020 06:54:36 -0700 (PDT) Received: by mail-wr1-x442.google.com with SMTP id x13so20859509wrv.4 for ; Tue, 16 Jun 2020 06:54:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iUGGlLHCO3otOOHojhNK90R/D2K76Rxe4RnhKkj0ZJg=; b=rDV9T/RKG7tgVMzzHfcKh97OGuTfVQ3tZyHdNIw+5vil2PbabFkD8k3EHRhMNbvmA0 xaigYCxvns3oS/CkHQtJaTgk8dwVg0iz6vNvbjhpq3O+aZ9zAYeC85Kxvun3yinWvL2w PKttA7A/fNKVMAtatmAGRioxm3+w6Wq20kswTDSOu7cyQ2/aY+P9G9BIGsZRbdJfDORG B0LYAuJKzW2eu9Iid9BRBAjAI3KcCuAxNJ2lkKgY2jyerF0OmljdxJNtwcaPOviCmWWi H8/ssoCO91nVDtYu43e4MXx5lmpi4IbDz7JxHIqKFDv2RZhRKTnqKSiAL/Ag8LtlBRlD O1mA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iUGGlLHCO3otOOHojhNK90R/D2K76Rxe4RnhKkj0ZJg=; b=oqsLjOv9gBwF5tZ8h2GTByPsOzw/+i4MgfP856IXXvuVhsgd++VsLxC9DK6cpYFLLj gwfdbZLXvMzjbAHxn+R4xeh3G5lqI6jTIoRh28a3wYhNImQrc+pjRvgQiHwge1keynOD RzetRM5yF6giKrnuhAkH1YCkMuBpCZJH1h/Xt41SjN7Vo7V+UFTmtTcdcx1zacWI1AUR cdhgZf2AIsFaR/t5+4FzC6sPjppMZ7vMtUImNySSWJzXUrNoK/Pb7FTrTN7tT5QbqeMH w2ptIkQPkY5qPKhRXSQblOEKZQsLHxCHnaDJHorxNdvqeW7xrRBTN4XZ/KKd7qeFmgKY ujNA== X-Gm-Message-State: AOAM531oq+PT7xd/QclONEtfikpBwVD+3R7UnatIis1yc3yuG+VyoK3Y 5SLTjh4QyMSGUdGbCId+ITY= X-Google-Smtp-Source: ABdhPJwlysuFl1HhqVqR03E8fIV3rAPMC/xCd2un4eBrG2FUrg8nysVfgPA9K/BElWQqyJRwlKhXeA== X-Received: by 2002:a5d:6b86:: with SMTP id n6mr3127178wrx.167.1592315675040; Tue, 16 Jun 2020 06:54:35 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id x13sm1712793wre.83.2020.06.16.06.54.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:54:34 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 44/73] arm64: tegra: Add Tegra132 compatible string for host1x Date: Tue, 16 Jun 2020 15:52:09 +0200 Message-Id: <20200616135238.3001888-45-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding While the host1x controller found on Tegra132 is the same as on Tegra124 it is good practice to also list a SoC-specific compatible string so any SoC-specific quirks can be implemented in drivers if necessary. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 11a1bb428595..6ebfe503489f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -83,7 +83,9 @@ pci@2,0 { }; host1x@50000000 { - compatible = "nvidia,tegra124-host1x", "simple-bus"; + compatible = "nvidia,tegra132-host1x", + "nvidia,tegra124-host1x", + "simple-bus"; reg = <0x0 0x50000000 0x0 0x00034000>; interrupts = , /* syncpt */ ; /* general */ From patchwork Tue Jun 16 13:52:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310397 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=KO1jqiv6; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV7Q4t5tz9sRK for ; Tue, 16 Jun 2020 23:54:42 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728803AbgFPNym (ORCPT ); Tue, 16 Jun 2020 09:54:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57218 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728553AbgFPNyl (ORCPT ); Tue, 16 Jun 2020 09:54:41 -0400 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64E5CC06174E for ; Tue, 16 Jun 2020 06:54:39 -0700 (PDT) Received: by mail-wm1-x344.google.com with SMTP id f185so3165032wmf.3 for ; Tue, 16 Jun 2020 06:54:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ovQJ+nxLPgIkYbuQt2SCQKzxVuaVAKxPiX+Ud+yngTY=; b=KO1jqiv6JeFiRDgWo9+UDUMuiQ1ij+1+FXo0eIpu4YmpwS9Opv1/Ba/x8EoN4tnhH6 tAz6JbF/AypHdOlPnYVU6xhd0p8h4uFq3ZLwo2v4k7Vt+0cwV06/T28aOqhqnX6/Vm6O vK2hrCJqjZSdxPEQLAzhaUaQfjPUhrUzRl8Sm7lE8xnlIHeigwUrKL9iQWGZ0S+/EqBM kfvsA377kicEBaIfLjWyAsptopGNUCbRHvBPyNn1ih8Ax7JmAGtr9HyXeBIc5XvWSezA OQd6H3A4Pz1I1nxrjQLVNL+xTB+Y/cDsppn6cs4EyPR3+hc3i7FO9OC0/8tTomi2jlbO wkmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ovQJ+nxLPgIkYbuQt2SCQKzxVuaVAKxPiX+Ud+yngTY=; b=mT3h5R1apy3xpDjL/SNMVThRFkvvgHbI/Vij3saICiM+G3bssoNS8JXcsWxSI6TF2Q 6EUr2d+hKN4KZn6gdc+xgJepCoL9t+C+4/RZl0MOAswV9GDbqVm6+Bzq4z8llftUE4TQ MFMySFGQK9mKmDATKIOUMcRDv7m4gIci6rmg7JQJx0iFu3t37oe714MRN+fd+Ya+t122 kqn+XxQPO2+93bsY/SjCEPtmCHsKwGOn4iHFsH0vn1WR7oYDHRXsFYduEjIRXtu928e5 qCrF+ConsDXa0QezbqGYGjz6hePXtLccHGA48DwlQLKHvldmyMgWP1P7iojEvQatBkup ZMCQ== X-Gm-Message-State: AOAM531Ly9vfaqZ6kqh1RgQ0zXTefC6txpel5v4XuHUM6GtHx772SHXN H0YmeItIxxU/VxmjW6ZA/71gmv6l X-Google-Smtp-Source: ABdhPJw73cbPplV8KFd2PJxjrIwAqhVcwVIxNEO/gK1/CetMp7W8w3S2dltFFYXMsAz0u9PiABkTAw== X-Received: by 2002:a1c:7215:: with SMTP id n21mr3337969wmc.10.1592315678136; Tue, 16 Jun 2020 06:54:38 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id f9sm28542733wre.65.2020.06.16.06.54.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:54:36 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 45/73] arm64: tegra: Add interrupt-names for host1x Date: Tue, 16 Jun 2020 15:52:10 +0200 Message-Id: <20200616135238.3001888-46-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Interrupt names are used to distinguish between the syncpoint and general host1x interrupts. Make sure they are available in the DT so that drivers can use them if necessary. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 1 + arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + arch/arm64/boot/dts/nvidia/tegra194.dtsi | 1 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 6ebfe503489f..76e1a6451e83 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -89,6 +89,7 @@ host1x@50000000 { reg = <0x0 0x50000000 0x0 0x00034000>; interrupts = , /* syncpt */ ; /* general */ + interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA124_CLK_HOST1X>; clock-names = "host1x"; resets = <&tegra_car 28>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index decf8de3bbe5..e86b682f8645 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -940,6 +940,7 @@ host1x@13e00000 { reg-names = "hypervisor", "vm"; interrupts = , ; + interrupt-names = "syncpt", "host1x"; clocks = <&bpmp TEGRA186_CLK_HOST1X>; clock-names = "host1x"; resets = <&bpmp TEGRA186_RESET_HOST1X>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 73aba724bf67..f056158a2634 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1042,6 +1042,7 @@ host1x@13e00000 { reg-names = "hypervisor", "vm"; interrupts = , ; + interrupt-names = "syncpt", "host1x"; clocks = <&bpmp TEGRA194_CLK_HOST1X>; clock-names = "host1x"; resets = <&bpmp TEGRA194_RESET_HOST1X>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index cbf0d30a2f8b..0586722df64b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -90,6 +90,7 @@ host1x@50000000 { reg = <0x0 0x50000000 0x0 0x00034000>; interrupts = , /* syncpt */ ; /* general */ + interrupt-names = "syncpt", "host1x"; clocks = <&tegra_car TEGRA210_CLK_HOST1X>; clock-names = "host1x"; resets = <&tegra_car 28>; From patchwork Tue Jun 16 13:52:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310398 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=ix86ceYk; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV7S1LS6z9sRK for ; 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Tue, 16 Jun 2020 06:54:39 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 46/73] arm64: tegra: Remove parent clock from display controllers Date: Tue, 16 Jun 2020 15:52:11 +0200 Message-Id: <20200616135238.3001888-47-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The display controller's parent clock depends on the output that's consuming data from the display controller, so it needs to be specified as the parent of the corresponding output. The device tree bindings do specify this, so just correct the existing device trees that get this wrong. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 10 ++++------ arch/arm64/boot/dts/nvidia/tegra210.dtsi | 10 ++++------ 2 files changed, 8 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 76e1a6451e83..4fc34c5ec2dc 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -104,9 +104,8 @@ dc@54200000 { compatible = "nvidia,tegra124-dc"; reg = <0x0 0x54200000 0x0 0x00040000>; interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DISP1>, - <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "dc", "parent"; + clocks = <&tegra_car TEGRA124_CLK_DISP1>; + clock-names = "dc"; resets = <&tegra_car 27>; reset-names = "dc"; @@ -119,9 +118,8 @@ dc@54240000 { compatible = "nvidia,tegra124-dc"; reg = <0x0 0x54240000 0x0 0x00040000>; interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DISP2>, - <&tegra_car TEGRA124_CLK_PLL_P>; - clock-names = "dc", "parent"; + clocks = <&tegra_car TEGRA124_CLK_DISP2>; + clock-names = "dc"; resets = <&tegra_car 26>; reset-names = "dc"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 0586722df64b..41ffa0531cd8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -187,9 +187,8 @@ dc@54200000 { compatible = "nvidia,tegra210-dc"; reg = <0x0 0x54200000 0x0 0x00040000>; interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_DISP1>, - <&tegra_car TEGRA210_CLK_PLL_P>; - clock-names = "dc", "parent"; + clocks = <&tegra_car TEGRA210_CLK_DISP1>; + clock-names = "dc"; resets = <&tegra_car 27>; reset-names = "dc"; @@ -202,9 +201,8 @@ dc@54240000 { compatible = "nvidia,tegra210-dc"; reg = <0x0 0x54240000 0x0 0x00040000>; interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_DISP2>, - <&tegra_car TEGRA210_CLK_PLL_P>; - clock-names = "dc", "parent"; + clocks = <&tegra_car TEGRA210_CLK_DISP2>; + clock-names = "dc"; resets = <&tegra_car 26>; reset-names = "dc"; From patchwork Tue Jun 16 13:52:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310400 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=bXdMiZu0; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV7j6ghqz9sRK for ; Tue, 16 Jun 2020 23:54:57 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728803AbgFPNyz (ORCPT ); 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Tue, 16 Jun 2020 06:54:41 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 47/73] arm64: tegra: Fixup I/O and PLL supply names for HDMI/DP Date: Tue, 16 Jun 2020 15:52:12 +0200 Message-Id: <20200616135238.3001888-48-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The I/O and PLL supplies used for HDMI/DP have alternative names. Use the names that are given in the hardware documentation for consistency. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 4 ++-- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 4 ++-- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 4 ++-- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 1af7f9ffb7b6..f35b0ba29cb5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -286,8 +286,8 @@ sor@15540000 { sor@15580000 { status = "okay"; - avdd-io-supply = <&vdd_hdmi_1v05>; - vdd-pll-supply = <&vdd_1v8_ap>; + avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>; + vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>; hdmi-supply = <&vdd_hdmi>; nvidia,ddc-i2c-bus = <&ddc>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index e15d1eac05f5..9a7d136b467f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -145,8 +145,8 @@ sor@15b40000 { sor@15b80000 { status = "okay"; - avdd-io-supply = <&vdd_1v0>; - vdd-pll-supply = <&vdd_1v8hs>; + avdd-io-hdmi-dp-supply = <&vdd_1v0>; + vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>; hdmi-supply = <&vdd_hdmi>; nvidia,ddc-i2c-bus = <&ddc>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 5c3771e8d683..f72afdf547ee 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -27,8 +27,8 @@ csi@838 { sor@54580000 { status = "okay"; - avdd-io-supply = <&avdd_1v05>; - vdd-pll-supply = <&vdd_1v8>; + avdd-io-hdmi-dp-supply = <&avdd_1v05>; + vdd-hdmi-dp-pll-supply = <&vdd_1v8>; hdmi-supply = <&vdd_hdmi>; nvidia,ddc-i2c-bus = <&hdmi_ddc>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index ced01d15e457..e7ebf1afeb7a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -74,8 +74,8 @@ sor@54540000 { sor@54580000 { status = "okay"; - avdd-io-supply = <&avdd_1v05>; - vdd-pll-supply = <&vdd_1v8>; + avdd-io-hdmi-dp-supply = <&avdd_1v05>; + vdd-hdmi-dp-pll-supply = <&vdd_1v8>; hdmi-supply = <&vdd_hdmi>; nvidia,ddc-i2c-bus = <&hdmi_ddc>; From patchwork Tue Jun 16 13:52:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310399 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=kiWhB3Q4; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV7d3kw3z9sSS for ; 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Tue, 16 Jun 2020 06:54:43 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 48/73] arm64: tegra: Add unit-address to memory node Date: Tue, 16 Jun 2020 15:52:13 +0200 Message-Id: <20200616135238.3001888-49-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The memory node requires a unit-address. For some boards the bootloader, which is usually locked down, uses a hard-coded name for the memory node without a unit-address, so we can't fix it on those boards. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index 9f3206c63900..d0d03cc30197 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -18,7 +18,7 @@ chosen { stdout-path = "serial0:115200n8"; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x80000000>; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index de049d8d458a..7b5b9bb332cf 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -27,7 +27,7 @@ chosen { stdout-path = "serial0:115200n8"; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x2 0x00000000>; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index cc6ed45a2b48..751775357d51 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -17,7 +17,7 @@ chosen { stdout-path = "serial0:115200n8"; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x1 0x0>; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi index d0dc03923723..9ace2d9ea085 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi @@ -14,7 +14,7 @@ chosen { stdout-path = "serial0:115200n8"; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0xc0000000>; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index 88a4b9333d84..615a8f5a6cf2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -16,7 +16,7 @@ chosen { stdout-path = "serial0:115200n8"; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0xc0000000>; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index e7ebf1afeb7a..e6f4a36efa73 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -22,7 +22,7 @@ chosen { stdout-path = "serial0:115200n8"; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x1 0x0>; }; From patchwork Tue Jun 16 13:52:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310401 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; 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Tue, 16 Jun 2020 06:54:48 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id s18sm35893062wra.85.2020.06.16.06.54.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:54:46 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 49/73] arm64: tegra: Rename sdhci nodes to mmc Date: Tue, 16 Jun 2020 15:52:14 +0200 Message-Id: <20200616135238.3001888-50-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The new json-schema based validation tools require SD/MMC controller nodes to be named mmc. Rename all references to them. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 6 +++--- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 8 ++++---- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 10 +++++----- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 8 ++++---- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 8 ++++---- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 6 +++--- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 4 ++-- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 8 ++++---- 15 files changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index d0d03cc30197..e6fe62e5c234 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -894,12 +894,12 @@ pmc@7000e400 { }; /* WIFI/BT module */ - sdhci@700b0000 { + mmc@700b0000 { status = "disabled"; }; /* external SD/MMC */ - sdhci@700b0400 { + mmc@700b0400 { cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; @@ -909,7 +909,7 @@ sdhci@700b0400 { }; /* EMMC 4.51 */ - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 4fc34c5ec2dc..8558ad38b69c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -691,7 +691,7 @@ utmi-2 { }; }; - sdhci@700b0000 { + mmc@700b0000 { compatible = "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0000 0x0 0x200>; interrupts = ; @@ -702,7 +702,7 @@ sdhci@700b0000 { status = "disabled"; }; - sdhci@700b0200 { + mmc@700b0200 { compatible = "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0200 0x0 0x200>; interrupts = ; @@ -713,7 +713,7 @@ sdhci@700b0200 { status = "disabled"; }; - sdhci@700b0400 { + mmc@700b0400 { compatible = "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0400 0x0 0x200>; interrupts = ; @@ -724,7 +724,7 @@ sdhci@700b0400 { status = "disabled"; }; - sdhci@700b0600 { + mmc@700b0600 { compatible = "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0600 0x0 0x200>; interrupts = ; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index f35b0ba29cb5..37ec15a14c77 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -103,7 +103,7 @@ exp2: gpio@77 { }; /* SDMMC1 (SD/MMC) */ - sdhci@3400000 { + mmc@3400000 { status = "okay"; vmmc-supply = <&vdd_sd>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index 7b5b9bb332cf..d1ed7eee949a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -9,8 +9,8 @@ / { aliases { ethernet0 = "/ethernet@2490000"; - sdhci0 = "/sdhci@3460000"; - sdhci1 = "/sdhci@3400000"; + mmc0 = "/mmc@3460000"; + mmc1 = "/mmc@3400000"; serial0 = &uarta; i2c0 = "/bpmp/i2c"; i2c1 = "/i2c@3160000"; @@ -135,7 +135,7 @@ i2c@31e0000 { }; /* SDMMC1 (SD/MMC) */ - sdhci@3400000 { + mmc@3400000 { cd-gpios = <&gpio TEGRA186_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA186_MAIN_GPIO(P, 4) GPIO_ACTIVE_HIGH>; @@ -143,12 +143,12 @@ sdhci@3400000 { }; /* SDMMC3 (SDIO) */ - sdhci@3440000 { + mmc@3440000 { status = "okay"; }; /* SDMMC4 (eMMC) */ - sdhci@3460000 { + mmc@3460000 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index e86b682f8645..927c646620cb 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -333,7 +333,7 @@ gen9_i2c: i2c@31e0000 { status = "disabled"; }; - sdmmc1: sdhci@3400000 { + sdmmc1: mmc@3400000 { compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03400000 0x0 0x10000>; interrupts = ; @@ -362,7 +362,7 @@ sdmmc1: sdhci@3400000 { status = "disabled"; }; - sdmmc2: sdhci@3420000 { + sdmmc2: mmc@3420000 { compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03420000 0x0 0x10000>; interrupts = ; @@ -386,7 +386,7 @@ sdmmc2: sdhci@3420000 { status = "disabled"; }; - sdmmc3: sdhci@3440000 { + sdmmc3: mmc@3440000 { compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03440000 0x0 0x10000>; interrupts = ; @@ -412,7 +412,7 @@ sdmmc3: sdhci@3440000 { status = "disabled"; }; - sdmmc4: sdhci@3460000 { + sdmmc4: mmc@3460000 { compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03460000 0x0 0x10000>; interrupts = ; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index f3781e86f321..442e333ac13f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -9,8 +9,8 @@ / { aliases { ethernet0 = "/cbb@0/ethernet@2490000"; - sdhci0 = "/cbb@0/sdhci@3460000"; - sdhci1 = "/cbb@0/sdhci@3400000"; + mmc0 = "/cbb@0/mmc@3460000"; + mmc1 = "/cbb@0/mmc@3400000"; serial0 = &tcu; i2c0 = "/bpmp/i2c"; i2c1 = "/cbb@0/i2c@3160000"; @@ -58,12 +58,12 @@ serial@3110000 { }; /* SDMMC1 (SD/MMC) */ - sdhci@3400000 { + mmc@3400000 { cd-gpios = <&gpio TEGRA194_MAIN_GPIO(A, 0) GPIO_ACTIVE_LOW>; }; /* SDMMC4 (eMMC) */ - sdhci@3460000 { + mmc@3460000 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 9a7d136b467f..0f9868b6fd6b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -28,7 +28,7 @@ ddc: i2c@31c0000 { }; /* SDMMC1 (SD/MMC) */ - sdhci@3400000 { + mmc@3400000 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index f056158a2634..d5246c75b782 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -456,7 +456,7 @@ pwm8: pwm@32f0000 { #pwm-cells = <2>; }; - sdmmc1: sdhci@3400000 { + sdmmc1: mmc@3400000 { compatible = "nvidia,tegra194-sdhci"; reg = <0x03400000 0x10000>; interrupts = ; @@ -481,7 +481,7 @@ sdmmc1: sdhci@3400000 { status = "disabled"; }; - sdmmc3: sdhci@3440000 { + sdmmc3: mmc@3440000 { compatible = "nvidia,tegra194-sdhci"; reg = <0x03440000 0x10000>; interrupts = ; @@ -507,7 +507,7 @@ sdmmc3: sdhci@3440000 { status = "disabled"; }; - sdmmc4: sdhci@3460000 { + sdmmc4: mmc@3460000 { compatible = "nvidia,tegra194-sdhci"; reg = <0x03460000 0x10000>; interrupts = ; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 751775357d51..251c6099482a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -293,7 +293,7 @@ pmc@7000e400 { }; /* eMMC */ - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi index 9ace2d9ea085..f9158dc943f9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi @@ -34,7 +34,7 @@ pmc@7000e400 { }; /* eMMC */ - sdhci@700b0600 { + mmc@700b0600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index f72afdf547ee..fb0db05647c4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1500,7 +1500,7 @@ usb3-1 { }; /* MMC/SD */ - sdhci@700b0000 { + mmc@700b0000 { status = "okay"; bus-width = <4>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index 615a8f5a6cf2..579d5b8a757d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -1580,7 +1580,7 @@ pmc@7000e400 { status = "okay"; }; - sdhci@700b0600 { + mmc@700b0600 { bus-width = <8>; non-removable; status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index e6f4a36efa73..4a354f5293fc 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -535,7 +535,7 @@ usb3-0 { }; }; - sdhci@700b0000 { + mmc@700b0000 { status = "okay"; bus-width = <4>; @@ -553,7 +553,7 @@ usb@700d0000 { hvdd-usb-supply = <&vdd_1v8>; }; - sdhci@700b0400 { + mmc@700b0400 { status = "okay"; bus-width = <4>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 0b5b6ffbff43..d32053934f3c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1693,7 +1693,7 @@ usb3-0 { }; }; - sdhci@700b0600 { + mmc@700b0600 { bus-width = <8>; non-removable; status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 41ffa0531cd8..1f7dc518b394 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1175,7 +1175,7 @@ usb3-3 { }; }; - sdhci@700b0000 { + mmc@700b0000 { compatible = "nvidia,tegra210-sdhci"; reg = <0x0 0x700b0000 0x0 0x200>; interrupts = ; @@ -1203,7 +1203,7 @@ sdhci@700b0000 { status = "disabled"; }; - sdhci@700b0200 { + mmc@700b0200 { compatible = "nvidia,tegra210-sdhci"; reg = <0x0 0x700b0200 0x0 0x200>; interrupts = ; @@ -1220,7 +1220,7 @@ sdhci@700b0200 { status = "disabled"; }; - sdhci@700b0400 { + mmc@700b0400 { compatible = "nvidia,tegra210-sdhci"; reg = <0x0 0x700b0400 0x0 0x200>; interrupts = ; @@ -1243,7 +1243,7 @@ sdhci@700b0400 { status = "disabled"; }; - sdhci@700b0600 { + mmc@700b0600 { compatible = "nvidia,tegra210-sdhci"; reg = <0x0 0x700b0600 0x0 0x200>; interrupts = ; From patchwork Tue Jun 16 13:52:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310402 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; 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Tue, 16 Jun 2020 06:54:50 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id c6sm4337866wma.15.2020.06.16.06.54.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:54:49 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 50/73] arm64: tegra: Enable XUSB on Norrin Date: Tue, 16 Jun 2020 15:52:15 +0200 Message-Id: <20200616135238.3001888-51-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Use the XUSB controller instead of the legacy EHCI controller to enable USB 3.0 support. Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra132-norrin.dts | 124 +++++++++++---- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 148 ++++++++++++++++-- 2 files changed, 230 insertions(+), 42 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index e6fe62e5c234..bba8a4b82b0b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -671,7 +671,7 @@ vdd_gpu: sd6 { regulator-boot-on; }; - ldo0 { + avdd_1v05_run: ldo0 { regulator-name = "+1.05_RUN_AVDD"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; @@ -893,6 +893,101 @@ pmc@7000e400 { nvidia,reset-gpio = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; }; + usb@70090000 { + phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */ + <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */ + <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */ + <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */ + <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */ + phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1"; + + avddio-pex-supply = <&vdd_1v05_run>; + dvddio-pex-supply = <&vdd_1v05_run>; + avdd-usb-supply = <&vdd_3v3_lp0>; + hvdd-usb-ss-supply = <&vdd_3v3_lp0>; + + status = "okay"; + }; + + padctl@7009f000 { + avdd-pll-utmip-supply = <&vddio_1v8>; + avdd-pll-erefe-supply = <&avdd_1v05_run>; + avdd-pex-pll-supply = <&vdd_1v05_run>; + hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; + + pads { + usb2 { + status = "okay"; + + lanes { + usb2-0 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-1 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-2 { + nvidia,function = "xusb"; + status = "okay"; + }; + }; + }; + + pcie { + status = "okay"; + + lanes { + pcie-0 { + nvidia,function = "usb3-ss"; + status = "okay"; + }; + + pcie-1 { + nvidia,function = "usb3-ss"; + status = "okay"; + }; + }; + }; + }; + + ports { + usb2-0 { + status = "okay"; + mode = "otg"; + + vbus-supply = <&vdd_usb1_vbus>; + }; + + usb2-1 { + status = "okay"; + mode = "host"; + + vbus-supply = <&vdd_run_cam>; + }; + + usb2-2 { + status = "okay"; + mode = "host"; + + vbus-supply = <&vdd_usb3_vbus>; + }; + + usb3-0 { + nvidia,usb2-companion = <0>; + status = "okay"; + }; + + usb3-1 { + nvidia,usb2-companion = <2>; + status = "okay"; + }; + }; + }; + /* WIFI/BT module */ mmc@700b0000 { status = "disabled"; @@ -915,33 +1010,6 @@ mmc@700b0600 { non-removable; }; - usb@7d000000 { - status = "okay"; - }; - - usb-phy@7d000000 { - status = "okay"; - vbus-supply = <&vdd_usb1_vbus>; - }; - - usb@7d004000 { - status = "okay"; - }; - - usb-phy@7d004000 { - status = "okay"; - vbus-supply = <&vdd_run_cam>; - }; - - usb@7d008000 { - status = "okay"; - }; - - usb-phy@7d008000 { - status = "okay"; - vbus-supply = <&vdd_usb3_vbus>; - }; - backlight: backlight { compatible = "pwm-backlight"; diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 8558ad38b69c..0cc6b4e9f954 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -50,9 +50,6 @@ pcie@1003000 { reset-names = "pex", "afi", "pcie_x"; status = "disabled"; - phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; - phy-names = "pcie"; - pci@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; @@ -630,8 +627,6 @@ sata@70020000 { <&tegra_car 123>, <&tegra_car 129>; reset-names = "sata", "sata-oob", "sata-cold"; - phys = <&padctl TEGRA_XUSB_PADCTL_SATA>; - phy-names = "sata-phy"; status = "disabled"; }; @@ -651,6 +646,41 @@ hda@70030000 { status = "disabled"; }; + usb@70090000 { + compatible = "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"; + reg = <0x0 0x70090000 0x0 0x8000>, + <0x0 0x70098000 0x0 0x1000>, + <0x0 0x70099000 0x0 0x1000>; + reg-names = "hcd", "fpci", "ipfs"; + + interrupts = , + ; + + clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, + <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_SS>, + <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, + <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, + <&tegra_car TEGRA124_CLK_PLL_U_480M>, + <&tegra_car TEGRA124_CLK_CLK_M>, + <&tegra_car TEGRA124_CLK_PLL_E>; + clock-names = "xusb_host", "xusb_host_src", + "xusb_falcon_src", "xusb_ss", + "xusb_ss_src", "xusb_ss_div2", + "xusb_hs_src", "xusb_fs_src", + "pll_u_480m", "clk_m", "pll_e"; + resets = <&tegra_car 89>, <&tegra_car 156>, + <&tegra_car 143>; + reset-names = "xusb_host", "xusb_ss", "xusb_src"; + + nvidia,xusb-padctl = <&padctl>; + + status = "disabled"; + }; + padctl: padctl@7009f000 { compatible = "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"; @@ -658,34 +688,124 @@ padctl: padctl@7009f000 { resets = <&tegra_car 142>; reset-names = "padctl"; - #phy-cells = <1>; + pads { + usb2 { + status = "disabled"; - phys { - pcie-0 { + lanes { + usb2-0 { + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-1 { + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-2 { + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + ulpi { status = "disabled"; + + lanes { + ulpi-0 { + status = "disabled"; + #phy-cells = <0>; + }; + }; }; - sata-0 { + hsic { status = "disabled"; + + lanes { + hsic-0 { + status = "disabled"; + #phy-cells = <0>; + }; + + hsic-1 { + status = "disabled"; + #phy-cells = <0>; + }; + }; }; - usb3-0 { + pcie { status = "disabled"; + + lanes { + pcie-0 { + status = "disabled"; + #phy-cells = <0>; + }; + + pcie-1 { + status = "disabled"; + #phy-cells = <0>; + }; + + pcie-2 { + status = "disabled"; + #phy-cells = <0>; + }; + + pcie-3 { + status = "disabled"; + #phy-cells = <0>; + }; + + pcie-4 { + status = "disabled"; + #phy-cells = <0>; + }; + }; }; - usb3-1 { + sata { + status = "disabled"; + + lanes { + sata-0 { + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + }; + + ports { + usb2-0 { + status = "disabled"; + }; + + usb2-1 { status = "disabled"; }; - utmi-0 { + usb2-2 { status = "disabled"; }; - utmi-1 { + hsic-0 { status = "disabled"; }; - utmi-2 { + hsic-1 { + status = "disabled"; + }; + + usb3-0 { + status = "disabled"; + }; + + usb3-1 { status = "disabled"; }; }; From patchwork Tue Jun 16 13:52:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310403 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Tue, 16 Jun 2020 06:54:52 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id j41sm539180wre.12.2020.06.16.06.54.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:54:51 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 51/73] arm64: tegra: Remove undocumented battery-name property Date: Tue, 16 Jun 2020 15:52:16 +0200 Message-Id: <20200616135238.3001888-52-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding battery-name is not a documented property, so drop it to avoid validation failures. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 1 - arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index bba8a4b82b0b..bb45ca6a5cf2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -781,7 +781,6 @@ TEGRA_GPIO(J, 0) battery: smart-battery { compatible = "sbs,sbs-battery"; reg = <0xb>; - battery-name = "battery"; sbs,i2c-retry-count = <2>; sbs,poll-retry-count = <10>; /* power-supplies = <&charger>; */ diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index d32053934f3c..9f630ecc06bc 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1330,7 +1330,6 @@ ec_i2c_0: i2c-tunnel { battery: bq27742@55 { compatible = "ti,bq27742"; reg = <0x55>; - battery-name = "battery"; }; }; }; From patchwork Tue Jun 16 13:52:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310404 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=isC2qMgE; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV7m5wsqz9sSS for ; Tue, 16 Jun 2020 23:55:00 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728899AbgFPNy5 (ORCPT ); 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Tue, 16 Jun 2020 06:54:53 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 52/73] arm64: tegra: Remove simple clocks bus Date: Tue, 16 Jun 2020 15:52:17 +0200 Message-Id: <20200616135238.3001888-53-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The standard way to do this is to list out the clocks at the top-level. Adopt the standard way to fix validation. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 15 ++++----------- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 15 ++++----------- arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi | 15 ++++----------- arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 15 ++++----------- .../arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 15 ++++----------- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 15 ++++----------- 6 files changed, 24 insertions(+), 66 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index bb45ca6a5cf2..278bef2d8810 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -1022,17 +1022,10 @@ backlight: backlight { backlight-boot-off; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; gpio-keys { diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 251c6099482a..8a4ba371ff92 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -300,17 +300,10 @@ mmc@700b0600 { vqmmc-supply = <&vdd_1v8>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; cpus { diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi index f9158dc943f9..58aa0518965e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi @@ -40,17 +40,10 @@ mmc@700b0600 { non-removable; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; cpus { diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index 579d5b8a757d..9f81cabdcbb6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -1586,17 +1586,10 @@ mmc@700b0600 { status = "okay"; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; gpio-keys { diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 4a354f5293fc..b888efcea86f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -566,17 +566,10 @@ mmc@700b0400 { wakeup-source; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; cpus { diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 9f630ecc06bc..a28ca6620b86 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1722,17 +1722,10 @@ agic@702f9000 { }; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: clock@0 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; cpus { From patchwork Tue Jun 16 13:52:18 2020 Content-Type: text/plain; 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Tue, 16 Jun 2020 06:54:55 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 53/73] arm64: tegra: Remove simple regulators bus Date: Tue, 16 Jun 2020 15:52:18 +0200 Message-Id: <20200616135238.3001888-54-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The standard way to do this is to list out the regulators at the top- level. Adopt the standard way to fix validation. Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra132-norrin.dts | 247 ++++++------ .../boot/dts/nvidia/tegra186-p2771-0000.dts | 81 ++-- .../arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 60 ++- .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 96 ++--- .../arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 23 +- .../arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 274 +++++++------ .../arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 361 ++++++++---------- .../boot/dts/nvidia/tegra210-p3450-0000.dts | 177 ++++----- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 137 +++---- 9 files changed, 671 insertions(+), 785 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index 278bef2d8810..607d28a6772e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -1055,142 +1055,139 @@ panel: panel { ddc-i2c-bus = <&dpaux>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; + vdd_mux: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "+VDD_MUX"; + regulator-min-microvolt = <19000000>; + regulator-max-microvolt = <19000000>; + regulator-always-on; + regulator-boot-on; + }; - vdd_mux: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "+VDD_MUX"; - regulator-min-microvolt = <19000000>; - regulator-max-microvolt = <19000000>; - regulator-always-on; - regulator-boot-on; - }; + vdd_5v0_sys: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "+5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "+5V_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; + vdd_3v3_sys: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; - vdd_3v3_sys: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "+3.3V_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; + vdd_3v3_run: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_RUN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&as3722 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; - vdd_3v3_run: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "+3.3V_RUN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&as3722 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; + vdd_3v3_hdmi: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_run>; + }; - vdd_3v3_hdmi: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_run>; - }; + vdd_led: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "+VDD_LED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_mux>; + }; - vdd_led: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "+VDD_LED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_mux>; - }; + vdd_usb1_vbus: regulator@6 { + compatible = "regulator-fixed"; + regulator-name = "+5V_USB_HS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; - vdd_usb1_vbus: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "+5V_USB_HS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_usb3_vbus: regulator@7 { + compatible = "regulator-fixed"; + regulator-name = "+5V_USB_SS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; - vdd_usb3_vbus: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "+5V_USB_SS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_3v3_panel: regulator@8 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_PANEL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&as3722 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; - vdd_3v3_panel: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "+3.3V_PANEL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&as3722 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; + vdd_hdmi_pll: regulator@9 { + compatible = "regulator-fixed"; + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05_run>; + }; - vdd_hdmi_pll: regulator@9 { - compatible = "regulator-fixed"; - reg = <9>; - regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05_run>; - }; + vdd_5v0_hdmi: regulator@10 { + compatible = "regulator-fixed"; + regulator-name = "+5V_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; - vdd_5v0_hdmi: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "+5V_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_5v0_ts: regulator@11 { + compatible = "regulator-fixed"; + regulator-name = "+5V_VDD_TS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vdd_5v0_ts: regulator@11 { - compatible = "regulator-fixed"; - reg = <11>; - regulator-name = "+5V_VDD_TS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + vdd_3v3_lp0: regulator@12 { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_LP0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* + * TODO: find a way to wire this up with the USB EHCI + * controllers so that it can be enabled on demand. + */ + regulator-always-on; + gpio = <&as3722 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 37ec15a14c77..43b8d643e7a1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -333,62 +333,51 @@ volume-down { }; }; - regulators { - vdd_sd: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; + vdd_sd: regulator@100 { + compatible = "regulator-fixed"; + regulator-name = "SD_CARD_SW_PWR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; - regulator-name = "SD_CARD_SW_PWR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA186_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; - gpio = <&gpio TEGRA186_MAIN_GPIO(P, 6) - GPIO_ACTIVE_HIGH>; - enable-active-high; - - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_hdmi: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - - regulator-name = "VDD_HDMI_5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + vin-supply = <&vdd_3v3_sys>; + }; - gpio = <&exp1 14 GPIO_ACTIVE_HIGH>; - enable-active-high; + vdd_hdmi: regulator@101 { + compatible = "regulator-fixed"; + regulator-name = "VDD_HDMI_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; - vin-supply = <&vdd_5v0_sys>; - }; + gpio = <&exp1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; - vdd_usb0: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - - regulator-name = "VDD_USB0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + vin-supply = <&vdd_5v0_sys>; + }; - gpio = <&gpio TEGRA186_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; + vdd_usb0: regulator@102 { + compatible = "regulator-fixed"; + regulator-name = "VDD_USB0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; - vin-supply = <&vdd_5v0_sys>; - }; + gpio = <&gpio TEGRA186_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; - vdd_usb1: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; + vin-supply = <&vdd_5v0_sys>; + }; - regulator-name = "VDD_USB1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + vdd_usb1: regulator@103 { + compatible = "regulator-fixed"; + regulator-name = "VDD_USB1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA186_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; + gpio = <&gpio TEGRA186_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; + vin-supply = <&vdd_5v0_sys>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index d1ed7eee949a..b5568b9ff181 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -392,45 +392,33 @@ psci { method = "smc"; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - gnd: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - - regulator-name = "GND"; - regulator-min-microvolt = <0>; - regulator-max-microvolt = <0>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - - regulator-name = "VDD_5V0_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; + gnd: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "GND"; + regulator-min-microvolt = <0>; + regulator-max-microvolt = <0>; + regulator-always-on; + regulator-boot-on; + }; - vdd_1v8_ap: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; + vdd_5v0_sys: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V0_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; - regulator-name = "VDD_1V8_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + vdd_1v8_ap: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; - vin-supply = <&vdd_1v8>; - }; + vin-supply = <&vdd_1v8>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 442e333ac13f..6f2c0754c870 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -293,65 +293,49 @@ temperature-sensor@4c { }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_5v0_sys: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - - regulator-name = "VIN_SYS_5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_hdmi: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - - regulator-name = "VDD_5V0_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA194_MAIN_GPIO(A, 3) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_3v3_pcie: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - - regulator-name = "PEX_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - enable-active-high; - }; + vdd_5v0_sys: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "VIN_SYS_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; - vdd_12v_pcie: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; + vdd_hdmi: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V0_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA194_MAIN_GPIO(A, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - regulator-name = "VDD_12V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; + vdd_3v3_pcie: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "PEX_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + enable-active-high; + }; - vdd_5v_sata: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; + vdd_12v_pcie: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "VDD_12V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; - regulator-name = "VDD_5V_SATA"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + vdd_5v_sata: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V_SATA"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 8a4ba371ff92..d818fac3070c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -335,18 +335,15 @@ psci { method = "smc"; }; - regulators { - vdd_gpu: regulator@100 { - compatible = "pwm-regulator"; - reg = <100>; - pwms = <&pwm 1 4880>; - regulator-name = "VDD_GPU"; - regulator-min-microvolt = <710000>; - regulator-max-microvolt = <1320000>; - enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; - regulator-ramp-delay = <80>; - regulator-enable-ramp-delay = <2000>; - regulator-settling-time-us = <160>; - }; + vdd_gpu: regulator@100 { + compatible = "pwm-regulator"; + pwms = <&pwm 1 4880>; + regulator-name = "VDD_GPU"; + regulator-min-microvolt = <710000>; + regulator-max-microvolt = <1320000>; + enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; + regulator-ramp-delay = <80>; + regulator-enable-ramp-delay = <2000>; + regulator-settling-time-us = <160>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index fb0db05647c4..4771c1668825 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1518,152 +1518,6 @@ usb@700d0000 { hvdd-usb-supply = <&vdd_1v8>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_sys_mux: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "VDD_SYS_MUX"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "VDD_5V0_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_sys_mux>; - }; - - vdd_3v3_sys: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "VDD_3V3_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_sys_mux>; - - regulator-enable-ramp-delay = <160>; - regulator-disable-ramp-delay = <10000>; - }; - - vdd_5v0_io: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "VDD_5V0_IO_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_3v3_sd: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "VDD_3V3_SD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - - regulator-enable-ramp-delay = <472>; - regulator-disable-ramp-delay = <4880>; - }; - - vdd_dsi_csi: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "AVDD_DSI_CSI_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - vin-supply = <&vdd_sys_1v2>; - }; - - vdd_3v3_dis: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "VDD_DIS_3V3_LCD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_1v8_dis: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "VDD_LCD_1V8_DIS"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - gpio = <&exp1 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_1v8>; - }; - - vdd_5v0_rtl: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "RTL_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb_vbus: regulator@9 { - compatible = "regulator-fixed"; - reg = <9>; - regulator-name = "USB_VBUS_EN1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb_vbus_otg: regulator@11 { - compatible = "regulator-fixed"; - reg = <9>; - regulator-name = "USB_VBUS_EN0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_hdmi: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "VDD_HDMI_5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&exp1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - }; - gpio-keys { compatible = "gpio-keys"; label = "gpio-keys"; @@ -1687,4 +1541,132 @@ volume_up { linux,code = ; }; }; + + vdd_sys_mux: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "VDD_SYS_MUX"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_5v0_sys: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V0_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_sys_mux>; + }; + + vdd_3v3_sys: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_sys_mux>; + + regulator-enable-ramp-delay = <160>; + regulator-disable-ramp-delay = <10000>; + }; + + vdd_5v0_io: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V0_IO_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v3_sd: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + + regulator-enable-ramp-delay = <472>; + regulator-disable-ramp-delay = <4880>; + }; + + vdd_dsi_csi: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "AVDD_DSI_CSI_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vdd_sys_1v2>; + }; + + vdd_3v3_dis: regulator@6 { + compatible = "regulator-fixed"; + regulator-name = "VDD_DIS_3V3_LCD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_1v8_dis: regulator@7 { + compatible = "regulator-fixed"; + regulator-name = "VDD_LCD_1V8_DIS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + gpio = <&exp1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_1v8>; + }; + + vdd_5v0_rtl: regulator@8 { + compatible = "regulator-fixed"; + regulator-name = "RTL_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_usb_vbus: regulator@9 { + compatible = "regulator-fixed"; + regulator-name = "USB_VBUS_EN1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_usb_vbus_otg: regulator@11 { + compatible = "regulator-fixed"; + regulator-name = "USB_VBUS_EN0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_hdmi: regulator@10 { + compatible = "regulator-fixed"; + regulator-name = "VDD_HDMI_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&exp1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index 9f81cabdcbb6..a348789bc5e1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -1635,223 +1635,198 @@ psci { method = "smc"; }; - regulators { - compatible = "simple-bus"; - device_type = "fixed-regulators"; - #address-cells = <1>; - #size-cells = <0>; - - battery_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd-ac-bat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + battery_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vdd-ac-bat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - vdd_3v3: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vdd-3v3"; - regulator-enable-ramp-delay = <160>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - - gpio = <&max77620 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + vdd_3v3: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vdd-3v3"; + regulator-enable-ramp-delay = <160>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; - max77620_gpio7: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "max77620-gpio7"; - regulator-enable-ramp-delay = <240>; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - vin-supply = <&max77620_ldo0>; - regulator-always-on; - regulator-boot-on; - - gpio = <&max77620 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - lcd_bl_en: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "lcd-bl-en"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; + max77620_gpio7: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "max77620-gpio7"; + regulator-enable-ramp-delay = <240>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&max77620_ldo0>; + regulator-always-on; + regulator-boot-on; + + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + lcd_bl_en: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "lcd-bl-en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; - en_vdd_sd: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "en-vdd-sd"; - regulator-enable-ramp-delay = <472>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3>; - - gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - en_vdd_cam: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "en-vdd-cam"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + en_vdd_sd: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "en-vdd-sd"; + regulator-enable-ramp-delay = <472>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3>; - gpio = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vdd_sys_boost: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "vdd-sys-boost"; - regulator-enable-ramp-delay = <3090>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - - gpio = <&max77620 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + en_vdd_cam: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "en-vdd-cam"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; - vdd_hdmi: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "vdd-hdmi"; - regulator-enable-ramp-delay = <468>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vdd_sys_boost>; - regulator-boot-on; - - gpio = <&gpio TEGRA_GPIO(CC, 7) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + gpio = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - en_vdd_cpu_fixed: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "vdd-cpu-fixed"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; + vdd_sys_boost: regulator@6 { + compatible = "regulator-fixed"; + regulator-name = "vdd-sys-boost"; + regulator-enable-ramp-delay = <3090>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; - vdd_aux_3v3: regulator@9 { - compatible = "regulator-fixed"; - reg = <9>; - regulator-name = "aux-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vdd_snsr_pm: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "snsr_pm"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + vdd_hdmi: regulator@7 { + compatible = "regulator-fixed"; + regulator-name = "vdd-hdmi"; + regulator-enable-ramp-delay = <468>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vdd_sys_boost>; + regulator-boot-on; + + gpio = <&gpio TEGRA_GPIO(CC, 7) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - enable-active-high; - }; + en_vdd_cpu_fixed: regulator@8 { + compatible = "regulator-fixed"; + regulator-name = "vdd-cpu-fixed"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; - vdd_usb_5v0: regulator@11 { - compatible = "regulator-fixed"; - reg = <11>; - status = "disabled"; - regulator-name = "vdd-usb-5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vdd_3v3>; + vdd_aux_3v3: regulator@9 { + compatible = "regulator-fixed"; + regulator-name = "aux-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; - enable-active-high; - }; + vdd_snsr_pm: regulator@10 { + compatible = "regulator-fixed"; + regulator-name = "snsr_pm"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; - vdd_cdc_1v2_aud: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - status = "disabled"; - regulator-name = "vdd_cdc_1v2_aud"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - startup-delay-us = <250000>; + enable-active-high; + }; - enable-active-high; - }; + vdd_usb_5v0: regulator@11 { + compatible = "regulator-fixed"; + status = "disabled"; + regulator-name = "vdd-usb-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vdd_3v3>; - vdd_disp_3v0: regulator@12 { - compatible = "regulator-fixed"; - reg = <12>; - regulator-name = "vdd-disp-3v0"; - regulator-enable-ramp-delay = <232>; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - - gpio = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + enable-active-high; + }; - vdd_fan: regulator@13 { - compatible = "regulator-fixed"; - reg = <13>; - regulator-name = "vdd-fan"; - regulator-enable-ramp-delay = <284>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + vdd_cdc_1v2_aud: regulator@101 { + compatible = "regulator-fixed"; + status = "disabled"; + regulator-name = "vdd_cdc_1v2_aud"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + startup-delay-us = <250000>; - gpio = <&gpio TEGRA_GPIO(E, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + enable-active-high; + }; - usb_vbus1: regulator@14 { - compatible = "regulator-fixed"; - reg = <14>; - regulator-name = "usb-vbus1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + vdd_disp_3v0: regulator@12 { + compatible = "regulator-fixed"; + regulator-name = "vdd-disp-3v0"; + regulator-enable-ramp-delay = <232>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; - gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - }; + gpio = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - usb_vbus2: regulator@15 { - compatible = "regulator-fixed"; - reg = <15>; - regulator-name = "usb-vbus2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + vdd_fan: regulator@13 { + compatible = "regulator-fixed"; + regulator-name = "vdd-fan"; + regulator-enable-ramp-delay = <284>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - }; + gpio = <&gpio TEGRA_GPIO(E, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vdd_3v3_eth: regulator@16 { - compatible = "regulator-fixed"; - reg = <16>; - regulator-name = "vdd-3v3-eth-a02"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - }; + usb_vbus1: regulator@14 { + compatible = "regulator-fixed"; + regulator-name = "usb-vbus1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + }; + + usb_vbus2: regulator@15 { + compatible = "regulator-fixed"; + regulator-name = "usb-vbus2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + }; + + vdd_3v3_eth: regulator@16 { + compatible = "regulator-fixed"; + regulator-name = "vdd-3v3-eth-a02"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index b888efcea86f..d7a4eced0149 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -683,120 +683,109 @@ psci { method = "smc"; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_5v0_sys: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - - regulator-name = "VDD_5V0_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; + vdd_5v0_sys: regulator@0 { + compatible = "regulator-fixed"; + + regulator-name = "VDD_5V0_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; - vdd_3v3_sys: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "VDD_3V3_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <240>; - regulator-disable-ramp-delay = <11340>; - regulator-always-on; - regulator-boot-on; - - gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - - vin-supply = <&vdd_5v0_sys>; - }; + vdd_3v3_sys: regulator@1 { + compatible = "regulator-fixed"; - vdd_3v3_sd: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; + regulator-name = "VDD_3V3_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <240>; + regulator-disable-ramp-delay = <11340>; + regulator-always-on; + regulator-boot-on; - regulator-name = "VDD_3V3_SD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; + enable-active-high; - gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; - enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; - vin-supply = <&vdd_3v3_sys>; - }; + vdd_3v3_sd: regulator@2 { + compatible = "regulator-fixed"; - vdd_hdmi: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; + regulator-name = "VDD_3V3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; - regulator-name = "VDD_HDMI_5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; + vin-supply = <&vdd_3v3_sys>; + }; - vdd_hub_3v3: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; + vdd_hdmi: regulator@3 { + compatible = "regulator-fixed"; - regulator-name = "VDD_HUB_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-name = "VDD_HDMI_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; - vin-supply = <&vdd_5v0_sys>; - }; + vdd_hub_3v3: regulator@4 { + compatible = "regulator-fixed"; + + regulator-name = "VDD_HUB_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; - vdd_cpu: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; + gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; - regulator-name = "VDD_CPU"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; + vin-supply = <&vdd_5v0_sys>; + }; - gpio = <&pmic 5 GPIO_ACTIVE_HIGH>; - enable-active-high; + vdd_cpu: regulator@5 { + compatible = "regulator-fixed"; - vin-supply = <&vdd_5v0_sys>; - }; + regulator-name = "VDD_CPU"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; - vdd_gpu: regulator@6 { - compatible = "pwm-regulator"; - reg = <6>; - pwms = <&pwm 1 4880>; - regulator-name = "VDD_GPU"; - regulator-min-microvolt = <710000>; - regulator-max-microvolt = <1320000>; - regulator-ramp-delay = <80>; - regulator-enable-ramp-delay = <2000>; - regulator-settling-time-us = <160>; - enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v0_sys>; - }; + gpio = <&pmic 5 GPIO_ACTIVE_HIGH>; + enable-active-high; - avdd_io_edp_1v05: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; + vin-supply = <&vdd_5v0_sys>; + }; - regulator-name = "AVDD_IO_EDP_1V05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; + vdd_gpu: regulator@6 { + compatible = "pwm-regulator"; + pwms = <&pwm 1 4880>; - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; - enable-active-high; + regulator-name = "VDD_GPU"; + regulator-min-microvolt = <710000>; + regulator-max-microvolt = <1320000>; + regulator-ramp-delay = <80>; + regulator-enable-ramp-delay = <2000>; + regulator-settling-time-us = <160>; - vin-supply = <&avdd_1v05_pll>; - }; + enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v0_sys>; + }; + + avdd_io_edp_1v05: regulator@7 { + compatible = "regulator-fixed"; + + regulator-name = "AVDD_IO_EDP_1V05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&avdd_1v05_pll>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index a28ca6620b86..cc0d7b4a5834 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1803,88 +1803,73 @@ psci { method = "smc"; }; - regulators { - compatible = "simple-bus"; - device_type = "fixed-regulators"; - #address-cells = <1>; - #size-cells = <0>; - - ppvar_sys: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "PPVAR_SYS"; - regulator-min-microvolt = <4400000>; - regulator-max-microvolt = <4400000>; - regulator-always-on; - }; + ppvar_sys: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "PPVAR_SYS"; + regulator-min-microvolt = <4400000>; + regulator-max-microvolt = <4400000>; + regulator-always-on; + }; - pplcd_vdd: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "PPLCD_VDD"; - regulator-min-microvolt = <4400000>; - regulator-max-microvolt = <4400000>; - gpio = <&gpio TEGRA_GPIO(V, 4) 0>; - enable-active-high; - regulator-boot-on; - }; + pplcd_vdd: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "PPLCD_VDD"; + regulator-min-microvolt = <4400000>; + regulator-max-microvolt = <4400000>; + gpio = <&gpio TEGRA_GPIO(V, 4) 0>; + enable-active-high; + regulator-boot-on; + }; - pp3000_always: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "PP3000_ALWAYS"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; + pp3000_always: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "PP3000_ALWAYS"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; - pp3300: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "PP3300"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - enable-active-high; - }; + pp3300: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "PP3300"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + }; - pp5000: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "PP5000"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + pp5000: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "PP5000"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - pp1800_lcdio: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "PP1800_LCDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio TEGRA_GPIO(V, 3) 0>; - enable-active-high; - regulator-boot-on; - }; + pp1800_lcdio: regulator@5 { + compatible = "regulator-fixed"; + regulator-name = "PP1800_LCDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio TEGRA_GPIO(V, 3) 0>; + enable-active-high; + regulator-boot-on; + }; - pp1800_cam: regulator@6 { - compatible = "regulator-fixed"; - reg= <6>; - regulator-name = "PP1800_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio TEGRA_GPIO(K, 3) 0>; - enable-active-high; - }; + pp1800_cam: regulator@6 { + compatible = "regulator-fixed"; + regulator-name = "PP1800_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio TEGRA_GPIO(K, 3) 0>; + enable-active-high; + }; - usbc_vbus: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "USBC_VBUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; + usbc_vbus: regulator@7 { + compatible = "regulator-fixed"; + regulator-name = "USBC_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; }; }; From patchwork Tue Jun 16 13:52:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310406 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Tue, 16 Jun 2020 06:54:58 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id k14sm28335712wrq.97.2020.06.16.06.54.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:54:57 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 54/73] arm64: tegra: norrin: Add missing panel power supply Date: Tue, 16 Jun 2020 15:52:19 +0200 Message-Id: <20200616135238.3001888-55-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding This panel supply is always on, so this does happen to work by accident. Make sure to properly hook up the power supply to model the dependency correctly and so that the panel continues to operate properly even if the supply is not always on. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index 607d28a6772e..fb27812eace1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -1051,6 +1051,7 @@ power { panel: panel { compatible = "innolux,n116bge"; + power-supply = <&vdd_3v3_panel>; backlight = <&backlight>; ddc-i2c-bus = <&dpaux>; }; From patchwork Tue Jun 16 13:52:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310407 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=QvwVCvkO; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV7z4Wjsz9sSS for ; Tue, 16 Jun 2020 23:55:11 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728885AbgFPNzJ (ORCPT ); Tue, 16 Jun 2020 09:55:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728917AbgFPNzD (ORCPT ); Tue, 16 Jun 2020 09:55:03 -0400 Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D357C06174E for ; Tue, 16 Jun 2020 06:55:02 -0700 (PDT) Received: by mail-wm1-x343.google.com with SMTP id b82so2984379wmb.1 for ; Tue, 16 Jun 2020 06:55:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=W/M1fUYn2r2/Jsy3Jez/sKFCeauEM3+RErjPgAoJLmI=; b=QvwVCvkOEKFlweEvbjFoMYj2e7vsPdY6rdLKHGYbxYvHwE/46T50FrSOij388qcQTe 5SPqom4Km8Oh0CjnG3EwE9wNIsoOOx/qW4l8Z7Ipo9ts8LB+gStxyF38B+LNsJCcqN6Y BqVudkEncyKzn3O/Sv/t6Lh9RBAWIeL3BwTS272YK3fjMPGwSJdptGR7O7/fMGevPTgc AjIf5FRrNjzmrsSiLEfWI1E9xiqZ9TRjJvEidgV/SNzaK7BE2TCbytYmSRz0oKYYFtzL wS0uD8nfeEr/3oU5hqqlhvErGBop3VFkm65MKzrcFNbsICFmMddu6jese4mRmrnA0V++ jspg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W/M1fUYn2r2/Jsy3Jez/sKFCeauEM3+RErjPgAoJLmI=; b=mJSSW86EoLYY7NDCMOhWe3Mf4E6GhY+LXGeF55Frq2qloFNFBvcbM2FgBWz/qt6emM 2Bv6Hy+GMqEcq0jXCw/QkYFzXhkSeKkRdnyb1g921fzx2U2fOiPe3gU9PMtlCSTcSpyd QvkJ7pvu86UFlIxWbWSCZgAisNSoS/Ca7IZ+1+pAnP39yZkqHa9u381W3j4Zhov506dI 8zexstcgk/OQKha3NWLLUa2AKuSPwKvUF44vJyw9yrOF+gWheacgh7SWeQnkyjF9mt6G B2RnDlQq7USm83pbp81J9bh1C5Jo2rRYII54SBITKjTBA6ey4DtUxYDJqKIedWvFJ1vI 0r6Q== X-Gm-Message-State: AOAM532rEaLaGi7VTWvk+P5H0Frt9CdTsUy/tSfv2Mb38M8aWblErbCR DhZo6I7F6GhFPVKumdL5/ZQ= X-Google-Smtp-Source: ABdhPJwzYfMAuWzLLvj+zU7n3KVwF9WrcoLap5wgsHnyIkUTKJKLQ73mEnafvLyTjYqrWKbdcv7XSQ== X-Received: by 2002:a1c:7dd5:: with SMTP id y204mr3190652wmc.182.1592315700743; Tue, 16 Jun 2020 06:55:00 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id c65sm4142705wme.8.2020.06.16.06.54.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:54:59 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 55/73] arm64: tegra: Use proper tuple notation Date: Tue, 16 Jun 2020 15:52:20 +0200 Message-Id: <20200616135238.3001888-56-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Tuple boundaries should be marked by < and > to make it clear which cells are part of the same tuple. This also helps the json-schema based validation tooling to properly parse this data. While at it, also remove the "immovable" bit from PCI addresses. All of these addresses are in fact "movable". Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 16 +-- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 18 +-- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 112 +++++++++--------- .../arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 3 +- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 16 +-- 5 files changed, 83 insertions(+), 82 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 0cc6b4e9f954..fa5ee55fd4a5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -17,9 +17,9 @@ / { pcie@1003000 { compatible = "nvidia,tegra124-pcie"; device_type = "pci"; - reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ - 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ - 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ + reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ + <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ + <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ reg-names = "pads", "afi", "cs"; interrupts = , /* controller interrupt */ ; /* MSI interrupt */ @@ -33,11 +33,11 @@ pcie@1003000 { #address-cells = <3>; #size-cells = <2>; - ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ - 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ - 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ - 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ - 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ + ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ + <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ + <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ + <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ + <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ clocks = <&tegra_car TEGRA124_CLK_PCIE>, <&tegra_car TEGRA124_CLK_AFI>, diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 927c646620cb..184cc0365002 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -776,9 +776,9 @@ pcie@10003000 { compatible = "nvidia,tegra186-pcie"; power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; device_type = "pci"; - reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ - 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ - 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ + reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ + <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ + <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ reg-names = "pads", "afi", "cs"; interrupts = , /* controller interrupt */ @@ -793,12 +793,12 @@ pcie@10003000 { #address-cells = <3>; #size-cells = <2>; - ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ - 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ - 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ - 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ - 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ - 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ + ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ + <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ + <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ + <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ + <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ + <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ clocks = <&bpmp TEGRA186_CLK_AFI>, <&bpmp TEGRA186_CLK_PCIE>, diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index d5246c75b782..72ba5146b0a9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -144,8 +144,8 @@ agic: interrupt-controller@2a40000 { pinmux: pinmux@2430000 { compatible = "nvidia,tegra194-pinmux"; - reg = <0x2430000 0x17000 - 0xc300000 0x4000>; + reg = <0x2430000 0x17000>, + <0xc300000 0x4000>; status = "okay"; @@ -1404,10 +1404,10 @@ sor3: sor@15bc0000 { pcie@14100000 { compatible = "nvidia,tegra194-pcie"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; - reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */ - 0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */ - 0x00 0x30040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ - 0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ reg-names = "appl", "config", "atu_dma", "dbi"; status = "disabled"; @@ -1442,9 +1442,9 @@ pcie@14100000 { bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc3000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */ - 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ + ranges = <0x01000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000>, /* downstream I/O (1MB) */ + <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768MB) */ + <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; @@ -1454,10 +1454,10 @@ pcie@14100000 { pcie@14120000 { compatible = "nvidia,tegra194-pcie"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; - reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */ - 0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */ - 0x00 0x32040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ - 0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ reg-names = "appl", "config", "atu_dma", "dbi"; status = "disabled"; @@ -1492,9 +1492,9 @@ pcie@14120000 { bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc3000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */ - 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ + ranges = <0x01000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000>, /* downstream I/O (1MB) */ + <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768MB) */ + <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; @@ -1504,10 +1504,10 @@ pcie@14120000 { pcie@14140000 { compatible = "nvidia,tegra194-pcie"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; - reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */ - 0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */ - 0x00 0x34040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ - 0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ reg-names = "appl", "config", "atu_dma", "dbi"; status = "disabled"; @@ -1542,9 +1542,9 @@ pcie@14140000 { bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc3000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */ - 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ + ranges = <0x01000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000>, /* downstream I/O (1MB) */ + <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768MB) */ + <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; @@ -1554,10 +1554,10 @@ pcie@14140000 { pcie@14160000 { compatible = "nvidia,tegra194-pcie"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; - reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */ - 0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */ - 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ - 0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ reg-names = "appl", "config", "atu_dma", "dbi"; status = "disabled"; @@ -1592,9 +1592,9 @@ pcie@14160000 { bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc3000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ - 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ + ranges = <0x01000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000>, /* downstream I/O (1MB) */ + <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13GB) */ + <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; @@ -1604,10 +1604,10 @@ pcie@14160000 { pcie@14180000 { compatible = "nvidia,tegra194-pcie"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; - reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ - 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */ - 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ - 0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ reg-names = "appl", "config", "atu_dma", "dbi"; status = "disabled"; @@ -1642,9 +1642,9 @@ pcie@14180000 { bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc3000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ - 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ + ranges = <0x01000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, /* downstream I/O (1MB) */ + <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13GB) */ + <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; @@ -1654,10 +1654,10 @@ pcie@14180000 { pcie@141a0000 { compatible = "nvidia,tegra194-pcie"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; - reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ - 0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */ - 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ - 0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ reg-names = "appl", "config", "atu_dma", "dbi"; status = "disabled"; @@ -1696,9 +1696,9 @@ pcie@141a0000 { bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc3000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ - 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ + ranges = <0x01000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000>, /* downstream I/O (1MB) */ + <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13GB) */ + <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; @@ -1708,10 +1708,10 @@ pcie@141a0000 { pcie_ep@14160000 { compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; - reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */ - 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ - 0x00 0x36080000 0x0 0x00040000 /* DBI reg space (256K) */ - 0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ + reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ reg-names = "appl", "atu_dma", "dbi", "addr_space"; status = "disabled"; @@ -1740,10 +1740,10 @@ pcie_ep@14160000 { pcie_ep@14180000 { compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; - reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ - 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ - 0x00 0x38080000 0x0 0x00040000 /* DBI reg space (256K) */ - 0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ + reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ reg-names = "appl", "atu_dma", "dbi", "addr_space"; status = "disabled"; @@ -1772,10 +1772,10 @@ pcie_ep@14180000 { pcie_ep@141a0000 { compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; - reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ - 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ - 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */ - 0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ + reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ reg-names = "appl", "atu_dma", "dbi", "addr_space"; status = "disabled"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index a348789bc5e1..1acb9bb6c7df 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -1387,7 +1387,8 @@ pin_gpio3 { spmic-default-output-high { gpio-hog; output-high; - gpios = <2 GPIO_ACTIVE_HIGH 7 GPIO_ACTIVE_HIGH>; + gpios = <2 GPIO_ACTIVE_HIGH>, + <7 GPIO_ACTIVE_HIGH>; }; fps { diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 1f7dc518b394..6a78056b94f4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -18,9 +18,9 @@ / { pcie@1003000 { compatible = "nvidia,tegra210-pcie"; device_type = "pci"; - reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ - 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ - 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ + reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ + <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ + <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ reg-names = "pads", "afi", "cs"; interrupts = , /* controller interrupt */ ; /* MSI interrupt */ @@ -34,11 +34,11 @@ pcie@1003000 { #address-cells = <3>; #size-cells = <2>; - ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ - 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ - 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ - 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ - 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ + ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ + <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ + <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ + <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ + <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ clocks = <&tegra_car TEGRA210_CLK_PCIE>, <&tegra_car TEGRA210_CLK_AFI>, From patchwork Tue Jun 16 13:52:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310408 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=ULToSW5X; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV803Cvtz9sRK for ; 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Tue, 16 Jun 2020 06:55:01 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 56/73] arm64: tegra: Do not mark host1x as simple bus Date: Tue, 16 Jun 2020 15:52:21 +0200 Message-Id: <20200616135238.3001888-57-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The host1x is not a simple bus, so drop the corresponding compatible string. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 3 +-- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 +- 4 files changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index fa5ee55fd4a5..c4d3a88403eb 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -81,8 +81,7 @@ pci@2,0 { host1x@50000000 { compatible = "nvidia,tegra132-host1x", - "nvidia,tegra124-host1x", - "simple-bus"; + "nvidia,tegra124-host1x"; reg = <0x0 0x50000000 0x0 0x00034000>; interrupts = , /* syncpt */ ; /* general */ diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 184cc0365002..b4150d8cccf5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -934,7 +934,7 @@ smmu: iommu@12000000 { }; host1x@13e00000 { - compatible = "nvidia,tegra186-host1x", "simple-bus"; + compatible = "nvidia,tegra186-host1x"; reg = <0x0 0x13e00000 0x0 0x10000>, <0x0 0x13e10000 0x0 0x10000>; reg-names = "hypervisor", "vm"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 72ba5146b0a9..bf696ada856c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1036,7 +1036,7 @@ pmc: pmc@c360000 { }; host1x@13e00000 { - compatible = "nvidia,tegra194-host1x", "simple-bus"; + compatible = "nvidia,tegra194-host1x"; reg = <0x13e00000 0x10000>, <0x13e10000 0x10000>; reg-names = "hypervisor", "vm"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 6a78056b94f4..02a02ed1b264 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -86,7 +86,7 @@ pci@2,0 { }; host1x@50000000 { - compatible = "nvidia,tegra210-host1x", "simple-bus"; + compatible = "nvidia,tegra210-host1x"; reg = <0x0 0x50000000 0x0 0x00034000>; interrupts = , /* syncpt */ ; /* general */ From patchwork Tue Jun 16 13:52:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310409 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=Vdtswjqn; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV812fHYz9sSg for ; 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Tue, 16 Jun 2020 06:55:03 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 57/73] arm64: tegra: Use sor0_out clock on Tegra132 Date: Tue, 16 Jun 2020 15:52:22 +0200 Message-Id: <20200616135238.3001888-58-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The sor0_out clock is required to make eDP work properly. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index c4d3a88403eb..6d9bd9cae388 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -141,10 +141,11 @@ sor@54540000 { reg = <0x0 0x54540000 0x0 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_SOR0>, + <&tegra_car TEGRA124_CLK_SOR0_OUT>, <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, <&tegra_car TEGRA124_CLK_PLL_DP>, <&tegra_car TEGRA124_CLK_CLK_M>; - clock-names = "sor", "parent", "dp", "safe"; + clock-names = "sor", "out", "parent", "dp", "safe"; resets = <&tegra_car 182>; reset-names = "sor"; status = "disabled"; From patchwork Tue Jun 16 13:52:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310410 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=Ufp+uCIt; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV821KBDz9sSS for ; Tue, 16 Jun 2020 23:55:14 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728815AbgFPNzM (ORCPT ); Tue, 16 Jun 2020 09:55:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729007AbgFPNzI (ORCPT ); Tue, 16 Jun 2020 09:55:08 -0400 Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1FCFBC061573 for ; Tue, 16 Jun 2020 06:55:08 -0700 (PDT) Received: by mail-wr1-x443.google.com with SMTP id e1so20910831wrt.5 for ; Tue, 16 Jun 2020 06:55:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=e92nXRna6f6oAJuVgO2pIVWwwjLBTK0H6SidJH7THA4=; b=Ufp+uCItGeMBFHM0yFc0yz9wVLzyxUSYssv8/bqJ8uQ1pg8opkofPigX6Ho+4sHbwW uyCkwKZOnUdPLzRqoqNan4BQwPACLZtsT1BxbtPdx09YcCxGWuno374EJko+FzItmzzM 3Unz5dNEY02EdMJd8dtW8Hduxn8w/uNifbwEl/KJrSmTP5h7etNxWzGRCzvAiZr5qZGW hf/NPpETrKY1NwzFORWTyOrxAbNDrimX3RqmLXZus7d4Qh2xy6qpeSFnpZ/XP6n/VpT4 mV2hoyV3uyK1zE+szEc2MVZUhhcW3LXnNgWUOPNgwdHQdsCfwvyB7FQu1zMX9Mfresj3 E49Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=e92nXRna6f6oAJuVgO2pIVWwwjLBTK0H6SidJH7THA4=; b=rLIFJ6fO+VVBL4sA+y6CG+9G4WhfwpBfOxFK3dDPnzW9upXDVor99Ku9PZf4LcEqsH jJ36LXnaGZPHLhWUc63xMYPACsgJvyiccMnn4W+59kJXwLrUxaF3JMDZ7Dv+DhP6It+j /g3Y6F6tJtBOWQOIYMz23iA56XjnRF/5GBKB5nGmbcLYF5yG88FZ9gc4KEveap4cZ5tF zAn1CG0MB5hSVK82k7vLismXcWL4Q2Dmq0IAmLR6qSYsqyuHTUEi5EMlSaDqUH5tgRv3 kYACSgY/eTGr6jMiTGRDNPrF0h49vN2o73dfq0jQd10Hr0sQPzMkEg6oZwBq8pNYLao7 UQOw== X-Gm-Message-State: AOAM532waPwGvNINbP0etsAVaqNaX8JPOh5JdT1i5ol75jK/7Cu3F1K1 lrLGNTrTTj41dNLEIws87Vo= X-Google-Smtp-Source: ABdhPJxU9dhTz7gsboG0QB69wlJs4Cyv0/uF0p4ZfoeNELT+fOfwzZzmOcZw3dyK+4QXoQO5ij9xlQ== X-Received: by 2002:a5d:4282:: with SMTP id k2mr3153179wrq.196.1592315706907; Tue, 16 Jun 2020 06:55:06 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id c6sm4339122wma.15.2020.06.16.06.55.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:55:05 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 58/73] arm64: tegra: Tegra132 EMC is not compatible with Tegra124 Date: Tue, 16 Jun 2020 15:52:23 +0200 Message-Id: <20200616135238.3001888-59-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The external memory controller found on Tegra132 is not fully compatible with the instantiation on Tegra124, so remove the corresponding string from the list of compatible strings. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 6d9bd9cae388..0425e584791b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -605,7 +605,7 @@ mc: memory-controller@70019000 { }; emc: external-memory-controller@7001b000 { - compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc"; + compatible = "nvidia,tegra132-emc"; reg = <0x0 0x7001b000 0x0 0x1000>; clocks = <&tegra_car TEGRA124_CLK_EMC>; clock-names = "emc"; From patchwork Tue Jun 16 13:52:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310411 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=ejfJqBK5; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV833SdVz9sRK for ; Tue, 16 Jun 2020 23:55:15 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729014AbgFPNzO (ORCPT ); Tue, 16 Jun 2020 09:55:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57308 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728861AbgFPNzM (ORCPT ); Tue, 16 Jun 2020 09:55:12 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8EBD1C06174E for ; Tue, 16 Jun 2020 06:55:10 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id d128so3181966wmc.1 for ; Tue, 16 Jun 2020 06:55:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OICfzC5DNLWC8Mt/Hql2kszDs/lPys4EDGoOcxnuo0E=; b=ejfJqBK5B17ICN8HyRWo+casH8nlg9Up9/8htgKPkCd8aRnMre1x9N/B/gQ0sWK3T1 bnWnGSaFnd1xS5jO4Fdk0JOTxkQgA7EUSGZamPQyABLoiIyXKpr3KAaovLLQK6R1JAr0 3SOJ5QpW6xINrnsIOBiV7PSAz8/zvXGQVHZYgjNF5CHA2gkAjvLp+S0Nvl/MXGB6lKQZ ziddCKD9Lb1xR6EY+y+Vkg0WXy276udCubEHjZfZoqE47rKHWxJViy1U0wSdj50w6bbR wjjVFaRipO/uTWuWhLv6Zrw+BCRBWtNSHEa/AflX7tw++/b8eXeP08UAitNIUcYb676b IdgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OICfzC5DNLWC8Mt/Hql2kszDs/lPys4EDGoOcxnuo0E=; b=TEO7tZ6TjKclHpuFO8BMhV6kiwa93bEPBsiH30j2jvKg9zb/oLZX2V3qYtkVU9+Ho8 hjtGGIoRbGmSKZkBYwulQ0vgGDxLxbGERaYfD+2grDeL510fJeW+FRa5chnrk+HdCY/J iWaBcb4ijh7N9dAZE5kde1+hsUpYo62oT64/XxCiT9M5lcFx72WNxZAdq+iaXaYM4Kii 7ZUVHUOlDNKFU53h03FyNsKwQitq2uUODym1BExW9osprxvcDJcPI86zo5qVXOoq5Vr7 vYaXp4qMOe3TXlRZC/SXjQ4cqrnMdU/vOTDByZ+HYXUxLSpmy4mAwt1Df4FOM2DL3hys aJgw== X-Gm-Message-State: AOAM532Cjf2o6ym2zo2NacYFd7wM0umbrv4SkB3QI7YwwOwrJZgb7HX9 m1MAHpoPOh85NR8rABm1XBo= X-Google-Smtp-Source: ABdhPJzOQCn/2tSUkdTXWMJYbll+3NsWiJc9+A2Xy3fZHYpJeayA9xv/Fk+mcpbj4ole1j/Zprj1qA== X-Received: by 2002:a7b:c944:: with SMTP id i4mr3358571wml.22.1592315709317; Tue, 16 Jun 2020 06:55:09 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id a10sm1096846wrm.21.2020.06.16.06.55.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:55:07 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 59/73] arm64: tegra: Add missing #phy-cells property to USB PHYs Date: Tue, 16 Jun 2020 15:52:24 +0200 Message-Id: <20200616135238.3001888-60-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding USB PHYs must have a #phy-cells property, so add one to the Tegra USB PHYs which don't have one. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 0425e584791b..9d1dd021a2cb 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -1113,6 +1113,7 @@ phy1: usb-phy@7d000000 { clock-names = "reg", "pll_u", "utmi-pads"; resets = <&tegra_car 22>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <0>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; @@ -1151,6 +1152,7 @@ phy2: usb-phy@7d004000 { clock-names = "reg", "pll_u", "utmi-pads"; resets = <&tegra_car 58>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <0>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; @@ -1188,6 +1190,7 @@ phy3: usb-phy@7d008000 { clock-names = "reg", "pll_u", "utmi-pads"; resets = <&tegra_car 59>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; nvidia,hssync-start-delay = <0>; nvidia,idle-wait-delay = <17>; nvidia,elastic-limit = <16>; From patchwork Tue Jun 16 13:52:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310412 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=lG33AK5P; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV840XWlz9sSg for ; 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Tue, 16 Jun 2020 06:55:10 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 60/73] arm64: tegra: Remove unneeded power supplies Date: Tue, 16 Jun 2020 15:52:25 +0200 Message-Id: <20200616135238.3001888-61-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding On Tegra186 and later, the BPMP is responsible for enabling/disabling the PCIe related power supplies of the pad controller and there is no need for the operating system to control them, so they can be removed. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 43b8d643e7a1..482ed7b0fcff 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -119,10 +119,6 @@ padctl@3520000 { avdd-pll-erefeut-supply = <&vdd_1v8_pll>; avdd-usb-supply = <&vdd_3v3_sys>; - dvdd-pex-supply = <&vdd_pex>; - dvdd-pex-pll-supply = <&vdd_pex>; - hvdd-pex-supply = <&vdd_1v8>; - hvdd-pex-pll-supply = <&vdd_1v8>; vclamp-usb-supply = <&vdd_1v8>; vddio-hsic-supply = <&gnd>; From patchwork Tue Jun 16 13:52:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310413 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=BbG8JMK4; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV850y9Kz9sSS for ; Tue, 16 Jun 2020 23:55:17 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728997AbgFPNzP (ORCPT ); Tue, 16 Jun 2020 09:55:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728553AbgFPNzO (ORCPT ); Tue, 16 Jun 2020 09:55:14 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05A7AC06174E for ; Tue, 16 Jun 2020 06:55:14 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id d128so3182187wmc.1 for ; Tue, 16 Jun 2020 06:55:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5UaeiYULrewUtGThWV95Xt3+CgB3hdR6MxdVeCxs+eU=; b=BbG8JMK4tEiZ0a2HH5vQb9gMCG84W2N5EGnIixOTYaqZ/4yn/FDrGR5qKk7J+fJN2j l5MiPzMoKpgbxClG4i2DXZWTfkO6oSxKjfFGyC2yeVjzmwKJg+snkWRNDI9qn/LLNSEP q2yE1ZZNykudgaJinVIB2JrpMbOriHb/gES1qM2JTtzzbCLuBeDLmB6UZQXujYUJHXyS R+aNafBH9Y2iS0gQXNdwdUDW51MOQ0h8ylCQfAKECO4WVW2617VQQvrTbFOf5EaQ3AUy 7bbld7Bwq/A+SbnVkvlhFLXXXBaYgRU08A7h0GOPUuDBv+KZz0P44WTjk3Y4pQPL5KUc DJxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5UaeiYULrewUtGThWV95Xt3+CgB3hdR6MxdVeCxs+eU=; b=kBdBJTIpZ85Dawfa6mTK9srIWiHS6079+hMzPMhRAzost6/pavUsm0qzz3lE7ayebd Mlie6WmZREH3/Valch1VuK64Licscx7GgLoMVKbbIMqp5W5me0NYdy40zbKiKmpoE32Z L64BlgIYXvoekQln/tqE69znakztIkjZC6qStK8ULaBAY0QmEbev+dvTRX0f4ge5GTKb PVFYuY2rdYBX9Qm6Y550DOKeeiGY1j2T/67rzKLk7FQHuJZbDMDcgW2PBrfRJOOkMPZ5 bofvUCO9eOOgecpPHpItVrhL3S5SWQWXnlzqkRZP/SWV+p1pshE03G77REcbtGByKtTJ pckw== X-Gm-Message-State: AOAM532odkIi1bqjDsxhwcv/zhd4hSqD3t0WrTl2czdEdDXR18tNbDPh o0JfwMk3rKhmrOD5l1z5Kdk= X-Google-Smtp-Source: ABdhPJx0YWWE5EwMSLqluEDsr0Na6X/CXb8aWgF9NZ01YYq2d32S8wQk3UtDXGfxw0Z+zyfFUmAI8w== X-Received: by 2002:a7b:c1c5:: with SMTP id a5mr3293085wmj.35.1592315712791; Tue, 16 Jun 2020 06:55:12 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id u130sm4293586wmg.32.2020.06.16.06.55.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:55:12 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 61/73] arm64: tegra: Update USB connector nodes Date: Tue, 16 Jun 2020 15:52:26 +0200 Message-Id: <20200616135238.3001888-62-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Use the preferred {id,vbus}-gpios over the {id,vbus}-gpio properties and fix the ordering of compatible strings (most-specific ones should come first). Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 15 +++++++-------- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 12 ++++++------ .../arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 10 +++++----- 3 files changed, 18 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 482ed7b0fcff..4a7a022acabb 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -171,19 +171,18 @@ usb2-0 { status = "okay"; mode = "otg"; vbus-supply = <&vdd_usb0>; - usb-role-switch; + connector { - compatible = "usb-b-connector", - "gpio-usb-b-connector"; + compatible = "gpio-usb-b-connector", + "usb-b-connector"; label = "micro-USB"; type = "micro"; - vbus-gpio = <&gpio - TEGRA186_MAIN_GPIO(X, 7) - GPIO_ACTIVE_LOW>; - id-gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + vbus-gpios = <&gpio + TEGRA186_MAIN_GPIO(X, 7) + GPIO_ACTIVE_LOW>; + id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>; }; - }; usb2-1 { diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 4771c1668825..3ba36a52dc89 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1456,17 +1456,17 @@ ports { usb2-0 { status = "okay"; vbus-supply = <&vdd_usb_vbus_otg>; + usb-role-switch; mode = "otg"; - usb-role-switch; connector { - compatible = "usb-b-connector", - "gpio-usb-b-connector"; + compatible = "gpio-usb-b-connector", + "usb-b-connector"; label = "micro-USB"; type = "micro"; - vbus-gpio = <&gpio TEGRA_GPIO(Z, 0) - GPIO_ACTIVE_LOW>; - id-gpio = <&pmic 0 0>; + vbus-gpios = <&gpio TEGRA_GPIO(Z, 0) + GPIO_ACTIVE_LOW>; + id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index d7a4eced0149..ac17f5485bf8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -505,15 +505,15 @@ ports { usb2-0 { status = "okay"; mode = "peripheral"; - usb-role-switch; + connector { - compatible = "usb-b-connector", - "gpio-usb-b-connector"; + compatible = "gpio-usb-b-connector", + "usb-b-connector"; label = "micro-USB"; type = "micro"; - vbus-gpio = <&gpio TEGRA_GPIO(CC, 4) - GPIO_ACTIVE_LOW>; + vbus-gpios = <&gpio TEGRA_GPIO(CC, 4) + GPIO_ACTIVE_LOW>; }; }; From patchwork Tue Jun 16 13:52:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310414 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=EGRqQsip; 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Tue, 16 Jun 2020 06:55:15 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id z9sm3919624wmi.41.2020.06.16.06.55.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:55:14 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 62/73] arm64: tegra: Use standard EEPROM properties Date: Tue, 16 Jun 2020 15:52:27 +0200 Message-Id: <20200616135238.3001888-63-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The address-bits and page-size properties that are currently used are not valid properties according to the bindings. Use the address-width and pagesize properties instead. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 4 ++-- arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 ++-- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 4 ++-- arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 4 ++-- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 8 ++++---- 5 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 4a7a022acabb..a70fd4e86840 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -222,8 +222,8 @@ eeprom@57 { reg = <0x57>; vcc-supply = <&vdd_1v8>; - address-bits = <8>; - page-size = <8>; + address-width = <8>; + pagesize = <8>; size = <256>; read-only; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index b5568b9ff181..654c55ed048b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -174,8 +174,8 @@ eeprom@50 { reg = <0x50>; vcc-supply = <&vdd_1v8>; - address-bits = <8>; - page-size = <8>; + address-width = <8>; + pagesize = <8>; size = <256>; read-only; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index d818fac3070c..6a4b50aaa25d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -274,8 +274,8 @@ eeprom@50 { reg = <0x50>; vcc-supply = <&vdd_1v8>; - address-bits = <8>; - page-size = <8>; + address-width = <8>; + pagesize = <8>; size = <256>; read-only; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index eb46f745d75f..0c0d51c23975 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -84,8 +84,8 @@ eeprom@57 { reg = <0x57>; vcc-supply = <&vdd_1v8>; - address-bits = <8>; - page-size = <8>; + address-width = <8>; + pagesize = <8>; size = <256>; read-only; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index ac17f5485bf8..beec6aab2157 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -116,8 +116,8 @@ eeprom@50 { reg = <0x50>; vcc-supply = <&vdd_1v8>; - address-bits = <8>; - page-size = <8>; + address-width = <8>; + pagesize = <8>; size = <256>; read-only; }; @@ -127,8 +127,8 @@ eeprom@57 { reg = <0x57>; vcc-supply = <&vdd_1v8>; - address-bits = <8>; - page-size = <8>; + address-width = <8>; + pagesize = <8>; size = <256>; read-only; }; From patchwork Tue Jun 16 13:52:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310415 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; 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Tue, 16 Jun 2020 06:55:16 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id f9sm28545072wre.65.2020.06.16.06.55.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:55:16 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 63/73] arm64: tegra: Remove XUSB pad controller interrupt from XUSB node Date: Tue, 16 Jun 2020 15:52:28 +0200 Message-Id: <20200616135238.3001888-64-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The XUSB controller doesn't need the XUSB pad controller's interrupt, so remove it. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 3 +-- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index b4150d8cccf5..1cd369ac48d2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -568,8 +568,7 @@ usb@3530000 { <0x0 0x03538000 0x0 0x1000>; reg-names = "hcd", "fpci"; interrupts = , - , - ; + ; clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, <&bpmp TEGRA186_CLK_XUSB_FALCON>, <&bpmp TEGRA186_CLK_XUSB_SS>, diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index bf696ada856c..4d6f2127dd4a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -688,8 +688,7 @@ usb@3610000 { reg-names = "hcd", "fpci"; interrupts = , - , - ; + ; clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, <&bpmp TEGRA194_CLK_XUSB_FALCON>, From patchwork Tue Jun 16 13:52:29 2020 Content-Type: text/plain; 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Tue, 16 Jun 2020 06:55:17 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 64/73] arm64: tegra: Fix {clock,reset}-names ordering Date: Tue, 16 Jun 2020 15:52:29 +0200 Message-Id: <20200616135238.3001888-65-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding It's very difficult to describe string lists that can be in arbitrary order using the json-schema based validation tooling. Since the OS is not going to care either way, take the easy way out and reorder these entries to match the order defined in the bindings. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 1cd369ac48d2..a73050ec61a7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -799,15 +799,15 @@ pcie@10003000 { <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ - clocks = <&bpmp TEGRA186_CLK_AFI>, - <&bpmp TEGRA186_CLK_PCIE>, + clocks = <&bpmp TEGRA186_CLK_PCIE>, + <&bpmp TEGRA186_CLK_AFI>, <&bpmp TEGRA186_CLK_PLLE>; - clock-names = "afi", "pex", "pll_e"; + clock-names = "pex", "afi", "pll_e"; - resets = <&bpmp TEGRA186_RESET_AFI>, - <&bpmp TEGRA186_RESET_PCIE>, + resets = <&bpmp TEGRA186_RESET_PCIE>, + <&bpmp TEGRA186_RESET_AFI>, <&bpmp TEGRA186_RESET_PCIEXCLK>; - reset-names = "afi", "pex", "pcie_x"; + reset-names = "pex", "afi", "pcie_x"; interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; From patchwork Tue Jun 16 13:52:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310417 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=txZgLaXF; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV8L0vwYz9sTG for ; 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Tue, 16 Jun 2020 06:55:20 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 65/73] arm64: tegra: Do not mark display hub as simple bus Date: Tue, 16 Jun 2020 15:52:30 +0200 Message-Id: <20200616135238.3001888-66-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The display hub on Tegra186 and Tegra194 is not a simple bus, so drop the corresponding compatible string. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index a73050ec61a7..3a41203deba2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -990,7 +990,7 @@ i2c-bus { }; display-hub@15200000 { - compatible = "nvidia,tegra186-display", "simple-bus"; + compatible = "nvidia,tegra186-display"; reg = <0x15200000 0x00040000>; resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 4d6f2127dd4a..3089ebecfbef 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1055,7 +1055,7 @@ host1x@13e00000 { interconnect-names = "dma-mem"; display-hub@15200000 { - compatible = "nvidia,tegra194-display", "simple-bus"; + compatible = "nvidia,tegra194-display"; reg = <0x15200000 0x00040000>; resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, From patchwork Tue Jun 16 13:52:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310418 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=UIL/3uQu; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV8L5Y2Gz9sTH for ; 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Tue, 16 Jun 2020 06:55:22 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 66/73] arm64: tegra: Use standard names for SRAM nodes Date: Tue, 16 Jun 2020 15:52:31 +0200 Message-Id: <20200616135238.3001888-67-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding SRAM nodes should be named sram@ to match the bindings. While at it, also remove the unneeded, custom compatible string for SRAM partition nodes. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 8 +++----- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 8 +++----- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 3a41203deba2..d92eea1ddac7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1262,22 +1262,20 @@ gpu@17000000 { interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; }; - sysram@30000000 { + sram@30000000 { compatible = "nvidia,tegra186-sysram", "mmio-sram"; reg = <0x0 0x30000000 0x0 0x50000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x30000000 0x50000>; - cpu_bpmp_tx: shmem@4e000 { - compatible = "nvidia,tegra186-bpmp-shmem"; + cpu_bpmp_tx: sram@4e000 { reg = <0x4e000 0x1000>; label = "cpu-bpmp-tx"; pool; }; - cpu_bpmp_rx: shmem@4f000 { - compatible = "nvidia,tegra186-bpmp-shmem"; + cpu_bpmp_rx: sram@4f000 { reg = <0x4f000 0x1000>; label = "cpu-bpmp-rx"; pool; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 3089ebecfbef..2ecb80e1b09d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1803,22 +1803,20 @@ pcie_ep@141a0000 { nvidia,aspm-l0s-entrance-latency-us = <3>; }; - sysram@40000000 { + sram@40000000 { compatible = "nvidia,tegra194-sysram", "mmio-sram"; reg = <0x0 0x40000000 0x0 0x50000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x40000000 0x50000>; - cpu_bpmp_tx: shmem@4e000 { - compatible = "nvidia,tegra194-bpmp-shmem"; + cpu_bpmp_tx: sram@4e000 { reg = <0x4e000 0x1000>; label = "cpu-bpmp-tx"; pool; }; - cpu_bpmp_rx: shmem@4f000 { - compatible = "nvidia,tegra194-bpmp-shmem"; + cpu_bpmp_rx: sram@4f000 { reg = <0x4f000 0x1000>; label = "cpu-bpmp-rx"; pool; From patchwork Tue Jun 16 13:52:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310419 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Tue, 16 Jun 2020 06:55:26 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id u3sm4187727wmg.38.2020.06.16.06.55.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:55:25 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 67/73] arm64: tegra: Remove unused interrupts from Tegra194 AON GPIO Date: Tue, 16 Jun 2020 15:52:32 +0200 Message-Id: <20200616135238.3001888-68-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The AON GPIO controller on Tegra194 currently only uses a single interrupt, so remove the extra ones. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 2ecb80e1b09d..e0aa6c74073a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -999,10 +999,7 @@ gpio_aon: gpio@c2f0000 { reg-names = "security", "gpio"; reg = <0xc2f0000 0x1000>, <0xc2f1000 0x1000>; - interrupts = , - , - , - ; + interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; From patchwork Tue Jun 16 13:52:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310420 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=LxamS/MK; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV8N3HW5z9sTK for ; Tue, 16 Jun 2020 23:55:32 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728885AbgFPNzb (ORCPT ); Tue, 16 Jun 2020 09:55:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728557AbgFPNza (ORCPT ); Tue, 16 Jun 2020 09:55:30 -0400 Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 51D4FC061573 for ; Tue, 16 Jun 2020 06:55:29 -0700 (PDT) Received: by mail-wm1-x343.google.com with SMTP id l26so2973894wme.3 for ; Tue, 16 Jun 2020 06:55:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=m+Oy5TCjklnJXJnTpsKQEAS9YPNmRw7/jZUo1uh4cXY=; b=LxamS/MKqnBLmNYe28YdSGsQ2D8LWMfmQDzPPPrawRoo0jK+j9uVCTVLqs3pRS/lLV fPfBQTV4wbWNspZy2uIfTzJLjaPx88EiNXMYxUhzlj94j4q3Ua6rTaCdigGBt1p3vAED EsLzN8r3e7G/PmEt1aeNOjqoo63QtrqHRoEJ0NbE9VuZ9zjOQVvGH8EU6yxURx12AARe YTMteZDPpvpcq2c7rfr4RUc+BoMcVO73enc2RF6ANHiWUarzlVFt8MkXya37iTOScJgU aN4QX72MwfXU/uMzvNOrO9+IUZWhYtoLMPNs8DIZ0zePW1mYaDGMcvDLoBpMbhImHzH+ i1OQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=m+Oy5TCjklnJXJnTpsKQEAS9YPNmRw7/jZUo1uh4cXY=; b=YDgg4+f4FfQj9iW33suHQJbmd0ohNGzMgiJRSfPsCZoiz8H2KnxbPdf7baiSb03FAj 20qcGJtRiB3xdCQhaKbsAOCYEbzTRYCJ6AsJlRL8rTcejDsjjwC5z758QmTkKNqsCeZ4 GAweeLGqmREWqhgFm+a27nTFz0OQRcQ+02YQhLh3eHXkRM/J4LpVPSfDHRh3j1IxAaeM 0/6e/aOtWQ5Tynp1K8IwTlN6ou8P8zFsmTyiZEVkYy9RaW2o11P/9nW/AwaDEyArP2i+ 7yz0jiiymSWjDXIABpZailJ2D+U4bHaM7zXoMQKv2xUX9lBay+00Mkr+BGZpFTtKA+1Z s6EQ== X-Gm-Message-State: AOAM530Aq/jBm/5aZo62uKczG6MQbZUclK3kqqM/MIIiIwtQhPxfA8Ap rygCN15enThxfb8lG1R8w3g= X-Google-Smtp-Source: ABdhPJw3jkTqJ+lgKZ6qIB5biG0YKqBZg1et2dqIrNIfkE5GKlgmyf7OxfU5uJnFQ/yiM2iWbEIe1w== X-Received: by 2002:a7b:c10c:: with SMTP id w12mr3164846wmi.132.1592315728126; Tue, 16 Jun 2020 06:55:28 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id w14sm1974388wrt.55.2020.06.16.06.55.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:55:27 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 68/73] arm64: tegra: Fix indentation in Tegra194 device tree Date: Tue, 16 Jun 2020 15:52:33 +0200 Message-Id: <20200616135238.3001888-69-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Properly indent subsequent lines so that they align with the first line. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index e0aa6c74073a..307f999edbf9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1669,7 +1669,7 @@ pcie@141a0000 { pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, - <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; + <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; clock-names = "core", "core_m"; resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, From patchwork Tue Jun 16 13:52:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310422 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=NlQD9Hds; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49mV8b0BKCz9sTZ for ; Tue, 16 Jun 2020 23:55:43 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729040AbgFPNzh (ORCPT ); Tue, 16 Jun 2020 09:55:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729001AbgFPNzd (ORCPT ); Tue, 16 Jun 2020 09:55:33 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92C8DC061573 for ; Tue, 16 Jun 2020 06:55:31 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id e1so20912196wrt.5 for ; Tue, 16 Jun 2020 06:55:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Bn1siE7j5QgVJ2P/0HXryBjQl66K/xnjGvXsbTL+kqQ=; b=NlQD9HdswI3+kQ0ylBD+r/kCIVPm0kyt8CDC9V5C+kEtu3MKMuyiLKNAQlkaxW3lyw z+3zO4MC3JUBUkirt2pbgdz/gMbbqJPOTPjZ4H1ALdXWQEzRXhG5TEal9HHNf24S4Hd9 V/8QwDkws7bw0J9Pdti3SZqpgqyMXuE7QjIuNa5reGYRX3raaHucCeLd0snInrK5rVTC lP5NUp3GoNVAQH3iJQ7K/FTPDnMeEwrrzHQt71NCoAIPdp93WrZMLGYkK97D0C4MJmln s9RVho2hrwEQ+LM5ibDu5vILl8sHkzin/rVoMYmFfhPVGadWu2n4q4L7hxwC8dcX9q7J 8qSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Bn1siE7j5QgVJ2P/0HXryBjQl66K/xnjGvXsbTL+kqQ=; b=MIV8mVgezctdBMOKRNKjnazxGyNB2AQHLedkUEAU6ecDSQrnZLstPutl1pZmalTwWP +q6kMCjXV2Va/7S7feX0m47S/TGYOe/GejAydYn2hEwO5xqkvXZACVqbcsMGYrPrPXR4 OpgKLK/ilXqV7aH3S9aa43g3wRvcWLFZRBGjIIIphKrPskQyblDGZGiFxsoqFWJaqPsA Kyw5LG6E/dQhRpoOkBJODMG6U+USN8GtesQqq3srIZGtDusaKCOjeeUHb99sdm7H/JPs F4leYHjZwgRncHqmr8JkryDmHfVGXr3Urm6HDvtEWxjx0pHBIRXaE4gEqx1J+BJfAuMm 64NQ== X-Gm-Message-State: AOAM531HbHdN5LzP6Rw9ryGr/mz4i/RcyViS+xFLwgNXXslPHqRnDuRv ZVay2S69r80gg6qT6eaNueUfNpNf X-Google-Smtp-Source: ABdhPJxCMHFkReSqDHQAMRCTmOevakodwkUPBhsFcNJTNyIT7KpTWMGsc2hvmCJ4YGTlnfQsXAWsrQ== X-Received: by 2002:a05:6000:104f:: with SMTP id c15mr3178128wrx.391.1592315730029; Tue, 16 Jun 2020 06:55:30 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id a16sm29260858wrx.8.2020.06.16.06.55.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:55:29 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 69/73] arm64: tegra: Rename agic -> interrupt-controller Date: Tue, 16 Jun 2020 15:52:34 +0200 Message-Id: <20200616135238.3001888-70-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Device tree nodes for interrupt controllers should be named "interrupt- controller", so rename the AGIC accordingly. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 0c0d51c23975..0ccb62606bef 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -119,7 +119,7 @@ dma@702e2000 { status = "okay"; }; - agic@702f9000 { + interrupt-controller@702f9000 { status = "okay"; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index cc0d7b4a5834..f7840e5e069a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1717,7 +1717,7 @@ dma@702e2000 { status = "okay"; }; - agic@702f9000 { + interrupt-controller@702f9000 { status = "okay"; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 02a02ed1b264..c265211f8a84 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1355,7 +1355,7 @@ adma: dma@702e2000 { status = "disabled"; }; - agic: agic@702f9000 { + agic: interrupt-controller@702f9000 { compatible = "nvidia,tegra210-agic"; #interrupt-cells = <3>; interrupt-controller; From patchwork Tue Jun 16 13:52:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310424 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; 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Tue, 16 Jun 2020 06:55:32 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id w10sm29435711wrp.16.2020.06.16.06.55.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:55:31 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 70/73] arm64: tegra: Various fixes for PMICs Date: Tue, 16 Jun 2020 15:52:35 +0200 Message-Id: <20200616135238.3001888-71-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Standardize on "pmic" as the node name for the PMIC on Tegra210 systems and use consistent names for pinmux and GPIO hog nodes. Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 31 +++++++++---------- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 14 ++++----- 2 files changed, 22 insertions(+), 23 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index 1acb9bb6c7df..41beab626d95 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -1328,7 +1328,7 @@ i2c@7000d000 { status = "okay"; clock-frequency = <400000>; - max77620: max77620@3c { + pmic: pmic@3c { compatible = "maxim,max77620"; reg = <0x3c>; interrupts = ; @@ -1343,12 +1343,12 @@ max77620: max77620@3c { pinctrl-0 = <&max77620_default>; max77620_default: pinmux@0 { - pin_gpio0 { + gpio0 { pins = "gpio0"; function = "gpio"; }; - pin_gpio1 { + gpio1 { pins = "gpio1"; function = "fps-out"; drive-push-pull = <1>; @@ -1357,34 +1357,33 @@ pin_gpio1 { maxim,active-fps-power-down-slot = <0>; }; - pin_gpio2_3 { - pins = "gpio2", "gpio3"; + gpio2 { + pins = "gpio2"; function = "fps-out"; drive-open-drain = <1>; maxim,active-fps-source = ; }; - pin_gpio4 { + gpio3 { + pins = "gpio3"; + function = "fps-out"; + drive-open-drain = <1>; + maxim,active-fps-source = ; + }; + + gpio4 { pins = "gpio4"; function = "32k-out1"; }; - pin_gpio5_6_7 { + gpio5_6_7 { pins = "gpio5", "gpio6", "gpio7"; function = "gpio"; drive-push-pull = <1>; }; - - pin_gpio2 { - maxim,active-fps-source = ; - }; - - pin_gpio3 { - maxim,active-fps-source = ; - }; }; - spmic-default-output-high { + gpio@0 { gpio-hog; output-high; gpios = <2 GPIO_ACTIVE_HIGH>, diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index f7840e5e069a..a946c5c31102 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1354,11 +1354,11 @@ max77621_cpu: max77621@1b { maxim,enable-active-discharge; maxim,enable-bias-control; maxim,enable-etr; - maxim,enable-gpio = <&max77620 5 0>; + maxim,enable-gpio = <&pmic 5 0>; maxim,externally-enable; }; - max77620: max77620@3c { + pmic: pmic@3c { compatible = "maxim,max77620"; reg = <0x3c>; interrupts = ; @@ -1372,8 +1372,8 @@ max77620: max77620@3c { pinctrl-names = "default"; pinctrl-0 = <&max77620_default>; - max77620_default: pinmux@0 { - pin_gpio { + max77620_default: pinmux { + gpio0_1_2_7 { pins = "gpio0", "gpio1", "gpio2", "gpio7"; function = "gpio"; }; @@ -1383,7 +1383,7 @@ pin_gpio { * sequence, So it must be sequenced up (automatically * set by OTP) and down properly. */ - pin_gpio3 { + gpio3 { pins = "gpio3"; function = "fps-out"; drive-open-drain = <1>; @@ -1392,13 +1392,13 @@ pin_gpio3 { maxim,active-fps-power-down-slot = <2>; }; - pin_gpio5_6 { + gpio5_6 { pins = "gpio5", "gpio6"; function = "gpio"; drive-push-pull = <1>; }; - pin_32k { + gpio4 { pins = "gpio4"; function = "32k-out1"; }; From patchwork Tue Jun 16 13:52:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310423 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Tue, 16 Jun 2020 06:55:34 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id g82sm4221734wmf.1.2020.06.16.06.55.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:55:33 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 71/73] arm64: tegra: Sort nodes by unit-address on Jetson Nano Date: Tue, 16 Jun 2020 15:52:36 +0200 Message-Id: <20200616135238.3001888-72-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Move the usb@700d0000 node to the correct place in the device tree, ordered by unit-address. Signed-off-by: Thierry Reding --- .../boot/dts/nvidia/tegra210-p3450-0000.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index beec6aab2157..4eb51e5eef3a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -545,14 +545,6 @@ mmc@700b0000 { vmmc-supply = <&vdd_3v3_sd>; }; - usb@700d0000 { - status = "okay"; - phys = <µ_b>; - phy-names = "usb2-0"; - avddio-usb-supply = <&vdd_3v3_sys>; - hvdd-usb-supply = <&vdd_1v8>; - }; - mmc@700b0400 { status = "okay"; bus-width = <4>; @@ -566,6 +558,14 @@ mmc@700b0400 { wakeup-source; }; + usb@700d0000 { + status = "okay"; + phys = <µ_b>; + phy-names = "usb2-0"; + avddio-usb-supply = <&vdd_3v3_sys>; + hvdd-usb-supply = <&vdd_1v8>; + }; + clk32k_in: clock@0 { compatible = "fixed-clock"; clock-frequency = <32768>; From patchwork Tue Jun 16 13:52:37 2020 Content-Type: text/plain; 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Tue, 16 Jun 2020 06:55:35 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 72/73] arm64: tegra: Rename cbb@0 to bus@0 on Tegra194 Date: Tue, 16 Jun 2020 15:52:37 +0200 Message-Id: <20200616135238.3001888-73-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The control backbone is a simple-bus and hence its device tree node should be named "bus@" according to the bindings. Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 22 +++++++++---------- .../boot/dts/nvidia/tegra194-p2972-0000.dts | 10 ++++----- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +- 3 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 6f2c0754c870..cefbd0000357 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -8,18 +8,18 @@ / { compatible = "nvidia,p2888", "nvidia,tegra194"; aliases { - ethernet0 = "/cbb@0/ethernet@2490000"; - mmc0 = "/cbb@0/mmc@3460000"; - mmc1 = "/cbb@0/mmc@3400000"; + ethernet0 = "/bus@0/ethernet@2490000"; + mmc0 = "/bus@0/mmc@3460000"; + mmc1 = "/bus@0/mmc@3400000"; serial0 = &tcu; i2c0 = "/bpmp/i2c"; - i2c1 = "/cbb@0/i2c@3160000"; - i2c2 = "/cbb@0/i2c@c240000"; - i2c3 = "/cbb@0/i2c@3180000"; - i2c4 = "/cbb@0/i2c@3190000"; - i2c5 = "/cbb@0/i2c@31c0000"; - i2c6 = "/cbb@0/i2c@c250000"; - i2c7 = "/cbb@0/i2c@31e0000"; + i2c1 = "/bus@0/i2c@3160000"; + i2c2 = "/bus@0/i2c@c240000"; + i2c3 = "/bus@0/i2c@3180000"; + i2c4 = "/bus@0/i2c@3190000"; + i2c5 = "/bus@0/i2c@31c0000"; + i2c6 = "/bus@0/i2c@c250000"; + i2c7 = "/bus@0/i2c@31e0000"; }; chosen { @@ -27,7 +27,7 @@ chosen { stdout-path = "serial0:115200n8"; }; - cbb@0 { + bus@0 { ethernet@2490000 { status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 0f9868b6fd6b..90b6ea5467fa 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -10,7 +10,7 @@ / { model = "NVIDIA Jetson AGX Xavier Developer Kit"; compatible = "nvidia,p2972-0000", "nvidia,tegra194"; - cbb@0 { + bus@0 { aconnect@2900000 { status = "okay"; @@ -93,10 +93,10 @@ usb3-3 { usb@3610000 { status = "okay"; - phys = <&{/cbb@0/padctl@3520000/pads/usb2/lanes/usb2-1}>, - <&{/cbb@0/padctl@3520000/pads/usb2/lanes/usb2-3}>, - <&{/cbb@0/padctl@3520000/pads/usb3/lanes/usb3-0}>, - <&{/cbb@0/padctl@3520000/pads/usb3/lanes/usb3-3}>; + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-3}>; phy-names = "usb2-1", "usb2-3", "usb3-0", "usb3-3"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 307f999edbf9..ea629dae6880 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -16,7 +16,7 @@ / { #size-cells = <2>; /* control backbone */ - cbb@0 { + bus@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; From patchwork Tue Jun 16 13:52:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1310426 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; 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Tue, 16 Jun 2020 06:55:38 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id a1sm4008540wmj.29.2020.06.16.06.55.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2020 06:55:37 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 73/73] arm64: tegra: Fix order of XUSB controller clocks Date: Tue, 16 Jun 2020 15:52:38 +0200 Message-Id: <20200616135238.3001888-74-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200616135238.3001888-1-thierry.reding@gmail.com> References: <20200616135238.3001888-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding This is purely to make the json-schema validation tools happy because they cannot deal with string arrays that may be in arbitrary order. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index c265211f8a84..b9c6ba707ef9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -997,8 +997,8 @@ usb@70090000 { <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, <&tegra_car TEGRA210_CLK_XUSB_SS>, - <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, <&tegra_car TEGRA210_CLK_PLL_U_480M>, @@ -1006,7 +1006,7 @@ usb@70090000 { <&tegra_car TEGRA210_CLK_PLL_E>; clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src", "xusb_ss", - "xusb_ss_div2", "xusb_ss_src", + "xusb_ss_src", "xusb_ss_div2", "xusb_hs_src", "xusb_fs_src", "pll_u_480m", "clk_m", "pll_e"; resets = <&tegra_car 89>, <&tegra_car 156>,