From patchwork Wed Dec 13 19:05:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 848182 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yxmNl1s6sz9sBZ for ; Thu, 14 Dec 2017 06:05:27 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753818AbdLMTFZ (ORCPT ); Wed, 13 Dec 2017 14:05:25 -0500 Received: from andre.telenet-ops.be ([195.130.132.53]:56038 "EHLO andre.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753803AbdLMTFX (ORCPT ); Wed, 13 Dec 2017 14:05:23 -0500 Received: from ayla.of.borg ([84.195.106.246]) by andre.telenet-ops.be with bizsmtp id lX5M1w00X5JzmfG01X5Mxm; Wed, 13 Dec 2017 20:05:21 +0100 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.86_2) (envelope-from ) id 1ePCLJ-0006m3-Ca; Wed, 13 Dec 2017 20:05:21 +0100 Received: from geert by ramsan with local (Exim 4.86_2) (envelope-from ) id 1ePCLJ-0002mA-7i; Wed, 13 Dec 2017 20:05:21 +0100 From: Geert Uytterhoeven To: Mark Brown , Rob Herring , Mark Rutland Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 2/4] spi: sh-msiof: Extend support to 3 native chip selects Date: Wed, 13 Dec 2017 20:05:11 +0100 Message-Id: <1513191913-10612-3-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513191913-10612-1-git-send-email-geert+renesas@glider.be> References: <1513191913-10612-1-git-send-email-geert+renesas@glider.be> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Currently only the MSIOF_SYNC signal can be used as a native chip select. Extend support to up to 3 native chipselects using the MSIOF_SS1 and MSIOF_SS2 signals. Inspired by a patch in the BSP by Hiromitsu Yamasaki. Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/spi/sh-msiof.txt | 6 +++++- drivers/spi/spi-sh-msiof.c | 18 +++++++++++++----- 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt index bdd83959019c7883..bc8c16a6cfc82685 100644 --- a/Documentation/devicetree/bindings/spi/sh-msiof.txt +++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt @@ -36,7 +36,11 @@ Required properties: Optional properties: - clocks : Must contain a reference to the functional clock. -- num-cs : Total number of chip-selects (default is 1) +- num-cs : Total number of chip selects (default is 1). + Up to 3 native chip selects are supported: + 0: MSIOF_SYNC + 1: MSIOF_SS1 + 2: MSIOF_SS2 - dmas : Must contain a list of two references to DMA specifiers, one for transmission, and one for reception. diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 2704abb11ea41fd0..9bdc292aa050cb16 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -60,6 +60,8 @@ struct sh_msiof_spi_priv { bool slave_aborted; }; +#define MAX_SS 3 /* Maximum number of native chip selects */ + #define TMDR1 0x00 /* Transmit Mode Register 1 */ #define TMDR2 0x04 /* Transmit Mode Register 2 */ #define TMDR3 0x08 /* Transmit Mode Register 3 */ @@ -93,6 +95,8 @@ struct sh_msiof_spi_priv { #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */ /* TMDR1 */ #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */ +#define TMDR1_SYNCCH_MASK 0xc000000 /* Synchronization Signal Channel Select */ +#define TMDR1_SYNCCH_SHIFT 26 /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */ /* TMDR2 and RMDR2 */ #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */ @@ -326,7 +330,7 @@ static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p) return val; } -static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, +static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss, u32 cpol, u32 cpha, u32 tx_hi_z, u32 lsb_first, u32 cs_high) { @@ -344,10 +348,13 @@ static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, tmp |= !cs_high << MDR1_SYNCAC_SHIFT; tmp |= lsb_first << MDR1_BITLSB_SHIFT; tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p); - if (spi_controller_is_slave(p->master)) + if (spi_controller_is_slave(p->master)) { sh_msiof_write(p, TMDR1, tmp | TMDR1_PCON); - else - sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON); + } else { + sh_msiof_write(p, TMDR1, + tmp | MDR1_TRMD | TMDR1_PCON | + (ss < MAX_SS ? ss : 0) << TMDR1_SYNCCH_SHIFT); + } if (p->master->flags & SPI_MASTER_MUST_TX) { /* These bits are reserved if RX needs TX */ tmp &= ~0x0000ffff; @@ -575,7 +582,8 @@ static int sh_msiof_prepare_message(struct spi_master *master, const struct spi_device *spi = msg->spi; /* Configure pins before asserting CS */ - sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), + sh_msiof_spi_set_pin_regs(p, spi->chip_select, + !!(spi->mode & SPI_CPOL), !!(spi->mode & SPI_CPHA), !!(spi->mode & SPI_3WIRE), !!(spi->mode & SPI_LSB_FIRST), From patchwork Wed Dec 13 19:05:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 848183 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yxmNm4sjqz9t3F for ; Thu, 14 Dec 2017 06:05:28 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753441AbdLMTF1 (ORCPT ); Wed, 13 Dec 2017 14:05:27 -0500 Received: from baptiste.telenet-ops.be ([195.130.132.51]:35906 "EHLO baptiste.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753779AbdLMTFX (ORCPT ); Wed, 13 Dec 2017 14:05:23 -0500 Received: from ayla.of.borg ([84.195.106.246]) by baptiste.telenet-ops.be with bizsmtp id lX5M1w00S5JzmfG01X5MXh; Wed, 13 Dec 2017 20:05:21 +0100 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.86_2) (envelope-from ) id 1ePCLJ-0006m4-Cb; Wed, 13 Dec 2017 20:05:21 +0100 Received: from geert by ramsan with local (Exim 4.86_2) (envelope-from ) id 1ePCLJ-0002mJ-9E; Wed, 13 Dec 2017 20:05:21 +0100 From: Geert Uytterhoeven To: Mark Brown , Rob Herring , Mark Rutland Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 4/4] spi: sh-msiof: Document hardware limitations related to chip selects Date: Wed, 13 Dec 2017 20:05:13 +0100 Message-Id: <1513191913-10612-5-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513191913-10612-1-git-send-email-geert+renesas@glider.be> References: <1513191913-10612-1-git-send-email-geert+renesas@glider.be> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Guide users to maintain the proper balance between native and GPIO chip selects. Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/spi/sh-msiof.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt index bc8c16a6cfc82685..80710f0f04489174 100644 --- a/Documentation/devicetree/bindings/spi/sh-msiof.txt +++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt @@ -41,6 +41,16 @@ Optional properties: 0: MSIOF_SYNC 1: MSIOF_SS1 2: MSIOF_SS2 + Hardware limitations related to chip selects: + - Native chip selects are always deasserted in + between transfers that are part of the same + message. Use cs-gpios to work around this. + - All slaves using native chip selects must use the + same spi-cs-high configuration. Use cs-gpios to + work around this. + - When using GPIO chip selects, at least one native + chip select must be left unused, as it will be + driven anyway. - dmas : Must contain a list of two references to DMA specifiers, one for transmission, and one for reception.