From patchwork Wed Dec 13 18:30:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timur Tabi X-Patchwork-Id: 848113 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=codeaurora.org header.i=@codeaurora.org header.b="bh2NPBq0"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="gE/b2/dq"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yxlcP3b2dz9sBZ for ; Thu, 14 Dec 2017 05:30:28 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753011AbdLMSa0 (ORCPT ); Wed, 13 Dec 2017 13:30:26 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:58944 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753323AbdLMSaZ (ORCPT ); Wed, 13 Dec 2017 13:30:25 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 1828D60A65; Wed, 13 Dec 2017 18:30:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1513189825; bh=H+mGa3JwGNx67kvs6oflVGit4dtVbFq6OhP342EPczA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bh2NPBq0KX+kwSqjw+00pEDKiidLm3Jg0xezyqgzz021P6q7kCwbx15Zg3V1SQG2d uVdGR83rs2G6THhaUOEjtuFl4W6kYQxz33EjjR0jmbbtPgQ5osDUtsv7vMhS7Xgv6w jRY7AWzgLcwfrAja//R5bTDIATnk5EbbgyC0TwrQ= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED, T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from timur-ubuntu.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: timur@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 799AF607E1; Wed, 13 Dec 2017 18:30:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1513189824; bh=H+mGa3JwGNx67kvs6oflVGit4dtVbFq6OhP342EPczA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gE/b2/dqWfhjguBnaRVpgcGXcJO1KCoDPoa0EYktdPQOONaY2oa46WSQsjWttRthQ 8emJSGYbl9F7nhLOxiL04UcyGbtuODOVtsaxSxnmzB0tpF1Lr0XmpyDj86/VYkCgaD f0HLbFda8EMBtPBHg24o4SYO++AaXayvZTC47l9Q= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 799AF607E1 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=timur@codeaurora.org From: Timur Tabi To: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij , Andy Shevchenko , Mika Westerberg , thierry.reding@gmail.com, Stephen Boyd , david.brown@linaro.org, andy.gross@linaro.org, Bjorn Andersson , Varadarajan Narayanan , Archit Taneja Cc: timur@codeaurora.org Subject: [PATCH 1/3] [v2] Revert "gpio: set up initial state from .get_direction()" Date: Wed, 13 Dec 2017 12:30:16 -0600 Message-Id: <1513189818-7384-2-git-send-email-timur@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1513189818-7384-1-git-send-email-timur@codeaurora.org> References: <1513189818-7384-1-git-send-email-timur@codeaurora.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This reverts commit 72d3200061776264941be1b5a9bb8e926b3b30a5. We cannot blindly query the direction of all GPIOs when the pins are first registered. The get_direction callback normally triggers a read/write to hardware, but we shouldn't be touching the hardware for an individual GPIO until after it's been properly claimed. Signed-off-by: Timur Tabi Reviewed-by: Stephen Boyd --- drivers/gpio/gpiolib.c | 31 +++++++------------------------ 1 file changed, 7 insertions(+), 24 deletions(-) diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 641a5eb552cb..168dd831551d 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -1207,31 +1207,14 @@ int gpiochip_add_data_with_key(struct gpio_chip *chip, void *data, struct gpio_desc *desc = &gdev->descs[i]; desc->gdev = gdev; - /* - * REVISIT: most hardware initializes GPIOs as inputs - * (often with pullups enabled) so power usage is - * minimized. Linux code should set the gpio direction - * first thing; but until it does, and in case - * chip->get_direction is not set, we may expose the - * wrong direction in sysfs. - */ - - if (chip->get_direction) { - /* - * If we have .get_direction, set up the initial - * direction flag from the hardware. - */ - int dir = chip->get_direction(chip, i); - if (!dir) - set_bit(FLAG_IS_OUT, &desc->flags); - } else if (!chip->direction_input) { - /* - * If the chip lacks the .direction_input callback - * we logically assume all lines are outputs. - */ - set_bit(FLAG_IS_OUT, &desc->flags); - } + /* REVISIT: most hardware initializes GPIOs as inputs (often + * with pullups enabled) so power usage is minimized. Linux + * code should set the gpio direction first thing; but until + * it does, and in case chip->get_direction is not set, we may + * expose the wrong direction in sysfs. + */ + desc->flags = !chip->direction_input ? (1 << FLAG_IS_OUT) : 0; } #ifdef CONFIG_PINCTRL From patchwork Wed Dec 13 18:30:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timur Tabi X-Patchwork-Id: 848114 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=codeaurora.org header.i=@codeaurora.org header.b="dDYxr4F7"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="dDYxr4F7"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yxlcc5dbBz9t2Z for ; Thu, 14 Dec 2017 05:30:39 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753323AbdLMSa2 (ORCPT ); Wed, 13 Dec 2017 13:30:28 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:59088 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753144AbdLMSa1 (ORCPT ); Wed, 13 Dec 2017 13:30:27 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id D3ED060A9B; Wed, 13 Dec 2017 18:30:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1513189826; bh=Mlp9mB2nw9AZpcScDM+CormzMkVMYP0WF5cu4E2Abe8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dDYxr4F7AX5OBGCFkYllxni4/IeVvsvTSmhnAlZEiIaa0ia7kO4DLwnplHFnBc8SQ TTcQ1Angdm3ZVGP4+u579gtF+HM29uDgqIRObOGwEYbn7MiR/z2U7akVxmKmU6Mri+ DlnFOGNSfEsLQOn01HsmP4BiHhPIRyMUTDeM/cUo= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED, T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from timur-ubuntu.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: timur@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id D754860A60; Wed, 13 Dec 2017 18:30:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1513189826; bh=Mlp9mB2nw9AZpcScDM+CormzMkVMYP0WF5cu4E2Abe8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dDYxr4F7AX5OBGCFkYllxni4/IeVvsvTSmhnAlZEiIaa0ia7kO4DLwnplHFnBc8SQ TTcQ1Angdm3ZVGP4+u579gtF+HM29uDgqIRObOGwEYbn7MiR/z2U7akVxmKmU6Mri+ DlnFOGNSfEsLQOn01HsmP4BiHhPIRyMUTDeM/cUo= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D754860A60 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=timur@codeaurora.org From: Timur Tabi To: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij , Andy Shevchenko , Mika Westerberg , thierry.reding@gmail.com, Stephen Boyd , david.brown@linaro.org, andy.gross@linaro.org, Bjorn Andersson , Varadarajan Narayanan , Archit Taneja Cc: timur@codeaurora.org Subject: [PATCH 2/3] [v8] pinctrl: qcom: disable GPIO groups with no pins Date: Wed, 13 Dec 2017 12:30:17 -0600 Message-Id: <1513189818-7384-3-git-send-email-timur@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1513189818-7384-1-git-send-email-timur@codeaurora.org> References: <1513189818-7384-1-git-send-email-timur@codeaurora.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org pinctrl-msm only accepts an array of GPIOs from 0 to n-1, and it expects each group to support have only one pin (npins == 1). We can support "sparse" GPIO maps if we allow for some groups to have zero pins (npins == 0). These pins are "hidden" from the rest of the driver and gpiolib. Access to unavailable GPIOs is blocked via a request callback. If the requested GPIO is unavailable, -EACCES is returned, which prevents further access to that GPIO. Signed-off-by: Timur Tabi Reviewed-by: Stephen Boyd --- drivers/pinctrl/qcom/pinctrl-msm.c | 28 +++++++++++++++++++++++----- 1 file changed, 23 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 7a960590ecaa..d45b4c2b5af1 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -507,6 +507,11 @@ static void msm_gpio_dbg_show_one(struct seq_file *s, }; g = &pctrl->soc->groups[offset]; + + /* If the GPIO group has no pins, then don't show it. */ + if (!g->npins) + return; + ctl_reg = readl(pctrl->regs + g->ctl_reg); is_out = !!(ctl_reg & BIT(g->oe_bit)); @@ -516,7 +521,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s, seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); seq_printf(s, " %dmA", msm_regval_to_drive(drive)); - seq_printf(s, " %s", pulls[pull]); + seq_printf(s, " %s\n", pulls[pull]); } static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) @@ -524,23 +529,36 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) unsigned gpio = chip->base; unsigned i; - for (i = 0; i < chip->ngpio; i++, gpio++) { + for (i = 0; i < chip->ngpio; i++, gpio++) msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); - seq_puts(s, "\n"); - } } #else #define msm_gpio_dbg_show NULL #endif +/* + * If the requested GPIO has no pins, then treat it as unavailable. + * Otherwise, call the standard request function. + */ +static int msm_gpio_request(struct gpio_chip *chip, unsigned int offset) +{ + struct msm_pinctrl *pctrl = gpiochip_get_data(chip); + const struct msm_pingroup *g = &pctrl->soc->groups[offset]; + + if (!g->npins) + return -EACCES; + + return gpiochip_generic_request(chip, offset); +} + static const struct gpio_chip msm_gpio_template = { .direction_input = msm_gpio_direction_input, .direction_output = msm_gpio_direction_output, .get_direction = msm_gpio_get_direction, .get = msm_gpio_get, .set = msm_gpio_set, - .request = gpiochip_generic_request, + .request = msm_gpio_request, .free = gpiochip_generic_free, .dbg_show = msm_gpio_dbg_show, }; From patchwork Wed Dec 13 18:30:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timur Tabi X-Patchwork-Id: 848115 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=codeaurora.org header.i=@codeaurora.org header.b="O0zggO4O"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="E52/QImr"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yxlcg24h9z9t3H for ; Thu, 14 Dec 2017 05:30:42 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753430AbdLMSaa (ORCPT ); Wed, 13 Dec 2017 13:30:30 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:59202 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753144AbdLMSa3 (ORCPT ); Wed, 13 Dec 2017 13:30:29 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 7E5B160AD2; Wed, 13 Dec 2017 18:30:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1513189828; bh=YXnOXFPCnLNN2fVtDv8poTyT0j93LRTNaLJYXLmpri0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=O0zggO4Ots9GyWCA9R8jW0RCKsWbuqLyCa/ePng7FsXfWp2ewm+5FRbeLjFnE4JRW NvzYZE1HQoFkL7XNT8IyKE6VcAOBdq04RUSCNHVhig1dF1yy1DYlL1PBe9qXgMuwsc h5iloloUacodVnWglFPpt8l24FbJ4BkRhX8xlFLo= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED, T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from timur-ubuntu.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: timur@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 3DBB660A97; Wed, 13 Dec 2017 18:30:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1513189827; bh=YXnOXFPCnLNN2fVtDv8poTyT0j93LRTNaLJYXLmpri0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E52/QImrICIcWh8hS4p3Y2xhLFBLxs8vrHMbsuQ3scj6Ra4kShK41xa4z2vmAXapz kegkPv2JELc/3jluKagom7OiRs9R5b++6GigJkf3yMxwDqswE5OEcC/W3uN5FqKMZF iFFHD2hNjY2cc1/NY+A+B19kRq2jh0b44VaeJAXE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 3DBB660A97 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=timur@codeaurora.org From: Timur Tabi To: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij , Andy Shevchenko , Mika Westerberg , thierry.reding@gmail.com, Stephen Boyd , david.brown@linaro.org, andy.gross@linaro.org, Bjorn Andersson , Varadarajan Narayanan , Archit Taneja Cc: timur@codeaurora.org Subject: [PATCH 3/3] [v6] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002 Date: Wed, 13 Dec 2017 12:30:18 -0600 Message-Id: <1513189818-7384-4-git-send-email-timur@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1513189818-7384-1-git-send-email-timur@codeaurora.org> References: <1513189818-7384-1-git-send-email-timur@codeaurora.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Newer versions of the firmware for the Qualcomm Datacenter Technologies QDF2400 restricts access to a subset of the GPIOs on the TLMM. To prevent older kernels from accidentally accessing the restricted GPIOs, we change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002, and introduce a new property "gpios". This property is an array of specific GPIOs that are accessible. When an older kernel boots on newer (restricted) firmware, it will fail to probe. To implement the sparse GPIO map, we register all of the GPIOs, but set the pin count for the unavailable GPIOs to zero. The pinctrl-msm driver will block those unavailable GPIOs from being accessed. To allow newer kernels to support older firmware, the driver retains support for QCOM8001. Signed-off-by: Timur Tabi Signed-off-by: Timur Tabi Signed-off-by: Stephen Boyd --- drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 134 +++++++++++++++++++++++++-------- 1 file changed, 103 insertions(+), 31 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c index bb3ce5c3e18b..deb08e08e86d 100644 --- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c +++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c @@ -38,68 +38,139 @@ /* maximum size of each gpio name (enough room for "gpioXXX" + null) */ #define NAME_SIZE 8 +enum { + QDF2XXX_V1, + QDF2XXX_V2, +}; + static int qdf2xxx_pinctrl_probe(struct platform_device *pdev) { + const struct acpi_device_id *id; struct pinctrl_pin_desc *pins; struct msm_pingroup *groups; char (*names)[NAME_SIZE]; unsigned int i; u32 num_gpios; + unsigned int avail_gpios; /* The number of GPIOs we support */ + u16 *gpios; /* An array of supported GPIOs */ int ret; /* Query the number of GPIOs from ACPI */ ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios); if (ret < 0) { - dev_warn(&pdev->dev, "missing num-gpios property\n"); + dev_err(&pdev->dev, "missing 'num-gpios' property\n"); return ret; } - if (!num_gpios || num_gpios > MAX_GPIOS) { - dev_warn(&pdev->dev, "invalid num-gpios property\n"); + dev_err(&pdev->dev, "invalid 'num-gpios' property\n"); return -ENODEV; } + /* + * The QCOM8001 HID contains only the number of GPIOs, and assumes + * that all of them are available. avail_gpios is the same as num_gpios. + * + * The QCOM8002 HID introduces the 'gpios' DSD, which lists + * specific GPIOs that the driver is allowed to access. + * + * The make the common code simpler, in both cases we create an + * array of GPIOs that are accessible. So for QCOM8001, that would + * be all of the GPIOs. + */ + id = acpi_match_device(pdev->dev.driver->acpi_match_table, &pdev->dev); + + if (id->driver_data == QDF2XXX_V1) { + avail_gpios = num_gpios; + + gpios = devm_kmalloc_array(&pdev->dev, avail_gpios, + sizeof(gpios[0]), GFP_KERNEL); + if (!gpios) + return -ENOMEM; + + for (i = 0; i < avail_gpios; i++) + gpios[i] = i; + } else { + /* The number of GPIOs in the approved list */ + ret = device_property_read_u16_array(&pdev->dev, "gpios", + NULL, 0); + if (ret < 0) { + dev_err(&pdev->dev, "missing 'gpios' property\n"); + return ret; + } + /* + * The number of available GPIOs should be non-zero, and no + * more than the total number of GPIOS. + */ + if (!ret || ret > num_gpios) { + dev_err(&pdev->dev, "invalid 'gpios' property\n"); + return -ENODEV; + } + avail_gpios = ret; + + gpios = devm_kmalloc_array(&pdev->dev, avail_gpios, + sizeof(gpios[0]), GFP_KERNEL); + if (!gpios) + return -ENOMEM; + + ret = device_property_read_u16_array(&pdev->dev, "gpios", gpios, + avail_gpios); + if (ret < 0) { + dev_err(&pdev->dev, "could not read list of GPIOs\n"); + return ret; + } + } + pins = devm_kcalloc(&pdev->dev, num_gpios, sizeof(struct pinctrl_pin_desc), GFP_KERNEL); groups = devm_kcalloc(&pdev->dev, num_gpios, sizeof(struct msm_pingroup), GFP_KERNEL); - names = devm_kcalloc(&pdev->dev, num_gpios, NAME_SIZE, GFP_KERNEL); + names = devm_kcalloc(&pdev->dev, avail_gpios, NAME_SIZE, GFP_KERNEL); if (!pins || !groups || !names) return -ENOMEM; + /* + * Initialize the array. GPIOs not listed in the 'gpios' array + * still need a number, but nothing else. + */ for (i = 0; i < num_gpios; i++) { - snprintf(names[i], NAME_SIZE, "gpio%u", i); - pins[i].number = i; - pins[i].name = names[i]; - - groups[i].npins = 1; - groups[i].name = names[i]; groups[i].pins = &pins[i].number; + } - groups[i].ctl_reg = 0x10000 * i; - groups[i].io_reg = 0x04 + 0x10000 * i; - groups[i].intr_cfg_reg = 0x08 + 0x10000 * i; - groups[i].intr_status_reg = 0x0c + 0x10000 * i; - groups[i].intr_target_reg = 0x08 + 0x10000 * i; - - groups[i].mux_bit = 2; - groups[i].pull_bit = 0; - groups[i].drv_bit = 6; - groups[i].oe_bit = 9; - groups[i].in_bit = 0; - groups[i].out_bit = 1; - groups[i].intr_enable_bit = 0; - groups[i].intr_status_bit = 0; - groups[i].intr_target_bit = 5; - groups[i].intr_target_kpss_val = 1; - groups[i].intr_raw_status_bit = 4; - groups[i].intr_polarity_bit = 1; - groups[i].intr_detection_bit = 2; - groups[i].intr_detection_width = 2; + /* Populate the entries that are meant to be exposes as GPIOs. */ + for (i = 0; i < avail_gpios; i++) { + unsigned int gpio = gpios[i]; + + groups[gpio].npins = 1; + snprintf(names[i], NAME_SIZE, "gpio%u", gpio); + pins[gpio].name = names[i]; + groups[gpio].name = names[i]; + + groups[gpio].ctl_reg = 0x10000 * gpio; + groups[gpio].io_reg = 0x04 + 0x10000 * gpio; + groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio; + groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio; + groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio; + + groups[gpio].mux_bit = 2; + groups[gpio].pull_bit = 0; + groups[gpio].drv_bit = 6; + groups[gpio].oe_bit = 9; + groups[gpio].in_bit = 0; + groups[gpio].out_bit = 1; + groups[gpio].intr_enable_bit = 0; + groups[gpio].intr_status_bit = 0; + groups[gpio].intr_target_bit = 5; + groups[gpio].intr_target_kpss_val = 1; + groups[gpio].intr_raw_status_bit = 4; + groups[gpio].intr_polarity_bit = 1; + groups[gpio].intr_detection_bit = 2; + groups[gpio].intr_detection_width = 2; } + devm_kfree(&pdev->dev, gpios); + qdf2xxx_pinctrl.pins = pins; qdf2xxx_pinctrl.groups = groups; qdf2xxx_pinctrl.npins = num_gpios; @@ -110,7 +181,8 @@ static int qdf2xxx_pinctrl_probe(struct platform_device *pdev) } static const struct acpi_device_id qdf2xxx_acpi_ids[] = { - {"QCOM8001"}, + {"QCOM8001", QDF2XXX_V1}, + {"QCOM8002", QDF2XXX_V2}, {}, }; MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);