From patchwork Thu Jun 4 12:39:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jean-Christophe Dubois X-Patchwork-Id: 1303493 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=tribudubois.net Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49d52y5yfQz9sSc for ; Thu, 4 Jun 2020 22:40:10 +1000 (AEST) Received: from localhost ([::1]:34494 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jgpAG-0008GO-Ih for incoming@patchwork.ozlabs.org; Thu, 04 Jun 2020 08:40:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52988) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jgp9b-0007ui-Ts; Thu, 04 Jun 2020 08:39:27 -0400 Received: from relay4-d.mail.gandi.net ([217.70.183.196]:51655) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jgp9a-0001gd-Ef; Thu, 04 Jun 2020 08:39:27 -0400 X-Originating-IP: 82.252.130.88 Received: from localhost.localdomain (lns-bzn-59-82-252-130-88.adsl.proxad.net [82.252.130.88]) (Authenticated sender: jcd@tribudubois.net) by relay4-d.mail.gandi.net (Postfix) with ESMTPSA id 50CDFE0017; Thu, 4 Jun 2020 12:39:23 +0000 (UTC) From: Jean-Christophe Dubois To: qemu-arm@nongnu.org Subject: [PATCH v5 1/3] hw/net/imx_fec: Convert debug fprintf() to trace events Date: Thu, 4 Jun 2020 14:39:08 +0200 Message-Id: <1db677b7d31ca3065f3987af7f2565eb57b29094.1591272275.git.jcd@tribudubois.net> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=217.70.183.196; envelope-from=jcd@tribudubois.net; helo=relay4-d.mail.gandi.net X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/04 08:39:21 X-ACL-Warn: Detected OS = Linux 3.11 and newer X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, f4bug@amsat.org, peter.chubb@nicta.com.au, qemu-devel@nongnu.org, Jean-Christophe Dubois Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Jean-Christophe Dubois Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Message-Id: <20200530102707.195131-1-jcd@tribudubois.net> [PMD: Fixed 32-bit format string using PRIx32/PRIx64] Signed-off-by: Philippe Mathieu-Daudé --- Based-on: <20200530102707.195131-1-jcd@tribudubois.net> --- v2: fix coding style issues. v3: improve tracing code based on feedback * change some tracing function names * remove unnecessary cast * add register index in addition to name v4: fix 32-bit format string using PRIx32/PRIx64 v5: Nothing hw/net/imx_fec.c | 106 +++++++++++++++++++------------------------- hw/net/trace-events | 18 ++++++++ 2 files changed, 63 insertions(+), 61 deletions(-) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index 7adcc9df654..eefedc252de 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -31,34 +31,11 @@ #include "qemu/module.h" #include "net/checksum.h" #include "net/eth.h" +#include "trace.h" /* For crc32 */ #include -#ifndef DEBUG_IMX_FEC -#define DEBUG_IMX_FEC 0 -#endif - -#define FEC_PRINTF(fmt, args...) \ - do { \ - if (DEBUG_IMX_FEC) { \ - fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_FEC, \ - __func__, ##args); \ - } \ - } while (0) - -#ifndef DEBUG_IMX_PHY -#define DEBUG_IMX_PHY 0 -#endif - -#define PHY_PRINTF(fmt, args...) \ - do { \ - if (DEBUG_IMX_PHY) { \ - fprintf(stderr, "[%s.phy]%s: " fmt , TYPE_IMX_FEC, \ - __func__, ##args); \ - } \ - } while (0) - #define IMX_MAX_DESC 1024 static const char *imx_default_reg_name(IMXFECState *s, uint32_t index) @@ -262,43 +239,45 @@ static void imx_eth_update(IMXFECState *s); * For now we don't handle any GPIO/interrupt line, so the OS will * have to poll for the PHY status. */ -static void phy_update_irq(IMXFECState *s) +static void imx_phy_update_irq(IMXFECState *s) { imx_eth_update(s); } -static void phy_update_link(IMXFECState *s) +static void imx_phy_update_link(IMXFECState *s) { /* Autonegotiation status mirrors link status. */ if (qemu_get_queue(s->nic)->link_down) { - PHY_PRINTF("link is down\n"); + trace_imx_phy_update_link("down"); s->phy_status &= ~0x0024; s->phy_int |= PHY_INT_DOWN; } else { - PHY_PRINTF("link is up\n"); + trace_imx_phy_update_link("up"); s->phy_status |= 0x0024; s->phy_int |= PHY_INT_ENERGYON; s->phy_int |= PHY_INT_AUTONEG_COMPLETE; } - phy_update_irq(s); + imx_phy_update_irq(s); } static void imx_eth_set_link(NetClientState *nc) { - phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc))); + imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc))); } -static void phy_reset(IMXFECState *s) +static void imx_phy_reset(IMXFECState *s) { + trace_imx_phy_reset(); + s->phy_status = 0x7809; s->phy_control = 0x3000; s->phy_advertise = 0x01e1; s->phy_int_mask = 0; s->phy_int = 0; - phy_update_link(s); + imx_phy_update_link(s); } -static uint32_t do_phy_read(IMXFECState *s, int reg) +static uint32_t imx_phy_read(IMXFECState *s, int reg) { uint32_t val; @@ -332,7 +311,7 @@ static uint32_t do_phy_read(IMXFECState *s, int reg) case 29: /* Interrupt source. */ val = s->phy_int; s->phy_int = 0; - phy_update_irq(s); + imx_phy_update_irq(s); break; case 30: /* Interrupt mask */ val = s->phy_int_mask; @@ -352,14 +331,14 @@ static uint32_t do_phy_read(IMXFECState *s, int reg) break; } - PHY_PRINTF("read 0x%04x @ %d\n", val, reg); + trace_imx_phy_read(val, reg); return val; } -static void do_phy_write(IMXFECState *s, int reg, uint32_t val) +static void imx_phy_write(IMXFECState *s, int reg, uint32_t val) { - PHY_PRINTF("write 0x%04x @ %d\n", val, reg); + trace_imx_phy_write(val, reg); if (reg > 31) { /* we only advertise one phy */ @@ -369,7 +348,7 @@ static void do_phy_write(IMXFECState *s, int reg, uint32_t val) switch (reg) { case 0: /* Basic Control */ if (val & 0x8000) { - phy_reset(s); + imx_phy_reset(s); } else { s->phy_control = val & 0x7980; /* Complete autonegotiation immediately. */ @@ -383,7 +362,7 @@ static void do_phy_write(IMXFECState *s, int reg, uint32_t val) break; case 30: /* Interrupt mask */ s->phy_int_mask = val & 0xff; - phy_update_irq(s); + imx_phy_update_irq(s); break; case 17: case 18: @@ -402,6 +381,8 @@ static void do_phy_write(IMXFECState *s, int reg, uint32_t val) static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr) { dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd)); + + trace_imx_fec_read_bd(addr, bd->flags, bd->length, bd->data); } static void imx_fec_write_bd(IMXFECBufDesc *bd, dma_addr_t addr) @@ -412,6 +393,9 @@ static void imx_fec_write_bd(IMXFECBufDesc *bd, dma_addr_t addr) static void imx_enet_read_bd(IMXENETBufDesc *bd, dma_addr_t addr) { dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd)); + + trace_imx_enet_read_bd(addr, bd->flags, bd->length, bd->data, + bd->option, bd->status); } static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr) @@ -471,11 +455,11 @@ static void imx_fec_do_tx(IMXFECState *s) int len; imx_fec_read_bd(&bd, addr); - FEC_PRINTF("tx_bd %x flags %04x len %d data %08x\n", - addr, bd.flags, bd.length, bd.data); if ((bd.flags & ENET_BD_R) == 0) { + /* Run out of descriptors to transmit. */ - FEC_PRINTF("tx_bd ran out of descriptors to transmit\n"); + trace_imx_eth_tx_bd_busy(); + break; } len = bd.length; @@ -552,11 +536,11 @@ static void imx_enet_do_tx(IMXFECState *s, uint32_t index) int len; imx_enet_read_bd(&bd, addr); - FEC_PRINTF("tx_bd %x flags %04x len %d data %08x option %04x " - "status %04x\n", addr, bd.flags, bd.length, bd.data, - bd.option, bd.status); if ((bd.flags & ENET_BD_R) == 0) { /* Run out of descriptors to transmit. */ + + trace_imx_eth_tx_bd_busy(); + break; } len = bd.length; @@ -633,7 +617,7 @@ static void imx_eth_enable_rx(IMXFECState *s, bool flush) s->regs[ENET_RDAR] = (bd.flags & ENET_BD_E) ? ENET_RDAR_RDAR : 0; if (!s->regs[ENET_RDAR]) { - FEC_PRINTF("RX buffer full\n"); + trace_imx_eth_rx_bd_full(); } else if (flush) { qemu_flush_queued_packets(qemu_get_queue(s->nic)); } @@ -676,7 +660,7 @@ static void imx_eth_reset(DeviceState *d) memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor)); /* We also reset the PHY */ - phy_reset(s); + imx_phy_reset(s); } static uint32_t imx_default_read(IMXFECState *s, uint32_t index) @@ -774,8 +758,7 @@ static uint64_t imx_eth_read(void *opaque, hwaddr offset, unsigned size) break; } - FEC_PRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_eth_reg_name(s, index), - value); + trace_imx_eth_read(index, imx_eth_reg_name(s, index), value); return value; } @@ -884,8 +867,7 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value, const bool single_tx_ring = !imx_eth_is_multi_tx_ring(s); uint32_t index = offset >> 2; - FEC_PRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_eth_reg_name(s, index), - (uint32_t)value); + trace_imx_eth_write(index, imx_eth_reg_name(s, index), value); switch (index) { case ENET_EIR: @@ -940,12 +922,12 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value, if (extract32(value, 29, 1)) { /* This is a read operation */ s->regs[ENET_MMFR] = deposit32(s->regs[ENET_MMFR], 0, 16, - do_phy_read(s, + imx_phy_read(s, extract32(value, 18, 10))); } else { /* This a write operation */ - do_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16)); + imx_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16)); } /* raise the interrupt as the PHY operation is done */ s->regs[ENET_EIR] |= ENET_INT_MII; @@ -1053,8 +1035,6 @@ static bool imx_eth_can_receive(NetClientState *nc) { IMXFECState *s = IMX_FEC(qemu_get_nic_opaque(nc)); - FEC_PRINTF("\n"); - return !!s->regs[ENET_RDAR]; } @@ -1071,7 +1051,7 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf, unsigned int buf_len; size_t size = len; - FEC_PRINTF("len %d\n", (int)size); + trace_imx_fec_receive(size); if (!s->regs[ENET_RDAR]) { qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Unexpected packet\n", @@ -1113,7 +1093,7 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf, bd.length = buf_len; size -= buf_len; - FEC_PRINTF("rx_bd 0x%x length %d\n", addr, bd.length); + trace_imx_fec_receive_len(addr, bd.length); /* The last 4 bytes are the CRC. */ if (size < 4) { @@ -1131,7 +1111,9 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf, if (size == 0) { /* Last buffer in frame. */ bd.flags |= flags | ENET_BD_L; - FEC_PRINTF("rx frame flags %04x\n", bd.flags); + + trace_imx_fec_receive_last(bd.flags); + s->regs[ENET_EIR] |= ENET_INT_RXF; } else { s->regs[ENET_EIR] |= ENET_INT_RXB; @@ -1164,7 +1146,7 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, size_t size = len; bool shift16 = s->regs[ENET_RACC] & ENET_RACC_SHIFT16; - FEC_PRINTF("len %d\n", (int)size); + trace_imx_enet_receive(size); if (!s->regs[ENET_RDAR]) { qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Unexpected packet\n", @@ -1210,7 +1192,7 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, bd.length = buf_len; size -= buf_len; - FEC_PRINTF("rx_bd 0x%x length %d\n", addr, bd.length); + trace_imx_enet_receive_len(addr, bd.length); /* The last 4 bytes are the CRC. */ if (size < 4) { @@ -1246,7 +1228,9 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, if (size == 0) { /* Last buffer in frame. */ bd.flags |= flags | ENET_BD_L; - FEC_PRINTF("rx frame flags %04x\n", bd.flags); + + trace_imx_enet_receive_last(bd.flags); + /* Indicate that we've updated the last buffer descriptor. */ bd.last_buffer = ENET_BD_BDU; if (bd.option & ENET_BD_RX_INT) { diff --git a/hw/net/trace-events b/hw/net/trace-events index e18f883cfd4..26700dad997 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -408,3 +408,21 @@ i82596_receive_packet(size_t sz) "len=%zu" i82596_new_mac(const char *id_with_mac) "New MAC for: %s" i82596_set_multicast(uint16_t count) "Added %d multicast entries" i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION" + +# imx_fec.c +imx_phy_read(uint32_t val, int reg) "0x%04"PRIx32" <= reg[%d]" +imx_phy_write(uint32_t val, int reg) "0x%04"PRIx32" => reg[%d]" +imx_phy_update_link(const char *s) "%s" +imx_phy_reset(void) "" +imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x" +imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x" +imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit" +imx_eth_rx_bd_full(void) "RX buffer is full" +imx_eth_read(int reg, const char *reg_name, uint32_t value) "reg[%d:%s] => 0x%08"PRIx32 +imx_eth_write(int reg, const char *reg_name, uint64_t value) "reg[%d:%s] <= 0x%08"PRIx64 +imx_fec_receive(size_t size) "len %zu" +imx_fec_receive_len(uint64_t addr, int len) "rx_bd 0x%"PRIx64" length %d" +imx_fec_receive_last(int last) "rx frame flags 0x%04x" +imx_enet_receive(size_t size) "len %zu" +imx_enet_receive_len(uint64_t addr, int len) "rx_bd 0x%"PRIx64" length %d" +imx_enet_receive_last(int last) "rx frame flags 0x%04x" From patchwork Thu Jun 4 12:39:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Christophe Dubois X-Patchwork-Id: 1303495 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=tribudubois.net Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49d55956Y1z9sSc for ; Thu, 4 Jun 2020 22:42:05 +1000 (AEST) Received: from localhost ([::1]:40462 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jgpC7-0002VE-DM for incoming@patchwork.ozlabs.org; Thu, 04 Jun 2020 08:42:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52998) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jgp9f-000824-Bo; Thu, 04 Jun 2020 08:39:31 -0400 Received: from relay4-d.mail.gandi.net ([217.70.183.196]:35391) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jgp9e-0001h4-FF; Thu, 04 Jun 2020 08:39:31 -0400 X-Originating-IP: 82.252.130.88 Received: from localhost.localdomain (lns-bzn-59-82-252-130-88.adsl.proxad.net [82.252.130.88]) (Authenticated sender: jcd@tribudubois.net) by relay4-d.mail.gandi.net (Postfix) with ESMTPSA id 2EE69E0005; Thu, 4 Jun 2020 12:39:26 +0000 (UTC) From: Jean-Christophe Dubois To: qemu-arm@nongnu.org Subject: [PATCH v5 2/3] hw/net/imx_fec: Allow phy not to be the first device on the mii bus. Date: Thu, 4 Jun 2020 14:39:09 +0200 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=217.70.183.196; envelope-from=jcd@tribudubois.net; helo=relay4-d.mail.gandi.net X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/04 08:39:21 X-ACL-Warn: Detected OS = Linux 3.11 and newer X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, f4bug@amsat.org, peter.chubb@nicta.com.au, qemu-devel@nongnu.org, Jean-Christophe Dubois Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Up to now we were allowing only one PHY device and it had to be the first device on the bus. The i.MX6UL has 2 Ethernet devices and can therefore have several PHY devices on the bus (and not necessarilly as device 0). This patch allows for PHY devices on 2nd, 3rd or any position. Signed-off-by: Jean-Christophe Dubois --- v2: Not present v3: Not present v4: Not present v5: Allow phy not to be the first device on the mii bus. hw/net/imx_fec.c | 19 ++++++++----------- hw/net/trace-events | 4 ++-- 2 files changed, 10 insertions(+), 13 deletions(-) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index eefedc252de..29e613699ee 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -280,11 +280,9 @@ static void imx_phy_reset(IMXFECState *s) static uint32_t imx_phy_read(IMXFECState *s, int reg) { uint32_t val; + uint32_t phy = reg / 32; - if (reg > 31) { - /* we only advertise one phy */ - return 0; - } + reg %= 32; switch (reg) { case 0: /* Basic Control */ @@ -331,19 +329,18 @@ static uint32_t imx_phy_read(IMXFECState *s, int reg) break; } - trace_imx_phy_read(val, reg); + trace_imx_phy_read(val, phy, reg); return val; } static void imx_phy_write(IMXFECState *s, int reg, uint32_t val) { - trace_imx_phy_write(val, reg); + uint32_t phy = reg / 32; - if (reg > 31) { - /* we only advertise one phy */ - return; - } + reg %= 32; + + trace_imx_phy_write(val, phy, reg); switch (reg) { case 0: /* Basic Control */ @@ -926,7 +923,7 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value, extract32(value, 18, 10))); } else { - /* This a write operation */ + /* This is a write operation */ imx_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16)); } /* raise the interrupt as the PHY operation is done */ diff --git a/hw/net/trace-events b/hw/net/trace-events index 26700dad997..27dfa0ef775 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -410,8 +410,8 @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries" i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION" # imx_fec.c -imx_phy_read(uint32_t val, int reg) "0x%04"PRIx32" <= reg[%d]" -imx_phy_write(uint32_t val, int reg) "0x%04"PRIx32" => reg[%d]" +imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]" +imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]" imx_phy_update_link(const char *s) "%s" imx_phy_reset(void) "" imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x" From patchwork Thu Jun 4 12:39:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Christophe Dubois X-Patchwork-Id: 1303497 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=tribudubois.net Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49d55z50t6z9sSc for ; Thu, 4 Jun 2020 22:42:47 +1000 (AEST) Received: from localhost ([::1]:42788 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jgpCn-0003Wv-FL for incoming@patchwork.ozlabs.org; Thu, 04 Jun 2020 08:42:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53004) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jgp9g-00085b-Qm; Thu, 04 Jun 2020 08:39:32 -0400 Received: from relay4-d.mail.gandi.net ([217.70.183.196]:55553) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jgp9f-0001i1-Lk; Thu, 04 Jun 2020 08:39:32 -0400 X-Originating-IP: 82.252.130.88 Received: from localhost.localdomain (lns-bzn-59-82-252-130-88.adsl.proxad.net [82.252.130.88]) (Authenticated sender: jcd@tribudubois.net) by relay4-d.mail.gandi.net (Postfix) with ESMTPSA id 4A988E0018; Thu, 4 Jun 2020 12:39:28 +0000 (UTC) From: Jean-Christophe Dubois To: qemu-arm@nongnu.org Subject: [PATCH v5 3/3] hw/net/imx_fec: improve PHY implementation. Date: Thu, 4 Jun 2020 14:39:10 +0200 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=217.70.183.196; envelope-from=jcd@tribudubois.net; helo=relay4-d.mail.gandi.net X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/04 08:39:21 X-ACL-Warn: Detected OS = Linux 3.11 and newer X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, f4bug@amsat.org, peter.chubb@nicta.com.au, qemu-devel@nongnu.org, Jean-Christophe Dubois Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" improve the PHY implementation with more generic code. This patch remove a lot of harcoded values to replace them with generic symbols from header files. Signed-off-by: Jean-Christophe Dubois --- v2: Not present v3: Not present v4: Not present v5: improve PHY implementation. hw/net/imx_fec.c | 76 +++++++++++++++++++++++++++----------------- include/hw/net/mii.h | 4 +++ 2 files changed, 50 insertions(+), 30 deletions(-) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index 29e613699ee..bf9583a93f4 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -24,6 +24,7 @@ #include "qemu/osdep.h" #include "hw/irq.h" #include "hw/net/imx_fec.h" +#include "hw/net/mii.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" #include "sysemu/dma.h" @@ -231,6 +232,9 @@ static const VMStateDescription vmstate_imx_eth = { #define PHY_INT_PARFAULT (1 << 2) #define PHY_INT_AUTONEG_PAGE (1 << 1) +#define MII_SMC911X_ISF 29 +#define MII_SMC911X_IM 30 + static void imx_eth_update(IMXFECState *s); /* @@ -249,11 +253,11 @@ static void imx_phy_update_link(IMXFECState *s) /* Autonegotiation status mirrors link status. */ if (qemu_get_queue(s->nic)->link_down) { trace_imx_phy_update_link("down"); - s->phy_status &= ~0x0024; + s->phy_status &= ~(MII_BMSR_LINK_ST | MII_BMSR_AN_COMP); s->phy_int |= PHY_INT_DOWN; } else { trace_imx_phy_update_link("up"); - s->phy_status |= 0x0024; + s->phy_status |= MII_BMSR_LINK_ST | MII_BMSR_AN_COMP; s->phy_int |= PHY_INT_ENERGYON; s->phy_int |= PHY_INT_AUTONEG_COMPLETE; } @@ -269,9 +273,11 @@ static void imx_phy_reset(IMXFECState *s) { trace_imx_phy_reset(); - s->phy_status = 0x7809; - s->phy_control = 0x3000; - s->phy_advertise = 0x01e1; + s->phy_status = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD | + MII_BMSR_10T_HD | MII_BMSR_AUTONEG | MII_BMSR_EXTCAP; + s->phy_control = MII_BMCR_AUTOEN | MII_BMCR_SPEED100; + s->phy_advertise = MII_ANAR_CSMACD | MII_ANAR_TX | MII_ANAR_10FD | + MII_ANAR_10 | MII_ANAR_TXFD; s->phy_int_mask = 0; s->phy_int = 0; imx_phy_update_link(s); @@ -285,37 +291,42 @@ static uint32_t imx_phy_read(IMXFECState *s, int reg) reg %= 32; switch (reg) { - case 0: /* Basic Control */ + case MII_BMCR: /* Basic Control */ val = s->phy_control; break; - case 1: /* Basic Status */ + case MII_BMSR: /* Basic Status */ val = s->phy_status; break; - case 2: /* ID1 */ - val = 0x0007; + case MII_PHYID1: /* ID1 */ + val = LAN911x_PHYID1; break; - case 3: /* ID2 */ - val = 0xc0d1; + case MII_PHYID2: /* ID2 */ + val = LAN911x_PHYID2; break; - case 4: /* Auto-neg advertisement */ + case MII_ANAR: /* Auto-neg advertisement */ val = s->phy_advertise; break; - case 5: /* Auto-neg Link Partner Ability */ - val = 0x0f71; + case MII_ANLPAR: /* Auto-neg Link Partner Ability */ + val = MII_ANLPAR_CSMACD | MII_ANLPAR_10 | MII_ANLPAR_10FD | + MII_ANLPAR_TX | MII_ANLPAR_TXFD | MII_ANLPAR_PAUSE | + MII_ANLPAR_PAUSEASY; break; - case 6: /* Auto-neg Expansion */ - val = 1; + case MII_ANER: /* Auto-neg Expansion */ + val = MII_ANER_NWAY; break; - case 29: /* Interrupt source. */ + case MII_SMC911X_ISF: /* Interrupt source. */ val = s->phy_int; s->phy_int = 0; imx_phy_update_irq(s); break; - case 30: /* Interrupt mask */ + case MII_SMC911X_IM: /* Interrupt mask */ val = s->phy_int_mask; break; - case 17: - case 18: + case MII_NSR: + val = 1 << 6; + break; + case MII_LBREMR: + case MII_REC: case 27: case 31: qemu_log_mask(LOG_UNIMP, "[%s.phy]%s: reg %d not implemented\n", @@ -343,26 +354,31 @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val) trace_imx_phy_write(val, phy, reg); switch (reg) { - case 0: /* Basic Control */ - if (val & 0x8000) { + case MII_BMCR: /* Basic Control */ + if (val & MII_BMCR_RESET) { imx_phy_reset(s); } else { - s->phy_control = val & 0x7980; + s->phy_control = val & (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 | + MII_BMCR_AUTOEN | MII_BMCR_PDOWN | + MII_BMCR_FD | MII_BMCR_CTST); /* Complete autonegotiation immediately. */ - if (val & 0x1000) { - s->phy_status |= 0x0020; + if (val & MII_BMCR_AUTOEN) { + s->phy_status |= MII_BMSR_AN_COMP; } } break; - case 4: /* Auto-neg advertisement */ - s->phy_advertise = (val & 0x2d7f) | 0x80; + case MII_ANAR: /* Auto-neg advertisement */ + s->phy_advertise = (val & (MII_ANAR_PAUSE_ASYM | MII_ANAR_PAUSE | + MII_ANAR_TXFD | MII_ANAR_TX | + MII_ANAR_10FD | MII_ANAR_10 | 0x1f)) | + MII_ANAR_TX; break; - case 30: /* Interrupt mask */ + case MII_SMC911X_IM: /* Interrupt mask */ s->phy_int_mask = val & 0xff; imx_phy_update_irq(s); break; - case 17: - case 18: + case MII_LBREMR: + case MII_REC: case 27: case 31: qemu_log_mask(LOG_UNIMP, "[%s.phy)%s: reg %d not implemented\n", diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h index 4ae4dcce7e3..d2001bd859b 100644 --- a/include/hw/net/mii.h +++ b/include/hw/net/mii.h @@ -112,4 +112,8 @@ #define DP83848_PHYID1 0x2000 #define DP83848_PHYID2 0x5c90 +/* SMSC LAN911x Internal PHY */ +#define LAN911x_PHYID1 0x0007 +#define LAN911x_PHYID2 0xc0d1 + #endif /* MII_H */