From patchwork Tue Dec 12 05:22:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 847329 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ywpBk4l9Dz9s7f for ; Tue, 12 Dec 2017 16:23:26 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3ywpBk3NrDzDrTp for ; Tue, 12 Dec 2017 16:23:26 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3ywpBd0wxszDrT9 for ; Tue, 12 Dec 2017 16:23:20 +1100 (AEDT) Received: from pasglop.ozlabs.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id vBC5Mw9g019898; Mon, 11 Dec 2017 23:23:00 -0600 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Tue, 12 Dec 2017 16:22:51 +1100 Message-Id: <20171212052255.17214-1-benh@kernel.crashing.org> X-Mailer: git-send-email 2.14.3 Subject: [Skiboot] [PATCH v2 1/5] xive: Mark a freed IRQ's IVE as valid and masked X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Removing the valid bit means a FIR will trip if it's accessed inadvertently. Under some circumstances, the XIVE will speculatively access an IVE for a masked interrupt and trip it. So make sure that freed entries are still marked valid (but masked). Signed-off-by: Benjamin Herrenschmidt Tested-by: Oliver O'Halloran --- hw/xive.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/xive.c b/hw/xive.c index e9aa030d..364be549 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -5116,7 +5116,7 @@ static int64_t opal_xive_free_irq(uint32_t girq) xive_update_irq_mask(s, girq - s->esb_base, true); /* Mark the IVE masked and invalid */ - ive->w = IVE_MASKED; + ive->w = IVE_MASKED | IVE_VALID; xive_ivc_scrub(x, x->block_id, idx); /* Free it */ From patchwork Tue Dec 12 05:22:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 847330 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ywpC42v10z9s7f for ; Tue, 12 Dec 2017 16:23:44 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3ywpC41cStzDrVw for ; Tue, 12 Dec 2017 16:23:44 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3ywpBd2wPrzDrTl for ; Tue, 12 Dec 2017 16:23:21 +1100 (AEDT) Received: from pasglop.ozlabs.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id vBC5Mw9h019898; Mon, 11 Dec 2017 23:23:01 -0600 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Tue, 12 Dec 2017 16:22:52 +1100 Message-Id: <20171212052255.17214-2-benh@kernel.crashing.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171212052255.17214-1-benh@kernel.crashing.org> References: <20171212052255.17214-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH v2 2/5] xive: Do not return a trigger page for an escalation interrupt X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This is bogus, we don't support them. (Thankfully the callers didn't actually try to use this on escalation interrupts). Signed-off-by: Benjamin Herrenschmidt Tested-by: Oliver O'Halloran --- hw/xive.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 364be549..76939b79 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -2111,8 +2111,8 @@ void *xive_get_trigger_port(uint32_t girq) return NULL; if (GIRQ_IS_ESCALATION(girq)) { - /* Page 2 of the EQ MMIO space is the escalate irq */ - return x->eq_mmio + idx * 0x20000 + 0x10000; + /* There is no trigger page for escalation interrupts */ + return NULL; } else { /* Make sure it's an IPI on that chip */ if (girq < x->int_base || From patchwork Tue Dec 12 05:22:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 847333 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ywpCq5H7fz9s7m for ; Tue, 12 Dec 2017 16:24:23 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3ywpCq4K55zDrTj for ; Tue, 12 Dec 2017 16:24:23 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3ywpBs6FjbzDrVf for ; Tue, 12 Dec 2017 16:23:33 +1100 (AEDT) Received: from pasglop.ozlabs.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id vBC5Mw9i019898; Mon, 11 Dec 2017 23:23:03 -0600 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Tue, 12 Dec 2017 16:22:53 +1100 Message-Id: <20171212052255.17214-3-benh@kernel.crashing.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171212052255.17214-1-benh@kernel.crashing.org> References: <20171212052255.17214-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH v2 3/5] io: Add load_wait() helper X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This uses the standard form twi/isync pair to ensure a load is consumed by the core before continuing. This can be necessary under some circumstances for example when having the following sequence: - Store reg A - Load reg A (ensure above store pushed out) - delay loop - Store reg A IE, a mandatory delay between 2 stores. In theory the first store is only guaranteed to rach the device after the load from the same location has completed. However the processor will start executing the delay loop without waiting for the return value from the load. This construct enforces that the delay loop isn't executed until the load value has been returned. Signed-off-by: Benjamin Herrenschmidt --- include/io.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/io.h b/include/io.h index 45a385ed..c056c37e 100644 --- a/include/io.h +++ b/include/io.h @@ -170,6 +170,14 @@ static inline void out_le64(volatile uint64_t *addr, uint64_t val) #define in_le8 in_8 #define out_le8 out_8 +/* Ensure completion of a load (ie, value returned to CPU) + * before continuing execution + */ +static inline void load_wait(uint64_t data) +{ + asm volatile("twi 0,%0,0;isync" : : "r" (data) : "memory"); +} + #endif /* __ASSEMBLY__ */ #endif /* __IO_H */ From patchwork Tue Dec 12 05:22:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 847331 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ywpCL1GZSz9s7m for ; Tue, 12 Dec 2017 16:23:58 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3ywpCL051rzDrV1 for ; Tue, 12 Dec 2017 16:23:58 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3ywpBg1KfBzDrT9 for ; Tue, 12 Dec 2017 16:23:22 +1100 (AEDT) Received: from pasglop.ozlabs.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id vBC5Mw9j019898; Mon, 11 Dec 2017 23:23:04 -0600 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Tue, 12 Dec 2017 16:22:54 +1100 Message-Id: <20171212052255.17214-4-benh@kernel.crashing.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171212052255.17214-1-benh@kernel.crashing.org> References: <20171212052255.17214-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH v2 4/5] xive: Fix occasional VC checkstops in xive_reset X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The current workaround for the scrub bug described in __xive_cache_scrub() has an issue in that it can leave dirty invalid entries in the cache. When cleaning up EQs or VPs during reset, if we then remove the underlying indirect page for these entries, the XIVE will checkstop when trying to flush them out of the cache. This replaces the existing workaround with a new pair of workarounds for VPs and EQs: - The VP one does the dummy watch on another entry than the one we scrubbed (which does the job of pushing old stores out) using an entry that is known to be backed by a permanent indirect page. - The EQ one switches to a more efficient workaround which consists of doing a non-side-effect ESB load from the EQ's ESe control bits. Signed-off-by: Benjamin Herrenschmidt --- v2. Fix typo and rename in_complete to load_wait --- hw/xive.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 54 insertions(+), 3 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 76939b79..bab4892f 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -1251,6 +1251,52 @@ static int64_t __xive_cache_watch(struct xive *x, enum xive_cache_type ctype, void *new_data, bool light_watch, bool synchronous); +static void xive_scrub_workaround_vp(struct xive *x, uint32_t block, uint32_t idx __unused) +{ + /* VP variant of the workaround described in __xive_cache_scrub(), + * we need to be careful to use for that workaround an NVT that + * sits on the same xive but isn NOT part of a donated indirect + * entry. + * + * The reason is that the dummy cache watch will re-create a + * dirty entry in the cache, even if the entry is marked + * invalid. + * + * Thus if we are about to dispose of the indirect entry backing + * it, we'll cause a checkstop later on when trying to write it + * out. + * + * Note: This means the workaround only works for block group + * mode. + */ +#ifdef USE_BLOCK_GROUP_MODE + __xive_cache_watch(x, xive_cache_vpc, block, INITIAL_VP_BASE, 0, + 0, NULL, true, false); +#else + /* WARNING: Some workarounds related to cache scrubs require us to + * have at least one firmware owned (permanent) indirect entry for + * each XIVE instance. This currently only happens in block group + * mode + */ +#warning Block group mode should not be disabled +#endif +} + +static void xive_scrub_workaround_eq(struct xive *x, uint32_t block __unused, uint32_t idx) +{ + void *mmio; + + /* EQ variant of the workaround described in __xive_cache_scrub(), + * a simple non-side effect load from ESn will do + */ + mmio = x->eq_mmio + idx * 0x20000; + + /* Ensure the above has returned before we do anything else + * the XIVE store queue is completely empty + */ + load_wait(in_be64(mmio + 0x800)); +} + static int64_t __xive_cache_scrub(struct xive *x, enum xive_cache_type ctype, uint64_t block, uint64_t idx, bool want_inval, bool want_disable) @@ -1270,6 +1316,9 @@ static int64_t __xive_cache_scrub(struct xive *x, enum xive_cache_type ctype, * invalidate, then after the scrub, we do a dummy cache * watch which will make the HW read the data back, which * should be ordered behind all the preceding stores. + * + * Update: For EQs we can do a non-side effect ESB load instead + * which is faster. */ want_inval = true; @@ -1331,9 +1380,11 @@ static int64_t __xive_cache_scrub(struct xive *x, enum xive_cache_type ctype, /* Workaround for HW bug described above (only applies to * EQC and VPC */ - if (ctype == xive_cache_eqc || ctype == xive_cache_vpc) - __xive_cache_watch(x, ctype, block, idx, 0, 0, NULL, - true, false); + if (ctype == xive_cache_eqc) + xive_scrub_workaround_eq(x, block, idx); + else if (ctype == xive_cache_vpc) + xive_scrub_workaround_vp(x, block, idx); + return 0; } From patchwork Tue Dec 12 05:22:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 847332 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ywpCb25TXz9s7m for ; Tue, 12 Dec 2017 16:24:11 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3ywpCb0p8bzDrVw for ; Tue, 12 Dec 2017 16:24:11 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3ywpBh36X2zDrT9 for ; Tue, 12 Dec 2017 16:23:24 +1100 (AEDT) Received: from pasglop.ozlabs.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id vBC5Mw9k019898; Mon, 11 Dec 2017 23:23:06 -0600 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Tue, 12 Dec 2017 16:22:55 +1100 Message-Id: <20171212052255.17214-5-benh@kernel.crashing.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171212052255.17214-1-benh@kernel.crashing.org> References: <20171212052255.17214-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH v2 5/5] xive: Ensure VC informational FIRs are masked X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Some HostBoot versions leave those as checkstop, they are harmless and can sometimes occur during normal operations. Signed-off-by: Benjamin Herrenschmidt Tested-by: Oliver O'Halloran Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Tested-by: Oliver O'Halloran <oohall@gmail.com>
--- hw/xive.c | 5 +++++ include/xive.h | 6 ++++++ 2 files changed, 11 insertions(+) diff --git a/hw/xive.c b/hw/xive.c index bab4892f..04dceda6 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -1780,6 +1780,11 @@ static bool xive_config_init(struct xive *x) val |= VC_EQC_CONF_ENABLE_END_u_BIT; xive_regw(x, VC_EQC_CONFIG, val); + /* Disable error reporting in the FIR for info errors + * from the VC. + */ + xive_regw(x, CQ_FIRMASK_OR, 3ull); + return true; } diff --git a/include/xive.h b/include/xive.h index 22e6a895..824ca0b8 100644 --- a/include/xive.h +++ b/include/xive.h @@ -70,6 +70,12 @@ #define CQ_AIB_CTL 0x110 #define X_CQ_RST_CTL 0x23 #define CQ_RST_CTL 0x118 +#define X_CQ_FIRMASK 0x33 +#define CQ_FIRMASK 0x198 +#define X_CQ_FIRMASK_AND 0x34 +#define CQ_FIRMASK_AND 0x1a0 +#define X_CQ_FIRMASK_OR 0x35 +#define CQ_FIRMASK_OR 0x1a8 /* PC LBS1 register offsets */ #define X_PC_TCTXT_CFG 0x100