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Tue, 26 May 2020 17:09:26 +0000 From: Sagar Shrikant Kadam To: u-boot@lists.denx.de, rick@andestech.com, lukma@denx.de Cc: jagan@amarulasolutions.com, bmeng.cn@gmail.com, pragnesh.patel@sifive.com, seanga2@gmail.com, Sagar Shrikant Kadam Subject: [PATCH v2 1/4] fu540: prci: add request and free clock handlers Date: Tue, 26 May 2020 10:09:08 -0700 Message-Id: <1590512951-1045-2-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1590512951-1045-1-git-send-email-sagar.kadam@sifive.com> References: <1590512951-1045-1-git-send-email-sagar.kadam@sifive.com> X-ClientProxiedBy: BYAPR01CA0054.prod.exchangelabs.com (2603:10b6:a03:94::31) To BN8PR13MB2611.namprd13.prod.outlook.com (2603:10b6:408:81::17) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from gamma07.internal.sifive.com (64.62.193.194) by BYAPR01CA0054.prod.exchangelabs.com (2603:10b6:a03:94::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3021.23 via Frontend Transport; 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Signed-off-by: Sagar Shrikant Kadam Reviewed-by: Pragnesh Patel --- drivers/clk/sifive/fu540-prci.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index 67e21b6..bf50ea2 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -581,6 +581,25 @@ static ulong sifive_fu540_prci_set_rate(struct clk *clk, ulong rate) return rate; } +static int sifive_fu540_prci_clk_request(struct clk *clk) +{ + debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, + clk->id); + + if (clk->id >= ARRAY_SIZE(__prci_init_clocks)) + return -EINVAL; + + return 0; +} + +static int sifive_fu540_prci_clk_free(struct clk *clk) +{ + debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, + clk->id); + + return 0; +} + static int sifive_fu540_prci_probe(struct udevice *dev) { int i, err; @@ -612,6 +631,8 @@ static int sifive_fu540_prci_probe(struct udevice *dev) static struct clk_ops sifive_fu540_prci_ops = { .set_rate = sifive_fu540_prci_set_rate, .get_rate = sifive_fu540_prci_get_rate, + .request = sifive_fu540_prci_clk_request, + .rfree = sifive_fu540_prci_clk_free, }; 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Tue, 26 May 2020 17:09:28 +0000 From: Sagar Shrikant Kadam To: u-boot@lists.denx.de, rick@andestech.com, lukma@denx.de Cc: jagan@amarulasolutions.com, bmeng.cn@gmail.com, pragnesh.patel@sifive.com, seanga2@gmail.com, Sagar Shrikant Kadam Subject: [PATCH v2 2/4] riscv: dts: hifive-unleashed-a00: add cpu aliases Date: Tue, 26 May 2020 10:09:09 -0700 Message-Id: <1590512951-1045-3-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1590512951-1045-1-git-send-email-sagar.kadam@sifive.com> References: <1590512951-1045-1-git-send-email-sagar.kadam@sifive.com> X-ClientProxiedBy: BYAPR01CA0054.prod.exchangelabs.com (2603:10b6:a03:94::31) To BN8PR13MB2611.namprd13.prod.outlook.com (2603:10b6:408:81::17) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from gamma07.internal.sifive.com (64.62.193.194) by BYAPR01CA0054.prod.exchangelabs.com (2603:10b6:a03:94::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3021.23 via Frontend Transport; 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Without aliases we see that the CPU device sequence numbers are set randomly and the cpu list/detail command will show it as follows: => cpu list 1: cpu@0 rv64imac 0: cpu@1 rv64imafdc 2: cpu@2 rv64imafdc 3: cpu@3 rv64imafdc 4: cpu@4 rv64imafdc Seems like CPU probing with dm-model also relies on aliases as observed in case spi. The fu540-c000-u-boot.dtsi has cpu0/1/2/3/4 nodes and so adding corresponding aliases we can ensure that cpu devices are assigned proper sequence as follows: => cpu list 0: cpu@0 rv64imac 1: cpu@1 rv64imafdc 2: cpu@2 rv64imafdc 3: cpu@3 rv64imafdc 4: cpu@4 rv64imafdc Signed-off-by: Sagar Shrikant Kadam Reviewed-by: Pragnesh Patel --- arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi index 9787332..9894260 100644 --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi @@ -7,6 +7,11 @@ / { aliases { + cpu0 = &cpu0; + cpu1 = &cpu1; + cpu2 = &cpu2; + cpu3 = &cpu3; + cpu4 = &cpu4; spi0 = &qspi0; spi2 = &qspi2; }; From patchwork Tue May 26 17:09:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sagar Shrikant Kadam X-Patchwork-Id: 1298224 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Tue, 26 May 2020 17:09:31 +0000 From: Sagar Shrikant Kadam To: u-boot@lists.denx.de, rick@andestech.com, lukma@denx.de Cc: jagan@amarulasolutions.com, bmeng.cn@gmail.com, pragnesh.patel@sifive.com, seanga2@gmail.com, Sagar Shrikant Kadam Subject: [PATCH v2 3/4] riscv: cpu: fixes to display proper CPU features Date: Tue, 26 May 2020 10:09:10 -0700 Message-Id: <1590512951-1045-4-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1590512951-1045-1-git-send-email-sagar.kadam@sifive.com> References: <1590512951-1045-1-git-send-email-sagar.kadam@sifive.com> X-ClientProxiedBy: BYAPR01CA0054.prod.exchangelabs.com (2603:10b6:a03:94::31) To BN8PR13MB2611.namprd13.prod.outlook.com (2603:10b6:408:81::17) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from gamma07.internal.sifive.com (64.62.193.194) by BYAPR01CA0054.prod.exchangelabs.com (2603:10b6:a03:94::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3021.23 via Frontend Transport; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: zNIUIXkRpAO6GC++yd0EuRuR1FX/ahY8rnTS4arswiuE8yhr0nmxq0gePFNTD/1/vzwW/krl+JXPjp4Qdgttn3n2Vk50oATbFdgjDJOg+mnPn55uo8xqSHzVAYP9vJNrtO4H47Br//fVtB6MWxMvKYurxH2cvOi+Rl5/7st4SqVP+EH4zAYqwMv8/GAfjh5Q8IV6PFkJUOi2Yg5k1S1Mgxb6MyExF7dQhrlM9ounYvT2BZJImASijGFePSN5IFLjZ0+1V5L+i5UE5ZoeozpQWAQvYw6Uc+YzUGOUgFeCnu7AgiQJ/g3GmLPl9eT8P+aXlv4JFx5TDt3QRgQOhtj2DmthuBRryPlU1bgdv4vmru08Edk5XjvmxFhbgdcTvGuSNPbg2oxUCZU+TscjJmMIhWAAa8Mq5+i5LdtLFuvCcHd2204durWYdcOnC7NmcvhxJJ3J/X1WFb7XGXxakRbqnqNVKxMh6FQ7rPvElcja/2s= X-OriginatorOrg: sifive.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4e07d711-9f15-4116-f02d-08d801978e15 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 May 2020 17:09:31.1585 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 22f88e9d-ae0d-4ed9-b984-cdc9be1529f1 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: BRsEqji0NZAs3LS2a5Xmkg5mXSbSSYLodNGNVtpdKqnnemHwlvV7UvscvkGX/NoXfNmdprENrkE4UZAvZQHpng== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR13MB2897 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean The cmd "cpu detail" fetches uninitialized cpu feature information and thus displays wrong / inconsitent details as below. FU540-C000 doesn't have any microcode, yet the cmd display's it. => cpu detail 0: cpu@0 rv64imac ID = 0, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID Microcode version 0x0 Device ID 0x0 1: cpu@1 rv64imafdc ID = 1, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID Microcode version 0x0 Device ID 0x0 2: cpu@2 rv64imafdc ID = 2, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID Microcode version 0x0 Device ID 0x0 3: cpu@3 rv64imafdc ID = 3, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID Microcode version 0x0 Device ID 0x0 4: cpu@4 rv64imafdc ID = 4, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID Microcode version 0x0 Device ID 0x0 The L1 cache or MMU entry seen above is also displayed inconsistently. So initialize features to zero before fetching from device tree. Additionally the conditional check to read "mmu-type" from device tree is not rightly handled due to which the cpu feature doesn't include CPU_FEAT_MMU even if it's corresponding entry is present in device tree. We now see correct features as: => cpu detail 0: cpu@0 rv64imac ID = 0, freq = 999.100 MHz 1: cpu@1 rv64imafdc ID = 1, freq = 999.100 MHz: MMU 2: cpu@2 rv64imafdc ID = 2, freq = 999.100 MHz: MMU 3: cpu@3 rv64imafdc ID = 3, freq = 999.100 MHz: MMU 4: cpu@4 rv64imafdc ID = 4, freq = 999.100 MHz: MMU Signed-off-by: Sagar Shrikant Kadam Reviewed-by: Pragnesh Patel --- drivers/cpu/riscv_cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index 76b0489..8c4b5e7 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -38,6 +38,8 @@ static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info) /* Zero out the frequency, in case sizeof(ulong) != sizeof(u32) */ info->cpu_freq = 0; + /* Initialise cpu features before updating from device tree */ + info->features = 0; /* First try getting the frequency from the assigned clock */ ret = clk_get_by_index(dev, 0, &clk); @@ -52,7 +54,7 @@ static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info) dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq); 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Tue, 26 May 2020 17:09:34 +0000 From: Sagar Shrikant Kadam To: u-boot@lists.denx.de, rick@andestech.com, lukma@denx.de Cc: jagan@amarulasolutions.com, bmeng.cn@gmail.com, pragnesh.patel@sifive.com, seanga2@gmail.com, Sagar Shrikant Kadam Subject: [PATCH v2 4/4] riscv: cpu: check and append L1 cache to cpu features Date: Tue, 26 May 2020 10:09:11 -0700 Message-Id: <1590512951-1045-5-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1590512951-1045-1-git-send-email-sagar.kadam@sifive.com> References: <1590512951-1045-1-git-send-email-sagar.kadam@sifive.com> X-ClientProxiedBy: BYAPR01CA0054.prod.exchangelabs.com (2603:10b6:a03:94::31) To BN8PR13MB2611.namprd13.prod.outlook.com (2603:10b6:408:81::17) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from gamma07.internal.sifive.com (64.62.193.194) by BYAPR01CA0054.prod.exchangelabs.com (2603:10b6:a03:94::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3021.23 via Frontend Transport; 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Set the L1 feature bit using the i-cache-size as one of the property from device tree indicating that L1 cache is present on the cpu core. => cpu detail 0: cpu@0 rv64imac ID = 0, freq = 999.100 MHz: L1 cache 1: cpu@1 rv64imafdc ID = 1, freq = 999.100 MHz: L1 cache, MMU 2: cpu@2 rv64imafdc ID = 2, freq = 999.100 MHz: L1 cache, MMU 3: cpu@3 rv64imafdc ID = 3, freq = 999.100 MHz: L1 cache, MMU 4: cpu@4 rv64imafdc ID = 4, freq = 999.100 MHz: L1 cache, MMU Signed-off-by: Sagar Shrikant Kadam Reviewed-by: Pragnesh Patel --- drivers/cpu/riscv_cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index 8c4b5e7..ce722cb 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -35,6 +35,7 @@ static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info) int ret; struct clk clk; const char *mmu; + u32 split_cache_size; /* Zero out the frequency, in case sizeof(ulong) != sizeof(u32) */ info->cpu_freq = 0; @@ -57,6 +58,11 @@ static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info) if (mmu) info->features |= BIT(CPU_FEAT_MMU); + /* check if I/D cache is present */ + ret = dev_read_u32(dev, "i-cache-size", &split_cache_size); + if (!ret) + info->features |= BIT(CPU_FEAT_L1_CACHE); + return 0; }