From patchwork Mon Dec 11 18:50:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 847171 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="MLxC6ESE"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ywX8q1GgVz9sNx for ; Tue, 12 Dec 2017 05:50:51 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752316AbdLKSuq (ORCPT ); Mon, 11 Dec 2017 13:50:46 -0500 Received: from mail-lf0-f68.google.com ([209.85.215.68]:34526 "EHLO mail-lf0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752621AbdLKSui (ORCPT ); Mon, 11 Dec 2017 13:50:38 -0500 Received: by mail-lf0-f68.google.com with SMTP id x20so20399880lff.1; Mon, 11 Dec 2017 10:50:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FywjnSL1tS9QHtYacjY7XuSgaczoFxYdwQbx2I/oRDo=; b=MLxC6ESEp4elWcibcAlrItMGkiXIuiZT4vnGwoku96pGFOUa7hso2+fMbJmpzYgVuj 3IlkEQTTzObyEIglbRjWyIP0UZiK6e3G/bHtyIFnSzTuQnNQV9q6eiOI4KNsY18bhfdE ZM4tOZ6cRsUBX4Rusi3PMlYdVhqK911VOdzLY/EaZIJRMvdili5YTXuKzsvRy7xWAvxL 2dwEkBsnIrlbZT8ecbQuwwUtjD8J7gcqIkVg6HR+TTddE1oIrm7r/kAjmytuSTbLKsO9 2UbUM5FVQOIUFZ2nm4NmAJ7I0qlXiZ0aJBG+EjsJHgdhM9KunyxhxBiEjCLp6GTlxVoM dT3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FywjnSL1tS9QHtYacjY7XuSgaczoFxYdwQbx2I/oRDo=; b=H+i2vrjQHmS2pd7HtAkEwWX54Woev4RFsNGhYIQOCf8uP4JETesYjSTkCDpdwYsMei 7qTNj2qjaiO+SS0QUJSGmqIc21LSHCZ5KoM1Jek+uh+fe6pPkzC9IMQh0zMU+nBDDDE7 gzjlX4MMWuK/PtcHOVkYJ23J+NdrgdIsoYVCEMgMZE5/V6/tFfIP0rysWnFrh32YIgyP 7eipGUuJubtNrVtp42D+PNJnx24Bd3Ay0laHIXUqDEjzNNBxtLbvjyifgBv5M/3n68aw 9UXvNvpX7TK7+RCpFEzz4ozS3z58jRWjMA5JlKxyZvZx54cJTxa0ohGmXokCxtd7/sZE 4xXQ== X-Gm-Message-State: AKGB3mKyQpPhVxeytpCGYc/5Bg0lDVDFxxjQHs+0L9/EM01u14ivtNPo FcNLW4QF7NgyzwTJdsWNs0c= X-Google-Smtp-Source: ACJfBouRSVMlEUFk+TInO+IWiGdP7O59jdu54nXRcnNhlIIWHo9A9nX0jvMKmSOdyiZT18fqkLg8GA== X-Received: by 10.46.18.216 with SMTP id 85mr693927ljs.100.1513018236506; Mon, 11 Dec 2017 10:50:36 -0800 (PST) Received: from localhost.localdomain (ppp109-252-55-194.pppoe.spdop.ru. [109.252.55.194]) by smtp.gmail.com with ESMTPSA id 71sm2930678ljr.68.2017.12.11.10.50.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Dec 2017 10:50:35 -0800 (PST) From: Dmitry Osipenko To: Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Thierry Reding , Jonathan Hunter Cc: linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1] clk: tegra: Specify VDE clock rate Date: Mon, 11 Dec 2017 21:50:11 +0300 Message-Id: <41813e7cda9ade75637d6c25b0a1b004462058f4.1513018131.git.digetx@gmail.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: References: Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Currently VDE clock rate is determined by clock config left from bootloader, let's not rely on it and explicitly specify the clock rate in the CCF driver. Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver --- drivers/clk/tegra/clk-tegra114.c | 1 + drivers/clk/tegra/clk-tegra124.c | 2 +- drivers/clk/tegra/clk-tegra20.c | 1 + drivers/clk/tegra/clk-tegra30.c | 1 + 4 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index f39e09d1bdba..3523852accd8 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -1189,6 +1189,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0 }, { TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 }, { TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 }, + { TEGRA114_CLK_VDE, TEGRA114_CLK_CLK_MAX, 600000000, 0 }, /* must be the last entry */ { TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 }, }; diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index c802fbcbc5fa..dda7c2163521 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -1268,7 +1268,7 @@ static struct tegra_clk_init_table common_init_table[] __initdata = { { TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 }, { TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 }, { TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 }, - { TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0 }, + { TEGRA124_CLK_VDE, TEGRA124_CLK_CLK_MAX, 600000000, 0 }, { TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1 }, { TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0 }, { TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0 }, diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index c39e7e2446d8..66d9a2c91b9c 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1056,6 +1056,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0 }, { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 }, { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 }, + { TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 300000000, 0 }, /* must be the last entry */ { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 }, }; diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 54d2c3436a31..aa47617850a6 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1269,6 +1269,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 }, + { TEGRA30_CLK_VDE, TEGRA30_CLK_CLK_MAX, 600000000, 0 }, /* must be the last entry */ { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 }, };