From patchwork Tue May 26 05:06:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandipan Patra X-Patchwork-Id: 1297684 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=QJTlDTnc; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49WMPQ0DnFz9sRK for ; Tue, 26 May 2020 15:06:18 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726049AbgEZFGN (ORCPT ); Tue, 26 May 2020 01:06:13 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:10483 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725872AbgEZFGN (ORCPT ); Tue, 26 May 2020 01:06:13 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 25 May 2020 22:04:44 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 25 May 2020 22:06:12 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 25 May 2020 22:06:12 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 26 May 2020 05:06:12 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 26 May 2020 05:06:12 +0000 Received: from sandipan-pc.nvidia.com (Not Verified[10.24.42.163]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 25 May 2020 22:06:11 -0700 From: Sandipan Patra To: , , , , , , CC: , , , , , , , Sandipan Patra Subject: [PATCH 1/2] hwmon: pwm-fan: Add profile support and add remove module support Date: Tue, 26 May 2020 10:36:04 +0530 Message-ID: <1590469565-14953-1-git-send-email-spatra@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1590469484; bh=YNG08g8NnR/+zB8mCjRyNEMkFDmY+YHQZPfszu7vlRU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=QJTlDTnceYS2J34I7iRMFfYK2CYe10VK6NMuTxJQZBoooYRyUKE12HKCU2sswxDCQ ifEpevlvL3eBaDVkiWbDEUE8LpyiINY4oX9JpJTnW/TIgdGR1TyA4cXnM0JU7p/1Tp Y2nYyLiEQ7GeGuoQ/YWP9T27luL6BB1xqiW5Ag0fgLj5VYwW1xnylRdhX1AIbzJt64 7bQiubyFZ0+GW4TtA+fMoLSMqbjirsBlRYwh6FzExvVgenMo1IxalBu7e9uK6NQus6 BqBL5dbWm2JenHevUxYitomVWMRuNnybwweUJRt+bmQk3x7NPOs6wCZ0hlD35GQGyw Beo3fsxLdc/ew== Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This change has 2 parts: 1. Add support for profiles mode settings. This allows different fan settings for trip point temp/hyst/pwm. T194 has multiple fan-profiles support. 2. Add pwm-fan remove support. This is essential since the config is tristate capable. Signed-off-by: Sandipan Patra --- drivers/hwmon/pwm-fan.c | 112 ++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 100 insertions(+), 12 deletions(-) diff --git a/drivers/hwmon/pwm-fan.c b/drivers/hwmon/pwm-fan.c index 30b7b3e..26db589 100644 --- a/drivers/hwmon/pwm-fan.c +++ b/drivers/hwmon/pwm-fan.c @@ -3,8 +3,10 @@ * pwm-fan.c - Hwmon driver for fans connected to PWM lines. * * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * Copyright (c) 2020, NVIDIA Corporation. * * Author: Kamil Debski + * Author: Sandipan Patra */ #include @@ -21,6 +23,8 @@ #include #define MAX_PWM 255 +/* Based on OF max device tree node name length */ +#define MAX_PROFILE_NAME_LENGTH 31 struct pwm_fan_ctx { struct mutex lock; @@ -38,6 +42,12 @@ struct pwm_fan_ctx { unsigned int pwm_fan_state; unsigned int pwm_fan_max_state; unsigned int *pwm_fan_cooling_levels; + + unsigned int pwm_fan_profiles; + const char **fan_profile_names; + unsigned int **fan_profile_cooling_levels; + unsigned int fan_current_profile; + struct thermal_cooling_device *cdev; }; @@ -227,28 +237,86 @@ static int pwm_fan_of_get_cooling_data(struct device *dev, struct pwm_fan_ctx *ctx) { struct device_node *np = dev->of_node; + struct device_node *base_profile = NULL; + struct device_node *profile_np = NULL; + const char *default_profile = NULL; int num, i, ret; - if (!of_find_property(np, "cooling-levels", NULL)) - return 0; + num = of_property_count_u32_elems(np, "cooling-levels"); + if (num <= 0) { + base_profile = of_get_child_by_name(np, "profiles"); + if (!base_profile) { + dev_err(dev, "Wrong Data\n"); + return -EINVAL; + } + } + + if (base_profile) { + ctx->pwm_fan_profiles = + of_get_available_child_count(base_profile); + + if (ctx->pwm_fan_profiles <= 0) { + dev_err(dev, "Profiles used but not defined\n"); + return -EINVAL; + } - ret = of_property_count_u32_elems(np, "cooling-levels"); - if (ret <= 0) { - dev_err(dev, "Wrong data!\n"); - return ret ? : -EINVAL; + ctx->fan_profile_names = devm_kzalloc(dev, + sizeof(const char *) * ctx->pwm_fan_profiles, + GFP_KERNEL); + ctx->fan_profile_cooling_levels = devm_kzalloc(dev, + sizeof(int *) * ctx->pwm_fan_profiles, + GFP_KERNEL); + + if (!ctx->fan_profile_names + || !ctx->fan_profile_cooling_levels) + return -ENOMEM; + + ctx->fan_current_profile = 0; + i = 0; + for_each_available_child_of_node(base_profile, profile_np) { + num = of_property_count_u32_elems(profile_np, + "cooling-levels"); + if (num <= 0) { + dev_err(dev, "No data in cooling-levels inside profile node!\n"); + return -EINVAL; + } + + of_property_read_string(profile_np, "name", + &ctx->fan_profile_names[i]); + if (default_profile && + !strncmp(default_profile, + ctx->fan_profile_names[i], + MAX_PROFILE_NAME_LENGTH)) + ctx->fan_current_profile = i; + + ctx->fan_profile_cooling_levels[i] = + devm_kzalloc(dev, sizeof(int) * num, + GFP_KERNEL); + if (!ctx->fan_profile_cooling_levels[i]) + return -ENOMEM; + + of_property_read_u32_array(profile_np, "cooling-levels", + ctx->fan_profile_cooling_levels[i], num); + i++; + } } - num = ret; ctx->pwm_fan_cooling_levels = devm_kcalloc(dev, num, sizeof(u32), GFP_KERNEL); if (!ctx->pwm_fan_cooling_levels) return -ENOMEM; - ret = of_property_read_u32_array(np, "cooling-levels", - ctx->pwm_fan_cooling_levels, num); - if (ret) { - dev_err(dev, "Property 'cooling-levels' cannot be read!\n"); - return ret; + if (base_profile) { + memcpy(ctx->pwm_fan_cooling_levels, + ctx->fan_profile_cooling_levels[ctx->fan_current_profile], + num); + } else { + ret = of_property_read_u32_array(np, "cooling-levels", + ctx->pwm_fan_cooling_levels, num); + if (ret) { + dev_err(dev, "Property 'cooling-levels' cannot be read!\n"); + return -EINVAL; + } } for (i = 0; i < num; i++) { @@ -390,6 +458,25 @@ static int pwm_fan_probe(struct platform_device *pdev) return 0; } +static int pwm_fan_remove(struct platform_device *pdev) +{ + struct pwm_fan_ctx *ctx = platform_get_drvdata(pdev); + struct pwm_args args; + + if (!ctx) + return -EINVAL; + + if (IS_ENABLED(CONFIG_THERMAL)) + thermal_cooling_device_unregister(ctx->cdev); + + pwm_get_args(ctx->pwm, &args); + pwm_config(ctx->pwm, 0, args.period); + pwm_disable(ctx->pwm); + + return 0; +} + + static int pwm_fan_disable(struct device *dev) { struct pwm_fan_ctx *ctx = dev_get_drvdata(dev); @@ -465,6 +552,7 @@ MODULE_DEVICE_TABLE(of, of_pwm_fan_match); static struct platform_driver pwm_fan_driver = { .probe = pwm_fan_probe, + .remove = pwm_fan_remove, .shutdown = pwm_fan_shutdown, .driver = { .name = "pwm-fan", From patchwork Tue May 26 05:06:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandipan Patra X-Patchwork-Id: 1297687 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=o4Vu2bQN; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49WMPR4kL0z9sSt for ; Tue, 26 May 2020 15:06:19 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726690AbgEZFGS (ORCPT ); Tue, 26 May 2020 01:06:18 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:1452 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726181AbgEZFGS (ORCPT ); Tue, 26 May 2020 01:06:18 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 25 May 2020 22:04:55 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 25 May 2020 22:06:17 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 25 May 2020 22:06:17 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 26 May 2020 05:06:17 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 26 May 2020 05:06:17 +0000 Received: from sandipan-pc.nvidia.com (Not Verified[10.24.42.163]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 25 May 2020 22:06:16 -0700 From: Sandipan Patra To: , , , , , , CC: , , , , , , , Sandipan Patra Subject: [PATCH 2/2] arm64: tegra: Add pwm-fan profile settings Date: Tue, 26 May 2020 10:36:05 +0530 Message-ID: <1590469565-14953-2-git-send-email-spatra@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1590469565-14953-1-git-send-email-spatra@nvidia.com> References: <1590469565-14953-1-git-send-email-spatra@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1590469495; bh=XQiGWOGFzg3l+QIfS45QIJAE9J403LC3AAuTqpFbPj4=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=o4Vu2bQNYOmORHo3E4N3VM2YnDjSdCgPiPw+JT6WKKvUWogGR9uX/a4JK4FFCginm 6CWpkHmRz4bGTKPJNCOZrwuGReH9xMH0lXc0U+Mn2G5rZ7OB3Sx2N3ZCNb9BxhFGvR c5pCdGGcvjVG6YSyWjtNtCz1LC02QTOSrq14lBSfU3vAv0eSOkJb6hh4zLYXompGPO WulcGOZdMuNW3TO0iELI3PdMgAYaCeu24gSqShSewxs445f5ONx7NWrgioGwMdV+8H vlsDE6RVrgdofNftW6VDCP0WXXXm2gHRUdxVFag8QNf2O+2mabB+H6f7zXfQGO+QIH 3JJ/0i9Zog9AQ== Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Add support for profiles in device tree to allow different fan settings for trip point temp/hyst/pwm. Signed-off-by: Sandipan Patra --- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index e15d1ea..ff2b980 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -219,10 +219,19 @@ fan: fan { compatible = "pwm-fan"; - pwms = <&pwm4 0 45334>; - - cooling-levels = <0 64 128 255>; #cooling-cells = <2>; + pwms = <&pwm4 0 45334>; + profiles { + default = "quiet"; + quiet { + state_cap = <4>; + cooling-levels = <0 77 120 160 255 255 255 255 255 255>; + }; + cool { + state_cap = <4>; + cooling-levels = <0 77 120 160 255 255 255 255 255 255>; + }; + }; }; gpio-keys {